Rizin
unix-like reverse engineering framework and cli tools
Classes | Macros | Typedefs | Functions | Variables
sh_il.c File Reference
#include "sh_il.h"
#include <rz_il/rz_il_opbuilder_begin.h>
#include "../../../asm/arch/sh/regs.h"
#include <rz_il/rz_il_opbuilder_end.h>

Go to the source code of this file.

Classes

struct  sh_param_helper_t
 Helper struct to take care of converting operands to IL. More...
 

Macros

#define SH_U_ADDR(x)   UN(SH_ADDR_SIZE, x)
 
#define SH_S_ADDR(x)   SN(SH_ADDR_SIZE, x)
 
#define SH_U_REG(x)   UN(SH_REG_SIZE, (x))
 
#define SH_S_REG(x)   SN(SH_REG_SIZE, (x))
 
#define SH_BIT(x)   UN(1, x)
 
#define SH_TRUE   SH_U_REG(1)
 
#define SH_FALSE   SH_U_REG(0)
 
#define sh_il_get_pure_param(x)    sh_il_get_param(op->param[x], op->scaling).pure
 
#define sh_il_set_pure_param(x, val)    sh_il_set_param(op->param[x], val, op->scaling)
 
#define sh_il_get_effective_addr_param(x)    sh_il_get_effective_addr(op->param[x], op->scaling)
 
#define sh_il_get_privilege()   sh_il_get_privilege_ctx(ctx)
 
#define sh_il_get_reg(reg)   sh_il_get_reg_ctx(reg, ctx)
 
#define sh_il_set_reg(reg, val)   sh_il_set_reg_ctx(reg, val, ctx)
 
#define sh_il_get_effective_addr(x, y)   sh_il_get_effective_addr_pc_ctx(x, y, pc, ctx)
 
#define sh_il_get_param(x, y)   sh_il_get_param_pc_ctx(x, y, pc, ctx)
 
#define sh_il_set_param(x, y, z)   sh_il_set_param_pc_ctx(x, y, z, pc, ctx)
 

Typedefs

typedef struct sh_param_helper_t SHParamHelper
 Helper struct to take care of converting operands to IL. More...
 
typedef RzILOpEffect *(* sh_il_op) (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 

Functions

static bool sh_valid_gpr (ut16 reg)
 
static bool sh_banked_reg (ut16 reg)
 
RzILOpEffect * sh_il_signed (unsigned int len, RZ_OWN RzILOpPure *val, const char *cast_var, const char *temp_var)
 Cast val to len bits This uses a local temp variable temp_var to store the value val and then casts the local variable temp_var to its signed value and stores that value in the local variable cast_var. More...
 
static const char * sh_get_banked_reg (ut16 reg, ut8 bank)
 Get the register name for reg in bank bank. More...
 
static RzILOpBitVector * sh_il_bool_to_bv (RzILOpBool *b)
 Convert b to SH_TRUE or SH_FALSE (bool zero-extended to SH_REG_SIZE) More...
 
static RzILOpBitVector * sh_il_get_status_reg_bit (const char *bit)
 We need this because sometimes we would want an RzILOpBitvector back when we ask for a status reg bit, so this returns us an RzILOpBitvector instead of the RzILOpBool returned when using VARG More...
 
static RzILOpPure * sh_il_get_status_reg ()
 Return the status register (sr), calculated by shifting all the status register bits at the correct offsets. More...
 
static RzILOpEffect * sh_il_set_status_reg (RZ_OWN RzILOpPure *val)
 Set the value of the status register (sr) to val by setting the values of the individual status register bits. More...
 
static RzILOpEffect * sh_il_initialize_privilege ()
 Set the value of the local variable "_priv" This exists so that the privilege mode IL doesn't have to be duplicated everywhere, instead one can directly use the local variable. More...
 
static RzILOpPure * sh_il_get_privilege_ctx (SHILContext *ctx)
 Get the privilege mode Do NOT call this before initializing privilege through sh_il_initialize_privilege Otherwise, the local variable would not have been initialized For all the liftings, this is taken care of in rz_sh_il_opcode More...
 
static RzILOpPure * sh_il_get_reg_ctx (ut16 reg, SHILContext *ctx)
 Get register corresponding to reg index This function is smart enough to give the correct register in case of banked registers or status register. More...
 
static RzILOpEffect * sh_il_set_reg_ctx (ut16 reg, RZ_OWN RzILOpPure *val, SHILContext *ctx)
 Set the value of the register corresponding to index reg to value val This function is smart enough to set values correctly in case of banked registers or status register. More...
 
st16 convert_to_st12 (ut16 num)
 Convert an unsigned 12 bit num to signed 12 bit num I have used 16 bits to represent the numbers involved here, but the 4 most significant bits are the same, so for all purposes these are basically 12 bit numbers extended to 16 bits. More...
 
static RzILOpPure * sh_il_get_effective_addr_pc_ctx (SHParam param, SHScaling scaling, ut64 pc, SHILContext *ctx)
 Get the effective address obtained from the given param and scaling. More...
 
static SHParamHelper sh_il_get_param_pc_ctx (SHParam param, SHScaling scaling, ut64 pc, SHILContext *ctx)
 Convert the param with scaling to it's IL representation. More...
 
static RzILOpEffect * sh_apply_effects (RZ_NULLABLE RzILOpEffect *target, RZ_NULLABLE RzILOpEffect *pre, RZ_NULLABLE RzILOpEffect *post)
 Apply the effects in order: pre, target, post The good thing about this function is that any of the arguments can be NULL which implies that they do not exist/matter, and the final effect woulds be calculated without these NULL arguments (keeping in mind the above order) More...
 
static RzILOpEffect * sh_il_set_param_pc_ctx (SHParam param, RZ_OWN RzILOpPure *val, SHScaling scaling, ut64 pc, SHILContext *ctx)
 Set the value of the param at scaling to val This function is smart enough to also apply any effects corresponding to the param. More...
 
static RzILOpBool * sh_il_is_add_carry (RZ_OWN RzILOpPure *res, RZ_OWN RzILOpPure *x, RZ_OWN RzILOpPure *y)
 Check if there was a carry in the addition of x and y to get res Here res = x + y (+ 1, optional) This function can also be used of there was a carry bit added as well. More...
 
static RzILOpBool * sh_il_is_sub_borrow (RZ_OWN RzILOpPure *res, RZ_OWN RzILOpPure *x, RZ_OWN RzILOpPure *y)
 Check if there was a borrow in the subtraction of x and y to get res Here res = x - y (- 1, optional) This function can also be used of there was a borrow bit added as well. More...
 
static RzILOpBool * sh_il_is_add_overflow (RZ_OWN RzILOpPure *res, RZ_OWN RzILOpPure *x, RZ_OWN RzILOpPure *y)
 Check if there was a overflow in the addition of x and y to get res Here res = x + y. More...
 
static RzILOpBool * sh_il_is_sub_underflow (RZ_OWN RzILOpPure *res, RZ_OWN RzILOpPure *x, RZ_OWN RzILOpPure *y)
 Check if there was a underflow in the subtraction of x and y to get res Here res = x - y. More...
 
static RzILOpEffect * sh_il_invalid (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_mov (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_movt (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_swap (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_xtrct (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_add (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_addc (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_addv (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_cmp_eq (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_cmp_hs (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_cmp_ge (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_cmp_hi (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_cmp_gt (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_cmp_pz (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_cmp_pl (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_cmp_str (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_div1 (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_div0s (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_div0u (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_dmuls (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_dmulu (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_dt (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_exts (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_extu (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_mac (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_mul (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_muls (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_mulu (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_neg (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_negc (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_sub (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_subc (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_subv (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_and (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_not (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_or (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_tas (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_tst (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_xor (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_rotl (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_rotr (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_rotcl (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_rotcr (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_shad (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_shal (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_shar (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_shld (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_shll (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_shlr (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_shll2 (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_shlr2 (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_shll8 (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_shlr8 (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_shll16 (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_shlr16 (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_bf (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_bfs (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_bt (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_bts (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_bra (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_braf (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_bsr (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_bsrf (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_jmp (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_jsr (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_rts (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_clrmac (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_clrs (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_clrt (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_ldc (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_lds (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_movca (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_nop (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_rte (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_sets (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_sett (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_sleep (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_stc (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_sts (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 
static RzILOpEffect * sh_il_unimpl (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
 Unimplemented instruction/opcode To be used for valid SuperH-4 instruction which yet haven't been lifted to the IL. More...
 
RZ_IPI bool rz_sh_il_opcode (RZ_NONNULL RzAnalysis *analysis, RZ_NONNULL RzAnalysisOp *aop, ut64 pc, RZ_BORROW RZ_NONNULL const SHOp *op, RZ_NULLABLE SHILContext *ctx)
 Store the lifted IL for op in aop This function also takes care of initializing and adding the privilege mode local variable if required. More...
 
RZ_IPI RzAnalysisILConfig * rz_sh_il_config (RZ_NONNULL RzAnalysis *analysis)
 Initialize new config for the SuperH IL. More...
 

Variables

static const char * sh_global_registers []
 
static const sh_il_op sh_ops [SH_OP_SIZE]
 Lookup table for the IL lifting handlers for the various instructions. More...
 

Detailed Description

Converts SuperH-4 instructions to RzIL statements References:

Both the above references are almost the same

Note
Some things to know before working on this code:
  • I have used the terms "operand(s)" and "param(s)" interchangeably, and both of them refer to the arguments/params/operands of the instruction
  • op doesn NOT mean operand. It is more akin to instruction or opcode. In majority of the places, it means the type of instruction
  • I have used the term "pure" in function names very loosely and shouldn't be used in a literal sense. Refer to the Doxygen documentation to know what a function does, do not infer it from the function name

Definition in file sh_il.c.

Macro Definition Documentation

◆ SH_BIT

#define SH_BIT (   x)    UN(1, x)

Definition at line 29 of file sh_il.c.

◆ SH_FALSE

#define SH_FALSE   SH_U_REG(0)

Definition at line 31 of file sh_il.c.

◆ sh_il_get_effective_addr

#define sh_il_get_effective_addr (   x,
  y 
)    sh_il_get_effective_addr_pc_ctx(x, y, pc, ctx)

Definition at line 331 of file sh_il.c.

◆ sh_il_get_effective_addr_param

#define sh_il_get_effective_addr_param (   x)     sh_il_get_effective_addr(op->param[x], op->scaling)

Definition at line 39 of file sh_il.c.

◆ sh_il_get_param

#define sh_il_get_param (   x,
  y 
)    sh_il_get_param_pc_ctx(x, y, pc, ctx)

Definition at line 394 of file sh_il.c.

◆ sh_il_get_privilege

#define sh_il_get_privilege ( )    sh_il_get_privilege_ctx(ctx)

Definition at line 212 of file sh_il.c.

◆ sh_il_get_pure_param

#define sh_il_get_pure_param (   x)     sh_il_get_param(op->param[x], op->scaling).pure

Definition at line 33 of file sh_il.c.

◆ sh_il_get_reg

#define sh_il_get_reg (   reg)    sh_il_get_reg_ctx(reg, ctx)

Definition at line 234 of file sh_il.c.

◆ sh_il_set_param

#define sh_il_set_param (   x,
  y,
  z 
)    sh_il_set_param_pc_ctx(x, y, z, pc, ctx)

Definition at line 486 of file sh_il.c.

◆ sh_il_set_pure_param

#define sh_il_set_pure_param (   x,
  val 
)     sh_il_set_param(op->param[x], val, op->scaling)

Definition at line 36 of file sh_il.c.

◆ sh_il_set_reg

#define sh_il_set_reg (   reg,
  val 
)    sh_il_set_reg_ctx(reg, val, ctx)

Definition at line 256 of file sh_il.c.

◆ SH_S_ADDR

#define SH_S_ADDR (   x)    SN(SH_ADDR_SIZE, x)

Definition at line 26 of file sh_il.c.

◆ SH_S_REG

#define SH_S_REG (   x)    SN(SH_REG_SIZE, (x))

Definition at line 28 of file sh_il.c.

◆ SH_TRUE

#define SH_TRUE   SH_U_REG(1)

Definition at line 30 of file sh_il.c.

◆ SH_U_ADDR

#define SH_U_ADDR (   x)    UN(SH_ADDR_SIZE, x)

Definition at line 25 of file sh_il.c.

◆ SH_U_REG

#define SH_U_REG (   x)    UN(SH_REG_SIZE, (x))

Definition at line 27 of file sh_il.c.

Typedef Documentation

◆ sh_il_op

typedef RzILOpEffect*(* sh_il_op) (const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)

Definition at line 1660 of file sh_il.c.

◆ SHParamHelper

typedef struct sh_param_helper_t SHParamHelper

Helper struct to take care of converting operands to IL.

Function Documentation

◆ convert_to_st12()

st16 convert_to_st12 ( ut16  num)

Convert an unsigned 12 bit num to signed 12 bit num I have used 16 bits to represent the numbers involved here, but the 4 most significant bits are the same, so for all purposes these are basically 12 bit numbers extended to 16 bits.

Parameters
num
Returns
st16

Definition at line 276 of file sh_il.c.

276  {
277  return (num << 4) >> 4;
278 }
num
static static fork const void static count static fd const char const char static newpath char char char static envp time_t static t const char static mode static whence const char static dir time_t static t unsigned static seconds const char struct utimbuf static buf static inc static sig const char static mode static oldfd struct tms static buf static getgid static geteuid const char static filename static arg static mask struct ustat static ubuf static getppid static setsid static egid sigset_t static set struct timeval struct timezone static tz fd_set fd_set fd_set struct timeval static timeout const char char static bufsiz const char static swapflags void static offset const char static length static mode static who const char struct statfs static buf unsigned unsigned num
Definition: sflib.h:126

References num.

Referenced by sh_il_get_effective_addr_pc_ctx().

◆ rz_sh_il_config()

RZ_IPI RzAnalysisILConfig* rz_sh_il_config ( RZ_NONNULL RzAnalysis *  analysis)

Initialize new config for the SuperH IL.

Parameters
analysisRzAnalysis instance
Returns
RzAnalysisILConfig* RzIL config for SuperH ISA

Definition at line 1784 of file sh_il.c.

1784  {
1785  rz_return_val_if_fail(analysis, NULL);
1786 
1787  RzAnalysisILConfig *r = rz_analysis_il_config_new(SH_ADDR_SIZE, analysis->big_endian, SH_ADDR_SIZE);
1788  return r;
1789 }
rz_analysis_il_config_new
RZ_API RZ_OWN RzAnalysisILConfig * rz_analysis_il_config_new(ut32 pc_size, bool big_endian, ut32 mem_key_size)
Definition: analysis_il.c:53
NULL
#define NULL
Definition: cris-opc.c:27
r
#define r
Definition: crypto_rc6.c:12
rz_return_val_if_fail
#define rz_return_val_if_fail(expr, val)
Definition: rz_assert.h:108
SH_ADDR_SIZE
#define SH_ADDR_SIZE
Definition: disassembler.h:11
rz_analysis_il_config_t
Description of the global context of an RzAnalysisILVM.
Definition: rz_analysis.h:1134

References NULL, r, rz_analysis_il_config_new(), rz_return_val_if_fail, and SH_ADDR_SIZE.

◆ rz_sh_il_opcode()

RZ_IPI bool rz_sh_il_opcode ( RZ_NONNULL RzAnalysis *  analysis,
RZ_NONNULL RzAnalysisOp *  aop,
ut64  pc,
RZ_BORROW RZ_NONNULL const SHOp *  op,
RZ_NULLABLE SHILContext *  ctx 
)

Store the lifted IL for op in aop This function also takes care of initializing and adding the privilege mode local variable if required.

Parameters
analysisRzAnalysis instance
aop
pcProgram counter
op
ctxContext variables for the current IL lifting
Returns
bool True if successful ; false otherwise

Definition at line 1759 of file sh_il.c.

1759  {
1760  rz_return_val_if_fail(analysis && aop && op, false);
1761  if (op->mnemonic >= SH_OP_SIZE) {
1762  RZ_LOG_ERROR("RzIL: SuperH: out of bounds op\n");
1763  return false;
1764  }
1765 
1766  sh_il_op create_op = sh_ops[op->mnemonic];
1767  RzILOpEffect *lifted = create_op(op, pc, analysis, ctx);
1768 
1769  // If the privilege was checked, then we need to set the local variable before the IL lifting
1770  if (ctx && ctx->privilege_check) {
1771  lifted = sh_apply_effects(lifted, sh_il_initialize_privilege(), NULL);
1772  }
1773 
1774  aop->il_op = lifted;
1775  return true;
1776 }
RZ_LOG_ERROR
#define RZ_LOG_ERROR(fmtstr,...)
Definition: rz_log.h:58
SH_OP_SIZE
@ SH_OP_SIZE
Definition: disassembler.h:234
sh_ops
static const sh_il_op sh_ops[SH_OP_SIZE]
Lookup table for the IL lifting handlers for the various instructions.
Definition: sh_il.c:1665
sh_il_op
RzILOpEffect *(* sh_il_op)(const SHOp *op, ut64 pc, RzAnalysis *analysis, SHILContext *ctx)
Definition: sh_il.c:1660
sh_il_initialize_privilege
static RzILOpEffect * sh_il_initialize_privilege()
Set the value of the local variable "_priv" This exists so that the privilege mode IL doesn't have to...
Definition: sh_il.c:192
sh_apply_effects
static RzILOpEffect * sh_apply_effects(RZ_NULLABLE RzILOpEffect *target, RZ_NULLABLE RzILOpEffect *pre, RZ_NULLABLE RzILOpEffect *post)
Apply the effects in order: pre, target, post The good thing about this function is that any of the a...
Definition: sh_il.c:407
rz_il_op_effect_t
Definition: rz_il_opcodes.h:511
op
Definition: dis.c:32

References NULL, pc, RZ_LOG_ERROR, rz_return_val_if_fail, sh_apply_effects(), sh_il_initialize_privilege(), SH_OP_SIZE, and sh_ops.

Referenced by sh_op().

◆ sh_apply_effects()

static RzILOpEffect* sh_apply_effects ( RZ_NULLABLE RzILOpEffect *  target,
RZ_NULLABLE RzILOpEffect *  pre,
RZ_NULLABLE RzILOpEffect *  post 
)
static

Apply the effects in order: pre, target, post The good thing about this function is that any of the arguments can be NULL which implies that they do not exist/matter, and the final effect woulds be calculated without these NULL arguments (keeping in mind the above order)

Parameters
target
pre
post
Returns
RzILOpEffect*

Definition at line 407 of file sh_il.c.

407  {
408  if (!target) {
409  if (pre) {
410  target = pre;
411  goto append;
412  } else if (post) {
413  return post;
414  }
415  return NULL;
416  }
417 
418  if (pre) {
419  target = SEQ2(pre, target);
420  }
421 append:
422  if (post) {
423  target = SEQ2(target, post);
424  }
425 
426  return target;
427 }
append
#define append(x, y)
Definition: cmd_print.c:1740
SEQ2
#define SEQ2(e0, e1)
Definition: rz_il_opbuilder_begin.h:106
post
static void post(QUEUE *q, enum uv__work_kind kind)
Definition: threadpool.c:142

References append, NULL, post(), and SEQ2.

Referenced by rz_sh_il_opcode(), sh_il_mov(), and sh_il_set_param_pc_ctx().

◆ sh_banked_reg()

static bool sh_banked_reg ( ut16  reg)
static

Definition at line 48 of file sh_il.c.

48  {
49  return reg < SH_BANKED_REG_COUNT;
50 }
reg
#define reg(n)
SH_BANKED_REG_COUNT
#define SH_BANKED_REG_COUNT
Definition: disassembler.h:14

References reg, and SH_BANKED_REG_COUNT.

Referenced by sh_get_banked_reg(), sh_il_get_reg_ctx(), and sh_il_set_reg_ctx().

◆ sh_get_banked_reg()

static const char* sh_get_banked_reg ( ut16  reg,
ut8  bank 
)
static

Get the register name for reg in bank bank.

Parameters
regRegister index
bankBank number
Returns
const char* IL global variable name

Definition at line 97 of file sh_il.c.

97  {
98  if (!sh_banked_reg(reg) || bank > 1) {
99  return NULL;
100  }
101  return sh_global_registers[reg + bank * SH_BANKED_REG_COUNT];
102 }
sh_global_registers
static const char * sh_global_registers[]
Definition: sh_il.c:55
sh_banked_reg
static bool sh_banked_reg(ut16 reg)
Definition: sh_il.c:48

References NULL, reg, sh_banked_reg(), SH_BANKED_REG_COUNT, and sh_global_registers.

Referenced by sh_il_get_reg_ctx(), sh_il_ldc(), sh_il_set_reg_ctx(), and sh_il_stc().

◆ sh_il_add()

static RzILOpEffect* sh_il_add ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

ADD Rm, Rn Rn + Rm -> Rn 0011nnnnmmmm1100

ADD imm, Rn Rn + imm -> Rn 0111nnnniiiiiiii

Definition at line 689 of file sh_il.c.

689  {
690  return sh_il_set_pure_param(1, ADD(sh_il_get_pure_param(0), sh_il_get_pure_param(1)));
691 }
ADD
#define ADD
Definition: rsp_idec.c:200
sh_il_get_pure_param
#define sh_il_get_pure_param(x)
Definition: sh_il.c:33
sh_il_set_pure_param
#define sh_il_set_pure_param(x, val)
Definition: sh_il.c:36

References ADD, sh_il_get_pure_param, and sh_il_set_pure_param.

◆ sh_il_addc()

static RzILOpEffect* sh_il_addc ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

ADDC Rm, Rn Rn + Rm + T -> Rn carry -> T 0011nnnnmmmm1110

Definition at line 699 of file sh_il.c.

699  {
700  RzILOpPure *sum = ADD(sh_il_get_pure_param(0), sh_il_get_pure_param(1));
701  RzILOpEffect *local_sum = SETL("sum", ADD(sum, UNSIGNED(SH_REG_SIZE, sh_il_get_status_reg_bit(SH_SR_T))));
702 
703  RzILOpEffect *tbit = SETG(SH_SR_T, sh_il_is_add_carry(VARL("sum"), sh_il_get_pure_param(0), sh_il_get_pure_param(1)));
704  RzILOpEffect *ret = sh_il_set_pure_param(1, VARL("sum"));
705  return SEQ3(local_sum, tbit, ret);
706 }
SEQ3
#define SEQ3(e0, e1, e2)
Definition: rz_il_opbuilder_begin.h:107
SETL
#define SETL(name, v)
Definition: rz_il_opbuilder_begin.h:103
UNSIGNED
#define UNSIGNED(n, x)
Definition: rz_il_opbuilder_begin.h:59
VARL
#define VARL(name)
Definition: rz_il_opbuilder_begin.h:100
SETG
#define SETG(name, v)
Definition: rz_il_opbuilder_begin.h:102
SH_SR_T
#define SH_SR_T
SR.T: True/False condition or carry/borrow bit.
Definition: disassembler.h:49
SH_REG_SIZE
#define SH_REG_SIZE
Definition: disassembler.h:10
sh_il_get_status_reg_bit
static RzILOpBitVector * sh_il_get_status_reg_bit(const char *bit)
We need this because sometimes we would want an RzILOpBitvector back when we ask for a status reg bit...
Definition: sh_il.c:122
sh_il_is_add_carry
static RzILOpBool * sh_il_is_add_carry(RZ_OWN RzILOpPure *res, RZ_OWN RzILOpPure *x, RZ_OWN RzILOpPure *y)
Check if there was a carry in the addition of x and y to get res Here res = x + y (+ 1,...
Definition: sh_il.c:501
rz_il_op_pure_t
An IL op performing a pure computation, 'a pure.
Definition: rz_il_opcodes.h:399

References ADD, SEQ3, SETG, SETL, sh_il_get_pure_param, sh_il_get_status_reg_bit(), sh_il_is_add_carry(), sh_il_set_pure_param, SH_REG_SIZE, SH_SR_T, UNSIGNED, and VARL.

◆ sh_il_addv()

static RzILOpEffect* sh_il_addv ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

ADDV Rm, Rn Rn + Rm -> Rn overflow -> T 0011nnnnmmmm1111

Definition at line 714 of file sh_il.c.

714  {
715  RzILOpPure *sum = ADD(sh_il_get_pure_param(0), sh_il_get_pure_param(1));
716  RzILOpEffect *local_sum = SETL("sum", sum);
717 
718  RzILOpEffect *tbit = SETG(SH_SR_T, sh_il_is_add_overflow(VARL("sum"), sh_il_get_pure_param(0), sh_il_get_pure_param(1)));
719  RzILOpEffect *ret = sh_il_set_pure_param(1, VARL("sum"));
720  return SEQ3(local_sum, tbit, ret);
721 }
sh_il_is_add_overflow
static RzILOpBool * sh_il_is_add_overflow(RZ_OWN RzILOpPure *res, RZ_OWN RzILOpPure *x, RZ_OWN RzILOpPure *y)
Check if there was a overflow in the addition of x and y to get res Here res = x + y.
Definition: sh_il.c:570

References ADD, SEQ3, SETG, SETL, sh_il_get_pure_param, sh_il_is_add_overflow(), sh_il_set_pure_param, SH_SR_T, and VARL.

◆ sh_il_and()

static RzILOpEffect* sh_il_and ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

AND Rm, Rn Rn & Rm -> Rn 0010nnnnmmmm1001

AND imm, R0 R0 & imm -> R0 11001001iiiiiiii

AND.B imm, @(R0, GBR) (R0 + GBR) & imm -> (R0 + GBR) 11001101iiiiiiii

Definition at line 1090 of file sh_il.c.

1090  {
1091  return sh_il_set_pure_param(1, LOGAND(sh_il_get_pure_param(0), sh_il_get_pure_param(1)));
1092 }
LOGAND
#define LOGAND(x, y)
Definition: rz_il_opbuilder_begin.h:74

References LOGAND, sh_il_get_pure_param, and sh_il_set_pure_param.

◆ sh_il_bf()

static RzILOpEffect* sh_il_bf ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

BF label if T = 0, disp * 2 + PC + 4 -> PC ; otherwise (T = 1) NOP 10001011dddddddd

Definition at line 1354 of file sh_il.c.

1354  {
1355  RzILOpPure *new_pc = sh_il_get_effective_addr_param(0);
1356  return BRANCH(VARG(SH_SR_T), JMP(new_pc), NOP());
1357 }
BRANCH
#define BRANCH
NOP
#define NOP
Definition: rsp_idec.c:182
VARG
#define VARG(name)
Definition: rz_il_opbuilder_begin.h:99
JMP
#define JMP(tgt)
Definition: rz_il_opbuilder_begin.h:119
sh_il_get_effective_addr_param
#define sh_il_get_effective_addr_param(x)
Definition: sh_il.c:39

References BRANCH, JMP, NOP, sh_il_get_effective_addr_param, SH_SR_T, and VARG.

◆ sh_il_bfs()

static RzILOpEffect* sh_il_bfs ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

BF/S label if T = 0, disp * 2 + PC + 4 -> PC ; otherwise (T = 1) NOP ; delayed branch 10001111dddddddd TODO: Implement delayed branch

Definition at line 1365 of file sh_il.c.

1365  {
1366  RzILOpPure *new_pc = sh_il_get_effective_addr_param(0);
1367  return BRANCH(VARG(SH_SR_T), JMP(new_pc), NOP());
1368 }

References BRANCH, JMP, NOP, sh_il_get_effective_addr_param, SH_SR_T, and VARG.

◆ sh_il_bool_to_bv()

static RzILOpBitVector* sh_il_bool_to_bv ( RzILOpBool *  b)
static

Convert b to SH_TRUE or SH_FALSE (bool zero-extended to SH_REG_SIZE)

Parameters
bRzILOpBool to be converted
Returns
RzILOpBitVector* Zero extended bitvector value

Definition at line 110 of file sh_il.c.

110  {
111  return ITE(b, SH_TRUE, SH_FALSE);
112 }
ITE
#define ITE(c, t, f)
Definition: rz_il_opbuilder_begin.h:38
SH_TRUE
#define SH_TRUE
Definition: sh_il.c:30
SH_FALSE
#define SH_FALSE
Definition: sh_il.c:31
b
#define b(i)
Definition: sha256.c:42

References b, ITE, SH_FALSE, and SH_TRUE.

Referenced by sh_il_div1(), and sh_il_get_status_reg_bit().

◆ sh_il_bra()

static RzILOpEffect* sh_il_bra ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

BRA label disp * 2 + PC + 4 -> PC ; delayed branch 1010dddddddddddd TODO: Implement delayed branch

Definition at line 1397 of file sh_il.c.

1397  {
1398  return JMP(sh_il_get_effective_addr_param(0));
1399 }

References JMP, and sh_il_get_effective_addr_param.

◆ sh_il_braf()

static RzILOpEffect* sh_il_braf ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

BRAF Rn Rn + PC + 4 -> PC ; delayed branch 0000nnnn00100011 TODO: Implement delayed branch

Definition at line 1407 of file sh_il.c.

1407  {
1408  return JMP(sh_il_get_effective_addr_param(0));
1409 }

References JMP, and sh_il_get_effective_addr_param.

◆ sh_il_bsr()

static RzILOpEffect* sh_il_bsr ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

BSR label PC + 4 -> PR ; disp * 2 + PC + 4 -> PC ; delayed branch 1011dddddddddddd TODO: Implement delayed branch

Definition at line 1417 of file sh_il.c.

1417  {
1418  return SEQ2(SETG("pr", ADD(SH_U_ADDR(pc), SH_U_ADDR(4))), JMP(sh_il_get_effective_addr_param(0)));
1419 }
SH_U_ADDR
#define SH_U_ADDR(x)
Definition: sh_il.c:25

References ADD, JMP, pc, SEQ2, SETG, sh_il_get_effective_addr_param, and SH_U_ADDR.

◆ sh_il_bsrf()

static RzILOpEffect* sh_il_bsrf ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

BSRF Rn PC + 4 -> PR ; Rn + PC + 4 -> PC ; delayed branch 0000nnnn00000011 TODO: Implement delayed branch

Definition at line 1427 of file sh_il.c.

1427  {
1428  return SEQ2(SETG("pr", ADD(SH_U_ADDR(pc), SH_U_ADDR(4))), JMP(sh_il_get_effective_addr_param(0)));
1429 }

References ADD, JMP, pc, SEQ2, SETG, sh_il_get_effective_addr_param, and SH_U_ADDR.

◆ sh_il_bt()

static RzILOpEffect* sh_il_bt ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

BT label if T = 1, disp * 2 + PC + 4 -> PC ; otherwise (T = 0) NOP 10001001dddddddd

Definition at line 1375 of file sh_il.c.

1375  {
1376  RzILOpPure *new_pc = sh_il_get_effective_addr_param(0);
1377  return BRANCH(VARG(SH_SR_T), JMP(new_pc), NOP());
1378 }

References BRANCH, JMP, NOP, sh_il_get_effective_addr_param, SH_SR_T, and VARG.

◆ sh_il_bts()

static RzILOpEffect* sh_il_bts ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

BT/S label if T = 1, disp * 2 + PC + 4 -> PC ; otherwise (T = 0) NOP ; delayed branch 10001101dddddddd TODO: Implement delayed branch

Definition at line 1386 of file sh_il.c.

1386  {
1387  RzILOpPure *new_pc = sh_il_get_effective_addr_param(0);
1388  return BRANCH(VARG(SH_SR_T), JMP(new_pc), NOP());
1389 }

References BRANCH, JMP, NOP, sh_il_get_effective_addr_param, SH_SR_T, and VARG.

◆ sh_il_clrmac()

static RzILOpEffect* sh_il_clrmac ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

CLRMAC 0 -> MACH, MACL 0000000000101000

Definition at line 1466 of file sh_il.c.

1466  {
1467  return SEQ2(SETG("mach", UN(SH_REG_SIZE, 0)), SETG("macl", UN(SH_REG_SIZE, 0)));
1468 }
UN
#define UN(l, val)
Definition: rz_il_opbuilder_begin.h:40

References SEQ2, SETG, SH_REG_SIZE, and UN.

◆ sh_il_clrs()

static RzILOpEffect* sh_il_clrs ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

CLRS 0 -> S 0000000001001000

Definition at line 1475 of file sh_il.c.

1475  {
1476  return SETG(SH_SR_S, IL_FALSE);
1477 }
IL_FALSE
#define IL_FALSE
Definition: rz_il_opbuilder_begin.h:52
SH_SR_S
#define SH_SR_S
SR.S: Specifies a saturation operation for a MAC instruction.
Definition: disassembler.h:51

References IL_FALSE, SETG, and SH_SR_S.

◆ sh_il_clrt()

static RzILOpEffect* sh_il_clrt ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

CLRT 0 -> T 0000000000001000

Definition at line 1484 of file sh_il.c.

1484  {
1485  return SETG(SH_SR_T, IL_FALSE);
1486 }

References IL_FALSE, SETG, and SH_SR_T.

◆ sh_il_cmp_eq()

static RzILOpEffect* sh_il_cmp_eq ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

CMP/EQ imm, R0 When R0 = imm, 1 -> T ; Otherwise, 0 -> T 10001000iiiiiiii

CMP/EQ Rm, Rn When Rn = Rm, 1 -> T ; Otherwise, 0 -> T 0011nnnnmmmm0000

Definition at line 732 of file sh_il.c.

732  {
733  return SETG(SH_SR_T, EQ(sh_il_get_pure_param(0), sh_il_get_pure_param(1)));
734 }
EQ
#define EQ(x, y)
Definition: rz_il_opbuilder_begin.h:84

References EQ, SETG, sh_il_get_pure_param, and SH_SR_T.

◆ sh_il_cmp_ge()

static RzILOpEffect* sh_il_cmp_ge ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

CMP/GE Rm, Rn When Rn >= Rm (signed), 1 -> T ; Otherwise, 0 -> T 0011nnnnmmmm0011

Definition at line 750 of file sh_il.c.

750  {
751  return SETG(SH_SR_T, SGE(sh_il_get_pure_param(1), sh_il_get_pure_param(0)));
752 }
SGE
#define SGE(x, y)
Definition: rz_il_opbuilder_begin.h:92

References SETG, SGE, sh_il_get_pure_param, and SH_SR_T.

◆ sh_il_cmp_gt()

static RzILOpEffect* sh_il_cmp_gt ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

CMP/GT Rm, Rn When Rn > Rm (signed), 1 -> T ; Otherwise, 0 -> T 0011nnnnmmmm0111

Definition at line 768 of file sh_il.c.

768  {
769  return SETG(SH_SR_T, SGT(sh_il_get_pure_param(1), sh_il_get_pure_param(0)));
770 }
SGT
#define SGT(x, y)
Definition: rz_il_opbuilder_begin.h:91

References SETG, SGT, sh_il_get_pure_param, and SH_SR_T.

◆ sh_il_cmp_hi()

static RzILOpEffect* sh_il_cmp_hi ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

CMP/HI Rm, Rn When Rn > Rm (unsigned), 1 -> T ; Otherwise, 0 -> T 0011nnnnmmmm0110

Definition at line 759 of file sh_il.c.

759  {
760  return SETG(SH_SR_T, UGT(sh_il_get_pure_param(1), sh_il_get_pure_param(0)));
761 }
UGT
#define UGT(x, y)
Definition: rz_il_opbuilder_begin.h:87

References SETG, sh_il_get_pure_param, SH_SR_T, and UGT.

◆ sh_il_cmp_hs()

static RzILOpEffect* sh_il_cmp_hs ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

CMP/HS Rm, Rn When Rn >= Rm (unsigned), 1 -> T ; Otherwise, 0 -> T 0011nnnnmmmm0010

Definition at line 741 of file sh_il.c.

741  {
742  return SETG(SH_SR_T, UGE(sh_il_get_pure_param(1), sh_il_get_pure_param(0)));
743 }
UGE
#define UGE(x, y)
Definition: rz_il_opbuilder_begin.h:88

References SETG, sh_il_get_pure_param, SH_SR_T, and UGE.

◆ sh_il_cmp_pl()

static RzILOpEffect* sh_il_cmp_pl ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

CMP/PL Rn When Rn > 0, 1 -> T ; Otherwise, 0 -> T 0100nnnn00010101

Definition at line 786 of file sh_il.c.

786  {
787  return SETG(SH_SR_T, SGT(sh_il_get_pure_param(0), SH_S_REG(0)));
788 }
SH_S_REG
#define SH_S_REG(x)
Definition: sh_il.c:28

References SETG, SGT, sh_il_get_pure_param, SH_S_REG, and SH_SR_T.

◆ sh_il_cmp_pz()

static RzILOpEffect* sh_il_cmp_pz ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

CMP/PZ Rn When Rn >= 0, 1 -> T ; Otherwise, 0 -> T 0100nnnn00010001

Definition at line 777 of file sh_il.c.

777  {
778  return SETG(SH_SR_T, SGE(sh_il_get_pure_param(0), SH_S_REG(0)));
779 }

References SETG, SGE, sh_il_get_pure_param, SH_S_REG, and SH_SR_T.

◆ sh_il_cmp_str()

static RzILOpEffect* sh_il_cmp_str ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

CMP/STR Rm, Rn When any bytes are equal, 1 -> T ; Otherwise, 0 -> T 0010nnnnmmmm1100

Definition at line 795 of file sh_il.c.

795  {
796  RzILOpPure *full_xor = LOGXOR(sh_il_get_pure_param(0), sh_il_get_pure_param(1));
797  RzILOpEffect *eff = SETL("xor", full_xor);
798 
799  eff = SEQ2(eff, SETL("eq", EQ(LOGAND(VARL("xor"), SH_U_REG(0xff)), SH_U_REG(0x0))));
800  eff = SEQ2(eff, SETL("xor", SHIFTR0(VARL("xor"), SH_U_REG(BITS_PER_BYTE))));
801  eff = SEQ2(eff, SETL("eq", OR(VARL("eq"), EQ(LOGAND(VARL("xor"), SH_U_REG(0xff)), SH_U_REG(0x0)))));
802  eff = SEQ2(eff, SETL("xor", SHIFTR0(VARL("xor"), SH_U_REG(BITS_PER_BYTE))));
803  eff = SEQ2(eff, SETL("eq", OR(VARL("eq"), EQ(LOGAND(VARL("xor"), SH_U_REG(0xff)), SH_U_REG(0x0)))));
804  eff = SEQ2(eff, SETL("xor", SHIFTR0(VARL("xor"), SH_U_REG(BITS_PER_BYTE))));
805  eff = SEQ2(eff, SETL("eq", OR(VARL("eq"), EQ(LOGAND(VARL("xor"), SH_U_REG(0xff)), SH_U_REG(0x0)))));
806 
807  return SEQ2(eff, SETG(SH_SR_T, VARL("eq")));
808 }
OR
#define OR
Definition: rsp_idec.c:210
SHIFTR0
#define SHIFTR0(v, dist)
Definition: rz_il_opbuilder_begin.h:72
LOGXOR
#define LOGXOR(x, y)
Definition: rz_il_opbuilder_begin.h:76
BITS_PER_BYTE
#define BITS_PER_BYTE
Definition: disassembler.h:9
SH_U_REG
#define SH_U_REG(x)
Definition: sh_il.c:27

References BITS_PER_BYTE, EQ, LOGAND, LOGXOR, OR, SEQ2, SETG, SETL, sh_il_get_pure_param, SH_SR_T, SH_U_REG, SHIFTR0, and VARL.

◆ sh_il_div0s()

static RzILOpEffect* sh_il_div0s ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

DIV0S Rm, Rn MSB of Rn -> Q ; MSB of Rm -> M, M^Q -> T 0010nnnnmmmm0111

Definition at line 855 of file sh_il.c.

855  {
856  RzILOpEffect *setq = SETG(SH_SR_Q, MSB(sh_il_get_pure_param(1)));
857  RzILOpEffect *setm = SETG(SH_SR_M, MSB(sh_il_get_pure_param(0)));
858  RzILOpEffect *sett = SETG(SH_SR_T, XOR(VARG(SH_SR_M), VARG(SH_SR_Q)));
859 
860  return SEQ3(setq, setm, sett);
861 }
XOR
#define XOR
Definition: rsp_idec.c:212
MSB
#define MSB(x)
Definition: rz_il_opbuilder_begin.h:82
SH_SR_M
#define SH_SR_M
SR.M: State for divide step (Used by the DIV0S, DIV0U and DIV1 instructions)
Definition: disassembler.h:57
SH_SR_Q
#define SH_SR_Q
SR.Q: State for divide step (Used by the DIV0S, DIV0U and DIV1 instructions)
Definition: disassembler.h:55

References MSB, SEQ3, SETG, sh_il_get_pure_param, SH_SR_M, SH_SR_Q, SH_SR_T, VARG, and XOR.

◆ sh_il_div0u()

static RzILOpEffect* sh_il_div0u ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

DIV0U Rm, Rn 0 -> M/Q/T 0000000000011001

Definition at line 868 of file sh_il.c.

868  {
869  return SEQ3(SETG(SH_SR_M, IL_FALSE), SETG(SH_SR_Q, IL_FALSE), SETG(SH_SR_T, IL_FALSE));
870 }

References IL_FALSE, SEQ3, SETG, SH_SR_M, SH_SR_Q, and SH_SR_T.

◆ sh_il_div1()

static RzILOpEffect* sh_il_div1 ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

DIV1 Rm, Rn 1-step division (Rn ÷ Rm) ; Calculation result -> T 0011nnnnmmmm0100

Definition at line 815 of file sh_il.c.

815  {
816  RzILOpEffect *ret = NULL;
817  RzILOpEffect *q = SETL("q", VARG(SH_SR_Q));
818  RzILOpEffect *m = SETL("m", VARG(SH_SR_M));
819  RzILOpEffect *t = SETL("t", VARG(SH_SR_T));
820  ret = SEQ3(q, m, t);
821 
822  RzILOpEffect *op1 = SETL("op1", sh_il_get_pure_param(0));
823  RzILOpEffect *op2 = SETL("op2", sh_il_get_pure_param(1));
824  RzILOpEffect *old_q = SETL("old_q", VARL("q"));
825  ret = SEQ4(ret, op1, op2, old_q);
826 
827  // Get 31st bit of var q
828  q = SETL("q", NON_ZERO(LOGAND(VARL("op2"), SH_U_REG(0x80000000))));
829  op2 = SETL("op2", LOGOR(SHIFTL0(VARL("op2"), SH_U_REG(1)), sh_il_bool_to_bv(VARL("t"))));
830  ret = SEQ3(ret, q, op2);
831 
832  RzILOpEffect *true_eff = SETL("op2", SUB(VARL("op2"), VARL("op1")));
833  RzILOpEffect *false_eff = SETL("op2", ADD(VARL("op2"), VARL("op1")));
834  RzILOpEffect *cond = BRANCH(EQ(sh_il_bool_to_bv(VARL("old_q")), sh_il_bool_to_bv(VARL("m"))), true_eff, false_eff);
835  ret = SEQ2(ret, cond);
836 
837  // q = q ^ m ^ msb(op2)
838  q = SETL("q", XOR(XOR(VARL("q"), VARL("m")), MSB(VARL("op2"))));
839  t = SETL("t", NON_ZERO(SUB(SH_U_REG(1), LOGXOR(sh_il_bool_to_bv(VARL("q")), sh_il_bool_to_bv(VARL("m"))))));
840  ret = SEQ3(ret, q, t);
841 
842  RzILOpEffect *rn = sh_il_set_pure_param(1, VARL("op2"));
843  q = SETG(SH_SR_Q, VARL("q"));
844  t = SETG(SH_SR_T, VARL("t"));
845  ret = SEQ4(ret, rn, q, t);
846 
847  return ret;
848 }
LOGOR
#define LOGOR(x, y)
Definition: rz_il_opbuilder_begin.h:75
SEQ4
#define SEQ4(e0, e1, e2, e3)
Definition: rz_il_opbuilder_begin.h:108
NON_ZERO
#define NON_ZERO(x)
Definition: rz_il_opbuilder_begin.h:80
SHIFTL0
#define SHIFTL0(v, dist)
Definition: rz_il_opbuilder_begin.h:71
SUB
#define SUB(ns, call)
sh_il_bool_to_bv
static RzILOpBitVector * sh_il_bool_to_bv(RzILOpBool *b)
Convert b to SH_TRUE or SH_FALSE (bool zero-extended to SH_REG_SIZE)
Definition: sh_il.c:110
cond
#define cond(bop, top, mask, flags)

References ADD, BRANCH, cond, EQ, LOGAND, LOGOR, LOGXOR, regress::m, MSB, NON_ZERO, NULL, SEQ2, SEQ3, SEQ4, SETG, SETL, sh_il_bool_to_bv(), sh_il_get_pure_param, sh_il_set_pure_param, SH_SR_M, SH_SR_Q, SH_SR_T, SH_U_REG, SHIFTL0, SUB, VARG, VARL, and XOR.

◆ sh_il_dmuls()

static RzILOpEffect* sh_il_dmuls ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

DMULS.L Rm, Rn Signed, Rn * Rm -> MAC ; 32 * 32 -> 64 bits 0011nnnnmmmm1101

Definition at line 877 of file sh_il.c.

877  {
878  RzILOpEffect *eff = SETL("res_wide", MUL(SIGNED(2 * SH_REG_SIZE, sh_il_get_pure_param(0)), SIGNED(2 * SH_REG_SIZE, sh_il_get_pure_param(1))));
879  RzILOpPure *lower_bits = UNSIGNED(SH_REG_SIZE, LOGAND(VARL("res_wide"), UN(2 * SH_REG_SIZE, 0xffffffff)));
880  RzILOpPure *higher_bits = UNSIGNED(SH_REG_SIZE, SHIFTR0(VARL("res_wide"), SH_U_REG(SH_REG_SIZE)));
881  return SEQ3(eff, SETG("macl", lower_bits), SETG("mach", higher_bits));
882 }
SIGNED
#define SIGNED
Definition: ansidecl.h:248
MUL
#define MUL(x, y)
Definition: rz_il_opbuilder_begin.h:66

References LOGAND, MUL, SEQ3, SETG, SETL, sh_il_get_pure_param, SH_REG_SIZE, SH_U_REG, SHIFTR0, SIGNED, UN, UNSIGNED, and VARL.

◆ sh_il_dmulu()

static RzILOpEffect* sh_il_dmulu ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

DMULU.L Rm, Rn Unsigned, Rn * Rm -> MAC ; 32 * 32 -> 64 bits 0011nnnnmmmm0101

Definition at line 889 of file sh_il.c.

889  {
890  RzILOpEffect *eff = SETL("res_wide", MUL(UNSIGNED(2 * SH_REG_SIZE, sh_il_get_pure_param(0)), UNSIGNED(2 * SH_REG_SIZE, sh_il_get_pure_param(1))));
891  RzILOpPure *lower_bits = UNSIGNED(SH_REG_SIZE, LOGAND(VARL("res_wide"), UN(2 * SH_REG_SIZE, 0xffffffff)));
892  RzILOpPure *higher_bits = UNSIGNED(SH_REG_SIZE, SHIFTR0(VARL("res_wide"), SH_U_REG(SH_REG_SIZE)));
893  return SEQ3(eff, SETG("macl", lower_bits), SETG("mach", higher_bits));
894 }

References LOGAND, MUL, SEQ3, SETG, SETL, sh_il_get_pure_param, SH_REG_SIZE, SH_U_REG, SHIFTR0, UN, UNSIGNED, and VARL.

◆ sh_il_dt()

static RzILOpEffect* sh_il_dt ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

DT Rn Rn - 1 -> Rn ; When Rn = 0, 1 -> T ; Otherwise 0 -> T 0100nnnn00010000

Definition at line 901 of file sh_il.c.

901  {
902  return SEQ2(sh_il_set_pure_param(0, SUB(sh_il_get_pure_param(0), SH_U_REG(1))), SETG(SH_SR_T, IS_ZERO(sh_il_get_pure_param(0))));
903 }
IS_ZERO
#define IS_ZERO(x)
Definition: rz_il_opbuilder_begin.h:81

References IS_ZERO, SEQ2, SETG, sh_il_get_pure_param, sh_il_set_pure_param, SH_SR_T, SH_U_REG, and SUB.

◆ sh_il_exts()

static RzILOpEffect* sh_il_exts ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

EXTS.B Rm, Rn Rm sign-extended from byte -> Rn 0110nnnnmmmm1110

EXTS.W Rm, Rn Rm sign-extended from word -> Rn 0110nnnnmmmm1111

Definition at line 914 of file sh_il.c.

914  {
915  return sh_il_set_pure_param(1, sh_il_get_pure_param(0));
916 }

References sh_il_get_pure_param, and sh_il_set_pure_param.

◆ sh_il_extu()

static RzILOpEffect* sh_il_extu ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

EXTU.B Rm, Rn Rm zero-extended from byte -> Rn 0110nnnnmmmm1100

EXTU.W Rm, Rn Rm zero-extended from word -> Rn 0110nnnnmmmm1101

Definition at line 927 of file sh_il.c.

927  {
928  /* Do not use `sh_il_set_pure_param` here since that will sign extend the Rn value, but we want
929  it extend it unsigned, which is why we need to directly call `sh_il_set_reg` */
930  return sh_il_set_reg(op->param[1].param[0], UNSIGNED(SH_REG_SIZE, sh_il_get_pure_param(0)));
931 }
sh_il_set_reg
#define sh_il_set_reg(reg, val)
Definition: sh_il.c:256

References sh_il_get_pure_param, sh_il_set_reg, SH_REG_SIZE, and UNSIGNED.

◆ sh_il_get_effective_addr_pc_ctx()

static RzILOpPure* sh_il_get_effective_addr_pc_ctx ( SHParam  param,
SHScaling  scaling,
ut64  pc,
SHILContext *  ctx 
)
static

Get the effective address obtained from the given param and scaling.

Parameters
param
scaling
pcProgram counter
ctxSHILContext instance
Returns
RzILOpPure*

Definition at line 289 of file sh_il.c.

289  {
290  switch (param.mode) {
291  case SH_REG_INDIRECT:
292  case SH_REG_INDIRECT_I:
293  case SH_REG_INDIRECT_D:
294  return sh_il_get_reg(param.param[0]);
295  case SH_REG_INDIRECT_DISP:
296  return ADD(sh_il_get_reg(param.param[0]), MUL(SH_U_ADDR(param.param[1]), SH_U_ADDR(sh_scaling_size[scaling])));
297  case SH_REG_INDIRECT_INDEXED:
298  return ADD(sh_il_get_reg(SH_REG_IND_R0), sh_il_get_reg(param.param[0]));
299  case SH_GBR_INDIRECT_DISP:
300  return ADD(VARG("gbr"), MUL(SH_U_ADDR(param.param[0]), SH_U_ADDR(sh_scaling_size[scaling])));
301  case SH_GBR_INDIRECT_INDEXED:
302  return ADD(VARG("gbr"), sh_il_get_reg(SH_REG_IND_R0));
303  case SH_PC_RELATIVE_DISP: {
304  RzILOpBitVector *pcbv = SH_U_ADDR(pc);
305  // mask lower 2 bits if long word
306  if (scaling == SH_SCALING_L) {
307  pcbv = LOGAND(pcbv, SH_U_ADDR(0xfffffffc));
308  }
309  pcbv = ADD(pcbv, SH_U_ADDR(4));
310  return ADD(pcbv, MUL(SH_U_ADDR(param.param[0]), SH_U_ADDR(sh_scaling_size[scaling])));
311  }
312  case SH_PC_RELATIVE8: {
313  // sign-extended for 8 bits and shifted left by 1 (i.e. multiplied by 2)
314  RzILOpBitVector *relative = SHIFTL0(SH_S_ADDR((st8)param.param[0]), U32(1));
315  return ADD(ADD(SH_U_ADDR(pc), SH_U_ADDR(4)), relative);
316  }
317  case SH_PC_RELATIVE12: {
318  // sign-extended for 12 bits and shifted left by 1 (i.e. multiplied by 2)
319  RzILOpBitVector *relative = SHIFTL0(SH_S_ADDR(convert_to_st12(param.param[0])), U32(1));
320  return ADD(ADD(SH_U_ADDR(pc), SH_U_ADDR(4)), relative);
321  }
322  case SH_PC_RELATIVE_REG:
323  return ADD(ADD(SH_U_ADDR(pc), SH_U_ADDR(4)), sh_il_get_reg(param.param[0]));
324  default:
325  RZ_LOG_WARN("RzIL: SuperH: No effective address for this mode: %u\n", param.mode);
326  }
327 
328  return NULL;
329 }
U32
unsigned int U32
Definition: lz4.c:288
RZ_LOG_WARN
#define RZ_LOG_WARN(fmtstr,...)
Definition: rz_log.h:56
st8
#define st8
Definition: rz_types_base.h:16
SH_SCALING_L
@ SH_SCALING_L
long word
Definition: disassembler.h:39
sh_scaling_size
static const ut8 sh_scaling_size[]
Definition: disassembler.h:43
SH_REG_IND_R0
@ SH_REG_IND_R0
Definition: disassembler.h:72
SH_PC_RELATIVE8
@ SH_PC_RELATIVE8
Definition: disassembler.h:28
SH_REG_INDIRECT_DISP
@ SH_REG_INDIRECT_DISP
register indirect with displacement
Definition: disassembler.h:23
SH_PC_RELATIVE_DISP
@ SH_PC_RELATIVE_DISP
Definition: disassembler.h:27
SH_PC_RELATIVE_REG
@ SH_PC_RELATIVE_REG
Definition: disassembler.h:30
SH_PC_RELATIVE12
@ SH_PC_RELATIVE12
Definition: disassembler.h:29
SH_REG_INDIRECT_INDEXED
@ SH_REG_INDIRECT_INDEXED
indexed register indirect
Definition: disassembler.h:24
SH_REG_INDIRECT_I
@ SH_REG_INDIRECT_I
register indirect with post-increment
Definition: disassembler.h:21
SH_REG_INDIRECT
@ SH_REG_INDIRECT
Definition: disassembler.h:20
SH_REG_INDIRECT_D
@ SH_REG_INDIRECT_D
register indirect with pre-decrement
Definition: disassembler.h:22
SH_GBR_INDIRECT_DISP
@ SH_GBR_INDIRECT_DISP
Definition: disassembler.h:25
SH_GBR_INDIRECT_INDEXED
@ SH_GBR_INDIRECT_INDEXED
Definition: disassembler.h:26
SH_S_ADDR
#define SH_S_ADDR(x)
Definition: sh_il.c:26
sh_il_get_reg
#define sh_il_get_reg(reg)
Definition: sh_il.c:234
convert_to_st12
st16 convert_to_st12(ut16 num)
Convert an unsigned 12 bit num to signed 12 bit num I have used 16 bits to represent the numbers invo...
Definition: sh_il.c:276
sh_param_t::param
ut16 param[2]
Definition: disassembler.h:238
sh_param_t::mode
SHAddrMode mode
Definition: disassembler.h:239

References ADD, convert_to_st12(), LOGAND, sh_param_t::mode, MUL, NULL, sh_param_t::param, pc, RZ_LOG_WARN, SH_GBR_INDIRECT_DISP, SH_GBR_INDIRECT_INDEXED, sh_il_get_reg, SH_PC_RELATIVE12, SH_PC_RELATIVE8, SH_PC_RELATIVE_DISP, SH_PC_RELATIVE_REG, SH_REG_IND_R0, SH_REG_INDIRECT, SH_REG_INDIRECT_D, SH_REG_INDIRECT_DISP, SH_REG_INDIRECT_I, SH_REG_INDIRECT_INDEXED, SH_S_ADDR, SH_SCALING_L, sh_scaling_size, SH_U_ADDR, SHIFTL0, st8, and VARG.

◆ sh_il_get_param_pc_ctx()

static SHParamHelper sh_il_get_param_pc_ctx ( SHParam  param,
SHScaling  scaling,
ut64  pc,
SHILContext *  ctx 
)
static

Convert the param with scaling to it's IL representation.

Parameters
param
scaling
pcProgram counter
ctxSHILContext instance
Returns
SHParamHelper Consists of the value of the param and the pre, post effects

Definition at line 342 of file sh_il.c.

342  {
343  SHParamHelper ret = {
344  .pre = NULL,
345  .pure = NULL,
346  .post = NULL
347  };
348 
349  /* In case of invalid scaling, just default to `SH_SCALING_L`, and assume param width of 32 bits (4 bytes)
350  This makes the param calculation process simpler and doesn't lead to any functional difference */
351  if (scaling == SH_SCALING_INVALID) {
352  scaling = SH_SCALING_L;
353  }
354 
355  switch (param.mode) {
356  case SH_REG_DIRECT:
357  if (scaling == SH_SCALING_L) {
358  ret.pure = sh_il_get_reg(param.param[0]);
359  } else {
360  ret.pure = UNSIGNED(BITS_PER_BYTE * sh_scaling_size[scaling], sh_il_get_reg(param.param[0]));
361  }
362  break;
363  case SH_REG_INDIRECT_I:
364  ret.post = sh_il_set_reg(param.param[0], ADD(sh_il_get_reg(param.param[0]), SH_U_ADDR(sh_scaling_size[scaling])));
365  goto set_pure;
366  case SH_REG_INDIRECT_D:
367  ret.pre = sh_il_set_reg(param.param[0], SUB(sh_il_get_reg(param.param[0]), SH_U_ADDR(sh_scaling_size[scaling])));
368  goto set_pure;
369  case SH_REG_INDIRECT:
370  case SH_REG_INDIRECT_DISP:
371  case SH_REG_INDIRECT_INDEXED:
372  case SH_GBR_INDIRECT_DISP:
373  case SH_GBR_INDIRECT_INDEXED:
374  case SH_PC_RELATIVE_DISP:
375  case SH_PC_RELATIVE8:
376  case SH_PC_RELATIVE12:
377  case SH_PC_RELATIVE_REG:
378  set_pure:
379  ret.pure = LOADW(BITS_PER_BYTE * sh_scaling_size[scaling], sh_il_get_effective_addr(param, scaling));
380  break;
381  case SH_IMM_U:
382  ret.pure = UN(sh_scaling_size[scaling] * BITS_PER_BYTE, param.param[0]);
383  break;
384  case SH_IMM_S:
385  ret.pure = SN(sh_scaling_size[scaling] * BITS_PER_BYTE, param.param[0]);
386  break;
387  default:
388  RZ_LOG_ERROR("RzIL: SuperH: Invalid addressing mode\n");
389  }
390 
391  return ret;
392 }
LOADW
#define LOADW(n, addr)
Definition: rz_il_opbuilder_begin.h:95
SN
#define SN(l, val)
Definition: rz_il_opbuilder_begin.h:46
SH_SCALING_INVALID
@ SH_SCALING_INVALID
Definition: disassembler.h:36
SH_IMM_S
@ SH_IMM_S
8-bit immediate value (sign-extended)
Definition: disassembler.h:32
SH_REG_DIRECT
@ SH_REG_DIRECT
Definition: disassembler.h:19
SH_IMM_U
@ SH_IMM_U
8-bit immediate value (zero-extended)
Definition: disassembler.h:31
sh_il_get_effective_addr
#define sh_il_get_effective_addr(x, y)
Definition: sh_il.c:331
sh_param_helper_t
Helper struct to take care of converting operands to IL.
Definition: sh_il.c:261
sh_param_helper_t::post
RzILOpEffect * post
post effect for the operand
Definition: sh_il.c:264
sh_param_helper_t::pure
RzILOpPure * pure
pure effect for the operand
Definition: sh_il.c:263
sh_param_helper_t::pre
RzILOpEffect * pre
pre effect for the operand
Definition: sh_il.c:262

References ADD, BITS_PER_BYTE, LOADW, sh_param_t::mode, NULL, sh_param_t::param, sh_param_helper_t::post, sh_param_helper_t::pre, sh_param_helper_t::pure, RZ_LOG_ERROR, SH_GBR_INDIRECT_DISP, SH_GBR_INDIRECT_INDEXED, sh_il_get_effective_addr, sh_il_get_reg, sh_il_set_reg, SH_IMM_S, SH_IMM_U, SH_PC_RELATIVE12, SH_PC_RELATIVE8, SH_PC_RELATIVE_DISP, SH_PC_RELATIVE_REG, SH_REG_DIRECT, SH_REG_INDIRECT, SH_REG_INDIRECT_D, SH_REG_INDIRECT_DISP, SH_REG_INDIRECT_I, SH_REG_INDIRECT_INDEXED, SH_SCALING_INVALID, SH_SCALING_L, sh_scaling_size, SH_U_ADDR, SN, SUB, UN, and UNSIGNED.

◆ sh_il_get_privilege_ctx()

static RzILOpPure* sh_il_get_privilege_ctx ( SHILContext *  ctx)
static

Get the privilege mode Do NOT call this before initializing privilege through sh_il_initialize_privilege Otherwise, the local variable would not have been initialized For all the liftings, this is taken care of in rz_sh_il_opcode

Parameters
ctxSHILContext instance used to store the whether privilege was checked or not
Returns
RzILOpPure* (RzILOpBool*) IL_TRUE if in privilege mode ; IL_FALSE otherwise

Definition at line 205 of file sh_il.c.

205  {
206  if (ctx) {
207  ctx->privilege_check = true;
208  }
209  return VARL("_priv");
210 }

References VARL.

◆ sh_il_get_reg_ctx()

static RzILOpPure* sh_il_get_reg_ctx ( ut16  reg,
SHILContext *  ctx 
)
static

Get register corresponding to reg index This function is smart enough to give the correct register in case of banked registers or status register.

Parameters
reg
ctxSHILContext instance
Returns
RzILOpPure*

Definition at line 222 of file sh_il.c.

222  {
223  if (!sh_banked_reg(reg) || !ctx->use_banked) {
224  if (reg == SH_REG_IND_SR) {
225  return sh_il_get_status_reg();
226  }
227  return VARG(sh_registers[reg]);
228  }
229 
230  // check if both SR.MD = 1 and SR.RB = 1
231  return ITE(sh_il_get_privilege(), VARG(sh_get_banked_reg(reg, 1)), VARG(sh_get_banked_reg(reg, 0)));
232 }
sh_registers
static const char * sh_registers[]
Definition: regs.h:10
SH_REG_IND_SR
@ SH_REG_IND_SR
Definition: disassembler.h:91
sh_il_get_privilege
#define sh_il_get_privilege()
Definition: sh_il.c:212
sh_il_get_status_reg
static RzILOpPure * sh_il_get_status_reg()
Return the status register (sr), calculated by shifting all the status register bits at the correct o...
Definition: sh_il.c:131
sh_get_banked_reg
static const char * sh_get_banked_reg(ut16 reg, ut8 bank)
Get the register name for reg in bank bank.
Definition: sh_il.c:97

References ITE, reg, sh_banked_reg(), sh_get_banked_reg(), sh_il_get_privilege, sh_il_get_status_reg(), SH_REG_IND_SR, sh_registers, and VARG.

◆ sh_il_get_status_reg()

static RzILOpPure* sh_il_get_status_reg ( )
static

Return the status register (sr), calculated by shifting all the status register bits at the correct offsets.

Returns
RzILOpPure* The status register IL bitvector

Definition at line 131 of file sh_il.c.

131  {
132  RzILOpPure *val = SH_U_REG(0);
133  val = LOGOR(sh_il_get_status_reg_bit(SH_SR_D), val);
134  val = SHIFTL0(val, SH_U_REG(1));
135  val = LOGOR(sh_il_get_status_reg_bit(SH_SR_R), val);
136  val = SHIFTL0(val, SH_U_REG(1));
137  val = LOGOR(sh_il_get_status_reg_bit(SH_SR_B), val);
138  val = SHIFTL0(val, SH_U_REG(13));
139  val = LOGOR(sh_il_get_status_reg_bit(SH_SR_F), val);
140  val = SHIFTL0(val, SH_U_REG(6));
141  val = LOGOR(sh_il_get_status_reg_bit(SH_SR_M), val);
142  val = SHIFTL0(val, SH_U_REG(1));
143  val = LOGOR(sh_il_get_status_reg_bit(SH_SR_Q), val);
144  val = SHIFTL0(val, SH_U_REG(4));
145  // VARG(SH_SR_I) is of 4 bits
146  val = LOGOR(UNSIGNED(SH_REG_SIZE, VARG(SH_SR_I)), val);
147  val = SHIFTL0(val, SH_U_REG(3));
148  val = LOGOR(sh_il_get_status_reg_bit(SH_SR_S), val);
149  val = SHIFTL0(val, SH_U_REG(1));
150  val = LOGOR(sh_il_get_status_reg_bit(SH_SR_T), val);
151 
152  return val;
153 }
val
ut16 val
Definition: armass64_const.h:6
SH_SR_R
#define SH_SR_R
SR.RB: General register bank specifier in privileged mode (set to 1 by a reset, exception or interrup...
Definition: disassembler.h:63
SH_SR_B
#define SH_SR_B
SR.BL: Exception/interrupt block bit (set to 1 by a reset, exception, or interrupt)
Definition: disassembler.h:61
SH_SR_D
#define SH_SR_D
SR.MD: Processor mode.
Definition: disassembler.h:65
SH_SR_I
#define SH_SR_I
SR.I: Interrupt mask level: External interrupts of a lower level than IMASK are masked.
Definition: disassembler.h:53
SH_SR_F
#define SH_SR_F
SR.FD: FPU disable bit (cleared to 0 by a reset)
Definition: disassembler.h:59

References LOGOR, sh_il_get_status_reg_bit(), SH_REG_SIZE, SH_SR_B, SH_SR_D, SH_SR_F, SH_SR_I, SH_SR_M, SH_SR_Q, SH_SR_R, SH_SR_S, SH_SR_T, SH_U_REG, SHIFTL0, UNSIGNED, val, and VARG.

Referenced by sh_il_get_reg_ctx().

◆ sh_il_get_status_reg_bit()

static RzILOpBitVector* sh_il_get_status_reg_bit ( const char *  bit)
static

We need this because sometimes we would want an RzILOpBitvector back when we ask for a status reg bit, so this returns us an RzILOpBitvector instead of the RzILOpBool returned when using VARG

Parameters
bitThe status register bit global variable name
Returns
RzILOpBitVector* Zero extended bitvector value

Definition at line 122 of file sh_il.c.

122  {
123  return sh_il_bool_to_bv(VARG(bit));
124 }
bit
RzCryptoSelector bit
Definition: crypto.c:16

References bit, sh_il_bool_to_bv(), and VARG.

Referenced by sh_il_addc(), sh_il_get_status_reg(), sh_il_movt(), sh_il_negc(), and sh_il_subc().

◆ sh_il_initialize_privilege()

static RzILOpEffect* sh_il_initialize_privilege ( )
static

Set the value of the local variable "_priv" This exists so that the privilege mode IL doesn't have to be duplicated everywhere, instead one can directly use the local variable.

Returns
RzILOpEffect*

Definition at line 192 of file sh_il.c.

192  {
193  return SETL("_priv", AND(VARG(SH_SR_D), VARG(SH_SR_R)));
194 }
AND
#define AND
Definition: ansidecl.h:254

References AND, SETL, SH_SR_D, SH_SR_R, and VARG.

Referenced by rz_sh_il_opcode().

◆ sh_il_invalid()

static RzILOpEffect* sh_il_invalid ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

Unknown instruction

Definition at line 619 of file sh_il.c.

619  {
620  return NULL;
621 }

References NULL.

◆ sh_il_is_add_carry()

static RzILOpBool* sh_il_is_add_carry ( RZ_OWN RzILOpPure *  res,
RZ_OWN RzILOpPure *  x,
RZ_OWN RzILOpPure *  y 
)
static

Check if there was a carry in the addition of x and y to get res Here res = x + y (+ 1, optional) This function can also be used of there was a carry bit added as well.

Pass in local variables to this function because otherwise the DUPs inside it will lead to an unnecessarily long IL

Parameters
res
x
y
Returns
RzILOpBool* IL_TRUE if carry during addition ; IL_FALSE otherwise

Definition at line 501 of file sh_il.c.

501  {
502  // res = x + y
503  RzILOpBool *xmsb = MSB(x);
504  RzILOpBool *ymsb = MSB(y);
505  RzILOpBool *resmsb = MSB(res);
506 
507  // x & y
508  RzILOpBool *xy = AND(xmsb, ymsb);
509  RzILOpBool *nres = INV(resmsb);
510 
511  // !res & y
512  RzILOpBool *ry = AND(nres, DUP(ymsb));
513  // x & !res
514  RzILOpBool *xr = AND(DUP(xmsb), DUP(nres));
515 
516  // bit = xy | ry | xr
517  RzILOpBool * or = OR(xy, ry);
518  or = OR(or, xr);
519 
520  return or ;
521 }
xr
#define xr(subject)
Definition: analysis_8051.c:387
x
int x
Definition: mipsasm.c:20
INV
#define INV(x)
Definition: rz_il_opbuilder_begin.h:54
DUP
@ DUP
Definition: packet.c:12

References AND, DUP, INV, MSB, OR, x, and xr.

Referenced by sh_il_addc().

◆ sh_il_is_add_overflow()

static RzILOpBool* sh_il_is_add_overflow ( RZ_OWN RzILOpPure *  res,
RZ_OWN RzILOpPure *  x,
RZ_OWN RzILOpPure *  y 
)
static

Check if there was a overflow in the addition of x and y to get res Here res = x + y.

Pass in local variables to this function because otherwise the DUPs inside it will lead to an unnecessarily long IL

Parameters
res
x
y
Returns
RzILOpBool* IL_TRUE if overflow during addition ; IL_FALSE otherwise

Definition at line 570 of file sh_il.c.

570  {
571  // res = x + y
572  RzILOpBool *xmsb = MSB(x);
573  RzILOpBool *ymsb = MSB(y);
574  RzILOpBool *resmsb = MSB(res);
575 
576  // !res & x & y
577  RzILOpBool *nrxy = AND(AND(INV(resmsb), xmsb), ymsb);
578  // res & !x & !y
579  RzILOpBool *rnxny = AND(AND(DUP(resmsb), INV(DUP(xmsb))), INV(DUP(ymsb)));
580  // or = nrxy | rnxny
581  RzILOpBool * or = OR(nrxy, rnxny);
582 
583  return or ;
584 }

References AND, DUP, INV, MSB, OR, and x.

Referenced by sh_il_addv().

◆ sh_il_is_sub_borrow()

static RzILOpBool* sh_il_is_sub_borrow ( RZ_OWN RzILOpPure *  res,
RZ_OWN RzILOpPure *  x,
RZ_OWN RzILOpPure *  y 
)
static

Check if there was a borrow in the subtraction of x and y to get res Here res = x - y (- 1, optional) This function can also be used of there was a borrow bit added as well.

Pass in local variables to this function because otherwise the DUPs inside it will lead to an unnecessarily long IL

Parameters
res
x
y
Returns
RzILOpBool* IL_TRUE if borrow during subtraction ; IL_FALSE otherwise

Definition at line 536 of file sh_il.c.

536  {
537  // res = x - y
538  RzILOpBool *xmsb = MSB(x);
539  RzILOpBool *ymsb = MSB(y);
540  RzILOpBool *resmsb = MSB(res);
541 
542  // !x & y
543  RzILOpBool *nx = INV(xmsb);
544  RzILOpBool *nxy = AND(nx, ymsb);
545 
546  // y & res
547  RzILOpBool *rny = AND(DUP(ymsb), resmsb);
548  // res & !x
549  RzILOpBool *rnx = AND(DUP(resmsb), DUP(nx));
550 
551  // bit = nxy | rny | rnx
552  RzILOpBool * or = OR(nxy, rny);
553  or = OR(or, rnx);
554 
555  return or ;
556 }

References AND, DUP, INV, MSB, OR, and x.

Referenced by sh_il_negc(), and sh_il_subc().

◆ sh_il_is_sub_underflow()

static RzILOpBool* sh_il_is_sub_underflow ( RZ_OWN RzILOpPure *  res,
RZ_OWN RzILOpPure *  x,
RZ_OWN RzILOpPure *  y 
)
static

Check if there was a underflow in the subtraction of x and y to get res Here res = x - y.

Pass in local variables to this function because otherwise the DUPs inside it will lead to an unnecessarily long IL

Parameters
res
x
y
Returns
RzILOpBool* IL_TRUE if underflow during subtraction ; IL_FALSE otherwise

Definition at line 598 of file sh_il.c.

598  {
599  // res = x - y
600  RzILOpBool *xmsb = MSB(x);
601  RzILOpBool *ymsb = MSB(y);
602  RzILOpBool *resmsb = MSB(res);
603 
604  // !res & x & !y
605  RzILOpBool *nrxny = AND(AND(INV(resmsb), xmsb), INV(ymsb));
606  // res & !x & y
607  RzILOpBool *rnxy = AND(AND(DUP(resmsb), INV(DUP(xmsb))), DUP(ymsb));
608  // or = nrxny | rnxy
609  RzILOpBool * or = OR(nrxny, rnxy);
610 
611  return or ;
612 }

References AND, DUP, INV, MSB, OR, and x.

Referenced by sh_il_subv().

◆ sh_il_jmp()

static RzILOpEffect* sh_il_jmp ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

JMP @Rn Rn -> PC ; delayed branch 0100nnnn00101011 TODO: Implement delayed branch

Definition at line 1437 of file sh_il.c.

1437  {
1438  return JMP(sh_il_get_effective_addr_param(0));
1439 }

References JMP, and sh_il_get_effective_addr_param.

◆ sh_il_jsr()

static RzILOpEffect* sh_il_jsr ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

JSR @Rn PC + 4 -> PR ; Rn -> PC ; delayed branch 0100nnnn00001011 TODO: Implement delayed branch

Definition at line 1447 of file sh_il.c.

1447  {
1448  return SEQ2(SETG("pr", ADD(SH_U_ADDR(pc), SH_U_ADDR(4))), JMP(sh_il_get_effective_addr_param(0)));
1449 }

References ADD, JMP, pc, SEQ2, SETG, sh_il_get_effective_addr_param, and SH_U_ADDR.

◆ sh_il_ldc()

static RzILOpEffect* sh_il_ldc ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

LDC Rm, REG REG := SR/GBR/VBR/SSR/SPC/DBR/Rn_BANK Rm -> REG PRIVILEGED (Only GBR is not privileged)

LDC.L @Rm+, REG REG := SR/GBR/VBR/SSR/SPC/DBR/Rn_BANK (Rm) -> REG ; Rm + 4 -> Rm PRIVILEGED (Only GBR is not privileged)

Definition at line 1499 of file sh_il.c.

1499  {
1500  /* We won't be using banked registers for these instructions (except for unprivileged GBR) */
1501  // TODO: Check what the correct implementation is
1502  ctx->use_banked = false;
1503  if (op->param[1].param[0] == SH_REG_IND_GBR) {
1504  ctx->use_banked = true;
1505  }
1506 
1507  RzILOpEffect *eff = NULL;
1508  if (op->scaling == SH_SCALING_INVALID) {
1509  if (sh_valid_gpr(op->param[1].param[0])) {
1510  eff = SETG(sh_get_banked_reg(op->param[1].param[0], 1), sh_il_get_pure_param(0));
1511  } else {
1512  eff = sh_il_set_pure_param(1, sh_il_get_pure_param(0));
1513  }
1514  } else if (op->scaling == SH_SCALING_L) {
1515  SHParamHelper rm = sh_il_get_param(op->param[0], op->scaling);
1516  if (sh_valid_gpr(op->param[1].param[0])) {
1517  eff = SEQ2(SETG(sh_get_banked_reg(op->param[1].param[0], 1), rm.pure), rm.post);
1518  } else {
1519  eff = SEQ2(sh_il_set_pure_param(1, rm.pure), rm.post);
1520  }
1521  }
1522 
1523  if (op->param[1].param[0] != SH_REG_IND_GBR) {
1524  eff = BRANCH(sh_il_get_privilege(), eff, EMPTY());
1525  }
1526  return eff;
1527 }
EMPTY
#define EMPTY()
Definition: rz_il_opbuilder_begin.h:115
SH_REG_IND_GBR
@ SH_REG_IND_GBR
Definition: disassembler.h:92
sh_valid_gpr
static bool sh_valid_gpr(ut16 reg)
Definition: sh_il.c:44
sh_il_get_param
#define sh_il_get_param(x, y)
Definition: sh_il.c:394

References BRANCH, EMPTY, NULL, sh_param_helper_t::post, sh_param_helper_t::pure, SEQ2, SETG, sh_get_banked_reg(), sh_il_get_param, sh_il_get_privilege, sh_il_get_pure_param, sh_il_set_pure_param, SH_REG_IND_GBR, SH_SCALING_INVALID, SH_SCALING_L, and sh_valid_gpr().

◆ sh_il_lds()

static RzILOpEffect* sh_il_lds ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

LDS Rm, REG REG := MACH/MACL/PR Rm -> REG

LDS.L @Rm+, REG REG := MACH/MACL/PR (Rm) -> REG ; Rm + 4 -> Rm

Definition at line 1538 of file sh_il.c.

1538  {
1539  if (op->scaling == SH_SCALING_INVALID) {
1540  return sh_il_set_pure_param(1, sh_il_get_pure_param(0));
1541  } else if (op->scaling == SH_SCALING_L) {
1542  SHParamHelper rm = sh_il_get_param(op->param[0], op->scaling);
1543  return SEQ2(sh_il_set_pure_param(1, rm.pure), rm.post);
1544  }
1545  return NOP();
1546 }

References NOP, sh_param_helper_t::post, sh_param_helper_t::pure, SEQ2, sh_il_get_param, sh_il_get_pure_param, sh_il_set_pure_param, SH_SCALING_INVALID, and SH_SCALING_L.

◆ sh_il_mac()

static RzILOpEffect* sh_il_mac ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

MAC.L @Rm+, @Rn+ Rn * Rm + MAC -> MAC (Signed) (32 * 32 + 64 -> 64 bits) Rn + 4 -> Rn ; Rm + 4 -> Rm 0000nnnnmmmm1111

When S bit is enabled, the MAC addition is a saturation operation of 48 bits So only the lower 48 bits of result and MAC are considered

MAC.W @Rm+, @Rn+ Rn * Rm + MAC -> MAC (Signed) (16 * 16 + 64 -> 64 bits) Rn + 2 -> Rn ; Rm + 2 -> Rm 0000nnnnmmmm1111

When S bit is enabled, the MAC addition is a saturation operation of 32 bits So only the lower 32 bits of result and MAC are considered (which is basically MACL register)

Definition at line 950 of file sh_il.c.

950  {
951  SHParamHelper shp_rm = sh_il_get_param(op->param[0], op->scaling);
952  SHParamHelper shp_rn = sh_il_get_param(op->param[1], op->scaling);
953  RzILOpEffect *eff = NULL;
954 
955  if (op->scaling == SH_SCALING_L) {
956  RzILOpEffect *mac = SETL("mac", LOGOR(SHIFTL0((UNSIGNED(2 * SH_REG_SIZE, VARG("mach"))), SH_U_REG(SH_REG_SIZE)), UNSIGNED(2 * SH_REG_SIZE, VARG("macl"))));
957  RzILOpEffect *rm = SETL("rm", shp_rm.pure);
958  RzILOpEffect *rn = SETL("rn", shp_rn.pure);
959  eff = SEQ2(rm, rn);
960 
961  RzILOpEffect *mul = SETL("mul", MUL(SIGNED(2 * SH_REG_SIZE, VARL("rm")), SIGNED(2 * SH_REG_SIZE, VARL("rn"))));
962  RzILOpEffect *add = SETL("add", ADD(VARL("mul"), VARL("mac")));
963  RzILOpPure *lower_bits = UNSIGNED(SH_REG_SIZE, LOGAND(VARL("add"), UN(2 * SH_REG_SIZE, 0xffffffff)));
964  RzILOpEffect *higher_bits = SETL("high", UNSIGNED(SH_REG_SIZE, SHIFTR0(VARL("add"), SH_U_REG(SH_REG_SIZE))));
965 
966  eff = SEQ7(eff, mac, mul, add, SETG("macl", lower_bits), higher_bits, BRANCH(VARG(SH_SR_S), SETG("mach", LOGAND(VARL("high"), SH_U_REG(0xffff))), SETG("mach", VARL("high"))));
967  } else if (op->scaling == SH_SCALING_W) {
968  RzILOpEffect *mac = SETL("mac", LOGOR(SHIFTL0((UNSIGNED(2 * SH_REG_SIZE, VARG("mach"))), SH_U_REG(SH_REG_SIZE)), UNSIGNED(2 * SH_REG_SIZE, VARG("macl"))));
969  RzILOpEffect *rm = SETL("rm", shp_rm.pure);
970  RzILOpEffect *rn = SETL("rn", shp_rn.pure);
971  eff = SEQ2(rm, rn);
972 
973  RzILOpEffect *mul = SETL("mul", UNSIGNED(2 * SH_REG_SIZE, MUL(SIGNED(SH_REG_SIZE, VARL("rm")), SIGNED(SH_REG_SIZE, VARL("rn")))));
974  RzILOpEffect *add = SETL("add", ADD(VARL("mul"), VARL("mac")));
975  RzILOpEffect *lower_bits = SETL("low", UNSIGNED(SH_REG_SIZE, LOGAND(VARL("add"), UN(2 * SH_REG_SIZE, 0xffffffff))));
976  RzILOpPure *higher_bits = UNSIGNED(SH_REG_SIZE, SHIFTR0(VARL("add"), SH_U_REG(SH_REG_SIZE)));
977 
978  eff = SEQ6(eff, mac, mul, add, lower_bits, BRANCH(VARG(SH_SR_S), SETG("macl", VARL("low")), SEQ2(SETG("macl", VARL("low")), SETG("mach", higher_bits))));
979  }
980 
981  eff = SEQ3(eff, shp_rn.post, shp_rm.post);
982  return eff;
983 }
mul
static RzILOpEffect * mul(cs_insn *insn, bool is_thumb)
Definition: arm_il32.c:539
SEQ7
#define SEQ7(e0, e1, e2, e3, e4, e5, e6)
Definition: rz_il_opbuilder_begin.h:111
SEQ6
#define SEQ6(e0, e1, e2, e3, e4, e5)
Definition: rz_il_opbuilder_begin.h:110
SH_SCALING_W
@ SH_SCALING_W
word
Definition: disassembler.h:38
add
static int add(char *argv[])
Definition: ziptool.c:84

References ADD, add(), BRANCH, LOGAND, LOGOR, mul(), MUL, NULL, sh_param_helper_t::post, sh_param_helper_t::pure, SEQ2, SEQ3, SEQ6, SEQ7, SETG, SETL, sh_il_get_param, SH_REG_SIZE, SH_SCALING_L, SH_SCALING_W, SH_SR_S, SH_U_REG, SHIFTL0, SHIFTR0, SIGNED, UN, UNSIGNED, VARG, and VARL.

◆ sh_il_mov()

static RzILOpEffect* sh_il_mov ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

MOV family instructions

Definition at line 626 of file sh_il.c.

626  {
627  SHParamHelper shp = sh_il_get_param(op->param[0], op->scaling);
628  return sh_apply_effects(sh_il_set_pure_param(1, shp.pure), shp.pre, shp.post);
629 }

References sh_param_helper_t::post, sh_param_helper_t::pre, sh_param_helper_t::pure, sh_apply_effects(), sh_il_get_param, and sh_il_set_pure_param.

◆ sh_il_movca()

static RzILOpEffect* sh_il_movca ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

MOVCA.L R0, @Rn R0 -> (Rn) (without fetching cache block) 0000nnnn11000011

Definition at line 1553 of file sh_il.c.

1553  {
1554  return sh_il_set_pure_param(1, sh_il_get_pure_param(0));
1555 }

References sh_il_get_pure_param, and sh_il_set_pure_param.

◆ sh_il_movt()

static RzILOpEffect* sh_il_movt ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

MOVT Rn T -> Rn 0000nnnn00101001

Definition at line 636 of file sh_il.c.

636  {
637  return sh_il_set_pure_param(0, UNSIGNED(SH_REG_SIZE, sh_il_get_status_reg_bit(SH_SR_T)));
638 }

References sh_il_get_status_reg_bit(), sh_il_set_pure_param, SH_REG_SIZE, SH_SR_T, and UNSIGNED.

◆ sh_il_mul()

static RzILOpEffect* sh_il_mul ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

MUL.L Rm, Rn Rn * Rm -> MACL (32 * 32 -> 32 bits) 0000nnnnmmmm0111

Definition at line 990 of file sh_il.c.

990  {
991  return SETG("macl", MUL(sh_il_get_pure_param(0), sh_il_get_pure_param(1)));
992 }

References MUL, SETG, and sh_il_get_pure_param.

◆ sh_il_muls()

static RzILOpEffect* sh_il_muls ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

MULS.W Rm, Rn Rn * Rm -> MACL (Signed) (16 * 16 -> 32 bits) 0010nnnnmmmm1111

Definition at line 999 of file sh_il.c.

999  {
1000  RzILOpEffect *rm = SETL("rm", sh_il_get_pure_param(0));
1001  RzILOpEffect *rn = SETL("rn", sh_il_get_pure_param(1));
1002  RzILOpPure *m = SIGNED(SH_REG_SIZE, VARL("rm"));
1003  RzILOpPure *n = SIGNED(SH_REG_SIZE, VARL("rn"));
1004  return SEQ3(rm, rn, SETG("macl", MUL(m, n)));
1005 }
n
int n
Definition: mipsasm.c:19

References regress::m, MUL, n, SEQ3, SETG, SETL, sh_il_get_pure_param, SH_REG_SIZE, SIGNED, and VARL.

◆ sh_il_mulu()

static RzILOpEffect* sh_il_mulu ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

MULU.W Rm, Rn Rn * Rm -> MACL (Unsigned) (16 * 16 -> 32 bits) 0010nnnnmmmm1110

Definition at line 1012 of file sh_il.c.

1012  {
1013  RzILOpPure *m = UNSIGNED(SH_REG_SIZE, sh_il_get_pure_param(0));
1014  RzILOpPure *n = UNSIGNED(SH_REG_SIZE, sh_il_get_pure_param(1));
1015  return SETG("macl", MUL(m, n));
1016 }

References regress::m, MUL, n, SETG, sh_il_get_pure_param, SH_REG_SIZE, and UNSIGNED.

◆ sh_il_neg()

static RzILOpEffect* sh_il_neg ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

NEG Rm, Rn 0 - Rm -> Rn 0110nnnnmmmm1011

Definition at line 1023 of file sh_il.c.

1023  {
1024  RzILOpPure *sub = SUB(SH_U_REG(0), sh_il_get_pure_param(0));
1025  return sh_il_set_pure_param(1, sub);
1026 }

References sh_il_get_pure_param, sh_il_set_pure_param, SH_U_REG, and SUB.

◆ sh_il_negc()

static RzILOpEffect* sh_il_negc ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

NEGC Rm, Rn 0 - Rm - T -> Rn ; borrow -> T 0110nnnnmmmm1010

Definition at line 1033 of file sh_il.c.

1033  {
1034  RzILOpPure *sub = SUB(SH_U_REG(0), sh_il_get_pure_param(0));
1035  RzILOpEffect *subvar = SETL("sub", SUB(sub, sh_il_get_status_reg_bit(SH_SR_T)));
1036  return SEQ3(subvar, sh_il_set_pure_param(1, VARL("sub")), SETG(SH_SR_T, sh_il_is_sub_borrow(VARL("sub"), SH_U_REG(0), sh_il_get_pure_param(0))));
1037 }
subvar
static bool subvar(RzParse *p, RzAnalysisFunction *f, RzAnalysisOp *op, char *data, char *str, int len)
Definition: parse_arm_pseudo.c:256
sh_il_is_sub_borrow
static RzILOpBool * sh_il_is_sub_borrow(RZ_OWN RzILOpPure *res, RZ_OWN RzILOpPure *x, RZ_OWN RzILOpPure *y)
Check if there was a borrow in the subtraction of x and y to get res Here res = x - y (- 1,...
Definition: sh_il.c:536

References SEQ3, SETG, SETL, sh_il_get_pure_param, sh_il_get_status_reg_bit(), sh_il_is_sub_borrow(), sh_il_set_pure_param, SH_SR_T, SH_U_REG, SUB, subvar(), and VARL.

◆ sh_il_nop()

static RzILOpEffect* sh_il_nop ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

NOP No operation 0000000000001001

Definition at line 1562 of file sh_il.c.

1562  {
1563  return NOP();
1564 }

References NOP.

◆ sh_il_not()

static RzILOpEffect* sh_il_not ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

NOT Rm, Rn ~Rm -> Rn 0110nnnnmmmm0111

Definition at line 1099 of file sh_il.c.

1099  {
1100  return sh_il_set_pure_param(1, LOGNOT(sh_il_get_pure_param(0)));
1101 }
LOGNOT
#define LOGNOT(x)
Definition: rz_il_opbuilder_begin.h:77

References LOGNOT, sh_il_get_pure_param, and sh_il_set_pure_param.

◆ sh_il_or()

static RzILOpEffect* sh_il_or ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

OR Rm, Rn Rn | Rm -> Rn 0010nnnnmmmm1011

OR imm, R0 R0 | imm -> R0 11001011iiiiiiii

OR.B imm, @(R0, GBR) (R0 + GBR) | imm -> (R0 + GBR) 11001111iiiiiiii

Definition at line 1116 of file sh_il.c.

1116  {
1117  return sh_il_set_pure_param(1, LOGOR(sh_il_get_pure_param(0), sh_il_get_pure_param(1)));
1118 }

References LOGOR, sh_il_get_pure_param, and sh_il_set_pure_param.

◆ sh_il_rotcl()

static RzILOpEffect* sh_il_rotcl ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

ROTCL Rn T <- Rn <- T 0100nnnn00100100

Definition at line 1197 of file sh_il.c.

1197  {
1198  RzILOpEffect *msb = SETL("msb_", MSB(sh_il_get_pure_param(0)));
1199  RzILOpEffect *shl = SETL("shl_", SHIFTL0(sh_il_get_pure_param(0), SH_U_REG(1)));
1200  RzILOpPure *lsb = ITE(VARG(SH_SR_T), LOGOR(VARL("shl_"), SH_U_REG(1)), VARL("shl_"));
1201  RzILOpEffect *tbit = SETG(SH_SR_T, VARL("msb_"));
1202  return SEQ4(msb, shl, sh_il_set_pure_param(0, lsb), tbit);
1203 }

References ITE, LOGOR, MSB, SEQ4, SETG, SETL, sh_il_get_pure_param, sh_il_set_pure_param, SH_SR_T, SH_U_REG, SHIFTL0, VARG, and VARL.

◆ sh_il_rotcr()

static RzILOpEffect* sh_il_rotcr ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

ROTCR Rn T -> Rn -> T 0100nnnn00100101

Definition at line 1210 of file sh_il.c.

1210  {
1211  RzILOpEffect *lsb = SETL("lsb_", LSB(sh_il_get_pure_param(0)));
1212  RzILOpEffect *shr = SETL("shr_", SHIFTR0(sh_il_get_pure_param(0), SH_U_REG(1)));
1213  RzILOpPure *msb = ITE(VARG(SH_SR_T), LOGOR(VARL("shr_"), SH_U_REG(0x80000000)), VARL("shr_"));
1214  RzILOpEffect *tbit = SETG(SH_SR_T, VARL("lsb_"));
1215  return SEQ4(lsb, shr, sh_il_set_pure_param(0, msb), tbit);
1216 }
LSB
#define LSB(x)
Definition: rz_il_opbuilder_begin.h:83

References ITE, LOGOR, LSB, SEQ4, SETG, SETL, sh_il_get_pure_param, sh_il_set_pure_param, SH_SR_T, SH_U_REG, SHIFTR0, VARG, and VARL.

◆ sh_il_rotl()

static RzILOpEffect* sh_il_rotl ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

ROTL Rn T <- Rn <- MSB 0100nnnn00000100

Definition at line 1171 of file sh_il.c.

1171  {
1172  RzILOpEffect *msb = SETL("msb_", MSB(sh_il_get_pure_param(0)));
1173  RzILOpEffect *tbit = SETG(SH_SR_T, VARL("msb_"));
1174  RzILOpEffect *shl = SETL("shl_", SHIFTL0(sh_il_get_pure_param(0), SH_U_REG(1)));
1175  RzILOpPure *lsb = ITE(VARL("msb_"), LOGOR(VARL("shl_"), SH_U_REG(1)), VARL("shl_"));
1176  return SEQ4(msb, tbit, shl, sh_il_set_pure_param(0, lsb));
1177 }

References ITE, LOGOR, MSB, SEQ4, SETG, SETL, sh_il_get_pure_param, sh_il_set_pure_param, SH_SR_T, SH_U_REG, SHIFTL0, and VARL.

◆ sh_il_rotr()

static RzILOpEffect* sh_il_rotr ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

ROTR Rn LSB -> Rn -> T 0100nnnn00000101

Definition at line 1184 of file sh_il.c.

1184  {
1185  RzILOpEffect *lsb = SETL("lsb_", LSB(sh_il_get_pure_param(0)));
1186  RzILOpEffect *tbit = SETG(SH_SR_T, VARL("lsb_"));
1187  RzILOpEffect *shr = SETL("shr_", SHIFTR0(sh_il_get_pure_param(0), SH_U_REG(1)));
1188  RzILOpPure *msb = ITE(VARL("lsb_"), LOGOR(VARL("shr_"), SH_U_REG(0x80000000)), VARL("shr_"));
1189  return SEQ4(lsb, tbit, shr, sh_il_set_pure_param(0, msb));
1190 }

References ITE, LOGOR, LSB, SEQ4, SETG, SETL, sh_il_get_pure_param, sh_il_set_pure_param, SH_SR_T, SH_U_REG, SHIFTR0, and VARL.

◆ sh_il_rte()

static RzILOpEffect* sh_il_rte ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

RTE SSR -> SR ; SPC -> PC ; delayed branch 0000000000101011 PRIVILEGED TODO: Implement delayed branch

Definition at line 1573 of file sh_il.c.

1573  {
1574  return BRANCH(sh_il_get_privilege(), SEQ2(sh_il_set_status_reg(VARG("ssr")), JMP(VARG("spc"))), EMPTY());
1575 }
sh_il_set_status_reg
static RzILOpEffect * sh_il_set_status_reg(RZ_OWN RzILOpPure *val)
Set the value of the status register (sr) to val by setting the values of the individual status regis...
Definition: sh_il.c:161

References BRANCH, EMPTY, JMP, SEQ2, sh_il_get_privilege, sh_il_set_status_reg(), and VARG.

◆ sh_il_rts()

static RzILOpEffect* sh_il_rts ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

RTS PR -> PC ; delayed branch 0000000000001011 TODO: Implement delayed branch

Definition at line 1457 of file sh_il.c.

1457  {
1458  return JMP(VARG("pr"));
1459 }

References JMP, and VARG.

◆ sh_il_set_param_pc_ctx()

static RzILOpEffect* sh_il_set_param_pc_ctx ( SHParam  param,
RZ_OWN RzILOpPure *  val,
SHScaling  scaling,
ut64  pc,
SHILContext *  ctx 
)
static

Set the value of the param at scaling to val This function is smart enough to also apply any effects corresponding to the param.

Parameters
param
val
scaling
pcProgram counter
ctxSHILContext instance
Returns
RzILOpEffect*

Definition at line 440 of file sh_il.c.

440  {
441  RzILOpEffect *ret = NULL, *pre = NULL, *post = NULL;
442  switch (param.mode) {
443  case SH_REG_DIRECT:
444  if (scaling == SH_SCALING_INVALID || scaling == SH_SCALING_L) {
445  ret = sh_il_set_reg(param.param[0], val);
446  } else {
447  /* We don't need to worry about sizes not matching up when calling `sh_il_signed` two times in an effect.
448  This is because within an effect, the scaling will stay the same, so all the time `sh_il_signed` is called,
449  it will be setting the local variables "_sign" and "_temp" to the same bitvector size.
450  Thus, there will be no IL validation errors. */
451  RzILOpEffect *cast = sh_il_signed(SH_REG_SIZE, val, "_sign", "_temp");
452  ret = SEQ2(cast, sh_il_set_reg(param.param[0], VARL("_sign")));
453  }
454  break;
455  case SH_REG_INDIRECT:
456  case SH_REG_INDIRECT_I:
457  case SH_REG_INDIRECT_D:
458  case SH_REG_INDIRECT_DISP:
459  case SH_REG_INDIRECT_INDEXED:
460  case SH_GBR_INDIRECT_DISP:
461  case SH_GBR_INDIRECT_INDEXED:
462  case SH_PC_RELATIVE_DISP:
463  case SH_PC_RELATIVE8:
464  case SH_PC_RELATIVE12:
465  case SH_PC_RELATIVE_REG:
466  break;
467  case SH_IMM_U:
468  case SH_IMM_S:
469  default:
470  RZ_LOG_ERROR("RzIL: SuperH: Cannot set value for addressing mode: %u\n", param.mode);
471  return NULL;
472  }
473 
474  if (!ret) {
475  SHParamHelper ret_h = sh_il_get_param(param, scaling);
476  RZ_FREE(ret_h.pure);
477  RzILOpPure *eff_addr = sh_il_get_effective_addr(param, scaling);
478  ret = STOREW(eff_addr, val);
479  pre = ret_h.pre;
480  post = ret_h.post;
481  }
482 
483  return sh_apply_effects(ret, pre, post);
484 }
cast
#define cast(x, y)
Definition: arch_53.h:166
STOREW
#define STOREW(addr, val)
Definition: rz_il_opbuilder_begin.h:97
RZ_FREE
#define RZ_FREE(x)
Definition: rz_types.h:369
sh_il_signed
RzILOpEffect * sh_il_signed(unsigned int len, RZ_OWN RzILOpPure *val, const char *cast_var, const char *temp_var)
Cast val to len bits This uses a local temp variable temp_var to store the value val and then casts t...
Definition: sh_il.c:82

References cast, sh_param_t::mode, NULL, sh_param_t::param, sh_param_helper_t::post, post(), sh_param_helper_t::pre, sh_param_helper_t::pure, RZ_FREE, RZ_LOG_ERROR, SEQ2, sh_apply_effects(), SH_GBR_INDIRECT_DISP, SH_GBR_INDIRECT_INDEXED, sh_il_get_effective_addr, sh_il_get_param, sh_il_set_reg, sh_il_signed(), SH_IMM_S, SH_IMM_U, SH_PC_RELATIVE12, SH_PC_RELATIVE8, SH_PC_RELATIVE_DISP, SH_PC_RELATIVE_REG, SH_REG_DIRECT, SH_REG_INDIRECT, SH_REG_INDIRECT_D, SH_REG_INDIRECT_DISP, SH_REG_INDIRECT_I, SH_REG_INDIRECT_INDEXED, SH_REG_SIZE, SH_SCALING_INVALID, SH_SCALING_L, STOREW, val, and VARL.

◆ sh_il_set_reg_ctx()

static RzILOpEffect* sh_il_set_reg_ctx ( ut16  reg,
RZ_OWN RzILOpPure *  val,
SHILContext *  ctx 
)
static

Set the value of the register corresponding to index reg to value val This function is smart enough to set values correctly in case of banked registers or status register.

Parameters
reg
val
ctxSHILContext instance
Returns
RzILOpEffect*

Definition at line 245 of file sh_il.c.

245  {
246  if (!sh_banked_reg(reg) || !ctx->use_banked) {
247  if (reg == SH_REG_IND_SR) {
248  return sh_il_set_status_reg(val);
249  }
250  return SETG(sh_registers[reg], val);
251  }
252 
253  return SEQ2(SETL("_regv", val), BRANCH(sh_il_get_privilege(), SETG(sh_get_banked_reg(reg, 1), VARL("_regv")), SETG(sh_get_banked_reg(reg, 0), VARL("_regv"))));
254 }

References BRANCH, reg, SEQ2, SETG, SETL, sh_banked_reg(), sh_get_banked_reg(), sh_il_get_privilege, sh_il_set_status_reg(), SH_REG_IND_SR, sh_registers, val, and VARL.

◆ sh_il_set_status_reg()

static RzILOpEffect* sh_il_set_status_reg ( RZ_OWN RzILOpPure *  val)
static

Set the value of the status register (sr) to val by setting the values of the individual status register bits.

Parameters
val
Returns
RzILOpEffect*

Definition at line 161 of file sh_il.c.

161  {
162  RzILOpEffect *sreg = SETL("_sreg", val);
163  RzILOpEffect *eff = SETG(SH_SR_T, LSB(VARL("_sreg")));
164 
165  eff = SEQ2(eff, SETL("_sreg", SHIFTR0(VARL("_sreg"), SH_U_REG(1))));
166  eff = SEQ2(eff, SETG(SH_SR_S, LSB(VARL("_sreg"))));
167  eff = SEQ2(eff, SETL("_sreg", SHIFTR0(VARL("_sreg"), SH_U_REG(3))));
168  eff = SEQ2(eff, SETG(SH_SR_I, LOGAND(UN(4, 0xf), UNSIGNED(4, VARL("_sreg")))));
169  eff = SEQ2(eff, SETL("_sreg", SHIFTR0(VARL("_sreg"), SH_U_REG(4))));
170  eff = SEQ2(eff, SETG(SH_SR_Q, LSB(VARL("_sreg"))));
171  eff = SEQ2(eff, SETL("_sreg", SHIFTR0(VARL("_sreg"), SH_U_REG(1))));
172  eff = SEQ2(eff, SETG(SH_SR_M, LSB(VARL("_sreg"))));
173  eff = SEQ2(eff, SETL("_sreg", SHIFTR0(VARL("_sreg"), SH_U_REG(6))));
174  eff = SEQ2(eff, SETG(SH_SR_F, LSB(VARL("_sreg"))));
175  eff = SEQ2(eff, SETL("_sreg", SHIFTR0(VARL("_sreg"), SH_U_REG(13))));
176  eff = SEQ2(eff, SETG(SH_SR_B, LSB(VARL("_sreg"))));
177  eff = SEQ2(eff, SETL("_sreg", SHIFTR0(VARL("_sreg"), SH_U_REG(1))));
178  eff = SEQ2(eff, SETG(SH_SR_R, LSB(VARL("_sreg"))));
179  eff = SEQ2(eff, SETL("_sreg", SHIFTR0(VARL("_sreg"), SH_U_REG(1))));
180  eff = SEQ2(eff, SETG(SH_SR_D, LSB(VARL("_sreg"))));
181 
182  return SEQ2(sreg, eff);
183 }

References LOGAND, LSB, SEQ2, SETG, SETL, SH_SR_B, SH_SR_D, SH_SR_F, SH_SR_I, SH_SR_M, SH_SR_Q, SH_SR_R, SH_SR_S, SH_SR_T, SH_U_REG, SHIFTR0, UN, UNSIGNED, val, and VARL.

Referenced by sh_il_rte(), and sh_il_set_reg_ctx().

◆ sh_il_sets()

static RzILOpEffect* sh_il_sets ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

SETS 1 -> S 0000000001011000

Definition at line 1582 of file sh_il.c.

1582  {
1583  return SETG(SH_SR_S, IL_TRUE);
1584 }
IL_TRUE
#define IL_TRUE
Definition: rz_il_opbuilder_begin.h:53

References IL_TRUE, SETG, and SH_SR_S.

◆ sh_il_sett()

static RzILOpEffect* sh_il_sett ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

SETT 1 -> T 0000000000011000

Definition at line 1591 of file sh_il.c.

1591  {
1592  return SETG(SH_SR_T, IL_TRUE);
1593 }

References IL_TRUE, SETG, and SH_SR_T.

◆ sh_il_shad()

static RzILOpEffect* sh_il_shad ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

SHAD Rm, Rn If Rn >= 0, Rn << Rm -> Rn If Rn < 0, Rn >> Rm -> [MSB -> Rn] MSB -> Rn 0100nnnnmmmm1100

Definition at line 1225 of file sh_il.c.

1225  {
1226  RzILOpEffect *shift_amount = SETL("shift_", UNSIGNED(5, sh_il_get_pure_param(0)));
1227 
1228  RzILOpPure *shl = SHIFTL0(sh_il_get_pure_param(1), VARL("shift_"));
1229  RzILOpPure *shr = SHIFTRA(sh_il_get_pure_param(1), NEG(VARL("shift_")));
1230 
1231  return SEQ2(shift_amount, BRANCH(SGE(sh_il_get_pure_param(0), SN(32, 0)), sh_il_set_pure_param(1, shl), sh_il_set_pure_param(1, shr)));
1232 }
NEG
#define NEG(x)
Definition: rz_il_opbuilder_begin.h:78
SHIFTRA
#define SHIFTRA(v, dist)
Definition: rz_il_opbuilder_begin.h:73

References BRANCH, NEG, SEQ2, SETL, SGE, sh_il_get_pure_param, sh_il_set_pure_param, SHIFTL0, SHIFTRA, SN, UNSIGNED, and VARL.

◆ sh_il_shal()

static RzILOpEffect* sh_il_shal ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

SHAL Rn T <- Rn <- 0 0100nnnn00100000

Definition at line 1239 of file sh_il.c.

1239  {
1240  RzILOpPure *msb = MSB(sh_il_get_pure_param(0));
1241  RzILOpPure *shl = SHIFTL0(sh_il_get_pure_param(0), SH_U_REG(1));
1242  return SEQ2(SETG(SH_SR_T, msb), sh_il_set_pure_param(0, shl));
1243 }

References MSB, SEQ2, SETG, sh_il_get_pure_param, sh_il_set_pure_param, SH_SR_T, SH_U_REG, and SHIFTL0.

◆ sh_il_shar()

static RzILOpEffect* sh_il_shar ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

SHAR Rn MSB -> Rn -> T 0100nnnn00100001

Definition at line 1250 of file sh_il.c.

1250  {
1251  RzILOpPure *lsb = LSB(sh_il_get_pure_param(0));
1252  RzILOpPure *shl = SHIFTRA(sh_il_get_pure_param(0), SH_U_REG(1));
1253  return SEQ2(SETG(SH_SR_T, lsb), sh_il_set_pure_param(0, shl));
1254 }

References LSB, SEQ2, SETG, sh_il_get_pure_param, sh_il_set_pure_param, SH_SR_T, SH_U_REG, and SHIFTRA.

◆ sh_il_shld()

static RzILOpEffect* sh_il_shld ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

SHLD Rm, Rn If Rn >= 0, Rn << Rm -> Rn If Rn < 0, Rn >> Rm -> [0 -> Rn] MSB -> Rn 0100nnnnmmmm1101

Definition at line 1263 of file sh_il.c.

1263  {
1264  RzILOpEffect *shift_amount = SETL("shift_", UNSIGNED(5, sh_il_get_pure_param(0)));
1265 
1266  RzILOpPure *shl = SHIFTL0(sh_il_get_pure_param(1), VARL("shift_"));
1267  RzILOpPure *shr = SHIFTR0(sh_il_get_pure_param(1), NEG(VARL("shift_")));
1268 
1269  return SEQ2(shift_amount, BRANCH(SGE(sh_il_get_pure_param(0), SN(32, 0)), sh_il_set_pure_param(1, shl), sh_il_set_pure_param(1, shr)));
1270  ;
1271 }

References BRANCH, NEG, SEQ2, SETL, SGE, sh_il_get_pure_param, sh_il_set_pure_param, SHIFTL0, SHIFTR0, SN, UNSIGNED, and VARL.

◆ sh_il_shll()

static RzILOpEffect* sh_il_shll ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

SHLL Rn T <- Rn <- 0 0100nnnn00000000

Definition at line 1278 of file sh_il.c.

1278  {
1279  RzILOpPure *msb = MSB(sh_il_get_pure_param(0));
1280  RzILOpPure *shl = SHIFTL0(sh_il_get_pure_param(0), SH_U_REG(1));
1281  return SEQ2(SETG(SH_SR_T, msb), sh_il_set_pure_param(0, shl));
1282 }

References MSB, SEQ2, SETG, sh_il_get_pure_param, sh_il_set_pure_param, SH_SR_T, SH_U_REG, and SHIFTL0.

◆ sh_il_shll16()

static RzILOpEffect* sh_il_shll16 ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

SHLL16 Rn Rn << 16 -> Rn 0100nnnn00101000

Definition at line 1336 of file sh_il.c.

1336  {
1337  return sh_il_set_pure_param(0, SHIFTL0(sh_il_get_pure_param(0), SH_U_REG(16)));
1338 }

References sh_il_get_pure_param, sh_il_set_pure_param, SH_U_REG, and SHIFTL0.

◆ sh_il_shll2()

static RzILOpEffect* sh_il_shll2 ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

SHLL2 Rn Rn << 2 -> Rn 0100nnnn00001000

Definition at line 1300 of file sh_il.c.

1300  {
1301  return sh_il_set_pure_param(0, SHIFTL0(sh_il_get_pure_param(0), SH_U_REG(2)));
1302 }

References sh_il_get_pure_param, sh_il_set_pure_param, SH_U_REG, and SHIFTL0.

◆ sh_il_shll8()

static RzILOpEffect* sh_il_shll8 ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

SHLL8 Rn Rn << 8 -> Rn 0100nnnn00011000

Definition at line 1318 of file sh_il.c.

1318  {
1319  return sh_il_set_pure_param(0, SHIFTL0(sh_il_get_pure_param(0), SH_U_REG(8)));
1320 }

References sh_il_get_pure_param, sh_il_set_pure_param, SH_U_REG, and SHIFTL0.

◆ sh_il_shlr()

static RzILOpEffect* sh_il_shlr ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

SHLR Rn 0 -> Rn -> T 0100nnnn00000001

Definition at line 1289 of file sh_il.c.

1289  {
1290  RzILOpPure *lsb = LSB(sh_il_get_pure_param(0));
1291  RzILOpPure *shr = SHIFTR0(sh_il_get_pure_param(0), SH_U_REG(1));
1292  return SEQ2(SETG(SH_SR_T, lsb), sh_il_set_pure_param(0, shr));
1293 }

References LSB, SEQ2, SETG, sh_il_get_pure_param, sh_il_set_pure_param, SH_SR_T, SH_U_REG, and SHIFTR0.

◆ sh_il_shlr16()

static RzILOpEffect* sh_il_shlr16 ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

SHLR16 Rn Rn >> 16 -> Rn 0100nnnn00101001

Definition at line 1345 of file sh_il.c.

1345  {
1346  return sh_il_set_pure_param(0, SHIFTR0(sh_il_get_pure_param(0), SH_U_REG(16)));
1347 }

References sh_il_get_pure_param, sh_il_set_pure_param, SH_U_REG, and SHIFTR0.

◆ sh_il_shlr2()

static RzILOpEffect* sh_il_shlr2 ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

SHLR2 Rn Rn >> 2 -> Rn 0100nnnn00001001

Definition at line 1309 of file sh_il.c.

1309  {
1310  return sh_il_set_pure_param(0, SHIFTR0(sh_il_get_pure_param(0), SH_U_REG(2)));
1311 }

References sh_il_get_pure_param, sh_il_set_pure_param, SH_U_REG, and SHIFTR0.

◆ sh_il_shlr8()

static RzILOpEffect* sh_il_shlr8 ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

SHLR8 Rn Rn >> 8 -> Rn 0100nnnn00011001

Definition at line 1327 of file sh_il.c.

1327  {
1328  return sh_il_set_pure_param(0, SHIFTR0(sh_il_get_pure_param(0), SH_U_REG(8)));
1329 }

References sh_il_get_pure_param, sh_il_set_pure_param, SH_U_REG, and SHIFTR0.

◆ sh_il_signed()

RzILOpEffect* sh_il_signed ( unsigned int  len,
RZ_OWN RzILOpPure *  val,
const char *  cast_var,
const char *  temp_var 
)

Cast val to len bits This uses a local temp variable temp_var to store the value val and then casts the local variable temp_var to its signed value and stores that value in the local variable cast_var.

The purpose of this function is to remove the redundant IL block introduced by SIGNED opbuilder macro (MSB of val for fill bits, and val for value), and instead use a local variable to refer to val in both the above places, making the IL dump much more concise and readable

TODO: Ideally this should be integrated in SIGNED itself (need to be clever about it though)

Parameters
len
val
cast_varCasted variable name ; Use this variable to access the casted value in the caller
temp_varTemp variable name ; Do NOT use this variable outside this function
Returns
RzILOpEffect* Effect corresponding to setting the local variables

Definition at line 82 of file sh_il.c.

82  {
83  RzILOpEffect *init = SETL(temp_var, val);
84  RzILOpPure *cast = rz_il_op_new_cast(len, MSB(VARL(temp_var)), VARL(temp_var));
85  RzILOpEffect *set = SETL(cast_var, cast);
86 
87  return SEQ2(init, set);
88 }
len
size_t len
Definition: 6502dis.c:15
rz_il_op_new_cast
RZ_API RZ_OWN RzILOpBitVector * rz_il_op_new_cast(ut32 length, RZ_NONNULL RzILOpBool *fill, RZ_NONNULL RzILOpBitVector *val)
op structure for casting bitv
Definition: il_opcodes.c:341
init
bool init
Definition: core.c:77

References cast, init, len, MSB, rz_il_op_new_cast(), SEQ2, SETL, val, and VARL.

Referenced by sh_il_set_param_pc_ctx().

◆ sh_il_sleep()

static RzILOpEffect* sh_il_sleep ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

SLEEP Sleep or standby (so effectively, just a NOP) 0000000000011011 PRIVILEGED

Definition at line 1601 of file sh_il.c.

1601  {
1602  return BRANCH(sh_il_get_privilege(), NOP(), EMPTY());
1603 }

References BRANCH, EMPTY, NOP, and sh_il_get_privilege.

◆ sh_il_stc()

static RzILOpEffect* sh_il_stc ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

STC REG, Rn REG := SR/GBR/VBR/SSR/SPC/SGR/DBR/Rn_BANK REG -> Rn PRIVILEGED (Only GBR is not privileged)

STC.L REG, -Rn REG := SR/GBR/VBR/SSR/SPC/SGR/DBR/Rn_BANK Rn - 4 -> Rn ; REG -> (Rn) PRIVILEGED (Only GBR is not privileged)

Definition at line 1616 of file sh_il.c.

1616  {
1617  /* We won't be using banked registers for these instructions (except for unprivileged GBR) */
1618  // TODO: Check what the correct implementation is
1619  ctx->use_banked = false;
1620  if (op->param[0].param[0] == SH_REG_IND_GBR) {
1621  ctx->use_banked = true;
1622  }
1623 
1624  RzILOpEffect *eff = NULL;
1625  if (sh_valid_gpr(op->param[0].param[0])) { // REG = Rn_BANK
1626  eff = sh_il_set_pure_param(1, VARG(sh_get_banked_reg(op->param[0].param[0], 1)));
1627  } else {
1628  eff = sh_il_set_pure_param(1, sh_il_get_pure_param(0));
1629  }
1630  if (op->param[0].param[0] != SH_REG_IND_GBR) {
1631  eff = BRANCH(sh_il_get_privilege(), eff, EMPTY());
1632  }
1633  return eff;
1634 }

References BRANCH, EMPTY, NULL, sh_get_banked_reg(), sh_il_get_privilege, sh_il_get_pure_param, sh_il_set_pure_param, SH_REG_IND_GBR, sh_valid_gpr(), and VARG.

◆ sh_il_sts()

static RzILOpEffect* sh_il_sts ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

STS REG, Rn REG := MACH/MACL/PR REG -> Rn

STS.L REG, -Rn REG := MACH/MACL/PR Rn + 4 -> Rn ; REG -> (Rn)

Definition at line 1645 of file sh_il.c.

1645  {
1646  return sh_il_set_pure_param(1, sh_il_get_pure_param(0));
1647 }

References sh_il_get_pure_param, and sh_il_set_pure_param.

◆ sh_il_sub()

static RzILOpEffect* sh_il_sub ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

SUB Rm, Rn Rn - Rm -> Rn 0011nnnnmmmm1000

Definition at line 1044 of file sh_il.c.

1044  {
1045  return sh_il_set_pure_param(1, SUB(sh_il_get_pure_param(1), sh_il_get_pure_param(0)));
1046 }

References sh_il_get_pure_param, sh_il_set_pure_param, and SUB.

◆ sh_il_subc()

static RzILOpEffect* sh_il_subc ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

SUBC Rm, Rn Rn - Rm - T -> Rn ; borrow -> T 0011nnnnmmmm1010

Definition at line 1053 of file sh_il.c.

1053  {
1054  RzILOpPure *dif = SUB(sh_il_get_pure_param(1), sh_il_get_pure_param(0));
1055  dif = SUB(dif, sh_il_get_status_reg_bit(SH_SR_T));
1056  RzILOpEffect *local_dif = SETL("dif", dif);
1057 
1058  RzILOpEffect *ret = sh_il_set_pure_param(1, VARL("dif"));
1059  RzILOpEffect *tbit = SETG(SH_SR_T, sh_il_is_sub_borrow(VARL("dif"), sh_il_get_pure_param(0), sh_il_get_pure_param(1)));
1060  return SEQ3(local_dif, ret, tbit);
1061 }

References SEQ3, SETG, SETL, sh_il_get_pure_param, sh_il_get_status_reg_bit(), sh_il_is_sub_borrow(), sh_il_set_pure_param, SH_SR_T, SUB, and VARL.

◆ sh_il_subv()

static RzILOpEffect* sh_il_subv ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

SUBV Rm, Rn Rn - Rm -> Rn ; underflow -> T 0011nnnnmmmm1011

Definition at line 1068 of file sh_il.c.

1068  {
1069  RzILOpPure *dif = SUB(sh_il_get_pure_param(1), sh_il_get_pure_param(0));
1070  RzILOpEffect *local_dif = SETL("dif", dif);
1071 
1072  RzILOpEffect *ret = sh_il_set_pure_param(1, VARL("dif"));
1073  RzILOpEffect *tbit = SETG(SH_SR_T, sh_il_is_sub_underflow(VARL("dif"), sh_il_get_pure_param(0), sh_il_get_pure_param(1)));
1074  return SEQ3(local_dif, ret, tbit);
1075 }
sh_il_is_sub_underflow
static RzILOpBool * sh_il_is_sub_underflow(RZ_OWN RzILOpPure *res, RZ_OWN RzILOpPure *x, RZ_OWN RzILOpPure *y)
Check if there was a underflow in the subtraction of x and y to get res Here res = x - y.
Definition: sh_il.c:598

References SEQ3, SETG, SETL, sh_il_get_pure_param, sh_il_is_sub_underflow(), sh_il_set_pure_param, SH_SR_T, SUB, and VARL.

◆ sh_il_swap()

static RzILOpEffect* sh_il_swap ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

SWAP.B Rm, Rn Rm -> swap lower 2 bytes -> REG 0110nnnnmmmm1000

SWAP.W Rm, Rn Rm -> swap upper/lower words -> Rn 0110nnnnmmmm1001

Definition at line 649 of file sh_il.c.

649  {
650  /* We won't be using `sh_il_{get,set}_param_pure`, because it will cast the pure value to the scaling size,
651  but we want the whole register, which is why we need to call `sh_il_{get,set}_param directly` */
652  if (op->scaling == SH_SCALING_B) {
653  // swap lower two bytes
654  RzILOpPure *lower_byte = LOGAND(sh_il_get_param(op->param[0], SH_SCALING_L).pure, SH_U_REG(0xff));
655  RzILOpPure *new_lower_byte = LOGAND(SHIFTR0(sh_il_get_param(op->param[0], SH_SCALING_L).pure, SH_U_REG(BITS_PER_BYTE)), SH_U_REG(0xff));
656  RzILOpPure *new_upper_byte = SHIFTL0(lower_byte, SH_U_REG(BITS_PER_BYTE));
657  RzILOpPure *upper_word = LOGAND(sh_il_get_param(op->param[0], SH_SCALING_L).pure, SH_U_REG(0xffff0000));
658  return sh_il_set_param(op->param[1], LOGOR(upper_word, LOGOR(new_upper_byte, new_lower_byte)), SH_SCALING_L);
659  } else if (op->scaling == SH_SCALING_W) {
660  // swap upper and lower words and store in dst
661  RzILOpPure *high = SHIFTL0(sh_il_get_param(op->param[0], SH_SCALING_L).pure, SH_U_REG(BITS_PER_BYTE * 2));
662  RzILOpPure *low = SHIFTR0(sh_il_get_param(op->param[0], SH_SCALING_L).pure, SH_U_REG(BITS_PER_BYTE * 2));
663  return sh_il_set_param(op->param[1], LOGOR(high, low), SH_SCALING_L);
664  }
665 
666  return NULL;
667 }
SH_SCALING_B
@ SH_SCALING_B
byte
Definition: disassembler.h:37
sh_il_set_param
#define sh_il_set_param(x, y, z)
Definition: sh_il.c:486

References BITS_PER_BYTE, LOGAND, LOGOR, NULL, sh_il_get_param, sh_il_set_param, SH_SCALING_B, SH_SCALING_L, SH_SCALING_W, SH_U_REG, SHIFTL0, and SHIFTR0.

◆ sh_il_tas()

static RzILOpEffect* sh_il_tas ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

TAS.B @Rn If (Rn) = 0, 1 -> T ; Otherwise 0 -> T 1 -> MSB of (Rn) 0110nnnnmmmm0111

Definition at line 1126 of file sh_il.c.

1126  {
1127  RzILOpPure *mem = sh_il_get_pure_param(0);
1128  RzILOpEffect *tbit = SETG(SH_SR_T, IS_ZERO(mem));
1129  return SEQ2(tbit, sh_il_set_pure_param(0, LOGOR(DUP(mem), UN(8, 0x80))));
1130 }
mem
void * mem
Definition: libc.cpp:91

References DUP, IS_ZERO, LOGOR, mem, SEQ2, SETG, sh_il_get_pure_param, sh_il_set_pure_param, SH_SR_T, and UN.

◆ sh_il_tst()

static RzILOpEffect* sh_il_tst ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

TST Rm, Rn If Rn & Rm = 0, 1 -> T ; Otherwise 0 -> T 0010nnnnmmmm1000

TST imm, R0 If R0 & imm = 0, 1 -> T ; Otherwise 0 -> T 11001000iiiiiiii

TST.B imm, @(R0, GBR) If (R0 + GBR) & imm = 0, 1 -> T ; Otherwise 0 -> T 11001100iiiiiiii

Definition at line 1145 of file sh_il.c.

1145  {
1146  return SETG(SH_SR_T, IS_ZERO(LOGAND(sh_il_get_pure_param(0), sh_il_get_pure_param(1))));
1147 }

References IS_ZERO, LOGAND, SETG, sh_il_get_pure_param, and SH_SR_T.

◆ sh_il_unimpl()

static RzILOpEffect* sh_il_unimpl ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

Unimplemented instruction/opcode To be used for valid SuperH-4 instruction which yet haven't been lifted to the IL.

Definition at line 1653 of file sh_il.c.

1653  {
1654  RZ_LOG_WARN("SuperH: Instruction with opcode 0x%04x is unimplemented\n", op->opcode);
1655  return EMPTY();
1656 }

References EMPTY, and RZ_LOG_WARN.

◆ sh_il_xor()

static RzILOpEffect* sh_il_xor ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

XOR Rm, Rn Rn ^ Rm -> Rn 0010nnnnmmmm1010

XOR imm, R0 R0 ^ imm -> R0 11001010iiiiiiii

XOR.B imm, @(R0, GBR) (R0 + GBR) ^ imm -> (R0 + GBR) 11001110iiiiiiii

Definition at line 1162 of file sh_il.c.

1162  {
1163  return sh_il_set_pure_param(1, LOGXOR(sh_il_get_pure_param(0), sh_il_get_pure_param(1)));
1164 }

References LOGXOR, sh_il_get_pure_param, and sh_il_set_pure_param.

◆ sh_il_xtrct()

static RzILOpEffect* sh_il_xtrct ( const SHOp *  op,
ut64  pc,
RzAnalysis *  analysis,
SHILContext *  ctx 
)
static

XTRCT Rm, Rn Rm:Rn middle 32 bits -> Rn 0010nnnnmmmm1101

Definition at line 674 of file sh_il.c.

674  {
675  RzILOpPure *high = SHIFTL0(sh_il_get_pure_param(0), SH_U_REG(BITS_PER_BYTE * 2));
676  RzILOpPure *low = SHIFTR0(sh_il_get_pure_param(1), SH_U_REG(BITS_PER_BYTE * 2));
677  return sh_il_set_pure_param(1, LOGOR(high, low));
678 }

References BITS_PER_BYTE, LOGOR, sh_il_get_pure_param, sh_il_set_pure_param, SH_U_REG, SHIFTL0, and SHIFTR0.

◆ sh_valid_gpr()

static bool sh_valid_gpr ( ut16  reg)
static

Definition at line 44 of file sh_il.c.

44  {
45  return reg < SH_GPR_COUNT;
46 }
SH_GPR_COUNT
#define SH_GPR_COUNT
Definition: disassembler.h:13

References reg, and SH_GPR_COUNT.

Referenced by sh_il_ldc(), and sh_il_stc().

Variable Documentation

◆ sh_global_registers

const char* sh_global_registers[]
static
Initial value:
= {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", "sr",
SH_SR_T, SH_SR_S, SH_SR_I, SH_SR_I, SH_SR_Q, SH_SR_M, SH_SR_F, SH_SR_B, SH_SR_R, SH_SR_D,
"gbr", "ssr", "spc", "sgr", "dbr", "vbr", "mach", "macl", "pr"
}

Registers available as global variables in the IL

Definition at line 55 of file sh_il.c.

Referenced by sh_get_banked_reg().

◆ sh_ops

const sh_il_op sh_ops[SH_OP_SIZE]
static

Lookup table for the IL lifting handlers for the various instructions.

Definition at line 1665 of file sh_il.c.

Referenced by rz_sh_il_opcode().