#include <rz_types.h>
#include <rz_util.h>

Go to the source code of this file.

Classes
struct	sh_param_t

struct	sh_opcode_t

Macros
#define	BITS_PER_BYTE 8

#define	SH_REG_SIZE 4 * BITS_PER_BYTE

#define	SH_ADDR_SIZE 4 * BITS_PER_BYTE

#define	SH_INSTR_SIZE 2 * BITS_PER_BYTE

#define	SH_GPR_COUNT 16

#define	SH_BANKED_REG_COUNT 8

#define	SH_REG_COUNT 61

#define	SH_SR_T_BIT 1u << 0

#define	SH_SR_T "sr_t"
	SR.T: True/False condition or carry/borrow bit. More...

#define	SH_SR_S_BIT 1u << 1

#define	SH_SR_S "sr_s"
	SR.S: Specifies a saturation operation for a MAC instruction. More...

#define	SH_SR_I_BIT 1u << 4

#define	SH_SR_I "sr_i"
	SR.I: Interrupt mask level: External interrupts of a lower level than IMASK are masked. More...

#define	SH_SR_Q_BIT 1u << 8

#define	SH_SR_Q "sr_q"
	SR.Q: State for divide step (Used by the DIV0S, DIV0U and DIV1 instructions) More...

#define	SH_SR_M_BIT 1u << 9

#define	SH_SR_M "sr_m"
	SR.M: State for divide step (Used by the DIV0S, DIV0U and DIV1 instructions) More...

#define	SH_SR_F_BIT 1u << 15

#define	SH_SR_F "sr_f"
	SR.FD: FPU disable bit (cleared to 0 by a reset) More...

#define	SH_SR_B_BIT 1u << 28

#define	SH_SR_B "sr_b"
	SR.BL: Exception/interrupt block bit (set to 1 by a reset, exception, or interrupt) More...

#define	SH_SR_R_BIT 1u << 29

#define	SH_SR_R "sr_r"
	SR.RB: General register bank specifier in privileged mode (set to 1 by a reset, exception or interrupt) More...

#define	SH_SR_D_BIT 1u << 30

#define	SH_SR_D "sr_d"
	SR.MD: Processor mode. More...

Typedefs
typedef enum sh_addr_mode_t	SHAddrMode

typedef enum sh_scaling_t	SHScaling

typedef enum sh_register_index_t	SHRegisterIndex

typedef struct sh_param_t	SHParam

typedef struct sh_opcode_t	SHOp

Enumerations
enum	sh_addr_mode_t { SH_ADDR_INVALID = 0 , SH_REG_DIRECT , SH_REG_INDIRECT , SH_REG_INDIRECT_I , SH_REG_INDIRECT_D , SH_REG_INDIRECT_DISP , SH_REG_INDIRECT_INDEXED , SH_GBR_INDIRECT_DISP , SH_GBR_INDIRECT_INDEXED , SH_PC_RELATIVE_DISP , SH_PC_RELATIVE8 , SH_PC_RELATIVE12 , SH_PC_RELATIVE_REG , SH_IMM_U , SH_IMM_S }

enum	sh_scaling_t { SH_SCALING_INVALID = 0 , SH_SCALING_B , SH_SCALING_W , SH_SCALING_L , SH_SCALING_Q }

enum	sh_register_index_t { SH_REG_IND_R0 = 0 , SH_REG_IND_R1 , SH_REG_IND_R2 , SH_REG_IND_R3 , SH_REG_IND_R4 , SH_REG_IND_R5 , SH_REG_IND_R6 , SH_REG_IND_R7 , SH_REG_IND_R8 , SH_REG_IND_R9 , SH_REG_IND_R10 , SH_REG_IND_R11 , SH_REG_IND_R12 , SH_REG_IND_R13 , SH_REG_IND_R14 , SH_REG_IND_R15 , SH_REG_IND_PC , SH_REG_IND_SR , SH_REG_IND_GBR , SH_REG_IND_SSR , SH_REG_IND_SPC , SH_REG_IND_SGR , SH_REG_IND_DBR , SH_REG_IND_VBR , SH_REG_IND_MACH , SH_REG_IND_MACL , SH_REG_IND_PR , SH_REG_IND_FPUL , SH_REG_IND_FPSCR , SH_REG_IND_FR0 , SH_REG_IND_FR1 , SH_REG_IND_FR2 , SH_REG_IND_FR3 , SH_REG_IND_FR4 , SH_REG_IND_FR5 , SH_REG_IND_FR6 , SH_REG_IND_FR7 , SH_REG_IND_FR8 , SH_REG_IND_FR9 , SH_REG_IND_FR10 , SH_REG_IND_FR11 , SH_REG_IND_FR12 , SH_REG_IND_FR13 , SH_REG_IND_FR14 , SH_REG_IND_FR15 , SH_REG_IND_XF0 , SH_REG_IND_XF1 , SH_REG_IND_XF2 , SH_REG_IND_XF3 , SH_REG_IND_XF4 , SH_REG_IND_XF5 , SH_REG_IND_XF6 , SH_REG_IND_XF7 , SH_REG_IND_XF8 , SH_REG_IND_XF9 , SH_REG_IND_XF10 , SH_REG_IND_XF11 , SH_REG_IND_XF12 , SH_REG_IND_XF13 , SH_REG_IND_XF14 , SH_REG_IND_XF15 , SH_REG_IND_R0B , SH_REG_IND_R1B , SH_REG_IND_R2B , SH_REG_IND_R3B , SH_REG_IND_R4B , SH_REG_IND_R5B , SH_REG_IND_R6B , SH_REG_IND_R7B , SH_REG_IND_SIZE }

enum	SHOpMnem { SH_OP_INVALID = 0 , SH_OP_MOV , SH_OP_MOVT , SH_OP_SWAP , SH_OP_XTRCT , SH_OP_ADD , SH_OP_ADDC , SH_OP_ADDV , SH_OP_CMP_EQ , SH_OP_CMP_HS , SH_OP_CMP_GE , SH_OP_CMP_HI , SH_OP_CMP_GT , SH_OP_CMP_PZ , SH_OP_CMP_PL , SH_OP_CMP_STR , SH_OP_DIV1 , SH_OP_DIV0S , SH_OP_DIV0U , SH_OP_DMULS , SH_OP_DMULU , SH_OP_DT , SH_OP_EXTS , SH_OP_EXTU , SH_OP_MAC , SH_OP_MUL , SH_OP_MULS , SH_OP_MULU , SH_OP_NEG , SH_OP_NEGC , SH_OP_SUB , SH_OP_SUBC , SH_OP_SUBV , SH_OP_AND , SH_OP_NOT , SH_OP_OR , SH_OP_TAS , SH_OP_TST , SH_OP_XOR , SH_OP_ROTL , SH_OP_ROTR , SH_OP_ROTCL , SH_OP_ROTCR , SH_OP_SHAD , SH_OP_SHAL , SH_OP_SHAR , SH_OP_SHLD , SH_OP_SHLL , SH_OP_SHLR , SH_OP_SHLL2 , SH_OP_SHLR2 , SH_OP_SHLL8 , SH_OP_SHLR8 , SH_OP_SHLL16 , SH_OP_SHLR16 , SH_OP_BF , SH_OP_BFS , SH_OP_BT , SH_OP_BTS , SH_OP_BRA , SH_OP_BRAF , SH_OP_BSR , SH_OP_BSRF , SH_OP_JMP , SH_OP_JSR , SH_OP_RTS , SH_OP_CLRMAC , SH_OP_CLRS , SH_OP_CLRT , SH_OP_LDC , SH_OP_LDS , SH_OP_MOVCA , SH_OP_NOP , SH_OP_RTE , SH_OP_SETS , SH_OP_SETT , SH_OP_SLEEP , SH_OP_STC , SH_OP_STS , SH_OP_UNIMPL , SH_OP_SIZE }

Functions
RZ_IPI RZ_OWN SHOp *	sh_disassembler (ut16 opcode)
	Disassemble `opcode` and return a SHOp. More...

RZ_IPI RZ_OWN char *	sh_op_param_to_str (SHParam param, SHScaling scaling, ut64 pc)
	Return string representation of disassembled `param`. More...

RZ_IPI RZ_OWN char *	sh_op_to_str (RZ_NONNULL const SHOp *op, ut64 pc)
	Return string representation of disassembled `op`. More...

Variables
static const ut8	sh_scaling_size [] = { -1, 1, 2, 4, 8 }

Macro Definition Documentation

◆ BITS_PER_BYTE

#define BITS_PER_BYTE 8

Definition at line 9 of file disassembler.h.

◆ SH_ADDR_SIZE

#define SH_ADDR_SIZE 4 * BITS_PER_BYTE

Definition at line 11 of file disassembler.h.

◆ SH_BANKED_REG_COUNT

#define SH_BANKED_REG_COUNT 8

Definition at line 14 of file disassembler.h.

◆ SH_GPR_COUNT

#define SH_GPR_COUNT 16

Definition at line 13 of file disassembler.h.

◆ SH_INSTR_SIZE

#define SH_INSTR_SIZE 2 * BITS_PER_BYTE

Definition at line 12 of file disassembler.h.

◆ SH_REG_COUNT

#define SH_REG_COUNT 61

Definition at line 15 of file disassembler.h.

◆ SH_REG_SIZE

#define SH_REG_SIZE 4 * BITS_PER_BYTE

Definition at line 10 of file disassembler.h.

◆ SH_SR_B

#define SH_SR_B "sr_b"

SR.BL: Exception/interrupt block bit (set to 1 by a reset, exception, or interrupt)

Definition at line 61 of file disassembler.h.

◆ SH_SR_B_BIT

#define SH_SR_B_BIT 1u << 28

Definition at line 60 of file disassembler.h.

◆ SH_SR_D

#define SH_SR_D "sr_d"

SR.MD: Processor mode.

Definition at line 65 of file disassembler.h.

◆ SH_SR_D_BIT

#define SH_SR_D_BIT 1u << 30

Definition at line 64 of file disassembler.h.

◆ SH_SR_F

#define SH_SR_F "sr_f"

SR.FD: FPU disable bit (cleared to 0 by a reset)

Definition at line 59 of file disassembler.h.

◆ SH_SR_F_BIT

#define SH_SR_F_BIT 1u << 15

Definition at line 58 of file disassembler.h.

◆ SH_SR_I

#define SH_SR_I "sr_i"

SR.I: Interrupt mask level: External interrupts of a lower level than IMASK are masked.

Definition at line 53 of file disassembler.h.

◆ SH_SR_I_BIT

#define SH_SR_I_BIT 1u << 4

Definition at line 52 of file disassembler.h.

◆ SH_SR_M

#define SH_SR_M "sr_m"

SR.M: State for divide step (Used by the DIV0S, DIV0U and DIV1 instructions)

Definition at line 57 of file disassembler.h.

◆ SH_SR_M_BIT

#define SH_SR_M_BIT 1u << 9

Definition at line 56 of file disassembler.h.

◆ SH_SR_Q

#define SH_SR_Q "sr_q"

SR.Q: State for divide step (Used by the DIV0S, DIV0U and DIV1 instructions)

Definition at line 55 of file disassembler.h.

◆ SH_SR_Q_BIT

#define SH_SR_Q_BIT 1u << 8

Definition at line 54 of file disassembler.h.

◆ SH_SR_R

#define SH_SR_R "sr_r"

SR.RB: General register bank specifier in privileged mode (set to 1 by a reset, exception or interrupt)

Definition at line 63 of file disassembler.h.

◆ SH_SR_R_BIT

#define SH_SR_R_BIT 1u << 29

Definition at line 62 of file disassembler.h.

◆ SH_SR_S

#define SH_SR_S "sr_s"

SR.S: Specifies a saturation operation for a MAC instruction.

Definition at line 51 of file disassembler.h.

◆ SH_SR_S_BIT

#define SH_SR_S_BIT 1u << 1

Definition at line 50 of file disassembler.h.

◆ SH_SR_T

#define SH_SR_T "sr_t"

SR.T: True/False condition or carry/borrow bit.

Definition at line 49 of file disassembler.h.

◆ SH_SR_T_BIT

#define SH_SR_T_BIT 1u << 0

Definition at line 48 of file disassembler.h.

Typedef Documentation

◆ SHAddrMode

typedef enum sh_addr_mode_t SHAddrMode

◆ SHOp

typedef struct sh_opcode_t SHOp

◆ SHParam

typedef struct sh_param_t SHParam

◆ SHRegisterIndex

typedef enum sh_register_index_t SHRegisterIndex

Enum for register indexes

◆ SHScaling

typedef enum sh_scaling_t SHScaling

Enumeration Type Documentation

◆ sh_addr_mode_t

enum sh_addr_mode_t

Enumerator
SH_ADDR_INVALID
SH_REG_DIRECT
SH_REG_INDIRECT
SH_REG_INDIRECT_I	register indirect with post-increment
SH_REG_INDIRECT_D	register indirect with pre-decrement
SH_REG_INDIRECT_DISP	register indirect with displacement
SH_REG_INDIRECT_INDEXED	indexed register indirect
SH_GBR_INDIRECT_DISP
SH_GBR_INDIRECT_INDEXED
SH_PC_RELATIVE_DISP
SH_PC_RELATIVE8
SH_PC_RELATIVE12
SH_PC_RELATIVE_REG
SH_IMM_U	8-bit immediate value (zero-extended)
SH_IMM_S	8-bit immediate value (sign-extended)

Definition at line 17 of file disassembler.h.

                             {
     SH_ADDR_INVALID = 0,
     SH_REG_DIRECT,
     SH_REG_INDIRECT,
     SH_REG_INDIRECT_I, 
     SH_REG_INDIRECT_D, 
     SH_REG_INDIRECT_DISP, 
     SH_REG_INDIRECT_INDEXED, 
     SH_GBR_INDIRECT_DISP,
     SH_GBR_INDIRECT_INDEXED,
     SH_PC_RELATIVE_DISP,
     SH_PC_RELATIVE8,
     SH_PC_RELATIVE12,
     SH_PC_RELATIVE_REG,
     SH_IMM_U, 
     SH_IMM_S, 
 } SHAddrMode;

◆ sh_register_index_t

enum sh_register_index_t

Enum for register indexes

Enumerator
SH_REG_IND_R0
SH_REG_IND_R1
SH_REG_IND_R2
SH_REG_IND_R3
SH_REG_IND_R4
SH_REG_IND_R5
SH_REG_IND_R6
SH_REG_IND_R7
SH_REG_IND_R8
SH_REG_IND_R9
SH_REG_IND_R10
SH_REG_IND_R11
SH_REG_IND_R12
SH_REG_IND_R13
SH_REG_IND_R14
SH_REG_IND_R15
SH_REG_IND_PC
SH_REG_IND_SR
SH_REG_IND_GBR
SH_REG_IND_SSR
SH_REG_IND_SPC
SH_REG_IND_SGR
SH_REG_IND_DBR
SH_REG_IND_VBR
SH_REG_IND_MACH
SH_REG_IND_MACL
SH_REG_IND_PR
SH_REG_IND_FPUL
SH_REG_IND_FPSCR
SH_REG_IND_FR0
SH_REG_IND_FR1
SH_REG_IND_FR2
SH_REG_IND_FR3
SH_REG_IND_FR4
SH_REG_IND_FR5
SH_REG_IND_FR6
SH_REG_IND_FR7
SH_REG_IND_FR8
SH_REG_IND_FR9
SH_REG_IND_FR10
SH_REG_IND_FR11
SH_REG_IND_FR12
SH_REG_IND_FR13
SH_REG_IND_FR14
SH_REG_IND_FR15
SH_REG_IND_XF0
SH_REG_IND_XF1
SH_REG_IND_XF2
SH_REG_IND_XF3
SH_REG_IND_XF4
SH_REG_IND_XF5
SH_REG_IND_XF6
SH_REG_IND_XF7
SH_REG_IND_XF8
SH_REG_IND_XF9
SH_REG_IND_XF10
SH_REG_IND_XF11
SH_REG_IND_XF12
SH_REG_IND_XF13
SH_REG_IND_XF14
SH_REG_IND_XF15
SH_REG_IND_R0B
SH_REG_IND_R1B
SH_REG_IND_R2B
SH_REG_IND_R3B
SH_REG_IND_R4B
SH_REG_IND_R5B
SH_REG_IND_R6B
SH_REG_IND_R7B
SH_REG_IND_SIZE

Definition at line 70 of file disassembler.h.

                                  {
     // General purpose registers
     SH_REG_IND_R0 = 0,
     SH_REG_IND_R1,
     SH_REG_IND_R2,
     SH_REG_IND_R3,
     SH_REG_IND_R4,
     SH_REG_IND_R5,
     SH_REG_IND_R6,
     SH_REG_IND_R7,
     SH_REG_IND_R8,
     SH_REG_IND_R9,
     SH_REG_IND_R10,
     SH_REG_IND_R11,
     SH_REG_IND_R12,
     SH_REG_IND_R13,
     SH_REG_IND_R14,
     SH_REG_IND_R15,
  
     // System registers
     SH_REG_IND_PC,
     SH_REG_IND_SR,
     SH_REG_IND_GBR,
     SH_REG_IND_SSR,
     SH_REG_IND_SPC,
     SH_REG_IND_SGR,
     SH_REG_IND_DBR,
     SH_REG_IND_VBR,
     SH_REG_IND_MACH,
     SH_REG_IND_MACL,
     SH_REG_IND_PR,
  
     // Floating point registers
     SH_REG_IND_FPUL,
     SH_REG_IND_FPSCR,
     SH_REG_IND_FR0,
     SH_REG_IND_FR1,
     SH_REG_IND_FR2,
     SH_REG_IND_FR3,
     SH_REG_IND_FR4,
     SH_REG_IND_FR5,
     SH_REG_IND_FR6,
     SH_REG_IND_FR7,
     SH_REG_IND_FR8,
     SH_REG_IND_FR9,
     SH_REG_IND_FR10,
     SH_REG_IND_FR11,
     SH_REG_IND_FR12,
     SH_REG_IND_FR13,
     SH_REG_IND_FR14,
     SH_REG_IND_FR15,
     SH_REG_IND_XF0,
     SH_REG_IND_XF1,
     SH_REG_IND_XF2,
     SH_REG_IND_XF3,
     SH_REG_IND_XF4,
     SH_REG_IND_XF5,
     SH_REG_IND_XF6,
     SH_REG_IND_XF7,
     SH_REG_IND_XF8,
     SH_REG_IND_XF9,
     SH_REG_IND_XF10,
     SH_REG_IND_XF11,
     SH_REG_IND_XF12,
     SH_REG_IND_XF13,
     SH_REG_IND_XF14,
     SH_REG_IND_XF15,
  
     // Banked registers
     SH_REG_IND_R0B,
     SH_REG_IND_R1B,
     SH_REG_IND_R2B,
     SH_REG_IND_R3B,
     SH_REG_IND_R4B,
     SH_REG_IND_R5B,
     SH_REG_IND_R6B,
     SH_REG_IND_R7B,
  
     // Size
     SH_REG_IND_SIZE
 } SHRegisterIndex;

◆ sh_scaling_t

enum sh_scaling_t

Enumerator
SH_SCALING_INVALID
SH_SCALING_B	byte
SH_SCALING_W	word
SH_SCALING_L	long word
SH_SCALING_Q	quad word

Definition at line 35 of file disassembler.h.

                           {
     SH_SCALING_INVALID = 0,
     SH_SCALING_B, 
     SH_SCALING_W, 
     SH_SCALING_L, 
     SH_SCALING_Q 
 } SHScaling;

◆ SHOpMnem

enum SHOpMnem

Enumerator
SH_OP_INVALID
SH_OP_MOV
SH_OP_MOVT
SH_OP_SWAP
SH_OP_XTRCT
SH_OP_ADD
SH_OP_ADDC
SH_OP_ADDV
SH_OP_CMP_EQ
SH_OP_CMP_HS
SH_OP_CMP_GE
SH_OP_CMP_HI
SH_OP_CMP_GT
SH_OP_CMP_PZ
SH_OP_CMP_PL
SH_OP_CMP_STR
SH_OP_DIV1
SH_OP_DIV0S
SH_OP_DIV0U
SH_OP_DMULS
SH_OP_DMULU
SH_OP_DT
SH_OP_EXTS
SH_OP_EXTU
SH_OP_MAC
SH_OP_MUL
SH_OP_MULS
SH_OP_MULU
SH_OP_NEG
SH_OP_NEGC
SH_OP_SUB
SH_OP_SUBC
SH_OP_SUBV
SH_OP_AND
SH_OP_NOT
SH_OP_OR
SH_OP_TAS
SH_OP_TST
SH_OP_XOR
SH_OP_ROTL
SH_OP_ROTR
SH_OP_ROTCL
SH_OP_ROTCR
SH_OP_SHAD
SH_OP_SHAL
SH_OP_SHAR
SH_OP_SHLD
SH_OP_SHLL
SH_OP_SHLR
SH_OP_SHLL2
SH_OP_SHLR2
SH_OP_SHLL8
SH_OP_SHLR8
SH_OP_SHLL16
SH_OP_SHLR16
SH_OP_BF
SH_OP_BFS
SH_OP_BT
SH_OP_BTS
SH_OP_BRA
SH_OP_BRAF
SH_OP_BSR
SH_OP_BSRF
SH_OP_JMP
SH_OP_JSR
SH_OP_RTS
SH_OP_CLRMAC
SH_OP_CLRS
SH_OP_CLRT
SH_OP_LDC
SH_OP_LDS
SH_OP_MOVCA
SH_OP_NOP
SH_OP_RTE
SH_OP_SETS
SH_OP_SETT
SH_OP_SLEEP
SH_OP_STC
SH_OP_STS
SH_OP_UNIMPL
SH_OP_SIZE

Definition at line 152 of file disassembler.h.

              {
     SH_OP_INVALID = 0,
     SH_OP_MOV,
     SH_OP_MOVT,
     SH_OP_SWAP,
     SH_OP_XTRCT,
     SH_OP_ADD,
     SH_OP_ADDC,
     SH_OP_ADDV,
     SH_OP_CMP_EQ,
     SH_OP_CMP_HS,
     SH_OP_CMP_GE,
     SH_OP_CMP_HI,
     SH_OP_CMP_GT,
     SH_OP_CMP_PZ,
     SH_OP_CMP_PL,
     SH_OP_CMP_STR,
     SH_OP_DIV1,
     SH_OP_DIV0S,
     SH_OP_DIV0U,
     SH_OP_DMULS,
     SH_OP_DMULU,
     SH_OP_DT,
     SH_OP_EXTS,
     SH_OP_EXTU,
     SH_OP_MAC,
     SH_OP_MUL,
     SH_OP_MULS,
     SH_OP_MULU,
     SH_OP_NEG,
     SH_OP_NEGC,
     SH_OP_SUB,
     SH_OP_SUBC,
     SH_OP_SUBV,
     SH_OP_AND,
     SH_OP_NOT,
     SH_OP_OR,
     SH_OP_TAS,
     SH_OP_TST,
     SH_OP_XOR,
     SH_OP_ROTL,
     SH_OP_ROTR,
     SH_OP_ROTCL,
     SH_OP_ROTCR,
     SH_OP_SHAD,
     SH_OP_SHAL,
     SH_OP_SHAR,
     SH_OP_SHLD,
     SH_OP_SHLL,
     SH_OP_SHLR,
     SH_OP_SHLL2,
     SH_OP_SHLR2,
     SH_OP_SHLL8,
     SH_OP_SHLR8,
     SH_OP_SHLL16,
     SH_OP_SHLR16,
     SH_OP_BF,
     SH_OP_BFS,
     SH_OP_BT,
     SH_OP_BTS,
     SH_OP_BRA,
     SH_OP_BRAF,
     SH_OP_BSR,
     SH_OP_BSRF,
     SH_OP_JMP,
     SH_OP_JSR,
     SH_OP_RTS,
     SH_OP_CLRMAC,
     SH_OP_CLRS,
     SH_OP_CLRT,
     SH_OP_LDC,
     SH_OP_LDS,
     SH_OP_MOVCA,
     SH_OP_NOP,
     SH_OP_RTE,
     SH_OP_SETS,
     SH_OP_SETT,
     SH_OP_SLEEP,
     SH_OP_STC,
     SH_OP_STS,
     SH_OP_UNIMPL,
     /* end */
     SH_OP_SIZE
 } SHOpMnem;

Function Documentation

◆ sh_disassembler()

RZ_IPI RZ_OWN SHOp* sh_disassembler ( ut16 opcode )

Disassemble opcode and return a SHOp.

Parameters

opcode 16 bit wide opcode

Returns: SHOp object corresponding to the opcode

Definition at line 130 of file disassembler.c.

                                                  {
     for (ut16 i = 0; i < OPCODE_NUM; i++) {
         if ((opcode | sh_op_lookup[i].mask) != sh_op_lookup[i].opcode) {
             continue;
         }
  
         SHOpRaw raw = sh_op_lookup[i];
         SHOp *op = RZ_NEW(SHOp);
         op->opcode = opcode;
         op->mnemonic = raw.mnemonic;
         op->scaling = raw.scaling;
         op->str_mnem = raw.str_mnem;
         // check for "weird" mov.l
         if (raw.opcode == MOVL) {
             op->param[0] = sh_op_get_param_movl(opcode, true);
             op->param[1] = sh_op_get_param_movl(opcode, false);
             return op;
         }
         op->param[0] = sh_op_get_param(opcode, raw.param_builder[0]);
         op->param[1] = sh_op_get_param(opcode, raw.param_builder[1]);
         return op;
     }
  
     RZ_LOG_DEBUG("SuperH: Invalid opcode encountered by disassembler: 0x%06x\n", opcode);
     return NULL;
 }

References i, mask, sh_op_raw_t::mnemonic, MOVL, NULL, op, sh_op_raw_t::opcode, OPCODE_NUM, sh_op_raw_t::param_builder, RZ_LOG_DEBUG, RZ_NEW, sh_op_raw_t::scaling, sh_op_get_param(), sh_op_get_param_movl(), sh_op_lookup, and sh_op_raw_t::str_mnem.

Referenced by disassemble(), and sh_op().

◆ sh_op_param_to_str()

RZ_IPI RZ_OWN char* sh_op_param_to_str	(	SHParam	param,
		SHScaling	scaling,
		ut64	pc
	)

Return string representation of disassembled param.

Parameters

SHParam	to be disassembled
SHScaling	of the instruction associated with the param

Returns: char *, owned by the caller

Definition at line 166 of file disassembler.c.

                                                                                   {
     if (param.mode == SH_ADDR_INVALID) {
         return NULL;
     }
  
     RzStrBuf *buf = rz_strbuf_new(NULL);
     switch (param.mode) {
     case SH_REG_DIRECT:
         rz_strbuf_appendf(buf, "%s", sh_registers[param.param[0]]);
         break;
     case SH_REG_INDIRECT:
         rz_strbuf_appendf(buf, "@%s", sh_registers[param.param[0]]);
         break;
     case SH_REG_INDIRECT_I:
         rz_strbuf_appendf(buf, "@%s+", sh_registers[param.param[0]]);
         break;
     case SH_REG_INDIRECT_D:
         rz_strbuf_appendf(buf, "@-%s", sh_registers[param.param[0]]);
         break;
     case SH_REG_INDIRECT_DISP:
         rz_strbuf_appendf(buf, "@(0x%02x,%s)", param.param[1] * sh_scaling_size[scaling], sh_registers[param.param[0]]);
         break;
     case SH_REG_INDIRECT_INDEXED:
         rz_strbuf_appendf(buf, "@(r0,%s)", sh_registers[param.param[0]]);
         break;
     case SH_GBR_INDIRECT_DISP:
         rz_strbuf_appendf(buf, "@(0x%03x,gbr)", param.param[0] * sh_scaling_size[scaling]);
         break;
     case SH_GBR_INDIRECT_INDEXED:
         rz_strbuf_append(buf, "@(r0,gbr)");
         break;
     case SH_PC_RELATIVE_DISP:
         rz_strbuf_appendf(buf, "@(0x%03x,pc)", param.param[0] * sh_scaling_size[scaling]);
         break;
     case SH_PC_RELATIVE8:
     case SH_PC_RELATIVE12:
         rz_strbuf_appendf(buf, "0x%08x", (ut32)pc + 4 + (st32)((st8)param.param[0]) * 2);
         break;
     case SH_PC_RELATIVE_REG:
         rz_strbuf_appendf(buf, "%s", sh_registers[param.param[0]]);
         break;
     case SH_IMM_U:
     case SH_IMM_S:
         rz_strbuf_appendf(buf, "0x%02x", param.param[0]);
         break;
     default:
         rz_warn_if_reached();
     }
  
     return rz_strbuf_drain(buf);
 }

References sh_param_t::mode, NULL, sh_param_t::param, pc, rz_strbuf_append(), rz_strbuf_appendf(), rz_strbuf_drain(), rz_strbuf_new(), rz_warn_if_reached, SH_ADDR_INVALID, SH_GBR_INDIRECT_DISP, SH_GBR_INDIRECT_INDEXED, SH_IMM_S, SH_IMM_U, SH_PC_RELATIVE12, SH_PC_RELATIVE8, SH_PC_RELATIVE_DISP, SH_PC_RELATIVE_REG, SH_REG_DIRECT, SH_REG_INDIRECT, SH_REG_INDIRECT_D, SH_REG_INDIRECT_DISP, SH_REG_INDIRECT_I, SH_REG_INDIRECT_INDEXED, sh_registers, sh_scaling_size, st32, and st8.

Referenced by sh_op_to_str().

◆ sh_op_to_str()

RZ_IPI RZ_OWN char* sh_op_to_str	(	RZ_NONNULL const SHOp *	op,
		ut64	pc
	)

Return string representation of disassembled op.

Parameters

SHOp	to be disassembled

Returns: char *, owned by the caller

Definition at line 224 of file disassembler.c.

                                                                      {
     rz_return_val_if_fail(op, NULL);
     if (!op->str_mnem) {
         return NULL;
     }
     RzStrBuf *buf = rz_strbuf_new(op->str_mnem);
  
     char *param = NULL;
     if ((param = sh_op_param_to_str(op->param[0], op->scaling, pc))) {
         rz_strbuf_appendf(buf, " %s", param);
         free(param);
         if ((param = sh_op_param_to_str(op->param[1], op->scaling, pc))) {
             rz_strbuf_appendf(buf, ", %s", param);
             free(param);
         }
     }
  
     return rz_strbuf_drain(buf);
 }

References free(), NULL, pc, rz_return_val_if_fail, rz_strbuf_appendf(), rz_strbuf_drain(), rz_strbuf_new(), and sh_op_param_to_str().

Referenced by disassemble().

Variable Documentation

◆ sh_scaling_size

const ut8 sh_scaling_size[] = { -1, 1, 2, 4, 8 }

static

Definition at line 43 of file disassembler.h.

Referenced by sh_il_get_effective_addr_pc_ctx(), sh_il_get_param_pc_ctx(), sh_op_movl_param_bits(), sh_op_param_bits(), and sh_op_param_to_str().

Classes

Macros

Typedefs

Enumerations

Functions

Variables

Macro Definition Documentation

◆ BITS_PER_BYTE

◆ SH_ADDR_SIZE

◆ SH_BANKED_REG_COUNT

◆ SH_GPR_COUNT

◆ SH_INSTR_SIZE

◆ SH_REG_COUNT

◆ SH_REG_SIZE

◆ SH_SR_B

◆ SH_SR_B_BIT

◆ SH_SR_D

◆ SH_SR_D_BIT

◆ SH_SR_F

◆ SH_SR_F_BIT

◆ SH_SR_I

◆ SH_SR_I_BIT

◆ SH_SR_M

◆ SH_SR_M_BIT

◆ SH_SR_Q

◆ SH_SR_Q_BIT

◆ SH_SR_R

◆ SH_SR_R_BIT

◆ SH_SR_S

◆ SH_SR_S_BIT

◆ SH_SR_T

◆ SH_SR_T_BIT

Typedef Documentation

◆ SHAddrMode

◆ SHOp

◆ SHParam

◆ SHRegisterIndex

◆ SHScaling

Enumeration Type Documentation

◆ sh_addr_mode_t

◆ sh_register_index_t

◆ sh_scaling_t

◆ SHOpMnem

Function Documentation

◆ sh_disassembler()

◆ sh_op_param_to_str()

◆ sh_op_to_str()

Variable Documentation

◆ sh_scaling_size