Rizin
unix-like reverse engineering framework and cli tools
Classes | Macros | Functions | Variables
rsp_idec.c File Reference
#include "rsp_idec.h"

Go to the source code of this file.

Classes

struct  rsp_operand_decoder
 
struct  rsp_instruction_priv
 
struct  rsp_op_escape
 

Macros

#define RS_DECODER    { RSP_OPND_GP_REG, 21, 0x1f, 0, 0, 0, 0, 0 }
 
#define RT_DECODER    { RSP_OPND_GP_REG, 16, 0x1f, 0, 0, 0, 0, 0 }
 
#define RD_DECODER    { RSP_OPND_GP_REG, 11, 0x1f, 0, 0, 0, 0, 0 }
 
#define SA_DECODER    { RSP_OPND_SHIFT_AMOUNT, 6, 0x1f, 0, 0, 0, 0, 0 }
 
#define LUI_DECODER    { RSP_OPND_ZIMM, 0, 0xffff, 16, 0, 0, 0, 0 }
 
#define ZIMM_DECODER    { RSP_OPND_ZIMM, 0, 0xffff, 0, 0, 0, 0, 0 }
 
#define SIMM_DECODER    { RSP_OPND_SIMM, 0, 0, 0, 0, 0xffff, 0x8000, 0 }
 
#define OFFSET_DECODER    { RSP_OPND_OFFSET, 0, 0, 0, 0, 0xffff, 0x8000, 2 }
 
#define BASE_OFFSET_DECODER    { RSP_OPND_BASE_OFFSET, 21, 0x1f, 0, 0, 0xffff, 0x8000, 0 }
 
#define TARGET_DECODER    { RSP_OPND_TARGET, 0, 0x03ff, 2, 0, 0, 0, 0 }
 
#define C0_REG_DECODER    { RSP_OPND_C0_REG, 11, 0x0f, 0, 0, 0, 0, 0 }
 
#define C2_CREG_DECODER    { RSP_OPND_C2_CREG, 11, 0x03, 0, 0, 0, 0, 0 }
 
#define C2_ACCU_DECODER    { RSP_OPND_C2_ACCU, 21, 0x03, 0, 0, 0, 0, 0 }
 
#define VS_DECODER    { RSP_OPND_C2_VREG, 11, 0x1f, 0, 0, 0, 0, 0 }
 
#define VD_DECODER    { RSP_OPND_C2_VREG, 6, 0x1f, 0, 0, 0, 0, 0 }
 
#define VT_BYTE_DECODER    { RSP_OPND_C2_VREG_BYTE, 16, 0x1f, 0, 7, 0xf, 0, 0 }
 
#define VS_BYTE_DECODER    { RSP_OPND_C2_VREG_BYTE, 11, 0x1f, 0, 7, 0xf, 0, 0 }
 
#define VT_SCALAR_DECODER    { RSP_OPND_C2_VREG_SCALAR, 16, 0x1f, 0, 21, 0x7, 0, 0 }
 
#define VD_SCALAR_DECODER    { RSP_OPND_C2_VREG_SCALAR, 6, 0x1f, 0, 11, 0x7, 0, 0 }
 
#define VT_ELEMENT_DECODER    { RSP_OPND_C2_VREG_ELEMENT, 16, 0x1f, 0, 21, 0xf, 0, 0 }
 
#define BASE_VOFFSET1_DECODER    { RSP_OPND_BASE_OFFSET, 21, 0x1f, 0, 0, 0x7f, 0x40, 0 }
 
#define BASE_VOFFSET2_DECODER    { RSP_OPND_BASE_OFFSET, 21, 0x1f, 0, 0, 0x7f, 0x40, 1 }
 
#define BASE_VOFFSET4_DECODER    { RSP_OPND_BASE_OFFSET, 21, 0x1f, 0, 0, 0x7f, 0x40, 2 }
 
#define BASE_VOFFSET8_DECODER    { RSP_OPND_BASE_OFFSET, 21, 0x1f, 0, 0, 0x7f, 0x40, 3 }
 
#define BASE_VOFFSET16_DECODER    { RSP_OPND_BASE_OFFSET, 21, 0x1f, 0, 0, 0x7f, 0x40, 4 }
 
#define OPNDS_NONE   0,
 
#define OPNDS_TARGET    1, { TARGET_DECODER }
 
#define OPNDS_RS_OFFSET    2, { RS_DECODER, OFFSET_DECODER }
 
#define OPNDS_RS_RT_OFFSET    3, { RS_DECODER, RT_DECODER, OFFSET_DECODER }
 
#define OPNDS_RT_BASE_OFFSET    2, { RT_DECODER, BASE_OFFSET_DECODER }
 
#define OPNDS_RS    1, { RS_DECODER }
 
#define OPNDS_RT_LUI    2, { RT_DECODER, LUI_DECODER }
 
#define OPNDS_RT_RS_SIMM    3, { RT_DECODER, RS_DECODER, SIMM_DECODER }
 
#define OPNDS_RT_RS_ZIMM    3, { RT_DECODER, RS_DECODER, ZIMM_DECODER }
 
#define OPNDS_RD_RT_SA    3, { RD_DECODER, RT_DECODER, SA_DECODER }
 
#define OPNDS_RD_RT_RS    3, { RD_DECODER, RT_DECODER, RS_DECODER }
 
#define OPNDS_RD_RS_RT    3, { RD_DECODER, RS_DECODER, RT_DECODER }
 
#define OPNDS_RT_C0_REG    2, { RT_DECODER, C0_REG_DECODER }
 
#define OPNDS_RT_C2_CREG    2, { RT_DECODER, C2_CREG_DECODER }
 
#define OPNDS_RT_VSB    2, { RT_DECODER, VS_BYTE_DECODER }
 
#define OPNDS_VDS_VTS    2, { VD_SCALAR_DECODER, VT_SCALAR_DECODER }
 
#define OPNDS_VTB_BASE_OFFSET1    2, { VT_BYTE_DECODER, BASE_VOFFSET1_DECODER }
 
#define OPNDS_VTB_BASE_OFFSET2    2, { VT_BYTE_DECODER, BASE_VOFFSET2_DECODER }
 
#define OPNDS_VTB_BASE_OFFSET4    2, { VT_BYTE_DECODER, BASE_VOFFSET4_DECODER }
 
#define OPNDS_VTB_BASE_OFFSET8    2, { VT_BYTE_DECODER, BASE_VOFFSET8_DECODER }
 
#define OPNDS_VTB_BASE_OFFSET16    2, { VT_BYTE_DECODER, BASE_VOFFSET16_DECODER }
 
#define OPNDS_VD_VS_C2_ACCU    3, { VD_DECODER, VS_DECODER, C2_ACCU_DECODER }
 
#define OPNDS_VD_VS_VTE    3, { VD_DECODER, VS_DECODER, VT_ELEMENT_DECODER }
 
#define INVALID    { "invalid", RSP_OP_INVALID, OPNDS_NONE }
 
#define NOP    { "nop", RSP_OP_NOP, OPNDS_NONE }
 
#define SLL    { "sll", RSP_OP_SLL, OPNDS_RD_RT_SA }
 
#define SRL    { "srl", RSP_OP_SRL, OPNDS_RD_RT_SA }
 
#define SRA    { "sra", RSP_OP_SRA, OPNDS_RD_RT_SA }
 
#define SLLV    { "sllv", RSP_OP_SLLV, OPNDS_RD_RT_RS }
 
#define SRLV    { "srlv", RSP_OP_SRLV, OPNDS_RD_RT_RS }
 
#define SRAV    { "srav", RSP_OP_SRAV, OPNDS_RD_RT_RS }
 
#define JR    { "jr", RSP_OP_JR, OPNDS_RS }
 
#define BREAK    { "break", RSP_OP_BREAK, OPNDS_NONE }
 
#define ADD    { "add", RSP_OP_ADD, OPNDS_RD_RS_RT }
 
#define ADDU    { "addu", RSP_OP_ADDU, OPNDS_RD_RS_RT }
 
#define SUB    { "sub", RSP_OP_SUB, OPNDS_RD_RS_RT }
 
#define SUBU    { "subu", RSP_OP_SUBU, OPNDS_RD_RS_RT }
 
#define AND    { "and", RSP_OP_AND, OPNDS_RD_RS_RT }
 
#define OR    { "or", RSP_OP_OR, OPNDS_RD_RS_RT }
 
#define XOR    { "xor", RSP_OP_XOR, OPNDS_RD_RS_RT }
 
#define NOR    { "nor", RSP_OP_NOR, OPNDS_RD_RS_RT }
 
#define SLT    { "slt", RSP_OP_SLT, OPNDS_RD_RS_RT }
 
#define SLTU    { "sltu", RSP_OP_SLTU, OPNDS_RD_RS_RT }
 
#define BLTZ    { "bltz", RSP_OP_BLTZ, OPNDS_RS_OFFSET }
 
#define BGEZ    { "bgez", RSP_OP_BGEZ, OPNDS_RS_OFFSET }
 
#define BLTZAL    { "bltzal", RSP_OP_BLTZAL, OPNDS_RS_OFFSET }
 
#define BGEZAL    { "bgezal", RSP_OP_BGEZAL, OPNDS_RS_OFFSET }
 
#define MFC0    { "mfc0", RSP_OP_MFC0, OPNDS_RT_C0_REG }
 
#define MTC0    { "mtc0", RSP_OP_MTC0, OPNDS_RT_C0_REG }
 
#define MFC2    { "mfc2", RSP_OP_MFC2, OPNDS_RT_VSB }
 
#define MTC2    { "mtc2", RSP_OP_MTC2, OPNDS_RT_VSB }
 
#define CFC2    { "cfc2", RSP_OP_CFC2, OPNDS_RT_C2_CREG }
 
#define CTC2    { "ctc2", RSP_OP_CTC2, OPNDS_RT_C2_CREG }
 
#define VMULF    { "vmulf", RSP_OP_VMULF, OPNDS_VD_VS_VTE }
 
#define VMULU    { "vmulu", RSP_OP_VMULU, OPNDS_VD_VS_VTE }
 
#define VMUDL    { "vmudl", RSP_OP_VMUDL, OPNDS_VD_VS_VTE }
 
#define VMUDM    { "vmudm", RSP_OP_VMUDM, OPNDS_VD_VS_VTE }
 
#define VMUDN    { "vmudn", RSP_OP_VMUDN, OPNDS_VD_VS_VTE }
 
#define VMUDH    { "vmudh", RSP_OP_VMUDH, OPNDS_VD_VS_VTE }
 
#define VMACF    { "vmacf", RSP_OP_VMACF, OPNDS_VD_VS_VTE }
 
#define VMACU    { "vmacu", RSP_OP_VMACU, OPNDS_VD_VS_VTE }
 
#define VMADL    { "vmadl", RSP_OP_VMADL, OPNDS_VD_VS_VTE }
 
#define VMADM    { "vmadm", RSP_OP_VMADM, OPNDS_VD_VS_VTE }
 
#define VMADN    { "vmadn", RSP_OP_VMADN, OPNDS_VD_VS_VTE }
 
#define VMADH    { "vmadh", RSP_OP_VMADH, OPNDS_VD_VS_VTE }
 
#define VADD    { "vadd", RSP_OP_VADD, OPNDS_VD_VS_VTE }
 
#define VSUB    { "vsub", RSP_OP_VSUB, OPNDS_VD_VS_VTE }
 
#define VABS    { "vabs", RSP_OP_VABS, OPNDS_VD_VS_VTE }
 
#define VADDC    { "vaddc", RSP_OP_VADDC, OPNDS_VD_VS_VTE }
 
#define VSUBC    { "vsubc", RSP_OP_VSUBC, OPNDS_VD_VS_VTE }
 
#define VSAR    { "vsar", RSP_OP_VSAR, OPNDS_VD_VS_C2_ACCU }
 
#define VLT    { "vlt", RSP_OP_VLT, OPNDS_VD_VS_VTE }
 
#define VEQ    { "veq", RSP_OP_VEQ, OPNDS_VD_VS_VTE }
 
#define VNE    { "vne", RSP_OP_VNE, OPNDS_VD_VS_VTE }
 
#define VGE    { "vge", RSP_OP_VGE, OPNDS_VD_VS_VTE }
 
#define VCL    { "vcl", RSP_OP_VCL, OPNDS_VD_VS_VTE }
 
#define VCH    { "vch", RSP_OP_VCH, OPNDS_VD_VS_VTE }
 
#define VCR    { "vcr", RSP_OP_VCR, OPNDS_VD_VS_VTE }
 
#define VMRG    { "vmrg", RSP_OP_VMRG, OPNDS_VD_VS_VTE }
 
#define VAND    { "vand", RSP_OP_VAND, OPNDS_VD_VS_VTE }
 
#define VNAND    { "vnand", RSP_OP_VNAND, OPNDS_VD_VS_VTE }
 
#define VOR    { "vor", RSP_OP_VOR, OPNDS_VD_VS_VTE }
 
#define VNOR    { "vnor", RSP_OP_VNOR, OPNDS_VD_VS_VTE }
 
#define VXOR    { "vxor", RSP_OP_VXOR, OPNDS_VD_VS_VTE }
 
#define VNXOR    { "vnxor", RSP_OP_VNXOR, OPNDS_VD_VS_VTE }
 
#define VRCP    { "vrcp", RSP_OP_VRCP, OPNDS_VDS_VTS }
 
#define VRCPL    { "vrcpl", RSP_OP_VRCPL, OPNDS_VDS_VTS }
 
#define VRCPH    { "vrcph", RSP_OP_VRCPH, OPNDS_VDS_VTS }
 
#define VMOV    { "vmov", RSP_OP_VMOV, OPNDS_VDS_VTS }
 
#define VRSQ    { "vrsq", RSP_OP_VRSQ, OPNDS_VDS_VTS }
 
#define VRSQL    { "vrsql", RSP_OP_VRSQL, OPNDS_VDS_VTS }
 
#define VRSQH    { "vrsqh", RSP_OP_VRSQH, OPNDS_VDS_VTS }
 
#define VNOP    { "vnop", RSP_OP_VNOP, OPNDS_NONE }
 
#define LBV    { "lbv", RSP_OP_LBV, OPNDS_VTB_BASE_OFFSET1 }
 
#define LSV    { "lsv", RSP_OP_LSV, OPNDS_VTB_BASE_OFFSET2 }
 
#define LLV    { "llv", RSP_OP_LLV, OPNDS_VTB_BASE_OFFSET4 }
 
#define LDV    { "ldv", RSP_OP_LDV, OPNDS_VTB_BASE_OFFSET8 }
 
#define LQV    { "lqv", RSP_OP_LQV, OPNDS_VTB_BASE_OFFSET16 }
 
#define LRV    { "lrv", RSP_OP_LRV, OPNDS_VTB_BASE_OFFSET16 }
 
#define LPV    { "lpv", RSP_OP_LPV, OPNDS_VTB_BASE_OFFSET8 }
 
#define LUV    { "luv", RSP_OP_LUV, OPNDS_VTB_BASE_OFFSET8 }
 
#define LHV    { "lhv", RSP_OP_LHV, OPNDS_VTB_BASE_OFFSET16 }
 
#define LFV    { "lfv", RSP_OP_LFV, OPNDS_VTB_BASE_OFFSET16 }
 
#define LTV    { "ltv", RSP_OP_LTV, OPNDS_VTB_BASE_OFFSET16 }
 
#define SBV    { "sbv", RSP_OP_SBV, OPNDS_VTB_BASE_OFFSET1 }
 
#define SSV    { "ssv", RSP_OP_SSV, OPNDS_VTB_BASE_OFFSET2 }
 
#define SLV    { "slv", RSP_OP_SLV, OPNDS_VTB_BASE_OFFSET4 }
 
#define SDV    { "sdv", RSP_OP_SDV, OPNDS_VTB_BASE_OFFSET8 }
 
#define SQV    { "sqv", RSP_OP_SQV, OPNDS_VTB_BASE_OFFSET16 }
 
#define SRV    { "srv", RSP_OP_SRV, OPNDS_VTB_BASE_OFFSET8 }
 
#define SPV    { "spv", RSP_OP_SPV, OPNDS_VTB_BASE_OFFSET8 }
 
#define SUV    { "suv", RSP_OP_SUV, OPNDS_VTB_BASE_OFFSET16 }
 
#define SHV    { "shv", RSP_OP_SHV, OPNDS_VTB_BASE_OFFSET16 }
 
#define SFV    { "sfv", RSP_OP_SFV, OPNDS_VTB_BASE_OFFSET16 }
 
#define SWV    { "swv", RSP_OP_SWV, OPNDS_VTB_BASE_OFFSET16 }
 
#define STV    { "stv", RSP_OP_STV, OPNDS_VTB_BASE_OFFSET16 }
 
#define J    { "j", RSP_OP_J, OPNDS_TARGET }
 
#define JAL    { "jal", RSP_OP_JAL, OPNDS_TARGET }
 
#define BEQ    { "beq", RSP_OP_BEQ, OPNDS_RS_RT_OFFSET }
 
#define BNE    { "bne", RSP_OP_BNE, OPNDS_RS_RT_OFFSET }
 
#define BLEZ    { "blez", RSP_OP_BLEZ, OPNDS_RS_RT_OFFSET }
 
#define BGTZ    { "bgtz", RSP_OP_BGTZ, OPNDS_RS_RT_OFFSET }
 
#define ADDI    { "addi", RSP_OP_ADDI, OPNDS_RT_RS_SIMM }
 
#define ADDIU    { "addiu", RSP_OP_ADDIU, OPNDS_RT_RS_SIMM }
 
#define SLTI    { "slti", RSP_OP_SLTI, OPNDS_RT_RS_SIMM }
 
#define SLTIU    { "sltiu", RSP_OP_SLTIU, OPNDS_RT_RS_SIMM }
 
#define ANDI    { "andi", RSP_OP_ANDI, OPNDS_RT_RS_ZIMM }
 
#define ORI    { "ori", RSP_OP_ORI, OPNDS_RT_RS_ZIMM }
 
#define XORI    { "xori", RSP_OP_XORI, OPNDS_RT_RS_ZIMM }
 
#define LUI    { "lui", RSP_OP_LUI, OPNDS_RT_LUI }
 
#define LB    { "lb", RSP_OP_LB, OPNDS_RT_BASE_OFFSET }
 
#define LH    { "lh", RSP_OP_LH, OPNDS_RT_BASE_OFFSET }
 
#define LW    { "lw", RSP_OP_LW, OPNDS_RT_BASE_OFFSET }
 
#define LBU    { "lbu", RSP_OP_LBU, OPNDS_RT_BASE_OFFSET }
 
#define LHU    { "lhu", RSP_OP_LHU, OPNDS_RT_BASE_OFFSET }
 
#define SB    { "sb", RSP_OP_SB, OPNDS_RT_BASE_OFFSET }
 
#define SH    { "sh", RSP_OP_SH, OPNDS_RT_BASE_OFFSET }
 
#define SW    { "sw", RSP_OP_SW, OPNDS_RT_BASE_OFFSET }
 
#define SPECIAL    { 0, 0, 0x3f }
 
#define REGIMM    { 64, 16, 0x1f }
 
#define COP0    { 96, 21, 0x1f }
 
#define COP2    { 128, 21, 0x1f }
 
#define VECTOP    { 160, 0, 0x3f }
 
#define LWC2    { 224, 11, 0x1f }
 
#define SWC2    { 256, 11, 0x1f }
 
#define MAIN    { 288, 26, 0x3f }
 

Functions

static const rsp_instruction_priv * rsp_decode_priv (ut32 iw)
 
static st32 rsp_sign_extend (st32 x, st32 m)
 
static rsp_operand rsp_operand_decode (ut64 pc, ut32 iw, const rsp_operand_decoder *odec)
 
rsp_instruction rsp_instruction_decode (ut64 pc, ut32 iw)
 

Variables

const char * rsp_gp_reg_soft_names []
 
const char * rsp_c0_reg_soft_names []
 
const char * rsp_gp_reg_names []
 
const char * rsp_c0_reg_names []
 
const char * rsp_c2_creg_names []
 
const char * rsp_c2_accu_names []
 
const char * rsp_c2_vreg_names []
 
const char * rsp_c2_vreg_element_names []
 
static const rsp_instruction_priv rsp_op_table []
 
static const rsp_op_escape rsp_escapes_table []
 

Macro Definition Documentation

◆ ADD

#define ADD    { "add", RSP_OP_ADD, OPNDS_RD_RS_RT }

Definition at line 200 of file rsp_idec.c.

◆ ADDI

#define ADDI    { "addi", RSP_OP_ADDI, OPNDS_RT_RS_SIMM }

Definition at line 378 of file rsp_idec.c.

◆ ADDIU

#define ADDIU    { "addiu", RSP_OP_ADDIU, OPNDS_RT_RS_SIMM }

Definition at line 380 of file rsp_idec.c.

◆ ADDU

#define ADDU    { "addu", RSP_OP_ADDU, OPNDS_RD_RS_RT }

Definition at line 202 of file rsp_idec.c.

◆ AND

#define AND    { "and", RSP_OP_AND, OPNDS_RD_RS_RT }

Definition at line 208 of file rsp_idec.c.

◆ ANDI

#define ANDI    { "andi", RSP_OP_ANDI, OPNDS_RT_RS_ZIMM }

Definition at line 386 of file rsp_idec.c.

◆ BASE_OFFSET_DECODER

#define BASE_OFFSET_DECODER    { RSP_OPND_BASE_OFFSET, 21, 0x1f, 0, 0, 0xffff, 0x8000, 0 }

Definition at line 97 of file rsp_idec.c.

◆ BASE_VOFFSET16_DECODER

#define BASE_VOFFSET16_DECODER    { RSP_OPND_BASE_OFFSET, 21, 0x1f, 0, 0, 0x7f, 0x40, 4 }

Definition at line 129 of file rsp_idec.c.

◆ BASE_VOFFSET1_DECODER

#define BASE_VOFFSET1_DECODER    { RSP_OPND_BASE_OFFSET, 21, 0x1f, 0, 0, 0x7f, 0x40, 0 }

Definition at line 121 of file rsp_idec.c.

◆ BASE_VOFFSET2_DECODER

#define BASE_VOFFSET2_DECODER    { RSP_OPND_BASE_OFFSET, 21, 0x1f, 0, 0, 0x7f, 0x40, 1 }

Definition at line 123 of file rsp_idec.c.

◆ BASE_VOFFSET4_DECODER

#define BASE_VOFFSET4_DECODER    { RSP_OPND_BASE_OFFSET, 21, 0x1f, 0, 0, 0x7f, 0x40, 2 }

Definition at line 125 of file rsp_idec.c.

◆ BASE_VOFFSET8_DECODER

#define BASE_VOFFSET8_DECODER    { RSP_OPND_BASE_OFFSET, 21, 0x1f, 0, 0, 0x7f, 0x40, 3 }

Definition at line 127 of file rsp_idec.c.

◆ BEQ

#define BEQ    { "beq", RSP_OP_BEQ, OPNDS_RS_RT_OFFSET }

Definition at line 370 of file rsp_idec.c.

◆ BGEZ

#define BGEZ    { "bgez", RSP_OP_BGEZ, OPNDS_RS_OFFSET }

Definition at line 222 of file rsp_idec.c.

◆ BGEZAL

#define BGEZAL    { "bgezal", RSP_OP_BGEZAL, OPNDS_RS_OFFSET }

Definition at line 226 of file rsp_idec.c.

◆ BGTZ

#define BGTZ    { "bgtz", RSP_OP_BGTZ, OPNDS_RS_RT_OFFSET }

Definition at line 376 of file rsp_idec.c.

◆ BLEZ

#define BLEZ    { "blez", RSP_OP_BLEZ, OPNDS_RS_RT_OFFSET }

Definition at line 374 of file rsp_idec.c.

◆ BLTZ

#define BLTZ    { "bltz", RSP_OP_BLTZ, OPNDS_RS_OFFSET }

Definition at line 220 of file rsp_idec.c.

◆ BLTZAL

#define BLTZAL    { "bltzal", RSP_OP_BLTZAL, OPNDS_RS_OFFSET }

Definition at line 224 of file rsp_idec.c.

◆ BNE

#define BNE    { "bne", RSP_OP_BNE, OPNDS_RS_RT_OFFSET }

Definition at line 372 of file rsp_idec.c.

◆ BREAK

#define BREAK    { "break", RSP_OP_BREAK, OPNDS_NONE }

Definition at line 198 of file rsp_idec.c.

◆ C0_REG_DECODER

#define C0_REG_DECODER    { RSP_OPND_C0_REG, 11, 0x0f, 0, 0, 0, 0, 0 }

Definition at line 101 of file rsp_idec.c.

◆ C2_ACCU_DECODER

#define C2_ACCU_DECODER    { RSP_OPND_C2_ACCU, 21, 0x03, 0, 0, 0, 0, 0 }

Definition at line 105 of file rsp_idec.c.

◆ C2_CREG_DECODER

#define C2_CREG_DECODER    { RSP_OPND_C2_CREG, 11, 0x03, 0, 0, 0, 0, 0 }

Definition at line 103 of file rsp_idec.c.

◆ CFC2

#define CFC2    { "cfc2", RSP_OP_CFC2, OPNDS_RT_C2_CREG }

Definition at line 236 of file rsp_idec.c.

◆ COP0

#define COP0    { 96, 21, 0x1f }

Definition at line 508 of file rsp_idec.c.

◆ COP2

#define COP2    { 128, 21, 0x1f }

Definition at line 510 of file rsp_idec.c.

◆ CTC2

#define CTC2    { "ctc2", RSP_OP_CTC2, OPNDS_RT_C2_CREG }

Definition at line 238 of file rsp_idec.c.

◆ INVALID

#define INVALID    { "invalid", RSP_OP_INVALID, OPNDS_NONE }

Definition at line 180 of file rsp_idec.c.

◆ J

#define J    { "j", RSP_OP_J, OPNDS_TARGET }

Definition at line 366 of file rsp_idec.c.

◆ JAL

#define JAL    { "jal", RSP_OP_JAL, OPNDS_TARGET }

Definition at line 368 of file rsp_idec.c.

◆ JR

#define JR    { "jr", RSP_OP_JR, OPNDS_RS }

Definition at line 196 of file rsp_idec.c.

◆ LB

#define LB    { "lb", RSP_OP_LB, OPNDS_RT_BASE_OFFSET }

Definition at line 394 of file rsp_idec.c.

◆ LBU

#define LBU    { "lbu", RSP_OP_LBU, OPNDS_RT_BASE_OFFSET }

Definition at line 400 of file rsp_idec.c.

◆ LBV

#define LBV    { "lbv", RSP_OP_LBV, OPNDS_VTB_BASE_OFFSET1 }

Definition at line 320 of file rsp_idec.c.

◆ LDV

#define LDV    { "ldv", RSP_OP_LDV, OPNDS_VTB_BASE_OFFSET8 }

Definition at line 326 of file rsp_idec.c.

◆ LFV

#define LFV    { "lfv", RSP_OP_LFV, OPNDS_VTB_BASE_OFFSET16 }

Definition at line 338 of file rsp_idec.c.

◆ LH

#define LH    { "lh", RSP_OP_LH, OPNDS_RT_BASE_OFFSET }

Definition at line 396 of file rsp_idec.c.

◆ LHU

#define LHU    { "lhu", RSP_OP_LHU, OPNDS_RT_BASE_OFFSET }

Definition at line 402 of file rsp_idec.c.

◆ LHV

#define LHV    { "lhv", RSP_OP_LHV, OPNDS_VTB_BASE_OFFSET16 }

Definition at line 336 of file rsp_idec.c.

◆ LLV

#define LLV    { "llv", RSP_OP_LLV, OPNDS_VTB_BASE_OFFSET4 }

Definition at line 324 of file rsp_idec.c.

◆ LPV

#define LPV    { "lpv", RSP_OP_LPV, OPNDS_VTB_BASE_OFFSET8 }

Definition at line 332 of file rsp_idec.c.

◆ LQV

#define LQV    { "lqv", RSP_OP_LQV, OPNDS_VTB_BASE_OFFSET16 }

Definition at line 328 of file rsp_idec.c.

◆ LRV

#define LRV    { "lrv", RSP_OP_LRV, OPNDS_VTB_BASE_OFFSET16 }

Definition at line 330 of file rsp_idec.c.

◆ LSV

#define LSV    { "lsv", RSP_OP_LSV, OPNDS_VTB_BASE_OFFSET2 }

Definition at line 322 of file rsp_idec.c.

◆ LTV

#define LTV    { "ltv", RSP_OP_LTV, OPNDS_VTB_BASE_OFFSET16 }

Definition at line 340 of file rsp_idec.c.

◆ LUI

#define LUI    { "lui", RSP_OP_LUI, OPNDS_RT_LUI }

Definition at line 392 of file rsp_idec.c.

◆ LUI_DECODER

#define LUI_DECODER    { RSP_OPND_ZIMM, 0, 0xffff, 16, 0, 0, 0, 0 }

Definition at line 89 of file rsp_idec.c.

◆ LUV

#define LUV    { "luv", RSP_OP_LUV, OPNDS_VTB_BASE_OFFSET8 }

Definition at line 334 of file rsp_idec.c.

◆ LW

#define LW    { "lw", RSP_OP_LW, OPNDS_RT_BASE_OFFSET }

Definition at line 398 of file rsp_idec.c.

◆ LWC2

#define LWC2    { 224, 11, 0x1f }

Definition at line 514 of file rsp_idec.c.

◆ MAIN

#define MAIN    { 288, 26, 0x3f }

Definition at line 518 of file rsp_idec.c.

◆ MFC0

#define MFC0    { "mfc0", RSP_OP_MFC0, OPNDS_RT_C0_REG }

Definition at line 228 of file rsp_idec.c.

◆ MFC2

#define MFC2    { "mfc2", RSP_OP_MFC2, OPNDS_RT_VSB }

Definition at line 232 of file rsp_idec.c.

◆ MTC0

#define MTC0    { "mtc0", RSP_OP_MTC0, OPNDS_RT_C0_REG }

Definition at line 230 of file rsp_idec.c.

◆ MTC2

#define MTC2    { "mtc2", RSP_OP_MTC2, OPNDS_RT_VSB }

Definition at line 234 of file rsp_idec.c.

◆ NOP

#define NOP    { "nop", RSP_OP_NOP, OPNDS_NONE }

Definition at line 182 of file rsp_idec.c.

◆ NOR

#define NOR    { "nor", RSP_OP_NOR, OPNDS_RD_RS_RT }

Definition at line 214 of file rsp_idec.c.

◆ OFFSET_DECODER

#define OFFSET_DECODER    { RSP_OPND_OFFSET, 0, 0, 0, 0, 0xffff, 0x8000, 2 }

Definition at line 95 of file rsp_idec.c.

◆ OPNDS_NONE

#define OPNDS_NONE   0,

Definition at line 133 of file rsp_idec.c.

◆ OPNDS_RD_RS_RT

#define OPNDS_RD_RS_RT    3, { RD_DECODER, RS_DECODER, RT_DECODER }

Definition at line 154 of file rsp_idec.c.

◆ OPNDS_RD_RT_RS

#define OPNDS_RD_RT_RS    3, { RD_DECODER, RT_DECODER, RS_DECODER }

Definition at line 152 of file rsp_idec.c.

◆ OPNDS_RD_RT_SA

#define OPNDS_RD_RT_SA    3, { RD_DECODER, RT_DECODER, SA_DECODER }

Definition at line 150 of file rsp_idec.c.

◆ OPNDS_RS

#define OPNDS_RS    1, { RS_DECODER }

Definition at line 142 of file rsp_idec.c.

◆ OPNDS_RS_OFFSET

#define OPNDS_RS_OFFSET    2, { RS_DECODER, OFFSET_DECODER }

Definition at line 136 of file rsp_idec.c.

◆ OPNDS_RS_RT_OFFSET

#define OPNDS_RS_RT_OFFSET    3, { RS_DECODER, RT_DECODER, OFFSET_DECODER }

Definition at line 138 of file rsp_idec.c.

◆ OPNDS_RT_BASE_OFFSET

#define OPNDS_RT_BASE_OFFSET    2, { RT_DECODER, BASE_OFFSET_DECODER }

Definition at line 140 of file rsp_idec.c.

◆ OPNDS_RT_C0_REG

#define OPNDS_RT_C0_REG    2, { RT_DECODER, C0_REG_DECODER }

Definition at line 156 of file rsp_idec.c.

◆ OPNDS_RT_C2_CREG

#define OPNDS_RT_C2_CREG    2, { RT_DECODER, C2_CREG_DECODER }

Definition at line 158 of file rsp_idec.c.

◆ OPNDS_RT_LUI

#define OPNDS_RT_LUI    2, { RT_DECODER, LUI_DECODER }

Definition at line 144 of file rsp_idec.c.

◆ OPNDS_RT_RS_SIMM

#define OPNDS_RT_RS_SIMM    3, { RT_DECODER, RS_DECODER, SIMM_DECODER }

Definition at line 146 of file rsp_idec.c.

◆ OPNDS_RT_RS_ZIMM

#define OPNDS_RT_RS_ZIMM    3, { RT_DECODER, RS_DECODER, ZIMM_DECODER }

Definition at line 148 of file rsp_idec.c.

◆ OPNDS_RT_VSB

#define OPNDS_RT_VSB    2, { RT_DECODER, VS_BYTE_DECODER }

Definition at line 160 of file rsp_idec.c.

◆ OPNDS_TARGET

#define OPNDS_TARGET    1, { TARGET_DECODER }

Definition at line 134 of file rsp_idec.c.

◆ OPNDS_VD_VS_C2_ACCU

#define OPNDS_VD_VS_C2_ACCU    3, { VD_DECODER, VS_DECODER, C2_ACCU_DECODER }

Definition at line 174 of file rsp_idec.c.

◆ OPNDS_VD_VS_VTE

#define OPNDS_VD_VS_VTE    3, { VD_DECODER, VS_DECODER, VT_ELEMENT_DECODER }

Definition at line 176 of file rsp_idec.c.

◆ OPNDS_VDS_VTS

#define OPNDS_VDS_VTS    2, { VD_SCALAR_DECODER, VT_SCALAR_DECODER }

Definition at line 162 of file rsp_idec.c.

◆ OPNDS_VTB_BASE_OFFSET1

#define OPNDS_VTB_BASE_OFFSET1    2, { VT_BYTE_DECODER, BASE_VOFFSET1_DECODER }

Definition at line 164 of file rsp_idec.c.

◆ OPNDS_VTB_BASE_OFFSET16

#define OPNDS_VTB_BASE_OFFSET16    2, { VT_BYTE_DECODER, BASE_VOFFSET16_DECODER }

Definition at line 172 of file rsp_idec.c.

◆ OPNDS_VTB_BASE_OFFSET2

#define OPNDS_VTB_BASE_OFFSET2    2, { VT_BYTE_DECODER, BASE_VOFFSET2_DECODER }

Definition at line 166 of file rsp_idec.c.

◆ OPNDS_VTB_BASE_OFFSET4

#define OPNDS_VTB_BASE_OFFSET4    2, { VT_BYTE_DECODER, BASE_VOFFSET4_DECODER }

Definition at line 168 of file rsp_idec.c.

◆ OPNDS_VTB_BASE_OFFSET8

#define OPNDS_VTB_BASE_OFFSET8    2, { VT_BYTE_DECODER, BASE_VOFFSET8_DECODER }

Definition at line 170 of file rsp_idec.c.

◆ OR

#define OR    { "or", RSP_OP_OR, OPNDS_RD_RS_RT }

Definition at line 210 of file rsp_idec.c.

◆ ORI

#define ORI    { "ori", RSP_OP_ORI, OPNDS_RT_RS_ZIMM }

Definition at line 388 of file rsp_idec.c.

◆ RD_DECODER

#define RD_DECODER    { RSP_OPND_GP_REG, 11, 0x1f, 0, 0, 0, 0, 0 }

Definition at line 85 of file rsp_idec.c.

◆ REGIMM

#define REGIMM    { 64, 16, 0x1f }

Definition at line 506 of file rsp_idec.c.

◆ RS_DECODER

#define RS_DECODER    { RSP_OPND_GP_REG, 21, 0x1f, 0, 0, 0, 0, 0 }

Definition at line 81 of file rsp_idec.c.

◆ RT_DECODER

#define RT_DECODER    { RSP_OPND_GP_REG, 16, 0x1f, 0, 0, 0, 0, 0 }

Definition at line 83 of file rsp_idec.c.

◆ SA_DECODER

#define SA_DECODER    { RSP_OPND_SHIFT_AMOUNT, 6, 0x1f, 0, 0, 0, 0, 0 }

Definition at line 87 of file rsp_idec.c.

◆ SB

#define SB    { "sb", RSP_OP_SB, OPNDS_RT_BASE_OFFSET }

Definition at line 404 of file rsp_idec.c.

◆ SBV

#define SBV    { "sbv", RSP_OP_SBV, OPNDS_VTB_BASE_OFFSET1 }

Definition at line 342 of file rsp_idec.c.

◆ SDV

#define SDV    { "sdv", RSP_OP_SDV, OPNDS_VTB_BASE_OFFSET8 }

Definition at line 348 of file rsp_idec.c.

◆ SFV

#define SFV    { "sfv", RSP_OP_SFV, OPNDS_VTB_BASE_OFFSET16 }

Definition at line 360 of file rsp_idec.c.

◆ SH

#define SH    { "sh", RSP_OP_SH, OPNDS_RT_BASE_OFFSET }

Definition at line 406 of file rsp_idec.c.

◆ SHV

#define SHV    { "shv", RSP_OP_SHV, OPNDS_VTB_BASE_OFFSET16 }

Definition at line 358 of file rsp_idec.c.

◆ SIMM_DECODER

#define SIMM_DECODER    { RSP_OPND_SIMM, 0, 0, 0, 0, 0xffff, 0x8000, 0 }

Definition at line 93 of file rsp_idec.c.

◆ SLL

#define SLL    { "sll", RSP_OP_SLL, OPNDS_RD_RT_SA }

Definition at line 184 of file rsp_idec.c.

◆ SLLV

#define SLLV    { "sllv", RSP_OP_SLLV, OPNDS_RD_RT_RS }

Definition at line 190 of file rsp_idec.c.

◆ SLT

#define SLT    { "slt", RSP_OP_SLT, OPNDS_RD_RS_RT }

Definition at line 216 of file rsp_idec.c.

◆ SLTI

#define SLTI    { "slti", RSP_OP_SLTI, OPNDS_RT_RS_SIMM }

Definition at line 382 of file rsp_idec.c.

◆ SLTIU

#define SLTIU    { "sltiu", RSP_OP_SLTIU, OPNDS_RT_RS_SIMM }

Definition at line 384 of file rsp_idec.c.

◆ SLTU

#define SLTU    { "sltu", RSP_OP_SLTU, OPNDS_RD_RS_RT }

Definition at line 218 of file rsp_idec.c.

◆ SLV

#define SLV    { "slv", RSP_OP_SLV, OPNDS_VTB_BASE_OFFSET4 }

Definition at line 346 of file rsp_idec.c.

◆ SPECIAL

#define SPECIAL    { 0, 0, 0x3f }

Definition at line 504 of file rsp_idec.c.

◆ SPV

#define SPV    { "spv", RSP_OP_SPV, OPNDS_VTB_BASE_OFFSET8 }

Definition at line 354 of file rsp_idec.c.

◆ SQV

#define SQV    { "sqv", RSP_OP_SQV, OPNDS_VTB_BASE_OFFSET16 }

Definition at line 350 of file rsp_idec.c.

◆ SRA

#define SRA    { "sra", RSP_OP_SRA, OPNDS_RD_RT_SA }

Definition at line 188 of file rsp_idec.c.

◆ SRAV

#define SRAV    { "srav", RSP_OP_SRAV, OPNDS_RD_RT_RS }

Definition at line 194 of file rsp_idec.c.

◆ SRL

#define SRL    { "srl", RSP_OP_SRL, OPNDS_RD_RT_SA }

Definition at line 186 of file rsp_idec.c.

◆ SRLV

#define SRLV    { "srlv", RSP_OP_SRLV, OPNDS_RD_RT_RS }

Definition at line 192 of file rsp_idec.c.

◆ SRV

#define SRV    { "srv", RSP_OP_SRV, OPNDS_VTB_BASE_OFFSET8 }

Definition at line 352 of file rsp_idec.c.

◆ SSV

#define SSV    { "ssv", RSP_OP_SSV, OPNDS_VTB_BASE_OFFSET2 }

Definition at line 344 of file rsp_idec.c.

◆ STV

#define STV    { "stv", RSP_OP_STV, OPNDS_VTB_BASE_OFFSET16 }

Definition at line 364 of file rsp_idec.c.

◆ SUB

#define SUB    { "sub", RSP_OP_SUB, OPNDS_RD_RS_RT }

Definition at line 204 of file rsp_idec.c.

◆ SUBU

#define SUBU    { "subu", RSP_OP_SUBU, OPNDS_RD_RS_RT }

Definition at line 206 of file rsp_idec.c.

◆ SUV

#define SUV    { "suv", RSP_OP_SUV, OPNDS_VTB_BASE_OFFSET16 }

Definition at line 356 of file rsp_idec.c.

◆ SW

#define SW    { "sw", RSP_OP_SW, OPNDS_RT_BASE_OFFSET }

Definition at line 408 of file rsp_idec.c.

◆ SWC2

#define SWC2    { 256, 11, 0x1f }

Definition at line 516 of file rsp_idec.c.

◆ SWV

#define SWV    { "swv", RSP_OP_SWV, OPNDS_VTB_BASE_OFFSET16 }

Definition at line 362 of file rsp_idec.c.

◆ TARGET_DECODER

#define TARGET_DECODER    { RSP_OPND_TARGET, 0, 0x03ff, 2, 0, 0, 0, 0 }

Definition at line 99 of file rsp_idec.c.

◆ VABS

#define VABS    { "vabs", RSP_OP_VABS, OPNDS_VD_VS_VTE }

Definition at line 268 of file rsp_idec.c.

◆ VADD

#define VADD    { "vadd", RSP_OP_VADD, OPNDS_VD_VS_VTE }

Definition at line 264 of file rsp_idec.c.

◆ VADDC

#define VADDC    { "vaddc", RSP_OP_VADDC, OPNDS_VD_VS_VTE }

Definition at line 270 of file rsp_idec.c.

◆ VAND

#define VAND    { "vand", RSP_OP_VAND, OPNDS_VD_VS_VTE }

Definition at line 292 of file rsp_idec.c.

◆ VCH

#define VCH    { "vch", RSP_OP_VCH, OPNDS_VD_VS_VTE }

Definition at line 286 of file rsp_idec.c.

◆ VCL

#define VCL    { "vcl", RSP_OP_VCL, OPNDS_VD_VS_VTE }

Definition at line 284 of file rsp_idec.c.

◆ VCR

#define VCR    { "vcr", RSP_OP_VCR, OPNDS_VD_VS_VTE }

Definition at line 288 of file rsp_idec.c.

◆ VD_DECODER

#define VD_DECODER    { RSP_OPND_C2_VREG, 6, 0x1f, 0, 0, 0, 0, 0 }

Definition at line 109 of file rsp_idec.c.

◆ VD_SCALAR_DECODER

#define VD_SCALAR_DECODER    { RSP_OPND_C2_VREG_SCALAR, 6, 0x1f, 0, 11, 0x7, 0, 0 }

Definition at line 117 of file rsp_idec.c.

◆ VECTOP

#define VECTOP    { 160, 0, 0x3f }

Definition at line 512 of file rsp_idec.c.

◆ VEQ

#define VEQ    { "veq", RSP_OP_VEQ, OPNDS_VD_VS_VTE }

Definition at line 278 of file rsp_idec.c.

◆ VGE

#define VGE    { "vge", RSP_OP_VGE, OPNDS_VD_VS_VTE }

Definition at line 282 of file rsp_idec.c.

◆ VLT

#define VLT    { "vlt", RSP_OP_VLT, OPNDS_VD_VS_VTE }

Definition at line 276 of file rsp_idec.c.

◆ VMACF

#define VMACF    { "vmacf", RSP_OP_VMACF, OPNDS_VD_VS_VTE }

Definition at line 252 of file rsp_idec.c.

◆ VMACU

#define VMACU    { "vmacu", RSP_OP_VMACU, OPNDS_VD_VS_VTE }

Definition at line 254 of file rsp_idec.c.

◆ VMADH

#define VMADH    { "vmadh", RSP_OP_VMADH, OPNDS_VD_VS_VTE }

Definition at line 262 of file rsp_idec.c.

◆ VMADL

#define VMADL    { "vmadl", RSP_OP_VMADL, OPNDS_VD_VS_VTE }

Definition at line 256 of file rsp_idec.c.

◆ VMADM

#define VMADM    { "vmadm", RSP_OP_VMADM, OPNDS_VD_VS_VTE }

Definition at line 258 of file rsp_idec.c.

◆ VMADN

#define VMADN    { "vmadn", RSP_OP_VMADN, OPNDS_VD_VS_VTE }

Definition at line 260 of file rsp_idec.c.

◆ VMOV

#define VMOV    { "vmov", RSP_OP_VMOV, OPNDS_VDS_VTS }

Definition at line 310 of file rsp_idec.c.

◆ VMRG

#define VMRG    { "vmrg", RSP_OP_VMRG, OPNDS_VD_VS_VTE }

Definition at line 290 of file rsp_idec.c.

◆ VMUDH

#define VMUDH    { "vmudh", RSP_OP_VMUDH, OPNDS_VD_VS_VTE }

Definition at line 250 of file rsp_idec.c.

◆ VMUDL

#define VMUDL    { "vmudl", RSP_OP_VMUDL, OPNDS_VD_VS_VTE }

Definition at line 244 of file rsp_idec.c.

◆ VMUDM

#define VMUDM    { "vmudm", RSP_OP_VMUDM, OPNDS_VD_VS_VTE }

Definition at line 246 of file rsp_idec.c.

◆ VMUDN

#define VMUDN    { "vmudn", RSP_OP_VMUDN, OPNDS_VD_VS_VTE }

Definition at line 248 of file rsp_idec.c.

◆ VMULF

#define VMULF    { "vmulf", RSP_OP_VMULF, OPNDS_VD_VS_VTE }

Definition at line 240 of file rsp_idec.c.

◆ VMULU

#define VMULU    { "vmulu", RSP_OP_VMULU, OPNDS_VD_VS_VTE }

Definition at line 242 of file rsp_idec.c.

◆ VNAND

#define VNAND    { "vnand", RSP_OP_VNAND, OPNDS_VD_VS_VTE }

Definition at line 294 of file rsp_idec.c.

◆ VNE

#define VNE    { "vne", RSP_OP_VNE, OPNDS_VD_VS_VTE }

Definition at line 280 of file rsp_idec.c.

◆ VNOP

#define VNOP    { "vnop", RSP_OP_VNOP, OPNDS_NONE }

Definition at line 318 of file rsp_idec.c.

◆ VNOR

#define VNOR    { "vnor", RSP_OP_VNOR, OPNDS_VD_VS_VTE }

Definition at line 298 of file rsp_idec.c.

◆ VNXOR

#define VNXOR    { "vnxor", RSP_OP_VNXOR, OPNDS_VD_VS_VTE }

Definition at line 302 of file rsp_idec.c.

◆ VOR

#define VOR    { "vor", RSP_OP_VOR, OPNDS_VD_VS_VTE }

Definition at line 296 of file rsp_idec.c.

◆ VRCP

#define VRCP    { "vrcp", RSP_OP_VRCP, OPNDS_VDS_VTS }

Definition at line 304 of file rsp_idec.c.

◆ VRCPH

#define VRCPH    { "vrcph", RSP_OP_VRCPH, OPNDS_VDS_VTS }

Definition at line 308 of file rsp_idec.c.

◆ VRCPL

#define VRCPL    { "vrcpl", RSP_OP_VRCPL, OPNDS_VDS_VTS }

Definition at line 306 of file rsp_idec.c.

◆ VRSQ

#define VRSQ    { "vrsq", RSP_OP_VRSQ, OPNDS_VDS_VTS }

Definition at line 312 of file rsp_idec.c.

◆ VRSQH

#define VRSQH    { "vrsqh", RSP_OP_VRSQH, OPNDS_VDS_VTS }

Definition at line 316 of file rsp_idec.c.

◆ VRSQL

#define VRSQL    { "vrsql", RSP_OP_VRSQL, OPNDS_VDS_VTS }

Definition at line 314 of file rsp_idec.c.

◆ VS_BYTE_DECODER

#define VS_BYTE_DECODER    { RSP_OPND_C2_VREG_BYTE, 11, 0x1f, 0, 7, 0xf, 0, 0 }

Definition at line 113 of file rsp_idec.c.

◆ VS_DECODER

#define VS_DECODER    { RSP_OPND_C2_VREG, 11, 0x1f, 0, 0, 0, 0, 0 }

Definition at line 107 of file rsp_idec.c.

◆ VSAR

#define VSAR    { "vsar", RSP_OP_VSAR, OPNDS_VD_VS_C2_ACCU }

Definition at line 274 of file rsp_idec.c.

◆ VSUB

#define VSUB    { "vsub", RSP_OP_VSUB, OPNDS_VD_VS_VTE }

Definition at line 266 of file rsp_idec.c.

◆ VSUBC

#define VSUBC    { "vsubc", RSP_OP_VSUBC, OPNDS_VD_VS_VTE }

Definition at line 272 of file rsp_idec.c.

◆ VT_BYTE_DECODER

#define VT_BYTE_DECODER    { RSP_OPND_C2_VREG_BYTE, 16, 0x1f, 0, 7, 0xf, 0, 0 }

Definition at line 111 of file rsp_idec.c.

◆ VT_ELEMENT_DECODER

#define VT_ELEMENT_DECODER    { RSP_OPND_C2_VREG_ELEMENT, 16, 0x1f, 0, 21, 0xf, 0, 0 }

Definition at line 119 of file rsp_idec.c.

◆ VT_SCALAR_DECODER

#define VT_SCALAR_DECODER    { RSP_OPND_C2_VREG_SCALAR, 16, 0x1f, 0, 21, 0x7, 0, 0 }

Definition at line 115 of file rsp_idec.c.

◆ VXOR

#define VXOR    { "vxor", RSP_OP_VXOR, OPNDS_VD_VS_VTE }

Definition at line 300 of file rsp_idec.c.

◆ XOR

#define XOR    { "xor", RSP_OP_XOR, OPNDS_RD_RS_RT }

Definition at line 212 of file rsp_idec.c.

◆ XORI

#define XORI    { "xori", RSP_OP_XORI, OPNDS_RT_RS_ZIMM }

Definition at line 390 of file rsp_idec.c.

◆ ZIMM_DECODER

#define ZIMM_DECODER    { RSP_OPND_ZIMM, 0, 0xffff, 0, 0, 0, 0, 0 }

Definition at line 91 of file rsp_idec.c.

Function Documentation

◆ rsp_decode_priv()

static const rsp_instruction_priv* rsp_decode_priv ( ut32  iw)
static

Definition at line 546 of file rsp_idec.c.

546  {
547  const rsp_op_escape *escape;
548 
549  /* handle NOP pseudo instruction */
550  if (iw == 0) {
551  return &rsp_op_table[352];
552  }
553 
554  escape = &rsp_escapes_table[(iw >> 25)];
555  return &rsp_op_table[escape->offset + ((iw >> escape->shift) & escape->mask)];
556 }
rsp_op_table
static const rsp_instruction_priv rsp_op_table[]
Definition: rsp_idec.c:429
rsp_escapes_table
static const rsp_op_escape rsp_escapes_table[]
Definition: rsp_idec.c:527
rsp_op_escape
Definition: rsp_idec.c:521
rsp_op_escape::shift
ut8 shift
Definition: rsp_idec.c:523
rsp_op_escape::mask
ut8 mask
Definition: rsp_idec.c:524
rsp_op_escape::offset
ut16 offset
Definition: rsp_idec.c:522

References rsp_op_escape::mask, rsp_op_escape::offset, rsp_escapes_table, rsp_op_table, and rsp_op_escape::shift.

Referenced by rsp_instruction_decode().

◆ rsp_instruction_decode()

rsp_instruction rsp_instruction_decode ( ut64  pc,
ut32  iw 
)

Definition at line 587 of file rsp_idec.c.

587  {
588  int opnd;
589  const rsp_instruction_priv *priv = rsp_decode_priv(iw);
590 
591  rsp_instruction rz_instr;
592 
593  rz_instr.mnemonic = priv->mnemonic;
594  rz_instr.opcode = priv->opcode;
595  rz_instr.noperands = priv->noperands;
596  for (opnd = 0; opnd < rz_instr.noperands; opnd++) {
597  rz_instr.operands[opnd] = rsp_operand_decode(pc, iw, &priv->odecs[opnd]);
598  }
599 
600  return rz_instr;
601 }
rsp_decode_priv
static const rsp_instruction_priv * rsp_decode_priv(ut32 iw)
Definition: rsp_idec.c:546
rsp_operand_decode
static rsp_operand rsp_operand_decode(ut64 pc, ut32 iw, const rsp_operand_decoder *odec)
Definition: rsp_idec.c:565
rsp_instruction_priv
Definition: rsp_idec.c:422
rsp_instruction_priv::noperands
int noperands
Definition: rsp_idec.c:425
rsp_instruction_priv::opcode
rsp_opcode opcode
Definition: rsp_idec.c:424
rsp_instruction_priv::odecs
rsp_operand_decoder odecs[RSP_MAX_OPNDS]
Definition: rsp_idec.c:426
rsp_instruction_priv::mnemonic
const char * mnemonic
Definition: rsp_idec.c:423
rsp_instruction
Definition: rsp_idec.h:172
rsp_instruction::opcode
rsp_opcode opcode
Definition: rsp_idec.h:174
rsp_instruction::operands
rsp_operand operands[RSP_MAX_OPNDS]
Definition: rsp_idec.h:176
rsp_instruction::mnemonic
const char * mnemonic
Definition: rsp_idec.h:173
rsp_instruction::noperands
int noperands
Definition: rsp_idec.h:175

References rsp_instruction_priv::mnemonic, rsp_instruction::mnemonic, rsp_instruction_priv::noperands, rsp_instruction::noperands, rsp_instruction_priv::odecs, rsp_instruction_priv::opcode, rsp_instruction::opcode, rsp_instruction::operands, pc, rsp_decode_priv(), and rsp_operand_decode().

Referenced by disassemble(), and rsp_op().

◆ rsp_operand_decode()

static rsp_operand rsp_operand_decode ( ut64  pc,
ut32  iw,
const rsp_operand_decoder *  odec 
)
static

Definition at line 565 of file rsp_idec.c.

565  {
566  rsp_operand opnd;
567 
568  opnd.type = odec->type;
569  opnd.u = ((iw >> odec->u_shift) & odec->u_mask) << odec->u_lshift;
570  opnd.s = rsp_sign_extend((iw >> odec->s_shift) & odec->s_mask, odec->s_smask) << odec->s_lshift;
571 
572  /* handle targets/offsets IMEM addresses */
573  switch (opnd.type) {
574  case RSP_OPND_TARGET:
575  opnd.u = rsp_mem_addr(opnd.u, RSP_IMEM_OFFSET);
576  break;
577  case RSP_OPND_OFFSET:
578  /* +4 for delay slot */
579  opnd.u = rsp_mem_addr(pc + 4 + opnd.s, RSP_IMEM_OFFSET);
580  break;
581  default: /* do nothing */ break;
582  }
583 
584  return opnd;
585 }
rsp_sign_extend
static st32 rsp_sign_extend(st32 x, st32 m)
Definition: rsp_idec.c:558
rsp_mem_addr
static ut64 rsp_mem_addr(ut64 addr, ut64 base)
Definition: rsp_idec.h:23
RSP_IMEM_OFFSET
@ RSP_IMEM_OFFSET
Definition: rsp_idec.h:19
RSP_OPND_OFFSET
@ RSP_OPND_OFFSET
Definition: rsp_idec.h:150
RSP_OPND_TARGET
@ RSP_OPND_TARGET
Definition: rsp_idec.h:149
rsp_operand_decoder::type
rsp_operand_type type
Definition: rsp_idec.c:412
rsp_operand_decoder::u_shift
unsigned int u_shift
Definition: rsp_idec.c:413
rsp_operand_decoder::s_smask
ut32 s_smask
Definition: rsp_idec.c:418
rsp_operand_decoder::u_mask
ut32 u_mask
Definition: rsp_idec.c:414
rsp_operand_decoder::u_lshift
unsigned int u_lshift
Definition: rsp_idec.c:415
rsp_operand_decoder::s_lshift
unsigned int s_lshift
Definition: rsp_idec.c:419
rsp_operand_decoder::s_mask
ut32 s_mask
Definition: rsp_idec.c:417
rsp_operand_decoder::s_shift
unsigned int s_shift
Definition: rsp_idec.c:416
rsp_operand
Definition: rsp_idec.h:164
rsp_operand::s
st64 s
Definition: rsp_idec.h:167
rsp_operand::u
ut64 u
Definition: rsp_idec.h:166
rsp_operand::type
rsp_operand_type type
Definition: rsp_idec.h:165

References pc, RSP_IMEM_OFFSET, rsp_mem_addr(), RSP_OPND_OFFSET, RSP_OPND_TARGET, rsp_sign_extend(), rsp_operand::s, rsp_operand_decoder::s_lshift, rsp_operand_decoder::s_mask, rsp_operand_decoder::s_shift, rsp_operand_decoder::s_smask, rsp_operand_decoder::type, rsp_operand::type, rsp_operand::u, rsp_operand_decoder::u_lshift, rsp_operand_decoder::u_mask, and rsp_operand_decoder::u_shift.

Referenced by rsp_instruction_decode().

◆ rsp_sign_extend()

static st32 rsp_sign_extend ( st32  x,
st32  m 
)
inlinestatic

Definition at line 558 of file rsp_idec.c.

558  {
559  /* assume that bits of x above the m are already zeros
560  * which is the case when called from rsp_operand_decode
561  */
562  return (x ^ m) - m;
563 }
x
int x
Definition: mipsasm.c:20

References regress::m, and x.

Referenced by rsp_operand_decode().

Variable Documentation

◆ rsp_c0_reg_names

const char* rsp_c0_reg_names[]
Initial value:
= {
"$c0", "$c1", "$c2", "$c3", "$c4", "$c5", "$c6", "$c7",
"$c8", "$c9", "$c10", "$c11", "$c12", "$c13", "$c14", "$c15"
}

Definition at line 55 of file rsp_idec.c.

Referenced by rsp_op().

◆ rsp_c0_reg_soft_names

const char* rsp_c0_reg_soft_names[]
Initial value:
= {
"SP_MEM_ADDR", "SP_DRAM_ADDR", "SP_RD_LEN", "SP_WR_LEN",
"SP_STATUS", "SP_DMA_FULL", "SP_DMA_BUSY", "SP_SEMAPHORE",
"DPC_START", "DPC_END", "DPC_CURRENT", "DPC_STATUS",
"DPC_CLOCK", "DPC_BUF_BUSY", "DPC_PIPE_BUSY", "DPC_TMEM_BUSY"
}

Definition at line 13 of file rsp_idec.c.

Referenced by disassemble().

◆ rsp_c2_accu_names

const char* rsp_c2_accu_names[]
Initial value:
= {
"ACC_H", "ACC_M", "ACC_L", "???"
}

Definition at line 64 of file rsp_idec.c.

Referenced by disassemble().

◆ rsp_c2_creg_names

const char* rsp_c2_creg_names[]
Initial value:
= {
"$vco", "$vcc", "$vce", "???"
}

Definition at line 60 of file rsp_idec.c.

Referenced by disassemble().

◆ rsp_c2_vreg_element_names

const char* rsp_c2_vreg_element_names[]
Initial value:
= {
"", "[?]", "[0q]", "[1q]", "[0h]", "[1h]", "[2h]", "[3h]",
"[0]", "[1]", "[2]", "[3]", "[4]", "[5]", "[6]", "[7]"
}

Definition at line 75 of file rsp_idec.c.

Referenced by disassemble().

◆ rsp_c2_vreg_names

const char* rsp_c2_vreg_names[]
Initial value:
= {
"$v0", "$v1", "$v2", "$v3", "$v4", "$v5", "$v6", "$v7",
"$v8", "$v9", "$v10", "$v11", "$v12", "$v13", "$v14", "$v15",
"$v16", "$v17", "$v18", "$v19", "$v20", "$v21", "$v22", "$v23",
"$v24", "$v25", "$v26", "$v27", "$v28", "$v29", "$v30", "$v31"
}

Definition at line 68 of file rsp_idec.c.

Referenced by disassemble().

◆ rsp_escapes_table

const rsp_op_escape rsp_escapes_table[]
static
Initial value:
= {
SPECIAL, SPECIAL, REGIMM, REGIMM, MAIN, MAIN, MAIN, MAIN,
MAIN, MAIN, MAIN, MAIN, MAIN, MAIN, MAIN, MAIN,
MAIN, MAIN, MAIN, MAIN, MAIN, MAIN, MAIN, MAIN,
MAIN, MAIN, MAIN, MAIN, MAIN, MAIN, MAIN, MAIN,
COP0, COP0, MAIN, MAIN, COP2, VECTOP, MAIN, MAIN,
MAIN, MAIN, MAIN, MAIN, MAIN, MAIN, MAIN, MAIN,
MAIN, MAIN, MAIN, MAIN, MAIN, MAIN, MAIN, MAIN,
MAIN, MAIN, MAIN, MAIN, MAIN, MAIN, MAIN, MAIN,
MAIN, MAIN, MAIN, MAIN, MAIN, MAIN, MAIN, MAIN,
MAIN, MAIN, MAIN, MAIN, MAIN, MAIN, MAIN, MAIN,
MAIN, MAIN, MAIN, MAIN, MAIN, MAIN, MAIN, MAIN,
MAIN, MAIN, MAIN, MAIN, MAIN, MAIN, MAIN, MAIN,
MAIN, MAIN, MAIN, MAIN, LWC2, LWC2, MAIN, MAIN,
MAIN, MAIN, MAIN, MAIN, MAIN, MAIN, MAIN, MAIN,
MAIN, MAIN, MAIN, MAIN, SWC2, SWC2, MAIN, MAIN,
MAIN, MAIN, MAIN, MAIN, MAIN, MAIN, MAIN, MAIN
}
COP2
#define COP2
Definition: rsp_idec.c:510
MAIN
#define MAIN
Definition: rsp_idec.c:518
SWC2
#define SWC2
Definition: rsp_idec.c:516
SPECIAL
#define SPECIAL
Definition: rsp_idec.c:504
REGIMM
#define REGIMM
Definition: rsp_idec.c:506
LWC2
#define LWC2
Definition: rsp_idec.c:514
COP0
#define COP0
Definition: rsp_idec.c:508
VECTOP
#define VECTOP
Definition: rsp_idec.c:512

Definition at line 527 of file rsp_idec.c.

Referenced by rsp_decode_priv().

◆ rsp_gp_reg_names

const char* rsp_gp_reg_names[]

Definition at line 20 of file rsp_idec.c.

◆ rsp_gp_reg_soft_names

const char* rsp_gp_reg_soft_names[]
Initial value:
= {
"zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
"t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
}

Definition at line 6 of file rsp_idec.c.

Referenced by disassemble(), and rsp_op().

◆ rsp_op_table

const rsp_instruction_priv rsp_op_table[]
static

Definition at line 429 of file rsp_idec.c.

Referenced by rsp_decode_priv().