Rizin
unix-like reverse engineering framework and cli tools
Classes | Macros | Typedefs | Functions | Variables
avr_esil.c File Reference
#include "avr_esil.h"
#include <rz_crypto.h>

Go to the source code of this file.

Classes

struct  _cpu_const_tag
 
struct  _cpu_model_tag
 
struct  _opcodes_tag_
 

Macros

#define CPU_CONST_NONE   0
 
#define CPU_CONST_PARAM   1
 
#define CPU_CONST_REG   2
 
#define CPU_MODEL_DECL(model, pc, consts)
 
#define MASK(bits)   ((bits) == 32 ? 0xffffffff : (~((~((ut32)0)) << (bits))))
 
#define CPU_PC_MASK(cpu)   MASK((cpu)->pc)
 
#define CPU_PC_SIZE(cpu)   ((((cpu)->pc) >> 3) + ((((cpu)->pc) & 0x07) ? 1 : 0))
 
#define INST_HANDLER(OPCODE_NAME)   static void _inst__##OPCODE_NAME(RzAnalysis *analysis, RzAnalysisOp *op, const ut8 *buf, int len, int *fail, CPU_MODEL *cpu)
 
#define INST_DECL(OP, M, SL, C, SZ, T)    { #OP, (M), (SL), _inst__##OP, (C), (SZ), RZ_ANALYSIS_OP_TYPE_##T }
 
#define INST_LAST    { "unknown", 0, 0, (void *)0, 2, 1, RZ_ANALYSIS_OP_TYPE_UNK }
 
#define INST_CALL(OPCODE_NAME)   _inst__##OPCODE_NAME(analysis, op, buf, len, fail, cpu)
 
#define INST_INVALID
 
#define INST_ASSERT(x)
 
#define ESIL_A(e, ...)   rz_strbuf_appendf(&op->esil, e, ##__VA_ARGS__)
 
#define STR_BEGINS(in, s)   rz_str_ncasecmp(in, s, strlen(s))
 

Typedefs

typedef struct _cpu_const_tag CPU_CONST
 
typedef struct _cpu_model_tag CPU_MODEL
 
typedef void(* inst_handler_t) (RzAnalysis *analysis, RzAnalysisOp *op, const ut8 *buf, int len, int *fail, CPU_MODEL *cpu)
 
typedef struct _opcodes_tag_ OPCODE_DESC
 

Functions

static OPCODE_DESC * avr_op_analyze (RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, CPU_MODEL *cpu)
 
static CPU_MODEL * get_cpu_model (char *model)
 
static CPU_MODEL * __get_cpu_model_recursive (char *model)
 
static ut32 const_get_value (CPU_CONST *c)
 
static CPU_CONST * const_by_name (CPU_MODEL *cpu, int type, char *c)
 
static int __esil_pop_argument (RzAnalysisEsil *esil, ut64 *v)
 
static CPU_CONST * const_by_value (CPU_MODEL *cpu, int type, ut32 v)
 
static RzStrBuf * __generic_io_dest (ut8 port, int write, CPU_MODEL *cpu)
 
static void __generic_ld_st (RzAnalysisOp *op, char *mem, char ireg, int use_ramp, int prepostdec, int offset, int st)
 
static void __generic_pop (RzAnalysisOp *op, int sz)
 
static void __generic_push (RzAnalysisOp *op, int sz)
 
 INST_HANDLER (adc)
 
 INST_HANDLER (add)
 
 INST_HANDLER (adiw)
 
 INST_HANDLER (and)
 
 INST_HANDLER (andi)
 
 INST_HANDLER (asr)
 
 INST_HANDLER (bclr)
 
 INST_HANDLER (bld)
 
 INST_HANDLER (brbx)
 
 INST_HANDLER (break)
 
 INST_HANDLER (bset)
 
 INST_HANDLER (bst)
 
 INST_HANDLER (call)
 
 INST_HANDLER (cbi)
 
 INST_HANDLER (com)
 
 INST_HANDLER (cp)
 
 INST_HANDLER (cpc)
 
 INST_HANDLER (cpi)
 
 INST_HANDLER (cpse)
 
 INST_HANDLER (dec)
 
 INST_HANDLER (des)
 
 INST_HANDLER (eijmp)
 
 INST_HANDLER (eicall)
 
 INST_HANDLER (elpm)
 
 INST_HANDLER (eor)
 
 INST_HANDLER (fmul)
 
 INST_HANDLER (fmuls)
 
 INST_HANDLER (fmulsu)
 
 INST_HANDLER (ijmp)
 
 INST_HANDLER (icall)
 
 INST_HANDLER (in)
 
 INST_HANDLER (inc)
 
 INST_HANDLER (jmp)
 
 INST_HANDLER (lac)
 
 INST_HANDLER (las)
 
 INST_HANDLER (lat)
 
 INST_HANDLER (ld)
 
 INST_HANDLER (ldd)
 
 INST_HANDLER (ldi)
 
 INST_HANDLER (lds)
 
 INST_HANDLER (sts)
 
 INST_HANDLER (lpm)
 
 INST_HANDLER (lsr)
 
 INST_HANDLER (mov)
 
 INST_HANDLER (movw)
 
 INST_HANDLER (mul)
 
 INST_HANDLER (muls)
 
 INST_HANDLER (mulsu)
 
 INST_HANDLER (neg)
 
 INST_HANDLER (nop)
 
 INST_HANDLER (or)
 
 INST_HANDLER (ori)
 
 INST_HANDLER (out)
 
 INST_HANDLER (pop)
 
 INST_HANDLER (push)
 
 INST_HANDLER (rcall)
 
 INST_HANDLER (ret)
 
 INST_HANDLER (reti)
 
 INST_HANDLER (rjmp)
 
 INST_HANDLER (ror)
 
 INST_HANDLER (sbc)
 
 INST_HANDLER (sbci)
 
 INST_HANDLER (sub)
 
 INST_HANDLER (subi)
 
 INST_HANDLER (sbi)
 
 INST_HANDLER (sbix)
 
 INST_HANDLER (sbiw)
 
 INST_HANDLER (sbrx)
 
 INST_HANDLER (sleep)
 
 INST_HANDLER (spm)
 
 INST_HANDLER (st)
 
 INST_HANDLER (std)
 
 INST_HANDLER (swap)
 
static bool avr_custom_des (RzAnalysisEsil *esil)
 
static bool avr_custom_spm_page_erase (RzAnalysisEsil *esil)
 
static bool avr_custom_spm_page_fill (RzAnalysisEsil *esil)
 
static bool avr_custom_spm_page_write (RzAnalysisEsil *esil)
 
static int esil_avr_hook_reg_write (RzAnalysisEsil *esil, const char *name, ut64 *val)
 
RZ_IPI int rz_avr_esil_init (RzAnalysisEsil *esil)
 
RZ_IPI int rz_avr_esil_fini (RzAnalysisEsil *esil)
 
RZ_IPI void rz_avr_esil_opcode (RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len)
 

Variables

CPU_CONST cpu_reg_common []
 
CPU_CONST cpu_memsize_common []
 
CPU_CONST cpu_memsize_m640_m1280m_m1281_m2560_m2561 []
 
CPU_CONST cpu_memsize_xmega128a4u []
 
CPU_CONST cpu_pagesize_5_bits []
 
CPU_CONST cpu_pagesize_7_bits []
 
CPU_MODEL cpu_models []
 
OPCODE_DESC opcodes []
 

Detailed Description

Converts AVR instructions into ESIL statements

references:

Definition in file avr_esil.c.

Macro Definition Documentation

◆ CPU_CONST_NONE

#define CPU_CONST_NONE   0

Definition at line 26 of file avr_esil.c.

◆ CPU_CONST_PARAM

#define CPU_CONST_PARAM   1

Definition at line 27 of file avr_esil.c.

◆ CPU_CONST_REG

#define CPU_CONST_REG   2

Definition at line 28 of file avr_esil.c.

◆ CPU_MODEL_DECL

#define CPU_MODEL_DECL (   model,
  pc,
  consts 
)
Value:
{ \
model, \
pc, \
consts \
}

Definition at line 52 of file avr_esil.c.

◆ CPU_PC_MASK

#define CPU_PC_MASK (   cpu)    MASK((cpu)->pc)

Definition at line 59 of file avr_esil.c.

◆ CPU_PC_SIZE

#define CPU_PC_SIZE (   cpu)    ((((cpu)->pc) >> 3) + ((((cpu)->pc) & 0x07) ? 1 : 0))

Definition at line 60 of file avr_esil.c.

◆ ESIL_A

#define ESIL_A (   e,
  ... 
)    rz_strbuf_appendf(&op->esil, e, ##__VA_ARGS__)

Definition at line 81 of file avr_esil.c.

◆ INST_ASSERT

#define INST_ASSERT (   x)
Value:
{ \
if (!(x)) { \
INST_INVALID; \
} \
}
x
int x
Definition: mipsasm.c:20

Definition at line 74 of file avr_esil.c.

◆ INST_CALL

#define INST_CALL (   OPCODE_NAME)    _inst__##OPCODE_NAME(analysis, op, buf, len, fail, cpu)

Definition at line 68 of file avr_esil.c.

◆ INST_DECL

#define INST_DECL (   OP,
  M,
  SL,
  C,
  SZ,
  T 
)     { #OP, (M), (SL), _inst__##OP, (C), (SZ), RZ_ANALYSIS_OP_TYPE_##T }

Definition at line 63 of file avr_esil.c.

◆ INST_HANDLER

#define INST_HANDLER (   OPCODE_NAME)    static void _inst__##OPCODE_NAME(RzAnalysis *analysis, RzAnalysisOp *op, const ut8 *buf, int len, int *fail, CPU_MODEL *cpu)

Definition at line 62 of file avr_esil.c.

◆ INST_INVALID

#define INST_INVALID
Value:
{ \
*fail = 1; \
return; \
}
fail
#define fail(test)
Definition: tests.h:29

Definition at line 69 of file avr_esil.c.

◆ INST_LAST

#define INST_LAST    { "unknown", 0, 0, (void *)0, 2, 1, RZ_ANALYSIS_OP_TYPE_UNK }

Definition at line 65 of file avr_esil.c.

◆ MASK

#define MASK (   bits)    ((bits) == 32 ? 0xffffffff : (~((~((ut32)0)) << (bits))))

Definition at line 58 of file avr_esil.c.

◆ STR_BEGINS

#define STR_BEGINS (   in,
  s 
)    rz_str_ncasecmp(in, s, strlen(s))

Definition at line 83 of file avr_esil.c.

Typedef Documentation

◆ CPU_CONST

typedef struct _cpu_const_tag CPU_CONST

◆ CPU_MODEL

typedef struct _cpu_model_tag CPU_MODEL

◆ inst_handler_t

typedef void(* inst_handler_t) (RzAnalysis *analysis, RzAnalysisOp *op, const ut8 *buf, int len, int *fail, CPU_MODEL *cpu)

Definition at line 38 of file avr_esil.c.

◆ OPCODE_DESC

typedef struct _opcodes_tag_ OPCODE_DESC

Function Documentation

◆ __esil_pop_argument()

static int __esil_pop_argument ( RzAnalysisEsil *  esil,
ut64 *  v 
)
static

Definition at line 211 of file avr_esil.c.

211  {
212  char *t = rz_analysis_esil_pop(esil);
213  if (!t || !rz_analysis_esil_get_parm(esil, t, v)) {
214  free(t);
215  return false;
216  }
217  free(t);
218  return true;
219 }
v
const char * v
Definition: dsignal.c:12
rz_analysis_esil_get_parm
RZ_API int rz_analysis_esil_get_parm(RzAnalysisEsil *esil, const char *str, ut64 *num)
Definition: esil.c:483
rz_analysis_esil_pop
RZ_API char * rz_analysis_esil_pop(RzAnalysisEsil *esil)
Definition: esil.c:422
free
RZ_API void Ht_() free(HtName_(Ht) *ht)
Definition: ht_inc.c:130

References free(), rz_analysis_esil_get_parm(), rz_analysis_esil_pop(), and v.

Referenced by avr_custom_des(), avr_custom_spm_page_erase(), avr_custom_spm_page_fill(), and avr_custom_spm_page_write().

◆ __generic_io_dest()

static RzStrBuf* __generic_io_dest ( ut8  port,
int  write,
CPU_MODEL *  cpu 
)
static

Definition at line 237 of file avr_esil.c.

237  {
238  RzStrBuf *r = rz_strbuf_new("");
239  CPU_CONST *c = const_by_value(cpu, CPU_CONST_REG, port);
240  if (c != NULL) {
241  rz_strbuf_set(r, c->key);
242  if (write) {
243  rz_strbuf_append(r, ",=");
244  }
245  } else {
246  rz_strbuf_setf(r, "_io,%d,+,%s[1]", port, write ? "=" : "");
247  }
248 
249  return r;
250 }
cpu
static ut32 cpu[32]
Definition: analysis_or1k.c:21
const_by_value
static CPU_CONST * const_by_value(CPU_MODEL *cpu, int type, ut32 v)
Definition: avr_esil.c:221
CPU_CONST_REG
#define CPU_CONST_REG
Definition: avr_esil.c:28
NULL
#define NULL
Definition: cris-opc.c:27
r
#define r
Definition: crypto_rc6.c:12
write
static static fork write
Definition: sflib.h:33
rz_strbuf_set
RZ_API const char * rz_strbuf_set(RzStrBuf *sb, const char *s)
Definition: strbuf.c:153
rz_strbuf_append
RZ_API bool rz_strbuf_append(RzStrBuf *sb, const char *s)
Definition: strbuf.c:222
rz_strbuf_setf
RZ_API const char * rz_strbuf_setf(RzStrBuf *sb, const char *fmt,...) RZ_PRINTF_CHECK(2
rz_strbuf_new
RZ_API RzStrBuf * rz_strbuf_new(const char *s)
Definition: strbuf.c:8
c
#define c(i)
Definition: sha256.c:43
_cpu_const_tag
Definition: avr_esil.c:19

References c, const_by_value(), cpu, CPU_CONST_REG, NULL, r, rz_strbuf_append(), rz_strbuf_new(), rz_strbuf_set(), rz_strbuf_setf(), and write.

Referenced by INST_HANDLER().

◆ __generic_ld_st()

static void __generic_ld_st ( RzAnalysisOp *  op,
char *  mem,
char  ireg,
int  use_ramp,
int  prepostdec,
int  offset,
int  st 
)
static

Definition at line 252 of file avr_esil.c.

252  {
253  if (ireg) {
254  // preincrement index register
255  if (prepostdec < 0) {
256  ESIL_A("1,%c,-,%c,=,", ireg, ireg);
257  }
258  // set register index address
259  ESIL_A("%c,", ireg);
260  // add offset
261  if (offset != 0) {
262  ESIL_A("%d,+,", offset);
263  }
264  } else {
265  ESIL_A("%d,", offset);
266  }
267  if (use_ramp) {
268  ESIL_A("16,ramp%c,<<,+,", ireg ? ireg : 'd');
269  }
270  // set SRAM base address
271  ESIL_A("_%s,+,", mem);
272  // read/write from SRAM
273  ESIL_A("%s[1],", st ? "=" : "");
274  // postincrement index register
275  if (ireg && prepostdec > 0) {
276  ESIL_A("1,%c,+,%c,=,", ireg, ireg);
277  }
278 }
ESIL_A
#define ESIL_A(e,...)
Definition: avr_esil.c:81
offset
voidpf uLong offset
Definition: ioapi.h:144
mem
void * mem
Definition: libc.cpp:91

References ESIL_A, and mem.

Referenced by INST_HANDLER().

◆ __generic_pop()

static void __generic_pop ( RzAnalysisOp *  op,
int  sz 
)
static

Definition at line 280 of file avr_esil.c.

280  {
281  if (sz > 1) {
282  ESIL_A("1,sp,+,_ram,+,"); // calc SRAM(sp+1)
283  ESIL_A("[%d],", sz); // read value
284  ESIL_A("%d,sp,+=,", sz); // sp += item_size
285  } else {
286  ESIL_A("1,sp,+=," // increment stack pointer
287  "sp,_ram,+,[1],"); // load SRAM[sp]
288  }
289 }

References ESIL_A.

Referenced by INST_HANDLER().

◆ __generic_push()

static void __generic_push ( RzAnalysisOp *  op,
int  sz 
)
static

Definition at line 291 of file avr_esil.c.

291  {
292  ESIL_A("sp,_ram,+,"); // calc pointer SRAM(sp)
293  if (sz > 1) {
294  ESIL_A("-%d,+,", sz - 1); // dec SP by 'sz'
295  }
296  ESIL_A("=[%d],", sz); // store value in stack
297  ESIL_A("-%d,sp,+=,", sz); // decrement stack pointer
298 }

References ESIL_A.

Referenced by INST_HANDLER().

◆ __get_cpu_model_recursive()

static CPU_MODEL* __get_cpu_model_recursive ( char *  model)
static

Definition at line 153 of file avr_esil.c.

153  {
154  if (!model) {
155  return &cpu_models[0];
156  }
157  CPU_MODEL *cpu = NULL;
158 
159  for (cpu = cpu_models; cpu < cpu_models + ((sizeof(cpu_models) / sizeof(CPU_MODEL))) - 1; cpu++) {
160  if (!rz_str_casecmp(model, cpu->model)) {
161  break;
162  }
163  }
164 
165  // fix inheritance tree
166  if (cpu->inherit && !cpu->inherit_cpu_p) {
167  cpu->inherit_cpu_p = get_cpu_model(cpu->inherit);
168  if (!cpu->inherit_cpu_p) {
169  RZ_LOG_ERROR("Cannot inherit from unknown CPU model '%s'.\n", cpu->inherit);
170  }
171  }
172 
173  return cpu;
174 }
get_cpu_model
static CPU_MODEL * get_cpu_model(char *model)
Definition: avr_esil.c:176
cpu_models
CPU_MODEL cpu_models[]
Definition: avr_esil.c:130
RZ_LOG_ERROR
#define RZ_LOG_ERROR(fmtstr,...)
Definition: rz_log.h:58
rz_str_casecmp
RZ_API int rz_str_casecmp(const char *dst, const char *orig)
Definition: str.c:121
_cpu_model_tag
Definition: avr_esil.c:30

References cpu, cpu_models, get_cpu_model(), NULL, RZ_LOG_ERROR, and rz_str_casecmp().

Referenced by get_cpu_model().

◆ avr_custom_des()

static bool avr_custom_des ( RzAnalysisEsil *  esil)
static

Definition at line 1405 of file avr_esil.c.

1405  {
1406  if (!esil || !esil->analysis || !esil->analysis->reg) {
1407  return false;
1408  }
1409  ut64 arg;
1410  if (!__esil_pop_argument(esil, &arg)) {
1411  return false;
1412  }
1413  int round = arg;
1414  if (round < 0 || round > 15) {
1415  return false;
1416  }
1417  ut64 decrypt;
1418  rz_analysis_esil_reg_read(esil, "hf", &decrypt, NULL);
1419  if (decrypt) {
1420  round = 15 - round;
1421  }
1422  ut8 regs[0x10];
1423  static const char *reg_names[] = {
1424  "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1425  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
1426  };
1427  for (size_t i = 0; i < sizeof(regs); i++) {
1428  ut64 v = 0;
1429  rz_analysis_esil_reg_read(esil, reg_names[i], &v, NULL);
1430  regs[i] = v;
1431  }
1432 
1433  // Atmel's "AVR Instruction Set Manual" unfortunately is very ambiguous
1434  // regarding the details of this instruction and leaves the most interesting
1435  // questions open, especially what intermediate results are stored and how.
1436  // The below implementation has been developed based on observing the exact
1437  // results in the Simulator in Atmel/Microchip Studio emulating ATxmega128A1.
1438  // Things may seem very strange (especially hi/lo swapping), but it is all
1439  // intended to get the right behavior!
1440  ut32 buf_hi = rz_read_at_le32(regs, 0);
1441  ut32 buf_lo = rz_read_at_le32(regs, 4);
1442  ut32 key_orig_hi = rz_read_at_le32(regs, 8);
1443  ut32 key_orig_lo = rz_read_at_le32(regs, 0xc);
1444  ut32 key_lo = key_orig_lo;
1445  ut32 key_hi = key_orig_hi;
1446  rz_des_permute_key(&key_lo, &key_hi);
1447  int i = round;
1448  if (!decrypt) {
1449  rz_des_shift_key(i, false, &key_lo, &key_hi);
1450  }
1451  ut32 round_key_lo, round_key_hi;
1452  rz_des_pc2(&round_key_lo, &round_key_hi, key_lo, key_hi);
1453  if (decrypt) {
1454  rz_des_shift_key(i, true, &key_lo, &key_hi);
1455  }
1456  rz_des_permute_block0(&buf_lo, &buf_hi);
1457  rz_des_round(&buf_lo, &buf_hi, &round_key_lo, &round_key_hi);
1458  if (arg < 15) {
1459  rz_des_permute_block1(&buf_lo, &buf_hi);
1460  } else {
1461  rz_des_permute_block1(&buf_hi, &buf_lo);
1462  buf_lo ^= buf_hi;
1463  buf_hi ^= buf_lo;
1464  buf_lo ^= buf_hi;
1465  }
1466  rz_des_permute_key_inv(&key_lo, &key_hi); // un-permute so the rz_des_permute_key() in the next round will restore it
1467  key_lo |= key_orig_hi & 0x01010101; // restore the parity bits that got lost in PC-1
1468  key_hi |= key_orig_lo & 0x01010101;
1469 
1470  rz_write_at_le32(regs, buf_hi, 0);
1471  rz_write_at_le32(regs, buf_lo, 4);
1472  rz_write_at_le32(regs, key_lo, 8);
1473  rz_write_at_le32(regs, key_hi, 0xc);
1474  for (size_t i = 0; i < sizeof(regs); i++) {
1475  ut64 v = regs[i];
1476  rz_analysis_esil_reg_write(esil, reg_names[i], v);
1477  }
1478  return true;
1479 }
regs
static char * regs[]
Definition: analysis_sh.c:203
i
lzma_index ** i
Definition: index.h:629
arg
static const char * arg(RzAnalysis *a, csh *handle, cs_insn *insn, char *buf, int n)
Definition: arm_esil32.c:136
__esil_pop_argument
static int __esil_pop_argument(RzAnalysisEsil *esil, ut64 *v)
Definition: avr_esil.c:211
ut32
uint32_t ut32
Definition: demangler_util.h:31
rz_des_permute_key
RZ_API void rz_des_permute_key(ut32 *keylo, ut32 *keyhi)
Apply PC-1.
Definition: des.c:115
rz_des_pc2
RZ_API void rz_des_pc2(RZ_OUT ut32 *keylo, RZ_OUT ut32 *keyhi, RZ_IN ut32 deslo, RZ_IN ut32 deshi)
PC-2 permutation of a key.
Definition: des.c:247
rz_des_permute_block1
RZ_API void rz_des_permute_block1(ut32 *blocklo, ut32 *blockhi)
last permutation of the block
Definition: des.c:195
rz_des_shift_key
RZ_API void rz_des_shift_key(int i, bool decrypt, RZ_INOUT ut32 *deskeylo, RZ_INOUT ut32 *deskeyhi)
Apply the respective shift to the key for a given round.
Definition: des.c:225
rz_des_round
RZ_API void rz_des_round(RZ_OUT ut32 *buflo, RZ_OUT ut32 *bufhi, RZ_IN ut32 *roundkeylo, RZ_IN ut32 *roundkeyhi)
Apply the cipher function (f)
Definition: des.c:292
rz_des_permute_key_inv
RZ_API void rz_des_permute_key_inv(ut32 *keylo, ut32 *keyhi)
Inverse of rz_des_permute_key (PC-1)
Definition: des.c:153
rz_des_permute_block0
RZ_API void rz_des_permute_block0(ut32 *blocklo, ut32 *blockhi)
first permutation of the input block
Definition: des.c:171
rz_analysis_esil_reg_read
RZ_API int rz_analysis_esil_reg_read(RzAnalysisEsil *esil, const char *regname, ut64 *num, int *size)
Definition: esil.c:507
rz_analysis_esil_reg_write
RZ_API int rz_analysis_esil_reg_write(RzAnalysisEsil *esil, const char *dst, ut64 num)
Definition: esil.c:487
reg_names
static const char *const reg_names[]
Definition: hppa-dis.c:33
ut8
uint8_t ut8
Definition: lh5801.h:11
rz_read_at_le32
static ut32 rz_read_at_le32(const void *src, size_t offset)
Definition: rz_endian.h:248
rz_write_at_le32
static void rz_write_at_le32(void *dest, ut32 val, size_t offset)
Definition: rz_endian.h:261
rz_analysis_esil_t::analysis
RzAnalysis * analysis
Definition: rz_analysis.h:1043
rz_analysis_t::reg
RzReg * reg
Definition: rz_analysis.h:568
ut64
ut64(WINAPI *w32_GetEnabledXStateFeatures)()

References __esil_pop_argument(), rz_analysis_esil_t::analysis, arg(), i, NULL, rz_analysis_t::reg, reg_names, regs, rz_analysis_esil_reg_read(), rz_analysis_esil_reg_write(), rz_des_pc2(), rz_des_permute_block0(), rz_des_permute_block1(), rz_des_permute_key(), rz_des_permute_key_inv(), rz_des_round(), rz_des_shift_key(), rz_read_at_le32(), rz_write_at_le32(), ut64(), and v.

Referenced by rz_avr_esil_init().

◆ avr_custom_spm_page_erase()

static bool avr_custom_spm_page_erase ( RzAnalysisEsil *  esil)
static

Definition at line 1482 of file avr_esil.c.

1482  {
1483  CPU_MODEL *cpu;
1484  ut8 c;
1485  ut64 addr, page_size_bits, i;
1486 
1487  // sanity check
1488  if (!esil || !esil->analysis || !esil->analysis->reg) {
1489  return false;
1490  }
1491 
1492  // get target address
1493  if (!__esil_pop_argument(esil, &addr)) {
1494  return false;
1495  }
1496 
1497  // get details about current MCU and fix input address
1498  cpu = get_cpu_model(esil->analysis->cpu);
1499  page_size_bits = const_get_value(const_by_name(cpu, CPU_CONST_PARAM, "page_size"));
1500 
1501  // align base address to page_size_bits
1502  addr &= ~(MASK(page_size_bits));
1503 
1504  // perform erase
1505  // RZ_LOG_DEBUG("SPM_PAGE_ERASE %ld bytes @ 0x%08" PFMT64x ".\n", page_size, addr);
1506  c = 0xff;
1507  for (i = 0; i < (1ULL << page_size_bits); i++) {
1508  rz_analysis_esil_mem_write(
1509  esil, (addr + i) & CPU_PC_MASK(cpu), &c, 1);
1510  }
1511 
1512  return true;
1513 }
CPU_CONST_PARAM
#define CPU_CONST_PARAM
Definition: avr_esil.c:27
MASK
#define MASK(bits)
Definition: avr_esil.c:58
CPU_PC_MASK
#define CPU_PC_MASK(cpu)
Definition: avr_esil.c:59
const_get_value
static ut32 const_get_value(CPU_CONST *c)
Definition: avr_esil.c:190
const_by_name
static CPU_CONST * const_by_name(CPU_MODEL *cpu, int type, char *c)
Definition: avr_esil.c:194
rz_analysis_esil_mem_write
RZ_API int rz_analysis_esil_mem_write(RzAnalysisEsil *esil, ut64 addr, const ut8 *buf, int len)
Definition: esil.c:341
rz_analysis_t::cpu
char * cpu
Definition: rz_analysis.h:554
addr
static int addr
Definition: z80asm.c:58

References __esil_pop_argument(), addr, rz_analysis_esil_t::analysis, c, const_by_name(), const_get_value(), cpu, rz_analysis_t::cpu, CPU_CONST_PARAM, CPU_PC_MASK, get_cpu_model(), i, MASK, rz_analysis_t::reg, rz_analysis_esil_mem_write(), and ut64().

Referenced by rz_avr_esil_init().

◆ avr_custom_spm_page_fill()

static bool avr_custom_spm_page_fill ( RzAnalysisEsil *  esil)
static

Definition at line 1516 of file avr_esil.c.

1516  {
1517  CPU_MODEL *cpu;
1518  ut64 addr, page_size_bits, i;
1519  ut8 r0, r1;
1520 
1521  // sanity check
1522  if (!esil || !esil->analysis || !esil->analysis->reg) {
1523  return false;
1524  }
1525 
1526  // get target address, r0, r1
1527  if (!__esil_pop_argument(esil, &addr)) {
1528  return false;
1529  }
1530 
1531  if (!__esil_pop_argument(esil, &i)) {
1532  return false;
1533  }
1534  r0 = i;
1535 
1536  if (!__esil_pop_argument(esil, &i)) {
1537  return false;
1538  }
1539  r1 = i;
1540 
1541  // get details about current MCU and fix input address
1542  cpu = get_cpu_model(esil->analysis->cpu);
1543  page_size_bits = const_get_value(const_by_name(cpu, CPU_CONST_PARAM, "page_size"));
1544 
1545  // align and crop base address
1546  addr &= (MASK(page_size_bits) ^ 1);
1547 
1548  // perform write to temporary page
1549  // RZ_LOG_DEBUG("SPM_PAGE_FILL bytes (%02x, %02x) @ 0x%08" PFMT64x ".\n", r1, r0, addr);
1550  rz_analysis_esil_mem_write(esil, addr++, &r0, 1);
1551  rz_analysis_esil_mem_write(esil, addr++, &r1, 1);
1552 
1553  return true;
1554 }

References __esil_pop_argument(), addr, rz_analysis_esil_t::analysis, const_by_name(), const_get_value(), cpu, rz_analysis_t::cpu, CPU_CONST_PARAM, get_cpu_model(), i, MASK, r0, r1, rz_analysis_t::reg, rz_analysis_esil_mem_write(), and ut64().

Referenced by rz_avr_esil_init().

◆ avr_custom_spm_page_write()

static bool avr_custom_spm_page_write ( RzAnalysisEsil *  esil)
static

Definition at line 1557 of file avr_esil.c.

1557  {
1558  CPU_MODEL *cpu;
1559  char *t = NULL;
1560  ut64 addr, page_size_bits, tmp_page;
1561 
1562  // sanity check
1563  if (!esil || !esil->analysis || !esil->analysis->reg) {
1564  return false;
1565  }
1566 
1567  // get target address
1568  if (!__esil_pop_argument(esil, &addr)) {
1569  return false;
1570  }
1571 
1572  // get details about current MCU and fix input address and base address
1573  // of the internal temporary page
1574  cpu = get_cpu_model(esil->analysis->cpu);
1575  page_size_bits = const_get_value(const_by_name(cpu, CPU_CONST_PARAM, "page_size"));
1576  rz_analysis_esil_reg_read(esil, "_page", &tmp_page, NULL);
1577 
1578  // align base address to page_size_bits
1579  addr &= (~(MASK(page_size_bits)) & CPU_PC_MASK(cpu));
1580 
1581  // perform writing
1582  // RZ_LOG_DEBUG("SPM_PAGE_WRITE %ld bytes @ 0x%08" PFMT64x ".\n", page_size, addr);
1583  if (!(t = malloc(1 << page_size_bits))) {
1584  RZ_LOG_ERROR("Cannot alloc a buffer for copying the temporary page.\n");
1585  return false;
1586  }
1587  rz_analysis_esil_mem_read(esil, tmp_page, (ut8 *)t, 1 << page_size_bits);
1588  rz_analysis_esil_mem_write(esil, addr, (ut8 *)t, 1 << page_size_bits);
1589 
1590  return true;
1591 }
rz_analysis_esil_mem_read
RZ_API int rz_analysis_esil_mem_read(RzAnalysisEsil *esil, ut64 addr, ut8 *buf, int len)
Definition: esil.c:259
malloc
void * malloc(size_t size)
Definition: malloc.c:123

References __esil_pop_argument(), addr, rz_analysis_esil_t::analysis, const_by_name(), const_get_value(), cpu, rz_analysis_t::cpu, CPU_CONST_PARAM, CPU_PC_MASK, get_cpu_model(), malloc(), MASK, NULL, rz_analysis_t::reg, rz_analysis_esil_mem_read(), rz_analysis_esil_mem_write(), rz_analysis_esil_reg_read(), RZ_LOG_ERROR, and ut64().

Referenced by rz_avr_esil_init().

◆ avr_op_analyze()

static OPCODE_DESC * avr_op_analyze ( RzAnalysis *  analysis,
RzAnalysisOp *  op,
ut64  addr,
const ut8 *  buf,
int  len,
CPU_MODEL *  cpu 
)
static

Definition at line 1364 of file avr_esil.c.

1364  {
1365  OPCODE_DESC *opcode_desc;
1366  if (len < 2) {
1367  return NULL;
1368  }
1369  ut16 ins = (buf[1] << 8) | buf[0];
1370  int fail;
1371  char *t;
1372 
1373  // process opcode
1374  for (opcode_desc = opcodes; opcode_desc->handler; opcode_desc++) {
1375  if ((ins & opcode_desc->mask) == opcode_desc->selector) {
1376  fail = 0;
1377 
1378  // start void esil expression
1379  rz_strbuf_set(&op->esil, "");
1380 
1381  // handle opcode
1382  opcode_desc->handler(analysis, op, buf, len, &fail, cpu);
1383  if (fail) {
1384  break;
1385  } else if (opcode_desc->cycles <= 0) {
1386  opcode_desc->cycles = 2;
1387  }
1388 
1389  // remove trailing coma (COMETE LA COMA)
1390  t = rz_strbuf_get(&op->esil);
1391  if (t && strlen(t) > 1) {
1392  t += strlen(t) - 1;
1393  if (*t == ',') {
1394  *t = '\0';
1395  }
1396  }
1397 
1398  return opcode_desc;
1399  }
1400  }
1401 
1402  return NULL;
1403 }
len
size_t len
Definition: 6502dis.c:15
opcodes
OPCODE_DESC opcodes[]
Definition: avr_esil.c:1270
ut16
uint16_t ut16
Definition: demangler_util.h:30
buf
voidpf void * buf
Definition: ioapi.h:138
rz_strbuf_get
RZ_API char * rz_strbuf_get(RzStrBuf *sb)
Definition: strbuf.c:321
_opcodes_tag_
Definition: avr_esil.c:40
_opcodes_tag_::handler
inst_handler_t handler
Definition: avr_esil.c:44
_opcodes_tag_::cycles
int cycles
Definition: avr_esil.c:45
_opcodes_tag_::mask
int mask
Definition: avr_esil.c:42
_opcodes_tag_::selector
int selector
Definition: avr_esil.c:43
op
Definition: dis.c:32

References cpu, _opcodes_tag_::cycles, fail, _opcodes_tag_::handler, len, _opcodes_tag_::mask, NULL, opcodes, rz_strbuf_get(), rz_strbuf_set(), and _opcodes_tag_::selector.

Referenced by rz_avr_esil_opcode().

◆ const_by_name()

static CPU_CONST* const_by_name ( CPU_MODEL *  cpu,
int  type,
char *  c 
)
static

Definition at line 194 of file avr_esil.c.

194  {
195  CPU_CONST **clist, *citem;
196 
197  for (clist = cpu->consts; *clist; clist++) {
198  for (citem = *clist; citem->key; citem++) {
199  if (!strcmp(c, citem->key) && (type == CPU_CONST_NONE || type == citem->type)) {
200  return citem;
201  }
202  }
203  }
204  if (cpu->inherit_cpu_p) {
205  return const_by_name(cpu->inherit_cpu_p, type, c);
206  }
207  RZ_LOG_ERROR("Cannot find const key[%s].\n", c);
208  return NULL;
209 }
CPU_CONST_NONE
#define CPU_CONST_NONE
Definition: avr_esil.c:26
type
int type
Definition: mipsasm.c:17
_cpu_const_tag::type
ut8 type
Definition: avr_esil.c:21
_cpu_const_tag::key
const char *const key
Definition: avr_esil.c:20

References c, cpu, CPU_CONST_NONE, _cpu_const_tag::key, NULL, RZ_LOG_ERROR, _cpu_const_tag::type, and type.

Referenced by avr_custom_spm_page_erase(), avr_custom_spm_page_fill(), and avr_custom_spm_page_write().

◆ const_by_value()

static CPU_CONST* const_by_value ( CPU_MODEL *  cpu,
int  type,
ut32  v 
)
static

Definition at line 221 of file avr_esil.c.

221  {
222  CPU_CONST **clist, *citem;
223 
224  for (clist = cpu->consts; *clist; clist++) {
225  for (citem = *clist; citem && citem->key; citem++) {
226  if (citem->value == (MASK(citem->size * 8) & v) && (type == CPU_CONST_NONE || type == citem->type)) {
227  return citem;
228  }
229  }
230  }
231  if (cpu->inherit_cpu_p) {
232  return const_by_value(cpu->inherit_cpu_p, type, v);
233  }
234  return NULL;
235 }
_cpu_const_tag::size
ut8 size
Definition: avr_esil.c:23
_cpu_const_tag::value
ut32 value
Definition: avr_esil.c:22

References cpu, CPU_CONST_NONE, _cpu_const_tag::key, MASK, NULL, _cpu_const_tag::size, _cpu_const_tag::type, type, v, and _cpu_const_tag::value.

Referenced by __generic_io_dest().

◆ const_get_value()

static ut32 const_get_value ( CPU_CONST *  c)
static

Definition at line 190 of file avr_esil.c.

190  {
191  return c ? MASK(c->size * 8) & c->value : 0;
192 }

References c, and MASK.

Referenced by avr_custom_spm_page_erase(), avr_custom_spm_page_fill(), and avr_custom_spm_page_write().

◆ esil_avr_hook_reg_write()

static int esil_avr_hook_reg_write ( RzAnalysisEsil *  esil,
const char *  name,
ut64 *  val 
)
static

Definition at line 1593 of file avr_esil.c.

1593  {
1594  CPU_MODEL *cpu;
1595 
1596  if (!esil || !esil->analysis) {
1597  return 0;
1598  }
1599 
1600  // select cpu info
1601  cpu = get_cpu_model(esil->analysis->cpu);
1602 
1603  // crop registers and force certain values
1604  if (!strcmp(name, "pc")) {
1605  *val &= CPU_PC_MASK(cpu);
1606  } else if (!strcmp(name, "pcl")) {
1607  if (cpu->pc < 8) {
1608  *val &= MASK(8);
1609  }
1610  } else if (!strcmp(name, "pch")) {
1611  *val = cpu->pc > 8
1612  ? *val & MASK(cpu->pc - 8)
1613  : 0;
1614  }
1615 
1616  return 0;
1617 }
val
ut16 val
Definition: armass64_const.h:6
name
Definition: z80asm.h:102

References rz_analysis_esil_t::analysis, cpu, rz_analysis_t::cpu, CPU_PC_MASK, get_cpu_model(), MASK, and val.

Referenced by rz_avr_esil_init().

◆ get_cpu_model()

static CPU_MODEL * get_cpu_model ( char *  model)
static

Definition at line 176 of file avr_esil.c.

176  {
177  if (!model) {
178  return &cpu_models[0];
179  }
180  static CPU_MODEL *cpu = NULL;
181  // cached value?
182  if (cpu && !rz_str_casecmp(model, cpu->model)) {
183  return cpu;
184  }
185  // do the real search
186  cpu = __get_cpu_model_recursive(model);
187  return cpu;
188 }
__get_cpu_model_recursive
static CPU_MODEL * __get_cpu_model_recursive(char *model)
Definition: avr_esil.c:153

References __get_cpu_model_recursive(), cpu, cpu_models, NULL, and rz_str_casecmp().

Referenced by __get_cpu_model_recursive(), avr_custom_spm_page_erase(), avr_custom_spm_page_fill(), avr_custom_spm_page_write(), esil_avr_hook_reg_write(), and rz_avr_esil_opcode().

◆ INST_HANDLER() [1/73]

INST_HANDLER ( adc  )

Definition at line 300 of file avr_esil.c.

300  { // ADC Rd, Rr
301  // ROL Rd
302  if (len < 2) {
303  return;
304  }
305  const ut32 d = ((buf[0] >> 4) & 0xf) | ((buf[1] & 1) << 4);
306  const ut32 r = (buf[0] & 0xf) | ((buf[1] & 2) << 3);
307  ESIL_A("r%d,cf,+,r%d,+=,", r, d); // Rd + Rr + C
308  ESIL_A("$z,zf,:=,");
309  ESIL_A("3,$c,hf,:=,");
310  ESIL_A("7,$c,cf,:=,");
311  ESIL_A("7,$o,vf,:=,");
312  ESIL_A("0x80,r%d,&,!,!,nf,:=", d);
313 }
d
#define d(i)
Definition: sha256.c:44

References d, ESIL_A, len, and r.

◆ INST_HANDLER() [2/73]

INST_HANDLER ( add  )

Definition at line 315 of file avr_esil.c.

315  { // ADD Rd, Rr
316  // LSL Rd
317  if (len < 2) {
318  return;
319  }
320  const ut32 d = ((buf[0] >> 4) & 0xf) | ((buf[1] & 1) << 4);
321  const ut32 r = (buf[0] & 0xf) | ((buf[1] & 2) << 3);
322  ESIL_A("r%d,r%d,+=,", r, d); // Rd + Rr
323  ESIL_A("$z,zf,:=,");
324  ESIL_A("3,$c,hf,:=,");
325  ESIL_A("7,$c,cf,:=,");
326  ESIL_A("7,$o,vf,:=,");
327  ESIL_A("0x80,r%d,&,!,!,nf,:=,", d);
328 }

References d, ESIL_A, len, and r.

◆ INST_HANDLER() [3/73]

INST_HANDLER ( adiw  )

Definition at line 330 of file avr_esil.c.

330  { // ADIW Rd+1:Rd, K
331  if (len < 1) {
332  return;
333  }
334  const ut32 d = ((buf[0] & 0x30) >> 3) + 24;
335  const ut32 k = (buf[0] & 0x0f) | ((buf[0] >> 2) & 0x30);
336  ESIL_A("7,r%d,>>,", d + 1); // remember previous highest bit
337  ESIL_A("8,%d,8,r%d,<<,r%d,|,+,DUP,r%d,=,>>,r%d,=,", k, d + 1, d, d, d + 1); // Rd+1_Rd + k
338  // FLAGS:
339  ESIL_A("DUP,!,7,r%d,>>,&,vf,:=,", d + 1); // V
340  ESIL_A("r%d,0x80,&,!,!,nf,:=,", d + 1); // N
341  ESIL_A("8,r%d,<<,r%d,|,!,zf,:=,", d + 1, d); // Z
342  ESIL_A("7,r%d,>>,!,&,cf,:=,", d + 1); // C
343  ESIL_A("vf,nf,^,sf,:="); // S
344 }
k
const char * k
Definition: dsignal.c:11

References d, ESIL_A, k, and len.

◆ INST_HANDLER() [4/73]

INST_HANDLER ( and  )

Definition at line 346 of file avr_esil.c.

346  { // AND Rd, Rr
347  // TST Rd
348  if (len < 2) {
349  return;
350  }
351  const ut32 d = ((buf[0] >> 4) & 0xf) | ((buf[1] & 1) << 4);
352  const ut32 r = (buf[0] & 0xf) | ((buf[1] & 2) << 3);
353  ESIL_A("r%d,r%d,&=,$z,zf,:=,r%d,0x80,&,!,!,nf,:=,0,vf,:=,nf,sf,:=,", r, d, d);
354 }

References d, ESIL_A, len, and r.

◆ INST_HANDLER() [5/73]

INST_HANDLER ( andi  )

Definition at line 356 of file avr_esil.c.

356  { // ANDI Rd, K
357  // CBR Rd, K (= ANDI Rd, 1-K)
358  if (len < 2) {
359  return;
360  }
361  const ut32 d = ((buf[0] >> 4) & 0xf) + 16;
362  const ut32 k = ((buf[1] & 0x0f) << 4) | (buf[0] & 0x0f);
363  ESIL_A("%d,r%d,&=,$z,zf,:=,r%d,0x80,&,!,!,nf,:=,0,vf,:=,nf,sf,:=,", k, d, d);
364 }

References d, ESIL_A, k, and len.

◆ INST_HANDLER() [6/73]

INST_HANDLER ( asr  )

Definition at line 366 of file avr_esil.c.

366  { // ASR Rd
367  if (len < 2) {
368  return;
369  }
370  int d = ((buf[0] >> 4) & 0xf) | ((buf[1] & 1) << 4);
371  ESIL_A("r%d,0x1,&,cf,:=,0x1,r%d,>>,r%d,0x80,&,|,", d, d, d);
372  // 0: R=(Rd >> 1) | Rd7
373  ESIL_A("$z,zf,:=,"); // Z
374  ESIL_A("r%d,0x80,&,!,!,nf,:=,", d); // N
375  ESIL_A("nf,cf,^,vf,:=,"); // V
376  ESIL_A("nf,vf,^,sf,:=,"); // S
377 }

References d, ESIL_A, and len.

◆ INST_HANDLER() [7/73]

INST_HANDLER ( bclr  )

Definition at line 379 of file avr_esil.c.

379  { // BCLR s
380  // CLC
381  // CLH
382  // CLI
383  // CLN
384  // CLR
385  // CLS
386  // CLT
387  // CLV
388  // CLZ
389  if (len < 1) {
390  return;
391  }
392  int s = (buf[0] >> 4) & 0x7;
393  ESIL_A("0xff,%d,1,<<,^,sreg,&=,", s);
394 }
s
static RzSocket * s
Definition: rtr.c:28

References ESIL_A, len, and s.

◆ INST_HANDLER() [8/73]

INST_HANDLER ( bld  )

Definition at line 396 of file avr_esil.c.

396  { // BLD Rd, b
397  if (len < 2) {
398  return;
399  }
400  int d = ((buf[1] & 0x01) << 4) | ((buf[0] >> 4) & 0xf);
401  int b = buf[0] & 0x7;
402  ESIL_A("r%d,%d,1,<<,0xff,^,&,", d, b); // Rd/b = 0
403  ESIL_A("%d,tf,<<,|,r%d,=,", b, d); // Rd/b |= T<<b
404 }
b
#define b(i)
Definition: sha256.c:42

References b, d, ESIL_A, and len.

◆ INST_HANDLER() [9/73]

INST_HANDLER ( brbx  )

Definition at line 406 of file avr_esil.c.

406  { // BRBC s, k
407  // BRBS s, k
408  // BRBC/S 0: BRCC BRCS
409  // BRSH BRLO
410  // BRBC/S 1: BREQ BRNE
411  // BRBC/S 2: BRPL BRMI
412  // BRBC/S 3: BRVC BRVS
413  // BRBC/S 4: BRGE BRLT
414  // BRBC/S 5: BRHC BRHS
415  // BRBC/S 6: BRTC BRTS
416  // BRBC/S 7: BRID BRIE
417  if (len < 2) {
418  return;
419  }
420  int s = buf[0] & 0x7;
421  ut64 jump = op->addr + ((((buf[1] & 0x03) << 6) | ((buf[0] & 0xf8) >> 2)) | (buf[1] & 0x2 ? ~((int)0x7f) : 0)) + 2;
422  ESIL_A("%d,1,<<,sreg,&,", s); // SREG(s)
423  ESIL_A(buf[1] & 0x4
424  ? "!," // BRBC => branch if cleared
425  : "!,!,"); // BRBS => branch if set
426  ESIL_A("?{,%" PFMT64d ",pc,=,},", jump); // ?true => jmp
427 }
jump
int jump(int a, int b)
Definition: bcj_test.c:35
PFMT64d
#define PFMT64d
Definition: rz_types.h:394

References ESIL_A, jump(), len, PFMT64d, s, and ut64().

◆ INST_HANDLER() [10/73]

INST_HANDLER ( break  )

Definition at line 429 of file avr_esil.c.

429  { // BREAK
430  ESIL_A("BREAK");
431 }

References ESIL_A.

◆ INST_HANDLER() [11/73]

INST_HANDLER ( bset  )

Definition at line 433 of file avr_esil.c.

433  { // BSET s
434  // SEC
435  // SEH
436  // SEI
437  // SEN
438  // SER
439  // SES
440  // SET
441  // SEV
442  // SEZ
443  if (len < 1) {
444  return;
445  }
446  int s = (buf[0] >> 4) & 0x7;
447  ESIL_A("%d,1,<<,sreg,|=,", s);
448 }

References ESIL_A, len, and s.

◆ INST_HANDLER() [12/73]

INST_HANDLER ( bst  )

Definition at line 450 of file avr_esil.c.

450  { // BST Rd, b
451  if (len < 2) {
452  return;
453  }
454  ESIL_A("r%d,%d,1,<<,&,!,!,tf,=,", // tf = Rd/b
455  ((buf[1] & 1) << 4) | ((buf[0] >> 4) & 0xf), // r
456  buf[0] & 0x7); // b
457 }

References ESIL_A, and len.

◆ INST_HANDLER() [13/73]

INST_HANDLER ( call  )

Definition at line 459 of file avr_esil.c.

459  { // CALL k
460  if (len < 4) {
461  return;
462  }
463  ut64 jump = (buf[2] << 1) | (buf[3] << 9) | (buf[1] & 0x01) << 23 | (buf[0] & 0x01) << 17 | (buf[0] & 0xf0) << 14;
464  ESIL_A("pc,"); // esil is already pointing to
465  // next instruction (@ret)
466  __generic_push(op, CPU_PC_SIZE(cpu)); // push @ret in stack
467  ESIL_A("%" PFMT64d ",pc,=,", jump); // jump!
468 }
__generic_push
static void __generic_push(RzAnalysisOp *op, int sz)
Definition: avr_esil.c:291
CPU_PC_SIZE
#define CPU_PC_SIZE(cpu)
Definition: avr_esil.c:60

References __generic_push(), cpu, CPU_PC_SIZE, ESIL_A, jump(), len, PFMT64d, and ut64().

◆ INST_HANDLER() [14/73]

INST_HANDLER ( cbi  )

Definition at line 470 of file avr_esil.c.

470  { // CBI A, b
471  if (len < 1) {
472  return;
473  }
474  int a = (buf[0] >> 3) & 0x1f;
475  int b = buf[0] & 0x07;
476  RzStrBuf *io_port;
477 
478  // read port a and clear bit b
479  io_port = __generic_io_dest(a, 0, cpu);
480  ESIL_A("0xff,%d,1,<<,^,%s,&,", b, rz_strbuf_get(io_port));
481  rz_strbuf_free(io_port);
482 
483  // write result to port a
484  io_port = __generic_io_dest(a, 1, cpu);
485  ESIL_A("%s,", rz_strbuf_get(io_port));
486  rz_strbuf_free(io_port);
487 }
__generic_io_dest
static RzStrBuf * __generic_io_dest(ut8 port, int write, CPU_MODEL *cpu)
Definition: avr_esil.c:237
rz_strbuf_free
RZ_API void rz_strbuf_free(RzStrBuf *sb)
Definition: strbuf.c:358
a
#define a(i)
Definition: sha256.c:41

References __generic_io_dest(), a, b, cpu, ESIL_A, len, rz_strbuf_free(), and rz_strbuf_get().

◆ INST_HANDLER() [15/73]

INST_HANDLER ( com  )

Definition at line 489 of file avr_esil.c.

489  { // COM Rd
490  if (len < 2) {
491  return;
492  }
493  int r = ((buf[0] >> 4) & 0x0f) | ((buf[1] & 1) << 4);
494 
495  ESIL_A("r%d,0xff,-,r%d,=,$z,zf,:=,0,cf,:=,0,vf,:=,r%d,0x80,&,!,!,nf,:=,vf,nf,^,sf,:=", r, r, r);
496  // Rd = 0xFF-Rd
497 }

References ESIL_A, len, and r.

◆ INST_HANDLER() [16/73]

INST_HANDLER ( cp  )

Definition at line 499 of file avr_esil.c.

499  { // CP Rd, Rr
500  if (len < 2) {
501  return;
502  }
503  const ut32 r = (buf[0] & 0x0f) | ((buf[1] << 3) & 0x10);
504  const ut32 d = ((buf[0] >> 4) & 0x0f) | ((buf[1] << 4) & 0x10);
505  ESIL_A("r%d,r%d,-,0x80,&,!,!,nf,:=,", r, d);
506  ESIL_A("r%d,r%d,==,", r, d);
507  ESIL_A("$z,zf,:=,");
508  ESIL_A("3,$b,hf,:=,");
509  ESIL_A("8,$b,cf,:=,");
510  ESIL_A("7,$o,vf,:=,");
511  ESIL_A("vf,nf,^,sf,:=");
512 }

References d, ESIL_A, len, and r.

◆ INST_HANDLER() [17/73]

INST_HANDLER ( cpc  )

Definition at line 514 of file avr_esil.c.

514  { // CPC Rd, Rr
515  if (len < 2) {
516  return;
517  }
518  const ut32 r = (buf[0] & 0x0f) | ((buf[1] << 3) & 0x10);
519  const ut32 d = ((buf[0] >> 4) & 0x0f) | ((buf[1] << 4) & 0x10);
520 
521  ESIL_A("cf,r%d,+,DUP,r%d,-,0x80,&,!,!,nf,:=,", r, d); // Rd - Rr - C
522  ESIL_A("r%d,==,", d);
523  ESIL_A("$z,zf,:=,");
524  ESIL_A("3,$b,hf,:=,");
525  ESIL_A("8,$b,cf,:=,");
526  ESIL_A("7,$o,vf,:=,");
527  ESIL_A("vf,nf,^,sf,:=");
528 }

References d, ESIL_A, len, and r.

◆ INST_HANDLER() [18/73]

INST_HANDLER ( cpi  )

Definition at line 530 of file avr_esil.c.

530  { // CPI Rd, K
531  if (len < 2) {
532  return;
533  }
534  const ut32 d = ((buf[0] >> 4) & 0xf) + 16;
535  const ut32 k = (buf[0] & 0xf) | ((buf[1] & 0xf) << 4);
536  ESIL_A("%d,r%d,-,0x80,&,!,!,nf,:=,", k, d); // Rd - k
537  ESIL_A("%d,r%d,==,", k, d);
538  ESIL_A("$z,zf,:=,");
539  ESIL_A("3,$b,hf,:=,");
540  ESIL_A("8,$b,cf,:=,");
541  ESIL_A("7,$o,vf,:=,");
542  ESIL_A("vf,nf,^,sf,:=");
543 }

References d, ESIL_A, k, and len.

◆ INST_HANDLER() [19/73]

INST_HANDLER ( cpse  )

Definition at line 545 of file avr_esil.c.

545  { // CPSE Rd, Rr
546  if (len < 2) {
547  return;
548  }
549  int r = (buf[0] & 0xf) | ((buf[1] & 0x2) << 3);
550  int d = ((buf[0] >> 4) & 0xf) | ((buf[1] & 0x1) << 4);
551  ESIL_A("r%d,r%d,^,!,", r, d); // Rr == Rd
552  ESIL_A("?{,%" PFMT64d ",pc,=,},", op->jump); // ?true => jmp
553 }

References d, ESIL_A, len, PFMT64d, and r.

◆ INST_HANDLER() [20/73]

INST_HANDLER ( dec  )

Definition at line 555 of file avr_esil.c.

555  { // DEC Rd
556  if (len < 2) {
557  return;
558  }
559  const ut32 d = ((buf[0] >> 4) & 0xf) | ((buf[1] & 0x1) << 4);
560  ESIL_A("0x1,r%d,-=,", d); // Rd--
561  // FLAGS:
562  ESIL_A("7,$o,vf,:=,"); // V
563  ESIL_A("r%d,0x80,&,!,!,nf,:=,", d); // N
564  ESIL_A("$z,zf,:=,"); // Z
565  ESIL_A("vf,nf,^,sf,:=,"); // S
566 }

References d, ESIL_A, and len.

◆ INST_HANDLER() [21/73]

INST_HANDLER ( des  )

Definition at line 568 of file avr_esil.c.

568  { // DES k
569  int round = (buf[0] >> 4);
570  ESIL_A("%d,des", round);
571 }

References ESIL_A.

◆ INST_HANDLER() [22/73]

INST_HANDLER ( eicall  )

Definition at line 577 of file avr_esil.c.

577  { // EICALL
578  // push pc in stack
579  ESIL_A("pc,"); // esil is already pointing to
580  // next instruction (@ret)
581  __generic_push(op, CPU_PC_SIZE(cpu)); // push @ret in stack
582  // do a standard EIJMP
583  INST_CALL(eijmp);
584 }
INST_CALL
#define INST_CALL(OPCODE_NAME)
Definition: avr_esil.c:68

References __generic_push(), cpu, CPU_PC_SIZE, ESIL_A, and INST_CALL.

◆ INST_HANDLER() [23/73]

INST_HANDLER ( eijmp  )

Definition at line 573 of file avr_esil.c.

573  { // EIJMP
574  ESIL_A("1,z,16,eind,<<,+,<<,pc,=,");
575 }

References ESIL_A.

◆ INST_HANDLER() [24/73]

INST_HANDLER ( elpm  )

Definition at line 586 of file avr_esil.c.

586  { // ELPM
587  // ELPM Rd
588  // ELPM Rd, Z+
589  if (len < 2) {
590  return;
591  }
592  int d = ((buf[1] & 0xfe) == 0x90)
593  ? ((buf[1] & 1) << 4) | ((buf[0] >> 4) & 0xf) // Rd
594  : 0; // R0
595  ESIL_A("16,rampz,<<,z,+,_prog,+,[1],"); // read RAMPZ:Z
596  ESIL_A("r%d,=,", d); // Rd = [1]
597  if ((buf[1] & 0xfe) == 0x90 && (buf[0] & 0xf) == 0x7) {
598  ESIL_A("16,1,z,+,DUP,z,=,>>,1,&,rampz,+=,"); // ++(rampz:z)
599  }
600 }

References d, ESIL_A, and len.

◆ INST_HANDLER() [25/73]

INST_HANDLER ( eor  )

Definition at line 602 of file avr_esil.c.

602  { // EOR Rd, Rr
603  // CLR Rd
604  if (len < 2) {
605  return;
606  }
607  const ut32 d = ((buf[0] >> 4) & 0xf) | ((buf[1] & 1) << 4);
608  const ut32 r = (buf[0] & 0xf) | ((buf[1] & 2) << 3);
609  ESIL_A("r%d,r%d,^=,$z,zf,:=,0,vf,:=,r%d,0x80,&,!,!,nf,:=,nf,sf,:=", r, d, d);
610  // 0: Rd ^= Rr
611 }

References d, ESIL_A, len, and r.

◆ INST_HANDLER() [26/73]

INST_HANDLER ( fmul  )

Definition at line 613 of file avr_esil.c.

613  { // FMUL Rd, Rr
614  if (len < 1) {
615  return;
616  }
617  const ut32 d = ((buf[0] >> 4) & 0x7) + 16;
618  const ut32 r = (buf[0] & 0x7) + 16;
619 
620  ESIL_A("8,");
621  ESIL_A("0xffff,1,r%d,r%d,*,<<,&,DUP,r0,=,>>,r1,=,", r, d); // 0: r1_r0 = (rd * rr) << 1
622  ESIL_A("8,r1,<<,r0,|,DUP,0x8000,&,!,!,cf,:=,"); // C = R/15
623  ESIL_A("!,zf,:="); // Z = !R
624 }

References d, ESIL_A, len, and r.

◆ INST_HANDLER() [27/73]

INST_HANDLER ( fmuls  )

Definition at line 626 of file avr_esil.c.

626  { // FMULS Rd, Rr
627  if (len < 1) {
628  return;
629  }
630  const ut32 d = ((buf[0] >> 4) & 0x7) + 16;
631  const ut32 r = (buf[0] & 0x7) + 16;
632 
633  ESIL_A("8,1,");
634  ESIL_A("r%d,DUP,0x80,&,?{,0xff00,|,},", d); // sign extension Rd
635  ESIL_A("r%d,DUP,0x80,&,?{,0xff00,|,},", r); // sign extension Rr
636  ESIL_A("*,<<,DUP,r0,=,>>,r1,=,"); // 0: (Rd*Rr)<<1
637 
638  ESIL_A("8,r1,<<,r0,|,DUP,0x8000,&,!,!,cf,:=,"); // C = R/16
639  ESIL_A("!,zf,:="); // Z = !R
640 }

References d, ESIL_A, len, and r.

◆ INST_HANDLER() [28/73]

INST_HANDLER ( fmulsu  )

Definition at line 642 of file avr_esil.c.

642  { // FMULSU Rd, Rr
643  if (len < 1) {
644  return;
645  }
646  const ut32 d = ((buf[0] >> 4) & 0x7) + 16;
647  const ut32 r = (buf[0] & 0x7) + 16;
648 
649  ESIL_A("8,1,");
650  ESIL_A("r%d,DUP,0x80,&,?{,0xff00,|,},", d); // sign extension Rd
651  ESIL_A("r%d,*,<<,DUP,r0,=,>>,r1,=,", r); // 0: (Rd*Rr)<<1
652 
653  ESIL_A("8,r1,<<,r0,|,DUP,0x8000,&,!,!,cf,:=,"); // C = R/16
654  ESIL_A("!,zf,:="); // Z = !R
655 }

References d, ESIL_A, len, and r.

◆ INST_HANDLER() [29/73]

INST_HANDLER ( icall  )

Definition at line 662 of file avr_esil.c.

662  { // ICALL k
663  // push pc in stack
664  ESIL_A("pc,"); // esil is already pointing to
665  // next instruction (@ret)
666  __generic_push(op, CPU_PC_SIZE(cpu)); // push @ret in stack
667  // do a standard IJMP
668  INST_CALL(ijmp);
669 }

References __generic_push(), cpu, CPU_PC_SIZE, ESIL_A, and INST_CALL.

◆ INST_HANDLER() [30/73]

INST_HANDLER ( ijmp  )

Definition at line 657 of file avr_esil.c.

657  { // IJMP k
658  // read z for calculating jump address on runtime
659  ESIL_A("1,z,<<,pc,=,"); // jump!
660 }

References ESIL_A.

◆ INST_HANDLER() [31/73]

INST_HANDLER ( in  )

Definition at line 671 of file avr_esil.c.

671  { // IN Rd, A
672  if (len < 2) {
673  return;
674  }
675  int r = ((buf[0] >> 4) & 0x0f) | ((buf[1] & 0x01) << 4);
676  int a = (buf[0] & 0x0f) | ((buf[1] & 0x6) << 3);
677  RzStrBuf *io_src = __generic_io_dest(a, 0, cpu);
678  ESIL_A("%s,r%d,=,", rz_strbuf_get(io_src), r);
679  rz_strbuf_free(io_src);
680 }

References __generic_io_dest(), a, cpu, ESIL_A, len, r, rz_strbuf_free(), and rz_strbuf_get().

◆ INST_HANDLER() [32/73]

INST_HANDLER ( inc  )

Definition at line 682 of file avr_esil.c.

682  { // INC Rd
683  if (len < 2) {
684  return;
685  }
686  const ut32 d = ((buf[0] >> 4) & 0xf) | ((buf[1] & 0x1) << 4);
687  ESIL_A("1,r%d,+=,", d); // Rd++
688  // FLAGS:
689  ESIL_A("7,$o,vf,:=,"); // V
690  ESIL_A("r%d,0x80,&,!,!,nf,:=,", d); // N
691  ESIL_A("$z,zf,:=,"); // Z
692  ESIL_A("vf,nf,^,sf,:=,"); // S
693 }

References d, ESIL_A, and len.

◆ INST_HANDLER() [33/73]

INST_HANDLER ( jmp  )

Definition at line 695 of file avr_esil.c.

695  { // JMP k
696  if (len < 4) {
697  return;
698  }
699  ut64 jump = (buf[2] << 1) | (buf[3] << 9) | (buf[1] & 0x01) << 23 | (buf[0] & 0x01) << 17 | (buf[0] & 0xf0) << 14;
700  ESIL_A("%" PFMT64d ",pc,=,", jump); // jump!
701 }

References ESIL_A, jump(), len, PFMT64d, and ut64().

◆ INST_HANDLER() [34/73]

INST_HANDLER ( lac  )

Definition at line 703 of file avr_esil.c.

703  { // LAC Z, Rd
704  if (len < 2) {
705  return;
706  }
707  int d = ((buf[0] >> 4) & 0xf) | ((buf[1] & 0x1) << 4);
708 
709  // read memory from RAMPZ:Z
710  __generic_ld_st(op, "ram", 'z', 1, 0, 0, 0); // 0: Read (RAMPZ:Z)
711  ESIL_A("r%d,0xff,^,&,", d); // 0: (Z) & ~Rd
712  ESIL_A("DUP,r%d,=,", d); // Rd = [0]
713  __generic_ld_st(op, "ram", 'z', 1, 0, 0, 1); // Store in RAM
714 }
__generic_ld_st
static void __generic_ld_st(RzAnalysisOp *op, char *mem, char ireg, int use_ramp, int prepostdec, int offset, int st)
Definition: avr_esil.c:252

References __generic_ld_st(), d, ESIL_A, and len.

◆ INST_HANDLER() [35/73]

INST_HANDLER ( las  )

Definition at line 716 of file avr_esil.c.

716  { // LAS Z, Rd
717  if (len < 2) {
718  return;
719  }
720  int d = ((buf[0] >> 4) & 0xf) | ((buf[1] & 0x1) << 4);
721 
722  // read memory from RAMPZ:Z
723  __generic_ld_st(op, "ram", 'z', 1, 0, 0, 0); // 0: Read (RAMPZ:Z)
724  ESIL_A("r%d,|,", d); // 0: (Z) | Rd
725  ESIL_A("DUP,r%d,=,", d); // Rd = [0]
726  __generic_ld_st(op, "ram", 'z', 1, 0, 0, 1); // Store in RAM
727 }

References __generic_ld_st(), d, ESIL_A, and len.

◆ INST_HANDLER() [36/73]

INST_HANDLER ( lat  )

Definition at line 729 of file avr_esil.c.

729  { // LAT Z, Rd
730  if (len < 2) {
731  return;
732  }
733  int d = ((buf[0] >> 4) & 0xf) | ((buf[1] & 0x1) << 4);
734 
735  // read memory from RAMPZ:Z
736  __generic_ld_st(op, "ram", 'z', 1, 0, 0, 0); // 0: Read (RAMPZ:Z)
737  ESIL_A("r%d,^,", d); // 0: (Z) ^ Rd
738  ESIL_A("DUP,r%d,=,", d); // Rd = [0]
739  __generic_ld_st(op, "ram", 'z', 1, 0, 0, 1); // Store in RAM
740 }

References __generic_ld_st(), d, ESIL_A, and len.

◆ INST_HANDLER() [37/73]

INST_HANDLER ( ld  )

Definition at line 742 of file avr_esil.c.

742  { // LD Rd, X
743  // LD Rd, X+
744  // LD Rd, -X
745  if (len < 2) {
746  return;
747  }
748  // read memory
749  __generic_ld_st(
750  op, "ram",
751  'x', // use index register X
752  0, // no use RAMP* registers
753  (buf[0] & 0xf) == 0xe
754  ? -1 // pre decremented
755  : (buf[0] & 0xf) == 0xd
756  ? 1 // post incremented
757  : 0, // no increment
758  0, // offset always 0
759  0); // load operation (!st)
760  // load register
761  ESIL_A("r%d,=,", ((buf[1] & 1) << 4) | ((buf[0] >> 4) & 0xf));
762 }

References __generic_ld_st(), ESIL_A, and len.

◆ INST_HANDLER() [38/73]

INST_HANDLER ( ldd  )

Definition at line 764 of file avr_esil.c.

764  { // LD Rd, Y LD Rd, Z
765  // LD Rd, Y+ LD Rd, Z+
766  // LD Rd, -Y LD Rd, -Z
767  // LD Rd, Y+q LD Rd, Z+q
768  if (len < 2) {
769  return;
770  }
771  // calculate offset (this value only has sense in some opcodes,
772  // but we are optimistic and we calculate it always)
773  int offset = (buf[1] & 0x20) | ((buf[1] & 0xc) << 1) | (buf[0] & 0x7);
774  // read memory
775  __generic_ld_st(
776  op, "ram",
777  buf[0] & 0x8 ? 'y' : 'z', // index register Y/Z
778  0, // no use RAMP* registers
779  !(buf[1] & 0x10)
780  ? 0 // no increment
781  : buf[0] & 0x1
782  ? 1 // post incremented
783  : -1, // pre decremented
784  !(buf[1] & 0x10) ? offset : 0, // offset or not offset
785  0); // load operation (!st)
786  // load register
787  ESIL_A("r%d,=,", ((buf[1] & 1) << 4) | ((buf[0] >> 4) & 0xf));
788 }

References __generic_ld_st(), ESIL_A, and len.

◆ INST_HANDLER() [39/73]

INST_HANDLER ( ldi  )

Definition at line 790 of file avr_esil.c.

790  { // LDI Rd, K
791  if (len < 2) {
792  return;
793  }
794  int k = (buf[0] & 0xf) + ((buf[1] & 0xf) << 4);
795  int d = ((buf[0] >> 4) & 0xf) + 16;
796  ESIL_A("0x%x,r%d,=,", k, d);
797 }

References d, ESIL_A, k, and len.

◆ INST_HANDLER() [40/73]

INST_HANDLER ( lds  )

Definition at line 799 of file avr_esil.c.

799  { // LDS Rd, k
800  if (len < 4) {
801  return;
802  }
803  int d = ((buf[0] >> 4) & 0xf) | ((buf[1] & 0x1) << 4);
804  int k = (buf[3] << 8) | buf[2];
805 
806  // load value from RAMPD:k
807  __generic_ld_st(op, "ram", 0, 1, 0, k, 0);
808  ESIL_A("r%d,=,", d);
809 }

References __generic_ld_st(), d, ESIL_A, k, and len.

◆ INST_HANDLER() [41/73]

INST_HANDLER ( lpm  )

Definition at line 822 of file avr_esil.c.

822  { // LPM
823  // LPM Rd, Z
824  // LPM Rd, Z+
825  if (len < 2) {
826  return;
827  }
828  ut16 ins = (((ut16)buf[1]) << 8) | ((ut16)buf[0]);
829  // read program memory
830  __generic_ld_st(
831  op, "prog",
832  'z', // index register Y/Z
833  1, // use RAMP* registers
834  (ins & 0xfe0f) == 0x9005
835  ? 1 // post incremented
836  : 0, // no increment
837  0, // not offset
838  0); // load operation (!st)
839  // load register
840  ESIL_A("r%d,=,",
841  (ins == 0x95c8)
842  ? 0 // LPM (r0)
843  : ((buf[0] >> 4) & 0xf) // LPM Rd
844  | ((buf[1] & 0x1) << 4));
845 }

References __generic_ld_st(), ESIL_A, and len.

◆ INST_HANDLER() [42/73]

INST_HANDLER ( lsr  )

Definition at line 847 of file avr_esil.c.

847  { // LSR Rd
848  if (len < 2) {
849  return;
850  }
851  const ut32 d = ((buf[0] >> 4) & 0xf) | ((buf[1] & 1) << 4);
852  ESIL_A("r%d,0x1,&,cf,:=,", d); // C = Rd0
853  ESIL_A("1,r%d,>>=,", d); // 0: R=(Rd >> 1)
854  ESIL_A("$z,zf,:=,"); // Z
855  ESIL_A("0,nf,:=,"); // N
856  ESIL_A("cf,vf,:=,"); // V
857  ESIL_A("cf,sf,:=,"); // S
858 }

References d, ESIL_A, and len.

◆ INST_HANDLER() [43/73]

INST_HANDLER ( mov  )

Definition at line 860 of file avr_esil.c.

860  { // MOV Rd, Rr
861  if (len < 2) {
862  return;
863  }
864  const ut32 d = ((buf[1] << 4) & 0x10) | ((buf[0] >> 4) & 0x0f);
865  const ut32 r = ((buf[1] << 3) & 0x10) | (buf[0] & 0x0f);
866  ESIL_A("r%d,r%d,=,", r, d);
867 }

References d, ESIL_A, len, and r.

◆ INST_HANDLER() [44/73]

INST_HANDLER ( movw  )

Definition at line 869 of file avr_esil.c.

869  { // MOVW Rd+1:Rd, Rr+1:Rr
870  if (len < 1) {
871  return;
872  }
873  const ut32 d = (buf[0] & 0xf0) >> 3;
874  const ut32 r = (buf[0] & 0x0f) << 1;
875  ESIL_A("r%d,r%d,=,r%d,r%d,=,", r, d, r + 1, d + 1);
876 }

References d, ESIL_A, len, and r.

◆ INST_HANDLER() [45/73]

INST_HANDLER ( mul  )

Definition at line 878 of file avr_esil.c.

878  { // MUL Rd, Rr
879  if (len < 2) {
880  return;
881  }
882  const ut32 d = ((buf[1] << 4) & 0x10) | ((buf[0] >> 4) & 0x0f);
883  const ut32 r = ((buf[1] << 3) & 0x10) | (buf[0] & 0x0f);
884 
885  ESIL_A("8,r%d,r%d,*,DUP,r0,=,>>,r1,=,", r, d); // 0: r1_r0 = rd * rr
886  ESIL_A("8,r1,<<,r0,|,DUP,0x8000,&,!,!,cf,:=,"); // C = R/15
887  ESIL_A("!,zf,:="); // Z = !R
888 }

References d, ESIL_A, len, and r.

◆ INST_HANDLER() [46/73]

INST_HANDLER ( muls  )

Definition at line 890 of file avr_esil.c.

890  { // MULS Rd, Rr
891  if (len < 1) {
892  return;
893  }
894  const ut32 d = (buf[0] >> 4 & 0x0f) + 16;
895  const ut32 r = (buf[0] & 0x0f) + 16;
896 
897  ESIL_A("8,");
898  ESIL_A("r%d,DUP,0x80,&,?{,0xff00,|,},", d); // sign extension Rd
899  ESIL_A("r%d,DUP,0x80,&,?{,0xff00,|,},", r); // sign extension Rr
900  ESIL_A("*,DUP,r0,=,>>,r1,=,"); // 0: (Rd*Rr)
901 
902  ESIL_A("8,r1,<<,r0,|,DUP,0x8000,&,!,!,cf,:=,"); // C = R/16
903  ESIL_A("!,zf,:="); // Z = !R
904 }

References d, ESIL_A, len, and r.

◆ INST_HANDLER() [47/73]

INST_HANDLER ( mulsu  )

Definition at line 906 of file avr_esil.c.

906  { // MULSU Rd, Rr
907  if (len < 1) {
908  return;
909  }
910  const ut32 d = (buf[0] >> 4 & 0x07) + 16;
911  const ut32 r = (buf[0] & 0x07) + 16;
912 
913  ESIL_A("8,");
914  ESIL_A("r%d,DUP,0x80,&,?{,0xff00,|,},", d); // sign extension Rd
915  ESIL_A("r%d,*,DUP,r0,=,>>,r1,=,", r); // 0: (Rd*Rr)
916 
917  ESIL_A("8,r1,<<,r0,|,DUP,0x8000,&,!,!,cf,:=,"); // C = R/16
918  ESIL_A("!,zf,:="); // Z = !R
919 }

References d, ESIL_A, len, and r.

◆ INST_HANDLER() [48/73]

INST_HANDLER ( neg  )

Definition at line 921 of file avr_esil.c.

921  { // NEG Rd
922  if (len < 2) {
923  return;
924  }
925  int d = ((buf[0] >> 4) & 0xf) | ((buf[1] & 1) << 4);
926  ESIL_A("r%d,0x00,-,0xff,&,", d); // 0: (0-Rd)
927  ESIL_A("DUP,r%d,0xff,^,|,0x08,&,!,!,hf,=,", d); // H
928  ESIL_A("DUP,0x80,-,!,vf,=,"); // V
929  ESIL_A("DUP,0x80,&,!,!,nf,=,"); // N
930  ESIL_A("DUP,!,zf,=,"); // Z
931  ESIL_A("DUP,!,!,cf,=,"); // C
932  ESIL_A("vf,nf,^,sf,=,"); // S
933  ESIL_A("r%d,=,", d); // Rd = result
934 }

References d, ESIL_A, and len.

◆ INST_HANDLER() [49/73]

INST_HANDLER ( nop  )

Definition at line 936 of file avr_esil.c.

936  { // NOP
937  ESIL_A(",,");
938 }

References ESIL_A.

◆ INST_HANDLER() [50/73]

INST_HANDLER ( or  )

Definition at line 940 of file avr_esil.c.

940  { // OR Rd, Rr
941  if (len < 2) {
942  return;
943  }
944  int d = ((buf[0] >> 4) & 0xf) | ((buf[1] & 1) << 4);
945  int r = (buf[0] & 0xf) | ((buf[1] & 2) << 3);
946  ESIL_A("r%d,r%d,|=,", r, d); // 0: (Rd | Rr)
947  ESIL_A("$z,zf,:=,"); // Z
948  ESIL_A("r%d,&,!,!,nf,:=,", d); // N
949  ESIL_A("0,vf,:=,"); // V
950  ESIL_A("nf,sf,:="); // S
951 }

References d, ESIL_A, len, and r.

◆ INST_HANDLER() [51/73]

INST_HANDLER ( ori  )

Definition at line 953 of file avr_esil.c.

953  { // ORI Rd, K
954  // SBR Rd, K
955  if (len < 2) {
956  return;
957  }
958  const ut32 d = ((buf[0] >> 4) & 0xf) + 16;
959  const ut32 k = (buf[0] & 0xf) | ((buf[1] & 0xf) << 4);
960  ESIL_A("%d,r%d,|=,", k, d); // 0: (Rd | k)
961  ESIL_A("$z,zf,:=,"); // Z
962  ESIL_A("r%d,0x80,&,!,!,nf,:=,", d); // N
963  ESIL_A("0,vf,:=,"); // V
964  ESIL_A("nf,sf,:="); // S
965 }

References d, ESIL_A, k, and len.

◆ INST_HANDLER() [52/73]

INST_HANDLER ( out  )

Definition at line 967 of file avr_esil.c.

967  { // OUT A, Rr
968  if (len < 2) {
969  return;
970  }
971  int r = ((buf[0] >> 4) & 0x0f) | ((buf[1] & 0x01) << 4);
972  int a = (buf[0] & 0x0f) | ((buf[1] & 0x6) << 3);
973  RzStrBuf *io_dst = __generic_io_dest(a, 1, cpu);
974  ESIL_A("r%d,%s,", r, rz_strbuf_get(io_dst));
975  rz_strbuf_free(io_dst);
976 }

References __generic_io_dest(), a, cpu, ESIL_A, len, r, rz_strbuf_free(), and rz_strbuf_get().

◆ INST_HANDLER() [53/73]

INST_HANDLER ( pop  )

Definition at line 978 of file avr_esil.c.

978  { // POP Rd
979  if (len < 2) {
980  return;
981  }
982  int d = ((buf[1] & 0x1) << 4) | ((buf[0] >> 4) & 0xf);
983  __generic_pop(op, 1);
984  ESIL_A("r%d,=,", d); // store in Rd
985 }
__generic_pop
static void __generic_pop(RzAnalysisOp *op, int sz)
Definition: avr_esil.c:280

References __generic_pop(), d, ESIL_A, and len.

◆ INST_HANDLER() [54/73]

INST_HANDLER ( push  )

Definition at line 987 of file avr_esil.c.

987  { // PUSH Rr
988  if (len < 2) {
989  return;
990  }
991  int r = ((buf[1] & 0x1) << 4) | ((buf[0] >> 4) & 0xf);
992  ESIL_A("r%d,", r); // load Rr
993  __generic_push(op, 1); // push it into stack
994 }

References __generic_push(), ESIL_A, len, and r.

◆ INST_HANDLER() [55/73]

INST_HANDLER ( rcall  )

Definition at line 996 of file avr_esil.c.

996  { // RCALL k
997  if (len < 2) {
998  return;
999  }
1000  // target address
1001  ut64 jump = op->addr + ((((((buf[1] & 0xf) << 8) | buf[0]) << 1) | (((buf[1] & 0x8) ? ~((int)0x1fff) : 0))) + 2);
1002  // esil
1003  ESIL_A("pc,"); // esil already points to next
1004  // instruction (@ret)
1005  __generic_push(op, CPU_PC_SIZE(cpu)); // push @ret addr
1006  ESIL_A("%" PFMT64d ",pc,=,", jump); // jump!
1007 }

References __generic_push(), cpu, CPU_PC_SIZE, ESIL_A, jump(), len, PFMT64d, and ut64().

◆ INST_HANDLER() [56/73]

INST_HANDLER ( ret  )

Definition at line 1009 of file avr_esil.c.

1009  { // RET
1010  // esil
1011  __generic_pop(op, CPU_PC_SIZE(cpu));
1012  ESIL_A("pc,=,"); // jump!
1013 }

References __generic_pop(), cpu, CPU_PC_SIZE, and ESIL_A.

◆ INST_HANDLER() [57/73]

INST_HANDLER ( reti  )

Definition at line 1015 of file avr_esil.c.

1015  { // RETI
1016  // first perform a standard 'ret'
1017  INST_CALL(ret);
1018 
1019  // RETI: The I-bit is cleared by hardware after an interrupt
1020  // has occurred, and is set by the RETI instruction to enable
1021  // subsequent interrupts
1022  ESIL_A("1,if,=,");
1023 }

References ESIL_A, and INST_CALL.

◆ INST_HANDLER() [58/73]

INST_HANDLER ( rjmp  )

Definition at line 1025 of file avr_esil.c.

1025  { // RJMP k
1026  st32 loc = (((((buf[1] & 0xf) << 9) | (buf[0] << 1))) | (buf[1] & 0x8 ? ~(0x1fff) : 0)) + 2;
1027  ut64 jump = op->addr + loc;
1028  ESIL_A("%" PFMT64d ",pc,=,", jump);
1029 }
st32
#define st32
Definition: rz_types_base.h:12

References ESIL_A, jump(), PFMT64d, st32, and ut64().

◆ INST_HANDLER() [59/73]

INST_HANDLER ( ror  )

Definition at line 1031 of file avr_esil.c.

1031  { // ROR Rd
1032  const ut32 d = ((buf[0] >> 4) & 0x0f) | ((buf[1] << 4) & 0x10);
1033  ESIL_A("cf,nf,:=,"); // N
1034  ESIL_A("r%d,0x1,&,", d); // C
1035  ESIL_A("1,r%d,>>,7,cf,<<,|,r%d,=,cf,:=,", d, d); // 0: (Rd>>1) | (cf<<7)
1036  ESIL_A("$z,zf,:=,"); // Z
1037  ESIL_A("nf,cf,^,vf,:=,"); // V
1038  ESIL_A("vf,nf,^,sf,:="); // S
1039 }

References d, and ESIL_A.

◆ INST_HANDLER() [60/73]

INST_HANDLER ( sbc  )

Definition at line 1041 of file avr_esil.c.

1041  { // SBC Rd, Rr
1042  if (len < 2) {
1043  return;
1044  }
1045  const ut32 r = (buf[0] & 0x0f) | ((buf[1] & 0x2) << 3);
1046  const ut32 d = ((buf[0] >> 4) & 0xf) | ((buf[1] & 0x1) << 4);
1047 
1048  ESIL_A("cf,r%d,+,r%d,-=,", r, d); // 0: (Rd-Rr-C)
1049  ESIL_A("$z,zf,:=,");
1050  ESIL_A("3,$b,hf,:=,");
1051  ESIL_A("8,$b,cf,:=,");
1052  ESIL_A("7,$o,vf,:=,");
1053  ESIL_A("0x80,r%d,&,!,!,nf,:=,", d);
1054  ESIL_A("vf,nf,^,sf,:=");
1055 }

References d, ESIL_A, len, and r.

◆ INST_HANDLER() [61/73]

INST_HANDLER ( sbci  )

Definition at line 1057 of file avr_esil.c.

1057  { // SBCI Rd, k
1058  if (len < 2) {
1059  return;
1060  }
1061  const ut32 d = ((buf[0] >> 4) & 0xf) + 16;
1062  const ut32 k = ((buf[1] & 0xf) << 4) | (buf[0] & 0xf);
1063 
1064  ESIL_A("cf,%d,+,r%d,-=,", k, d); // 0: (Rd-k-C)
1065  ESIL_A("$z,zf,:=,");
1066  ESIL_A("3,$b,hf,:=,");
1067  ESIL_A("8,$b,cf,:=,");
1068  ESIL_A("7,$o,vf,:=,");
1069  ESIL_A("0x80,r%d,&,!,!,nf,:=,", d);
1070  ESIL_A("vf,nf,^,sf,:=");
1071 }

References d, ESIL_A, k, and len.

◆ INST_HANDLER() [62/73]

INST_HANDLER ( sbi  )

Definition at line 1105 of file avr_esil.c.

1105  { // SBI A, b
1106  if (len < 1) {
1107  return;
1108  }
1109  int a = (buf[0] >> 3) & 0x1f;
1110  int b = buf[0] & 0x07;
1111  RzStrBuf *io_port;
1112 
1113  // read port a and clear bit b
1114  io_port = __generic_io_dest(a, 0, cpu);
1115  ESIL_A("0xff,%d,1,<<,|,%s,&,", b, rz_strbuf_get(io_port));
1116  rz_strbuf_free(io_port);
1117 
1118  // write result to port a
1119  io_port = __generic_io_dest(a, 1, cpu);
1120  ESIL_A("%s,", rz_strbuf_get(io_port));
1121  rz_strbuf_free(io_port);
1122 }

References __generic_io_dest(), a, b, cpu, ESIL_A, len, rz_strbuf_free(), and rz_strbuf_get().

◆ INST_HANDLER() [63/73]

INST_HANDLER ( sbiw  )

Definition at line 1143 of file avr_esil.c.

1143  { // SBIW Rd+1:Rd, K
1144  if (len < 1) {
1145  return;
1146  }
1147  int d = ((buf[0] & 0x30) >> 3) + 24;
1148  int k = (buf[0] & 0xf) | ((buf[0] >> 2) & 0x30);
1149  ESIL_A("7,r%d,>>,", d + 1); // remember previous highest bit
1150  ESIL_A("8,%d,8,r%d,<<,r%d,|,-,DUP,r%d,=,>>,r%d,=,", k, d + 1, d, d, d + 1); // 0(Rd+1_Rd - k)
1151  ESIL_A("$z,zf,:=,");
1152  ESIL_A("DUP,!,7,r%d,>>,&,cf,:=,", d + 1); // C
1153  ESIL_A("r%d,0x80,&,!,!,nf,:=,", d + 1); // N
1154  ESIL_A("7,r%d,>>,!,&,vf,:=,", d + 1); // V
1155  ESIL_A("vf,nf,^,sf,:="); // S
1156 }

References d, ESIL_A, k, and len.

◆ INST_HANDLER() [64/73]

INST_HANDLER ( sbix  )

Definition at line 1124 of file avr_esil.c.

1124  { // SBIC A, b
1125  // SBIS A, b
1126  if (len < 2) {
1127  return;
1128  }
1129  int a = (buf[0] >> 3) & 0x1f;
1130  int b = buf[0] & 0x07;
1131  RzStrBuf *io_port;
1132 
1133  // read port a and clear bit b
1134  io_port = __generic_io_dest(a, 0, cpu);
1135  ESIL_A("%d,1,<<,%s,&,", b, rz_strbuf_get(io_port)); // IO(A,b)
1136  ESIL_A((buf[1] & 0xe) == 0xc
1137  ? "!," // SBIC => branch if 0
1138  : "!,!,"); // SBIS => branch if 1
1139  ESIL_A("?{,%" PFMT64d ",pc,=,},", op->jump); // ?true => jmp
1140  rz_strbuf_free(io_port);
1141 }

References __generic_io_dest(), a, b, cpu, ESIL_A, len, PFMT64d, rz_strbuf_free(), and rz_strbuf_get().

◆ INST_HANDLER() [65/73]

INST_HANDLER ( sbrx  )

Definition at line 1158 of file avr_esil.c.

1158  { // SBRC Rr, b
1159  // SBRS Rr, b
1160  if (len < 2) {
1161  return;
1162  }
1163  int b = buf[0] & 0x7;
1164  int r = ((buf[0] >> 4) & 0xf) | ((buf[1] & 0x01) << 4);
1165  ESIL_A("%d,1,<<,r%d,&,", b, r); // Rr(b)
1166  ESIL_A((buf[1] & 0xe) == 0xc
1167  ? "!," // SBRC => branch if cleared
1168  : "!,!,"); // SBRS => branch if set
1169  ESIL_A("?{,%" PFMT64d ",pc,=,},", op->jump); // ?true => jmp
1170 }

References b, ESIL_A, len, PFMT64d, and r.

◆ INST_HANDLER() [66/73]

INST_HANDLER ( sleep  )

Definition at line 1172 of file avr_esil.c.

1172  { // SLEEP
1173  ESIL_A("BREAK");
1174 }

References ESIL_A.

◆ INST_HANDLER() [67/73]

INST_HANDLER ( spm  )

Definition at line 1176 of file avr_esil.c.

1176  { // SPM Z+
1177  ut64 spmcsr;
1178 
1179  // read SPM Control Register (SPMCR)
1180  rz_analysis_esil_reg_read(analysis->esil, "spmcsr", &spmcsr, NULL);
1181 
1182  // clear SPMCSR
1183  ESIL_A("0x7c,spmcsr,&=,");
1184 
1185  // decide action depending on the old value of SPMCSR
1186  switch (spmcsr & 0x7f) {
1187  case 0x03: // PAGE ERASE
1188  // invoke SPM_CLEAR_PAGE (erases target page writing
1189  // the 0xff value
1190  ESIL_A("16,rampz,<<,z,+,"); // push target address
1191  ESIL_A("SPM_PAGE_ERASE,"); // do magic
1192  break;
1193 
1194  case 0x01: // FILL TEMPORARY BUFFER
1195  ESIL_A("r1,r0,"); // push data
1196  ESIL_A("z,"); // push target address
1197  ESIL_A("SPM_PAGE_FILL,"); // do magic
1198  break;
1199 
1200  case 0x05: // WRITE PAGE
1201  ESIL_A("16,rampz,<<,z,+,"); // push target address
1202  ESIL_A("SPM_PAGE_WRITE,"); // do magic
1203  break;
1204 
1205  default:
1206  RZ_LOG_DEBUG("SPM: I dont know what to do with SPMCSR %02" PFMT64x ".\n", spmcsr);
1207  break;
1208  }
1209 }
RZ_LOG_DEBUG
#define RZ_LOG_DEBUG(fmtstr,...)
Definition: rz_log.h:49
PFMT64x
#define PFMT64x
Definition: rz_types.h:393

References ESIL_A, NULL, PFMT64x, rz_analysis_esil_reg_read(), RZ_LOG_DEBUG, and ut64().

◆ INST_HANDLER() [68/73]

INST_HANDLER ( st  )

Definition at line 1211 of file avr_esil.c.

1211  { // ST X, Rr
1212  // ST X+, Rr
1213  // ST -X, Rr
1214  if (len < 2) {
1215  return;
1216  }
1217  // load register
1218  ESIL_A("r%d,", ((buf[1] & 1) << 4) | ((buf[0] >> 4) & 0xf));
1219  // write in memory
1220  __generic_ld_st(
1221  op, "ram",
1222  'x', // use index register X
1223  0, // no use RAMP* registers
1224  (buf[0] & 0xf) == 0xe
1225  ? -1 // pre decremented
1226  : (buf[0] & 0xf) == 0xd
1227  ? 1 // post increment
1228  : 0, // no increment
1229  0, // offset always 0
1230  1); // store operation (st)
1231 }

References __generic_ld_st(), ESIL_A, and len.

◆ INST_HANDLER() [69/73]

INST_HANDLER ( std  )

Definition at line 1233 of file avr_esil.c.

1233  { // ST Y, Rr ST Z, Rr
1234  // ST Y+, Rr ST Z+, Rr
1235  // ST -Y, Rr ST -Z, Rr
1236  // ST Y+q, Rr ST Z+q, Rr
1237  if (len < 2) {
1238  return;
1239  }
1240  // load register
1241  ESIL_A("r%d,", ((buf[1] & 1) << 4) | ((buf[0] >> 4) & 0xf));
1242  // write in memory
1243  __generic_ld_st(
1244  op, "ram",
1245  buf[0] & 0x8 ? 'y' : 'z', // index register Y/Z
1246  0, // no use RAMP* registers
1247  !(buf[1] & 0x10)
1248  ? 0 // no increment
1249  : buf[0] & 0x1
1250  ? 1 // post incremented
1251  : -1, // pre decremented
1252  !(buf[1] & 0x10)
1253  ? (buf[1] & 0x20) // offset
1254  | ((buf[1] & 0xc) << 1) | (buf[0] & 0x7)
1255  : 0, // no offset
1256  1); // load operation (!st)
1257 }

References __generic_ld_st(), ESIL_A, and len.

◆ INST_HANDLER() [70/73]

INST_HANDLER ( sts  )

Definition at line 811 of file avr_esil.c.

811  { // STS k, Rr
812  if (len < 4) {
813  return;
814  }
815  int r = ((buf[0] >> 4) & 0xf) | ((buf[1] & 0x1) << 4);
816  int k = (buf[3] << 8) | buf[2];
817 
818  ESIL_A("r%d,", r);
819  __generic_ld_st(op, "ram", 0, 1, 0, k, 1);
820 }

References __generic_ld_st(), ESIL_A, k, len, and r.

◆ INST_HANDLER() [71/73]

INST_HANDLER ( sub  )

Definition at line 1073 of file avr_esil.c.

1073  { // SUB Rd, Rr
1074  if (len < 2) {
1075  return;
1076  }
1077  const ut32 d = ((buf[0] >> 4) & 0xf) | ((buf[1] & 1) << 4);
1078  const ut32 r = (buf[0] & 0xf) | ((buf[1] & 2) << 3);
1079 
1080  ESIL_A("r%d,r%d,-=,", r, d); // 0: (Rd-k)
1081  ESIL_A("$z,zf,:=,");
1082  ESIL_A("3,$b,hf,:=,");
1083  ESIL_A("8,$b,cf,:=,");
1084  ESIL_A("7,$o,vf,:=,");
1085  ESIL_A("0x80,r%d,&,!,!,nf,:=,", d);
1086  ESIL_A("vf,nf,^,sf,:=");
1087 }

References d, ESIL_A, len, and r.

◆ INST_HANDLER() [72/73]

INST_HANDLER ( subi  )

Definition at line 1089 of file avr_esil.c.

1089  { // SUBI Rd, k
1090  if (len < 2) {
1091  return;
1092  }
1093  const ut32 d = ((buf[0] >> 4) & 0xf) + 16;
1094  const ut32 k = ((buf[1] & 0xf) << 4) | (buf[0] & 0xf);
1095 
1096  ESIL_A("%d,r%d,-=,", k, d); // 0: (Rd-k)
1097  ESIL_A("$z,zf,:=,");
1098  ESIL_A("3,$b,hf,:=,");
1099  ESIL_A("8,$b,cf,:=,");
1100  ESIL_A("7,$o,vf,:=,");
1101  ESIL_A("0x80,r%d,&,!,!,nf,:=,", d);
1102  ESIL_A("vf,nf,^,sf,:=");
1103 }

References d, ESIL_A, k, and len.

◆ INST_HANDLER() [73/73]

INST_HANDLER ( swap  )

Definition at line 1259 of file avr_esil.c.

1259  { // SWAP Rd
1260  if (len < 2) {
1261  return;
1262  }
1263  int d = ((buf[1] & 0x1) << 4) | ((buf[0] >> 4) & 0xf);
1264  ESIL_A("4,r%d,>>,0x0f,&,", d); // (Rd >> 4) & 0xf
1265  ESIL_A("4,r%d,<<,0xf0,&,", d); // (Rd >> 4) & 0xf
1266  ESIL_A("|,"); // S[0] | S[1]
1267  ESIL_A("r%d,=,", d); // Rd = result
1268 }

References d, ESIL_A, and len.

◆ rz_avr_esil_fini()

RZ_IPI int rz_avr_esil_fini ( RzAnalysisEsil *  esil)

Definition at line 1632 of file avr_esil.c.

1632  {
1633  return true;
1634 }

◆ rz_avr_esil_init()

RZ_IPI int rz_avr_esil_init ( RzAnalysisEsil *  esil)

Definition at line 1619 of file avr_esil.c.

1619  {
1620  if (!esil) {
1621  return false;
1622  }
1623  rz_analysis_esil_set_op(esil, "des", avr_custom_des, 0, 0, RZ_ANALYSIS_ESIL_OP_TYPE_CUSTOM); // better meta info plz
1624  rz_analysis_esil_set_op(esil, "SPM_PAGE_ERASE", avr_custom_spm_page_erase, 0, 0, RZ_ANALYSIS_ESIL_OP_TYPE_CUSTOM);
1625  rz_analysis_esil_set_op(esil, "SPM_PAGE_FILL", avr_custom_spm_page_fill, 0, 0, RZ_ANALYSIS_ESIL_OP_TYPE_CUSTOM);
1626  rz_analysis_esil_set_op(esil, "SPM_PAGE_WRITE", avr_custom_spm_page_write, 0, 0, RZ_ANALYSIS_ESIL_OP_TYPE_CUSTOM);
1627  esil->cb.hook_reg_write = esil_avr_hook_reg_write;
1628 
1629  return true;
1630 }
esil_avr_hook_reg_write
static int esil_avr_hook_reg_write(RzAnalysisEsil *esil, const char *name, ut64 *val)
Definition: avr_esil.c:1593
avr_custom_des
static bool avr_custom_des(RzAnalysisEsil *esil)
Definition: avr_esil.c:1405
avr_custom_spm_page_write
static bool avr_custom_spm_page_write(RzAnalysisEsil *esil)
Definition: avr_esil.c:1557
avr_custom_spm_page_erase
static bool avr_custom_spm_page_erase(RzAnalysisEsil *esil)
Definition: avr_esil.c:1482
avr_custom_spm_page_fill
static bool avr_custom_spm_page_fill(RzAnalysisEsil *esil)
Definition: avr_esil.c:1516
rz_analysis_esil_set_op
RZ_API bool rz_analysis_esil_set_op(RzAnalysisEsil *esil, const char *op, RzAnalysisEsilOpCb code, ut32 push, ut32 pop, ut32 type)
Definition: esil.c:110
RZ_ANALYSIS_ESIL_OP_TYPE_CUSTOM
@ RZ_ANALYSIS_ESIL_OP_TYPE_CUSTOM
Definition: rz_analysis.h:1184
rz_analysis_esil_callbacks_t::hook_reg_write
RzAnalysisEsilHookRegWriteCB hook_reg_write
Definition: rz_analysis.h:1038
rz_analysis_esil_t::cb
RzAnalysisEsilCallbacks cb
Definition: rz_analysis.h:1078

References avr_custom_des(), avr_custom_spm_page_erase(), avr_custom_spm_page_fill(), avr_custom_spm_page_write(), rz_analysis_esil_t::cb, esil_avr_hook_reg_write(), rz_analysis_esil_callbacks_t::hook_reg_write, RZ_ANALYSIS_ESIL_OP_TYPE_CUSTOM, and rz_analysis_esil_set_op().

◆ rz_avr_esil_opcode()

RZ_IPI void rz_avr_esil_opcode ( RzAnalysis *  analysis,
RzAnalysisOp *  op,
ut64  addr,
const ut8 *  buf,
int  len 
)

Definition at line 1636 of file avr_esil.c.

1636  {
1637  // select cpu info
1638  CPU_MODEL *cpu = get_cpu_model(analysis->cpu);
1639  avr_op_analyze(analysis, op, addr, buf, len, cpu);
1640 }
avr_op_analyze
static OPCODE_DESC * avr_op_analyze(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, CPU_MODEL *cpu)
Definition: avr_esil.c:1364

References addr, avr_op_analyze(), cpu, rz_analysis_t::cpu, get_cpu_model(), and len.

Referenced by avr_op().

Variable Documentation

◆ cpu_memsize_common

CPU_CONST cpu_memsize_common[]
Initial value:
= {
{ "eeprom_size", CPU_CONST_PARAM, 512, sizeof(ut32) },
{ "io_size", CPU_CONST_PARAM, 0x40, sizeof(ut32) },
{ "sram_start", CPU_CONST_PARAM, 0x60, sizeof(ut32) },
{ "sram_size", CPU_CONST_PARAM, 1024, sizeof(ut32) },
{ NULL, 0, 0, 0 },
}

Definition at line 96 of file avr_esil.c.

◆ cpu_memsize_m640_m1280m_m1281_m2560_m2561

CPU_CONST cpu_memsize_m640_m1280m_m1281_m2560_m2561[]
Initial value:
= {
{ "eeprom_size", CPU_CONST_PARAM, 512, sizeof(ut32) },
{ "io_size", CPU_CONST_PARAM, 0x1ff, sizeof(ut32) },
{ "sram_start", CPU_CONST_PARAM, 0x200, sizeof(ut32) },
{ "sram_size", CPU_CONST_PARAM, 0x2000, sizeof(ut32) },
{ NULL, 0, 0, 0 },
}

Definition at line 104 of file avr_esil.c.

◆ cpu_memsize_xmega128a4u

CPU_CONST cpu_memsize_xmega128a4u[]
Initial value:
= {
{ "eeprom_size", CPU_CONST_PARAM, 0x800, sizeof(ut32) },
{ "io_size", CPU_CONST_PARAM, 0x1000, sizeof(ut32) },
{ "sram_start", CPU_CONST_PARAM, 0x800, sizeof(ut32) },
{ "sram_size", CPU_CONST_PARAM, 0x2000, sizeof(ut32) },
{ NULL, 0, 0, 0 },
}

Definition at line 112 of file avr_esil.c.

◆ cpu_models

CPU_MODEL cpu_models[]
Initial value:
= {
{
.model = "ATmega640",
.pc = 15,
.consts = {
cpu_reg_common,
cpu_memsize_m640_m1280m_m1281_m2560_m2561,
cpu_pagesize_7_bits,
NULL },
},
{ .model = "ATxmega128a4u", .pc = 17, .consts = { cpu_reg_common, cpu_memsize_xmega128a4u, cpu_pagesize_7_bits, NULL } },
{ .model = "ATmega1280", .pc = 16, .inherit = "ATmega640" },
{ .model = "ATmega1281", .pc = 16, .inherit = "ATmega640" },
{ .model = "ATmega2560", .pc = 17, .inherit = "ATmega640" },
{ .model = "ATmega2561", .pc = 17, .inherit = "ATmega640" },
{ .model = "ATmega88", .pc = 8, .inherit = "ATmega8" },
{ .model = "ATmega8", .pc = 13, .consts = { cpu_reg_common, cpu_memsize_common, cpu_pagesize_5_bits, NULL } },
}
cpu_memsize_m640_m1280m_m1281_m2560_m2561
CPU_CONST cpu_memsize_m640_m1280m_m1281_m2560_m2561[]
Definition: avr_esil.c:104
cpu_memsize_common
CPU_CONST cpu_memsize_common[]
Definition: avr_esil.c:96
cpu_reg_common
CPU_CONST cpu_reg_common[]
Definition: avr_esil.c:88
cpu_pagesize_7_bits
CPU_CONST cpu_pagesize_7_bits[]
Definition: avr_esil.c:125
cpu_pagesize_5_bits
CPU_CONST cpu_pagesize_5_bits[]
Definition: avr_esil.c:120
cpu_memsize_xmega128a4u
CPU_CONST cpu_memsize_xmega128a4u[]
Definition: avr_esil.c:112

Definition at line 130 of file avr_esil.c.

Referenced by __get_cpu_model_recursive(), and get_cpu_model().

◆ cpu_pagesize_5_bits

CPU_CONST cpu_pagesize_5_bits[]
Initial value:
= {
{ "page_size", CPU_CONST_PARAM, 5, sizeof(ut8) },
{ NULL, 0, 0, 0 },
}
ut8
#define ut8
Definition: dcpu16.h:8

Definition at line 120 of file avr_esil.c.

◆ cpu_pagesize_7_bits

CPU_CONST cpu_pagesize_7_bits[]
Initial value:
= {
{ "page_size", CPU_CONST_PARAM, 7, sizeof(ut8) },
{ NULL, 0, 0, 0 },
}

Definition at line 125 of file avr_esil.c.

◆ cpu_reg_common

CPU_CONST cpu_reg_common[]
Initial value:
= {
{ "spl", CPU_CONST_REG, 0x3d, sizeof(ut8) },
{ "sph", CPU_CONST_REG, 0x3e, sizeof(ut8) },
{ "sreg", CPU_CONST_REG, 0x3f, sizeof(ut8) },
{ "spmcsr", CPU_CONST_REG, 0x37, sizeof(ut8) },
{ NULL, 0, 0, 0 },
}

Definition at line 88 of file avr_esil.c.

◆ opcodes

OPCODE_DESC opcodes[]

Definition at line 1270 of file avr_esil.c.

Referenced by avr_op_analyze(), diff_unified_append_ranges(), diff_unified_json_ranges(), free_opcode(), get_relocs(), reconstruct_chained_fixup(), rz_diff_opcodes_grouped_new(), rz_diff_opcodes_new(), rz_diff_unified_json(), and rz_diff_unified_text().