analysis_sh.c File Reference

#include <string.h>
#include <rz_types.h>
#include <rz_lib.h>
#include <rz_asm.h>
#include <rz_analysis.h>
#include "../arch/sh/sh_il.h"

Go to the source code of this file.

Macros
#define	API   static
#define	LONG_SIZE   4
#define	WORD_SIZE   2
#define	BYTE_SIZE   1
#define	BIT_32(x)   x ",0x80000000,&"
#define	S16_EXT(x)   x ",DUP,0x8000,&,?{,0xFFFFFFFFFFFF0000,|,}"
#define	S32_EXT(x)   x ",DUP,0x80000000,&,?{,0xFFFFFFFF00000000,|,}"
#define	IS_T   "sr,0x1,&,"
#define	SET_T   "0x1,sr,|="
#define	CLR_T   "0xFFFFFFFE,sr,&="
#define	IS_CLRT(x)   x == 0x0008
#define	IS_NOP(x)   x == 0x0009
#define	IS_RTS(x)   x == 0x000b
#define	IS_SETT(x)   x == 0x0018
#define	IS_DIV0U(x)   x == 0x0019
#define	IS_SLEEP(x)   x == 0x001b
#define	IS_CLRMAC(x)   x == 0x0028
#define	IS_RTE(x)   x == 0x002b
#define	IS_STCSR1(x)   (((x)&0xF0CF) == 0x0002)
#define	IS_BSRF(x)   ((x)&0xf0ff) == 0x0003
#define	IS_BRAF(x)   (((x)&0xf0ff) == 0x0023)
#define	IS_MOVB_REG_TO_R0REL(x)   (((x)&0xF00F) == 0x0004)
#define	IS_MOVW_REG_TO_R0REL(x)   (((x)&0xF00F) == 0x0005)
#define	IS_MOVL_REG_TO_R0REL(x)   (((x)&0xF00F) == 0x0006)
#define	IS_MULL(x)   (((x)&0xF00F) == 0x0007)
#define	IS_MOVB_R0REL_TO_REG(x)   (((x)&0xF00F) == 0x000C)
#define	IS_MOVW_R0REL_TO_REG(x)   (((x)&0xF00F) == 0x000D)
#define	IS_MOVL_R0REL_TO_REG(x)   (((x)&0xF00F) == 0x000E)
#define	IS_MACL(x)   (((x)&0xF00F) == 0x000F)
#define	IS_MOVT(x)   (((x)&0xF0FF) == 0x0029)
#define	IS_STSMACH(x)   (((x)&0xF0FF) == 0x000A)
#define	IS_STSMACL(x)   (((x)&0xF0FF) == 0x001A)
#define	IS_STSPR(x)   (((x)&0xF0FF) == 0x002A)
#define	IS_MOVB_REG_TO_REGREF(x)   (((x)&0xF00F) == 0x2000)
#define	IS_MOVW_REG_TO_REGREF(x)   (((x)&0xF00F) == 0x2001)
#define	IS_MOVL_REG_TO_REGREF(x)   (((x)&0xF00F) == 0x2002)
#define	IS_PUSHB(x)   (((x)&0xF00F) == 0x2004)
#define	IS_PUSHW(x)   (((x)&0xF00F) == 0x2005)
#define	IS_PUSHL(x)   (((x)&0xF00F) == 0x2006)
#define	IS_DIV0S(x)   (((x)&0xF00F) == 0x2007)
#define	IS_TSTRR(x)   (((x)&0xF00F) == 0x2008)
#define	IS_AND_REGS(x)   (((x)&0xF00F) == 0x2009)
#define	IS_XOR_REGS(x)   (((x)&0xF00F) == 0x200A)
#define	IS_OR_REGS(x)   (((x)&0xF00F) == 0x200B)
#define	IS_CMPSTR(x)   (((x)&0xF00F) == 0x200C)
#define	IS_XTRCT(x)   (((x)&0xF00F) == 0x200D)
#define	IS_MULUW(x)   (((x)&0xF00F) == 0x200E)
#define	IS_MULSW(x)   (((x)&0xF00F) == 0x200F)
#define	IS_CMPEQ(x)   (((x)&0xF00F) == 0x3000)
#define	IS_CMPHS(x)   (((x)&0xF00F) == 0x3002)
#define	IS_CMPGE(x)   (((x)&0xF00F) == 0x3003)
#define	IS_CMPHI(x)   (((x)&0xF00F) == 0x3006)
#define	IS_CMPGT(x)   (((x)&0xF00F) == 0x3007)
#define	IS_DIV1(x)   (((x)&0xF00F) == 0x3004)
#define	IS_DMULU(x)   (((x)&0xF00F) == 0x3005)
#define	IS_DMULS(x)   (((x)&0xF00F) == 0x300D)
#define	IS_SUB(x)   (((x)&0xF00F) == 0x3008)
#define	IS_SUBC(x)   (((x)&0xF00F) == 0x300A)
#define	IS_SUBV(x)   (((x)&0xF00F) == 0x300B)
#define	IS_ADD(x)   (((x)&0xF00F) == 0x300C)
#define	IS_ADDC(x)   (((x)&0xF00F) == 0x300E)
#define	IS_ADDV(x)   (((x)&0xF00F) == 0x300F)
#define	IS_MACW(x)   (((x)&0xF00F) == 0x400F)
#define	IS_JSR(x)   (((x)&0xf0ff) == 0x400b)
#define	IS_JMP(x)   (((x)&0xf0ff) == 0x402b)
#define	IS_CMPPL(x)   (((x)&0xf0ff) == 0x4015)
#define	IS_CMPPZ(x)   (((x)&0xf0ff) == 0x4011)
#define	IS_LDCSR(x)   (((x)&0xF0FF) == 0x400E)
#define	IS_LDCGBR(x)   (((x)&0xF0FF) == 0x401E)
#define	IS_LDCVBR(x)   (((x)&0xF0FF) == 0x402E)
#define	IS_LDCLSR(x)   (((x)&0xF0FF) == 0x4007)
#define	IS_LDCLSRGBR(x)   (((x)&0xF0FF) == 0x4017)
#define	IS_LDCLSRVBR(x)   (((x)&0xF0FF) == 0x4027)
#define	IS_LDSMACH(x)   (((x)&0xF0FF) == 0x400A)
#define	IS_LDSMACL(x)   (((x)&0xF0FF) == 0x401A)
#define	IS_LDSLMACH(x)   (((x)&0xF0FF) == 0x4006)
#define	IS_LDSLMACL(x)   (((x)&0xF0FF) == 0x4016)
#define	IS_LDSPR(x)   (((x)&0xF0FF) == 0x402A)
#define	IS_LDSLPR(x)   (((x)&0xF0FF) == 0x4026)
#define	IS_ROTCR(x)   (((x)&0xF0FF) == 0x4025)
#define	IS_ROTCL(x)   (((x)&0xF0FF) == 0x4024)
#define	IS_ROTL(x)   (((x)&0xF0FF) == 0x4004)
#define	IS_ROTR(x)   (((x)&0xF0FF) == 0x4005)
#define	IS_STSLMACL(x)   (((x)&0xF0FF) == 0x4012)
#define	IS_STSLMACH(x)   (((x)&0xF0FF) == 0x4002)
#define	IS_STCLSR(x)   (((x)&0xF0FF) == 0x4003)
#define	IS_STCLGBR(x)   (((x)&0xF0FF) == 0x4013)
#define	IS_STCLVBR(x)   (((x)&0xF0FF) == 0x4023)
#define	IS_STSLPR(x)   (((x)&0xF0FF) == 0x4022)
#define	IS_TASB(x)   (((x)&0xF0FF) == 0x401B)
#define	IS_DT(x)   (((x)&0xF0FF) == 0x4010)
#define	IS_MOVB_REGREF_TO_REG(x)   (((x)&0xF00F) == 0x6000)
#define	IS_MOVW_REGREF_TO_REG(x)   (((x)&0xF00F) == 0x6001)
#define	IS_MOVL_REGREF_TO_REG(x)   (((x)&0xF00F) == 0x6002)
#define	IS_MOV_REGS(x)   (((x)&0xf00f) == 0x6003)
#define	IS_MOVB_POP(x)   (((x)&0xF00F) == 0x6004)
#define	IS_MOVW_POP(x)   (((x)&0xF00F) == 0x6005)
#define	IS_MOVL_POP(x)   (((x)&0xF00F) == 0x6006)
#define	IS_NOT(x)   (((x)&0xF00F) == 0x6007)
#define	IS_SWAPB(x)   (((x)&0xF00F) == 0x6008)
#define	IS_SWAPW(x)   (((x)&0xF00F) == 0x6009)
#define	IS_NEG(x)   (((x)&0xF00F) == 0x600B)
#define	IS_NEGC(x)   (((x)&0xF00F) == 0x600A)
#define	IS_EXT(x)   (((x)&0xF00C) == 0x600C)
#define	IS_MOVB_R0_REGDISP(x)   (((x)&0xFF00) == 0x8000)
#define	IS_MOVW_R0_REGDISP(x)   (((x)&0xFF00) == 0x8100)
#define	IS_MOVB_REGDISP_R0(x)   (((x)&0xFF00) == 0x8400)
#define	IS_MOVW_REGDISP_R0(x)   (((x)&0xFF00) == 0x8500)
#define	IS_CMPIMM(x)   (((x)&0xFF00) == 0x8800)
#define	IS_BT(x)   (((x)&0xff00) == 0x8900)
#define	IS_BF(x)   (((x)&0xff00) == 0x8B00)
#define	IS_BTS(x)   (((x)&0xff00) == 0x8D00)
#define	IS_BFS(x)   (((x)&0xff00) == 0x8F00)
#define	IS_BT_OR_BF(x)   IS_BT(x) || IS_BTS(x) || IS_BF(x) || IS_BFS(x)
#define	IS_MOVB_R0_GBRREF(x)   (((x)&0xFF00) == 0xC000)
#define	IS_MOVW_R0_GBRREF(x)   (((x)&0xFF00) == 0xC100)
#define	IS_MOVL_R0_GBRREF(x)   (((x)&0xFF00) == 0xC200)
#define	IS_TRAP(x)   (((x)&0xFF00) == 0xC300)
#define	IS_MOVB_GBRREF_R0(x)   (((x)&0xFF00) == 0xC400)
#define	IS_MOVW_GBRREF_R0(x)   (((x)&0xFF00) == 0xC500)
#define	IS_MOVL_GBRREF_R0(x)   (((x)&0xFF00) == 0xC600)
#define	IS_MOVA_PCREL_R0(x)   (((x)&0xFF00) == 0xC700)
#define	IS_BINLOGIC_IMM_R0(x)   (((x)&0xFC00) == 0xC800)
#define	IS_BINLOGIC_IMM_GBR(x)   (((x)&0xFC00) == 0xCC00)
#define	GET_BRA_OFFSET(x)   ((x)&0x0fff)
#define	GET_BTF_OFFSET(x)   ((x)&0x00ff)
#define	GET_TARGET_REG(x)   (((x) >> 8) & 0x0f)
#define	GET_SOURCE_REG(x)   (((x) >> 4) & 0x0f)
#define	PC_IDX   16

Functions
static ut64	disarm_12bit_offset (RzAnalysisOp *op, unsigned int insoff)
static ut64	disarm_8bit_offset (ut64 pc, ut32 offs)
static RzAnalysisValue *	analysis_fill_ai_rg (RzAnalysis *analysis, int idx)
static RzAnalysisValue *	analysis_fill_im (RzAnalysis *analysis, st32 v)
static RzAnalysisValue *	analysis_fill_reg_disp_mem (RzAnalysis *analysis, int reg, st64 delta, st64 size)
static RzAnalysisValue *	analysis_fill_reg_ref (RzAnalysis *analysis, int reg, st64 size)
static RzAnalysisValue *	analysis_fill_r0_reg_ref (RzAnalysis *analysis, int reg, st64 size)
static RzAnalysisValue *	analysis_pcrel_disp_mov (RzAnalysis *analysis, RzAnalysisOp *op, ut8 disp, int size)
static RzAnalysisValue *	analysis_regrel_jump (RzAnalysis *analysis, RzAnalysisOp *op, ut8 reg)
static int	first_nibble_is_0 (RzAnalysis *analysis, RzAnalysisOp *op, ut16 code)
static int	movl_reg_rdisp (RzAnalysis *analysis, RzAnalysisOp *op, ut16 code)
static int	first_nibble_is_2 (RzAnalysis *analysis, RzAnalysisOp *op, ut16 code)
static int	first_nibble_is_3 (RzAnalysis *analysis, RzAnalysisOp *op, ut16 code)
static int	first_nibble_is_4 (RzAnalysis *analysis, RzAnalysisOp *op, ut16 code)
static int	movl_rdisp_reg (RzAnalysis *analysis, RzAnalysisOp *op, ut16 code)
static int	first_nibble_is_6 (RzAnalysis *analysis, RzAnalysisOp *op, ut16 code)
static int	add_imm (RzAnalysis *analysis, RzAnalysisOp *op, ut16 code)
static int	first_nibble_is_8 (RzAnalysis *analysis, RzAnalysisOp *op, ut16 code)
static int	movw_pcdisp_reg (RzAnalysis *analysis, RzAnalysisOp *op, ut16 code)
static int	bra (RzAnalysis *analysis, RzAnalysisOp *op, ut16 code)
static int	bsr (RzAnalysis *analysis, RzAnalysisOp *op, ut16 code)
static int	first_nibble_is_c (RzAnalysis *analysis, RzAnalysisOp *op, ut16 code)
static int	movl_pcdisp_reg (RzAnalysis *analysis, RzAnalysisOp *op, ut16 code)
static int	mov_imm_reg (RzAnalysis *analysis, RzAnalysisOp *op, ut16 code)
static int	fpu_insn (RzAnalysis *analysis, RzAnalysisOp *op, ut16 code)
static int	sh_op (RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const ut8 *data, int len, RzAnalysisOpMask mask)
static RZ_OWN char *	sh_get_reg_profile (RzAnalysis *analysis)
static int	archinfo (RzAnalysis *analysis, int q)

Variables
static char *	regs [] = { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", "pc" }
static int(*	first_nibble_decode [])(RzAnalysis *, RzAnalysisOp *, ut16)
RzAnalysisPlugin	rz_analysis_plugin_sh
RZ_API RzLibStruct	rizin_plugin

Macro Definition Documentation

API

#define API   static

Definition at line 11 of file analysis_sh.c.

BIT_32

#define BIT_32

(

x

)

x ",0x80000000,&"

Definition at line 24 of file analysis_sh.c.

BYTE_SIZE

#define BYTE_SIZE   1

Definition at line 15 of file analysis_sh.c.

CLR_T

#define CLR_T   "0xFFFFFFFE,sr,&="

Definition at line 29 of file analysis_sh.c.

GET_BRA_OFFSET

#define GET_BRA_OFFSET

(

x

)

((x)&0x0fff)

Definition at line 171 of file analysis_sh.c.

GET_BTF_OFFSET

#define GET_BTF_OFFSET

(

x

)

((x)&0x00ff)

Definition at line 172 of file analysis_sh.c.

GET_SOURCE_REG

#define GET_SOURCE_REG

(

x

)

(((x) >> 4) & 0x0f)

Definition at line 176 of file analysis_sh.c.

GET_TARGET_REG

#define GET_TARGET_REG

(

x

)

(((x) >> 8) & 0x0f)

Definition at line 175 of file analysis_sh.c.

IS_ADD

#define IS_ADD

(

x

)

(((x)&0xF00F) == 0x300C)

Definition at line 87 of file analysis_sh.c.

IS_ADDC

#define IS_ADDC

(

x

)

(((x)&0xF00F) == 0x300E)

Definition at line 88 of file analysis_sh.c.

IS_ADDV

#define IS_ADDV

(

x

)

(((x)&0xF00F) == 0x300F)

Definition at line 89 of file analysis_sh.c.

IS_AND_REGS

#define IS_AND_REGS

(

x

)

(((x)&0xF00F) == 0x2009)

Definition at line 67 of file analysis_sh.c.

IS_BF

#define IS_BF

(

x

)

(((x)&0xff00) == 0x8B00)

Definition at line 154 of file analysis_sh.c.

IS_BFS

#define IS_BFS

(

x

)

(((x)&0xff00) == 0x8F00)

Definition at line 156 of file analysis_sh.c.

IS_BINLOGIC_IMM_GBR

#define IS_BINLOGIC_IMM_GBR

(

x

)

(((x)&0xFC00) == 0xCC00)

Definition at line 168 of file analysis_sh.c.

IS_BINLOGIC_IMM_R0

#define IS_BINLOGIC_IMM_R0

(

x

)

(((x)&0xFC00) == 0xC800)

Definition at line 167 of file analysis_sh.c.

IS_BRAF

#define IS_BRAF

(

x

)

(((x)&0xf0ff) == 0x0023)

Definition at line 43 of file analysis_sh.c.

IS_BSRF

#define IS_BSRF

(

x

)

((x)&0xf0ff) == 0x0003

Definition at line 42 of file analysis_sh.c.

IS_BT

#define IS_BT

(

x

)

(((x)&0xff00) == 0x8900)

Definition at line 153 of file analysis_sh.c.

IS_BT_OR_BF

#define IS_BT_OR_BF

(

x

)

IS_BT(x) || IS_BTS(x) || IS_BF(x) || IS_BFS(x)

Definition at line 157 of file analysis_sh.c.

IS_BTS

#define IS_BTS

(

x

)

(((x)&0xff00) == 0x8D00)

Definition at line 155 of file analysis_sh.c.

IS_CLRMAC

#define IS_CLRMAC

(

x

)

x == 0x0028

Definition at line 38 of file analysis_sh.c.

IS_CLRT

#define IS_CLRT

(

x

)

x == 0x0008

Definition at line 32 of file analysis_sh.c.

IS_CMPEQ

#define IS_CMPEQ

(

x

)

(((x)&0xF00F) == 0x3000)

Definition at line 74 of file analysis_sh.c.

IS_CMPGE

#define IS_CMPGE

(

x

)

(((x)&0xF00F) == 0x3003)

Definition at line 77 of file analysis_sh.c.

IS_CMPGT

#define IS_CMPGT

(

x

)

(((x)&0xF00F) == 0x3007)

Definition at line 79 of file analysis_sh.c.

IS_CMPHI

#define IS_CMPHI

(

x

)

(((x)&0xF00F) == 0x3006)

Definition at line 78 of file analysis_sh.c.

IS_CMPHS

#define IS_CMPHS

(

x

)

(((x)&0xF00F) == 0x3002)

Definition at line 76 of file analysis_sh.c.

IS_CMPIMM

#define IS_CMPIMM

(

x

)

(((x)&0xFF00) == 0x8800)

Definition at line 151 of file analysis_sh.c.

IS_CMPPL

#define IS_CMPPL

(

x

)

(((x)&0xf0ff) == 0x4015)

Definition at line 93 of file analysis_sh.c.

IS_CMPPZ

#define IS_CMPPZ

(

x

)

(((x)&0xf0ff) == 0x4011)

Definition at line 94 of file analysis_sh.c.

IS_CMPSTR

#define IS_CMPSTR

(

x

)

(((x)&0xF00F) == 0x200C)

Definition at line 70 of file analysis_sh.c.

IS_DIV0S

#define IS_DIV0S

(

x

)

(((x)&0xF00F) == 0x2007)

Definition at line 65 of file analysis_sh.c.

IS_DIV0U

#define IS_DIV0U

(

x

)

x == 0x0019

Definition at line 36 of file analysis_sh.c.

IS_DIV1

#define IS_DIV1

(

x

)

(((x)&0xF00F) == 0x3004)

Definition at line 80 of file analysis_sh.c.

IS_DMULS

#define IS_DMULS

(

x

)

(((x)&0xF00F) == 0x300D)

Definition at line 82 of file analysis_sh.c.

IS_DMULU

#define IS_DMULU

(

x

)

(((x)&0xF00F) == 0x3005)

Definition at line 81 of file analysis_sh.c.

IS_DT

#define IS_DT

(

x

)

(((x)&0xF0FF) == 0x4010)

Definition at line 130 of file analysis_sh.c.

IS_EXT

#define IS_EXT

(

x

)

(((x)&0xF00C) == 0x600C)

Definition at line 144 of file analysis_sh.c.

IS_JMP

#define IS_JMP

(

x

)

(((x)&0xf0ff) == 0x402b)

Definition at line 92 of file analysis_sh.c.

IS_JSR

#define IS_JSR

(

x

)

(((x)&0xf0ff) == 0x400b)

Definition at line 91 of file analysis_sh.c.

IS_LDCGBR

#define IS_LDCGBR

(

x

)

(((x)&0xF0FF) == 0x401E)

Definition at line 96 of file analysis_sh.c.

IS_LDCLSR

#define IS_LDCLSR

(

x

)

(((x)&0xF0FF) == 0x4007)

Definition at line 98 of file analysis_sh.c.

IS_LDCLSRGBR

#define IS_LDCLSRGBR

(

x

)

(((x)&0xF0FF) == 0x4017)

Definition at line 99 of file analysis_sh.c.

IS_LDCLSRVBR

#define IS_LDCLSRVBR

(

x

)

(((x)&0xF0FF) == 0x4027)

Definition at line 100 of file analysis_sh.c.

IS_LDCSR

#define IS_LDCSR

(

x

)

(((x)&0xF0FF) == 0x400E)

Definition at line 95 of file analysis_sh.c.

IS_LDCVBR

#define IS_LDCVBR

(

x

)

(((x)&0xF0FF) == 0x402E)

Definition at line 97 of file analysis_sh.c.

IS_LDSLMACH

#define IS_LDSLMACH

(

x

)

(((x)&0xF0FF) == 0x4006)

Definition at line 103 of file analysis_sh.c.

IS_LDSLMACL

#define IS_LDSLMACL

(

x

)

(((x)&0xF0FF) == 0x4016)

Definition at line 104 of file analysis_sh.c.

IS_LDSLPR

#define IS_LDSLPR

(

x

)

(((x)&0xF0FF) == 0x4026)

Definition at line 106 of file analysis_sh.c.

IS_LDSMACH

#define IS_LDSMACH

(

x

)

(((x)&0xF0FF) == 0x400A)

Definition at line 101 of file analysis_sh.c.

IS_LDSMACL

#define IS_LDSMACL

(

x

)

(((x)&0xF0FF) == 0x401A)

Definition at line 102 of file analysis_sh.c.

IS_LDSPR

#define IS_LDSPR

(

x

)

(((x)&0xF0FF) == 0x402A)

Definition at line 105 of file analysis_sh.c.

IS_MACL

#define IS_MACL

(

x

)

(((x)&0xF00F) == 0x000F)

Definition at line 51 of file analysis_sh.c.

IS_MACW

#define IS_MACW

(

x

)

(((x)&0xF00F) == 0x400F)

Definition at line 90 of file analysis_sh.c.

IS_MOV_REGS

#define IS_MOV_REGS

(

x

)

(((x)&0xf00f) == 0x6003)

Definition at line 135 of file analysis_sh.c.

IS_MOVA_PCREL_R0

#define IS_MOVA_PCREL_R0

(

x

)

(((x)&0xFF00) == 0xC700)

Definition at line 166 of file analysis_sh.c.

IS_MOVB_GBRREF_R0

#define IS_MOVB_GBRREF_R0

(

x

)

(((x)&0xFF00) == 0xC400)

Definition at line 163 of file analysis_sh.c.

IS_MOVB_POP

#define IS_MOVB_POP

(

x

)

(((x)&0xF00F) == 0x6004)

Definition at line 136 of file analysis_sh.c.

IS_MOVB_R0_GBRREF

#define IS_MOVB_R0_GBRREF

(

x

)

(((x)&0xFF00) == 0xC000)

Definition at line 159 of file analysis_sh.c.

IS_MOVB_R0_REGDISP

#define IS_MOVB_R0_REGDISP

(

x

)

(((x)&0xFF00) == 0x8000)

Definition at line 146 of file analysis_sh.c.

IS_MOVB_R0REL_TO_REG

#define IS_MOVB_R0REL_TO_REG

(

x

)

(((x)&0xF00F) == 0x000C)

Definition at line 48 of file analysis_sh.c.

IS_MOVB_REG_TO_R0REL

#define IS_MOVB_REG_TO_R0REL

(

x

)

(((x)&0xF00F) == 0x0004)

Definition at line 44 of file analysis_sh.c.

IS_MOVB_REG_TO_REGREF

#define IS_MOVB_REG_TO_REGREF

(

x

)

(((x)&0xF00F) == 0x2000)

Definition at line 58 of file analysis_sh.c.

IS_MOVB_REGDISP_R0

#define IS_MOVB_REGDISP_R0

(

x

)

(((x)&0xFF00) == 0x8400)

Definition at line 149 of file analysis_sh.c.

IS_MOVB_REGREF_TO_REG

#define IS_MOVB_REGREF_TO_REG

(

x

)

(((x)&0xF00F) == 0x6000)

Definition at line 132 of file analysis_sh.c.

IS_MOVL_GBRREF_R0

#define IS_MOVL_GBRREF_R0

(

x

)

(((x)&0xFF00) == 0xC600)

Definition at line 165 of file analysis_sh.c.

IS_MOVL_POP

#define IS_MOVL_POP

(

x

)

(((x)&0xF00F) == 0x6006)

Definition at line 138 of file analysis_sh.c.

IS_MOVL_R0_GBRREF

#define IS_MOVL_R0_GBRREF

(

x

)

(((x)&0xFF00) == 0xC200)

Definition at line 161 of file analysis_sh.c.

IS_MOVL_R0REL_TO_REG

#define IS_MOVL_R0REL_TO_REG

(

x

)

(((x)&0xF00F) == 0x000E)

Definition at line 50 of file analysis_sh.c.

IS_MOVL_REG_TO_R0REL

#define IS_MOVL_REG_TO_R0REL

(

x

)

(((x)&0xF00F) == 0x0006)

Definition at line 46 of file analysis_sh.c.

IS_MOVL_REG_TO_REGREF

#define IS_MOVL_REG_TO_REGREF

(

x

)

(((x)&0xF00F) == 0x2002)

Definition at line 60 of file analysis_sh.c.

IS_MOVL_REGREF_TO_REG

#define IS_MOVL_REGREF_TO_REG

(

x

)

(((x)&0xF00F) == 0x6002)

Definition at line 134 of file analysis_sh.c.

IS_MOVT

#define IS_MOVT

(

x

)

(((x)&0xF0FF) == 0x0029)

Definition at line 52 of file analysis_sh.c.

IS_MOVW_GBRREF_R0

#define IS_MOVW_GBRREF_R0

(

x

)

(((x)&0xFF00) == 0xC500)

Definition at line 164 of file analysis_sh.c.

IS_MOVW_POP

#define IS_MOVW_POP

(

x

)

(((x)&0xF00F) == 0x6005)

Definition at line 137 of file analysis_sh.c.

IS_MOVW_R0_GBRREF

#define IS_MOVW_R0_GBRREF

(

x

)

(((x)&0xFF00) == 0xC100)

Definition at line 160 of file analysis_sh.c.

IS_MOVW_R0_REGDISP

#define IS_MOVW_R0_REGDISP

(

x

)

(((x)&0xFF00) == 0x8100)

Definition at line 147 of file analysis_sh.c.

IS_MOVW_R0REL_TO_REG

#define IS_MOVW_R0REL_TO_REG

(

x

)

(((x)&0xF00F) == 0x000D)

Definition at line 49 of file analysis_sh.c.

IS_MOVW_REG_TO_R0REL

#define IS_MOVW_REG_TO_R0REL

(

x

)

(((x)&0xF00F) == 0x0005)

Definition at line 45 of file analysis_sh.c.

IS_MOVW_REG_TO_REGREF

#define IS_MOVW_REG_TO_REGREF

(

x

)

(((x)&0xF00F) == 0x2001)

Definition at line 59 of file analysis_sh.c.

IS_MOVW_REGDISP_R0

#define IS_MOVW_REGDISP_R0

(

x

)

(((x)&0xFF00) == 0x8500)

Definition at line 150 of file analysis_sh.c.

IS_MOVW_REGREF_TO_REG

#define IS_MOVW_REGREF_TO_REG

(

x

)

(((x)&0xF00F) == 0x6001)

Definition at line 133 of file analysis_sh.c.

IS_MULL

#define IS_MULL

(

x

)

(((x)&0xF00F) == 0x0007)

Definition at line 47 of file analysis_sh.c.

IS_MULSW

#define IS_MULSW

(

x

)

(((x)&0xF00F) == 0x200F)

Definition at line 73 of file analysis_sh.c.

IS_MULUW

#define IS_MULUW

(

x

)

(((x)&0xF00F) == 0x200E)

Definition at line 72 of file analysis_sh.c.

IS_NEG

#define IS_NEG

(

x

)

(((x)&0xF00F) == 0x600B)

Definition at line 142 of file analysis_sh.c.

IS_NEGC

#define IS_NEGC

(

x

)

(((x)&0xF00F) == 0x600A)

Definition at line 143 of file analysis_sh.c.

IS_NOP

#define IS_NOP

(

x

)

x == 0x0009

Definition at line 33 of file analysis_sh.c.

IS_NOT

#define IS_NOT

(

x

)

(((x)&0xF00F) == 0x6007)

Definition at line 139 of file analysis_sh.c.

IS_OR_REGS

#define IS_OR_REGS

(

x

)

(((x)&0xF00F) == 0x200B)

Definition at line 69 of file analysis_sh.c.

IS_PUSHB

#define IS_PUSHB

(

x

)

(((x)&0xF00F) == 0x2004)

Definition at line 62 of file analysis_sh.c.

IS_PUSHL

#define IS_PUSHL

(

x

)

(((x)&0xF00F) == 0x2006)

Definition at line 64 of file analysis_sh.c.

IS_PUSHW

#define IS_PUSHW

(

x

)

(((x)&0xF00F) == 0x2005)

Definition at line 63 of file analysis_sh.c.

IS_ROTCL

#define IS_ROTCL

(

x

)

(((x)&0xF0FF) == 0x4024)

Definition at line 112 of file analysis_sh.c.

IS_ROTCR

#define IS_ROTCR

(

x

)

(((x)&0xF0FF) == 0x4025)

Definition at line 111 of file analysis_sh.c.

IS_ROTL

#define IS_ROTL

(

x

)

(((x)&0xF0FF) == 0x4004)

Definition at line 113 of file analysis_sh.c.

IS_ROTR

#define IS_ROTR

(

x

)

(((x)&0xF0FF) == 0x4005)

Definition at line 114 of file analysis_sh.c.

IS_RTE

#define IS_RTE

(

x

)

x == 0x002b

Definition at line 39 of file analysis_sh.c.

IS_RTS

#define IS_RTS

(

x

)

x == 0x000b

Definition at line 34 of file analysis_sh.c.

IS_SETT

#define IS_SETT

(

x

)

x == 0x0018

Definition at line 35 of file analysis_sh.c.

IS_SLEEP

#define IS_SLEEP

(

x

)

x == 0x001b

Definition at line 37 of file analysis_sh.c.

IS_STCLGBR

#define IS_STCLGBR

(

x

)

(((x)&0xF0FF) == 0x4013)

Definition at line 123 of file analysis_sh.c.

IS_STCLSR

#define IS_STCLSR

(

x

)

(((x)&0xF0FF) == 0x4003)

Definition at line 122 of file analysis_sh.c.

IS_STCLVBR

#define IS_STCLVBR

(

x

)

(((x)&0xF0FF) == 0x4023)

Definition at line 124 of file analysis_sh.c.

IS_STCSR1

#define IS_STCSR1

(

x

)

(((x)&0xF0CF) == 0x0002)

Definition at line 41 of file analysis_sh.c.

IS_STSLMACH

#define IS_STSLMACH

(

x

)

(((x)&0xF0FF) == 0x4002)

Definition at line 121 of file analysis_sh.c.

IS_STSLMACL

#define IS_STSLMACL

(

x

)

(((x)&0xF0FF) == 0x4012)

Definition at line 120 of file analysis_sh.c.

IS_STSLPR

#define IS_STSLPR

(

x

)

(((x)&0xF0FF) == 0x4022)

Definition at line 126 of file analysis_sh.c.

IS_STSMACH

#define IS_STSMACH

(

x

)

(((x)&0xF0FF) == 0x000A)

Definition at line 53 of file analysis_sh.c.

IS_STSMACL

#define IS_STSMACL

(

x

)

(((x)&0xF0FF) == 0x001A)

Definition at line 54 of file analysis_sh.c.

IS_STSPR

#define IS_STSPR

(

x

)

(((x)&0xF0FF) == 0x002A)

Definition at line 55 of file analysis_sh.c.

IS_SUB

#define IS_SUB

(

x

)

(((x)&0xF00F) == 0x3008)

Definition at line 83 of file analysis_sh.c.

IS_SUBC

#define IS_SUBC

(

x

)

(((x)&0xF00F) == 0x300A)

Definition at line 85 of file analysis_sh.c.

IS_SUBV

#define IS_SUBV

(

x

)

(((x)&0xF00F) == 0x300B)

Definition at line 86 of file analysis_sh.c.

IS_SWAPB

#define IS_SWAPB

(

x

)

(((x)&0xF00F) == 0x6008)

Definition at line 140 of file analysis_sh.c.

IS_SWAPW

#define IS_SWAPW

(

x

)

(((x)&0xF00F) == 0x6009)

Definition at line 141 of file analysis_sh.c.

IS_T

#define IS_T   "sr,0x1,&,"

Definition at line 27 of file analysis_sh.c.

IS_TASB

#define IS_TASB

(

x

)

(((x)&0xF0FF) == 0x401B)

Definition at line 129 of file analysis_sh.c.

IS_TRAP

#define IS_TRAP

(

x

)

(((x)&0xFF00) == 0xC300)

Definition at line 162 of file analysis_sh.c.

IS_TSTRR

#define IS_TSTRR

(

x

)

(((x)&0xF00F) == 0x2008)

Definition at line 66 of file analysis_sh.c.

IS_XOR_REGS

#define IS_XOR_REGS

(

x

)

(((x)&0xF00F) == 0x200A)

Definition at line 68 of file analysis_sh.c.

IS_XTRCT

#define IS_XTRCT

(

x

)

(((x)&0xF00F) == 0x200D)

Definition at line 71 of file analysis_sh.c.

LONG_SIZE

#define LONG_SIZE   4

Definition at line 13 of file analysis_sh.c.

PC_IDX

#define PC_IDX   16

Definition at line 179 of file analysis_sh.c.

S16_EXT

#define S16_EXT

(

x

)

x ",DUP,0x8000,&,?{,0xFFFFFFFFFFFF0000,|,}"

Definition at line 25 of file analysis_sh.c.

S32_EXT

#define S32_EXT

(

x

)

x ",DUP,0x80000000,&,?{,0xFFFFFFFF00000000,|,}"

Definition at line 26 of file analysis_sh.c.

SET_T

#define SET_T   "0x1,sr,|="

Definition at line 28 of file analysis_sh.c.

WORD_SIZE

#define WORD_SIZE   2

Definition at line 14 of file analysis_sh.c.

Function Documentation

add_imm()

static int add_imm ( RzAnalysis *  analysis, RzAnalysisOp *  op, ut16  code  )

static

Definition at line 864 of file analysis_sh.c.

                                                                      {
    op->type = RZ_ANALYSIS_OP_TYPE_ADD;
    op->src[0] = analysis_fill_im(analysis, (st8)(code & 0xFF)); // Casting to (st8) forces sign-extension.
    op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
    rz_strbuf_setf(&op->esil, "0x%x,DUP,0x80,&,?{,0xFFFFFF00,|,},r%d,+=", code & 0xFF, GET_TARGET_REG(code));
    return op->size;
}

References analysis_fill_ai_rg(), analysis_fill_im(), GET_TARGET_REG, RZ_ANALYSIS_OP_TYPE_ADD, rz_strbuf_setf(), and st8.

analysis_fill_ai_rg()

static RzAnalysisValue* analysis_fill_ai_rg ( RzAnalysis *  analysis, int  idx  )

static

Definition at line 205 of file analysis_sh.c.

                                                                           {
    RzAnalysisValue *ret = rz_analysis_value_new();
    ret->type = RZ_ANALYSIS_VAL_REG;
    ret->reg = rz_reg_get(analysis->reg, regs[idx], RZ_REG_TYPE_GPR);
    return ret;
}

References setup::idx, rz_analysis_t::reg, rz_analysis_value_t::reg, regs, RZ_ANALYSIS_VAL_REG, rz_analysis_value_new(), rz_reg_get(), RZ_REG_TYPE_GPR, and rz_analysis_value_t::type.

Referenced by add_imm(), analysis_fill_r0_reg_ref(), analysis_fill_reg_disp_mem(), analysis_fill_reg_ref(), first_nibble_is_0(), first_nibble_is_2(), first_nibble_is_3(), first_nibble_is_4(), first_nibble_is_6(), first_nibble_is_8(), first_nibble_is_c(), mov_imm_reg(), movl_pcdisp_reg(), movl_rdisp_reg(), movl_reg_rdisp(), and movw_pcdisp_reg().

analysis_fill_im()

static RzAnalysisValue* analysis_fill_im ( RzAnalysis *  analysis, st32  v  )

static

Definition at line 212 of file analysis_sh.c.

                                                                       {
    RzAnalysisValue *ret = rz_analysis_value_new();
    ret->type = RZ_ANALYSIS_VAL_IMM;
    ret->imm = v;
    return ret;
}

References rz_analysis_value_t::imm, RZ_ANALYSIS_VAL_IMM, rz_analysis_value_new(), rz_analysis_value_t::type, and v.

Referenced by add_imm(), first_nibble_is_c(), and mov_imm_reg().

analysis_fill_r0_reg_ref()

static RzAnalysisValue* analysis_fill_r0_reg_ref ( RzAnalysis *  analysis, int  reg, st64  size  )

static

Definition at line 237 of file analysis_sh.c.

                                                                                           {
    RzAnalysisValue *ret = analysis_fill_ai_rg(analysis, 0);
    ret->type = RZ_ANALYSIS_VAL_MEM;
    ret->regdelta = rz_reg_get(analysis->reg, regs[reg], RZ_REG_TYPE_GPR);
    ret->memref = size;
    return ret;
}

References analysis_fill_ai_rg(), rz_analysis_value_t::memref, reg, rz_analysis_t::reg, rz_analysis_value_t::regdelta, regs, RZ_ANALYSIS_VAL_MEM, rz_reg_get(), RZ_REG_TYPE_GPR, and rz_analysis_value_t::type.

Referenced by first_nibble_is_0().

analysis_fill_reg_disp_mem()

static RzAnalysisValue* analysis_fill_reg_disp_mem ( RzAnalysis *  analysis, int  reg, st64  delta, st64  size  )

static

Definition at line 220 of file analysis_sh.c.

                                                                                                         {
    RzAnalysisValue *ret = analysis_fill_ai_rg(analysis, reg);
    ret->type = RZ_ANALYSIS_VAL_MEM;
    ret->memref = size;
    ret->delta = delta * size;
    return ret;
}

References analysis_fill_ai_rg(), delta, rz_analysis_value_t::delta, rz_analysis_value_t::memref, reg, RZ_ANALYSIS_VAL_MEM, and rz_analysis_value_t::type.

Referenced by first_nibble_is_8(), movl_rdisp_reg(), and movl_reg_rdisp().

analysis_fill_reg_ref()

static RzAnalysisValue* analysis_fill_reg_ref ( RzAnalysis *  analysis, int  reg, st64  size  )

static

Definition at line 229 of file analysis_sh.c.

                                                                                        {
    RzAnalysisValue *ret = analysis_fill_ai_rg(analysis, reg);
    ret->type = RZ_ANALYSIS_VAL_MEM;
    ret->memref = size;
    return ret;
}

References analysis_fill_ai_rg(), rz_analysis_value_t::memref, reg, RZ_ANALYSIS_VAL_MEM, and rz_analysis_value_t::type.

Referenced by first_nibble_is_2(), and first_nibble_is_6().

analysis_pcrel_disp_mov()

static RzAnalysisValue* analysis_pcrel_disp_mov ( RzAnalysis *  analysis, RzAnalysisOp *  op, ut8  disp, int  size  )

static

Definition at line 246 of file analysis_sh.c.

                                                                                                            {
    RzAnalysisValue *ret = rz_analysis_value_new();
    ret->type = RZ_ANALYSIS_VAL_MEM;
    if (size == 2) {
        ret->base = op->addr + 4;
        ret->delta = disp << 1;
    } else {
        ret->base = (op->addr + 4) & ~0x03;
        ret->delta = disp << 2;
    }
    ret->memref = size;
    return ret;
}

References rz_analysis_value_t::base, rz_analysis_value_t::delta, rz_analysis_value_t::memref, RZ_ANALYSIS_VAL_MEM, rz_analysis_value_new(), and rz_analysis_value_t::type.

Referenced by first_nibble_is_c(), and movl_pcdisp_reg().

analysis_regrel_jump()

static RzAnalysisValue* analysis_regrel_jump ( RzAnalysis *  analysis, RzAnalysisOp *  op, ut8  reg  )

static

Definition at line 261 of file analysis_sh.c.

                                                                                              {
    RzAnalysisValue *ret = rz_analysis_value_new();
    ret->type = RZ_ANALYSIS_VAL_REG;
    ret->reg = rz_reg_get(analysis->reg, regs[reg], RZ_REG_TYPE_GPR);
    ret->base = op->addr + 4;
    return ret;
}

References rz_analysis_value_t::base, reg, rz_analysis_t::reg, rz_analysis_value_t::reg, regs, RZ_ANALYSIS_VAL_REG, rz_analysis_value_new(), rz_reg_get(), RZ_REG_TYPE_GPR, and rz_analysis_value_t::type.

Referenced by first_nibble_is_0().

archinfo()

static int archinfo ( RzAnalysis *  analysis, int  q  )

static

Definition at line 1176 of file analysis_sh.c.

                                                 {
#if 0
    if (q == RZ_ANALYSIS_ARCHINFO_ALIGN) {
        return 4;
    }
#endif
    return 2; /* :) */
}

References RZ_ANALYSIS_ARCHINFO_ALIGN.

bra()

static int bra ( RzAnalysis *  analysis, RzAnalysisOp *  op, ut16  code  )

static

Definition at line 932 of file analysis_sh.c.

                                                                  {
    /* Unconditional branch, relative to PC */
    op->type = RZ_ANALYSIS_OP_TYPE_JMP;
    op->delay = 1;
    op->jump = disarm_12bit_offset(op, GET_BRA_OFFSET(code));
    op->eob = true;
    rz_strbuf_setf(&op->esil, "1,SETD,0x%" PFMT64x ",pc,=", op->jump);
    return op->size;
}

References disarm_12bit_offset(), GET_BRA_OFFSET, PFMT64x, RZ_ANALYSIS_OP_TYPE_JMP, and rz_strbuf_setf().

bsr()

static int bsr ( RzAnalysis *  analysis, RzAnalysisOp *  op, ut16  code  )

static

Definition at line 943 of file analysis_sh.c.

                                                                  {
    /* Subroutine call, relative to PC */
    op->type = RZ_ANALYSIS_OP_TYPE_CALL;
    op->jump = disarm_12bit_offset(op, GET_BRA_OFFSET(code));
    op->delay = 1;
    rz_strbuf_setf(&op->esil, "1,SETD,pc,2,+,pr,=,0x%" PFMT64x ",pc,=", op->jump);
    return op->size;
}

References disarm_12bit_offset(), GET_BRA_OFFSET, PFMT64x, RZ_ANALYSIS_OP_TYPE_CALL, and rz_strbuf_setf().

disarm_12bit_offset()

static ut64 disarm_12bit_offset ( RzAnalysisOp *  op, unsigned int  insoff  )

static

Definition at line 182 of file analysis_sh.c.

                                                                       {
    ut64 off = insoff;
    /* sign extend if higher bit is 1 (0x0800) */
    if ((off & 0x0800) == 0x0800) {
        off |= ~0xFFF;
    }
    return (op->addr) + (off << 1) + 4;
}

References off, and ut64().

Referenced by bra(), and bsr().

disarm_8bit_offset()

static ut64 disarm_8bit_offset ( ut64  pc, ut32  offs  )

static

Definition at line 192 of file analysis_sh.c.

                                                   {
    /* pc (really, op->addr) is 64 bits, so we need to sign-extend
     * to 64 bits instead of the 32 the actual CPU does */
    ut64 off = offs;
    /* sign extend if higher bit is 1 (0x08) */
    if ((off & 0x80) == 0x80) {
        off |= ~0xFF;
    }
    return (off << 1) + pc + 4;
}

References off, pc, and ut64().

Referenced by first_nibble_is_8().

first_nibble_is_0()

static int first_nibble_is_0 ( RzAnalysis *  analysis, RzAnalysisOp *  op, ut16  code  )

static

Definition at line 270 of file analysis_sh.c.

                                                                                { // STOP
    if (IS_BSRF(code)) {
        /* Call 'far' subroutine Rn+PC+4 */
        op->type = RZ_ANALYSIS_OP_TYPE_UCALL;
        op->delay = 1;
        op->dst = analysis_regrel_jump(analysis, op, GET_TARGET_REG(code));
        rz_strbuf_setf(&op->esil, "1,SETD,pc,2,+,pr,=,r%d,2,+,pc,+=", GET_TARGET_REG(code));
    } else if (IS_BRAF(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_UJMP;
        op->dst = analysis_regrel_jump(analysis, op, GET_TARGET_REG(code));
        op->eob = true;
        op->delay = 1;
        rz_strbuf_setf(&op->esil, "1,SETD,r%d,2,+,pc,+=", GET_TARGET_REG(code));
    } else if (IS_RTS(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_RET;
        op->delay = 1;
        op->eob = true;
        rz_strbuf_setf(&op->esil, "pr,pc,=");
    } else if (IS_RTE(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_RET;
        op->delay = 1;
        op->eob = true;
        // rz_strbuf_setf (&op->esil, "1,SETD,r15,[4],4,+,pc,=,r15,4,+,[4],0xFFF0FFF,&,sr,=,8,r15,+=");
        // not sure if should be added 4 to pc
        rz_strbuf_setf(&op->esil, "1,SETD,r15,[4],pc,=,r15,4,+,[4],0xFFF0FFF,&,sr,=,8,r15,+=");
    } else if (IS_MOVB_REG_TO_R0REL(code)) { // 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)
        op->type = RZ_ANALYSIS_OP_TYPE_STORE;
        op->src[0] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
        op->dst = analysis_fill_r0_reg_ref(analysis, GET_TARGET_REG(code), BYTE_SIZE);
        rz_strbuf_setf(&op->esil, "r%d,0xFF,&,r0,r%d,+,=[1]", GET_SOURCE_REG(code), GET_TARGET_REG(code));
    } else if (IS_MOVW_REG_TO_R0REL(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_STORE;
        op->src[0] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
        op->dst = analysis_fill_r0_reg_ref(analysis, GET_TARGET_REG(code), WORD_SIZE);
        rz_strbuf_setf(&op->esil, "r%d,0xFFFF,&,r0,r%d,+,=[2]", GET_SOURCE_REG(code), GET_TARGET_REG(code));
    } else if (IS_MOVL_REG_TO_R0REL(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_STORE;
        op->src[0] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
        op->dst = analysis_fill_r0_reg_ref(analysis, GET_TARGET_REG(code), LONG_SIZE);
        rz_strbuf_setf(&op->esil, "r%d,r0,r%d,+,=[4]", GET_SOURCE_REG(code), GET_TARGET_REG(code));
    } else if (IS_MOVB_R0REL_TO_REG(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_LOAD;
        op->src[0] = analysis_fill_r0_reg_ref(analysis, GET_SOURCE_REG(code), BYTE_SIZE);
        op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        rz_strbuf_setf(&op->esil, "r0,r%d,+,[1],r%d,=,0x000000FF,r%d,&=,r%d,0x80,&,?{,0xFFFFFF00,r%d,|=,}", GET_SOURCE_REG(code), GET_TARGET_REG(code), GET_TARGET_REG(code), GET_TARGET_REG(code), GET_TARGET_REG(code));
    } else if (IS_MOVW_R0REL_TO_REG(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_LOAD;
        op->src[0] = analysis_fill_r0_reg_ref(analysis, GET_SOURCE_REG(code), WORD_SIZE);
        op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        rz_strbuf_setf(&op->esil, "r0,r%d,+,[2],r%d,=,0x0000FFFF,r%d,&=,r%d,0x8000,&,?{,0xFFFF0000,r%d,|=,}", GET_SOURCE_REG(code), GET_TARGET_REG(code), GET_TARGET_REG(code), GET_TARGET_REG(code), GET_TARGET_REG(code));
    } else if (IS_MOVL_R0REL_TO_REG(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_LOAD;
        op->src[0] = analysis_fill_r0_reg_ref(analysis, GET_SOURCE_REG(code), LONG_SIZE);
        op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        rz_strbuf_setf(&op->esil, "r0,r%d,+,[4],r%d,=", GET_SOURCE_REG(code), GET_TARGET_REG(code));
    } else if (IS_NOP(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_NOP;
        rz_strbuf_setf(&op->esil, " ");
    } else if (IS_CLRT(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_UNK;
        rz_strbuf_setf(&op->esil, "0xFFFFFFFE,sr,&=");
    } else if (IS_SETT(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_UNK;
        rz_strbuf_setf(&op->esil, "0x1,sr,|=");
    } else if (IS_CLRMAC(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_UNK;
        rz_strbuf_setf(&op->esil, "0,mach,=,0,macl,=");
    } else if (IS_DIV0U(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_DIV;
        rz_strbuf_setf(&op->esil, "0xFFFFFCFE,sr,&=");
    } else if (IS_MOVT(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_MOV;
        op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        rz_strbuf_setf(&op->esil, "0x1,sr,&,r%d,=", GET_TARGET_REG(code));
    } else if (IS_MULL(code)) { // multiply long
        op->type = RZ_ANALYSIS_OP_TYPE_MUL;
        op->src[0] = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        op->src[1] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
        rz_strbuf_setf(&op->esil, "r%d,r%d,*,macl,=", GET_TARGET_REG(code), GET_SOURCE_REG(code));
    } else if (IS_SLEEP(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_UNK;
        rz_strbuf_setf(&op->esil, "sleep_called,TRAP");
    } else if (IS_STSMACH(code)) { // 0000nnnn0000101_ sts MAC*,<REG_N>
        op->type = RZ_ANALYSIS_OP_TYPE_MOV;
        op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        rz_strbuf_setf(&op->esil, "mach,r%d,=", GET_TARGET_REG(code));
    } else if (IS_STSMACL(code)) { // 0000nnnn0000101_ sts MAC*,<REG_N>
        op->type = RZ_ANALYSIS_OP_TYPE_MOV;
        op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        rz_strbuf_setf(&op->esil, "macl,r%d,=", GET_TARGET_REG(code));
    } else if (IS_STSLMACL(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_MOV;
        op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        rz_strbuf_setf(&op->esil, "macl,r%d,=", GET_TARGET_REG(code));
    } else if (IS_STCSR1(code)) { // 0000nnnn00010010 stc {sr,gbr,vbr,ssr},<REG_N>
        op->type = RZ_ANALYSIS_OP_TYPE_MOV;
        op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        // todo: plug in src
        switch (GET_SOURCE_REG(code)) {
        case 0:
            rz_strbuf_setf(&op->esil, "sr,r%d,=", GET_TARGET_REG(code));
            break;
        case 1:
            rz_strbuf_setf(&op->esil, "gbr,r%d,=", GET_TARGET_REG(code));
            break;
        case 2:
            rz_strbuf_setf(&op->esil, "vbr,r%d,=", GET_TARGET_REG(code));
            break;
        default:
            rz_strbuf_setf(&op->esil, "%s", "");
            break;
        }
    } else if (IS_STSPR(code)) { // 0000nnnn00101010 sts PR,<REG_N>
        op->type = RZ_ANALYSIS_OP_TYPE_MOV;
        op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        rz_strbuf_setf(&op->esil, "pr,r%d,=", GET_TARGET_REG(code));
    } else if (IS_MACL(code)) {
        rz_strbuf_setf(&op->esil,
            "mach,0x80000000,&,!," // mach_old sign (0)
            S32_EXT("r%d,[4]") "," //@Rn sign extended
            S32_EXT("r%d,[4]") "," //@Rm sign extended
                       "*," //(1)
                       "macl,32,mach,<<,|," // macl | (mach << 32)
                       "+," // MAC+@Rm*@Rn
                       "32," S32_EXT("r%d,[4]") "," //@Rn sign extended
            S32_EXT("r%d,[4]") "," //@Rm sign extended
                       "*,"
                       "4,r%d,+=," // Rn+=4
                       "4,r%d,+=," // Rm+=4
                       "0xffffffff00000000,&,>>,mach,=," // MACH > mach
                       "0xffffffff,&,macl,=,"
                       "0x2,sr,&,!,?{,BREAK,}," // if S==0 BREAK
                       "0x00007fff,mach,>,"
                       "0x80000000,mach,&,!,&,"
                       "?{,0x00007fff,mach,=,0xffffffff,macl,=,}," // if (mach>0x00007fff&&mach>0) mac=0x00007fffffffffff
                       "0xffff8000,mach,<,"
                       "0x80000000,mach,&,!,!,&,"
                       "?{,0xffff8000,mach,=,0x0,macl,=,}," // if (mach>0xffff8000&&mach<0) mac=0xffff800000000000
            ,
            GET_TARGET_REG(code), GET_SOURCE_REG(code),
            GET_TARGET_REG(code), GET_SOURCE_REG(code),
            GET_TARGET_REG(code), GET_SOURCE_REG(code));
        op->type = RZ_ANALYSIS_OP_TYPE_MUL;
    }
    return op->size;
}

References analysis_fill_ai_rg(), analysis_fill_r0_reg_ref(), analysis_regrel_jump(), BYTE_SIZE, GET_SOURCE_REG, GET_TARGET_REG, IS_BRAF, IS_BSRF, IS_CLRMAC, IS_CLRT, IS_DIV0U, IS_MACL, IS_MOVB_R0REL_TO_REG, IS_MOVB_REG_TO_R0REL, IS_MOVL_R0REL_TO_REG, IS_MOVL_REG_TO_R0REL, IS_MOVT, IS_MOVW_R0REL_TO_REG, IS_MOVW_REG_TO_R0REL, IS_MULL, IS_NOP, IS_RTE, IS_RTS, IS_SETT, IS_SLEEP, IS_STCSR1, IS_STSLMACL, IS_STSMACH, IS_STSMACL, IS_STSPR, LONG_SIZE, RZ_ANALYSIS_OP_TYPE_DIV, RZ_ANALYSIS_OP_TYPE_LOAD, RZ_ANALYSIS_OP_TYPE_MOV, RZ_ANALYSIS_OP_TYPE_MUL, RZ_ANALYSIS_OP_TYPE_NOP, RZ_ANALYSIS_OP_TYPE_RET, RZ_ANALYSIS_OP_TYPE_STORE, RZ_ANALYSIS_OP_TYPE_UCALL, RZ_ANALYSIS_OP_TYPE_UJMP, RZ_ANALYSIS_OP_TYPE_UNK, rz_strbuf_setf(), S32_EXT, and WORD_SIZE.

first_nibble_is_2()

static int first_nibble_is_2 ( RzAnalysis *  analysis, RzAnalysisOp *  op, ut16  code  )

static

Definition at line 426 of file analysis_sh.c.

                                                                                {
    if (IS_MOVB_REG_TO_REGREF(code)) { // 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>
        op->type = RZ_ANALYSIS_OP_TYPE_STORE;
        op->src[0] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
        op->dst = analysis_fill_reg_ref(analysis, GET_TARGET_REG(code), BYTE_SIZE);
        rz_strbuf_setf(&op->esil, "r%d,r%d,=[1]", GET_SOURCE_REG(code), GET_TARGET_REG(code));
    } else if (IS_MOVW_REG_TO_REGREF(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_STORE;
        op->src[0] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
        op->dst = analysis_fill_reg_ref(analysis, GET_TARGET_REG(code), WORD_SIZE);
        rz_strbuf_setf(&op->esil, "r%d,r%d,=[2]", GET_SOURCE_REG(code) & 0xFF, GET_TARGET_REG(code));
    } else if (IS_MOVL_REG_TO_REGREF(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_STORE;
        op->src[0] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
        op->dst = analysis_fill_reg_ref(analysis, GET_TARGET_REG(code), LONG_SIZE);
        rz_strbuf_setf(&op->esil, "r%d,r%d,=[4]", GET_SOURCE_REG(code) & 0xFF, GET_TARGET_REG(code));
    } else if (IS_AND_REGS(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_AND;
        op->src[0] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
        op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        rz_strbuf_setf(&op->esil, "r%d,r%d,&=", GET_SOURCE_REG(code), GET_TARGET_REG(code));
    } else if (IS_XOR_REGS(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_XOR;
        op->src[0] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
        op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        rz_strbuf_setf(&op->esil, "r%d,r%d,^=", GET_SOURCE_REG(code), GET_TARGET_REG(code));
    } else if (IS_OR_REGS(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_OR;
        op->src[0] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
        op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        rz_strbuf_setf(&op->esil, "r%d,r%d,|=", GET_SOURCE_REG(code), GET_TARGET_REG(code));
    } else if (IS_PUSHB(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_PUSH;
        rz_strbuf_setf(&op->esil, "1,r%d,-=,r%d,r%d,=[1]", GET_TARGET_REG(code), GET_SOURCE_REG(code), GET_TARGET_REG(code));
    } else if (IS_PUSHW(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_PUSH;
        rz_strbuf_setf(&op->esil, "2,r%d,-=,r%d,r%d,=[2]", GET_TARGET_REG(code), GET_SOURCE_REG(code), GET_TARGET_REG(code));
    } else if (IS_PUSHL(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_PUSH;
        rz_strbuf_setf(&op->esil, "4,r%d,-=,r%d,r%d,=[4]", GET_TARGET_REG(code), GET_SOURCE_REG(code), GET_TARGET_REG(code));
    } else if (IS_TSTRR(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_ACMP;
        rz_strbuf_setf(&op->esil, "1,sr,|=,r%d,r%d,&,?{,0xFFFFFFFE,sr,&=,}", GET_SOURCE_REG(code), GET_TARGET_REG(code));
    } else if (IS_CMPSTR(code)) { // 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>
        op->type = RZ_ANALYSIS_OP_TYPE_ACMP; // maybe not?
        op->src[0] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
        op->src[1] = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        rz_strbuf_setf(&op->esil, "0xFFFFFFFE,sr,&=,24,r%d,r%d,^,>>,0xFF,&,!,?{,1,sr,|=,},16,r%d,r%d,^,>>,0xFF,&,!,?{,1,sr,|=,},8,r%d,r%d,^,>>,0xFF,&,!,?{,1,sr,|=,},r%d,r%d,^,0xFF,&,!,?{,1,sr,|=,}", GET_SOURCE_REG(code), GET_TARGET_REG(code), GET_SOURCE_REG(code), GET_TARGET_REG(code), GET_SOURCE_REG(code), GET_TARGET_REG(code), GET_SOURCE_REG(code), GET_TARGET_REG(code));
    } else if (IS_XTRCT(code)) { // 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>
        op->type = RZ_ANALYSIS_OP_TYPE_MOV;
        op->src[0] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
        op->src[1] = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        rz_strbuf_setf(&op->esil, "16,r%d,0xFFFF,&,<<,16,r%d,0xFFFF0000,&,>>,|,r%d,=", GET_SOURCE_REG(code), GET_TARGET_REG(code), GET_TARGET_REG(code));
    } else if (IS_DIV0S(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_DIV;
        rz_strbuf_setf(&op->esil, "0xFFFFFCFE,sr,&=,r%d,0x80000000,&,?{,0x200,sr,|=,},r%d,0x80000000,&,?{,0x100,sr,|=,},sr,1,sr,<<,^,0x200,&,?{,1,sr,|=,}", GET_SOURCE_REG(code), GET_TARGET_REG(code));
    } else if (IS_MULUW(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_MUL;
        op->src[0] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
        op->src[1] = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        rz_strbuf_setf(&op->esil, "r%d,0xFFFF,&,r%d,0xFFFF,&,*,macl,=", GET_SOURCE_REG(code), GET_TARGET_REG(code));
    } else if (IS_MULSW(code)) { // 0010nnnnmmmm111_ mul{s,u}.w <REG_M>,<REG_N>
        op->type = RZ_ANALYSIS_OP_TYPE_MUL;
        op->src[0] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
        op->src[1] = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        rz_strbuf_setf(&op->esil, S16_EXT("r%d") "," S16_EXT("r%d") ",*,macl,=", GET_SOURCE_REG(code), GET_TARGET_REG(code));
    }
 
    return op->size;
}

References analysis_fill_ai_rg(), analysis_fill_reg_ref(), BYTE_SIZE, GET_SOURCE_REG, GET_TARGET_REG, IS_AND_REGS, IS_CMPSTR, IS_DIV0S, IS_MOVB_REG_TO_REGREF, IS_MOVL_REG_TO_REGREF, IS_MOVW_REG_TO_REGREF, IS_MULSW, IS_MULUW, IS_OR_REGS, IS_PUSHB, IS_PUSHL, IS_PUSHW, IS_TSTRR, IS_XOR_REGS, IS_XTRCT, LONG_SIZE, RZ_ANALYSIS_OP_TYPE_ACMP, RZ_ANALYSIS_OP_TYPE_AND, RZ_ANALYSIS_OP_TYPE_DIV, RZ_ANALYSIS_OP_TYPE_MOV, RZ_ANALYSIS_OP_TYPE_MUL, RZ_ANALYSIS_OP_TYPE_OR, RZ_ANALYSIS_OP_TYPE_PUSH, RZ_ANALYSIS_OP_TYPE_STORE, RZ_ANALYSIS_OP_TYPE_XOR, rz_strbuf_setf(), S16_EXT, and WORD_SIZE.

first_nibble_is_3()

static int first_nibble_is_3 ( RzAnalysis *  analysis, RzAnalysisOp *  op, ut16  code  )

static

Definition at line 498 of file analysis_sh.c.

                                                                                {
    // TODO Handle carry/overflow , CMP/xx?
    if (IS_ADD(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_ADD;
        op->src[0] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
        op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        rz_strbuf_setf(&op->esil, "r%d,r%d,+=", GET_SOURCE_REG(code), GET_TARGET_REG(code));
    } else if (IS_ADDC(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_ADD;
        op->src[0] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
        op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        rz_strbuf_setf(&op->esil, "sr,0x1,&,0xFFFFFFFE,sr,&=,r%d,+=,31,$c,sr,|,sr,:=,r%d,r%d,+=,31,$c,sr,|,sr,:=", GET_TARGET_REG(code), GET_SOURCE_REG(code), GET_TARGET_REG(code));
    } else if (IS_ADDV(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_ADD;
        op->src[0] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
        op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        rz_strbuf_setf(&op->esil, "0xFFFFFFFE,sr,&=,r%d,r%d,+=,31,$o,sr,|=", GET_SOURCE_REG(code), GET_TARGET_REG(code));
    } else if (IS_SUB(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_SUB;
        op->src[0] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
        op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        rz_strbuf_setf(&op->esil, "r%d,r%d,-=", GET_SOURCE_REG(code), GET_TARGET_REG(code));
    } else if (IS_SUBC(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_SUB;
        op->src[0] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
        op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        rz_strbuf_setf(&op->esil, "sr,1,&," CLR_T ",r%d,-=,31,$b,sr,|,sr,:=,r%d,r%d,-=,31,$b,sr,|,sr,:=", GET_TARGET_REG(code), GET_SOURCE_REG(code), GET_TARGET_REG(code));
    } else if (IS_SUBV(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_SUB;
        op->src[0] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
        op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        rz_strbuf_setf(&op->esil, CLR_T ",r%d,r%d,-=,31,$o,sr,|,sr,:=", GET_SOURCE_REG(code), GET_TARGET_REG(code));
    } else if (IS_CMPEQ(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_CMP;
        op->src[0] = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        op->src[1] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
        rz_strbuf_setf(&op->esil, "0xFFFFFFFE,sr,&,r%d,r%d,^,!,|,sr,=", GET_SOURCE_REG(code), GET_TARGET_REG(code));
    } else if (IS_CMPGE(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_CMP;
        op->src[0] = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        op->src[1] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
        rz_strbuf_setf(&op->esil, "0xFFFFFFFE,sr,&=,r%d,r%d,>=,?{,0x1,sr,|=,}", GET_SOURCE_REG(code), GET_TARGET_REG(code));
    } else if (IS_CMPGT(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_CMP;
        op->src[0] = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        op->src[1] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
        rz_strbuf_setf(&op->esil, "0xFFFFFFFE,sr,&=,r%d,r%d,>,?{,0x1,sr,|=,}", GET_SOURCE_REG(code), GET_TARGET_REG(code));
    } else if (IS_CMPHI(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_CMP;
        op->src[0] = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        op->src[1] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
        rz_strbuf_setf(&op->esil, "0xFFFFFFFE,sr,&=,r%d,0x100000000,+,r%d,0x100000000,+,>,?{,0x1,sr,|=,}", GET_SOURCE_REG(code), GET_TARGET_REG(code));
    } else if (IS_CMPHS(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_CMP;
        op->src[0] = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        op->src[1] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
        rz_strbuf_setf(&op->esil, "0xFFFFFFFE,sr,&=,r%d,0x100000000,+,r%d,0x100000000,+,>=,?{,0x1,sr,|=,}", GET_SOURCE_REG(code), GET_TARGET_REG(code));
    } else if (IS_DIV1(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_DIV;
        op->src[0] = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        op->src[1] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
        rz_strbuf_setf(&op->esil,
            "1,sr,>>,sr,^,0x80,&," // old_Q^M
            "0xFFFFFF7F,sr,&=,"
            "1,r%d,DUP,0x80000000,&,?{,0x80,sr,|=,},<<,sr,0x1,&,|,r%d,=," // shift Q<-Rn<-T
            "DUP,!,!,?{,"
            "r%d,NUM," // Rn_old (before subtract)
            "r%d,r%d,+=,"
            "r%d,<,}{," // tmp0
            "r%d,NUM," // Rn_old (before subtract)
            "r%d,r%d,-=,"
            "r%d,>,}," // tmp0
            "sr,0x80,&,!,!,^," // Q^tmp0
            "sr,0x100,&,?{,!,}," // if (M) !(Q^tmp0)
            "0xFFFFFF7F,sr,&=," // Q==0
            "?{,0x80,sr,|=,}," // Q=!(Q^tmp0)or(Q^tmp0)
            CLR_T ","
            "1,sr,>>,sr,^,0x80,&,!,sr,|=", // sr=!Q^M
            GET_TARGET_REG(code), GET_TARGET_REG(code),
            GET_TARGET_REG(code),
            GET_SOURCE_REG(code), GET_TARGET_REG(code),
            GET_TARGET_REG(code),
            GET_TARGET_REG(code),
            GET_SOURCE_REG(code), GET_TARGET_REG(code),
            GET_TARGET_REG(code));
    } else if (IS_DMULU(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_MUL;
        op->src[0] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
        op->src[1] = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        rz_strbuf_setf(&op->esil, "32,r%d,r%d,*,DUP,0xFFFFFFFF,&,macl,=,>>,mach,=", GET_SOURCE_REG(code), GET_TARGET_REG(code));
    } else if (IS_DMULS(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_MUL;
        op->src[0] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
        op->src[1] = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        rz_strbuf_setf(&op->esil, "32,r%d,r%d,0x80000000,&,?{,0xFFFFFFFF00000000,+,},r%d,r%d,0x80000000,&,?{,0xFFFFFFFF00000000,+,},*,DUP,0xFFFFFFFF,&,macl,=,>>,mach,=", GET_SOURCE_REG(code), GET_SOURCE_REG(code), GET_TARGET_REG(code), GET_TARGET_REG(code));
    }
    return op->size;
}

References analysis_fill_ai_rg(), CLR_T, GET_SOURCE_REG, GET_TARGET_REG, IS_ADD, IS_ADDC, IS_ADDV, IS_CMPEQ, IS_CMPGE, IS_CMPGT, IS_CMPHI, IS_CMPHS, IS_DIV1, IS_DMULS, IS_DMULU, IS_SUB, IS_SUBC, IS_SUBV, RZ_ANALYSIS_OP_TYPE_ADD, RZ_ANALYSIS_OP_TYPE_CMP, RZ_ANALYSIS_OP_TYPE_DIV, RZ_ANALYSIS_OP_TYPE_MUL, RZ_ANALYSIS_OP_TYPE_SUB, and rz_strbuf_setf().

first_nibble_is_4()

static int first_nibble_is_4 ( RzAnalysis *  analysis, RzAnalysisOp *  op, ut16  code  )

static

Definition at line 597 of file analysis_sh.c.

                                                                                {
    switch (code & 0xF0FF) { // TODO: change to common } else if construction
    case 0x4020: // shal
        op->type = RZ_ANALYSIS_OP_TYPE_SAL;
        rz_strbuf_setf(&op->esil, "0xFFFFFFFE,sr,&=,r%d,0x80000000,&,?{,0x1,sr,|=,},1,r%d,<<=", GET_TARGET_REG(code), GET_TARGET_REG(code));
        break;
    case 0x4021: // shar
        op->type = RZ_ANALYSIS_OP_TYPE_SAR;
        rz_strbuf_setf(&op->esil, "0xFFFFFFFE,sr,&=,r%d,0x1,&,?{,0x1,sr,|=,},0,r%d,0x80000000,&,?{,0x80000000,+,},1,r%d,>>=,r%d,|=", GET_TARGET_REG(code), GET_TARGET_REG(code), GET_TARGET_REG(code), GET_TARGET_REG(code));
        break;
    case 0x4000: // shll
        op->type = RZ_ANALYSIS_OP_TYPE_SHL;
        rz_strbuf_setf(&op->esil, "0xFFFFFFFE,sr,&=,r%d,0x80000000,&,?{,0x1,sr,|=,},1,r%d,<<=", GET_TARGET_REG(code), GET_TARGET_REG(code));
        break;
    case 0x4008: // shll2
        op->type = RZ_ANALYSIS_OP_TYPE_SHL;
        rz_strbuf_setf(&op->esil, "2,r%d,<<=", GET_TARGET_REG(code));
        break;
    case 0x4018: // shll8
        op->type = RZ_ANALYSIS_OP_TYPE_SHL;
        rz_strbuf_setf(&op->esil, "8,r%d,<<=", GET_TARGET_REG(code));
        break;
    case 0x4028: // shll16
        op->type = RZ_ANALYSIS_OP_TYPE_SHL;
        rz_strbuf_setf(&op->esil, "16,r%d,<<=", GET_TARGET_REG(code));
        break;
    case 0x4001: // shlr
        rz_strbuf_setf(&op->esil, "0xFFFFFFFE,sr,&=,r%d,0x1,&,?{,0x1,sr,|=,},1,r%d,>>=", GET_TARGET_REG(code), GET_TARGET_REG(code));
        op->type = RZ_ANALYSIS_OP_TYPE_SHR;
        break;
    case 0x4009: // shlr2
        rz_strbuf_setf(&op->esil, "2,r%d,>>=", GET_TARGET_REG(code));
        op->type = RZ_ANALYSIS_OP_TYPE_SHR;
        break;
    case 0x4019: // shlr8
        rz_strbuf_setf(&op->esil, "8,r%d,>>=", GET_TARGET_REG(code));
        op->type = RZ_ANALYSIS_OP_TYPE_SHR;
        break;
    case 0x4029: // shlr16
        rz_strbuf_setf(&op->esil, "16,r%d,>>=", GET_TARGET_REG(code));
        op->type = RZ_ANALYSIS_OP_TYPE_SHR;
        break;
    default:
        break;
    }
 
    if (IS_JSR(code)) {
        // op->type = RZ_ANALYSIS_OP_TYPE_UCALL; //call to reg
        op->type = RZ_ANALYSIS_OP_TYPE_RCALL; // call to reg
        op->delay = 1;
        op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        rz_strbuf_setf(&op->esil, "1,SETD,pc,2,+,pr,=,r%d,pc,=", GET_TARGET_REG(code));
    } else if (IS_JMP(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_UJMP; // jmp to reg
        op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        op->delay = 1;
        op->eob = true;
        rz_strbuf_setf(&op->esil, "1,SETD,r%d,pc,=", GET_TARGET_REG(code));
    } else if (IS_CMPPL(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_CMP;
        rz_strbuf_setf(&op->esil, "0xFFFFFFFE,sr,&=,0,r%d,>,?{,0x1,sr,|=,}", GET_TARGET_REG(code));
    } else if (IS_CMPPZ(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_CMP;
        rz_strbuf_setf(&op->esil, "0xFFFFFFFE,sr,&=,0,r%d,>=,?{,0x1,sr,|=,}", GET_TARGET_REG(code));
    } else if (IS_LDCLSR(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_POP;
        rz_strbuf_setf(&op->esil, "r%d,[4],0x0FFF0FFF,&,sr,=,4,r%d,+=", GET_TARGET_REG(code), GET_TARGET_REG(code));
    } else if (IS_LDCLSRGBR(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_POP;
        rz_strbuf_setf(&op->esil, "r%d,[4],gbr,=,4,r%d,+=", GET_TARGET_REG(code), GET_TARGET_REG(code));
    } else if (IS_LDCLSRVBR(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_POP;
        rz_strbuf_setf(&op->esil, "r%d,[4],vbr,=,4,r%d,+=", GET_TARGET_REG(code), GET_TARGET_REG(code));
        // todo ssr?
    } else if (IS_LDSLMACH(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_POP;
        rz_strbuf_setf(&op->esil, "r%d,[4],mach,=,4,r%d,+=", GET_TARGET_REG(code), GET_TARGET_REG(code));
    } else if (IS_LDSLMACL(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_POP;
        rz_strbuf_setf(&op->esil, "r%d,[4],macl,=,4,r%d,+=", GET_TARGET_REG(code), GET_TARGET_REG(code));
    } else if (IS_LDSLPR(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_POP;
        rz_strbuf_setf(&op->esil, "r%d,[4],pr,=,4,r%d,+=", GET_TARGET_REG(code), GET_TARGET_REG(code));
    } else if (IS_LDCSR(code)) {
        rz_strbuf_setf(&op->esil, "r%d,0x0FFF0FFF,&,sr,=", GET_TARGET_REG(code));
        op->type = RZ_ANALYSIS_OP_TYPE_MOV;
    } else if (IS_LDCGBR(code)) {
        rz_strbuf_setf(&op->esil, "r%d,gbr,=", GET_TARGET_REG(code));
        op->type = RZ_ANALYSIS_OP_TYPE_MOV;
    } else if (IS_LDCVBR(code)) {
        rz_strbuf_setf(&op->esil, "r%d,vbr,=", GET_TARGET_REG(code));
        op->type = RZ_ANALYSIS_OP_TYPE_MOV;
    } else if (IS_LDSMACH(code)) {
        rz_strbuf_setf(&op->esil, "r%d,mach,=", GET_TARGET_REG(code));
        op->type = RZ_ANALYSIS_OP_TYPE_MOV;
    } else if (IS_LDSMACL(code)) {
        rz_strbuf_setf(&op->esil, "r%d,macl,=", GET_TARGET_REG(code));
        op->type = RZ_ANALYSIS_OP_TYPE_MOV;
    } else if (IS_LDSPR(code)) {
        rz_strbuf_setf(&op->esil, "r%d,pr,=", GET_TARGET_REG(code));
        op->type = RZ_ANALYSIS_OP_TYPE_MOV;
    } else if (IS_ROTR(code)) {
        rz_strbuf_setf(&op->esil, "0xFFFFFFFE,sr,&=,r%d,0x1,&,sr,|=,0x1,r%d,>>>,r%d,=", GET_TARGET_REG(code), GET_TARGET_REG(code), GET_TARGET_REG(code));
        op->type = (code & 1) ? RZ_ANALYSIS_OP_TYPE_ROR : RZ_ANALYSIS_OP_TYPE_ROL;
    } else if (IS_ROTL(code)) {
        rz_strbuf_setf(&op->esil, "0xFFFFFFFE,sr,&=,0x1,r%d,<<<,r%d,=,r%d,0x1,&,sr,|=", GET_TARGET_REG(code), GET_TARGET_REG(code), GET_TARGET_REG(code));
        op->type = (code & 1) ? RZ_ANALYSIS_OP_TYPE_ROR : RZ_ANALYSIS_OP_TYPE_ROL;
    } else if (IS_ROTCR(code)) {
        rz_strbuf_setf(&op->esil, "0,sr,0x1,&,?{,0x80000000,},0xFFFFFFFE,sr,&=,r%d,1,&,sr,|=,1,r%d,>>=,r%d,|=", GET_TARGET_REG(code), GET_TARGET_REG(code), GET_TARGET_REG(code));
        op->type = (code & 1) ? RZ_ANALYSIS_OP_TYPE_ROR : RZ_ANALYSIS_OP_TYPE_ROL;
    } else if (IS_ROTCL(code)) {
        rz_strbuf_setf(&op->esil, "sr,0x1,&,0xFFFFFFFE,sr,&=,r%d,0x80000000,&,?{,1,sr,|=,},1,r%d,<<=,r%d,|=", GET_TARGET_REG(code), GET_TARGET_REG(code), GET_TARGET_REG(code));
        op->type = (code & 1) ? RZ_ANALYSIS_OP_TYPE_ROR : RZ_ANALYSIS_OP_TYPE_ROL;
    } else if (IS_STCLSR(code)) {
        rz_strbuf_setf(&op->esil, "4,r%d,-=,sr,r%d,=[4]", GET_TARGET_REG(code), GET_TARGET_REG(code));
        op->type = RZ_ANALYSIS_OP_TYPE_PUSH;
    } else if (IS_STCLGBR(code)) {
        rz_strbuf_setf(&op->esil, "4,r%d,-=,gbr,r%d,=[4]", GET_TARGET_REG(code), GET_TARGET_REG(code));
        op->type = RZ_ANALYSIS_OP_TYPE_PUSH;
    } else if (IS_STCLVBR(code)) {
        rz_strbuf_setf(&op->esil, "4,r%d,-=,vbr,r%d,=[4]", GET_TARGET_REG(code), GET_TARGET_REG(code));
        op->type = RZ_ANALYSIS_OP_TYPE_PUSH;
    } else if (IS_STSLMACL(code)) {
        rz_strbuf_setf(&op->esil, "4,r%d,-=,macl,r%d,=[4]", GET_TARGET_REG(code), GET_TARGET_REG(code));
        op->type = RZ_ANALYSIS_OP_TYPE_PUSH;
    } else if (IS_STSLMACH(code)) {
        rz_strbuf_setf(&op->esil, "4,r%d,-=,mach,r%d,=[4]", GET_TARGET_REG(code), GET_TARGET_REG(code));
        op->type = RZ_ANALYSIS_OP_TYPE_PUSH;
    } else if (IS_STSLPR(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_PUSH;
        rz_strbuf_setf(&op->esil, "4,r%d,-=,pr,r%d,=[4]", GET_TARGET_REG(code), GET_TARGET_REG(code));
    } else if (IS_TASB(code)) {
        rz_strbuf_setf(&op->esil, "0xFFFFFFFE,sr,&=,r%d,[1],!,?{,0x80,r%d,=[1],1,sr,|=,}", GET_TARGET_REG(code), GET_TARGET_REG(code));
        op->type = RZ_ANALYSIS_OP_TYPE_UNK;
    } else if (IS_DT(code)) {
        rz_strbuf_setf(&op->esil, "0xFFFFFFFE,sr,&=,1,r%d,-=,$z,sr,|,sr,:=", GET_TARGET_REG(code));
        op->type = RZ_ANALYSIS_OP_TYPE_UNK;
    } else if (IS_MACW(code)) {
        rz_strbuf_setf(&op->esil,
            "0x2,sr,&,!,?{," // if S==0
            S16_EXT("r%d,[2]") "," //@Rn sign extended
            S16_EXT("r%d,[2]") "," //@Rm sign extended
                       "*,"
                       "macl,32,mach,<<,|," // macl | (mach << 32)
                       "+," // MAC+@Rm*@Rn
                       "32," S16_EXT("r%d,[2]") "," //@Rn sign extended
            S16_EXT("r%d,[2]") "," //@Rm sign extended
                       "*,"
                       "0xffffffff00000000,&,>>,mach,=," // MACH > mach
                       "0xffffffff,&,macl,=,"
                       "}{," // if S==1
            S16_EXT("r%d,[2]") "," //@Rn sign extended
            S16_EXT("r%d,[2]") "," //@Rm sign extended
                       "*"
                       "macl,+=," // macl+(@Rm+@Rm)
                       "31,$o,?{," // if overflow
                       "macl,0x80000000,&,?{,"
                       "0x7fffffff,macl,=,"
                       "}{,"
                       "0x80000000,macl,=,"
                       "},"
                       "},"
                       "},"
                       "2,r%d,+=," // Rn+=2
                       "2,r%d,+=,", // Rm+=2
            GET_TARGET_REG(code), GET_SOURCE_REG(code),
            GET_TARGET_REG(code), GET_SOURCE_REG(code),
            GET_TARGET_REG(code), GET_SOURCE_REG(code),
            GET_TARGET_REG(code), GET_SOURCE_REG(code));
        op->type = RZ_ANALYSIS_OP_TYPE_MUL;
    }
    return op->size;
}

References analysis_fill_ai_rg(), GET_SOURCE_REG, GET_TARGET_REG, IS_CMPPL, IS_CMPPZ, IS_DT, IS_JMP, IS_JSR, IS_LDCGBR, IS_LDCLSR, IS_LDCLSRGBR, IS_LDCLSRVBR, IS_LDCSR, IS_LDCVBR, IS_LDSLMACH, IS_LDSLMACL, IS_LDSLPR, IS_LDSMACH, IS_LDSMACL, IS_LDSPR, IS_MACW, IS_ROTCL, IS_ROTCR, IS_ROTL, IS_ROTR, IS_STCLGBR, IS_STCLSR, IS_STCLVBR, IS_STSLMACH, IS_STSLMACL, IS_STSLPR, IS_TASB, RZ_ANALYSIS_OP_TYPE_CMP, RZ_ANALYSIS_OP_TYPE_MOV, RZ_ANALYSIS_OP_TYPE_MUL, RZ_ANALYSIS_OP_TYPE_POP, RZ_ANALYSIS_OP_TYPE_PUSH, RZ_ANALYSIS_OP_TYPE_RCALL, RZ_ANALYSIS_OP_TYPE_ROL, RZ_ANALYSIS_OP_TYPE_ROR, RZ_ANALYSIS_OP_TYPE_SAL, RZ_ANALYSIS_OP_TYPE_SAR, RZ_ANALYSIS_OP_TYPE_SHL, RZ_ANALYSIS_OP_TYPE_SHR, RZ_ANALYSIS_OP_TYPE_UJMP, RZ_ANALYSIS_OP_TYPE_UNK, rz_strbuf_setf(), and S16_EXT.

first_nibble_is_6()

static int first_nibble_is_6 ( RzAnalysis *  analysis, RzAnalysisOp *  op, ut16  code  )

static

Definition at line 780 of file analysis_sh.c.

                                                                                {
    if (IS_MOV_REGS(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_MOV;
        op->src[0] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
        op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        rz_strbuf_setf(&op->esil, "r%d,r%d,=", GET_SOURCE_REG(code), GET_TARGET_REG(code));
    } else if (IS_MOVB_REGREF_TO_REG(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_LOAD;
        op->src[0] = analysis_fill_reg_ref(analysis, GET_SOURCE_REG(code), BYTE_SIZE);
        op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        rz_strbuf_setf(&op->esil, "0x000000FF,r%d,&=,r%d,[1],DUP,0x80,&,?{,0xFFFFFF00,|=,},r%d,=", GET_TARGET_REG(code), GET_SOURCE_REG(code), GET_TARGET_REG(code));
    } else if (IS_MOVW_REGREF_TO_REG(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_LOAD;
        op->src[0] = analysis_fill_reg_ref(analysis, GET_SOURCE_REG(code), WORD_SIZE);
        op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        rz_strbuf_setf(&op->esil, "0x0000FFFF,r%d,&=,r%d,[2],DUP,0x8000,&,?{,0xFFFF0000,|=,},r%d,=", GET_TARGET_REG(code), GET_SOURCE_REG(code), GET_TARGET_REG(code));
    } else if (IS_MOVL_REGREF_TO_REG(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_LOAD;
        op->src[0] = analysis_fill_reg_ref(analysis, GET_SOURCE_REG(code), LONG_SIZE);
        op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        rz_strbuf_setf(&op->esil, "r%d,[4],r%d,=", GET_SOURCE_REG(code), GET_TARGET_REG(code));
    } else if (IS_EXT(code)) {
        // ext{s,u}.{b,w} instructs. todo : more detail ?
        op->type = RZ_ANALYSIS_OP_TYPE_MOV;
        op->src[0] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
        op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        switch (code & 0xF) {
        case 0xC: // EXTU.B
            rz_strbuf_setf(&op->esil, "r%d,0xFF,&,r%d,=", GET_SOURCE_REG(code), GET_TARGET_REG(code));
            break;
        case 0xD: // EXTU.W
            rz_strbuf_setf(&op->esil, "r%d,0xFFFF,&,r%d,=", GET_SOURCE_REG(code), GET_TARGET_REG(code));
            break;
        case 0xE: // EXTS.B
            rz_strbuf_setf(&op->esil, "r%d,0xFF,&,DUP,0x80,&,?{,0xFFFFFF00,|,},r%d,=", GET_SOURCE_REG(code), GET_TARGET_REG(code));
            break;
        case 0xF: // EXTS.W
            rz_strbuf_setf(&op->esil, "r%d,0xFFFF,&,DUP,0x8000,&,?{,0xFFFF0000,|,},r%d,=", GET_SOURCE_REG(code), GET_TARGET_REG(code));
            break;
        default:
            rz_strbuf_setf(&op->esil, "TODO,NOT IMPLEMENTED");
            break;
        }
    } else if (IS_MOVB_POP(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_POP;
        op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        rz_strbuf_setf(&op->esil, "r%d,[1],DUP,0x80,&,?{,0xFFFFFF00,|,},r%d,=,1,r%d,+=", GET_SOURCE_REG(code), GET_TARGET_REG(code), GET_SOURCE_REG(code));
    } else if (IS_MOVW_POP(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_POP;
        op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        rz_strbuf_setf(&op->esil, "r%d,[2],DUP,0x8000,&,?{,0xFFFF0000,|,},r%d,=,2,r%d,+=", GET_SOURCE_REG(code), GET_TARGET_REG(code), GET_SOURCE_REG(code));
    } else if (IS_MOVL_POP(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_POP;
        op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
        rz_strbuf_setf(&op->esil, "r%d,[4],r%d,=,4,r%d,+=", GET_SOURCE_REG(code), GET_TARGET_REG(code), GET_SOURCE_REG(code));
    } else if (IS_NEG(code)) {
        // todo: neg and negc details
        op->type = RZ_ANALYSIS_OP_TYPE_UNK;
        rz_strbuf_setf(&op->esil, "r%d,0,-,r%d,=", GET_SOURCE_REG(code), GET_TARGET_REG(code));
        op->src[0] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
        op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
    } else if (IS_NEGC(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_UNK;
        rz_strbuf_setf(&op->esil, "1,sr,&,0xFFFFFFFE,sr,&=,r%d,+,0,-,31,$b,sr,|,sr,=,r%d,=", GET_SOURCE_REG(code), GET_TARGET_REG(code));
        op->src[0] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
        op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
    } else if (IS_NOT(code)) {
        // todo : details?
        rz_strbuf_setf(&op->esil, "0xFFFFFFFF,r%d,^,r%d,=", GET_SOURCE_REG(code), GET_TARGET_REG(code));
        op->type = RZ_ANALYSIS_OP_TYPE_NOT;
        op->src[0] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
        op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
    } else if (IS_SWAPB(code)) {
        rz_strbuf_setf(&op->esil, "r%d,0xFFFF0000,&,8,r%d,0xFF,&,<<,|,8,r%d,0xFF00,&,>>,|,r%d,=", GET_SOURCE_REG(code), GET_SOURCE_REG(code), GET_SOURCE_REG(code), GET_TARGET_REG(code));
        op->type = RZ_ANALYSIS_OP_TYPE_MOV;
        // todo : details
    } else if (IS_SWAPW(code)) {
        rz_strbuf_setf(&op->esil, "16,r%d,0xFFFF,&,<<,16,r%d,0xFFFF0000,&,>>,|,r%d,=", GET_SOURCE_REG(code), GET_SOURCE_REG(code), GET_TARGET_REG(code));
        op->type = RZ_ANALYSIS_OP_TYPE_MOV;
    }
    return op->size;
}

References analysis_fill_ai_rg(), analysis_fill_reg_ref(), BYTE_SIZE, GET_SOURCE_REG, GET_TARGET_REG, IS_EXT, IS_MOV_REGS, IS_MOVB_POP, IS_MOVB_REGREF_TO_REG, IS_MOVL_POP, IS_MOVL_REGREF_TO_REG, IS_MOVW_POP, IS_MOVW_REGREF_TO_REG, IS_NEG, IS_NEGC, IS_NOT, IS_SWAPB, IS_SWAPW, LONG_SIZE, RZ_ANALYSIS_OP_TYPE_LOAD, RZ_ANALYSIS_OP_TYPE_MOV, RZ_ANALYSIS_OP_TYPE_NOT, RZ_ANALYSIS_OP_TYPE_POP, RZ_ANALYSIS_OP_TYPE_UNK, rz_strbuf_setf(), and WORD_SIZE.

first_nibble_is_8()

static int first_nibble_is_8 ( RzAnalysis *  analysis, RzAnalysisOp *  op, ut16  code  )

static

Definition at line 872 of file analysis_sh.c.

                                                                                {
    if (IS_BT_OR_BF(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_CJMP; // Jump if true or jump if false insns
        op->jump = disarm_8bit_offset(op->addr, GET_BTF_OFFSET(code));
        op->fail = op->addr + 2;
        op->eob = true;
        if (IS_BT(code)) {
            rz_strbuf_setf(&op->esil, "sr,1,&,?{,0x%" PFMT64x ",pc,=,}", op->jump);
        } else if (IS_BTS(code)) {
            rz_strbuf_setf(&op->esil, "1,SETD,sr,1,&,?{,0x%" PFMT64x ",pc,=,}", op->jump);
            op->delay = 1; // Only /S versions have a delay slot
        } else if (IS_BFS(code)) {
            rz_strbuf_setf(&op->esil, "1,SETD,sr,1,&,!,?{,0x%" PFMT64x ",pc,=,}", op->jump);
            op->delay = 1; // Only /S versions have a delay slot
        } else if (IS_BF(code)) {
            rz_strbuf_setf(&op->esil, "sr,1,&,!,?{,0x%" PFMT64x ",pc,=,}", op->jump);
        }
    } else if (IS_MOVB_REGDISP_R0(code)) {
        // 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0
        op->type = RZ_ANALYSIS_OP_TYPE_LOAD;
        op->dst = analysis_fill_ai_rg(analysis, 0);
        op->src[0] = analysis_fill_reg_disp_mem(analysis, GET_SOURCE_REG(code), code & 0x0F, BYTE_SIZE);
        rz_strbuf_setf(&op->esil, "r%d,0x%x,+,[1],DUP,0x80,&,?{,0xFFFFFF00,|,},r0,=", GET_SOURCE_REG(code), code & 0xF);
    } else if (IS_MOVW_REGDISP_R0(code)) {
        // 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0
        op->type = RZ_ANALYSIS_OP_TYPE_LOAD;
        op->dst = analysis_fill_ai_rg(analysis, 0);
        op->src[0] = analysis_fill_reg_disp_mem(analysis, GET_SOURCE_REG(code), code & 0x0F, WORD_SIZE);
        rz_strbuf_setf(&op->esil, "r%d,0x%x,+,[2],DUP,0x8000,&,?{,0xFFFF0000,|,},r0,=", GET_SOURCE_REG(code), (code & 0xF) * 2);
    } else if (IS_CMPIMM(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_CMP;
        rz_strbuf_setf(&op->esil, "0xFFFFFFFE,sr,&=,0x%x,DUP,0x80,&,?{,0xFFFFFF00,|,},r0,==,$z,sr,|,sr,:=", code & 0xFF);
    } else if (IS_MOVB_R0_REGDISP(code)) {
        /* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/
        op->type = RZ_ANALYSIS_OP_TYPE_STORE;
        op->src[0] = analysis_fill_ai_rg(analysis, 0);
        op->dst = analysis_fill_reg_disp_mem(analysis, GET_SOURCE_REG(code), code & 0x0F, BYTE_SIZE);
        rz_strbuf_setf(&op->esil, "r0,0xFF,&,0x%x,r%d,+,=[1]", code & 0xF, GET_SOURCE_REG(code));
    } else if (IS_MOVW_R0_REGDISP(code)) {
        // 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>))
        op->type = RZ_ANALYSIS_OP_TYPE_STORE;
        op->src[0] = analysis_fill_ai_rg(analysis, 0);
        op->dst = analysis_fill_reg_disp_mem(analysis, GET_SOURCE_REG(code), code & 0x0F, WORD_SIZE);
        rz_strbuf_setf(&op->esil, "r0,0xFFFF,&,0x%x,r%d,+,=[2]", (code & 0xF) * 2, GET_SOURCE_REG(code));
    }
    return op->size;
}

References analysis_fill_ai_rg(), analysis_fill_reg_disp_mem(), BYTE_SIZE, disarm_8bit_offset(), GET_BTF_OFFSET, GET_SOURCE_REG, IS_BF, IS_BFS, IS_BT, IS_BT_OR_BF, IS_BTS, IS_CMPIMM, IS_MOVB_R0_REGDISP, IS_MOVB_REGDISP_R0, IS_MOVW_R0_REGDISP, IS_MOVW_REGDISP_R0, PFMT64x, RZ_ANALYSIS_OP_TYPE_CJMP, RZ_ANALYSIS_OP_TYPE_CMP, RZ_ANALYSIS_OP_TYPE_LOAD, RZ_ANALYSIS_OP_TYPE_STORE, rz_strbuf_setf(), and WORD_SIZE.

first_nibble_is_c()

static int first_nibble_is_c ( RzAnalysis *  analysis, RzAnalysisOp *  op, ut16  code  )

static

Definition at line 952 of file analysis_sh.c.

                                                                                {
    if (IS_TRAP(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_SWI;
        op->val = (ut8)(code & 0xFF);
        rz_strbuf_setf(&op->esil, "4,r15,-=,sr,r15,=[4],4,r15,-=,2,pc,-,r15,=[4],2,0x%x,<<,4,+,vbr,+,pc,=", code & 0xFF);
    } else if (IS_MOVA_PCREL_R0(code)) {
        // 11000111i8p4.... mova @(<disp>,PC),R0
        op->type = RZ_ANALYSIS_OP_TYPE_LEA;
        op->src[0] = analysis_pcrel_disp_mov(analysis, op, code & 0xFF, LONG_SIZE); // this is wrong !
        op->dst = analysis_fill_ai_rg(analysis, 0); // Always R0
        rz_strbuf_setf(&op->esil, "0x%x,pc,+,r0,=", (code & 0xFF) * 4);
    } else if (IS_BINLOGIC_IMM_R0(code)) { // 110010__i8 (binop) #imm, R0
        op->src[0] = analysis_fill_im(analysis, code & 0xFF);
        op->src[1] = analysis_fill_ai_rg(analysis, 0); // Always R0
        op->dst = analysis_fill_ai_rg(analysis, 0); // Always R0 except tst #imm, R0
        switch (code & 0xFF00) {
        case 0xC800: // tst
            // TODO : get correct op->dst ! (T flag)
            op->type = RZ_ANALYSIS_OP_TYPE_ACMP;
            rz_strbuf_setf(&op->esil, "0xFFFFFFFE,sr,&=,r0,0x%x,&,!,?{,1,sr,|=,}", code & 0xFF);
            break;
        case 0xC900: // and
            op->type = RZ_ANALYSIS_OP_TYPE_AND;
            rz_strbuf_setf(&op->esil, "0x%x,r0,&=", code & 0xFF);
            break;
        case 0xCA00: // xor
            op->type = RZ_ANALYSIS_OP_TYPE_XOR;
            rz_strbuf_setf(&op->esil, "0x%x,r0,^=", code & 0xFF);
            break;
        case 0xCB00: // or
            op->type = RZ_ANALYSIS_OP_TYPE_OR;
            rz_strbuf_setf(&op->esil, "0x%x,r0,|=", code & 0xFF);
            break;
        }
    } else if (IS_BINLOGIC_IMM_GBR(code)) { // 110011__i8 (binop).b #imm, @(R0,gbr)
        op->src[0] = analysis_fill_im(analysis, code & 0xFF);
        switch (code & 0xFF00) {
        case 0xCC00: // tst
            // TODO : get correct op->dst ! (T flag)
            op->type = RZ_ANALYSIS_OP_TYPE_ACMP;
            rz_strbuf_setf(&op->esil, "0xFFFFFFFE,sr,&=,r0,gbr,+,[1],0x%x,&,!,?{,1,sr,|=,}", code & 0xFF);
            break;
        case 0xCD00: // and
            op->type = RZ_ANALYSIS_OP_TYPE_AND;
            rz_strbuf_setf(&op->esil, "r0,gbr,+,[1],0x%x,&,r0,gbr,+,=[1]", code & 0xFF);
            break;
        case 0xCE00: // xor
            op->type = RZ_ANALYSIS_OP_TYPE_XOR;
            rz_strbuf_setf(&op->esil, "r0,gbr,+,[1],0x%x,^,r0,gbr,+,=[1]", code & 0xFF);
            break;
        case 0xCF00: // or
            op->type = RZ_ANALYSIS_OP_TYPE_OR;
            rz_strbuf_setf(&op->esil, "r0,gbr,+,[1],0x%x,|,r0,gbr,+,=[1]", code & 0xFF);
            break;
        }
        // TODO : implement @(R0,gbr) dest and src[1]
    } else if (IS_MOVB_R0_GBRREF(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_STORE;
        op->src[0] = analysis_fill_ai_rg(analysis, 0);
        rz_strbuf_setf(&op->esil, "r0,gbr,0x%x,+,=[1]", code & 0xFF);
    } else if (IS_MOVW_R0_GBRREF(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_STORE;
        op->src[0] = analysis_fill_ai_rg(analysis, 0);
        rz_strbuf_setf(&op->esil, "r0,gbr,0x%x,+,=[2]", (code & 0xFF) * 2);
    } else if (IS_MOVL_R0_GBRREF(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_STORE;
        op->src[0] = analysis_fill_ai_rg(analysis, 0);
        rz_strbuf_setf(&op->esil, "r0,gbr,0x%x,+,=[4]", (code & 0xFF) * 4);
    } else if (IS_MOVB_GBRREF_R0(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_LOAD;
        op->dst = analysis_fill_ai_rg(analysis, 0);
        rz_strbuf_setf(&op->esil, "gbr,0x%x,+,[1],DUP,0x80,&,?{,0xFFFFFF00,|,},r0,=", (code & 0xFF));
    } else if (IS_MOVW_GBRREF_R0(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_LOAD;
        op->dst = analysis_fill_ai_rg(analysis, 0);
        rz_strbuf_setf(&op->esil, "gbr,0x%x,+,[2],DUP,0x8000,&,?{,0xFFFF0000,|,},r0,=", (code & 0xFF) * 2);
    } else if (IS_MOVL_GBRREF_R0(code)) {
        op->type = RZ_ANALYSIS_OP_TYPE_LOAD;
        op->dst = analysis_fill_ai_rg(analysis, 0);
        rz_strbuf_setf(&op->esil, "gbr,0x%x,+,[4],r0,=", (code & 0xFF) * 4);
    }
 
    return op->size;
}

References analysis_fill_ai_rg(), analysis_fill_im(), analysis_pcrel_disp_mov(), IS_BINLOGIC_IMM_GBR, IS_BINLOGIC_IMM_R0, IS_MOVA_PCREL_R0, IS_MOVB_GBRREF_R0, IS_MOVB_R0_GBRREF, IS_MOVL_GBRREF_R0, IS_MOVL_R0_GBRREF, IS_MOVW_GBRREF_R0, IS_MOVW_R0_GBRREF, IS_TRAP, LONG_SIZE, RZ_ANALYSIS_OP_TYPE_ACMP, RZ_ANALYSIS_OP_TYPE_AND, RZ_ANALYSIS_OP_TYPE_LEA, RZ_ANALYSIS_OP_TYPE_LOAD, RZ_ANALYSIS_OP_TYPE_OR, RZ_ANALYSIS_OP_TYPE_STORE, RZ_ANALYSIS_OP_TYPE_SWI, RZ_ANALYSIS_OP_TYPE_XOR, rz_strbuf_setf(), and ut8.

fpu_insn()

static int fpu_insn ( RzAnalysis *  analysis, RzAnalysisOp *  op, ut16  code  )

static

Definition at line 1058 of file analysis_sh.c.

                                                                       {
    // Not interested on FPU stuff for now
    op->family = RZ_ANALYSIS_OP_FAMILY_FPU;
    return op->size;
}

References RZ_ANALYSIS_OP_FAMILY_FPU.

mov_imm_reg()

static int mov_imm_reg ( RzAnalysis *  analysis, RzAnalysisOp *  op, ut16  code  )

static

Definition at line 1049 of file analysis_sh.c.

                                                                          {
    op->type = RZ_ANALYSIS_OP_TYPE_MOV;
    op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
    op->src[0] = analysis_fill_im(analysis, (st8)(code & 0xFF));
    rz_strbuf_setf(&op->esil, "0x%x,r%d,=,r%d,0x80,&,?{,0xFFFFFF00,r%d,|=,}", code & 0xFF, GET_TARGET_REG(code), GET_TARGET_REG(code), GET_TARGET_REG(code));
    return op->size;
}

References analysis_fill_ai_rg(), analysis_fill_im(), GET_TARGET_REG, RZ_ANALYSIS_OP_TYPE_MOV, rz_strbuf_setf(), and st8.

movl_pcdisp_reg()

static int movl_pcdisp_reg ( RzAnalysis *  analysis, RzAnalysisOp *  op, ut16  code  )

static

Definition at line 1038 of file analysis_sh.c.

                                                                              {
    op->type = RZ_ANALYSIS_OP_TYPE_LOAD;
    op->src[0] = analysis_pcrel_disp_mov(analysis, op, code & 0xFF, LONG_SIZE);
    // TODO: check it
    op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
    // rz_strbuf_setf (&op->esil, "0x%x,[4],r%d,=", (code & 0xFF) * 4 + (op->addr & 0xfffffff3) + 4, GET_TARGET_REG (code));
    rz_strbuf_setf(&op->esil, "0x%" PFMT64x ",[4],r%d,=", (code & 0xFF) * 4 + ((op->addr >> 2) << 2) + 4, GET_TARGET_REG(code));
    return op->size;
}

References analysis_fill_ai_rg(), analysis_pcrel_disp_mov(), GET_TARGET_REG, LONG_SIZE, PFMT64x, RZ_ANALYSIS_OP_TYPE_LOAD, and rz_strbuf_setf().

movl_rdisp_reg()

static int movl_rdisp_reg ( RzAnalysis *  analysis, RzAnalysisOp *  op, ut16  code  )

static

Definition at line 772 of file analysis_sh.c.

                                                                             {
    op->type = RZ_ANALYSIS_OP_TYPE_LOAD;
    op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
    op->src[0] = analysis_fill_reg_disp_mem(analysis, GET_SOURCE_REG(code), code & 0x0F, LONG_SIZE);
    rz_strbuf_setf(&op->esil, "r%d,0x%x,+,[4],r%d,=", GET_SOURCE_REG(code), (code & 0xF) * 4, GET_TARGET_REG(code));
    return op->size;
}

References analysis_fill_ai_rg(), analysis_fill_reg_disp_mem(), GET_SOURCE_REG, GET_TARGET_REG, LONG_SIZE, RZ_ANALYSIS_OP_TYPE_LOAD, and rz_strbuf_setf().

movl_reg_rdisp()

static int movl_reg_rdisp ( RzAnalysis *  analysis, RzAnalysisOp *  op, ut16  code  )

static

Definition at line 418 of file analysis_sh.c.

                                                                             {
    op->type = RZ_ANALYSIS_OP_TYPE_STORE;
    op->src[0] = analysis_fill_ai_rg(analysis, GET_SOURCE_REG(code));
    op->dst = analysis_fill_reg_disp_mem(analysis, GET_TARGET_REG(code), code & 0x0F, LONG_SIZE);
    rz_strbuf_setf(&op->esil, "r%d,r%d,0x%x,+,=[4]", GET_SOURCE_REG(code), GET_TARGET_REG(code), (code & 0xF) << 2);
    return op->size;
}

References analysis_fill_ai_rg(), analysis_fill_reg_disp_mem(), GET_SOURCE_REG, GET_TARGET_REG, LONG_SIZE, RZ_ANALYSIS_OP_TYPE_STORE, and rz_strbuf_setf().

movw_pcdisp_reg()

static int movw_pcdisp_reg ( RzAnalysis *  analysis, RzAnalysisOp *  op, ut16  code  )

static

Definition at line 921 of file analysis_sh.c.

                                                                              {
    op->type = RZ_ANALYSIS_OP_TYPE_LOAD;
    op->dst = analysis_fill_ai_rg(analysis, GET_TARGET_REG(code));
    op->src[0] = rz_analysis_value_new();
    op->src[0]->base = (code & 0xFF) * 2 + op->addr + 4;
    op->src[0]->memref = 1;
    rz_strbuf_setf(&op->esil, "0x%" PFMT64x ",[2],r%d,=,r%d,0x8000,&,?{,0xFFFF0000,r%d,|=,}", op->src[0]->base, GET_TARGET_REG(code), GET_TARGET_REG(code), GET_TARGET_REG(code));
    return op->size;
}

References analysis_fill_ai_rg(), GET_TARGET_REG, PFMT64x, RZ_ANALYSIS_OP_TYPE_LOAD, rz_analysis_value_new(), and rz_strbuf_setf().

sh_get_reg_profile()

static RZ_OWN char* sh_get_reg_profile ( RzAnalysis *  analysis )

static

Definition at line 1116 of file analysis_sh.c.

                                                             {
    // TODO Add fpu regs
    const char *p =
        "=PC    pc\n"
        "=SN    r0\n"
        "=SP    r15\n"
        "=BP    r14\n"
        "=A0    r4\n"
        "=A1    r5\n"
        "=A2    r6\n"
        "=A3    r7\n"
        "=R0    r0\n"
        "gpr    r0      .32 0       0\n"
        "gpr    r1      .32 4       0\n"
        "gpr    r2      .32 8       0\n"
        "gpr    r3      .32 12      0\n"
        "gpr    r4      .32 16      0\n"
        "gpr    r5      .32 20      0\n"
        "gpr    r6      .32 24      0\n"
        "gpr    r7      .32 28      0\n"
        "gpr    r0b     .32 32      0\n"
        "gpr    r1b     .32 36      0\n"
        "gpr    r2b     .32 40      0\n"
        "gpr    r3b     .32 44      0\n"
        "gpr    r4b     .32 48      0\n"
        "gpr    r5b     .32 52      0\n"
        "gpr    r6b     .32 56      0\n"
        "gpr    r7b     .32 60      0\n"
        "gpr    r8      .32 64      0\n"
        "gpr    r9      .32 68      0\n"
        "gpr    r10     .32 72      0\n"
        "gpr    r11     .32 76      0\n"
        "gpr    r12     .32 80      0\n"
        "gpr    r13     .32 84      0\n"
        "gpr    r14     .32 88      0\n"
        "gpr    r15     .32 92      0\n"
        "gpr    pc      .32 96      0\n"
        "gpr    sr      .32 100     0\n"
        "gpr    sr_t    .1  100.0   0\n"
        "gpr    sr_s    .1  100.1   0\n"
        "gpr    sr_i    .4  100.4   0\n"
        "gpr    sr_q    .1  101.0   0\n"
        "gpr    sr_m    .1  101.1   0\n"
        "gpr    sr_f    .1  101.7   0\n"
        "gpr    sr_b    .1  103.4   0\n"
        "gpr    sr_r    .1  103.5   0\n"
        "gpr    sr_d    .1  103.6   0\n"
        "gpr    gbr     .32 104     0\n"
        "gpr    ssr     .32 108     0\n"
        "gpr    spc     .32 112     0\n"
        "gpr    sgr     .32 116     0\n"
        "gpr    dbr     .32 120     0\n"
        "gpr    vbr     .32 124     0\n"
        "gpr    mach    .32 128     0\n"
        "gpr    macl    .32 132     0\n"
        "gpr    pr      .32 136     0\n";
 
    return strdup(p);
}

References p, and strdup().

sh_op()

static int sh_op ( RzAnalysis *  analysis, RzAnalysisOp *  op, ut64  addr, const ut8 *  data, int  len, RzAnalysisOpMask  mask  )

static

Definition at line 1087 of file analysis_sh.c.

                                                                                                                     {
    ut8 op_MSB, op_LSB;
    int ret;
    if (!data || len < 2) {
        return 0;
    }
    op->addr = addr;
    op->type = RZ_ANALYSIS_OP_TYPE_UNK;
 
    op->size = 2;
 
    op_MSB = analysis->big_endian ? data[0] : data[1];
    op_LSB = analysis->big_endian ? data[1] : data[0];
    ut16 opcode = (ut16)op_MSB << 8 | op_LSB;
    ret = first_nibble_decode[(op_MSB >> 4) & 0x0F](analysis, op, opcode);
 
    // RzIL uplifting
    SHOp *ilop = sh_disassembler(opcode);
    SHILContext *ctx = RZ_NEW0(SHILContext);
    ctx->use_banked = true;
 
    rz_sh_il_opcode(analysis, op, addr, ilop, ctx);
    RZ_FREE(ctx);
    RZ_FREE(ilop);
 
    return ret;
}

References addr, rz_analysis_t::big_endian, first_nibble_decode, len, RZ_ANALYSIS_OP_TYPE_UNK, RZ_FREE, RZ_NEW0, rz_sh_il_opcode(), and sh_disassembler().

Variable Documentation

first_nibble_decode

int(* first_nibble_decode[])(RzAnalysis *, RzAnalysisOp *, ut16) ( RzAnalysis *  , RzAnalysisOp *  , ut16    )

static

Initial value:

= {
    first_nibble_is_0,
    movl_reg_rdisp,
    first_nibble_is_2,
    first_nibble_is_3,
    first_nibble_is_4,
    movl_rdisp_reg,
    first_nibble_is_6,
    add_imm,
    first_nibble_is_8,
    movw_pcdisp_reg,
    bra,
    bsr,
    first_nibble_is_c,
    movl_pcdisp_reg,
    mov_imm_reg,
    fpu_insn
}

Definition at line 1065 of file analysis_sh.c.

Referenced by sh_op().

regs

char* regs[] = { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", "pc" }

static

Definition at line 203 of file analysis_sh.c.

Referenced by _extract_regs(), analysis_fill_ai_rg(), analysis_fill_r0_reg_ref(), analysis_regrel_jump(), autocmplt_reg(), avr_custom_des(), esil_peek_some(), esil_poke_some(), exists_reg_list(), fillRegisterValues(), filter(), foreach_reg_set_or_clear(), gdbr_parse_target_xml(), gdbr_write_bin_registers(), get_register_id(), linux_reg_read(), parse_line_raw(), parse_opcodes(), parseReg(), print_line_op(), regs_to_flags(), rz_bin_dwarf_line_header_reset_regs(), rz_bin_dwarf_line_op_run(), rz_core_bin_dwarf_print_line_units(), rz_debug_dmp_reg_read(), rz_il_reg_binding_derive(), rz_il_reg_binding_exactly(), rz_reg_filter_items_covered(), rz_reg_get_list(), rz_xnu_thread_get_gpr(), rz_xnu_thread_set_drx(), rz_xnu_thread_set_gpr(), and store_line_sample().

rizin_plugin

RZ_API RzLibStruct rizin_plugin

Initial value:

= {
    .type = RZ_LIB_TYPE_ANALYSIS,
    .data = &rz_analysis_plugin_sh,
    .version = RZ_VERSION
}

Definition at line 1200 of file analysis_sh.c.

rz_analysis_plugin_sh

RzAnalysisPlugin rz_analysis_plugin_sh

Initial value:

= {
    .name = "sh",
    .desc = "SH-4 code analysis plugin",
    .license = "LGPL3",
    .arch = "sh",
    .archinfo = archinfo,
    .bits = 32,
    .op = &sh_op,
    .get_reg_profile = &sh_get_reg_profile,
    .esil = true,
    .il_config = rz_sh_il_config
 
}

Definition at line 1185 of file analysis_sh.c.