Rizin
unix-like reverse engineering framework and cli tools
arcompact-dis.c
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1 /* Instruction printing code for the ARC.
2  Copyright 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2005, 2006, 2007, 2008, 2009
3  Free Software Foundation, Inc.
4  Contributed by Doug Evans (dje@cygnus.com).
5 
6  Copyright 2008-2012 Synopsys Inc.
7 
8  This program is free software; you can redistribute it and/or modify
9  it under the terms of the GNU General Public License as published by
10  the Free Software Foundation; either version 2 of the License, or
11  (at your option) any later version.
12 
13  This program is distributed in the hope that it will be useful,
14  but WITHOUT ANY WARRANTY; without even the implied warranty of
15  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16  GNU General Public License for more details.
17 
18  You should have received a copy of the GNU General Public License
19  along with this program; if not, write to the Free Software
20  Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21  MA 02110-1301, USA. */
22 
23 #include <ctype.h>
24 #include <stdarg.h>
25 #include <ansidecl.h>
26 #include <string.h>
27 #include <stdio.h>
28 
29 #include "disas-asm.h"
30 #include "arc.h"
31 #include "arc-ext.h"
32 #include "arc-dis.h"
33 #include "arcompact-dis.h"
34 #include "elf-bfd.h"
35 
36 static bfd_vma bfd_getm32(unsigned int);
37 static bfd_vma bfd_getm32_ac(unsigned int) ATTRIBUTE_UNUSED;
38 
39 #undef _NELEM
40 #define _NELEM(ary) (sizeof(ary) / sizeof((ary)[0]))
41 
42 #define BIT(word, n) ((word) & (1 << (n)))
43 /* START ARC LOCAL */
44 #define BITS(word, s, e) (((word) << (sizeof(word) * 8 - 1 - (e))) >> ((s) + (sizeof(word) * 8 - 1 - (e))))
45 /* END ARC LOCAL */
46 #define OPCODE(word) (BITS((word), 27, 31))
47 #define FIELDA(word) (BITS((word), 0, 5))
48 #define FIELDb(word) (BITS((word), 24, 26))
49 #define FIELDB(word) (BITS((word), 12, 14))
50 #define FIELDC(word) (BITS((word), 6, 11))
51 #define OPCODE_AC(word) (BITS((word), 11, 15))
52 #define FIELDA_AC(word) (BITS((word), 0, 2))
53 #define FIELDB_AC(word) (BITS((word), 8, 10))
54 #define FIELDC_AC(word) (BITS((word), 5, 7))
55 #define FIELDU_AC(word) (BITS((word), 0, 4))
56 
57 /*
58  * FIELDS_AC is the 11-bit signed immediate value used for
59  * GP-relative instructions.
60  */
61 #define FIELDS_AC(word) (BITS(((signed int)(word)), 0, 8))
62 
63 /*
64  * FIELDD is signed in all of its uses, so we make sure argument is
65  * treated as signed for bit shifting purposes.
66  */
67 #define FIELDD(word) (BITS(((signed int)(word)), 16, 23))
68 
69 /*
70  * FIELDD9 is the 9-bit signed immediate value used for
71  * load/store instructions.
72  */
73 #define FIELDD9(word) ((BITS(((signed int)(word)), 15, 15) << 8) | (BITS((word), 16, 23)))
74 
75 /*
76  * FIELDS is the 12-bit signed immediate value
77  */
78 #define FIELDS(word) ((BITS(((signed int)(word)), 0, 5) << 6) | (BITS((word), 6, 11)))
79 
80 /*
81  * FIELD S9 is the 9-bit signed immediate value used for
82  * bbit0/bbit instruction
83  */
84 #define FIELDS9(word) (((BITS(((signed int)(word)), 15, 15) << 7) | (BITS((word), 17, 23))) << 1)
85 #define FIELDS9_FLAG(word) (((BITS(((signed int)(word)), 0, 5) << 6) | (BITS((word), 6, 11))))
86 
87 #define PUT_NEXT_WORD_IN(a) \
88  { \
89  if (is_limm == 1 && !NEXT_WORD(1)) { \
90  mwerror(state, "Illegal limm reference in last instruction!\n"); \
91  } \
92  if (info->endian == BFD_ENDIAN_LITTLE) { \
93  (a) = ((state->words[1] & 0xff00) | (state->words[1] & 0xff)) << 16; \
94  (a) |= ((state->words[1] & 0xff0000) | (state->words[1] & 0xff000000)) >> 16; \
95  } else { \
96  (a) = state->words[1]; \
97  } \
98  }
99 
100 #define CHECK_NULLIFY() \
101  do { \
102  state->nullifyMode = BITS(state->words[0], 5, 5); \
103  } while (0)
104 
105 #define CHECK_COND_NULLIFY() \
106  do { \
107  state->nullifyMode = BITS(state->words[0], 5, 5); \
108  cond = BITS(state->words[0], 0, 4); \
109  } while (0)
110 
111 #define CHECK_FLAG_COND_NULLIFY() \
112  do { \
113  if (is_shimm == 0) { \
114  flag = BIT(state->words[0], 15); \
115  state->nullifyMode = BITS(state->words[0], 5, 5); \
116  cond = BITS(state->words[0], 0, 4); \
117  } \
118  } while (0)
119 
120 #define CHECK_FLAG_COND() \
121  { \
122  if (is_shimm == 0) { \
123  flag = BIT(state->words[0], 15); \
124  cond = BITS(state->words[0], 0, 4); \
125  } \
126  }
127 
128 #define CHECK_FLAG() \
129  { \
130  flag = BIT(state->words[0], 15); \
131  }
132 
133 #define CHECK_COND() \
134  { \
135  if (is_shimm == 0) { \
136  cond = BITS(state->words[0], 0, 4); \
137  } \
138  }
139 
140 #define CHECK_FIELD(field) \
141  { \
142  if ((field) == 62) { \
143  is_limm++; \
144  field##isReg = 0; \
145  PUT_NEXT_WORD_IN(field); \
146  } \
147  }
148 
149 #define CHECK_FIELD_A() \
150  { \
151  fieldA = FIELDA(state->words[0]); \
152  if (fieldA == 62) { \
153  fieldAisReg = 0; \
154  fieldA = 0; \
155  } \
156  }
157 
158 #define FIELD_B() \
159  { \
160  fieldB = (FIELDB(state->words[0]) << 3); \
161  fieldB |= FIELDb(state->words[0]); \
162  if (fieldB == 62) { \
163  fieldBisReg = 0; \
164  fieldB = 0; \
165  } \
166  }
167 
168 #define FIELD_C() \
169  { \
170  fieldC = FIELDC(state->words[0]); \
171  if (fieldC == 62) { \
172  fieldCisReg = 0; \
173  } \
174  }
175 /********** Aurora SIMD ARC 8 - bit constant **********/
176 #define FIELD_U8() \
177  { \
178 \
179  fieldC = BITS(state->words[0], 15, 16); \
180  fieldC = fieldC << 6; \
181  fieldC |= FIELDC(state->words[0]); \
182  fieldCisReg = 0; \
183  }
184 
185 #define CHECK_FIELD_B() \
186  { \
187  fieldB = (FIELDB(state->words[0]) << 3); \
188  fieldB |= FIELDb(state->words[0]); \
189  CHECK_FIELD(fieldB); \
190  }
191 
192 #define CHECK_FIELD_C() \
193  { \
194  fieldC = FIELDC(state->words[0]); \
195  CHECK_FIELD(fieldC); \
196  }
197 
198 #define FIELD_C_S() \
199  { \
200  fieldC_S = (FIELDC_S(state->words[0]) << 3); \
201  }
202 
203 #define FIELD_B_S() \
204  { \
205  fieldB_S = (FIELDB_S(state->words[0]) << 3); \
206  }
207 
208 #define CHECK_FIELD_H_AC() \
209  { \
210  fieldC = ((FIELDA_AC(state->words[0])) << 3); \
211  fieldC |= FIELDC_AC(state->words[0]); \
212  CHECK_FIELD(fieldC); \
213  }
214 
215 #define FIELD_H_AC() \
216  { \
217  fieldC = ((FIELDA_AC(state->words[0])) << 3); \
218  fieldC |= FIELDC_AC(state->words[0]); \
219  if (fieldC > 60) { \
220  fieldCisReg = 0; \
221  fieldC = 0; \
222  } \
223  }
224 
225 #define FIELD_C_AC() \
226  { \
227  fieldC = FIELDC_AC(state->words[0]); \
228  if (fieldC > 3) { \
229  fieldC += 8; \
230  } \
231  }
232 
233 #define FIELD_B_AC() \
234  { \
235  fieldB = FIELDB_AC(state->words[0]); \
236  if (fieldB > 3) { \
237  fieldB += 8; \
238  } \
239  }
240 
241 #define FIELD_A_AC() \
242  { \
243  fieldA = FIELDA_AC(state->words[0]); \
244  if (fieldA > 3) { \
245  fieldA += 8; \
246  } \
247  }
248 
249 #define IS_SMALL(x) (((field##x) < 256) && ((field##x) > -257))
250 #define IS_REG(x) (field##x##isReg)
251 #define IS_SIMD_128_REG(x) (usesSimdReg##x == 1)
252 #define IS_SIMD_16_REG(x) (usesSimdReg##x == 2)
253 #define IS_SIMD_DATA_REG(x) (usesSimdReg##x == 3)
254 #define WRITE_FORMAT_LB_Rx_RB(x) WRITE_FORMAT(x, "[", "]", "", "")
255 #define WRITE_FORMAT_x_COMMA_LB(x) WRITE_FORMAT(x, "", ", [", "", ",[")
256 #define WRITE_FORMAT_COMMA_x_RB(x) WRITE_FORMAT(x, ", ", "]", ", ", "]")
257 #define WRITE_FORMAT_x_RB(x) WRITE_FORMAT(x, "", "]", "", "]")
258 #define WRITE_FORMAT_COMMA_x(x) WRITE_FORMAT(x, ", ", "", ", ", "")
259 #define WRITE_FORMAT_x_COMMA(x) WRITE_FORMAT(x, "", ", ", "", ", ")
260 #define WRITE_FORMAT_x(x) WRITE_FORMAT(x, "", "", "", "")
261 #define WRITE_FORMAT(x, cb1, ca1, cb, ca) strcat(formatString, \
262  (IS_SIMD_128_REG(x) ? cb1 "%S" ca1 : IS_SIMD_16_REG(x) ? cb1 "%I" ca1 \
263  : IS_SIMD_DATA_REG(x) ? cb1 "%D" ca1 \
264  : IS_REG(x) ? cb1 "%r" ca1 \
265  : usesAuxReg ? cb "%a" ca \
266  : IS_SMALL(x) ? cb "%d" ca \
267  : cb "%h" ca))
268 
269 #define WRITE_FORMAT_LB() strcat(formatString, "[")
270 #define WRITE_FORMAT_RB() strcat(formatString, "]")
271 #define WRITE_COMMENT(str) (state->comm[state->commNum++] = (str))
272 #define WRITE_NOP_COMMENT() \
273  if (!fieldAisReg && !flag) \
274  WRITE_COMMENT("nop");
275 
276 #define NEXT_WORD(x) (offset += 4, state->words[x])
277 
278 #define NEXT_WORD_AC(x) (offset += 2, state->words[x])
279 
280 #define add_target(x) (state->targets[state->tcnt++] = (x))
281 
282 static short int enable_simd = 0;
283 static short int enable_insn_stream = 0;
284 
285 static const char *
286 core_reg_name(struct arcDisState *state, int val) {
287  if (state->coreRegName) {
288  return (*state->coreRegName)(state->_this, val);
289  }
290  return 0;
291 }
292 
293 static const char *
294 aux_reg_name(struct arcDisState *state, int val) {
295  if (state->auxRegName) {
296  return (*state->auxRegName)(state->_this, val);
297  }
298  return 0;
299 }
300 
301 static const char *
302 cond_code_name(struct arcDisState *state, int val) {
303  if (state->condCodeName) {
304  return (*state->condCodeName)(state->_this, val);
305  }
306  return 0;
307 }
308 
309 static const char *
310 instruction_name(struct arcDisState *state, int op1, int op2, int *flags) {
311  if (state->instName) {
312  return (*state->instName)(state->_this, op1, op2, flags);
313  }
314  return 0;
315 }
316 
317 static void
318 mwerror(struct arcDisState *state, const char *msg) {
319  if (state->err != 0) {
320  (*state->err)(state->_this, (msg));
321  }
322 }
323 
324 static const char *
325 post_address(struct arcDisState *state, int addr) {
326  static char id[3 * _NELEM(state->addresses)];
327  unsigned int j, i = state->acnt;
328  if (i < _NELEM(state->addresses)) {
329  state->addresses[i] = addr;
330  ++state->acnt;
331  j = i * 3;
332  id[j + 0] = '@';
333  id[j + 1] = '0' + i;
334  id[j + 2] = 0;
335  return id + j;
336  }
337  return "";
338 }
339 
340 static void
341 my_sprintf(struct arcDisState *state, char *buf, const char *format, ...) {
342  char *bp;
343  const char *p;
344  int size, leading_zero, regMap[2];
345  va_list ap;
346 
347  va_start(ap, format);
348  bp = buf;
349  *bp = 0;
350  p = format;
351  regMap[0] = 0;
352  regMap[1] = 0;
353  while (1) {
354  switch (*p++) {
355  case 0: goto DOCOMM; /*(return) */
356  default:
357  *bp++ = p[-1];
358  break;
359  case '%':
360  size = 0;
361  leading_zero = 0;
362  RETRY:;
363  switch (*p++) {
364  case '0':
365  case '1':
366  case '2':
367  case '3':
368  case '4':
369  case '5':
370  case '6':
371  case '7':
372  case '8':
373  case '9': {
374  /* size. */
375  size = p[-1] - '0';
376  if (size == 0) {
377  leading_zero = 1; /* e.g. %08x */
378  }
379  while (*p >= '0' && *p <= '9') {
380  size = size * 10 + *p - '0', p++;
381  }
382  goto RETRY;
383  }
384 #define inc_bp() bp = bp + strlen(bp)
385 
386  case 'h': {
387  unsigned u = va_arg(ap, int);
388  /*
389  * Hex. We can change the format to 0x%08x in
390  * one place, here, if we wish.
391  * We add underscores for easy reading.
392  */
393 #define CDT_DEBUG
394  if (u > 65536) {
395 #ifndef CDT_DEBUG
396  sprintf(bp, "0x%x_%04x", u >> 16, u & 0xffff);
397 #else
398  sprintf(bp, "0x%08x", u);
399 #endif // CDT_DEBUG
400  } else {
401  sprintf(bp, "0x%x", u);
402  }
403  inc_bp();
404  } break;
405  case 'X':
406  case 'x': {
407  int val = va_arg(ap, int);
408  if (size != 0) {
409  if (leading_zero) {
410  sprintf(bp, "%0*x", size, val);
411  } else {
412  sprintf(bp, "%*x", size, val);
413  }
414  } else {
415  sprintf(bp, "%x", val);
416  }
417  inc_bp();
418  } break;
419  case 'd': {
420  int val = va_arg(ap, int);
421  if (size != 0) {
422  sprintf(bp, "%*d", size, val);
423  } else {
424  sprintf(bp, "%d", val);
425  }
426  inc_bp();
427  } break;
428  case 'r': {
429  /* Register. */
430  int val = va_arg(ap, int);
431 
432 #define REG2NAME(num, name) \
433  case num: \
434  sprintf(bp, "" name); \
435  regMap[((num) < 32) ? 0 : 1] |= 1 << ((num) - (((num) < 32) ? 0 : 32)); \
436  break;
437  switch (val) {
438  REG2NAME(26, "gp");
439  REG2NAME(27, "fp");
440  REG2NAME(28, "sp");
441  REG2NAME(29, "ilink1");
442  REG2NAME(30, "ilink2");
443  REG2NAME(31, "blink");
444  REG2NAME(60, "lp_count");
445  REG2NAME(63, "pcl");
446  default: {
447  const char *ext;
448  ext = core_reg_name(state, val);
449  if (ext) {
450  sprintf(bp, "%s", ext);
451  } else {
452  sprintf(bp, "r%d", val);
453  }
454  } break;
455  }
456  inc_bp();
457  } break;
458 
459  case 'a': {
460  /* Aux Register. */
461  int val = va_arg(ap, int);
462  char *ret;
463  ret = arc_aux_reg_name(val);
464  if (ret) {
465  sprintf(bp, "%s", ret);
466  } else {
467  const char *ext;
468  ext = aux_reg_name(state, val);
469  if (ext) {
470  sprintf(bp, "%s", ext);
471  } else {
472  my_sprintf(state, bp, "%h", val);
473  }
474  }
475 
476  inc_bp();
477  } break;
478  case 's': {
479  sprintf(bp, "%s", va_arg(ap, char *));
480  inc_bp();
481  } break;
482  case '*': {
483 #if 0
484  va_arg(ap,char*);
485  inc_bp();
486  break;
487 #elif 1 /* used for prefetch to skip an argument. */
488  va_arg(ap, int);
489  break;
490 #else
491  extern void abort(void);
492 
493  abort();
494 #endif
495  }
496 
497  /* SIMD operands follow*/
498  case 'S': {
499  int val = va_arg(ap, int);
500 
501  sprintf(bp, "vr%d", val);
502  inc_bp();
503  break;
504  }
505  case 'I': {
506  int val = va_arg(ap, int);
507 
508  sprintf(bp, "i%d", val);
509  inc_bp();
510  break;
511  }
512  case 'D': {
513  int val = va_arg(ap, int);
514 
515  sprintf(bp, "dr%d", val);
516  inc_bp();
517  break;
518  }
519  /* SIMD operands end */
520  default:
521  fprintf(stderr, "?? format %c\n", p[-1]);
522  break;
523  }
524  }
525  }
526 
527 DOCOMM:
528  *bp = 0;
529  va_end(ap);
530 }
531 
532 static const char *condName[] = {
533  /* 0..15. */
534  "", "z", "nz", "p", "n", "c", "nc", "v",
535  "nv", "gt", "ge", "lt", "le", "hi", "ls", "pnz",
536  "ss", "sc"
537 
538 };
539 
540 static void
541 write_instr_name_(struct arcDisState *state,
542  const char *instrName,
543  int cond,
544  int condCodeIsPartOfName,
545  int flag,
546  int signExtend,
547  int addrWriteBack,
548  int directMem) {
549  if (!instrName) {
550  return;
551  }
552  strncpy(state->instrBuffer, instrName, sizeof(state->instrBuffer) - 1);
553  if (cond > 0) {
554  int condlim = 0; /* condition code limit*/
555  const char *cc = 0;
556  if (!condCodeIsPartOfName) {
557  strcat(state->instrBuffer, ".");
558  }
559  condlim = 18;
560  if (cond < condlim) {
561  cc = condName[cond];
562  } else {
563  cc = cond_code_name(state, cond);
564  }
565  if (!cc) {
566  cc = "???";
567  }
568  strcat(state->instrBuffer, cc);
569  }
570  if (flag) {
571  strcat(state->instrBuffer, ".f");
572  }
573  if (state->nullifyMode) {
574  if (strstr(state->instrBuffer, ".d") == NULL) {
575  strcat(state->instrBuffer, ".d");
576  }
577  }
578  if (signExtend) {
579  strcat(state->instrBuffer, ".x");
580  }
581  switch (addrWriteBack) {
582  case 1: strcat(state->instrBuffer, ".a"); break;
583  case 2: strcat(state->instrBuffer, ".ab"); break;
584  case 3: strcat(state->instrBuffer, ".as"); break;
585  }
586  if (directMem) {
587  strcat(state->instrBuffer, ".di");
588  }
589 }
590 
591 #define write_instr_name() \
592  { \
593  write_instr_name_(state, instrName, cond, condCodeIsPartOfName, flag, signExtend, addrWriteBack, directMem); \
594  formatString[0] = '\0'; \
595  }
596 
597 enum {
598  op_BC = 0,
599  op_BLC = 1,
600  op_LD = 2,
601  op_ST = 3,
602  op_MAJOR_4 = 4,
603  /* START ARC LOCAL */
604  op_MAJOR_5 = 5,
605  op_MAJOR_6 = 6,
606  op_SIMD = 9,
607  op_LD_ADD = 12,
608  op_ADD_SUB_SHIFT = 13,
609  /* END ARC LOCAL */
610  op_ADD_MOV_CMP = 14,
611  op_S = 15,
612  op_LD_S = 16,
613  op_LDB_S = 17,
614  op_LDW_S = 18,
615  op_LDWX_S = 19,
616  op_ST_S = 20,
617  op_STB_S = 21,
618  op_STW_S = 22,
619  op_Su5 = 23,
620  op_SP = 24,
621  op_GP = 25,
622  op_Pcl = 26,
623  op_MOV_S = 27,
624  op_ADD_CMP = 28,
625  op_BR_S = 29,
626  op_B_S = 30,
627  op_BL_S = 31
628 };
629 
630 extern disassemble_info tm_print_insn_info;
631 
632 /*
633  * bfd_getm32 - To retrieve the upper 16-bits of the ARCtangent-A5
634  * basecase (32-bit) instruction
635  */
636 static bfd_vma
637 bfd_getm32(data)
638 unsigned int data;
639 {
640  bfd_vma value = 0;
641 
642  value = ((data & 0xff00) | (data & 0xff)) << 16;
643  value |= ((data & 0xff0000) | (data & 0xff000000)) >> 16;
644  return value;
645 }
646 
647 /*
648  * bfd_getm32_ac - To retrieve the upper 8-bits of the ARCompact
649  * 16-bit instruction
650  */
651 static bfd_vma
652 bfd_getm32_ac(data)
653 unsigned int data;
654 {
655  bfd_vma value = 0;
656 
657  value = ((data & 0xff) << 8 | (data & 0xff00) >> 8);
658  return value;
659 }
660 
661 /*
662  * sign_extend - Sign Extend the value
663  *
664  */
665 static int
666 sign_extend(int value, int bits) {
667  if (BIT(value, (bits - 1))) {
668  value |= (0xffffffff << bits);
669  }
670  return value;
671 }
672 
673 /* dsmOneArcInst - This module is used to identify the instruction
674  * and to decode them based on the ARCtangent-A5
675  * instruction set architecture.
676  * First, the major opcode is computed. Based on the
677  * major opcode and sub opcode, the instruction is
678  * identified. The appropriate decoding class is assigned
679  * based on the instruction.Further subopcode 2 is used in
680  * cases where decoding upto subopcode1 is not possible.
681  *
682  * The instruction is then decoded accordingly.
683  */
684 static int
685 dsmOneArcInst(bfd_vma addr, struct arcDisState *state, disassemble_info *info) {
686 
687  int subopcode, mul;
688  int condCodeIsPartOfName = 0;
689  int decodingClass;
690  const char *instrName;
691  int fieldAisReg = 1, fieldBisReg = 1, fieldCisReg = 1;
692  int fieldA = 0, fieldB = 0, fieldC = 0;
693  int flag = 0, cond = 0, is_shimm = 0, is_limm = 0;
694  int signExtend = 0, addrWriteBack = 0, directMem = 0;
695  int is_linked = 0;
696  int offset = 0;
697  int usesAuxReg = 0;
698  int usesSimdRegA = 0, usesSimdRegB = 0, usesSimdRegC = 0, simd_scale_u8 = -1;
699  int flags = !E_ARC_MACH_A4;
700  char formatString[60];
701 
702  state->nullifyMode = BR_exec_when_no_jump;
703  state->isBranch = 0;
704 
705  state->_mem_load = 0;
706  state->_ea_present = 0;
707  state->_load_len = 0;
708  state->ea_reg1 = no_reg;
709  state->ea_reg2 = no_reg;
710  state->_offset = 0;
711 
712  state->sourceType = ARC_UNDEFINED;
713 
714  /* ARCtangent-A5 basecase instruction and little-endian mode */
715  if ((info->endian == BFD_ENDIAN_LITTLE) && (state->instructionLen == 4)) {
716  state->words[0] = bfd_getm32(state->words[0]);
717  }
718 
719  if (state->instructionLen == 4) {
720  if (!NEXT_WORD(0)) {
721  return 0;
722  }
723  /* Get the major opcode of the ARCtangent-A5 32-bit instruction. */
724  state->_opcode = OPCODE(state->words[0]);
725  } else {
726  /* ARCompact 16-bit instruction */
727  if (!NEXT_WORD_AC(0)) {
728  return 0;
729  }
730  /* Get the major opcode of the ARCompact 16-bit instruction. */
731  state->_opcode = OPCODE_AC(state->words[0]);
732  }
733 
734  instrName = 0;
735  decodingClass = 0; /* default! */
736  mul = 0;
737  condCodeIsPartOfName = 0;
738  state->commNum = 0;
739  state->tcnt = 0;
740  state->acnt = 0;
741  state->flow = noflow;
742 
743  /* Find the match for the opcode. Once the major opcode category is
744  * identified, get the subopcode to determine the exact instruction.
745  * Based on the instruction identified, select the decoding class.
746  * If condition code is part of the instruction name, then set the
747  * flag 'condCodeIsPartOfName'.
748  * For branch, jump instructions set 'isBranch' (state->isBranch).
749  */
750 
751  switch (state->_opcode) {
752  case op_BC:
753  /* Branch Conditionally */
754  instrName = "b";
755  decodingClass = 13;
756  condCodeIsPartOfName = 1;
757  state->isBranch = 1;
758  break;
759 
760  case op_BLC:
761  /* Branch and Link, Compare and Branch */
762  decodingClass = 9;
763  state->isBranch = 1;
764  switch (BITS(state->words[0], 16, 16)) {
765  case 0:
766  if (!instrName) {
767  instrName = "bl";
768  }
769  decodingClass = 13;
770  condCodeIsPartOfName = 1;
771  break;
772  case 1:
773  switch (BITS(state->words[0], 0, 3)) {
774  case 0: instrName = "breq"; break;
775  case 1: instrName = "brne"; break;
776  case 2: instrName = "brlt"; break;
777  case 3: instrName = "brge"; break;
778  case 4: instrName = "brlo"; break;
779  case 5: instrName = "brhs"; break;
780  case 14: instrName = "bbit0"; break;
781  case 15: instrName = "bbit1"; break;
782  default:
783  instrName = "??? (0[3])";
784  state->flow = invalid_instr;
785  break;
786  }
787  break;
788  default:
789  instrName = "??? (0[3])";
790  state->flow = invalid_instr;
791  break;
792  }
793  break;
794 
795  case op_LD:
796  /* Load register with offset [major opcode 2] */
797  decodingClass = 6;
798  switch (BITS(state->words[0], 7, 8)) {
799  case 0:
800  instrName = "ld";
801  state->_load_len = 4;
802  break;
803  case 1:
804  instrName = "ldb";
805  state->_load_len = 1;
806  break;
807  case 2:
808  instrName = "ldw";
809  state->_load_len = 2;
810  break;
811  default:
812  instrName = "??? (0[3])";
813  state->flow = invalid_instr;
814  break;
815  }
816  break;
817 
818  case op_ST:
819  /* Store register with offset [major opcode 0x03] */
820  decodingClass = 7;
821  switch (BITS(state->words[0], 1, 2)) {
822  case 0: instrName = "st"; break;
823  case 1: instrName = "stb"; break;
824  case 2: instrName = "stw"; break;
825  default:
826  instrName = "??? (2[3])";
827  state->flow = invalid_instr;
828  break;
829  }
830  break;
831 
832  case op_MAJOR_4:
833  /* ARC 32-bit basecase instructions with 3 Operands */
834  decodingClass = 0; /* Default for 3 operand instructions */
835  subopcode = BITS(state->words[0], 16, 21);
836  switch (subopcode) {
837  case 0: instrName = "add"; break;
838  case 1: instrName = "adc"; break;
839  case 2: instrName = "sub"; break;
840  case 3: instrName = "sbc"; break;
841  case 4: instrName = "and"; break;
842  case 5: instrName = "or"; break;
843  case 6: instrName = "bic"; break;
844  case 7: instrName = "xor"; break;
845  case 8: instrName = "max"; break;
846  case 9: instrName = "min"; break;
847  case 10: {
848  if (state->words[0] == 0x264a7000) {
849  instrName = "nop";
850  decodingClass = 26;
851  } else {
852  instrName = "mov";
853  decodingClass = 12;
854  }
855  break;
856  }
857  case 11:
858  instrName = "tst";
859  decodingClass = 2;
860  break;
861  case 12:
862  instrName = "cmp";
863  decodingClass = 2;
864  break;
865  case 13:
866  instrName = "rcmp";
867  decodingClass = 2;
868  break;
869  case 14: instrName = "rsub"; break;
870  case 15: instrName = "bset"; break;
871  case 16: instrName = "bclr"; break;
872  case 17:
873  instrName = "btst";
874  decodingClass = 2;
875  break;
876  case 18: instrName = "bxor"; break;
877  case 19: instrName = "bmsk"; break;
878  case 20: instrName = "add1"; break;
879  case 21: instrName = "add2"; break;
880  case 22: instrName = "add3"; break;
881  case 23: instrName = "sub1"; break;
882  case 24: instrName = "sub2"; break;
883  case 25: instrName = "sub3"; break;
884  case 30: instrName = "mpyw"; break;
885  case 31: instrName = "mpyuw"; break;
886  case 32:
887  case 33:
888  instrName = "j";
889  // fallthrough
890  case 34:
891  case 35:
892  if (!instrName) {
893  instrName = "jl";
894  }
895  decodingClass = 4;
896  condCodeIsPartOfName = 1;
897  state->isBranch = 1;
898  break;
899  case 40:
900  instrName = "lp";
901  decodingClass = 11;
902  condCodeIsPartOfName = 1;
903  state->isBranch = 1;
904  break;
905  case 41:
906  instrName = "flag";
907  decodingClass = 3;
908  break;
909  case 42:
910  instrName = "lr";
911  decodingClass = 10;
912  break;
913  case 43:
914  instrName = "sr";
915  decodingClass = 8;
916  break;
917  case 47:
918  decodingClass = 1;
919  switch (BITS(state->words[0], 0, 5)) /* Checking based on Subopcode2 */
920  {
921  case 0: instrName = "asl"; break;
922  case 1: instrName = "asr"; break;
923  case 2: instrName = "lsr"; break;
924  case 3: instrName = "ror"; break;
925  case 4: instrName = "rrc"; break;
926  case 5: instrName = "sexb"; break;
927  case 6: instrName = "sexw"; break;
928  case 7: instrName = "extb"; break;
929  case 8: instrName = "extw"; break;
930  case 9: instrName = "abs"; break;
931  case 10: instrName = "not"; break;
932  case 11: instrName = "rlc"; break;
933  case 12:
934  instrName = "ex";
935 
936  decodingClass = 34;
937  break; // ramana adds
938 
939  /* START ARC LOCAL */
940  case 16:
941  instrName = "llock";
942  decodingClass = 34;
943  break;
944  case 17:
945  instrName = "scond";
946  decodingClass = 34;
947  break;
948  /* END ARC LOCAL */
949 
950  case 63:
951  decodingClass = 26;
952  switch (BITS(state->words[0], 24, 26)) {
953  case 1:
954  instrName = "sleep";
955  decodingClass = 32;
956  break;
957  case 2:
958  if ((info->mach) == ARC_MACH_ARC7) {
959  instrName = "trap0";
960  } else {
961  instrName = "swi";
962  }
963  break;
964  case 3:
965 
966  if (BITS(state->words[0], 22, 23) == 1) {
967  instrName = "sync";
968  }
969 
970  break;
971  case 4: instrName = "rtie"; break;
972  case 5: instrName = "brk"; break;
973  default:
974 
975  instrName = "???";
976  state->flow = invalid_instr;
977  break;
978  }
979  break;
980  }
981  break;
982  }
983 
984  if (!instrName) {
985  subopcode = BITS(state->words[0], 17, 21);
986  decodingClass = 5;
987  switch (subopcode) {
988  case 24:
989  instrName = "ld";
990  state->_load_len = 4;
991  break;
992  case 25:
993  instrName = "ldb";
994  state->_load_len = 1;
995  break;
996  case 26:
997  instrName = "ldw";
998  state->_load_len = 2;
999  break;
1000  default:
1001  instrName = "??? (0[3])";
1002  state->flow = invalid_instr;
1003  break;
1004  }
1005  }
1006  break;
1007 
1008  case op_MAJOR_5:
1009  /* ARC 32-bit extension instructions */
1010  decodingClass = 0; /* Default for Major opcode 5 ... */
1011  subopcode = BITS(state->words[0], 16, 21);
1012  switch (subopcode) {
1013  case 0: instrName = "asl"; break;
1014  case 1: instrName = "lsr"; break;
1015  case 2: instrName = "asr"; break;
1016  case 3: instrName = "ror"; break;
1017  case 4:
1018  instrName = "mul64";
1019  mul = 1;
1020  decodingClass = 2;
1021  break;
1022  case 5:
1023  instrName = "mulu64";
1024  mul = 1;
1025  decodingClass = 2;
1026  break;
1027 
1028  /* ARC A700 */
1029  case 6: instrName = "adds"; break;
1030 
1031  case 7: instrName = "subs"; break;
1032  case 8: instrName = "divaw"; break;
1033  case 0xA: instrName = "asls"; break;
1034  case 0xB: instrName = "asrs"; break;
1035  case 0x28: instrName = "addsdw"; break;
1036  case 0x29: instrName = "subsdw"; break;
1037 
1038  case 47:
1039  switch (BITS(state->words[0], 0, 5)) {
1040  case 0:
1041  instrName = "swap";
1042  decodingClass = 1;
1043  break;
1044  case 1:
1045  instrName = "norm";
1046  decodingClass = 1;
1047  break;
1048  /* ARC A700 DSP Extensions */
1049  case 2:
1050  instrName = "sat16";
1051  decodingClass = 1;
1052  break;
1053  case 3:
1054  instrName = "rnd16";
1055  decodingClass = 1;
1056  break;
1057  case 4:
1058  instrName = "abssw";
1059  decodingClass = 1;
1060  break;
1061  case 5:
1062  instrName = "abss";
1063  decodingClass = 1;
1064  break;
1065  case 6:
1066  instrName = "negsw";
1067  decodingClass = 1;
1068  break;
1069  case 7:
1070  instrName = "negs";
1071  decodingClass = 1;
1072  break;
1073 
1074  case 8:
1075  instrName = "normw";
1076  decodingClass = 1;
1077  break;
1078 
1079  /* START ARC LOCAL */
1080  case 9:
1081  instrName = "swape";
1082  decodingClass = 1;
1083  break;
1084  /* END ARC LOCAL */
1085 
1086  default:
1087  instrName = "???";
1088  state->flow = invalid_instr;
1089  break;
1090  }
1091  break;
1092  default:
1093  instrName = "??? (2[3])";
1094  state->flow = invalid_instr;
1095  break;
1096  }
1097  break;
1098 
1099  /* START ARC LOCAL */
1100  case op_MAJOR_6:
1101  decodingClass = 44; /* Default for Major opcode 6 ... */
1102  subopcode = BITS(state->words[0], 0, 5);
1103  switch (subopcode) {
1104  case 26: /* 0x1a */ instrName = "rtsc"; break;
1105  default:
1106  instrName = "??? (2[3])";
1107  state->flow = invalid_instr;
1108  break;
1109  }
1110  break;
1111  /* END ARC LOCAL */
1112 
1113  /* Aurora SIMD instruction support*/
1114  case op_SIMD:
1115 
1116  if (enable_simd) {
1117  decodingClass = 42;
1118  subopcode = BITS(state->words[0], 17, 23);
1119 
1120  switch (subopcode) {
1121 
1122  case 68:
1123  instrName = "vld32";
1124  decodingClass = 37;
1125  usesSimdRegA = 1;
1126  usesSimdRegB = 2;
1127  usesSimdRegC = 0;
1128  simd_scale_u8 = 2;
1129  break;
1130 
1131  case 72:
1132  instrName = "vld64";
1133  decodingClass = 37;
1134  usesSimdRegA = 1;
1135  usesSimdRegB = 2;
1136  usesSimdRegC = 0;
1137  simd_scale_u8 = 3;
1138  break;
1139 
1140  case 74:
1141  instrName = "vld64w";
1142  decodingClass = 37;
1143  usesSimdRegA = 1;
1144  usesSimdRegB = 2;
1145  usesSimdRegC = 0;
1146  simd_scale_u8 = 3;
1147  break;
1148 
1149  case 70:
1150  instrName = "vld32wl";
1151  decodingClass = 37;
1152  usesSimdRegA = 1;
1153  usesSimdRegB = 2;
1154  usesSimdRegC = 0;
1155  simd_scale_u8 = 2;
1156  break;
1157 
1158  case 66:
1159  instrName = "vld32wh";
1160  decodingClass = 37;
1161  usesSimdRegA = 1;
1162  usesSimdRegB = 2;
1163  usesSimdRegC = 0;
1164  simd_scale_u8 = 2;
1165  break;
1166 
1167  case 76:
1168  instrName = "vld128";
1169  decodingClass = 37;
1170  usesSimdRegA = 1;
1171  usesSimdRegB = 2;
1172  usesSimdRegC = 0;
1173  simd_scale_u8 = 4;
1174  break;
1175 
1176  case 78: {
1177  short sub_subopcode = BITS(state->words[0], 15, 16);
1178  switch (sub_subopcode) {
1179  case 0:
1180  instrName = "vld128r";
1181  decodingClass = 38;
1182  usesSimdRegA = 1;
1183  usesSimdRegB = usesSimdRegC = 0;
1184  break;
1185  default:
1186  instrName = "SIMD";
1187  state->flow = invalid_instr;
1188  }
1189  } break;
1190  case 71:
1191  instrName = "vst16_0";
1192  decodingClass = 37;
1193  usesSimdRegA = 1;
1194  usesSimdRegB = 2;
1195  usesSimdRegC = 0;
1196  simd_scale_u8 = 1;
1197  break;
1198 
1199  case 81:
1200  instrName = "vst16_1";
1201  decodingClass = 37;
1202  usesSimdRegA = 1;
1203  usesSimdRegB = 2;
1204  usesSimdRegC = 0;
1205  simd_scale_u8 = 1;
1206  break;
1207 
1208  case 67:
1209  instrName = "vst16_2";
1210  decodingClass = 37;
1211  usesSimdRegA = 1;
1212  usesSimdRegB = 2;
1213  usesSimdRegC = 0;
1214  simd_scale_u8 = 1;
1215  break;
1216 
1217  case 75:
1218  instrName = "vst16_3";
1219  decodingClass = 37;
1220  usesSimdRegA = 1;
1221  usesSimdRegB = 2;
1222  usesSimdRegC = 0;
1223  simd_scale_u8 = 1;
1224  break;
1225 
1226  case 83:
1227  instrName = "vst16_4";
1228  decodingClass = 37;
1229  usesSimdRegA = 1;
1230  usesSimdRegB = 2;
1231  usesSimdRegC = 0;
1232  simd_scale_u8 = 1;
1233  break;
1234 
1235  case 89:
1236  instrName = "vst16_5";
1237  decodingClass = 37;
1238  usesSimdRegA = 1;
1239  usesSimdRegB = 2;
1240  usesSimdRegC = 0;
1241  simd_scale_u8 = 1;
1242  break;
1243 
1244  case 91:
1245  instrName = "vst16_6";
1246  decodingClass = 37;
1247  usesSimdRegA = 1;
1248  usesSimdRegB = 2;
1249  usesSimdRegC = 0;
1250  simd_scale_u8 = 1;
1251  break;
1252 
1253  case 93:
1254  instrName = "vst16_7";
1255  decodingClass = 37;
1256  usesSimdRegA = 1;
1257  usesSimdRegB = 2;
1258  usesSimdRegC = 0;
1259  simd_scale_u8 = 1;
1260  break;
1261 
1262  case 69:
1263  instrName = "vst32_0";
1264  decodingClass = 37;
1265  usesSimdRegA = 1;
1266  usesSimdRegB = 2;
1267  usesSimdRegC = 0;
1268  simd_scale_u8 = 2;
1269  break;
1270 
1271  case 82:
1272  instrName = "vst32_2";
1273  decodingClass = 37;
1274  usesSimdRegA = 1;
1275  usesSimdRegB = 2;
1276  usesSimdRegC = 0;
1277  simd_scale_u8 = 2;
1278  break;
1279 
1280  case 86:
1281  instrName = "vst32_4";
1282  decodingClass = 37;
1283  usesSimdRegA = 1;
1284  usesSimdRegB = 2;
1285  usesSimdRegC = 0;
1286  simd_scale_u8 = 2;
1287  break;
1288 
1289  case 88:
1290  instrName = "vst32_6";
1291  decodingClass = 37;
1292  usesSimdRegA = 1;
1293  usesSimdRegB = 2;
1294  usesSimdRegC = 0;
1295  simd_scale_u8 = 2;
1296  break;
1297 
1298  case 73:
1299  instrName = "vst64";
1300  decodingClass = 37;
1301  usesSimdRegA = 1;
1302  usesSimdRegB = 2;
1303  usesSimdRegC = 0;
1304  simd_scale_u8 = 3;
1305  break;
1306 
1307  case 77:
1308  instrName = "vst128";
1309  decodingClass = 37;
1310  usesSimdRegA = 1;
1311  usesSimdRegB = 2;
1312  usesSimdRegC = 0;
1313  simd_scale_u8 = 4;
1314  break;
1315 
1316  case 79: {
1317  short sub_subopcode = BITS(state->words[0], 15, 16);
1318  switch (sub_subopcode) {
1319  case 0:
1320  instrName = "vst128r";
1321  decodingClass = 38;
1322  usesSimdRegA = 1;
1323  usesSimdRegB = usesSimdRegC = 0;
1324  break;
1325 
1326  default:
1327  instrName = "SIMD";
1328  state->flow = invalid_instr;
1329  }
1330 
1331  } break;
1332  case 80:
1333  instrName = "vmvw";
1334  usesSimdRegA = usesSimdRegB = 1;
1335  usesSimdRegC = 0;
1336  decodingClass = 39;
1337  break;
1338 
1339  case 84:
1340  instrName = "vmvzw";
1341  decodingClass = 39;
1342  usesSimdRegA = usesSimdRegB = 1;
1343  usesSimdRegC = 0;
1344  break;
1345 
1346  case 90:
1347  instrName = "vmovw";
1348  decodingClass = 39;
1349  usesSimdRegA = 1;
1350  usesSimdRegB = usesSimdRegC = 0;
1351  break;
1352 
1353  case 94:
1354  instrName = "vmovzw";
1355  decodingClass = 39;
1356  usesSimdRegA = 1;
1357  usesSimdRegB = usesSimdRegC = 0;
1358  break;
1359 
1360  case 85:
1361  instrName = "vmvaw";
1362  decodingClass = 39;
1363  usesSimdRegA = usesSimdRegB = 1;
1364  usesSimdRegC = 0;
1365  break;
1366 
1367  case 95:
1368  instrName = "vmovaw";
1369  decodingClass = 39;
1370  usesSimdRegA = 1;
1371  usesSimdRegB = usesSimdRegC = 0;
1372  break;
1373 
1374  case 10: {
1375  short sub_subopcode = BITS(state->words[0], 15, 16);
1376  switch (sub_subopcode) {
1377  case 0:
1378  instrName = "vaddw";
1379  decodingClass = 42;
1380  usesSimdRegA = usesSimdRegB = usesSimdRegC = 1;
1381  break;
1382 
1383  case 1:
1384  instrName = "vaddaw";
1385  decodingClass = 42;
1386  usesSimdRegA = usesSimdRegB = usesSimdRegC = 1;
1387  break;
1388 
1389  case 2:
1390  instrName = "vbaddw";
1391  decodingClass = 42;
1392  usesSimdRegA = usesSimdRegB = 1;
1393  usesSimdRegC = 0;
1394  break;
1395  }
1396  break;
1397  }
1398 
1399  case 11: {
1400  short sub_subopcode = BITS(state->words[0], 15, 16);
1401  switch (sub_subopcode) {
1402  case 0:
1403  instrName = "vsubw";
1404  decodingClass = 42;
1405  usesSimdRegA = usesSimdRegB = usesSimdRegC = 1;
1406  break;
1407 
1408  case 1:
1409  instrName = "vsubaw";
1410  decodingClass = 42;
1411  usesSimdRegA = usesSimdRegB = usesSimdRegC = 1;
1412  break;
1413 
1414  case 2:
1415  instrName = "vbsubw";
1416  decodingClass = 42;
1417  usesSimdRegA = usesSimdRegB = 1;
1418  usesSimdRegC = 0;
1419  break;
1420  }
1421  } break;
1422 
1423  case 12: {
1424  short sub_subopcode = BITS(state->words[0], 15, 16);
1425  switch (sub_subopcode) {
1426  case 0:
1427  instrName = "vmulw";
1428  decodingClass = 42;
1429  usesSimdRegA = usesSimdRegB = usesSimdRegC = 1;
1430  break;
1431 
1432  case 1:
1433  instrName = "vmulaw";
1434  decodingClass = 42;
1435  usesSimdRegA = usesSimdRegB = usesSimdRegC = 1;
1436  break;
1437 
1438  case 2:
1439  instrName = "vbmulw";
1440  decodingClass = 42;
1441  usesSimdRegA = usesSimdRegB = 1;
1442  usesSimdRegC = 0;
1443  break;
1444 
1445  case 3:
1446  instrName = "vbmulaw";
1447  decodingClass = 42;
1448  usesSimdRegA = usesSimdRegB = 1;
1449  usesSimdRegC = 0;
1450  break;
1451  }
1452  } break;
1453 
1454  case 13: {
1455  short sub_subopcode = BITS(state->words[0], 15, 16);
1456  switch (sub_subopcode) {
1457  case 0:
1458  instrName = "vmulfw";
1459  decodingClass = 42;
1460  usesSimdRegA = usesSimdRegB = usesSimdRegC = 1;
1461  break;
1462 
1463  case 1:
1464  instrName = "vmulfaw";
1465  decodingClass = 42;
1466  usesSimdRegA = usesSimdRegB = usesSimdRegC = 1;
1467  break;
1468 
1469  case 2:
1470  instrName = "vbmulfw";
1471  decodingClass = 42;
1472  usesSimdRegA = usesSimdRegB = 1;
1473  usesSimdRegC = 0;
1474  break;
1475  }
1476  } break;
1477 
1478  case 15: {
1479  short sub_subopcode = BITS(state->words[0], 15, 16);
1480  switch (sub_subopcode) {
1481  case 0:
1482  instrName = "vsummw";
1483  decodingClass = 42;
1484  usesSimdRegA = usesSimdRegB = usesSimdRegC = 1;
1485  break;
1486  case 2:
1487  instrName = "vbrsubw";
1488  decodingClass = 42;
1489  usesSimdRegA = usesSimdRegB = 1;
1490  usesSimdRegC = 0;
1491  break;
1492  }
1493  } break;
1494 
1495  case 23: {
1496  short sub_subopcode = BITS(state->words[0], 15, 16);
1497  switch (sub_subopcode) {
1498  case 0:
1499  instrName = "vmr7w";
1500  decodingClass = 42;
1501  usesSimdRegA = usesSimdRegB = usesSimdRegC = 1;
1502  break;
1503 
1504  case 1:
1505  instrName = "vmr7aw";
1506  decodingClass = 42;
1507  usesSimdRegA = usesSimdRegB = usesSimdRegC = 1;
1508  break;
1509 
1510  case 2:
1511  switch (BITS(state->words[0], 0, 5)) {
1512  case 0:
1513  instrName = "vaddsuw";
1514  decodingClass = 40;
1515  usesSimdRegC = usesSimdRegB = 1;
1516  usesSimdRegA = 0;
1517  break;
1518 
1519  case 1:
1520  instrName = "vabsw";
1521  decodingClass = 40;
1522  usesSimdRegC = usesSimdRegB = 1;
1523  usesSimdRegA = 0;
1524  break;
1525 
1526  case 2:
1527  instrName = "vsignw";
1528  decodingClass = 40;
1529  usesSimdRegC = usesSimdRegB = 1;
1530  usesSimdRegA = 0;
1531  break;
1532 
1533  case 3:
1534  instrName = "vupbw";
1535  decodingClass = 40;
1536  usesSimdRegC = usesSimdRegB = 1;
1537  usesSimdRegA = 0;
1538  break;
1539 
1540  case 4:
1541  instrName = "vexch1";
1542  decodingClass = 40;
1543  usesSimdRegC = usesSimdRegB = 1;
1544  usesSimdRegA = 0;
1545  break;
1546 
1547  case 5:
1548  instrName = "vexch2";
1549  decodingClass = 40;
1550  usesSimdRegC = usesSimdRegB = 1;
1551  usesSimdRegA = 0;
1552  break;
1553 
1554  case 6:
1555  instrName = "vexch4";
1556  decodingClass = 40;
1557  usesSimdRegC = usesSimdRegB = 1;
1558  usesSimdRegA = 0;
1559  break;
1560 
1561  case 7:
1562  instrName = "vupsbw";
1563  decodingClass = 40;
1564  usesSimdRegC = usesSimdRegB = 1;
1565  usesSimdRegA = 0;
1566  break;
1567 
1568  case 8:
1569  instrName = "vdirun";
1570  decodingClass = 40;
1571  usesSimdRegC = usesSimdRegB = usesSimdRegA = 0;
1572  break;
1573 
1574  case 9:
1575  instrName = "vdorun";
1576  decodingClass = 40;
1577  usesSimdRegC = usesSimdRegB = usesSimdRegA = 0;
1578  break;
1579 
1580  case 10:
1581  instrName = "vdiwr";
1582  decodingClass = 40;
1583  usesSimdRegB = 3;
1584  usesSimdRegA = usesSimdRegC = 0;
1585  break;
1586 
1587  case 11:
1588  instrName = "vdowr";
1589  decodingClass = 40;
1590  usesSimdRegB = 3;
1591  usesSimdRegA = usesSimdRegC = 0;
1592  break;
1593 
1594  case 12:
1595  instrName = "vdird";
1596  decodingClass = 40;
1597  usesSimdRegB = 1;
1598  usesSimdRegC = 3;
1599  usesSimdRegA = 0;
1600  break;
1601 
1602  case 13:
1603  instrName = "vdord";
1604  decodingClass = 40;
1605  usesSimdRegB = 1;
1606  usesSimdRegC = 3;
1607  usesSimdRegA = 0;
1608  break;
1609 
1610  case 63: {
1611  switch (BITS(state->words[0], 24, 25)) {
1612  case 0:
1613  instrName = "vrec";
1614  decodingClass = 43;
1615  usesSimdRegC = 0;
1616  usesSimdRegB = usesSimdRegA = 0;
1617  break;
1618 
1619  case 1:
1620  instrName = "vrecrun";
1621  decodingClass = 43;
1622  usesSimdRegC = 0;
1623  usesSimdRegA = usesSimdRegB = 0;
1624  break;
1625 
1626  case 2:
1627  instrName = "vrun";
1628  decodingClass = 43;
1629  usesSimdRegC = 0;
1630  usesSimdRegB = usesSimdRegA = 0;
1631  break;
1632 
1633  case 3:
1634  instrName = "vendrec";
1635  decodingClass = 43;
1636  usesSimdRegC = 0;
1637  usesSimdRegB = usesSimdRegA = 0;
1638  break;
1639  }
1640  } break;
1641  }
1642  break;
1643 
1644  case 3:
1645  switch (BITS(state->words[0], 0, 2)) {
1646  case 1:
1647  instrName = "vabsaw";
1648  decodingClass = 40;
1649  usesSimdRegC = usesSimdRegB = 1;
1650  usesSimdRegA = 0;
1651  break;
1652  case 3:
1653  instrName = "vupbaw";
1654  decodingClass = 40;
1655  usesSimdRegC = usesSimdRegB = 1;
1656  usesSimdRegA = 0;
1657  break;
1658  case 7:
1659  instrName = "vupsbaw";
1660  decodingClass = 40;
1661  usesSimdRegC = usesSimdRegB = 1;
1662  usesSimdRegA = 0;
1663  break;
1664  }
1665  break;
1666  }
1667  } break;
1668 
1669  case 16:
1670  instrName = "vasrw";
1671  decodingClass = 42;
1672  usesSimdRegA = usesSimdRegB = 1;
1673  usesSimdRegC = 2;
1674  break;
1675 
1676  case 48: {
1677  short sub_subopcode = BITS(state->words[0], 15, 16);
1678  switch (sub_subopcode) {
1679  case 0:
1680  instrName = "vasrwi";
1681  decodingClass = 41;
1682  usesSimdRegA = usesSimdRegB = 1;
1683  usesSimdRegC = 0;
1684  break;
1685  case 2:
1686  instrName = "vasrrwi";
1687  decodingClass = 41;
1688  usesSimdRegA = usesSimdRegB = 1;
1689  usesSimdRegC = 0;
1690  break;
1691  }
1692  } break;
1693 
1694  case 59:
1695  instrName = "vasrsrwi";
1696  decodingClass = 41;
1697  usesSimdRegA = usesSimdRegB = 1;
1698  usesSimdRegC = 0;
1699  break;
1700 
1701  case 18: {
1702  short sub_subopcode = BITS(state->words[0], 15, 16);
1703  switch (sub_subopcode) {
1704  case 0:
1705  instrName = "vmaxw";
1706  usesSimdRegC = 1;
1707  break;
1708  case 1:
1709  instrName = "vmaxaw";
1710  usesSimdRegC = 1;
1711  break;
1712  case 2:
1713  instrName = "vbmaxw";
1714  usesSimdRegC = 0;
1715  break;
1716  }
1717  decodingClass = 42;
1718  usesSimdRegA = usesSimdRegB = 1;
1719  break;
1720  }
1721 
1722  case 19: {
1723  short sub_subopcode = BITS(state->words[0], 15, 16);
1724  switch (sub_subopcode) {
1725  case 0:
1726  instrName = "vminw";
1727  usesSimdRegC = 1;
1728  break;
1729  case 1:
1730  instrName = "vminaw";
1731  usesSimdRegC = 0;
1732  break;
1733  case 2:
1734  instrName = "vbminw";
1735  usesSimdRegC = 0;
1736  break;
1737  }
1738  decodingClass = 42;
1739  usesSimdRegA = usesSimdRegB = 1;
1740  break;
1741  }
1742 
1743  case 14: {
1744  short sub_subopcode = BITS(state->words[0], 15, 16);
1745  switch (sub_subopcode) {
1746  case 0:
1747  instrName = "vdifw";
1748  break;
1749  case 1:
1750  instrName = "vdifaw";
1751  break;
1752  case 2:
1753  instrName = "vmrb";
1754  break;
1755  }
1756  decodingClass = 42;
1757  usesSimdRegA = usesSimdRegB = usesSimdRegC = 1;
1758  break;
1759  }
1760 
1761  case 24: {
1762  short sub_subopcode = BITS(state->words[0], 15, 16);
1763  switch (sub_subopcode) {
1764  case 0:
1765  instrName = "vand";
1766  decodingClass = 42;
1767  usesSimdRegA = usesSimdRegB = usesSimdRegC = 1;
1768  break;
1769  case 1:
1770  instrName = "vandaw";
1771  decodingClass = 42;
1772  usesSimdRegA = usesSimdRegB = usesSimdRegC = 1;
1773  break;
1774  }
1775  break;
1776  }
1777 
1778  case 25: {
1779  short sub_subopcode = BITS(state->words[0], 15, 16);
1780  switch (sub_subopcode) {
1781  case 0:
1782  instrName = "vor";
1783  decodingClass = 42;
1784  usesSimdRegA = usesSimdRegB = usesSimdRegC = 1;
1785  break;
1786  }
1787  break;
1788  }
1789 
1790  case 26: {
1791  short sub_subopcode = BITS(state->words[0], 15, 16);
1792  switch (sub_subopcode) {
1793  case 0:
1794  instrName = "vxor";
1795  break;
1796  case 1:
1797  instrName = "vxoraw";
1798  break;
1799  }
1800  decodingClass = 42;
1801  usesSimdRegA = usesSimdRegB = usesSimdRegC = 1;
1802  break;
1803  }
1804 
1805  case 27: {
1806  short sub_subopcode = BITS(state->words[0], 15, 16);
1807  switch (sub_subopcode) {
1808  case 0:
1809  instrName = "vbic";
1810  break;
1811  case 1:
1812  instrName = "vbicaw";
1813  break;
1814  }
1815  decodingClass = 42;
1816  usesSimdRegA = usesSimdRegB = usesSimdRegC = 1;
1817  break;
1818  }
1819 
1820  case 4: {
1821  short sub_subopcode = BITS(state->words[0], 15, 16);
1822  switch (sub_subopcode) {
1823  case 0:
1824  instrName = "vavb";
1825  break;
1826  case 2:
1827  instrName = "vavrb";
1828  break;
1829  }
1830  decodingClass = 42;
1831  usesSimdRegA = usesSimdRegB = usesSimdRegC = 1;
1832  break;
1833  }
1834 
1835  case 28:
1836  instrName = "veqw";
1837  decodingClass = 42;
1838  usesSimdRegA = usesSimdRegB = usesSimdRegC = 1;
1839  break;
1840 
1841  case 29:
1842  instrName = "vnew";
1843  decodingClass = 42;
1844  usesSimdRegA = usesSimdRegB = usesSimdRegC = 1;
1845  break;
1846 
1847  case 30:
1848  instrName = "vlew";
1849  decodingClass = 42;
1850  usesSimdRegA = usesSimdRegB = usesSimdRegC = 1;
1851  break;
1852 
1853  case 31:
1854  instrName = "vltw";
1855  decodingClass = 42;
1856  usesSimdRegA = usesSimdRegB = usesSimdRegC = 1;
1857  break;
1858 
1859  case 49: {
1860  short sub_subopcode = BITS(state->words[0], 15, 16);
1861  switch (sub_subopcode) {
1862  case 0:
1863  instrName = "vasrpwbi";
1864  decodingClass = 41;
1865  usesSimdRegA = usesSimdRegB = 1;
1866  usesSimdRegC = 0;
1867  break;
1868  case 2:
1869  instrName = "vasrrpwbi";
1870  decodingClass = 41;
1871  usesSimdRegA = usesSimdRegB = 1;
1872  usesSimdRegC = 0;
1873  break;
1874  }
1875  break;
1876  }
1877 
1878  case 5: {
1879  short sub_subopcode = BITS(state->words[0], 15, 16);
1880  switch (sub_subopcode) {
1881  case 0:
1882  instrName = "vsr8";
1883  decodingClass = 42;
1884  usesSimdRegA = usesSimdRegB = 1;
1885  usesSimdRegC = 2;
1886  break;
1887 
1888  case 1:
1889  instrName = "vsr8aw";
1890  decodingClass = 42;
1891  usesSimdRegA = usesSimdRegB = 1;
1892  usesSimdRegC = 2;
1893  break;
1894  }
1895  break;
1896  }
1897 
1898  case 37: {
1899  short sub_subopcode = BITS(state->words[0], 15, 16);
1900  switch (sub_subopcode) {
1901  case 0:
1902  instrName = "vsr8i";
1903  decodingClass = 41;
1904  usesSimdRegA = usesSimdRegB = 1;
1905  usesSimdRegC = 0;
1906  break;
1907 
1908  case 1:
1909  instrName = "vsr8awi";
1910  decodingClass = 41;
1911  usesSimdRegA = usesSimdRegB = 1;
1912  usesSimdRegC = 0;
1913  break;
1914  }
1915  break;
1916  }
1917 
1918  case 20:
1919  case 21:
1920  case 22: {
1921  short subopcode2 = BITS(state->words[0], 15, 18);
1922  switch (subopcode2) {
1923  case 0:
1924  instrName = "vmr1w";
1925  break;
1926 
1927  case 2:
1928  instrName = "vmr2w";
1929  break;
1930 
1931  case 4:
1932  instrName = "vmr3w";
1933  break;
1934 
1935  case 6:
1936  instrName = "vmr4w";
1937  break;
1938 
1939  case 8:
1940  instrName = "vmr5w";
1941  break;
1942 
1943  case 10:
1944  instrName = "vmr6w";
1945  break;
1946 
1947  case 1:
1948  instrName = "vmr1aw";
1949  break;
1950 
1951  case 3:
1952  instrName = "vmr2aw";
1953  break;
1954 
1955  case 5:
1956  instrName = "vmr3aw";
1957  break;
1958 
1959  case 7:
1960  instrName = "vmr4aw";
1961  break;
1962 
1963  case 9:
1964  instrName = "vmr5aw";
1965  break;
1966 
1967  case 11:
1968  instrName = "vmr6aw";
1969  break;
1970  }
1971 
1972  decodingClass = 42;
1973  usesSimdRegA = usesSimdRegB = usesSimdRegC = 1;
1974  break;
1975  }
1976 
1977  case 7:
1978  case 6: {
1979  switch (BITS(state->words[0], 16, 19)) {
1980  case 15:
1981  instrName = "vh264ft";
1982  break;
1983  case 14:
1984  instrName = "vh264f";
1985  break;
1986  case 13:
1987  instrName = "vvc1ft";
1988  break;
1989  case 12:
1990  instrName = "vvc1f";
1991  break;
1992  }
1993  decodingClass = 42;
1994  usesSimdRegA = usesSimdRegB = usesSimdRegC = 1;
1995  break;
1996  }
1997 
1998  case 92:
1999  instrName = "vd6tapf";
2000  decodingClass = 39;
2001  usesSimdRegA = usesSimdRegB = 1;
2002  usesSimdRegC = 0;
2003  break;
2004 
2005  case 55:
2006  instrName = "vinti";
2007  decodingClass = 43;
2008  usesSimdRegA = usesSimdRegB = usesSimdRegC = 0;
2009  break;
2010 
2011  default:
2012  instrName = "SIMD";
2013  state->flow = invalid_instr;
2014  break;
2015  }
2016  } else {
2017  instrName = "???_SIMD";
2018  state->flow = invalid_instr;
2019  }
2020  break;
2021 
2022  case op_LD_ADD:
2023  /* Load/Add resister-register */
2024  decodingClass = 15; /* default for Major opcode 12 ... */
2025  switch (BITS(state->words[0], 3, 4)) {
2026  case 0: instrName = "ld_s"; break;
2027  case 1: instrName = "ldb_s"; break;
2028  case 2: instrName = "ldw_s"; break;
2029  case 3: instrName = "add_s"; break;
2030  default:
2031  instrName = "??? (2[3])";
2032  state->flow = invalid_instr;
2033  break;
2034  }
2035  break;
2036 
2037  case op_ADD_SUB_SHIFT:
2038  /* Add/sub/shift immediate */
2039  decodingClass = 16; /* default for Major opcode 13 ... */
2040  switch (BITS(state->words[0], 3, 4)) {
2041  case 0: instrName = "add_s"; break;
2042  case 1: instrName = "sub_s"; break;
2043  case 2: instrName = "asl_s"; break;
2044  case 3: instrName = "asr_s"; break;
2045  default:
2046  instrName = "??? (2[3])";
2047  state->flow = invalid_instr;
2048  break;
2049  }
2050  break;
2051 
2052  case op_ADD_MOV_CMP:
2053  /* One Dest/Source can be any of r0 - r63 */
2054  decodingClass = 17; /* default for Major opcode 14 ... */
2055  switch (BITS(state->words[0], 3, 4)) {
2056  case 0: instrName = "add_s"; break;
2057  case 1:
2058  case 3:
2059  instrName = "mov_s";
2060  decodingClass = 18;
2061  break;
2062  case 2:
2063  instrName = "cmp_s";
2064  decodingClass = 18;
2065  break;
2066  default:
2067  instrName = "??? (2[3])";
2068  state->flow = invalid_instr;
2069  break;
2070  }
2071  break;
2072 
2073  case op_S:
2074  /* ARCompact 16-bit instructions, General ops/ single ops */
2075  decodingClass = 22; /* default for Major opcode 15 ... */
2076  switch (BITS(state->words[0], 0, 4)) {
2077  case 0:
2078  decodingClass = 27;
2079  switch (BITS(state->words[0], 5, 7)) {
2080  case 0:
2081  instrName = "j_s";
2082  // fallthrough
2083  case 2:
2084  if (!instrName) {
2085  instrName = "jl_s";
2086  }
2087  state->isBranch = 1;
2088  state->nullifyMode = BR_exec_when_no_jump;
2089  break;
2090  case 1:
2091  if (!instrName) {
2092  instrName = "j_s.d";
2093  }
2094  // fallthrough
2095  case 3:
2096  if (!instrName) {
2097  instrName = "jl_s.d";
2098  }
2099  state->isBranch = 1;
2100  state->nullifyMode = BR_exec_always;
2101  break;
2102  case 6:
2103  instrName = "sub_s.ne";
2104  decodingClass = 35;
2105  break;
2106  case 7:
2107  decodingClass = 26;
2108  switch (BITS(state->words[0], 8, 10)) {
2109  case 0:
2110  instrName = "nop_s";
2111  break;
2112 
2113  /* Unimplemented instruction reserved in ARC700 */
2114  case 1: instrName = "unimp_s"; break;
2115 
2116  case 4:
2117  instrName = "jeq_s [blink]";
2118  // fallthrough
2119  case 5:
2120  if (!instrName) {
2121  instrName = "jne_s [blink]";
2122  }
2123  // fallthrough
2124  case 6:
2125  if (!instrName) {
2126  instrName = "j_s [blink]";
2127  }
2128  state->isBranch = 1;
2129  state->nullifyMode = BR_exec_when_no_jump;
2130  break;
2131  case 7:
2132  if (!instrName) {
2133  instrName = "j_s.d [blink]";
2134  }
2135  state->isBranch = 1;
2136  state->nullifyMode = BR_exec_always;
2137  break;
2138  default:
2139  instrName = "??? (2[3])";
2140  state->flow = invalid_instr;
2141  break;
2142  }
2143  break;
2144  default:
2145  instrName = "??? (2[3])";
2146  state->flow = invalid_instr;
2147  break;
2148  }
2149  break;
2150  case 2: instrName = "sub_s"; break;
2151  case 4: instrName = "and_s"; break;
2152  case 5: instrName = "or_s"; break;
2153  case 6: instrName = "bic_s"; break;
2154  case 7: instrName = "xor_s"; break;
2155  case 11:
2156  instrName = "tst_s";
2157  decodingClass = 14;
2158  break;
2159  case 12:
2160  instrName = "mul64_s";
2161  mul = 1;
2162  decodingClass = 14;
2163  break;
2164  case 13:
2165  instrName = "sexb_s";
2166  decodingClass = 14;
2167  break;
2168  case 14:
2169  instrName = "sexw_s";
2170  decodingClass = 14;
2171  break;
2172  case 15:
2173  instrName = "extb_s";
2174  decodingClass = 14;
2175  break;
2176  case 16:
2177  instrName = "extw_s";
2178  decodingClass = 14;
2179  break;
2180  case 17:
2181  instrName = "abs_s";
2182  decodingClass = 14;
2183  break;
2184  case 18:
2185  instrName = "not_s";
2186  decodingClass = 14;
2187  break;
2188  case 19:
2189  instrName = "neg_s";
2190  decodingClass = 14;
2191  break;
2192  case 20: instrName = "add1_s"; break;
2193  case 21: instrName = "add2_s"; break;
2194  case 22: instrName = "add3_s"; break;
2195  case 24: instrName = "asl_s"; break;
2196  case 25: instrName = "lsr_s"; break;
2197  case 26: instrName = "asr_s"; break;
2198  case 27:
2199  instrName = "asl_s";
2200  decodingClass = 14;
2201  break;
2202  case 28:
2203  instrName = "asr_s";
2204  decodingClass = 14;
2205  break;
2206  case 29:
2207  instrName = "lsr_s";
2208  decodingClass = 14;
2209  break;
2210  case 30:
2211  instrName = "trap_s";
2212  decodingClass = 33;
2213  break;
2214  case 31:
2215  instrName = "brk_s";
2216  decodingClass = 26;
2217  break;
2218 
2219  default:
2220  instrName = "??? (2[3])";
2221  state->flow = invalid_instr;
2222  break;
2223  }
2224  break;
2225 
2226  case op_LD_S:
2227  /* ARCompact 16-bit Load with offset, Major Opcode 0x10 */
2228  instrName = "ld_s";
2229  decodingClass = 28;
2230  break;
2231 
2232  case op_LDB_S:
2233  /* ARCompact 16-bit Load with offset, Major Opcode 0x11 */
2234  instrName = "ldb_s";
2235  decodingClass = 28;
2236  break;
2237 
2238  case op_LDW_S:
2239  /* ARCompact 16-bit Load with offset, Major Opcode 0x12 */
2240  instrName = "ldw_s";
2241  decodingClass = 28;
2242  break;
2243 
2244  case op_LDWX_S:
2245  /* ARCompact 16-bit Load with offset, Major Opcode 0x13 */
2246  instrName = "ldw_s.x";
2247  decodingClass = 28;
2248  break;
2249 
2250  case op_ST_S:
2251  /* ARCompact 16-bit Store with offset, Major Opcode 0x14 */
2252  instrName = "st_s";
2253  decodingClass = 28;
2254  break;
2255 
2256  case op_STB_S:
2257  /* ARCompact 16-bit Store with offset, Major Opcode 0x15 */
2258  instrName = "stb_s";
2259  decodingClass = 28;
2260  break;
2261 
2262  case op_STW_S:
2263  /* ARCompact 16-bit Store with offset, Major Opcode 0x16 */
2264  instrName = "stw_s";
2265  decodingClass = 28;
2266  break;
2267 
2268  case op_Su5:
2269  /* ARCompact 16-bit involving unsigned 5-bit immediate operand */
2270  decodingClass = 23; /* default for major opcode 0x17 ... */
2271  switch (BITS(state->words[0], 5, 7)) {
2272  case 0: instrName = "asl_s"; break;
2273  case 1: instrName = "lsr_s"; break;
2274  case 2: instrName = "asr_s"; break;
2275  case 3: instrName = "sub_s"; break;
2276  case 4: instrName = "bset_s"; break;
2277  case 5: instrName = "bclr_s"; break;
2278  case 6: instrName = "bmsk_s"; break;
2279  case 7:
2280  instrName = "btst_s";
2281  decodingClass = 21;
2282  break;
2283  }
2284  break;
2285 
2286  case op_SP:
2287  /* ARCompact 16-bit Stack pointer-based instructions */
2288  decodingClass = 19; /* default for Stack pointer-based insns ... */
2289  switch (BITS(state->words[0], 5, 7)) {
2290  case 0: instrName = "ld_s"; break;
2291  case 1: instrName = "ldb_s"; break;
2292  case 2: instrName = "st_s"; break;
2293  case 3: instrName = "stb_s"; break;
2294  case 4: instrName = "add_s"; break;
2295  case 5:
2296  if (!BITS(state->words[0], 8, 8)) {
2297  instrName = "add_s";
2298  } else {
2299  instrName = "sub_s";
2300  }
2301  break;
2302  case 6:
2303  instrName = "pop_s";
2304  decodingClass = 31;
2305  break;
2306  case 7:
2307  instrName = "push_s";
2308  decodingClass = 31;
2309  break;
2310  default:
2311  instrName = "??? (2[3])";
2312  state->flow = invalid_instr;
2313  break;
2314  }
2315  break;
2316 
2317  case op_GP:
2318  /* ARCompact 16-bit Gp-based ld/add (data aligned offset) */
2319  decodingClass = 20; /* default for gp-relative insns ... */
2320  switch (BITS(state->words[0], 9, 10)) {
2321  case 0: instrName = "ld_s"; break;
2322  case 1: instrName = "ldb_s"; break;
2323  case 2: instrName = "ldw_s"; break;
2324  case 3: instrName = "add_s"; break;
2325  }
2326  break;
2327 
2328  case op_Pcl:
2329  /* ARCompact 16-bit Pcl-based ld (32-bit aligned offset) */
2330  instrName = "ld_s";
2331  decodingClass = 29;
2332  break;
2333 
2334  case op_MOV_S:
2335  /* ARCompact 16-bit Move immediate */
2336  instrName = "mov_s";
2337  decodingClass = 30;
2338  break;
2339 
2340  case op_ADD_CMP:
2341  /* ARCompact 16-bit Add/compare immediate */
2342  decodingClass = 21; /* default for major opcode 0x1c ... */
2343  if (BIT(state->words[0], 7)) {
2344  instrName = "cmp_s";
2345  } else {
2346  instrName = "add_s";
2347  }
2348  break;
2349 
2350  case op_BR_S:
2351  /* ARCompact 16-bit Branch conditionally on reg z/nz */
2352  decodingClass = 25; /* Default for BR_S instruction ... */
2353  if (BIT(state->words[0], 7)) {
2354  instrName = "brne_s";
2355  } else {
2356  instrName = "breq_s";
2357  }
2358  state->isBranch = 1;
2359  break;
2360 
2361  case op_B_S:
2362  /* ARCompact 16-bit Branch conditionally */
2363  decodingClass = 24; /* Default for B_S instruction ... */
2364  state->isBranch = 1;
2365  switch (BITS(state->words[0], 9, 10)) {
2366  case 0: instrName = "b_s"; break;
2367  case 1: instrName = "beq_s"; break;
2368  case 2: instrName = "bne_s"; break;
2369  case 3:
2370  switch (BITS(state->words[0], 6, 8)) {
2371  case 0: instrName = "bgt_s"; break;
2372  case 1: instrName = "bge_s"; break;
2373  case 2: instrName = "blt_s"; break;
2374  case 3: instrName = "ble_s"; break;
2375  case 4: instrName = "bhi_s"; break;
2376  case 5: instrName = "bhs_s"; break;
2377  case 6: instrName = "blo_s"; break;
2378  case 7: instrName = "bls_s"; break;
2379  }
2380  break;
2381  }
2382  break;
2383 
2384  case op_BL_S:
2385  /* ARCompact 16-bit Branch and link unconditionally */
2386  decodingClass = 24; /* Default for B_S instruction ... */
2387  instrName = "bl_s";
2388  state->isBranch = 1;
2389  break;
2390 
2391  default:
2392 
2393  instrName = "???";
2394  state->flow = invalid_instr;
2395  break;
2396  }
2397 
2398  /* Maybe we should be checking for extension instructions over here
2399  * instead of all over this crazy switch case. */
2400  if (state->flow == invalid_instr) {
2401  if (!((state->_opcode == op_SIMD) && enable_simd)) {
2402  instrName = instruction_name(state, state->_opcode,
2403  state->words[0],
2404  &flags);
2405  }
2406 
2407  if (state->instructionLen == 2) {
2408  switch (flags) {
2409  case AC_SYNTAX_3OP:
2410  decodingClass = 22;
2411  break;
2412  case AC_SYNTAX_2OP:
2413  decodingClass = 14;
2414  break;
2415  case AC_SYNTAX_1OP:
2416  decodingClass = 36;
2417  break;
2418  case AC_SYNTAX_NOP:
2419  decodingClass = 26;
2420  break;
2421  default:
2422  mwerror(state, "Invalid syntax class\n");
2423  }
2424  } else {
2425  /* Must do the above for this one too */
2426  switch (flags) {
2427  case AC_SYNTAX_3OP:
2428  decodingClass = 0;
2429  break;
2430  case AC_SYNTAX_2OP:
2431  decodingClass = 1;
2432  break;
2433  case AC_SYNTAX_1OP:
2434  decodingClass = 32;
2435  break;
2436  case AC_SYNTAX_NOP:
2437  break;
2438  case AC_SYNTAX_SIMD:
2439  break;
2440  default:
2441  mwerror(state, "Invalid syntax class\n");
2442  }
2443  }
2444 
2445  if (!instrName) {
2446  instrName = "???";
2447  state->flow = invalid_instr;
2448  }
2449  }
2450 
2451  fieldAisReg = fieldBisReg = fieldCisReg = 1; /* assume regs for now */
2452  flag = cond = is_shimm = is_limm = 0;
2453  state->nullifyMode = BR_exec_when_no_jump; /* 0 */
2454  signExtend = addrWriteBack = directMem = 0;
2455  usesAuxReg = 0;
2456 
2457  /* The following module decodes the instruction */
2458  switch (decodingClass) {
2459  case 0:
2460 
2461  /* For ARCtangent 32-bit instructions with 3 operands */
2462 
2463  subopcode = BITS(state->words[0], 22, 23);
2464  switch (subopcode) {
2465  case 0:
2466 
2467  /* Either fieldB or fieldC or both can be a limm value;
2468  * fieldA can be 0;
2469  */
2470 
2471  CHECK_FIELD_C();
2472  if (!is_limm) {
2473  /* If fieldC is not a limm, then fieldB may be a limm value */
2474  CHECK_FIELD_B();
2475  } else {
2476  FIELD_B();
2477  if (!fieldBisReg) {
2478  fieldB = fieldC;
2479  }
2480  }
2481  CHECK_FIELD_A();
2482  CHECK_FLAG();
2483  break;
2484 
2485  case 1:
2486 
2487  /* fieldB may ba a limm value
2488  * fieldC is a shimm (unsigned 6-bit immediate)
2489  * fieldA can be 0
2490  */
2491 
2492  CHECK_FIELD_B();
2493  FIELD_C();
2494  fieldCisReg = 0;
2495  /* Say ea is not present, so only one of us will do the
2496  name lookup. */
2497  state->_offset += fieldB, state->_ea_present = 0;
2498  CHECK_FIELD_A();
2499  CHECK_FLAG();
2500  break;
2501 
2502  case 2:
2503 
2504  /* fieldB may ba a limm value
2505  * fieldC is a shimm (signed 12-bit immediate)
2506  * fieldA can be 0
2507  */
2508 
2509  fieldCisReg = 0;
2510  fieldC = FIELDS(state->words[0]);
2511  CHECK_FIELD_B();
2512  /* Say ea is not present, so only one of us will do the
2513  name lookup. */
2514  state->_offset += fieldB, state->_ea_present = 0;
2515  if (is_limm) {
2516  fieldAisReg = fieldA = 0;
2517  } else {
2518  fieldA = fieldB;
2519  }
2520  CHECK_FLAG();
2521  break;
2522 
2523  case 3:
2524 
2525  /* fieldB may ba a limm value
2526  * fieldC may be a limm or a shimm (unsigned 6-bit immediate)
2527  * fieldA can be 0
2528  * Conditional instructions
2529  */
2530 
2531  CHECK_FIELD_B();
2532  /* fieldC is a shimm (unsigned 6-bit immediate) */
2533  if (is_limm) {
2534  fieldAisReg = fieldA = 0;
2535  FIELD_C();
2536  if (BIT(state->words[0], 5)) {
2537  fieldCisReg = 0;
2538  } else if (fieldC == 62) {
2539  fieldCisReg = 0;
2540  fieldC = fieldB;
2541  }
2542  } else {
2543  fieldA = fieldB;
2544  if (BIT(state->words[0], 5)) {
2545  FIELD_C();
2546  fieldCisReg = 0;
2547  } else {
2548  CHECK_FIELD_C();
2549  }
2550  }
2551  CHECK_FLAG_COND();
2552  break;
2553  }
2554 
2555  write_instr_name();
2556  WRITE_FORMAT_x(A);
2557  WRITE_FORMAT_COMMA_x(B);
2558  WRITE_FORMAT_COMMA_x(C);
2559  WRITE_NOP_COMMENT();
2560  my_sprintf(state, state->operandBuffer, formatString, fieldA, fieldB, fieldC);
2561  break;
2562 
2563  case 1:
2564 
2565  /* For ARCtangent 32-bit instructions with 2 operands */
2566 
2567  /* field C is either a register or limm (different!) */
2568  CHECK_FIELD_C();
2569  FIELD_B();
2570  CHECK_FLAG();
2571 
2572  if (BITS(state->words[0], 22, 23) == 1) {
2573  fieldCisReg = 0;
2574  }
2575  if (fieldCisReg) {
2576  state->ea_reg1 = fieldC;
2577  /* field C is either a shimm (same as fieldC) or limm (different!) */
2578  /* Say ea is not present, so only one of us will do the name lookup. */
2579  } else {
2580  state->_offset += fieldB, state->_ea_present = 0;
2581  }
2582 
2583  write_instr_name();
2584  WRITE_FORMAT_x(B);
2585  WRITE_FORMAT_COMMA_x(C);
2586  WRITE_NOP_COMMENT();
2587  my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC);
2588  break;
2589 
2590  case 2:
2591 
2592  /* For BTST, CMP, MUL64, MULU64 instruction */
2593 
2594  /* field C is either a register or limm (different!) */
2595  subopcode = BITS(state->words[0], 22, 23);
2596  if (subopcode == 0 || ((subopcode == 3) && (!BIT(state->words[0], 5)))) {
2597  CHECK_FIELD_C();
2598  if (is_limm) {
2599  FIELD_B();
2600  if (!fieldBisReg) {
2601  fieldB = fieldC;
2602  }
2603  } else {
2604  CHECK_FIELD_B();
2605  }
2606  } else if (subopcode == 1 || ((subopcode == 3) && (BIT(state->words[0], 5)))) {
2607  FIELD_C();
2608  fieldCisReg = 0;
2609  CHECK_FIELD_B();
2610  } else if (subopcode == 2) {
2611  FIELD_B();
2612  fieldC = FIELDS(state->words[0]);
2613  fieldCisReg = 0;
2614  }
2615  if (subopcode == 3)
2616  CHECK_COND();
2617 
2618  if (fieldCisReg) {
2619  state->ea_reg1 = fieldC;
2620  /* field C is either a shimm (same as fieldC) or limm (different!) */
2621  /* Say ea is not present, so only one of us will do the name lookup. */
2622  } else {
2623  state->_offset += fieldB, state->_ea_present = 0;
2624  }
2625 
2626  write_instr_name();
2627  if (mul) {
2628  /* For Multiply instructions, the first operand is 0 */
2629  WRITE_FORMAT_x(A);
2630  WRITE_FORMAT_COMMA_x(B);
2631  WRITE_FORMAT_COMMA_x(C);
2632  WRITE_NOP_COMMENT();
2633  my_sprintf(state, state->operandBuffer, formatString, 0, fieldB, fieldC);
2634  } else {
2635  WRITE_FORMAT_x(B);
2636  WRITE_FORMAT_COMMA_x(C);
2637  WRITE_NOP_COMMENT();
2638  my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC);
2639  }
2640  break;
2641 
2642  case 3:
2643  /*
2644  * For FLAG instruction
2645  */
2646  subopcode = BITS(state->words[0], 22, 23);
2647 
2648  if (subopcode == 0 || ((subopcode == 3) && (!BIT(state->words[0], 5)))) {
2649  CHECK_FIELD_C();
2650  } else if (subopcode == 1 || ((subopcode == 3) && (BIT(state->words[0], 5)))) {
2651  FIELD_C();
2652  fieldCisReg = 0;
2653  } else if (subopcode == 2) {
2654  fieldC = FIELDS(state->words[0]);
2655  fieldCisReg = 0;
2656  }
2657  if (subopcode == 3)
2658  CHECK_COND();
2659  flag = 0; /* this is the FLAG instruction -- it's redundant */
2660 
2661  write_instr_name();
2662  WRITE_FORMAT_x(C);
2663  my_sprintf(state, state->operandBuffer, formatString, fieldC);
2664  break;
2665 
2666  case 4:
2667  /*
2668  * For op_JC -- jump to address specified.
2669  * Also covers jump and link--bit 9 of the instr. word
2670  * selects whether linked, thus "is_linked" is set above.
2671  */
2672  subopcode = BITS(state->words[0], 22, 23);
2673  if (subopcode == 0 || ((subopcode == 3) && (!BIT(state->words[0], 5)))) {
2674  CHECK_FIELD_C();
2675  /* ilink registers */
2676  if (fieldC == 29 || fieldC == 31)
2677  CHECK_FLAG();
2678  } else if (subopcode == 1 || ((subopcode == 3) && (BIT(state->words[0], 5)))) {
2679  FIELD_C();
2680  fieldCisReg = 0;
2681  } else if (subopcode == 2) {
2682  fieldC = FIELDS(state->words[0]);
2683  fieldCisReg = 0;
2684  }
2685 
2686  if (subopcode == 3)
2687  CHECK_COND();
2688 
2689  state->nullifyMode = BITS(state->words[0], 16, 16);
2690 
2691  if (!fieldCisReg) {
2692  state->flow = is_linked ? direct_call : direct_jump;
2693  add_target(fieldC);
2694  } else {
2695  state->flow = is_linked ? indirect_call : indirect_jump;
2696  /*
2697  * We should also treat this as indirect call if NOT linked
2698  * but the preceding instruction was a "lr blink,[status]"
2699  * and we have a delay slot with "add blink,blink,2".
2700  * For now we can't detect such.
2701  */
2702  state->register_for_indirect_jump = fieldC;
2703  }
2704 
2705  write_instr_name();
2706  strcat(formatString,
2707  IS_REG(C) ? "[%r]" : "%s"); /* address/label name */
2708 
2709  if (IS_REG(C)) {
2710  my_sprintf(state, state->operandBuffer, formatString, fieldC);
2711  } else {
2712  my_sprintf(state, state->operandBuffer, formatString,
2713  post_address(state, fieldC));
2714  }
2715  break;
2716 
2717  case 5:
2718  /* LD instruction. B and C can be regs, or one or both can be limm. */
2719 
2720  CHECK_FIELD_A();
2721  CHECK_FIELD_B();
2722 
2723  if (FIELDA(state->words[0]) == 62) {
2724  instrName = "prefetch";
2725  }
2726 
2727  if (is_limm) {
2728  FIELD_C();
2729  if (!fieldCisReg) {
2730  fieldC = fieldB;
2731  }
2732  } else {
2733  CHECK_FIELD_C();
2734  }
2735  state->_offset = 0;
2736  state->_ea_present = 1;
2737  if (fieldBisReg) {
2738  state->ea_reg1 = fieldB;
2739  } else {
2740  state->_offset += fieldB;
2741  }
2742  if (fieldCisReg) {
2743  state->ea_reg2 = fieldC;
2744  } else {
2745  state->_offset += fieldC;
2746  }
2747  state->_mem_load = 1;
2748 
2749  directMem = BIT(state->words[0], 15);
2750  /* - We should display the instruction as decoded, not some censored
2751  version of it
2752  - Scaled index is encoded as 'addrWriteBack', even though it isn't
2753  actually doing a write back; it is legitimate with a LIMM. */
2754 #if 0
2755  /* Check if address writeback is allowed before decoding the
2756  address writeback field of a load instruction.*/
2757  if (fieldBisReg && (fieldB != 62))
2758 #endif
2759  addrWriteBack = BITS(state->words[0], 22, 23);
2760  signExtend = BIT(state->words[0], 16);
2761 
2762  write_instr_name();
2763 
2764  /* Check for prefetch or ld 0,...*/
2765  if (IS_REG(A)) {
2766  WRITE_FORMAT_x_COMMA_LB(A);
2767  } else {
2768  strcat(formatString, "%*");
2769  WRITE_FORMAT_LB();
2770  }
2771 
2772  if (fieldBisReg || fieldB != 0) {
2773  WRITE_FORMAT_x(B);
2774  } else {
2775  fieldB = fieldC;
2776  }
2777 
2778  WRITE_FORMAT_COMMA_x_RB(C);
2779  my_sprintf(state, state->operandBuffer, formatString, fieldA, fieldB, fieldC);
2780  break;
2781 
2782  case 6:
2783  /* LD instruction. */
2784  CHECK_FIELD_B();
2785  CHECK_FIELD_A();
2786  /* Support for Prefetch */
2787  /* Fixme :: Check for A700 within this function */
2788 
2789  if (FIELDA(state->words[0]) == 62) {
2790  instrName = "prefetch";
2791  }
2792 
2793  fieldC = FIELDD9(state->words[0]);
2794  fieldCisReg = 0;
2795 
2796  state->_ea_present = 1;
2797  state->_offset = fieldC;
2798  state->_mem_load = 1;
2799  if (fieldBisReg) {
2800  state->ea_reg1 = fieldB;
2801  /* field B is either a shimm (same as fieldC) or limm (different!) */
2802  /* Say ea is not present, so only one of us will do the name lookup. */
2803  } else {
2804  state->_offset += fieldB, state->_ea_present = 0;
2805  }
2806 
2807  directMem = BIT(state->words[0], 11);
2808  /* Check if address writeback is allowed before decoding the
2809  address writeback field of a load instruction.*/
2810  if (fieldBisReg && (fieldB != 62)) {
2811  addrWriteBack = BITS(state->words[0], 9, 10);
2812  }
2813  signExtend = BIT(state->words[0], 6);
2814 
2815  write_instr_name();
2816  if (IS_REG(A)) {
2817  WRITE_FORMAT_x_COMMA_LB(A);
2818  } else {
2819  strcat(formatString, "%*");
2820  WRITE_FORMAT_LB();
2821  }
2822  if (!fieldBisReg) {
2823  fieldB = state->_offset;
2824  WRITE_FORMAT_x_RB(B);
2825  } else {
2826  WRITE_FORMAT_x(B);
2827  WRITE_FORMAT_COMMA_x_RB(C);
2828  }
2829  my_sprintf(state, state->operandBuffer, formatString, fieldA, fieldB, fieldC);
2830  break;
2831 
2832  case 7:
2833  /* ST instruction. */
2834  CHECK_FIELD_B();
2835  CHECK_FIELD_C();
2836  state->source_operand.registerNum = fieldC;
2837  state->sourceType = fieldCisReg ? ARC_REGISTER : ARC_LIMM;
2838  fieldA = FIELDD9(state->words[0]); /* shimm */
2839 
2840  /* [B,A offset] */
2841  state->_ea_present = 1;
2842  state->_offset = fieldA;
2843  if (fieldBisReg) {
2844  state->ea_reg1 = fieldB;
2845  /*
2846  * field B is either a shimm (same as fieldA) or limm (different!)
2847  * Say ea is not present, so only one of us will do the name lookup.
2848  * (for is_limm we do the name translation here).
2849  */
2850  } else {
2851  state->_offset += fieldB, state->_ea_present = 0;
2852  }
2853 
2854  directMem = BIT(state->words[0], 5);
2855  addrWriteBack = BITS(state->words[0], 3, 4);
2856 
2857  write_instr_name();
2858  WRITE_FORMAT_x_COMMA_LB(C);
2859  if (fieldA == 0) {
2860  WRITE_FORMAT_x_RB(B);
2861  } else {
2862  WRITE_FORMAT_x(B);
2863  fieldAisReg = 0;
2864  WRITE_FORMAT_COMMA_x_RB(A);
2865  }
2866  my_sprintf(state, state->operandBuffer, formatString, fieldC, fieldB, fieldA);
2867  break;
2868 
2869  case 8:
2870  /* SR instruction */
2871  CHECK_FIELD_B();
2872  switch (BITS(state->words[0], 22, 23)) {
2873  case 0:
2874  if (is_limm) {
2875  FIELD_C();
2876  if (!fieldCisReg) {
2877  fieldC = fieldB;
2878  }
2879  } else {
2880  CHECK_FIELD_C();
2881  }
2882  break;
2883  case 1:
2884  FIELD_C();
2885  fieldCisReg = 0;
2886  break;
2887  case 2:
2888  fieldC = FIELDS(state->words[0]);
2889  fieldCisReg = 0;
2890  break;
2891  }
2892 
2893  write_instr_name();
2894  WRITE_FORMAT_x_COMMA_LB(B);
2895  /* Try to print B as an aux reg if it is not a core reg. */
2896  usesAuxReg = 1;
2897  WRITE_FORMAT_x(C);
2898  WRITE_FORMAT_RB();
2899  my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC);
2900  break;
2901 
2902  case 9:
2903  /* BBIT0/BBIT1 Instruction */
2904 
2905  CHECK_FIELD_C();
2906  if (is_limm || BIT(state->words[0], 4)) {
2907  fieldCisReg = 0;
2908  FIELD_B();
2909  } else {
2910  CHECK_FIELD_B();
2911  }
2912  fieldAisReg = 0;
2913  fieldA = FIELDS9(state->words[0]);
2914  fieldA += (addr & ~0x3);
2915  CHECK_NULLIFY();
2916 
2917  write_instr_name();
2918 
2919  add_target(fieldA);
2920  state->flow = state->_opcode == op_BLC ? direct_call : direct_jump;
2921  WRITE_FORMAT_x(B);
2922  WRITE_FORMAT_COMMA_x(C);
2923  strcat(formatString, ",%s"); /* address/label name */
2924  WRITE_NOP_COMMENT();
2925  my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC, post_address(state, fieldA));
2926  break;
2927 
2928  case 10:
2929  /* LR instruction */
2930  CHECK_FIELD_B();
2931  switch (BITS(state->words[0], 22, 23)) {
2932  case 0:
2933  CHECK_FIELD_C();
2934  break;
2935  case 1:
2936  FIELD_C();
2937  fieldCisReg = 0;
2938  break;
2939  case 2:
2940  fieldC = FIELDS(state->words[0]);
2941  fieldCisReg = 0;
2942  break;
2943  }
2944 
2945  write_instr_name();
2946  WRITE_FORMAT_x_COMMA_LB(B);
2947  /* Try to print B as an aux reg if it is not a core reg. */
2948  usesAuxReg = 1;
2949  WRITE_FORMAT_x(C);
2950  WRITE_FORMAT_RB();
2951  my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC);
2952  break;
2953 
2954  case 11:
2955  /* lp instruction */
2956 
2957  if (BITS(state->words[0], 22, 23) == 3) {
2958  FIELD_C();
2959  CHECK_COND();
2960  } else {
2961  fieldC = FIELDS(state->words[0]);
2962  }
2963 
2964  fieldC = fieldC << 1;
2965  fieldC += (addr & ~0x3);
2966 
2967  write_instr_name();
2968 
2969  /* This address could be a label we know. Convert it. */
2970  add_target(fieldC);
2971  state->flow = state->_opcode == op_BLC ? direct_call : direct_jump;
2972 
2973  strcat(formatString, "%s"); /* address/label name */
2974  my_sprintf(state, state->operandBuffer, formatString, post_address(state, fieldC));
2975  break;
2976 
2977  case 12:
2978  /* MOV instruction */
2979  FIELD_B();
2980  subopcode = BITS(state->words[0], 22, 23);
2981  if (subopcode == 0 || ((subopcode == 3) && (!BIT(state->words[0], 5)))) {
2982  CHECK_FIELD_C();
2983  } else if (subopcode == 1 || ((subopcode == 3) && (BIT(state->words[0], 5)))) {
2984  FIELD_C();
2985  fieldCisReg = 0;
2986  } else if (subopcode == 2) {
2987  fieldC = FIELDS(state->words[0]);
2988  fieldCisReg = 0;
2989  }
2990  if (subopcode == 3) {
2991  CHECK_FLAG_COND();
2992  } else {
2993  CHECK_FLAG();
2994  }
2995 
2996  write_instr_name();
2997  WRITE_FORMAT_x(B);
2998  WRITE_FORMAT_COMMA_x(C);
2999  WRITE_NOP_COMMENT();
3000  my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC);
3001  break;
3002 
3003  case 13:
3004  /* "B", "BL" instruction */
3005 
3006  fieldA = 0;
3007  if ((state->_opcode == op_BC && (BIT(state->words[0], 16))) ||
3008  (state->_opcode == op_BLC && (BIT(state->words[0], 17)))) {
3009  /* unconditional branch s25 or branch and link d25 */
3010  fieldA = (BITS(state->words[0], 0, 4)) << 10;
3011  }
3012  fieldA |= BITS(state->words[0], 6, 15);
3013 
3014  if (state->_opcode == op_BLC) {
3015  /* Fix for Bug #553. A bl unconditional has only 9 bits in the
3016  * least order bits. */
3017  fieldA = fieldA << 9;
3018  fieldA |= BITS(state->words[0], 18, 26);
3019  fieldA = fieldA << 2;
3020  } else {
3021  fieldA = fieldA << 10;
3022  fieldA |= BITS(state->words[0], 17, 26);
3023  fieldA = fieldA << 1;
3024  }
3025 
3026  if ((state->_opcode == op_BC && (BIT(state->words[0], 16))) ||
3027  (state->_opcode == op_BLC && (BIT(state->words[0], 17)))) {
3028  /* unconditional branch s25 or branch and link d25 */
3029  fieldA = sign_extend(fieldA, 25);
3030  } else {
3031  /* conditional branch s21 or branch and link d21 */
3032  fieldA = sign_extend(fieldA, 21);
3033  }
3034 
3035  fieldA += (addr & ~0x3);
3036 
3037  if (BIT(state->words[0], 16) && state->_opcode == op_BC) {
3038  CHECK_NULLIFY();
3039  } else
3040  /* Checking for bl unconditionally FIX For Bug #553 */
3041  if ((state->_opcode == op_BLC && BITS(state->words[0], 16, 17) == 2) || (state->_opcode == op_BC && (BIT(state->words[0], 16)))) {
3042  CHECK_NULLIFY();
3043  } else {
3044  CHECK_COND_NULLIFY();
3045  }
3046 
3047  write_instr_name();
3048  /* This address could be a label we know. Convert it. */
3049  add_target(fieldA); /* For debugger. */
3050  state->flow = state->_opcode == op_BLC /* BL */
3051  ? direct_call
3052  : direct_jump;
3053  /* indirect calls are achieved by "lr blink,[status]; */
3054  /* lr dest<- func addr; j [dest]" */
3055 
3056  strcat(formatString, "%s"); /* address/label name */
3057  my_sprintf(state, state->operandBuffer, formatString, post_address(state, fieldA));
3058  break;
3059 
3060  case 14:
3061 
3062  /* Extension Instructions */
3063 
3064  FIELD_C_AC();
3065  FIELD_B_AC();
3066 
3067  write_instr_name();
3068  if (mul) {
3069  fieldA = fieldAisReg = 0;
3070  WRITE_FORMAT_x(A);
3071  WRITE_FORMAT_COMMA_x(B);
3072  } else {
3073  WRITE_FORMAT_x(B);
3074  }
3075  WRITE_FORMAT_COMMA_x(C);
3076  WRITE_NOP_COMMENT();
3077  if (mul) {
3078  my_sprintf(state, state->operandBuffer, formatString, 0, fieldB, fieldC);
3079  } else {
3080  my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC);
3081  }
3082  break;
3083 
3084  case 15:
3085 
3086  /* ARCompact 16-bit Load/Add resister-register */
3087 
3088  FIELD_C_AC();
3089  FIELD_B_AC();
3090  FIELD_A_AC();
3091 
3092  write_instr_name();
3093 
3094  if (BITS(state->words[0], 3, 4) != 3) {
3095  WRITE_FORMAT_x_COMMA_LB(A);
3096  WRITE_FORMAT_x(B);
3097  WRITE_FORMAT_COMMA_x_RB(C);
3098  } else {
3099  WRITE_FORMAT_x(A);
3100  WRITE_FORMAT_COMMA_x(B);
3101  WRITE_FORMAT_COMMA_x(C);
3102  }
3103  WRITE_NOP_COMMENT();
3104  my_sprintf(state, state->operandBuffer, formatString, fieldA, fieldB, fieldC);
3105  break;
3106 
3107  case 16:
3108 
3109  /* ARCompact 16-bit Add/Sub/Shift instructions */
3110 
3111  FIELD_C_AC();
3112  FIELD_B_AC();
3113  fieldA = FIELDA_AC(state->words[0]);
3114  fieldAisReg = 0;
3115 
3116  write_instr_name();
3117  WRITE_FORMAT_x(C);
3118  WRITE_FORMAT_COMMA_x(B);
3119  WRITE_FORMAT_COMMA_x(A);
3120  WRITE_NOP_COMMENT();
3121  my_sprintf(state, state->operandBuffer, formatString, fieldC, fieldB, fieldA);
3122  break;
3123 
3124  case 17:
3125 
3126  /* add_s instruction, one Dest/Source can be any of r0 - r63 */
3127 
3128  CHECK_FIELD_H_AC();
3129  FIELD_B_AC();
3130 
3131  write_instr_name();
3132  WRITE_FORMAT_x(B);
3133  WRITE_FORMAT_COMMA_x(B);
3134  WRITE_FORMAT_COMMA_x(C);
3135  WRITE_NOP_COMMENT();
3136  my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldB, fieldC);
3137  break;
3138 
3139  case 18:
3140 
3141  /* mov_s/cmp_s instruction, one Dest/Source can be any of r0 - r63 */
3142 
3143  if ((BITS(state->words[0], 3, 4) == 1) || (BITS(state->words[0], 3, 4) == 2)) {
3144  CHECK_FIELD_H_AC();
3145  } else if (BITS(state->words[0], 3, 4) == 3) {
3146  FIELD_H_AC();
3147  }
3148  FIELD_B_AC();
3149 
3150  write_instr_name();
3151  if (BITS(state->words[0], 3, 4) == 3) {
3152  WRITE_FORMAT_x(C);
3153  WRITE_FORMAT_COMMA_x(B);
3154  WRITE_NOP_COMMENT();
3155  my_sprintf(state, state->operandBuffer, formatString, fieldC, fieldB);
3156  } else {
3157  WRITE_FORMAT_x(B);
3158  WRITE_FORMAT_COMMA_x(C);
3159  WRITE_NOP_COMMENT();
3160  my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC);
3161  }
3162  break;
3163 
3164  case 19:
3165 
3166  /* Stack pointer-based instructions [major opcode 0x18] */
3167 
3168  if (BITS(state->words[0], 5, 7) == 5) {
3169  fieldA = 28;
3170  } else {
3171  FIELD_B_AC();
3172  fieldA = fieldB;
3173  }
3174  fieldB = 28; /* Field B is the stack pointer register */
3175  fieldC = (FIELDU_AC(state->words[0])) << 2;
3176  fieldCisReg = 0;
3177 
3178  write_instr_name();
3179 
3180  switch (BITS(state->words[0], 5, 7)) {
3181  case 0:
3182  case 1:
3183  case 2:
3184  case 3:
3185  WRITE_FORMAT_x_COMMA_LB(A);
3186  WRITE_FORMAT_x(B);
3187  WRITE_FORMAT_COMMA_x_RB(C);
3188  break;
3189  case 4:
3190  case 5:
3191  WRITE_FORMAT_x(A);
3192  WRITE_FORMAT_COMMA_x(B);
3193  WRITE_FORMAT_COMMA_x(C);
3194  break;
3195  }
3196  WRITE_NOP_COMMENT();
3197  my_sprintf(state, state->operandBuffer, formatString, fieldA, fieldB, fieldC);
3198  break;
3199 
3200  case 20:
3201 
3202  /* gp-relative instructions [major opcode 0x19] */
3203 
3204  fieldA = 0;
3205  fieldB = 26; /* Field B is the gp register */
3206  fieldC = FIELDS_AC(state->words[0]);
3207  switch (BITS(state->words[0], 9, 10)) {
3208  case 0:
3209  case 3:
3210  fieldC = fieldC << 2;
3211  break;
3212  case 2:
3213  fieldC = fieldC << 1;
3214  break;
3215  }
3216  fieldCisReg = 0;
3217 
3218  write_instr_name();
3219 
3220  if (BITS(state->words[0], 9, 10) != 3) {
3221  WRITE_FORMAT_x_COMMA_LB(A);
3222  WRITE_FORMAT_x(B);
3223  WRITE_FORMAT_COMMA_x_RB(C);
3224  } else {
3225  WRITE_FORMAT_x(A);
3226  WRITE_FORMAT_COMMA_x(B);
3227  WRITE_FORMAT_COMMA_x(C);
3228  }
3229  WRITE_NOP_COMMENT();
3230  my_sprintf(state, state->operandBuffer, formatString, fieldA, fieldB, fieldC);
3231  break;
3232 
3233  case 21:
3234 
3235  /* add/cmp/btst instructions [major opcode 28] */
3236 
3237  FIELD_B_AC();
3238  if (state->_opcode == op_Su5) {
3239  fieldC = (BITS(state->words[0], 0, 4));
3240  } else {
3241  fieldC = (BITS(state->words[0], 0, 6));
3242  }
3243  fieldCisReg = 0;
3244  write_instr_name();
3245 
3246  if (!BIT(state->words[0], 7)) {
3247  WRITE_FORMAT_x(B);
3248  WRITE_FORMAT_COMMA_x(B);
3249  WRITE_FORMAT_COMMA_x(C);
3250  WRITE_NOP_COMMENT();
3251  my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldB, fieldC);
3252  } else {
3253  WRITE_FORMAT_x(B);
3254  WRITE_FORMAT_COMMA_x(C);
3255  WRITE_NOP_COMMENT();
3256  my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC);
3257  }
3258  break;
3259 
3260  case 22:
3261 
3262  /* ARCompact 16-bit instructions, General ops/ single ops */
3263 
3264  FIELD_C_AC();
3265  FIELD_B_AC();
3266 
3267  write_instr_name();
3268 
3269  WRITE_FORMAT_x(B);
3270  WRITE_FORMAT_COMMA_x(B);
3271  WRITE_FORMAT_COMMA_x(C);
3272  WRITE_NOP_COMMENT();
3273  my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldB, fieldC);
3274  break;
3275 
3276  case 23:
3277 
3278  /* Shift/subtract/bit immediate instructions [major opcode 23] */
3279 
3280  FIELD_B_AC();
3281  fieldC = FIELDU_AC(state->words[0]);
3282  fieldCisReg = 0;
3283  write_instr_name();
3284  WRITE_FORMAT_x(B);
3285  WRITE_FORMAT_COMMA_x(B);
3286  WRITE_FORMAT_COMMA_x(C);
3287  WRITE_NOP_COMMENT();
3288  my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldB, fieldC);
3289  break;
3290 
3291  case 24:
3292 
3293  /* ARCompact 16-bit Branch conditionally */
3294 
3295  if (state->_opcode == op_BL_S) {
3296  fieldA = (BITS(state->words[0], 0, 10)) << 2;
3297  fieldA = sign_extend(fieldA, 13);
3298  } else if (BITS(state->words[0], 9, 10) != 3) {
3299  fieldA = (BITS(state->words[0], 0, 8)) << 1;
3300  fieldA = sign_extend(fieldA, 10);
3301  } else {
3302  fieldA = (BITS(state->words[0], 0, 5)) << 1;
3303  fieldA = sign_extend(fieldA, 7);
3304  }
3305  fieldA += (addr & ~0x3);
3306 
3307  write_instr_name();
3308  /* This address could be a label we know. Convert it. */
3309  add_target(fieldA); /* For debugger. */
3310  state->flow = state->_opcode == op_BL_S /* BL */
3311  ? direct_call
3312  : direct_jump;
3313  /* indirect calls are achieved by "lr blink,[status]; */
3314  /* lr dest<- func addr; j [dest]" */
3315 
3316  strcat(formatString, "%s"); /* address/label name */
3317  my_sprintf(state, state->operandBuffer, formatString, post_address(state, fieldA));
3318  break;
3319 
3320  case 25:
3321 
3322  /* ARCompact 16-bit Branch conditionally on reg z/nz */
3323 
3324  FIELD_B_AC();
3325  fieldC = (BITS(state->words[0], 0, 6)) << 1;
3326  fieldC = sign_extend(fieldC, 8);
3327 
3328  fieldC += (addr & ~0x3);
3329  fieldA = fieldAisReg = 0;
3330 
3331  write_instr_name();
3332  /* This address could be a label we know. Convert it. */
3333  add_target(fieldC); /* For debugger. */
3334  state->flow = direct_jump;
3335 
3336  WRITE_FORMAT_x(B);
3337  WRITE_FORMAT_COMMA_x(A);
3338  strcat(formatString, ",%s"); /* address/label name */
3339  WRITE_NOP_COMMENT();
3340  my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldA, post_address(state, fieldC));
3341  break;
3342 
3343  case 26:
3344 
3345  /* Zero operand Instructions */
3346 
3347  write_instr_name();
3348  state->operandBuffer[0] = '\0';
3349  break;
3350 
3351  case 27:
3352 
3353  /* j_s instruction */
3354 
3355  FIELD_B_AC();
3356  write_instr_name();
3357  strcat(formatString, "[%r]");
3358  my_sprintf(state, state->operandBuffer, formatString, fieldB);
3359  break;
3360 
3361  case 28:
3362 
3363  /* Load/Store with offset */
3364 
3365  FIELD_C_AC();
3366  FIELD_B_AC();
3367  switch (state->_opcode) {
3368  case op_LD_S:
3369  case op_ST_S:
3370  fieldA = (FIELDU_AC(state->words[0])) << 2;
3371  break;
3372  case op_LDB_S:
3373  case op_STB_S:
3374  fieldA = (FIELDU_AC(state->words[0]));
3375  break;
3376  case op_LDW_S:
3377  case op_LDWX_S:
3378  case op_STW_S:
3379  fieldA = (FIELDU_AC(state->words[0])) << 1;
3380  break;
3381  }
3382  fieldAisReg = 0;
3383 
3384  write_instr_name();
3385 
3386  WRITE_FORMAT_x_COMMA_LB(C);
3387  WRITE_FORMAT_x(B);
3388  WRITE_FORMAT_COMMA_x(A);
3389  WRITE_FORMAT_RB();
3390  WRITE_NOP_COMMENT();
3391  my_sprintf(state, state->operandBuffer, formatString, fieldC, fieldB, fieldA);
3392  break;
3393 
3394  case 29:
3395 
3396  /* Load pc-relative */
3397 
3398  FIELD_B_AC();
3399  fieldC = 63;
3400  fieldA = (BITS(state->words[0], 0, 7)) << 2;
3401  fieldAisReg = 0;
3402 
3403  write_instr_name();
3404 
3405  WRITE_FORMAT_x(B);
3406  WRITE_FORMAT_COMMA_x(C);
3407  WRITE_FORMAT_COMMA_x(A);
3408  WRITE_NOP_COMMENT();
3409  my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC, fieldA);
3410  break;
3411 
3412  case 30:
3413 
3414  /* mov immediate */
3415 
3416  FIELD_B_AC();
3417  fieldC = (BITS(state->words[0], 0, 7));
3418  fieldCisReg = 0;
3419 
3420  write_instr_name();
3421 
3422  WRITE_FORMAT_x(B);
3423  WRITE_FORMAT_COMMA_x(C);
3424  WRITE_NOP_COMMENT();
3425  my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC);
3426  break;
3427 
3428  case 31:
3429 
3430  /* push/pop instructions */
3431 
3432  if (BITS(state->words[0], 0, 4) == 1) {
3433  FIELD_B_AC();
3434  } else if (BITS(state->words[0], 0, 4) == 17) {
3435  fieldB = 31;
3436  }
3437 
3438  write_instr_name();
3439 
3440  WRITE_FORMAT_x(B);
3441  WRITE_NOP_COMMENT();
3442  my_sprintf(state, state->operandBuffer, formatString, fieldB);
3443  break;
3444 
3445  case 32:
3446 
3447  /* Single operand instruction */
3448 
3449  if (!BITS(state->words[0], 22, 23)) {
3450  CHECK_FIELD_C();
3451  } else {
3452  FIELD_C();
3453  fieldCisReg = 0;
3454  }
3455 
3456  write_instr_name();
3457 
3458  if (!fieldC) {
3459  state->operandBuffer[0] = '\0';
3460  } else {
3461  WRITE_FORMAT_x(C);
3462  WRITE_NOP_COMMENT();
3463  my_sprintf(state, state->operandBuffer, formatString, fieldC);
3464  }
3465  break;
3466 
3467  case 33:
3468  /* For trap_s and the class of instructions that have
3469  unsigned 6 bits in the fields B and C in A700 16 bit
3470  instructions */
3471  fieldC = FIELDC_AC(state->words[0]);
3472  fieldB = FIELDB_AC(state->words[0]);
3473  write_instr_name();
3474  strcat(formatString, "%d");
3475  my_sprintf(state, state->operandBuffer, formatString, ((fieldB << 3) | fieldC));
3476  break;
3477 
3478  case 34:
3479  /* For ex.di and its class of instructions within op_major_4
3480  This class is different from the normal set of instructions
3481  in op_major_4 because this uses bit 15 as .di and the second
3482  operand is actually a memory operand.
3483  This is of the class
3484  <op>.<di> b,[c] and <op>.<di> b,[limm]
3485  */
3486 
3487  /* field C is either a register or limm (different!) */
3488 
3489  CHECK_FIELD_C();
3490  FIELD_B();
3491  directMem = BIT(state->words[0], 15);
3492 
3493  if (BITS(state->words[0], 22, 23) == 1) {
3494  fieldCisReg = 0;
3495  }
3496  if (fieldCisReg) {
3497  state->ea_reg1 = fieldC;
3498  }
3499 
3500  write_instr_name();
3501  WRITE_FORMAT_x_COMMA_LB(B);
3502 
3503  WRITE_FORMAT_x_RB(C);
3504 
3505  WRITE_NOP_COMMENT();
3506  my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC);
3507  break;
3508 
3509  case 35:
3510 
3511  /* sub_s.ne instruction */
3512 
3513  FIELD_B_AC();
3514  write_instr_name();
3515  strcat(formatString, "%r,%r,%r");
3516  my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldB, fieldB);
3517  break;
3518 
3519  case 36:
3520 
3521  FIELD_B_AC();
3522 
3523  write_instr_name();
3524 
3525  WRITE_FORMAT_x(B);
3526  WRITE_NOP_COMMENT();
3527  my_sprintf(state, state->operandBuffer, formatString, fieldB);
3528 
3529  break;
3530 
3531  /* START ARC LOCAL */
3532  case 44:
3533  /* rtsc instruction */
3534  /* The source operand has no use. */
3535  fieldB = fieldBisReg = 0;
3536 
3537  write_instr_name();
3538  WRITE_FORMAT_x(A);
3539  WRITE_FORMAT_COMMA_x(B);
3540  WRITE_NOP_COMMENT();
3541  my_sprintf(state, state->operandBuffer, formatString, fieldA,
3542  fieldB);
3543  break;
3544  /* END ARC LOCAL */
3545 
3546  /*******SIMD instructions decoding follows*************/
3547  case 37:
3548  case 39:
3549  case 41:
3550  /*fieldA is vr register
3551  fieldB is I register
3552  fieldC is a constant
3553  %*,[%(,%<]
3554  or
3555  %*,%(,%<
3556  or
3557  %*,%(,%u
3558  */
3559 
3560  CHECK_FIELD_A();
3561 
3562  CHECK_FIELD_B();
3563  if (decodingClass == 41) {
3564  FIELD_C();
3565  } else {
3566  FIELD_U8();
3567 
3568  if (simd_scale_u8 > 0) {
3569  fieldC = fieldC << simd_scale_u8;
3570  }
3571  }
3572 
3573  fieldCisReg = 0;
3574 
3575  write_instr_name();
3576  (decodingClass == 37 ? WRITE_FORMAT_x_COMMA_LB(A) : WRITE_FORMAT_x_COMMA(A));
3577  WRITE_FORMAT_x_COMMA(B);
3578  (decodingClass == 37 ? WRITE_FORMAT_x_RB(C) : WRITE_FORMAT_x(C));
3579  WRITE_NOP_COMMENT();
3580  my_sprintf(state, state->operandBuffer, formatString, fieldA, fieldB, fieldC);
3581 
3582  break;
3583  case 38:
3584  /* fieldA is a vr register
3585  fieldB is a ARC700 basecase register.
3586  %*,[%b]
3587  */
3588  CHECK_FIELD_A();
3589  CHECK_FIELD_B();
3590 
3591  write_instr_name();
3592  WRITE_FORMAT_x_COMMA_LB(A);
3593  WRITE_FORMAT_x_RB(B);
3594  WRITE_NOP_COMMENT();
3595  my_sprintf(state, state->operandBuffer, formatString, fieldA, fieldB);
3596 
3597  break;
3598  case 40:
3599  /* fieldB & fieldC are vr registers
3600  %(,%)
3601  or
3602  %B,%C
3603  or
3604  %(,%C
3605  */
3606  CHECK_FIELD_B();
3607  CHECK_FIELD_C();
3608 
3609  write_instr_name();
3610  WRITE_FORMAT_x(B);
3611  WRITE_FORMAT_COMMA_x(C);
3612  my_sprintf(state, state->operandBuffer, formatString, fieldB, fieldC);
3613  break;
3614 
3615  case 42:
3616  /* fieldA, fieldB, fieldC are all vr registers
3617  %*, %(, %) */
3618  CHECK_FIELD_A();
3619  CHECK_FIELD_B();
3620  FIELD_C();
3621 
3622  write_instr_name();
3623  WRITE_FORMAT_x(A);
3624  WRITE_FORMAT_COMMA_x(B);
3625  WRITE_FORMAT_COMMA_x(C);
3626  my_sprintf(state, state->operandBuffer, formatString, fieldA, fieldB, fieldC);
3627  break;
3628 
3629  case 43:
3630  /* Only fieldC is a register
3631  %C*/
3632  CHECK_FIELD_C();
3633 
3634  if (BITS(state->words[0], 17, 23) == 55) {
3635  fieldCisReg = 0;
3636  }
3637 
3638  write_instr_name();
3639  WRITE_FORMAT_x(C);
3640  my_sprintf(state, state->operandBuffer, formatString, fieldC);
3641  break;
3642 
3643  /***************SIMD decoding ends*********************/
3644  default:
3645  mwerror(state, "Bad decoding class in ARC disassembler");
3646  break;
3647  }
3648 
3649  state->_cond = cond;
3650  return state->instructionLen = offset;
3651 }
3652 
3653 /*
3654  * _coreRegName - Returns the name the user specified core extension
3655  * register.
3656  */
3657 static const char *
3658 _coreRegName(
3659  void *_this ATTRIBUTE_UNUSED, /* C++ this pointer */
3660  int v /* Register value */
3661 ) {
3662  return arcExtMap_coreRegName(v);
3663 }
3664 
3665 /*
3666  * _auxRegName - Returns the name the user specified AUX extension
3667  * register.
3668  */
3669 static const char *
3670 _auxRegName(void *_this ATTRIBUTE_UNUSED, /* C++ this pointer */
3671  int v /* Register value */
3672 ) {
3673  return arcExtMap_auxRegName(v);
3674 }
3675 
3676 /*
3677  * _condCodeName - Returns the name the user specified condition code
3678  * name.
3679  */
3680 static const char *
3681 _condCodeName(
3682  void *_this ATTRIBUTE_UNUSED, /* C++ this pointer */
3683  int v /* Register value */
3684 ) {
3685  return arcExtMap_condCodeName(v);
3686 }
3687 
3688 /*
3689  * _instName - Returns the name the user specified extension instruction.
3690  */
3691 static const char *
3692 _instName(
3693  void *_this ATTRIBUTE_UNUSED, /* C++ this pointer */
3694  int op1, /* major opcode value */
3695  int op2, /* minor opcode value */
3696  int *flags /* instruction flags */
3697 ) {
3698  return arcExtMap_instName(op1, op2, flags);
3699 }
3700 
3701 static void
3702 parse_disassembler_options(char *options) {
3703  const char *p;
3704  for (p = options; p != NULL;) {
3705  if (CONST_STRNEQ(p, "simd")) {
3706  enable_simd = 1;
3707  }
3708  if (CONST_STRNEQ(p, "insn-stream")) {
3709  enable_insn_stream = 1;
3710  }
3711 
3712  p = strchr(p, ',');
3713 
3714  if (p != NULL) {
3715  p++;
3716  }
3717  }
3718 }
3719 
3720 /* ARCompact_decodeInstr - Decode an ARCompact instruction returning the
3721  size of the instruction in bytes or zero if unrecognized. */
3722 int ARCompact_decodeInstr(bfd_vma address, /* Address of this instruction. */
3723  disassemble_info *info) {
3724  int status;
3725  bfd_byte buffer[4];
3726  struct arcDisState s; /* ARC Disassembler state */
3727  void *stream = info->stream; /* output stream */
3728  fprintf_ftype func = info->fprintf_func;
3729  int bytes;
3730  int lowbyte, highbyte;
3731  char buf[256];
3732 
3733  if (info->disassembler_options) {
3734  parse_disassembler_options(info->disassembler_options);
3735 
3736  /* To avoid repeated parsing of these options, we remove them here. */
3737  info->disassembler_options = NULL;
3738  }
3739 
3740  lowbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 1 : 0);
3741  highbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 0 : 1);
3742 
3743  memset(&s, 0, sizeof(struct arcDisState));
3744 
3745  /* read first instruction */
3746  status = (*info->read_memory_func)(address, buffer, 2, info);
3747 
3748  if (status != 0) {
3749  (*info->memory_error_func)(status, address, info);
3750  return -1;
3751  }
3752 
3753  if (((buffer[lowbyte] & 0xf8) > 0x38) && ((buffer[lowbyte] & 0xf8) != 0x48)) {
3754  s.instructionLen = 2;
3755  s.words[0] = (buffer[lowbyte] << 8) | buffer[highbyte];
3756  (*info->read_memory_func)(address + 2, buffer, 4, info);
3757  if (info->endian == BFD_ENDIAN_LITTLE) {
3758  s.words[1] = bfd_getl32(buffer);
3759  } else {
3760  s.words[1] = bfd_getb32(buffer);
3761  }
3762  } else {
3763  s.instructionLen = 4;
3764  status = (*info->read_memory_func)(address + 2, &buffer[2], 2, info);
3765  if (status != 0) {
3766  (*info->memory_error_func)(status, address + 2, info);
3767  return -1;
3768  }
3769  if (info->endian == BFD_ENDIAN_LITTLE) {
3770  s.words[0] = bfd_getl32(buffer);
3771  } else {
3772  s.words[0] = bfd_getb32(buffer);
3773  }
3774 
3775  /* always read second word in case of limm */
3776  /* we ignore the result since last insn may not have a limm */
3777  (*info->read_memory_func)(address + 4, buffer, 4, info);
3778  if (info->endian == BFD_ENDIAN_LITTLE) {
3779  s.words[1] = bfd_getl32(buffer);
3780  } else {
3781  s.words[1] = bfd_getb32(buffer);
3782  }
3783  }
3784 
3785  s._this = &s;
3786  s.coreRegName = _coreRegName;
3787  s.auxRegName = _auxRegName;
3788  s.condCodeName = _condCodeName;
3789  s.instName = _instName;
3790 
3791  /* disassemble */
3792  bytes = dsmOneArcInst(address, (void *)&s, info);
3793 
3794  /* display the disassembled instruction */
3795  {
3796  char *instr = s.instrBuffer;
3797  char *operand = s.operandBuffer;
3798  char *space = strchr(instr, ' ');
3799 
3800  if (enable_insn_stream) {
3801  /* Show instruction stream from MSB to LSB*/
3802 
3803  if (s.instructionLen == 2) {
3804  (*func)(stream, " %04x ", (unsigned int)s.words[0]);
3805  } else {
3806  (*func)(stream, "%08x ", (unsigned int)s.words[0]);
3807  }
3808 
3809  (*func)(stream, " ");
3810  }
3811 
3812  /* if the operand is actually in the instruction buffer */
3813  if ((space != NULL) && (operand[0] == '\0')) {
3814  *space = '\0';
3815  operand = space + 1;
3816  }
3817 
3818  (*func)(stream, "%s ", instr);
3819 
3820  if (__TRANSLATION_REQUIRED(s)) {
3821  bfd_vma addr;
3822  char *tmpBuffer;
3823  int i = 1;
3824 
3825  if (operand[0] != '@') {
3826  /* Branch instruction with 3 operands, Translation is required
3827  only for the third operand. Print the first 2 operands */
3828  strncpy(buf, operand, sizeof(buf));
3829  buf[sizeof(buf) - 1] = '\0';
3830  tmpBuffer = strtok(buf, "@");
3831  (*func)(stream, "%s", tmpBuffer);
3832  i = strlen(tmpBuffer) + 1;
3833  }
3834 
3835  addr = s.addresses[operand[i] - '0'];
3836  (*info->print_address_func)((bfd_vma)addr, info);
3837  //(*func) (stream, "\n");
3838  } else {
3839  (*func)(stream, "%s", operand);
3840  }
3841  }
3842 
3843  /* We print max bytes for instruction */
3844  info->bytes_per_line = 8;
3845 
3846  return bytes; // s.instructionLen;
3847 }
3848 
3849 /*
3850  * This function is the same as decodeInstr except that this function
3851  * returns a struct arcDisState instead of the instruction length.
3852  *
3853  * This struct contains information useful to the debugger.
3854  */
3855 struct arcDisState
3856 arcAnalyzeInstr(
3857  bfd_vma address, /* Address of this instruction */
3858  disassemble_info *info) {
3859  int status;
3860  bfd_byte buffer[4];
3861  struct arcDisState s; /* ARC Disassembler state */
3862  int bytes;
3863  int lowbyte, highbyte;
3864 
3865  lowbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 1 : 0);
3866  highbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 0 : 1);
3867 
3868  memset(&s, 0, sizeof(struct arcDisState));
3869 
3870  /* read first instruction */
3871  status = (*info->read_memory_func)(address, buffer, 2, info);
3872 
3873  if (status != 0) {
3874  (*info->memory_error_func)(status, address, info);
3875  s.instructionLen = -1;
3876  return s;
3877  }
3878 
3879  if (((buffer[lowbyte] & 0xf8) > 0x38) && ((buffer[lowbyte] & 0xf8) != 0x48)) {
3880  s.instructionLen = 2;
3881  s.words[0] = (buffer[lowbyte] << 8) | buffer[highbyte];
3882  (*info->read_memory_func)(address + 2, buffer, 4, info);
3883  if (info->endian == BFD_ENDIAN_LITTLE) {
3884  s.words[1] = bfd_getl32(buffer);
3885  } else {
3886  s.words[1] = bfd_getb32(buffer);
3887  }
3888  } else {
3889  s.instructionLen = 4;
3890  status = (*info->read_memory_func)(address + 2, &buffer[2], 2, info);
3891  if (status != 0) {
3892  (*info->memory_error_func)(status, address + 2, info);
3893  s.instructionLen = -1;
3894  return s;
3895  }
3896  if (info->endian == BFD_ENDIAN_LITTLE) {
3897  s.words[0] = bfd_getl32(buffer);
3898  } else {
3899  s.words[0] = bfd_getb32(buffer);
3900  }
3901 
3902  /* always read second word in case of limm */
3903  /* we ignore the result since last insn may not have a limm */
3904  (*info->read_memory_func)(address + 4, buffer, 4, info);
3905  if (info->endian == BFD_ENDIAN_LITTLE) {
3906  s.words[1] = bfd_getl32(buffer);
3907  } else {
3908  s.words[1] = bfd_getb32(buffer);
3909  }
3910  }
3911 
3912  s._this = &s;
3913  s.coreRegName = _coreRegName;
3914  s.auxRegName = _auxRegName;
3915  s.condCodeName = _condCodeName;
3916  s.instName = _instName;
3917 
3918  /* disassemble */
3919  bytes = dsmOneArcInst(address, (void *)&s, info);
3920  /* We print max bytes for instruction */
3921  info->bytes_per_line = bytes;
3922  return s;
3923 }
3924 
3925 void arc_print_disassembler_options(FILE *stream) {
3926  fprintf(stream, "\n\
3927  ARC-specific disassembler options:\n\
3928  use with the -M switch, with options separated by commas\n\n");
3929 
3930  fprintf(stream, " insn-stream Show the instruction byte stream from most\n");
3931  fprintf(stream, " significant byte to least significant byte (excluding LIMM).\n");
3932  fprintf(stream, " This option is useful for viewing the actual encoding of instructions.\n");
3933 
3934  fprintf(stream, " simd Enable SIMD instructions disassembly.\n\n");
3935 }
i
lzma_index ** i
Definition: index.h:629
ext
static const char ext[]
Definition: apprentice.c:1981
core_reg_name
static const char * core_reg_name(struct arcDisState *state, int val)
Definition: arc-dis.c:157
no_reg
@ no_reg
Definition: arc-dis.h:55
ARC_UNDEFINED
@ ARC_UNDEFINED
Definition: arc-dis.h:36
ARC_LIMM
@ ARC_LIMM
Definition: arc-dis.h:37
ARC_REGISTER
@ ARC_REGISTER
Definition: arc-dis.h:39
__TRANSLATION_REQUIRED
#define __TRANSLATION_REQUIRED(state)
Definition: arc-dis.h:110
invalid_instr
@ invalid_instr
Definition: arc-dis.h:52
indirect_jump
@ indirect_jump
Definition: arc-dis.h:50
direct_jump
@ direct_jump
Definition: arc-dis.h:48
indirect_call
@ indirect_call
Definition: arc-dis.h:51
direct_call
@ direct_call
Definition: arc-dis.h:49
noflow
@ noflow
Definition: arc-dis.h:47
BR_exec_when_no_jump
@ BR_exec_when_no_jump
Definition: arc-dis.h:29
BR_exec_always
@ BR_exec_always
Definition: arc-dis.h:30
arcExtMap_auxRegName
const char * arcExtMap_auxRegName(long address)
Definition: arc-ext.c:435
arcExtMap_instName
const char * arcExtMap_instName(int opcode, int insn, int *flags)
Definition: arc-ext.c:300
arcExtMap_condCodeName
const char * arcExtMap_condCodeName(int code)
Definition: arc-ext.c:424
arcExtMap_coreRegName
const char * arcExtMap_coreRegName(int regnum)
Definition: arc-ext.c:402
arc_aux_reg_name
char * arc_aux_reg_name(int regVal)
Definition: arc-opc.c:4965
operand
operand
Definition: arc-opc.c:39
AC_SYNTAX_2OP
#define AC_SYNTAX_2OP
Definition: arc.h:96
A
#define A(x)
Definition: arc.h:165
AC_SYNTAX_3OP
#define AC_SYNTAX_3OP
Definition: arc.h:95
ARC_MACH_ARC7
#define ARC_MACH_ARC7
Definition: arc.h:44
AC_SYNTAX_1OP
#define AC_SYNTAX_1OP
Definition: arc.h:97
E_ARC_MACH_A4
#define E_ARC_MACH_A4
Definition: arc.h:47
B
#define B(x)
Definition: arc.h:166
AC_SYNTAX_SIMD
#define AC_SYNTAX_SIMD
Definition: arc.h:99
C
#define C(x)
Definition: arc.h:167
AC_SYNTAX_NOP
#define AC_SYNTAX_NOP
Definition: arc.h:98
CHECK_FIELD_A
#define CHECK_FIELD_A()
dsmOneArcInst
static int dsmOneArcInst(bfd_vma addr, struct arcDisState *state, disassemble_info *info)
Definition: arcompact-dis.c:685
_coreRegName
static const char * _coreRegName(void *_this ATTRIBUTE_UNUSED, int v)
Definition: arcompact-dis.c:3658
FIELD_U8
#define FIELD_U8()
IS_REG
#define IS_REG(x)
OPCODE
#define OPCODE(word)
sign_extend
static int sign_extend(int value, int bits)
Definition: arcompact-dis.c:666
tm_print_insn_info
disassemble_info tm_print_insn_info
WRITE_FORMAT_COMMA_x
#define WRITE_FORMAT_COMMA_x(x)
FIELD_A_AC
#define FIELD_A_AC()
cond_code_name
static const char * cond_code_name(struct arcDisState *state, int val)
Definition: arcompact-dis.c:302
inc_bp
#define inc_bp()
CHECK_FIELD_B
#define CHECK_FIELD_B()
FIELDS9
#define FIELDS9(word)
write_instr_name
#define write_instr_name()
Definition: arcompact-dis.c:591
CHECK_FLAG_COND
#define CHECK_FLAG_COND()
FIELD_C_AC
#define FIELD_C_AC()
arcAnalyzeInstr
struct arcDisState arcAnalyzeInstr(bfd_vma address, disassemble_info *info)
Definition: arcompact-dis.c:3856
FIELD_B_AC
#define FIELD_B_AC()
FIELDC_AC
#define FIELDC_AC(word)
REG2NAME
#define REG2NAME(num, name)
FIELDS
#define FIELDS(word)
FIELDA_AC
#define FIELDA_AC(word)
arc_print_disassembler_options
void arc_print_disassembler_options(FILE *stream)
Definition: arcompact-dis.c:3925
WRITE_FORMAT_LB
#define WRITE_FORMAT_LB()
BITS
#define BITS(word, s, e)
FIELD_H_AC
#define FIELD_H_AC()
condName
static const char * condName[]
Definition: arcompact-dis.c:532
WRITE_FORMAT_x
#define WRITE_FORMAT_x(x)
CHECK_COND_NULLIFY
#define CHECK_COND_NULLIFY()
WRITE_FORMAT_COMMA_x_RB
#define WRITE_FORMAT_COMMA_x_RB(x)
WRITE_FORMAT_RB
#define WRITE_FORMAT_RB()
add_target
#define add_target(x)
_instName
static const char * _instName(void *_this ATTRIBUTE_UNUSED, int op1, int op2, int *flags)
Definition: arcompact-dis.c:3692
OPCODE_AC
#define OPCODE_AC(word)
FIELDD9
#define FIELDD9(word)
CHECK_COND
#define CHECK_COND()
op_B_S
@ op_B_S
Definition: arcompact-dis.c:626
op_ST_S
@ op_ST_S
Definition: arcompact-dis.c:616
op_SP
@ op_SP
Definition: arcompact-dis.c:620
op_MAJOR_4
@ op_MAJOR_4
Definition: arcompact-dis.c:602
op_LDWX_S
@ op_LDWX_S
Definition: arcompact-dis.c:615
op_GP
@ op_GP
Definition: arcompact-dis.c:621
op_ADD_SUB_SHIFT
@ op_ADD_SUB_SHIFT
Definition: arcompact-dis.c:608
op_LD_ADD
@ op_LD_ADD
Definition: arcompact-dis.c:607
op_LDW_S
@ op_LDW_S
Definition: arcompact-dis.c:614
op_LDB_S
@ op_LDB_S
Definition: arcompact-dis.c:613
op_Pcl
@ op_Pcl
Definition: arcompact-dis.c:622
op_S
@ op_S
Definition: arcompact-dis.c:611
op_STW_S
@ op_STW_S
Definition: arcompact-dis.c:618
op_LD
@ op_LD
Definition: arcompact-dis.c:600
op_BR_S
@ op_BR_S
Definition: arcompact-dis.c:625
op_Su5
@ op_Su5
Definition: arcompact-dis.c:619
op_LD_S
@ op_LD_S
Definition: arcompact-dis.c:612
op_SIMD
@ op_SIMD
Definition: arcompact-dis.c:606
op_BLC
@ op_BLC
Definition: arcompact-dis.c:599
op_MAJOR_6
@ op_MAJOR_6
Definition: arcompact-dis.c:605
op_MOV_S
@ op_MOV_S
Definition: arcompact-dis.c:623
op_ADD_MOV_CMP
@ op_ADD_MOV_CMP
Definition: arcompact-dis.c:610
op_BC
@ op_BC
Definition: arcompact-dis.c:598
op_STB_S
@ op_STB_S
Definition: arcompact-dis.c:617
op_ADD_CMP
@ op_ADD_CMP
Definition: arcompact-dis.c:624
op_MAJOR_5
@ op_MAJOR_5
Definition: arcompact-dis.c:604
op_ST
@ op_ST
Definition: arcompact-dis.c:601
op_BL_S
@ op_BL_S
Definition: arcompact-dis.c:627
BIT
#define BIT(word, n)
_NELEM
#define _NELEM(ary)
FIELD_B
#define FIELD_B()
CHECK_FLAG
#define CHECK_FLAG()
FIELDB_AC
#define FIELDB_AC(word)
mwerror
static void mwerror(struct arcDisState *state, const char *msg)
Definition: arcompact-dis.c:318
_auxRegName
static const char * _auxRegName(void *_this ATTRIBUTE_UNUSED, int v)
Definition: arcompact-dis.c:3670
WRITE_FORMAT_x_COMMA_LB
#define WRITE_FORMAT_x_COMMA_LB(x)
NEXT_WORD
#define NEXT_WORD(x)
my_sprintf
static void my_sprintf(struct arcDisState *state, char *buf, const char *format,...)
Definition: arcompact-dis.c:341
FIELDA
#define FIELDA(word)
WRITE_NOP_COMMENT
#define WRITE_NOP_COMMENT()
post_address
static const char * post_address(struct arcDisState *state, int addr)
Definition: arcompact-dis.c:325
ARCompact_decodeInstr
int ARCompact_decodeInstr(bfd_vma address, disassemble_info *info)
Definition: arcompact-dis.c:3722
instruction_name
static const char * instruction_name(struct arcDisState *state, int op1, int op2, int *flags)
Definition: arcompact-dis.c:310
bfd_getm32_ac
static bfd_vma bfd_getm32_ac(unsigned int)
Definition: arcompact-dis.c:37
WRITE_FORMAT_x_COMMA
#define WRITE_FORMAT_x_COMMA(x)
FIELDU_AC
#define FIELDU_AC(word)
NEXT_WORD_AC
#define NEXT_WORD_AC(x)
bfd_getm32
static bfd_vma bfd_getm32(unsigned int)
Definition: arcompact-dis.c:637
FIELD_C
#define FIELD_C()
aux_reg_name
static const char * aux_reg_name(struct arcDisState *state, int val)
Definition: arcompact-dis.c:294
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