Rizin
unix-like reverse engineering framework and cli tools
Classes | Macros | Typedefs | Enumerations | Functions
disas-asm.h File Reference
#include <stdio.h>
#include <string.h>
#include "mybfd.h"

Go to the source code of this file.

Classes

struct  disassemble_info
 
struct  disasm_options_t
 

Macros

#define bfd_zalloc   calloc
 
#define bfd_malloc   malloc
 
#define xmalloc   malloc
 
#define INSN_HAS_RELOC   (1LL << 31)
 
#define DISASSEMBLE_DATA   (1LL << 30)
 
#define USER_SPECIFIED_MACHINE_TYPE   (1LL << 29)
 
#define FOR_EACH_DISASSEMBLER_OPTION(OPT, OPTIONS)
 
#define INIT_DISASSEMBLE_INFO(INFO, STREAM, FPRINTF_FUNC)    init_disassemble_info(&(INFO), (STREAM), (fprintf_ftype)(FPRINTF_FUNC))
 
#define INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC)    init_disassemble_info(&(INFO), (STREAM), (fprintf_ftype)(FPRINTF_FUNC))
 
#define DECLARE_GENERIC_FPRINTF_FUNC()
 
#define DECLARE_GENERIC_PRINT_ADDRESS_FUNC()
 

Typedefs

typedef int(* fprintf_ftype) (void *, const char *,...) ATTRIBUTE_FPTR_PRINTF_2
 
typedef struct disassemble_info disassemble_info
 
typedef int(* disassembler_ftype) (bfd_vma, disassemble_info *)
 

Enumerations

enum  dis_insn_type {
  dis_noninsn , dis_nonbranch , dis_branch , dis_condbranch ,
  dis_jsr , dis_condjsr , dis_dref , dis_dref2
}
 

Functions

int print_insn_aarch64 (bfd_vma, disassemble_info *)
 
int print_insn_alpha (bfd_vma, disassemble_info *)
 
int print_insn_avr (bfd_vma, disassemble_info *)
 
int print_insn_bfin (bfd_vma, disassemble_info *)
 
int print_insn_big_arm (bfd_vma, disassemble_info *)
 
int print_insn_big_mips (bfd_vma, disassemble_info *)
 
int print_insn_big_nios2 (bfd_vma, disassemble_info *)
 
int print_insn_big_powerpc (bfd_vma, disassemble_info *)
 
int print_insn_big_score (bfd_vma, disassemble_info *)
 
int print_insn_cr16 (bfd_vma, disassemble_info *)
 
int print_insn_crx (bfd_vma, disassemble_info *)
 
int print_insn_d10v (bfd_vma, disassemble_info *)
 
int print_insn_d30v (bfd_vma, disassemble_info *)
 
int print_insn_dlx (bfd_vma, disassemble_info *)
 
int print_insn_epiphany (bfd_vma, disassemble_info *)
 
int print_insn_fr30 (bfd_vma, disassemble_info *)
 
int print_insn_frv (bfd_vma, disassemble_info *)
 
int print_insn_ft32 (bfd_vma, disassemble_info *)
 
int print_insn_h8300 (bfd_vma, disassemble_info *)
 
int print_insn_h8300h (bfd_vma, disassemble_info *)
 
int print_insn_h8300s (bfd_vma, disassemble_info *)
 
int print_insn_h8500 (bfd_vma, disassemble_info *)
 
int print_insn_lanai (bfd_vma, disassemble_info *)
 
int print_insn_hppa (bfd_vma, disassemble_info *)
 
int print_insn_i370 (bfd_vma, disassemble_info *)
 
int print_insn_i386 (bfd_vma, disassemble_info *)
 
int print_insn_i386_att (bfd_vma, disassemble_info *)
 
int print_insn_i386_intel (bfd_vma, disassemble_info *)
 
int print_insn_i860 (bfd_vma, disassemble_info *)
 
int print_insn_i960 (bfd_vma, disassemble_info *)
 
int print_insn_ia64 (bfd_vma, disassemble_info *)
 
int print_insn_ip2k (bfd_vma, disassemble_info *)
 
int print_insn_iq2000 (bfd_vma, disassemble_info *)
 
int print_insn_little_arm (bfd_vma, disassemble_info *)
 
int print_insn_little_mips (bfd_vma, disassemble_info *)
 
int print_insn_little_nios2 (bfd_vma, disassemble_info *)
 
int print_insn_little_powerpc (bfd_vma, disassemble_info *)
 
int print_insn_riscv (bfd_vma, disassemble_info *)
 
int print_insn_little_score (bfd_vma, disassemble_info *)
 
int print_insn_lm32 (bfd_vma, disassemble_info *)
 
int print_insn_m32c (bfd_vma, disassemble_info *)
 
int print_insn_m32r (bfd_vma, disassemble_info *)
 
int print_insn_m68hc11 (bfd_vma, disassemble_info *)
 
int print_insn_m68hc12 (bfd_vma, disassemble_info *)
 
int print_insn_m9s12x (bfd_vma, disassemble_info *)
 
int print_insn_m9s12xg (bfd_vma, disassemble_info *)
 
int print_insn_m68k (bfd_vma, disassemble_info *)
 
int print_insn_m88k (bfd_vma, disassemble_info *)
 
int print_insn_mcore (bfd_vma, disassemble_info *)
 
int print_insn_mep (bfd_vma, disassemble_info *)
 
int print_insn_metag (bfd_vma, disassemble_info *)
 
int print_insn_microblaze (bfd_vma, disassemble_info *)
 
int print_insn_mmix (bfd_vma, disassemble_info *)
 
int print_insn_mn10200 (bfd_vma, disassemble_info *)
 
int print_insn_mn10300 (bfd_vma, disassemble_info *)
 
int print_insn_moxie (bfd_vma, disassemble_info *)
 
int print_insn_msp430 (bfd_vma, disassemble_info *)
 
int print_insn_mt (bfd_vma, disassemble_info *)
 
int print_insn_nds32 (bfd_vma, disassemble_info *)
 
int print_insn_ns32k (bfd_vma, disassemble_info *)
 
int print_insn_or1k (bfd_vma, disassemble_info *)
 
int print_insn_pdp11 (bfd_vma, disassemble_info *)
 
int print_insn_pj (bfd_vma, disassemble_info *)
 
int print_insn_pru (bfd_vma, disassemble_info *)
 
int print_insn_rs6000 (bfd_vma, disassemble_info *)
 
int print_insn_s390 (bfd_vma, disassemble_info *)
 
int print_insn_sh (bfd_vma, disassemble_info *)
 
int print_insn_sh64 (bfd_vma, disassemble_info *)
 
int print_insn_sh64x_media (bfd_vma, disassemble_info *)
 
int print_insn_sparc (bfd_vma, disassemble_info *)
 
int print_insn_spu (bfd_vma, disassemble_info *)
 
int print_insn_tic30 (bfd_vma, disassemble_info *)
 
int print_insn_tic4x (bfd_vma, disassemble_info *)
 
int print_insn_tic54x (bfd_vma, disassemble_info *)
 
int print_insn_tic6x (bfd_vma, disassemble_info *)
 
int print_insn_tic80 (bfd_vma, disassemble_info *)
 
int print_insn_tilegx (bfd_vma, disassemble_info *)
 
int print_insn_tilepro (bfd_vma, disassemble_info *)
 
int print_insn_v850 (bfd_vma, disassemble_info *)
 
int print_insn_vax (bfd_vma, disassemble_info *)
 
int print_insn_visium (bfd_vma, disassemble_info *)
 
int print_insn_w65 (bfd_vma, disassemble_info *)
 
int print_insn_xc16x (bfd_vma, disassemble_info *)
 
int print_insn_xgate (bfd_vma, disassemble_info *)
 
int print_insn_xstormy16 (bfd_vma, disassemble_info *)
 
int print_insn_xtensa (bfd_vma, disassemble_info *)
 
int print_insn_z80 (bfd_vma, disassemble_info *)
 
int print_insn_z8001 (bfd_vma, disassemble_info *)
 
int print_insn_z8002 (bfd_vma, disassemble_info *)
 
int print_insn_rx (bfd_vma, disassemble_info *)
 
int print_insn_rl78 (bfd_vma, disassemble_info *)
 
int print_insn_rl78_g10 (bfd_vma, disassemble_info *)
 
int print_insn_rl78_g13 (bfd_vma, disassemble_info *)
 
int print_insn_rl78_g14 (bfd_vma, disassemble_info *)
 
disassembler_ftype arc_get_disassembler (bfd *)
 
disassembler_ftype cris_get_disassembler (bfd *)
 
disassembler_ftype rl78_get_disassembler (bfd *)
 
void print_aarch64_disassembler_options (FILE *)
 
void print_i386_disassembler_options (FILE *)
 
void print_mips_disassembler_options (FILE *)
 
void print_ppc_disassembler_options (FILE *)
 
void print_riscv_disassembler_options (FILE *)
 
void print_arm_disassembler_options (FILE *)
 
void print_arc_disassembler_options (FILE *)
 
void print_s390_disassembler_options (FILE *)
 
bfd_boolean aarch64_symbol_is_valid (asymbol *, struct disassemble_info *)
 
bfd_boolean arm_symbol_is_valid (asymbol *, struct disassemble_info *)
 
void disassemble_init_powerpc (struct disassemble_info *)
 
void disassemble_init_s390 (struct disassemble_info *)
 
const disasm_options_t * disassembler_options_powerpc (void)
 
const disasm_options_t * disassembler_options_arm (void)
 
const disasm_options_t * disassembler_options_s390 (void)
 
disassembler_ftype disassembler (bfd *)
 
void disassemble_init_for_target (struct disassemble_info *dinfo)
 
void disassembler_usage (FILE *)
 
char * remove_whitespace_and_extra_commas (char *)
 
int disassembler_options_cmp (const char *, const char *)
 
static char * next_disassembler_option (char *options)
 
int buffer_read_memory (bfd_vma, bfd_byte *, unsigned int, struct disassemble_info *)
 
void perror_memory (int, bfd_vma, struct disassemble_info *)
 
void generic_print_address (bfd_vma, struct disassemble_info *)
 
int generic_symbol_at_address (bfd_vma, struct disassemble_info *)
 
bfd_boolean generic_symbol_is_valid (asymbol *, struct disassemble_info *)
 
void init_disassemble_info (struct disassemble_info *dinfo, void *stream, fprintf_ftype fprintf_func)
 
int print_insn_tricore (bfd_vma memaddr, struct disassemble_info *info)
 

Macro Definition Documentation

◆ bfd_malloc

#define bfd_malloc   malloc

Definition at line 42 of file disas-asm.h.

◆ bfd_zalloc

#define bfd_zalloc   calloc

Definition at line 41 of file disas-asm.h.

◆ DECLARE_GENERIC_FPRINTF_FUNC

#define DECLARE_GENERIC_FPRINTF_FUNC ( )
Value:
static int generic_fprintf_func(void *stream, const char *format, ...) { \
int ret; \
va_list ap; \
if (!buf_global || !format) { \
return 0; \
} \
va_start(ap, format); \
ret = rz_strbuf_vappendf(buf_global, format, ap); \
va_end(ap); \
return ret; \
}
buf_global
static RzStrBuf * buf_global
Definition: asm_arc.c:21
stream
voidpf stream
Definition: ioapi.h:138
rz_strbuf_vappendf
RZ_API bool RZ_API bool rz_strbuf_vappendf(RzStrBuf *sb, const char *fmt, va_list ap)
Definition: strbuf.c:290

Definition at line 422 of file disas-asm.h.

◆ DECLARE_GENERIC_PRINT_ADDRESS_FUNC

#define DECLARE_GENERIC_PRINT_ADDRESS_FUNC ( )
Value:
static void generic_print_address_func(bfd_vma address, struct disassemble_info *info) { \
if (!buf_global) { \
return; \
} \
rz_strbuf_appendf(buf_global, "0x%08" PFMT64x, (ut64)address); \
}
info
RzBinInfo * info(RzBinFile *bf)
Definition: bin_ne.c:86
bfd_vma
BFD_HOST_U_64_BIT bfd_vma
Definition: mybfd.h:111
PFMT64x
#define PFMT64x
Definition: rz_types.h:393
disassemble_info
Definition: disas-asm.h:68
ut64
ut64(WINAPI *w32_GetEnabledXStateFeatures)()

Definition at line 435 of file disas-asm.h.

◆ DISASSEMBLE_DATA

#define DISASSEMBLE_DATA   (1LL << 30)

Definition at line 120 of file disas-asm.h.

◆ FOR_EACH_DISASSEMBLER_OPTION

#define FOR_EACH_DISASSEMBLER_OPTION (   OPT,
  OPTIONS 
)
Value:
for ((OPT) = (OPTIONS); \
(OPT) != NULL; \
(OPT) = next_disassembler_option(OPT))
NULL
#define NULL
Definition: cris-opc.c:27
next_disassembler_option
static char * next_disassembler_option(char *options)
Definition: disas-asm.h:374
OPT
OPT('m', "magic-file", 1, " LIST use LIST as a colon-separated list of magic\n" " number files\n") OPT('c'
OPTIONS
#define OPTIONS
Definition: zipcmp.c:208

Definition at line 382 of file disas-asm.h.

◆ INIT_DISASSEMBLE_INFO

#define INIT_DISASSEMBLE_INFO (   INFO,
  STREAM,
  FPRINTF_FUNC 
)     init_disassemble_info(&(INFO), (STREAM), (fprintf_ftype)(FPRINTF_FUNC))

Definition at line 417 of file disas-asm.h.

◆ INIT_DISASSEMBLE_INFO_NO_ARCH

#define INIT_DISASSEMBLE_INFO_NO_ARCH (   INFO,
  STREAM,
  FPRINTF_FUNC 
)     init_disassemble_info(&(INFO), (STREAM), (fprintf_ftype)(FPRINTF_FUNC))

Definition at line 419 of file disas-asm.h.

◆ INSN_HAS_RELOC

#define INSN_HAS_RELOC   (1LL << 31)

Definition at line 118 of file disas-asm.h.

◆ USER_SPECIFIED_MACHINE_TYPE

#define USER_SPECIFIED_MACHINE_TYPE   (1LL << 29)

Definition at line 123 of file disas-asm.h.

◆ xmalloc

#define xmalloc   malloc

Definition at line 43 of file disas-asm.h.

Typedef Documentation

◆ disassemble_info

typedef struct disassemble_info disassemble_info

◆ disassembler_ftype

typedef int(* disassembler_ftype) (bfd_vma, disassemble_info *)

Definition at line 238 of file disas-asm.h.

◆ fprintf_ftype

typedef int(* fprintf_ftype) (void *, const char *,...) ATTRIBUTE_FPTR_PRINTF_2

Definition at line 45 of file disas-asm.h.

Enumeration Type Documentation

◆ dis_insn_type

enum dis_insn_type
Enumerator
dis_noninsn 
dis_nonbranch 
dis_branch 
dis_condbranch 
dis_jsr 
dis_condjsr 
dis_dref 
dis_dref2 

Definition at line 47 of file disas-asm.h.

47  {
48  dis_noninsn, /* Not a valid instruction. */
49  dis_nonbranch, /* Not a branch instruction. */
50  dis_branch, /* Unconditional branch. */
51  dis_condbranch, /* Conditional branch. */
52  dis_jsr, /* Jump to subroutine. */
53  dis_condjsr, /* Conditional jump to subroutine. */
54  dis_dref, /* Data reference instruction. */
55  dis_dref2 /* Two data references in instruction. */
56 };
dis_dref2
@ dis_dref2
Definition: disas-asm.h:55
dis_dref
@ dis_dref
Definition: disas-asm.h:54
dis_noninsn
@ dis_noninsn
Definition: disas-asm.h:48
dis_nonbranch
@ dis_nonbranch
Definition: disas-asm.h:49
dis_condbranch
@ dis_condbranch
Definition: disas-asm.h:51
dis_jsr
@ dis_jsr
Definition: disas-asm.h:52
dis_condjsr
@ dis_condjsr
Definition: disas-asm.h:53
dis_branch
@ dis_branch
Definition: disas-asm.h:50

Function Documentation

◆ aarch64_symbol_is_valid()

bfd_boolean aarch64_symbol_is_valid ( asymbol *  ,
struct disassemble_info *   
)

◆ arc_get_disassembler()

disassembler_ftype arc_get_disassembler ( bfd *  )

◆ arm_symbol_is_valid()

bfd_boolean arm_symbol_is_valid ( asymbol *  ,
struct disassemble_info *   
)

◆ buffer_read_memory()

int buffer_read_memory ( bfd_vma  ,
bfd_byte *  ,
unsigned int  ,
struct disassemble_info *   
)

◆ cris_get_disassembler()

disassembler_ftype cris_get_disassembler ( bfd *  abfd)

Definition at line 1635 of file cris-dis.c.

1636 {
1637 #if CR16_SUPPORTS_CPU
1638 const int mode = 0; // V32 by default
1639  /* If there's no bfd in sight, we return what is valid as input in all
1640  contexts if fed back to the assembler: disassembly *with* register
1641  prefix. Unfortunately this will be totally wrong for v32. */
1642 if (!abfd) {
1643  return print_insn_cris_with_register_prefix;
1644 }
1645 
1646 if (bfd_get_symbol_leading_char (abfd) == 0) {
1647  switch (mode) {
1648  case 0: // V32
1649  return print_insn_crisv32_with_register_prefix;
1650  case 1: // V10_V32
1651  return print_insn_crisv10_v32_with_register_prefix;
1652  default:
1653 
1654  /* We default to v10. This may be specifically specified in the
1655  bfd mach, but is also the default setting. */
1656  return print_insn_cris_with_register_prefix;
1657  }
1658  }
1659 
1660 switch (mode) {
1661 case 0: // V32
1662  //if (bfd_get_mach (abfd) == bfd_mach_cris_v32)
1663  return print_insn_crisv32_without_register_prefix;
1664 case 1: // V10_V32
1665  //if (bfd_get_mach (abfd) == bfd_mach_cris_v10_v32)
1666  return print_insn_crisv10_v32_without_register_prefix;
1667 default:
1668  return print_insn_cris_without_register_prefix;
1669 }
1670 #else
1671  return print_insn_crisv32_without_register_prefix;
1672 #endif
1673 }
print_insn_cris_without_register_prefix
int print_insn_cris_without_register_prefix(bfd_vma vma, disassemble_info *info)
Definition: cris-dis.c:1594
print_insn_crisv32_without_register_prefix
int print_insn_crisv32_without_register_prefix(bfd_vma vma, disassemble_info *info)
Definition: cris-dis.c:1606
print_insn_cris_with_register_prefix
int print_insn_cris_with_register_prefix(bfd_vma vma, disassemble_info *info)
Definition: cris-dis.c:1557
print_insn_crisv32_with_register_prefix
int print_insn_crisv32_with_register_prefix(bfd_vma vma, disassemble_info *info)
Definition: cris-dis.c:1569
print_insn_crisv10_v32_with_register_prefix
int print_insn_crisv10_v32_with_register_prefix(bfd_vma vma, disassemble_info *info)
Definition: cris-dis.c:1582
print_insn_crisv10_v32_without_register_prefix
int print_insn_crisv10_v32_without_register_prefix(bfd_vma vma, disassemble_info *info)
Definition: cris-dis.c:1619
mode
const char int mode
Definition: ioapi.h:137
bfd_get_symbol_leading_char
#define bfd_get_symbol_leading_char(abfd)
Definition: mybfd.h:524

References bfd_get_symbol_leading_char, print_insn_cris_with_register_prefix(), print_insn_cris_without_register_prefix(), print_insn_crisv10_v32_with_register_prefix(), print_insn_crisv10_v32_without_register_prefix(), print_insn_crisv32_with_register_prefix(), and print_insn_crisv32_without_register_prefix().

◆ disassemble_init_for_target()

void disassemble_init_for_target ( struct disassemble_info *  dinfo)

◆ disassemble_init_powerpc()

void disassemble_init_powerpc ( struct disassemble_info *  )

◆ disassemble_init_s390()

void disassemble_init_s390 ( struct disassemble_info *  )

◆ disassembler()

disassembler_ftype disassembler ( bfd *  )

◆ disassembler_options_arm()

const disasm_options_t* disassembler_options_arm ( void  )

◆ disassembler_options_cmp()

int disassembler_options_cmp ( const char *  ,
const char *   
)

◆ disassembler_options_powerpc()

const disasm_options_t* disassembler_options_powerpc ( void  )

◆ disassembler_options_s390()

const disasm_options_t* disassembler_options_s390 ( void  )

◆ disassembler_usage()

void disassembler_usage ( FILE *  )

◆ generic_print_address()

void generic_print_address ( bfd_vma  ,
struct disassemble_info *   
)

◆ generic_symbol_at_address()

int generic_symbol_at_address ( bfd_vma  ,
struct disassemble_info *   
)

◆ generic_symbol_is_valid()

bfd_boolean generic_symbol_is_valid ( asymbol *  ,
struct disassemble_info *   
)

◆ init_disassemble_info()

void init_disassemble_info ( struct disassemble_info *  dinfo,
void *  stream,
fprintf_ftype  fprintf_func 
)

◆ next_disassembler_option()

static char* next_disassembler_option ( char *  options)
inlinestatic

Definition at line 374 of file disas-asm.h.

374  {
375  char *opt = strchr(options, ',');
376  if (opt != NULL)
377  opt++;
378  return opt;
379 }
options
static const char struct stat static buf struct stat static buf static vhangup int options
Definition: sflib.h:145

References NULL, and options.

◆ perror_memory()

void perror_memory ( int  ,
bfd_vma  ,
struct disassemble_info *   
)

◆ print_aarch64_disassembler_options()

void print_aarch64_disassembler_options ( FILE *  stream)

Definition at line 3381 of file aarch64-dis.c.

3382 {
3383  fprintf (stream, _("\n\
3384 The following AARCH64 specific disassembler options are supported for use\n\
3385 with the -M switch (multiple options should be separated by commas):\n"));
3386 
3387  fprintf (stream, _("\n\
3388  no-aliases Don't print instruction aliases.\n"));
3389 
3390  fprintf (stream, _("\n\
3391  aliases Do print instruction aliases.\n"));
3392 
3393  fprintf (stream, _("\n\
3394  no-notes Don't print instruction notes.\n"));
3395 
3396  fprintf (stream, _("\n\
3397  notes Do print instruction notes.\n"));
3398 
3399 #ifdef DEBUG_AARCH64
3400  fprintf (stream, _("\n\
3401  debug_dump Temp switch for debug trace.\n"));
3402 #endif /* DEBUG_AARCH64 */
3403 
3404  fprintf (stream, _("\n"));
3405 }
_
#define _(String)
Definition: opintl.h:53

References _.

◆ print_arc_disassembler_options()

void print_arc_disassembler_options ( FILE *  )

◆ print_arm_disassembler_options()

void print_arm_disassembler_options ( FILE *  )

◆ print_i386_disassembler_options()

void print_i386_disassembler_options ( FILE *  )

◆ print_insn_aarch64()

int print_insn_aarch64 ( bfd_vma  pc,
disassemble_info *  info 
)

Definition at line 3248 of file aarch64-dis.c.

3250 {
3251  bfd_byte buffer[INSNLEN];
3252  int status;
3253  void (*printer) (bfd_vma, uint32_t, struct disassemble_info *,
3254  aarch64_operand_error *);
3255  bfd_boolean found = FALSE;
3256  unsigned int size = 4;
3257  unsigned long data;
3258  aarch64_operand_error errors;
3259 
3260  if (info->disassembler_options)
3261  {
3262  set_default_aarch64_dis_options (info);
3263 
3264  parse_aarch64_dis_options (info->disassembler_options);
3265 
3266  /* To avoid repeated parsing of these options, we remove them here. */
3267  info->disassembler_options = NULL;
3268  }
3269 
3270  /* Aarch64 instructions are always little-endian */
3271  info->endian_code = BFD_ENDIAN_LITTLE;
3272 
3273  /* First check the full symtab for a mapping symbol, even if there
3274  are no usable non-mapping symbols for this address. */
3275  if (info->symtab_size != 0
3276  && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
3277  {
3278  enum map_type type = MAP_INSN;
3279  int last_sym = -1;
3280  bfd_vma addr;
3281  int n;
3282 
3283  if (pc <= last_mapping_addr)
3284  last_mapping_sym = -1;
3285 
3286  /* Start scanning at the start of the function, or wherever
3287  we finished last time. */
3288  n = info->symtab_pos + 1;
3289  if (n < last_mapping_sym)
3290  n = last_mapping_sym;
3291 
3292  /* Scan up to the location being disassembled. */
3293  for (; n < info->symtab_size; n++)
3294  {
3295  addr = bfd_asymbol_value (info->symtab[n]);
3296  if (addr > pc)
3297  break;
3298  if (get_sym_code_type (info, n, &type))
3299  {
3300  last_sym = n;
3301  found = TRUE;
3302  }
3303  }
3304 
3305  if (!found)
3306  {
3307  n = info->symtab_pos;
3308  if (n < last_mapping_sym)
3309  n = last_mapping_sym;
3310 
3311  /* No mapping symbol found at this address. Look backwards
3312  for a preceeding one. */
3313  for (; n >= 0; n--)
3314  {
3315  if (get_sym_code_type (info, n, &type))
3316  {
3317  last_sym = n;
3318  break;
3319  }
3320  }
3321  }
3322 
3323  last_mapping_sym = last_sym;
3324  last_type = type;
3325 
3326  /* Look a little bit ahead to see if we should print out
3327  less than four bytes of data. If there's a symbol,
3328  mapping or otherwise, after two bytes then don't
3329  print more. */
3330  if (last_type == MAP_DATA)
3331  {
3332  size = 4 - (pc & 3);
3333  for (n = last_sym + 1; n < info->symtab_size; n++)
3334  {
3335  addr = bfd_asymbol_value (info->symtab[n]);
3336  if (addr > pc)
3337  {
3338  if (addr - pc < size)
3339  size = addr - pc;
3340  break;
3341  }
3342  }
3343  /* If the next symbol is after three bytes, we need to
3344  print only part of the data, so that we can use either
3345  .byte or .short. */
3346  if (size == 3)
3347  size = (pc & 1) ? 1 : 2;
3348  }
3349  }
3350 
3351  if (last_type == MAP_DATA)
3352  {
3353  /* size was set above. */
3354  info->bytes_per_chunk = size;
3355  info->display_endian = info->endian;
3356  printer = print_insn_data;
3357  }
3358  else
3359  {
3360  info->bytes_per_chunk = size = INSNLEN;
3361  info->display_endian = info->endian_code;
3362  printer = print_insn_aarch64_word;
3363  }
3364 
3365  status = (*info->read_memory_func) (pc, buffer, size, info);
3366  if (status != 0)
3367  {
3368  (*info->memory_error_func) (status, pc, info);
3369  return -1;
3370  }
3371 
3372  data = bfd_get_bits (buffer, size * 8,
3373  info->display_endian == BFD_ENDIAN_BIG);
3374 
3375  (*printer) (pc, data, info, &errors);
3376 
3377  return size;
3378 }
parse_aarch64_dis_options
static void parse_aarch64_dis_options(const char *options)
Definition: aarch64-dis.c:100
INSNLEN
#define INSNLEN
Definition: aarch64-dis.c:36
set_default_aarch64_dis_options
static void set_default_aarch64_dis_options(struct disassemble_info *info ATTRIBUTE_UNUSED)
Definition: aarch64-dis.c:55
get_sym_code_type
static int get_sym_code_type(struct disassemble_info *info, int n, enum map_type *map_type)
Definition: aarch64-dis.c:3211
map_type
map_type
Definition: aarch64-dis.c:40
MAP_INSN
@ MAP_INSN
Definition: aarch64-dis.c:41
MAP_DATA
@ MAP_DATA
Definition: aarch64-dis.c:42
print_insn_data
static void print_insn_data(bfd_vma pc ATTRIBUTE_UNUSED, uint32_t word, struct disassemble_info *info, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
Definition: aarch64-dis.c:3186
last_type
static enum map_type last_type
Definition: aarch64-dis.c:45
last_mapping_sym
static int last_mapping_sym
Definition: aarch64-dis.c:46
print_insn_aarch64_word
static void print_insn_aarch64_word(bfd_vma pc, uint32_t word, struct disassemble_info *info, aarch64_operand_error *errors)
Definition: aarch64-dis.c:3105
last_mapping_addr
static bfd_vma last_mapping_addr
Definition: aarch64-dis.c:47
found
RZ_API const KEY_TYPE bool * found
Definition: ht_inc.h:130
size
voidpf void uLong size
Definition: ioapi.h:138
status
static const char struct stat static buf struct stat static buf static vhangup int status
Definition: sflib.h:145
n
int n
Definition: mipsasm.c:19
type
int type
Definition: mipsasm.c:17
bfd_byte
unsigned char bfd_byte
Definition: mybfd.h:176
bfd_asymbol_flavour
#define bfd_asymbol_flavour(x)
Definition: mybfd.h:273
bfd_target_elf_flavour
@ bfd_target_elf_flavour
Definition: mybfd.h:4597
bfd_boolean
int bfd_boolean
Definition: mybfd.h:98
bfd_asymbol_value
#define bfd_asymbol_value(x)
Definition: mybfd.h:269
BFD_ENDIAN_LITTLE
@ BFD_ENDIAN_LITTLE
Definition: mybfd.h:4618
BFD_ENDIAN_BIG
@ BFD_ENDIAN_BIG
Definition: mybfd.h:4617
TRUE
#define TRUE
Definition: mybfd.h:103
FALSE
#define FALSE
Definition: mybfd.h:102
bfd_get_bits
static bfd_uint64_t bfd_get_bits(const void *p, int bits, bfd_boolean big_p)
Definition: mybfd.h:563
uint32_t
unsigned int uint32_t
Definition: sftypes.h:29
aarch64_operand_error
Definition: aarch64.h:1108
buffer
Definition: buffer.h:15
addr
static int addr
Definition: z80asm.c:58

References addr, bfd_asymbol_flavour, bfd_asymbol_value, BFD_ENDIAN_BIG, BFD_ENDIAN_LITTLE, bfd_get_bits(), bfd_target_elf_flavour, FALSE, found, get_sym_code_type(), info(), INSNLEN, last_mapping_addr, last_mapping_sym, last_type, MAP_DATA, MAP_INSN, n, NULL, parse_aarch64_dis_options(), pc, print_insn_aarch64_word(), print_insn_data(), set_default_aarch64_dis_options(), status, TRUE, and type.

◆ print_insn_alpha()

int print_insn_alpha ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_avr()

int print_insn_avr ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_bfin()

int print_insn_bfin ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_big_arm()

int print_insn_big_arm ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_big_mips()

int print_insn_big_mips ( bfd_vma  memaddr,
disassemble_info *  info 
)

Definition at line 2098 of file mips-dis.c.

2099 {
2100  return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
2101 }
_print_insn_mips
static int _print_insn_mips(bfd_vma memaddr, struct disassemble_info *info, enum bfd_endian endianness)
Definition: mips-dis.c:2053

References _print_insn_mips(), BFD_ENDIAN_BIG, and info().

Referenced by disassemble().

◆ print_insn_big_nios2()

int print_insn_big_nios2 ( bfd_vma  address,
disassemble_info *  info 
)

Definition at line 422 of file nios2-dis.c.

423 {
424  return print_insn_nios2 (address, info, BFD_ENDIAN_BIG);
425 }
print_insn_nios2
static int print_insn_nios2(bfd_vma address, disassemble_info *info, enum bfd_endian endianness)
Definition: nios2-dis.c:394

References BFD_ENDIAN_BIG, info(), and print_insn_nios2().

◆ print_insn_big_powerpc()

int print_insn_big_powerpc ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_big_score()

int print_insn_big_score ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_cr16()

int print_insn_cr16 ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_crx()

int print_insn_crx ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_d10v()

int print_insn_d10v ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_d30v()

int print_insn_d30v ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_dlx()

int print_insn_dlx ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_epiphany()

int print_insn_epiphany ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_fr30()

int print_insn_fr30 ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_frv()

int print_insn_frv ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_ft32()

int print_insn_ft32 ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_h8300()

int print_insn_h8300 ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_h8300h()

int print_insn_h8300h ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_h8300s()

int print_insn_h8300s ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_h8500()

int print_insn_h8500 ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_hppa()

int print_insn_hppa ( bfd_vma  memaddr,
disassemble_info *  info 
)

Definition at line 361 of file hppa-dis.c.

362 {
363  bfd_byte buffer[4];
364  unsigned int insn, i;
365 
366  {
367  int status =
368  (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
369  if (status != 0)
370  {
371  (*info->memory_error_func) (status, memaddr, info);
372  return -1;
373  }
374  }
375 
376  insn = bfd_getb32 (buffer);
377 
378  for (i = 0; i < NUMOPCODES; ++i)
379  {
380  const struct pa_opcode *opcode = &pa_opcodes[i];
381 
382  if ((insn & opcode->mask) == opcode->match)
383  {
384  const char *s;
385 #ifndef BFD64
386  if (opcode->arch == pa20w)
387  continue;
388 #endif
389  (*info->fprintf_func) (info->stream, "%s", opcode->name);
390 
391  if (!strchr ("cfCY?-+nHNZFIuv{", opcode->args[0])) {
392  (*info->fprintf_func) (info->stream, " ");
393  }
394  for (s = opcode->args; *s != '\0'; ++s)
395  {
396  switch (*s)
397  {
398  case 'x':
399  fput_reg (GET_FIELD (insn, 11, 15), info);
400  break;
401  case 'a':
402  case 'b':
403  fput_reg (GET_FIELD (insn, 6, 10), info);
404  break;
405  case '^':
406  fput_creg (GET_FIELD (insn, 6, 10), info);
407  break;
408  case 't':
409  fput_reg (GET_FIELD (insn, 27, 31), info);
410  break;
411 
412  /* Handle floating point registers. */
413  case 'f':
414  switch (*++s)
415  {
416  case 't':
417  fput_fp_reg (GET_FIELD (insn, 27, 31), info);
418  break;
419  case 'T':
420  if (GET_FIELD (insn, 25, 25)) {
421  fput_fp_reg_r (GET_FIELD (insn, 27, 31), info);
422  } else {
423  fput_fp_reg (GET_FIELD (insn, 27, 31), info);
424  }
425  break;
426  case 'a':
427  if (GET_FIELD (insn, 25, 25)) {
428  fput_fp_reg_r (GET_FIELD (insn, 6, 10), info);
429  } else {
430  fput_fp_reg (GET_FIELD (insn, 6, 10), info);
431  }
432  break;
433 
434  /* 'fA' will not generate a space before the register
435  name. Normally that is fine. Except that it
436  causes problems with xmpyu which has no FP format
437  completer. */
438  case 'X':
439  fputs_filtered (" ", info);
440  /* FALLTHRU */
441 
442  case 'A':
443  if (GET_FIELD (insn, 24, 24)) {
444  fput_fp_reg_r (GET_FIELD (insn, 6, 10), info);
445  } else {
446  fput_fp_reg (GET_FIELD (insn, 6, 10), info);
447  }
448  break;
449  case 'b':
450  if (GET_FIELD (insn, 25, 25)) {
451  fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
452  } else {
453  fput_fp_reg (GET_FIELD (insn, 11, 15), info);
454  }
455  break;
456  case 'B':
457  if (GET_FIELD (insn, 19, 19)) {
458  fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
459  } else {
460  fput_fp_reg (GET_FIELD (insn, 11, 15), info);
461  }
462  break;
463  case 'C':
464  {
465  int reg = GET_FIELD (insn, 21, 22);
466  reg |= GET_FIELD (insn, 16, 18) << 2;
467  if (GET_FIELD (insn, 23, 23) != 0) {
468  fput_fp_reg_r (reg, info);
469  } else {
470  fput_fp_reg (reg, info);
471  }
472  break;
473  }
474  case 'i':
475  {
476  int reg = GET_FIELD (insn, 6, 10);
477 
478  reg |= (GET_FIELD (insn, 26, 26) << 4);
479  fput_fp_reg (reg, info);
480  break;
481  }
482  case 'j':
483  {
484  int reg = GET_FIELD (insn, 11, 15);
485 
486  reg |= (GET_FIELD (insn, 26, 26) << 4);
487  fput_fp_reg (reg, info);
488  break;
489  }
490  case 'k':
491  {
492  int reg = GET_FIELD (insn, 27, 31);
493 
494  reg |= (GET_FIELD (insn, 26, 26) << 4);
495  fput_fp_reg (reg, info);
496  break;
497  }
498  case 'l':
499  {
500  int reg = GET_FIELD (insn, 21, 25);
501 
502  reg |= (GET_FIELD (insn, 26, 26) << 4);
503  fput_fp_reg (reg, info);
504  break;
505  }
506  case 'm':
507  {
508  int reg = GET_FIELD (insn, 16, 20);
509 
510  reg |= (GET_FIELD (insn, 26, 26) << 4);
511  fput_fp_reg (reg, info);
512  break;
513  }
514 
515  /* 'fe' will not generate a space before the register
516  name. Normally that is fine. Except that it
517  causes problems with fstw fe,y(b) which has no FP
518  format completer. */
519  case 'E':
520  fputs_filtered (" ", info);
521  /* FALLTHRU */
522 
523  case 'e':
524  if (GET_FIELD (insn, 30, 30)) {
525  fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
526  } else {
527  fput_fp_reg (GET_FIELD (insn, 11, 15), info);
528  }
529  break;
530  case 'x':
531  fput_fp_reg (GET_FIELD (insn, 11, 15), info);
532  break;
533  }
534  break;
535 
536  case '5':
537  fput_const (extract_5_load (insn), info);
538  break;
539  case 's':
540  {
541  int space = GET_FIELD (insn, 16, 17);
542  /* Zero means implicit addressing, not use of sr0. */
543  if (space != 0) {
544  (*info->fprintf_func) (info->stream, "sr%d", space);
545  }
546  }
547  break;
548 
549  case 'S':
550  (*info->fprintf_func) (info->stream, "sr%d",
551  extract_3 (insn));
552  break;
553 
554  /* Handle completers. */
555  case 'c':
556  switch (*++s)
557  {
558  case 'x':
559  (*info->fprintf_func)
560  (info->stream, "%s",
561  index_compl_names[GET_COMPL (insn)]);
562  break;
563  case 'X':
564  (*info->fprintf_func)
565  (info->stream, "%s ",
566  index_compl_names[GET_COMPL (insn)]);
567  break;
568  case 'm':
569  (*info->fprintf_func)
570  (info->stream, "%s",
571  short_ldst_compl_names[GET_COMPL (insn)]);
572  break;
573  case 'M':
574  (*info->fprintf_func)
575  (info->stream, "%s ",
576  short_ldst_compl_names[GET_COMPL (insn)]);
577  break;
578  case 'A':
579  (*info->fprintf_func)
580  (info->stream, "%s ",
581  short_bytes_compl_names[GET_COMPL (insn)]);
582  break;
583  case 's':
584  (*info->fprintf_func)
585  (info->stream, "%s",
586  short_bytes_compl_names[GET_COMPL (insn)]);
587  break;
588  case 'c':
589  case 'C':
590  switch (GET_FIELD (insn, 20, 21))
591  {
592  case 1:
593  (*info->fprintf_func) (info->stream, ",bc ");
594  break;
595  case 2:
596  (*info->fprintf_func) (info->stream, ",sl ");
597  break;
598  default:
599  (*info->fprintf_func) (info->stream, " ");
600  }
601  break;
602  case 'd':
603  switch (GET_FIELD (insn, 20, 21))
604  {
605  case 1:
606  (*info->fprintf_func) (info->stream, ",co ");
607  break;
608  default:
609  (*info->fprintf_func) (info->stream, " ");
610  }
611  break;
612  case 'o':
613  (*info->fprintf_func) (info->stream, ",o");
614  break;
615  case 'g':
616  (*info->fprintf_func) (info->stream, ",gate");
617  break;
618  case 'p':
619  (*info->fprintf_func) (info->stream, ",l,push");
620  break;
621  case 'P':
622  (*info->fprintf_func) (info->stream, ",pop");
623  break;
624  case 'l':
625  case 'L':
626  (*info->fprintf_func) (info->stream, ",l");
627  break;
628  case 'w':
629  (*info->fprintf_func)
630  (info->stream, "%s ",
631  read_write_names[GET_FIELD (insn, 25, 25)]);
632  break;
633  case 'W':
634  (*info->fprintf_func) (info->stream, ",w ");
635  break;
636  case 'r':
637  if (GET_FIELD (insn, 23, 26) == 5) {
638  (*info->fprintf_func) (info->stream, ",r");
639  }
640  break;
641  case 'Z':
642  if (GET_FIELD (insn, 26, 26)) {
643  (*info->fprintf_func) (info->stream, ",m ");
644  } else {
645  (*info->fprintf_func) (info->stream, " ");
646  }
647  break;
648  case 'i':
649  if (GET_FIELD (insn, 25, 25)) {
650  (*info->fprintf_func) (info->stream, ",i");
651  }
652  break;
653  case 'z':
654  if (!GET_FIELD (insn, 21, 21)) {
655  (*info->fprintf_func) (info->stream, ",z");
656  }
657  break;
658  case 'a':
659  (*info->fprintf_func)
660  (info->stream, "%s",
661  add_compl_names[GET_FIELD (insn, 20, 21)]);
662  break;
663  case 'Y':
664  (*info->fprintf_func)
665  (info->stream, ",dc%s",
666  add_compl_names[GET_FIELD (insn, 20, 21)]);
667  break;
668  case 'y':
669  (*info->fprintf_func)
670  (info->stream, ",c%s",
671  add_compl_names[GET_FIELD (insn, 20, 21)]);
672  break;
673  case 'v':
674  if (GET_FIELD (insn, 20, 20)) {
675  (*info->fprintf_func) (info->stream, ",tsv");
676  }
677  break;
678  case 't':
679  (*info->fprintf_func) (info->stream, ",tc");
680  if (GET_FIELD (insn, 20, 20)) {
681  (*info->fprintf_func) (info->stream, ",tsv");
682  }
683  break;
684  case 'B':
685  (*info->fprintf_func) (info->stream, ",db");
686  if (GET_FIELD (insn, 20, 20)) {
687  (*info->fprintf_func) (info->stream, ",tsv");
688  }
689  break;
690  case 'b':
691  (*info->fprintf_func) (info->stream, ",b");
692  if (GET_FIELD (insn, 20, 20)) {
693  (*info->fprintf_func) (info->stream, ",tsv");
694  }
695  break;
696  case 'T':
697  if (GET_FIELD (insn, 25, 25)) {
698  (*info->fprintf_func) (info->stream, ",tc");
699  }
700  break;
701  case 'S':
702  /* EXTRD/W has a following condition. */
703  if (*(s + 1) == '?') {
704  (*info->fprintf_func) (info->stream, "%s",
705  signed_unsigned_names[GET_FIELD (insn, 21, 21)]);
706  } else {
707  (*info->fprintf_func) (info->stream, "%s ",
708  signed_unsigned_names[GET_FIELD (insn, 21, 21)]);
709  }
710  break;
711  case 'h':
712  (*info->fprintf_func)
713  (info->stream, "%s",
714  mix_half_names[GET_FIELD (insn, 17, 17)]);
715  break;
716  case 'H':
717  (*info->fprintf_func)
718  (info->stream, "%s ",
719  saturation_names[GET_FIELD (insn, 24, 25)]);
720  break;
721  case '*':
722  (*info->fprintf_func)
723  (info->stream, ",%d%d%d%d ",
724  GET_FIELD (insn, 17, 18), GET_FIELD (insn, 20, 21),
725  GET_FIELD (insn, 22, 23), GET_FIELD (insn, 24, 25));
726  break;
727 
728  case 'q':
729  {
730  int m, a;
731 
732  m = GET_FIELD (insn, 28, 28);
733  a = GET_FIELD (insn, 29, 29);
734 
735  if (m && !a) {
736  fputs_filtered (",ma ", info);
737  } else if (m && a) {
738  fputs_filtered (",mb ", info);
739  } else {
740  fputs_filtered (" ", info);
741  }
742  break;
743  }
744 
745  case 'J':
746  {
747  int opc = GET_FIELD (insn, 0, 5);
748 
749  if (opc == 0x16 || opc == 0x1e)
750  {
751  if (GET_FIELD (insn, 29, 29) == 0) {
752  fputs_filtered (",ma ", info);
753  } else {
754  fputs_filtered (",mb ", info);
755  }
756  } else {
757  fputs_filtered (" ", info);
758  }
759  break;
760  }
761 
762  case 'e':
763  {
764  int opc = GET_FIELD (insn, 0, 5);
765 
766  if (opc == 0x13 || opc == 0x1b)
767  {
768  if (GET_FIELD (insn, 18, 18) == 1) {
769  fputs_filtered (",mb ", info);
770  } else {
771  fputs_filtered (",ma ", info);
772  }
773  }
774  else if (opc == 0x17 || opc == 0x1f)
775  {
776  if (GET_FIELD (insn, 31, 31) == 1) {
777  fputs_filtered (",ma ", info);
778  } else {
779  fputs_filtered (",mb ", info);
780  }
781  } else {
782  fputs_filtered (" ", info);
783  }
784 
785  break;
786  }
787  }
788  break;
789 
790  /* Handle conditions. */
791  case '?':
792  {
793  s++;
794  switch (*s)
795  {
796  case 'f':
797  (*info->fprintf_func)
798  (info->stream, "%s ",
799  float_comp_names[GET_FIELD (insn, 27, 31)]);
800  break;
801 
802  /* These four conditions are for the set of instructions
803  which distinguish true/false conditions by opcode
804  rather than by the 'f' bit (sigh): comb, comib,
805  addb, addib. */
806  case 't':
807  fputs_filtered
808  (compare_cond_names[GET_FIELD (insn, 16, 18)], info);
809  break;
810  case 'n':
811  fputs_filtered
812  (compare_cond_names[GET_FIELD (insn, 16, 18)
813  + GET_FIELD (insn, 4, 4) * 8],
814  info);
815  break;
816  case 'N':
817  fputs_filtered
818  (compare_cond_64_names[GET_FIELD (insn, 16, 18)
819  + GET_FIELD (insn, 2, 2) * 8],
820  info);
821  break;
822  case 'Q':
823  fputs_filtered
824  (cmpib_cond_64_names[GET_FIELD (insn, 16, 18)],
825  info);
826  break;
827  case '@':
828  fputs_filtered
829  (add_cond_names[GET_FIELD (insn, 16, 18)
830  + GET_FIELD (insn, 4, 4) * 8],
831  info);
832  break;
833  case 's':
834  (*info->fprintf_func)
835  (info->stream, "%s ",
836  compare_cond_names[GET_COND (insn)]);
837  break;
838  case 'S':
839  (*info->fprintf_func)
840  (info->stream, "%s ",
841  compare_cond_64_names[GET_COND (insn)]);
842  break;
843  case 'a':
844  (*info->fprintf_func)
845  (info->stream, "%s ",
846  add_cond_names[GET_COND (insn)]);
847  break;
848  case 'A':
849  (*info->fprintf_func)
850  (info->stream, "%s ",
851  add_cond_64_names[GET_COND (insn)]);
852  break;
853  case 'd':
854  (*info->fprintf_func)
855  (info->stream, "%s",
856  add_cond_names[GET_FIELD (insn, 16, 18)]);
857  break;
858 
859  case 'W':
860  (*info->fprintf_func)
861  (info->stream, "%s",
862  wide_add_cond_names[GET_FIELD (insn, 16, 18) +
863  GET_FIELD (insn, 4, 4) * 8]);
864  break;
865 
866  case 'l':
867  (*info->fprintf_func)
868  (info->stream, "%s ",
869  logical_cond_names[GET_COND (insn)]);
870  break;
871  case 'L':
872  (*info->fprintf_func)
873  (info->stream, "%s ",
874  logical_cond_64_names[GET_COND (insn)]);
875  break;
876  case 'u':
877  (*info->fprintf_func)
878  (info->stream, "%s ",
879  unit_cond_names[GET_COND (insn)]);
880  break;
881  case 'U':
882  (*info->fprintf_func)
883  (info->stream, "%s ",
884  unit_cond_64_names[GET_COND (insn)]);
885  break;
886  case 'y':
887  case 'x':
888  case 'b':
889  (*info->fprintf_func)
890  (info->stream, "%s",
891  shift_cond_names[GET_FIELD (insn, 16, 18)]);
892 
893  /* If the next character in args is 'n', it will handle
894  putting out the space. */
895  if (s[1] != 'n') {
896  (*info->fprintf_func) (info->stream, " ");
897  }
898  break;
899  case 'X':
900  (*info->fprintf_func)
901  (info->stream, "%s ",
902  shift_cond_64_names[GET_FIELD (insn, 16, 18)]);
903  break;
904  case 'B':
905  (*info->fprintf_func)
906  (info->stream, "%s",
907  bb_cond_64_names[GET_FIELD (insn, 16, 16)]);
908 
909  /* If the next character in args is 'n', it will handle
910  putting out the space. */
911  if (s[1] != 'n') {
912  (*info->fprintf_func) (info->stream, " ");
913  }
914  break;
915  }
916  break;
917  }
918 
919  case 'V':
920  fput_const (extract_5_store (insn), info);
921  break;
922  case 'r':
923  fput_const (extract_5r_store (insn), info);
924  break;
925  case 'R':
926  fput_const (extract_5R_store (insn), info);
927  break;
928  case 'U':
929  fput_const (extract_10U_store (insn), info);
930  break;
931  case 'B':
932  case 'Q':
933  fput_const (extract_5Q_store (insn), info);
934  break;
935  case 'i':
936  fput_const (extract_11 (insn), info);
937  break;
938  case 'j':
939  fput_const (extract_14 (insn), info);
940  break;
941  case 'k':
942  fputs_filtered ("L%", info);
943  fput_const (extract_21 (insn), info);
944  break;
945  case '<':
946  case 'l':
947  /* 16-bit long disp., PA2.0 wide only. */
948  fput_const (extract_16 (insn), info);
949  break;
950  case 'n':
951  if (insn & 0x2) {
952  (*info->fprintf_func) (info->stream, ",n ");
953  } else {
954  (*info->fprintf_func) (info->stream, " ");
955  }
956  break;
957  case 'N':
958  if ((insn & 0x20) && s[1]) {
959  (*info->fprintf_func) (info->stream, ",n ");
960  } else if (insn & 0x20) {
961  (*info->fprintf_func) (info->stream, ",n");
962  } else if (s[1]) {
963  (*info->fprintf_func) (info->stream, " ");
964  }
965  break;
966  case 'w':
967  (*info->print_address_func)
968  (memaddr + 8 + extract_12 (insn), info);
969  break;
970  case 'W':
971  /* 17 bit PC-relative branch. */
972  (*info->print_address_func)
973  ((memaddr + 8 + extract_17 (insn)), info);
974  break;
975  case 'z':
976  /* 17 bit displacement. This is an offset from a register
977  so it gets disasssembled as just a number, not any sort
978  of address. */
979  fput_const (extract_17 (insn), info);
980  break;
981 
982  case 'Z':
983  /* addil %r1 implicit output. */
984  fputs_filtered ("r1", info);
985  break;
986 
987  case 'Y':
988  /* be,l %sr0,%r31 implicit output. */
989  fputs_filtered ("sr0,r31", info);
990  break;
991 
992  case '@':
993  (*info->fprintf_func) (info->stream, "0");
994  break;
995 
996  case '.':
997  (*info->fprintf_func) (info->stream, "%d",
998  GET_FIELD (insn, 24, 25));
999  break;
1000  case '*':
1001  (*info->fprintf_func) (info->stream, "%d",
1002  GET_FIELD (insn, 22, 25));
1003  break;
1004  case '!':
1005  fputs_filtered ("sar", info);
1006  break;
1007  case 'p':
1008  (*info->fprintf_func) (info->stream, "%d",
1009  31 - GET_FIELD (insn, 22, 26));
1010  break;
1011  case '~':
1012  {
1013  int num;
1014  num = GET_FIELD (insn, 20, 20) << 5;
1015  num |= GET_FIELD (insn, 22, 26);
1016  (*info->fprintf_func) (info->stream, "%d", 63 - num);
1017  break;
1018  }
1019  case 'P':
1020  (*info->fprintf_func) (info->stream, "%d",
1021  GET_FIELD (insn, 22, 26));
1022  break;
1023  case 'q':
1024  {
1025  int num;
1026  num = GET_FIELD (insn, 20, 20) << 5;
1027  num |= GET_FIELD (insn, 22, 26);
1028  (*info->fprintf_func) (info->stream, "%d", num);
1029  break;
1030  }
1031  case 'T':
1032  (*info->fprintf_func) (info->stream, "%d",
1033  32 - GET_FIELD (insn, 27, 31));
1034  break;
1035  case '%':
1036  {
1037  int num;
1038  num = (GET_FIELD (insn, 23, 23) + 1) * 32;
1039  num -= GET_FIELD (insn, 27, 31);
1040  (*info->fprintf_func) (info->stream, "%d", num);
1041  break;
1042  }
1043  case '|':
1044  {
1045  int num;
1046  num = (GET_FIELD (insn, 19, 19) + 1) * 32;
1047  num -= GET_FIELD (insn, 27, 31);
1048  (*info->fprintf_func) (info->stream, "%d", num);
1049  break;
1050  }
1051  case '$':
1052  fput_const (GET_FIELD (insn, 20, 28), info);
1053  break;
1054  case 'A':
1055  fput_const (GET_FIELD (insn, 6, 18), info);
1056  break;
1057  case 'D':
1058  fput_const (GET_FIELD (insn, 6, 31), info);
1059  break;
1060  case 'v':
1061  (*info->fprintf_func) (info->stream, ",%d",
1062  GET_FIELD (insn, 23, 25));
1063  break;
1064  case 'O':
1065  fput_const ((GET_FIELD (insn, 6,20) << 5 |
1066  GET_FIELD (insn, 27, 31)), info);
1067  break;
1068  case 'o':
1069  fput_const (GET_FIELD (insn, 6, 20), info);
1070  break;
1071  case '2':
1072  fput_const ((GET_FIELD (insn, 6, 22) << 5 |
1073  GET_FIELD (insn, 27, 31)), info);
1074  break;
1075  case '1':
1076  fput_const ((GET_FIELD (insn, 11, 20) << 5 |
1077  GET_FIELD (insn, 27, 31)), info);
1078  break;
1079  case '0':
1080  fput_const ((GET_FIELD (insn, 16, 20) << 5 |
1081  GET_FIELD (insn, 27, 31)), info);
1082  break;
1083  case 'u':
1084  (*info->fprintf_func) (info->stream, ",%d",
1085  GET_FIELD (insn, 23, 25));
1086  break;
1087  case 'F':
1088  /* If no destination completer and not before a completer
1089  for fcmp, need a space here. */
1090  if (s[1] == 'G' || s[1] == '?') {
1091  fputs_filtered (float_format_names[GET_FIELD (insn, 19, 20)], info);
1092  } else {
1093  (*info->fprintf_func) (info->stream, "%s ",
1094  float_format_names[GET_FIELD (insn, 19, 20)]);
1095  }
1096  break;
1097  case 'G':
1098  (*info->fprintf_func)
1099  (info->stream, "%s ",
1100  float_format_names[GET_FIELD (insn, 17, 18)]);
1101  break;
1102  case 'H':
1103  if (GET_FIELD (insn, 26, 26) == 1) {
1104  (*info->fprintf_func) (info->stream, "%s ",
1105  float_format_names[0]);
1106  } else {
1107  (*info->fprintf_func) (info->stream, "%s ",
1108  float_format_names[1]);
1109  }
1110  break;
1111  case 'I':
1112  /* If no destination completer and not before a completer
1113  for fcmp, need a space here. */
1114  if (s[1] == '?') {
1115  fputs_filtered (float_format_names[GET_FIELD (insn, 20, 20)], info);
1116  } else {
1117  (*info->fprintf_func) (info->stream, "%s ",
1118  float_format_names[GET_FIELD (insn, 20, 20)]);
1119  }
1120  break;
1121 
1122  case 'J':
1123  fput_const (extract_14 (insn), info);
1124  break;
1125 
1126  case '#':
1127  {
1128  int sign = GET_FIELD (insn, 31, 31);
1129  int imm10 = GET_FIELD (insn, 18, 27);
1130  int disp;
1131 
1132  if (sign) {
1133  disp = (UT64_MAX << 10) | imm10;
1134  } else {
1135  disp = imm10;
1136  }
1137 
1138  disp <<= 3;
1139  fput_const (disp, info);
1140  break;
1141  }
1142  case 'K':
1143  case 'd':
1144  {
1145  int sign = GET_FIELD (insn, 31, 31);
1146  int imm11 = GET_FIELD (insn, 18, 28);
1147  int disp;
1148 
1149  if (sign) {
1150  disp = (UT64_MAX << 11) | imm11;
1151  } else {
1152  disp = imm11;
1153  }
1154 
1155  disp <<= 2;
1156  fput_const (disp, info);
1157  break;
1158  }
1159 
1160  case '>':
1161  case 'y':
1162  {
1163  /* 16-bit long disp., PA2.0 wide only. */
1164  int disp = extract_16 (insn);
1165  disp &= ~3;
1166  fput_const (disp, info);
1167  break;
1168  }
1169 
1170  case '&':
1171  {
1172  /* 16-bit long disp., PA2.0 wide only. */
1173  int disp = extract_16 (insn);
1174  disp &= ~7;
1175  fput_const (disp, info);
1176  break;
1177  }
1178 
1179  case '_':
1180  break; /* Dealt with by '{' */
1181 
1182  case '{':
1183  {
1184  int sub = GET_FIELD (insn, 14, 16);
1185  int df = GET_FIELD (insn, 17, 18);
1186  int sf = GET_FIELD (insn, 19, 20);
1187  const char * const * source = float_format_names;
1188  const char * const * dest = float_format_names;
1189  char *t = "";
1190 
1191  if (sub == 4)
1192  {
1193  fputs_filtered (",UND ", info);
1194  break;
1195  }
1196  if ((sub & 3) == 3) {
1197  t = ",t";
1198  }
1199  if ((sub & 3) == 1) {
1200  source = sub & 4 ? fcnv_ufixed_names : fcnv_fixed_names;
1201  }
1202  if (sub & 2) {
1203  dest = sub & 4 ? fcnv_ufixed_names : fcnv_fixed_names;
1204  }
1205 
1206  (*info->fprintf_func) (info->stream, "%s%s%s ",
1207  t, source[sf], dest[df]);
1208  break;
1209  }
1210 
1211  case 'm':
1212  {
1213  int y = GET_FIELD (insn, 16, 18);
1214 
1215  if (y != 1) {
1216  fput_const ((y ^ 1) - 1, info);
1217  }
1218  }
1219  break;
1220 
1221  case 'h':
1222  {
1223  int cbit;
1224 
1225  cbit = GET_FIELD (insn, 16, 18);
1226 
1227  if (cbit > 0) {
1228  (*info->fprintf_func) (info->stream, ",%d", cbit - 1);
1229  }
1230  break;
1231  }
1232 
1233  case '=':
1234  {
1235  int cond = GET_FIELD (insn, 27, 31);
1236 
1237  switch (cond)
1238  {
1239  case 0: fputs_filtered (" ", info); break;
1240  case 1: fputs_filtered ("acc ", info); break;
1241  case 2: fputs_filtered ("rej ", info); break;
1242  case 5: fputs_filtered ("acc8 ", info); break;
1243  case 6: fputs_filtered ("rej8 ", info); break;
1244  case 9: fputs_filtered ("acc6 ", info); break;
1245  case 13: fputs_filtered ("acc4 ", info); break;
1246  case 17: fputs_filtered ("acc2 ", info); break;
1247  default: break;
1248  }
1249  break;
1250  }
1251 
1252  case 'X':
1253  (*info->print_address_func)
1254  (memaddr + 8 + extract_22 (insn), info);
1255  break;
1256  case 'L':
1257  fputs_filtered (",rp", info);
1258  break;
1259  default:
1260  (*info->fprintf_func) (info->stream, "%c", *s);
1261  break;
1262  }
1263  }
1264  return sizeof (insn);
1265  }
1266  }
1267  (*info->fprintf_func) (info->stream, "#%8x", insn);
1268  return sizeof (insn);
1269 }
i
lzma_index ** i
Definition: index.h:629
opc
static ut64 opc
Definition: desil.c:33
extract_5R_store
static unsigned extract_5R_store(unsigned word)
Definition: hppa-dis.c:253
fput_fp_reg_r
static void fput_fp_reg_r(unsigned reg, disassemble_info *info)
Definition: hppa-dis.c:190
fput_creg
static void fput_creg(unsigned reg, disassemble_info *info)
Definition: hppa-dis.c:201
logical_cond_names
static const char *const logical_cond_names[]
Definition: hppa-dis.c:112
extract_10U_store
static unsigned extract_10U_store(unsigned word)
Definition: hppa-dis.c:261
extract_5_store
static int extract_5_store(unsigned word)
Definition: hppa-dis.c:237
wide_add_cond_names
static const char *const wide_add_cond_names[]
Definition: hppa-dis.c:107
extract_12
static int extract_12(unsigned word)
Definition: hppa-dis.c:329
compare_cond_64_names
static const char *const compare_cond_64_names[]
Definition: hppa-dis.c:88
short_ldst_compl_names
static const char *const short_ldst_compl_names[]
Definition: hppa-dis.c:143
float_format_names
static const char *const float_format_names[]
Definition: hppa-dis.c:148
add_compl_names
static const char *const add_compl_names[]
Definition: hppa-dis.c:162
extract_5_load
static int extract_5_load(unsigned word)
Definition: hppa-dis.c:229
mix_half_names
static const char *const mix_half_names[]
Definition: hppa-dis.c:159
extract_3
static int extract_3(unsigned word)
Definition: hppa-dis.c:223
logical_cond_64_names
static const char *const logical_cond_64_names[]
Definition: hppa-dis.c:116
GET_FIELD
#define GET_FIELD(X, FROM, TO)
Definition: hppa-dis.c:65
extract_16
static int extract_16(unsigned word)
Definition: hppa-dis.c:293
fput_reg
static void fput_reg(unsigned reg, disassemble_info *info)
Definition: hppa-dis.c:178
saturation_names
static const char *const saturation_names[]
Definition: hppa-dis.c:160
signed_unsigned_names
static const char *const signed_unsigned_names[]
Definition: hppa-dis.c:158
compare_cond_names
static const char *const compare_cond_names[]
Definition: hppa-dis.c:83
read_write_names
static const char *const read_write_names[]
Definition: hppa-dis.c:161
index_compl_names
static const char *const index_compl_names[]
Definition: hppa-dis.c:142
fcnv_ufixed_names
static const char *const fcnv_ufixed_names[]
Definition: hppa-dis.c:150
fcnv_fixed_names
static const char *const fcnv_fixed_names[]
Definition: hppa-dis.c:149
add_cond_64_names
static const char *const add_cond_64_names[]
Definition: hppa-dis.c:102
extract_11
static int extract_11(unsigned word)
Definition: hppa-dis.c:277
extract_21
static int extract_21(unsigned word)
Definition: hppa-dis.c:308
fput_const
static void fput_const(unsigned num, disassemble_info *info)
Definition: hppa-dis.c:209
bb_cond_64_names
static const char *const bb_cond_64_names[]
Definition: hppa-dis.c:138
extract_22
static int extract_22(unsigned word)
Definition: hppa-dis.c:349
fputs_filtered
#define fputs_filtered(STR, F)
Definition: hppa-dis.c:175
GET_COND
#define GET_COND(insn)
Definition: hppa-dis.c:169
extract_17
static int extract_17(unsigned word)
Definition: hppa-dis.c:340
extract_14
static int extract_14(unsigned word)
Definition: hppa-dis.c:285
unit_cond_names
static const char *const unit_cond_names[]
Definition: hppa-dis.c:120
GET_COMPL
#define GET_COMPL(insn)
Definition: hppa-dis.c:166
shift_cond_64_names
static const char *const shift_cond_64_names[]
Definition: hppa-dis.c:134
shift_cond_names
static const char *const shift_cond_names[]
Definition: hppa-dis.c:130
extract_5Q_store
static unsigned extract_5Q_store(unsigned word)
Definition: hppa-dis.c:269
unit_cond_64_names
static const char *const unit_cond_64_names[]
Definition: hppa-dis.c:125
cmpib_cond_64_names
static const char *const cmpib_cond_64_names[]
Definition: hppa-dis.c:93
fput_fp_reg
static void fput_fp_reg(unsigned reg, disassemble_info *info)
Definition: hppa-dis.c:184
float_comp_names
static const char *const float_comp_names[]
Definition: hppa-dis.c:151
short_bytes_compl_names
static const char *const short_bytes_compl_names[]
Definition: hppa-dis.c:144
add_cond_names
static const char *const add_cond_names[]
Definition: hppa-dis.c:97
extract_5r_store
static unsigned extract_5r_store(unsigned word)
Definition: hppa-dis.c:245
pa_opcodes
static const struct pa_opcode pa_opcodes[]
Definition: hppa.h:312
NUMOPCODES
#define NUMOPCODES
Definition: hppa.h:1079
reg
#define reg(n)
pa20w
@ pa20w
Definition: libhppa.h:37
num
static static fork const void static count static fd const char const char static newpath char char char static envp time_t static t const char static mode static whence const char static dir time_t static t unsigned static seconds const char struct utimbuf static buf static inc static sig const char static mode static oldfd struct tms static buf static getgid static geteuid const char static filename static arg static mask struct ustat static ubuf static getppid static setsid static egid sigset_t static set struct timeval struct timezone static tz fd_set fd_set fd_set struct timeval static timeout const char char static bufsiz const char static swapflags void static offset const char static length static mode static who const char struct statfs static buf unsigned unsigned num
Definition: sflib.h:126
source
const char * source
Definition: lz4.h:699
dest
char * dest
Definition: lz4.h:697
bfd_getb32
static bfd_vma bfd_getb32(const void *p)
Definition: mybfd.h:4979
s
static RzSocket * s
Definition: rtr.c:28
UT64_MAX
#define UT64_MAX
Definition: rz_types_base.h:86
a
#define a(i)
Definition: sha256.c:41
cond
#define cond(bop, top, mask, flags)
pa_opcode
Definition: hppa.h:43
pa_opcode::arch
enum pa_arch arch
Definition: hppa.h:48
pa_opcode::args
char * args
Definition: hppa.h:47
pa_opcode::mask
unsigned long int mask
Definition: hppa.h:46
pa_opcode::match
unsigned long int match
Definition: hppa.h:45
pa_opcode::name
const char * name
Definition: hppa.h:44

References a, add_compl_names, add_cond_64_names, add_cond_names, pa_opcode::arch, pa_opcode::args, bb_cond_64_names, bfd_getb32(), cmpib_cond_64_names, compare_cond_64_names, compare_cond_names, cond, dest, extract_10U_store(), extract_11(), extract_12(), extract_14(), extract_16(), extract_17(), extract_21(), extract_22(), extract_3(), extract_5_load(), extract_5_store(), extract_5Q_store(), extract_5r_store(), extract_5R_store(), fcnv_fixed_names, fcnv_ufixed_names, float_comp_names, float_format_names, fput_const(), fput_creg(), fput_fp_reg(), fput_fp_reg_r(), fput_reg(), fputs_filtered, GET_COMPL, GET_COND, GET_FIELD, i, index_compl_names, info(), logical_cond_64_names, logical_cond_names, regress::m, pa_opcode::mask, pa_opcode::match, mix_half_names, pa_opcode::name, num, NUMOPCODES, opc, pa20w, pa_opcodes, read_write_names, reg, s, saturation_names, shift_cond_64_names, shift_cond_names, short_bytes_compl_names, short_ldst_compl_names, signed_unsigned_names, source, status, unit_cond_64_names, unit_cond_names, UT64_MAX, and wide_add_cond_names.

Referenced by disassemble().

◆ print_insn_i370()

int print_insn_i370 ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_i386()

int print_insn_i386 ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_i386_att()

int print_insn_i386_att ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_i386_intel()

int print_insn_i386_intel ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_i860()

int print_insn_i860 ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_i960()

int print_insn_i960 ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_ia64()

int print_insn_ia64 ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_ip2k()

int print_insn_ip2k ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_iq2000()

int print_insn_iq2000 ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_lanai()

int print_insn_lanai ( bfd_vma  memaddr,
disassemble_info *  info 
)

Definition at line 106 of file lanai-dis.c.

109 {
110  FILE *stream = info->stream;
111  bfd_byte buffer[4];
112  unsigned int insn;
113  register int i;
114 
115  if (!opcodes_sorted)
116  {
117  qsort ((char *) lanai_opcodes, NUMOPCODES,
118  sizeof (lanai_opcodes[0]),
119  (int (*)(const void *,const void *))compare_opcodes);
120  opcodes_sorted = 1;
121  }
122 
123  {
124  int status =
125  (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
126  if (status != 0)
127  {
128  (*info->memory_error_func) (status, memaddr, info);
129  return -1;
130  }
131  }
132 
133  insn = bfd_getb32 (buffer);
134 
135  info->insn_info_valid = 1; /* We do return this info */
136  info->insn_type = dis_nonbranch; /* Assume non branch insn */
137  info->branch_delay_insns = 0; /* Assume no delay */
138  info->target = 0; /* Assume no target known */
139 
140  for (i = 0; i < NUMOPCODES; i++)
141  {
142  CONST struct lanai_opcode *opcode = &lanai_opcodes[i];
143  if ((opcode->match & insn) == opcode->match
144  && (opcode->lose & insn) == 0)
145  {
146  /* Nonzero means that we have found an instruction which has
147  the effect of adding or or'ing the imm13 field to rs1. */
148  int imm_added_to_rs1 = 0;
149 
150  /* Do we have an `add' or `or' immediate instruction where rs1 is
151  the same as rd? */
152 
153  if (((!(opcode->match & 0x80000000) /* RI insn */
154  && ( !(opcode->match & 0x70000000) /* RI add */
155  || (opcode->match & 0x70000000) == 0x50000000 /* RI or */
156  ))
157  || ((opcode->match & 0xf0000000) == 0xc0000000 /* RR insn */
158  && ( !(opcode->match & 0x00000700) /* RR add */
159  || (opcode->match & 0x00000700) == 0x00000500 /* RR or */ )))
160  && X_RS1(insn) == X_RD(insn))
161  {
162  imm_added_to_rs1 = 1;
163  }
164 
165 #ifdef BAD
166  if (X_RS1 (insn) != X_RD (insn)
167  && strchr (opcode->args, 'r') != 0)
168  /* Can't do simple format if source and dest are different. */
169  continue;
170 #endif
171 
172  (*info->fprintf_func) (stream, "%s", opcode->name);
173 
174  {
175  register CONST char *s;
176  unsigned int imm;
177 
178  for (s = opcode->args; *s != '\0'; ++s)
179  {
180 
181  (*info->fprintf_func) (stream, " ");
182 
183  switch (*s)
184  {
185  /* By default, just print the character. */
186  default:
187  (*info->fprintf_func) (stream, "%c", *s);
188  break;
189 
190 #define reg(n) (*info->fprintf_func) (stream, "%s", reg_names[n])
191 // #define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n])
192  case '1':
193  reg (X_RS1 (insn));
194  break;
195 
196  case '2':
197  reg (X_RS2 (insn));
198  break;
199 
200  case '3':
201  reg (X_RS3 (insn));
202  break;
203 
204  case 'd':
205  reg (X_RD (insn));
206  break;
207 
208 #undef reg
209 
210  case '4': /* Op1 (for RRR) */
211  (*info->fprintf_func) (stream, "%s", op_names[X_OP1(insn)]);
212  break;
213  case '5': /* Op2 (for RRR) */
214  (*info->fprintf_func) (stream, "%s", op_names[X_OP2(insn)]);
215  if (insn & L3_RRR_F) {
216  (*info->fprintf_func) (stream, ".f");
217  }
218  break;
219  case '6': /* Op2 (for RRM) */
220  (*info->fprintf_func) (stream, "%s", op_names[X_OP2(insn)]);
221  break;
222 
223  case 'J':
224  imm = X_C16(insn)<<16;
225  goto print_immediate;
226  case 'j':
227  imm = X_C16(insn);
228  goto print_immediate;
229  case 'L':
230  imm = (X_C16(insn)<<16)|0xffff;
231  goto print_immediate;
232  case 'l':
233  imm = X_C16(insn)|0xffff0000;
234  goto print_immediate;
235  case 'k':
236  /* This should never happen */
237  (*info->fprintf_func) (stream, "***ERROR***");
238  break;
239  case 'o':
240  imm = SIGN_EXT (X_C16(insn), 16);
241  if (X_RS1 (insn) == 0) {
242  goto print_address;
243  }
244  goto print_immediate;
245  case 's':
246  imm = SIGN_EXT (X_C16(insn), 16);
247  goto print_immediate;
248  case 'i':
249  imm = SIGN_EXT (X_C10(insn), 10);
250  if (X_RS1 (insn) == 0) {
251  goto print_address;
252  }
253  goto print_immediate;
254  case 'I':
255  imm = X_C21(insn);
256  goto print_address;
257  case 'Y':
258  imm = X_C21(insn);
259  goto print_address;
260  case 'B':
261  imm = X_C25(insn);
262  goto print_address;
263  case 'b':
264  imm = SIGN_EXT (X_C25(insn), 25);
265  goto print_address;
266 
267  print_immediate:
268  (*info->fprintf_func) (stream, "0x%x", imm);
269  break;
270  print_address:
271  info->target = imm;
272  (*info->print_address_func) (imm, info);
273  break;
274 
275  /* Named registers */
276 
277  case 'P':
278  (*info->fprintf_func) (stream, "%%pc");
279  break;
280 
281  case 'p':
282  (*info->fprintf_func) (stream, "%%ps");
283  break;
284 
285  case 'Q':
286  (*info->fprintf_func) (stream, "%%apc");
287  break;
288 
289  case 'q':
290  (*info->fprintf_func) (stream, "%%aps");
291  break;
292 
293  case 'S':
294  (*info->fprintf_func) (stream, "%%isr");
295  break;
296 
297  case 'M':
298  (*info->fprintf_func) (stream, "%%imr");
299  break;
300 
301  case '!':
302  (*info->fprintf_func) (stream, "%%r1");
303  break;
304 
305  case '0':
306  (*info->fprintf_func) (stream, "%%r0");
307  break;
308 
309  }
310  }
311  }
312 
313  /* If we are adding or or'ing something to rs1, then
314  check to see whether the previous instruction was
315  a mov to the same register as in the or.
316  If so, attempt to print the result of the add or
317  or (in this context add and or do the same thing)
318  and its symbolic value. */
319  if (imm_added_to_rs1)
320  {
321  unsigned long prev_insn;
322  int errcode;
323 
324  errcode =
325  (*info->read_memory_func)
326  (memaddr - 4, buffer, sizeof (buffer), info);
327  prev_insn = bfd_getb32 (buffer);
328 
329  if (errcode == 0)
330  {
331  /* If it is a delayed branch, we need to look at the
332  instruction before the delayed branch. This handles
333  sequences such as
334 
335  mov %hi(_foo), %r4
336  call _printf
337  or %r4, %lo(_foo), %r4
338  */
339 
340  if (is_delayed_branch (prev_insn))
341  {
342  errcode = (*info->read_memory_func)
343  (memaddr - 8, buffer, sizeof (buffer), info);
344  prev_insn = bfd_getb32 (buffer);
345  }
346  }
347 
348  /* If there was a problem reading memory, then assume
349  the previous instruction was not sethi. */
350  if (errcode == 0)
351  {
352  /* Is it an "{and,or} %r0,0x????????,%rd" to the same reg */
353  if (((prev_insn & 0xf07c0000) == 0x00000000
354  || (prev_insn & 0xf07c0000) == 0x50000000 )
355  && X_RD (prev_insn) == X_RS1 (insn)
356  && X_RD (prev_insn) )
357  {
358  (*info->fprintf_func) (stream, "\t! ");
359  info->target
360  = X_C16( insn) << (L3_RI_H& insn ? 16 : 0);
361  if((prev_insn & 0xf07c0000) == 0x50000000 ){
362  info->target
363  |= X_C16(prev_insn) << (L3_RI_H&prev_insn ? 16 : 0);
364  }else{
365  info->target
366  += X_C16(prev_insn) << (L3_RI_H&prev_insn ? 16 : 0);
367  }
368  (*info->print_address_func) (info->target, info);
369  info->insn_type = dis_dref;
370  info->data_size = 4; /* FIXME!!! */
371  }
372  }
373  }
374 
375  info->data_size = F_DATA_SIZE(opcode->flags);
376 
377  if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
378  {
379  /* FIXME -- check is_annulled flag */
380  if (opcode->flags & F_UNBR) {
381  info->insn_type = dis_branch;
382  } else if (opcode->flags & F_CONDBR) {
383  info->insn_type = dis_condbranch;
384  } else if (opcode->flags & F_JSR) {
385  info->insn_type = dis_jsr;
386  } else if (opcode->flags & F_BR) {
387  info->branch_delay_insns = 1;
388  }
389  }
390 
391  return sizeof (buffer);
392  }
393  }
394 
395  info->insn_type = dis_noninsn; /* Mark as non-valid instruction */
396  (*info->fprintf_func) (stream, "%#8x", insn);
397  return sizeof (buffer);
398 }
imm
#define imm
Definition: analysis_h8300.c:43
X_OP2
#define X_OP2(i)
Definition: analysis_sparc_gnu.c:144
X_RS2
#define X_RS2(i)
Definition: analysis_sparc_gnu.c:152
X_RD
#define X_RD(i)
Definition: analysis_sparc_gnu.c:148
X_RS1
#define X_RS1(i)
Definition: analysis_sparc_gnu.c:149
buffer
struct buffer buffer
is_delayed_branch
static int is_delayed_branch(unsigned long insn)
Definition: lanai-dis.c:79
op_names
static char * op_names[]
Definition: lanai-dis.c:72
compare_opcodes
static int compare_opcodes(char *a, char *b)
Definition: lanai-dis.c:403
opcodes_sorted
static int opcodes_sorted
Definition: lanai-dis.c:94
F_BR
#define F_BR
Definition: lanai.h:107
F_DATA_SIZE
#define F_DATA_SIZE(X)
Definition: lanai.h:118
F_UNBR
#define F_UNBR
Definition: lanai.h:126
X_OP1
#define X_OP1(i)
Definition: lanai.h:381
L3_RI_H
#define L3_RI_H
Definition: lanai.h:301
L3_RRR_F
#define L3_RRR_F
Definition: lanai.h:307
X_RS3
#define X_RS3(i)
Definition: lanai.h:379
F_CONDBR
#define F_CONDBR
Definition: lanai.h:125
lanai_opcodes
#define lanai_opcodes
Definition: lanai.h:76
F_JSR
#define F_JSR
Definition: lanai.h:100
SIGN_EXT
#define SIGN_EXT(value, bits)
Definition: lanai.h:370
X_C25
#define X_C25(i)
Definition: lanai.h:392
X_C10
#define X_C10(i)
Definition: lanai.h:389
X_C21
#define X_C21(i)
Definition: lanai.h:391
X_C16
#define X_C16(i)
Definition: lanai.h:390
CONST
#define CONST
Definition: ansidecl.h:246
benchmark.FILE
string FILE
Definition: benchmark.py:21
qsort
void qsort(void *a, size_t n, size_t es, int(*cmp)(const void *, const void *))
Definition: qsort.h:130
lanai_opcode
Definition: lanai.h:90
lanai_opcode::lose
unsigned long lose
Definition: lanai.h:93
lanai_opcode::flags
unsigned int flags
Definition: lanai.h:95
lanai_opcode::args
const char * args
Definition: lanai.h:94
lanai_opcode::match
unsigned long match
Definition: lanai.h:92
lanai_opcode::name
const char * name
Definition: lanai.h:91

References lanai_opcode::args, bfd_getb32(), compare_opcodes(), CONST, dis_branch, dis_condbranch, dis_dref, dis_jsr, dis_nonbranch, dis_noninsn, F_BR, F_CONDBR, F_DATA_SIZE, F_JSR, F_UNBR, benchmark::FILE, lanai_opcode::flags, i, imm, info(), is_delayed_branch(), L3_RI_H, L3_RRR_F, lanai_opcodes, lanai_opcode::lose, lanai_opcode::match, lanai_opcode::name, NUMOPCODES, op_names, opcodes_sorted, qsort(), reg, s, SIGN_EXT, status, X_C10, X_C16, X_C21, X_C25, X_OP1, X_OP2, X_RD, X_RS1, X_RS2, and X_RS3.

Referenced by disassemble().

◆ print_insn_little_arm()

int print_insn_little_arm ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_little_mips()

int print_insn_little_mips ( bfd_vma  memaddr,
disassemble_info *  info 
)

Definition at line 2104 of file mips-dis.c.

2105 {
2106  return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
2107 }

References _print_insn_mips(), BFD_ENDIAN_LITTLE, and info().

Referenced by disassemble().

◆ print_insn_little_nios2()

int print_insn_little_nios2 ( bfd_vma  address,
disassemble_info *  info 
)

Definition at line 428 of file nios2-dis.c.

429 {
430  return print_insn_nios2 (address, info, BFD_ENDIAN_LITTLE);
431 }

References BFD_ENDIAN_LITTLE, info(), and print_insn_nios2().

◆ print_insn_little_powerpc()

int print_insn_little_powerpc ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_little_score()

int print_insn_little_score ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_lm32()

int print_insn_lm32 ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_m32c()

int print_insn_m32c ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_m32r()

int print_insn_m32r ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_m68hc11()

int print_insn_m68hc11 ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_m68hc12()

int print_insn_m68hc12 ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_m68k()

int print_insn_m68k ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_m88k()

int print_insn_m88k ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_m9s12x()

int print_insn_m9s12x ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_m9s12xg()

int print_insn_m9s12xg ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_mcore()

int print_insn_mcore ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_mep()

int print_insn_mep ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_metag()

int print_insn_metag ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_microblaze()

int print_insn_microblaze ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_mmix()

int print_insn_mmix ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_mn10200()

int print_insn_mn10200 ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_mn10300()

int print_insn_mn10300 ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_moxie()

int print_insn_moxie ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_msp430()

int print_insn_msp430 ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_mt()

int print_insn_mt ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_nds32()

int print_insn_nds32 ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_ns32k()

int print_insn_ns32k ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_or1k()

int print_insn_or1k ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_pdp11()

int print_insn_pdp11 ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_pj()

int print_insn_pj ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_pru()

int print_insn_pru ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_riscv()

int print_insn_riscv ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_rl78()

int print_insn_rl78 ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_rl78_g10()

int print_insn_rl78_g10 ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_rl78_g13()

int print_insn_rl78_g13 ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_rl78_g14()

int print_insn_rl78_g14 ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_rs6000()

int print_insn_rs6000 ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_rx()

int print_insn_rx ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_s390()

int print_insn_s390 ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_sh()

int print_insn_sh ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_sh64()

int print_insn_sh64 ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_sh64x_media()

int print_insn_sh64x_media ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_sparc()

int print_insn_sparc ( bfd_vma  memaddr,
disassemble_info *  info 
)

Definition at line 480 of file sparc-dis.c.

481 {
482  FILE *stream = info->stream;
483  bfd_byte buffer[4];
484  unsigned long insn;
485  sparc_opcode_hash *op;
486  /* Nonzero of opcode table has been initialized. */
487  static int opcodes_initialized = 0;
488  /* bfd mach number of last call. */
489  static unsigned long current_mach = 0;
490  bfd_vma (*getword) (const void *);
491 
492  if (!opcodes_initialized
493  || info->mach != current_mach)
494  {
495  int i;
496 
497  current_arch_mask = compute_arch_mask (info->mach);
498 
499  if (!opcodes_initialized) {
500  sorted_opcodes =
501  xmalloc (sparc_num_opcodes * sizeof (sparc_opcode *));
502  }
503  /* Reset the sorted table so we can resort it. */
504  for (i = 0; i < sparc_num_opcodes; i++) {
505  sorted_opcodes[i] = &sparc_opcodes[i];
506  }
507  qsort ((char *) sorted_opcodes, sparc_num_opcodes,
508  sizeof (sorted_opcodes[0]), compare_opcodes);
509 
510  build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes);
511  current_mach = info->mach;
512  opcodes_initialized = 1;
513  }
514 
515  {
516  int status =
517  (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
518 
519  if (status != 0)
520  {
521  (*info->memory_error_func) (status, memaddr, info);
522  return -1;
523  }
524  }
525 
526  /* On SPARClite variants such as DANlite (sparc86x), instructions
527  are always big-endian even when the machine is in little-endian mode. */
528  if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite) {
529  getword = bfd_getb32;
530  } else {
531  getword = bfd_getl32;
532  }
533 
534  insn = getword (buffer);
535 
536  info->insn_info_valid = 1; /* We do return this info. */
537  info->insn_type = dis_nonbranch; /* Assume non branch insn. */
538  info->branch_delay_insns = 0; /* Assume no delay. */
539  info->target = 0; /* Assume no target known. */
540 
541  for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
542  {
543  const sparc_opcode *opcode = op->opcode;
544 
545  /* If the insn isn't supported by the current architecture, skip it. */
546  if (!(opcode->architecture & current_arch_mask)) {
547  continue;
548  }
549 
550  if ((opcode->match & insn) == opcode->match
551  && (opcode->lose & insn) == 0)
552  {
553  /* Nonzero means that we have found an instruction which has
554  the effect of adding or or'ing the imm13 field to rs1. */
555  int imm_added_to_rs1 = 0;
556  int imm_ored_to_rs1 = 0;
557 
558  /* Nonzero means that we have found a plus sign in the args
559  field of the opcode table. */
560  int found_plus = 0;
561 
562  /* Nonzero means we have an annulled branch. */
563  int is_annulled = 0;
564 
565  /* Do we have an `add' or `or' instruction combining an
566  immediate with rs1? */
567  if (opcode->match == 0x80102000) { /* or */
568  imm_ored_to_rs1 = 1;
569  }
570  if (opcode->match == 0x80002000) { /* add */
571  imm_added_to_rs1 = 1;
572  }
573 
574  if (X_RS1 (insn) != X_RD (insn) && strchr (opcode->args, 'r') != 0) {
575  /* Can't do simple format if source and dest are different. */
576  continue;
577  }
578  if (X_RS2 (insn) != X_RD (insn) && strchr (opcode->args, 'O') != 0) {
579  /* Can't do simple format if source and dest are different. */
580  continue;
581  }
582 
583  (*info->fprintf_func) (stream, "%s", opcode->name);
584 
585  {
586  const char *s;
587  int brackets = 0;
588 
589  for (s = opcode->args; *s != '\0'; s++)
590  {
591  while (*s == ',')
592  {
593  (*info->fprintf_func) (stream, ",");
594  ++s;
595  switch (*s)
596  {
597  case 'a':
598  (*info->fprintf_func) (stream, "a");
599  is_annulled = 1;
600  ++s;
601  continue;
602  case 'N':
603  (*info->fprintf_func) (stream, "pn");
604  ++s;
605  continue;
606 
607  case 'T':
608  (*info->fprintf_func) (stream, "pt");
609  ++s;
610  continue;
611 
612  default:
613  break;
614  }
615  }
616 
617  if (*s != '[' && !brackets) {
618  (*info->fprintf_func) (stream, " ");
619  } else if (*s == ']') {
620  (*info->fprintf_func) (stream, "%c", *s);
621  brackets = 0;
622  continue;
623  } else if (*s == '[') {
624  (*info->fprintf_func) (stream, " %c", *s);
625  brackets = 1;
626  continue;
627  }
628 
629  switch (*s)
630  {
631  case '+':
632  found_plus = 1;
633  /* Fall through. */
634 
635  default:
636  (*info->fprintf_func) (stream, "%c", *s);
637  break;
638 
639  case '#':
640  (*info->fprintf_func) (stream, "0");
641  break;
642 
643 #define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n])
644  case '1':
645  case 'r':
646  reg (X_RS1 (insn));
647  break;
648 
649  case '2':
650  case 'O':
651  reg (X_RS2 (insn));
652  break;
653 
654  case 'd':
655  reg (X_RD (insn));
656  break;
657 #undef reg
658 
659 #define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n])
660 #define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)])
661  case 'e':
662  freg (X_RS1 (insn));
663  break;
664  case 'v': /* Double/even. */
665  case 'V': /* Quad/multiple of 4. */
666  fregx (X_RS1 (insn));
667  break;
668 
669  case 'f':
670  freg (X_RS2 (insn));
671  break;
672  case 'B': /* Double/even. */
673  case 'R': /* Quad/multiple of 4. */
674  fregx (X_RS2 (insn));
675  break;
676 
677  case 'g':
678  freg (X_RD (insn));
679  break;
680  case 'H': /* Double/even. */
681  case 'J': /* Quad/multiple of 4. */
682  fregx (X_RD (insn));
683  break;
684 #undef freg
685 #undef fregx
686 
687 #define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n))
688  case 'b':
689  creg (X_RS1 (insn));
690  break;
691 
692  case 'c':
693  creg (X_RS2 (insn));
694  break;
695 
696  case 'D':
697  creg (X_RD (insn));
698  break;
699 #undef creg
700 
701  case 'h':
702  (*info->fprintf_func) (stream, "%%hi(%#x)",
703  ((unsigned) 0xFFFFFFFF
704  & ((int) X_IMM22 (insn) << 10)));
705  break;
706 
707  case 'i': /* 13 bit immediate. */
708  case 'I': /* 11 bit immediate. */
709  case 'j': /* 10 bit immediate. */
710  {
711  int imm;
712 
713  if (*s == 'i') {
714  imm = X_SIMM (insn, 13);
715  } else if (*s == 'I') {
716  imm = X_SIMM (insn, 11);
717  } else {
718  imm = X_SIMM (insn, 10);
719  }
720 
721  /* Check to see whether we have a 1+i, and take
722  note of that fact.
723 
724  Note: because of the way we sort the table,
725  we will be matching 1+i rather than i+1,
726  so it is OK to assume that i is after +,
727  not before it. */
728  if (found_plus) {
729  imm_added_to_rs1 = 1;
730  }
731 
732  if (imm <= 9) {
733  (*info->fprintf_func) (stream, "%d", imm);
734  } else {
735  (*info->fprintf_func) (stream, "%#x", imm);
736  }
737  }
738  break;
739 
740  case 'X': /* 5 bit unsigned immediate. */
741  case 'Y': /* 6 bit unsigned immediate. */
742  {
743  int imm = X_IMM (insn, *s == 'X' ? 5 : 6);
744 
745  if (imm <= 9) {
746  (info->fprintf_func) (stream, "%d", imm);
747  } else {
748  (info->fprintf_func) (stream, "%#x", (unsigned)imm);
749  }
750  }
751  break;
752 
753  case '3':
754  (info->fprintf_func) (stream, "%ld", X_IMM (insn, 3));
755  break;
756 
757  case 'K':
758  {
759  int mask = X_MEMBAR (insn);
760  int bit = 0x40, printed_one = 0;
761  const char *name;
762 
763  if (mask == 0) {
764  (info->fprintf_func) (stream, "0");
765  } else {
766  while (bit) {
767  if (mask & bit) {
768  if (printed_one) {
769  (info->fprintf_func) (stream, "|");
770  }
771  name = sparc_decode_membar (bit);
772  (info->fprintf_func) (stream, "%s", name);
773  printed_one = 1;
774  }
775  bit >>= 1;
776  }
777  }
778  break;
779  }
780 
781  case 'k':
782  info->target = memaddr + SIGN_EXT (X_DISP16 (insn), 16) * 4;
783  (*info->print_address_func) (info->target, info);
784  break;
785 
786  case 'G':
787  info->target = memaddr + SIGN_EXT (X_DISP19 (insn), 19) * 4;
788  (*info->print_address_func) (info->target, info);
789  break;
790 
791  case '6':
792  case '7':
793  case '8':
794  case '9':
795  (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0');
796  break;
797 
798  case 'z':
799  (*info->fprintf_func) (stream, "%%icc");
800  break;
801 
802  case 'Z':
803  (*info->fprintf_func) (stream, "%%xcc");
804  break;
805 
806  case 'E':
807  (*info->fprintf_func) (stream, "%%ccr");
808  break;
809 
810  case 's':
811  (*info->fprintf_func) (stream, "%%fprs");
812  break;
813 
814  case 'o':
815  (*info->fprintf_func) (stream, "%%asi");
816  break;
817 
818  case 'W':
819  (*info->fprintf_func) (stream, "%%tick");
820  break;
821 
822  case 'P':
823  (*info->fprintf_func) (stream, "%%pc");
824  break;
825 
826  case '?':
827  if (X_RS1 (insn) == 31) {
828  (*info->fprintf_func) (stream, "%%ver");
829  } else if ((unsigned)X_RS1 (insn) < 17) {
830  (*info->fprintf_func) (stream, "%%%s",
831  v9_priv_reg_names[X_RS1 (insn)]);
832  } else {
833  (*info->fprintf_func) (stream, "%%reserved");
834  }
835  break;
836 
837  case '!':
838  if ((unsigned)X_RD (insn) < 17) {
839  (*info->fprintf_func) (stream, "%%%s",
840  v9_priv_reg_names[X_RD (insn)]);
841  } else {
842  (*info->fprintf_func) (stream, "%%reserved");
843  }
844  break;
845 
846  case '$':
847  if ((unsigned)X_RS1 (insn) < 32) {
848  (*info->fprintf_func) (stream, "%%%s",
849  v9_hpriv_reg_names[X_RS1 (insn)]);
850  } else {
851  (*info->fprintf_func) (stream, "%%reserved");
852  }
853  break;
854 
855  case '%':
856  if ((unsigned)X_RD (insn) < 32) {
857  (*info->fprintf_func) (stream, "%%%s",
858  v9_hpriv_reg_names[X_RD (insn)]);
859  } else {
860  (*info->fprintf_func) (stream, "%%reserved");
861  }
862  break;
863 
864  case '/':
865  if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25) {
866  (*info->fprintf_func) (stream, "%%reserved");
867  } else {
868  (*info->fprintf_func) (stream, "%%%s",
869  v9a_asr_reg_names[X_RS1 (insn) - 16]);
870  }
871  break;
872 
873  case '_':
874  if (X_RD (insn) < 16 || X_RD (insn) > 25) {
875  (*info->fprintf_func) (stream, "%%reserved");
876  } else {
877  (*info->fprintf_func) (stream, "%%%s",
878  v9a_asr_reg_names[X_RD (insn) - 16]);
879  }
880  break;
881 
882  case '*':
883  {
884  const char *name = sparc_decode_prefetch (X_RD (insn));
885 
886  if (name) {
887  (*info->fprintf_func) (stream, "%s", name);
888  } else {
889  (*info->fprintf_func) (stream, "%ld", X_RD (insn));
890  }
891  break;
892  }
893 
894  case 'M':
895  (*info->fprintf_func) (stream, "%%asr%ld", X_RS1 (insn));
896  break;
897 
898  case 'm':
899  (*info->fprintf_func) (stream, "%%asr%ld", X_RD (insn));
900  break;
901 
902  case 'L':
903  info->target = memaddr + SIGN_EXT (X_DISP30 (insn), 30) * 4;
904  (*info->print_address_func) (info->target, info);
905  break;
906 
907  case 'n':
908  (*info->fprintf_func)
909  (stream, "%#x", SIGN_EXT (X_DISP22 (insn), 22));
910  break;
911 
912  case 'l':
913  info->target = memaddr + SIGN_EXT (X_DISP22 (insn), 22) * 4;
914  (*info->print_address_func) (info->target, info);
915  break;
916 
917  case 'A':
918  {
919  const char *name = sparc_decode_asi (X_ASI (insn));
920 
921  if (name) {
922  (*info->fprintf_func) (stream, "%s", name);
923  } else {
924  (*info->fprintf_func) (stream, "(%ld)", X_ASI (insn));
925  }
926  break;
927  }
928 
929  case 'C':
930  (*info->fprintf_func) (stream, "%%csr");
931  break;
932 
933  case 'F':
934  (*info->fprintf_func) (stream, "%%fsr");
935  break;
936 
937  case 'p':
938  (*info->fprintf_func) (stream, "%%psr");
939  break;
940 
941  case 'q':
942  (*info->fprintf_func) (stream, "%%fq");
943  break;
944 
945  case 'Q':
946  (*info->fprintf_func) (stream, "%%cq");
947  break;
948 
949  case 't':
950  (*info->fprintf_func) (stream, "%%tbr");
951  break;
952 
953  case 'w':
954  (*info->fprintf_func) (stream, "%%wim");
955  break;
956 
957  case 'x':
958  (*info->fprintf_func) (stream, "%ld",
959  ((X_LDST_I (insn) << 8)
960  + X_ASI (insn)));
961  break;
962 
963  case 'y':
964  (*info->fprintf_func) (stream, "%%y");
965  break;
966 
967  case 'u':
968  case 'U':
969  {
970  int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn);
971  const char *name = sparc_decode_sparclet_cpreg (val);
972 
973  if (name) {
974  (*info->fprintf_func) (stream, "%s", name);
975  } else {
976  (*info->fprintf_func) (stream, "%%cpreg(%d)", val);
977  }
978  break;
979  }
980  }
981  }
982  }
983 
984  /* If we are adding or or'ing something to rs1, then
985  check to see whether the previous instruction was
986  a sethi to the same register as in the sethi.
987  If so, attempt to print the result of the add or
988  or (in this context add and or do the same thing)
989  and its symbolic value. */
990  if (imm_ored_to_rs1 || imm_added_to_rs1)
991  {
992  unsigned long prev_insn;
993  int errcode;
994 
995  if (memaddr >= 4) {
996  errcode =
997  (*info->read_memory_func) (memaddr - 4, buffer, sizeof (buffer), info);
998  } else {
999  errcode = 1;
1000  }
1001 
1002  prev_insn = getword (buffer);
1003 
1004  if (errcode == 0)
1005  {
1006  /* If it is a delayed branch, we need to look at the
1007  instruction before the delayed branch. This handles
1008  sequences such as:
1009 
1010  sethi %o1, %hi(_foo), %o1
1011  call _printf
1012  or %o1, %lo(_foo), %o1 */
1013 
1014  if (is_delayed_branch (prev_insn))
1015  {
1016  if (memaddr >= 8) {
1017  errcode = (*info->read_memory_func) (memaddr - 8, buffer, sizeof (buffer), info);
1018  } else {
1019  errcode = 1;
1020  }
1021 
1022  prev_insn = getword (buffer);
1023  }
1024  }
1025 
1026  /* If there was a problem reading memory, then assume
1027  the previous instruction was not sethi. */
1028  if (errcode == 0)
1029  {
1030  /* Is it sethi to the same register? */
1031  if ((prev_insn & 0xc1c00000) == 0x01000000
1032  && X_RD (prev_insn) == X_RS1 (insn))
1033  {
1034  (*info->fprintf_func) (stream, "\t! ");
1035  info->target =
1036  ((unsigned) 0xFFFFFFFF
1037  & ((int) X_IMM22 (prev_insn) << 10));
1038  if (imm_added_to_rs1) {
1039  info->target += X_SIMM (insn, 13);
1040  } else {
1041  info->target |= X_SIMM (insn, 13);
1042  }
1043  (*info->print_address_func) (info->target, info);
1044  info->insn_type = dis_dref;
1045  info->data_size = 4; /* FIXME!!! */
1046  }
1047  }
1048  }
1049 
1050  if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
1051  {
1052  /* FIXME -- check is_annulled flag. */
1053  (void) is_annulled;
1054  if (opcode->flags & F_UNBR) {
1055  info->insn_type = dis_branch;
1056  }
1057  if (opcode->flags & F_CONDBR) {
1058  info->insn_type = dis_condbranch;
1059  }
1060  if (opcode->flags & F_JSR) {
1061  info->insn_type = dis_jsr;
1062  }
1063  if (opcode->flags & F_DELAYED) {
1064  info->branch_delay_insns = 1;
1065  }
1066  }
1067 
1068  return sizeof (buffer);
1069  }
1070  }
1071 
1072  info->insn_type = dis_noninsn; /* Mark as non-valid instruction. */
1073  (*info->fprintf_func) (stream, _("unknown"));
1074  return sizeof (buffer);
1075 }
op
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op
Definition: dis.c:32

References _, sparc_opcode::architecture, sparc_opcode::args, BFD_ENDIAN_BIG, bfd_getb32(), bfd_getl32(), bfd_mach_sparc_sparclite, bit, build_hash_table(), compare_opcodes(), compute_arch_mask(), creg, current_arch_mask, dis_branch, dis_condbranch, dis_dref, dis_jsr, dis_nonbranch, dis_noninsn, F_CONDBR, F_DELAYED, F_JSR, F_UNBR, benchmark::FILE, sparc_opcode::flags, freg, fregx, HASH_INSN, i, imm, info(), is_delayed_branch(), sparc_opcode::lose, mask, sparc_opcode::match, name, sparc_opcode::name, op, sparc_opcode_hash::opcode, opcode_hash_table, qsort(), reg, s, SIGN_EXT, sorted_opcodes, sparc_decode_asi(), sparc_decode_membar(), sparc_decode_prefetch(), sparc_decode_sparclet_cpreg(), sparc_num_opcodes, sparc_opcodes, status, unsigned, v9_hpriv_reg_names, v9_priv_reg_names, v9a_asr_reg_names, val, X_ASI, X_DISP16, X_DISP19, X_DISP22, X_DISP30, X_IMM, X_IMM22, X_LDST_I, X_MEMBAR, X_RD, X_RS1, X_RS2, X_SIMM, and xmalloc.

Referenced by disassemble().

◆ print_insn_spu()

int print_insn_spu ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_tic30()

int print_insn_tic30 ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_tic4x()

int print_insn_tic4x ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_tic54x()

int print_insn_tic54x ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_tic6x()

int print_insn_tic6x ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_tic80()

int print_insn_tic80 ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_tilegx()

int print_insn_tilegx ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_tilepro()

int print_insn_tilepro ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_tricore()

int print_insn_tricore ( bfd_vma  memaddr,
struct disassemble_info *  info 
)

Definition at line 1884 of file tricore-dis.c.

1887 {
1888  bfd_byte buffer[4];
1889  int len32 = 0, failure;
1890  unsigned long insn = 0;
1891 
1892  if (!initialized)
1893  {
1894  /* Set the current instruction set architecture. */
1895  switch (info->mach & bfd_mach_rider_mask)
1896  {
1897  case bfd_mach_rider_a:
1898  current_isa = TRICORE_RIDER_A;
1899  break;
1900 
1901  case bfd_mach_rider_b: /* Matches also rider_d! */
1902  current_isa = TRICORE_RIDER_B;
1903  break;
1904 
1905  case bfd_mach_rider_2:
1906  current_isa = TRICORE_V2;
1907  break;
1908  }
1909 
1910  /* Initialize architecture-dependent variables. */
1911  tricore_init_arch_vars (info->mach);
1912 
1913  /* Initialize the hash tables. */
1914  init_hash_tables ();
1915  initialized = 1;
1916  }
1917 
1918  memset ((char *) buffer, 0, sizeof (buffer));
1919  failure = (*info->read_memory_func) (memaddr, buffer, 1, info);
1920  if (failure)
1921  {
1922  (*info->memory_error_func) (failure, memaddr, info);
1923  return -1;
1924  }
1925 
1926  /* Try to read the 2nd byte. */
1927  failure = (*info->read_memory_func) (memaddr + 1, &buffer[1], 1, info);
1928  if (failure)
1929  {
1930  /* Maybe MEMADDR isn't even and we reached the end of a section. */
1931  (*info->fprintf_func) (info->stream, ".byte 0x%02x", buffer[0]);
1932  return 1;
1933  }
1934 
1935  /* Check if we're disassembling .pcp{text,data} sections. */
1936  if (info->section && (info->section->flags & SEC_ARCH_BIT_0)) {
1937  return decode_pcp_insn (memaddr, buffer, info);
1938  }
1939 
1940  /* Handle TriCore sections. */
1941  if (buffer[0] & 1) {
1942  /* Looks like this is a 32-bit insn; try to read 2 more bytes. */
1943  failure = (*info->read_memory_func) (memaddr + 2, &buffer[2], 2, info);
1944  if (failure) {
1945  insn = bfd_getl16 (buffer);
1946  (*info->fprintf_func) (info->stream, ".hword 0x%04lx", insn);
1947  return 2;
1948  } else {
1949  len32 = 1;
1950  }
1951  }
1952 
1953  if (len32) {
1954  insn = bfd_getl32 (buffer);
1955  } else {
1956  insn = bfd_getl16 (buffer);
1957  }
1958 
1959  return decode_tricore_insn (memaddr, insn, len32, info);
1960 }
tricore_init_arch_vars
void tricore_init_arch_vars(unsigned long mach)
Definition: cpu-tricore.c:187
memset
return memset(p, 0, total)
bfd_getl16
static bfd_vma bfd_getl16(const void *p)
Definition: mybfd.h:4969
decode_tricore_insn
static int decode_tricore_insn(bfd_vma memaddr, unsigned long insn, int len32, struct disassemble_info *info)
Definition: tricore-dis.c:1547
current_isa
static tricore_isa current_isa
Definition: tricore-dis.c:100
init_hash_tables
static void init_hash_tables()
Definition: tricore-dis.c:1081
decode_pcp_insn
static int decode_pcp_insn(bfd_vma memaddr, buffer, struct disassemble_info *info)
Definition: tricore-dis.c:1596
initialized
static int initialized
Definition: tricore-dis.c:96
bfd_mach_rider_2
#define bfd_mach_rider_2
Definition: tricore.h:41
TRICORE_RIDER_A
@ TRICORE_RIDER_A
Definition: tricore.h:30
TRICORE_RIDER_B
@ TRICORE_RIDER_B
Definition: tricore.h:31
TRICORE_V2
@ TRICORE_V2
Definition: tricore.h:33
SEC_ARCH_BIT_0
#define SEC_ARCH_BIT_0
Definition: tricore.h:45
bfd_mach_rider_mask
#define bfd_mach_rider_mask
Definition: tricore.h:43
bfd_mach_rider_a
#define bfd_mach_rider_a
Definition: tricore.h:38
bfd_mach_rider_b
#define bfd_mach_rider_b
Definition: tricore.h:39

References bfd_getl16(), bfd_getl32(), bfd_mach_rider_2, bfd_mach_rider_a, bfd_mach_rider_b, bfd_mach_rider_mask, current_isa, decode_pcp_insn(), decode_tricore_insn(), info(), init_hash_tables(), initialized, memset(), SEC_ARCH_BIT_0, tricore_init_arch_vars(), TRICORE_RIDER_A, TRICORE_RIDER_B, and TRICORE_V2.

Referenced by disassemble().

◆ print_insn_v850()

int print_insn_v850 ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_vax()

int print_insn_vax ( bfd_vma  memaddr,
disassemble_info *  info 
)

Definition at line 290 of file vax-dis.c.

290  {
291  // static bfd_boolean parsed_disassembler_options = FALSE;
292  const struct vot *votp;
293  const char *argp;
294  unsigned char *arg;
295  struct private priv;
296  bfd_byte *buffer = priv.the_buffer;
297 
298  info->private_data = &priv;
299  priv.max_fetched = priv.the_buffer;
300  priv.insn_start = memaddr;
301 
302  if (setjmp(priv.bailout) != 0) {
303  /* Error return. */
304  return -1;
305  }
306 
307  argp = NULL;
308  /* Check if the info buffer has more than one byte left since
309  the last opcode might be a single byte with no argument data. */
310  if (info->buffer_length - (memaddr - info->buffer_vma) > 1) {
311  FETCH_DATA(info, buffer + 2);
312  } else {
313  FETCH_DATA(info, buffer + 1);
314  buffer[1] = 0;
315  }
316 
317  for (votp = &votstrs[0]; votp->name[0]; votp++) {
318  vax_opcodeT opcode = votp->detail.code;
319 
320  /* 2 byte codes match 2 buffer pos. */
321  if ((bfd_byte)opcode == buffer[0] && (opcode >> 8 == 0 || opcode >> 8 == buffer[1])) {
322  argp = votp->detail.args;
323  break;
324  }
325  }
326  if (!argp) {
327  /* Handle undefined instructions. */
328  (*info->fprintf_func)(info->stream, ".word 0x%x",
329  (buffer[0] << 8) + buffer[1]);
330  return 2;
331  }
332 
333  /* Point at first byte of argument data, and at descriptor for first
334  argument. */
335  arg = buffer + ((votp->detail.code >> 8) ? 2 : 1);
336 
337  /* Make sure we have it in mem */
338  FETCH_DATA(info, arg);
339 
340  (*info->fprintf_func)(info->stream, "%s", votp->name);
341  if (*argp) {
342  (*info->fprintf_func)(info->stream, " ");
343  }
344 
345  while (*argp) {
346  arg += print_insn_arg(argp, arg, memaddr + arg - buffer, info);
347  argp += 2;
348  if (*argp) {
349  (*info->fprintf_func)(info->stream, ", ");
350  }
351  }
352 
353  return arg - buffer;
354 }
arg
static const char * arg(RzAnalysis *a, csh *handle, cs_insn *insn, char *buf, int n)
Definition: arm_esil32.c:136
argp
static static sync static getppid static getegid const char static filename char argp
Definition: sflib.h:62
vot_wot::args
const char * args
Definition: vax.h:31
vot_wot::code
vax_opcodeT code
Definition: vax.h:32
vot
Definition: vax.h:36
vot::name
const char * name
Definition: vax.h:37
vot::detail
struct vot_wot detail
Definition: vax.h:38
print_insn_arg
static int print_insn_arg(const char *d, unsigned char *p0, bfd_vma addr, disassemble_info *info)
Definition: vax-dis.c:251
FETCH_DATA
#define FETCH_DATA(info, addr)
Definition: vax-dis.c:90
vax_opcodeT
#define vax_opcodeT
Definition: vax.h:25
votstrs
static const struct vot votstrs[]
Definition: vax.h:47

References arg(), argp, vot_wot::args, private::bailout, vot_wot::code, vot::detail, FETCH_DATA, info(), private::insn_start, private::max_fetched, vot::name, NULL, print_insn_arg(), private::the_buffer, vax_opcodeT, and votstrs.

Referenced by disassemble().

◆ print_insn_visium()

int print_insn_visium ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_w65()

int print_insn_w65 ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_xc16x()

int print_insn_xc16x ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_xgate()

int print_insn_xgate ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_xstormy16()

int print_insn_xstormy16 ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_xtensa()

int print_insn_xtensa ( bfd_vma  memaddr,
disassemble_info *  info 
)

Definition at line 158 of file xtensa-dis.c.

159 {
160  unsigned operand_val;
161  int bytes_fetched, size, maxsize, i, n, noperands, nslots;
162  xtensa_isa isa;
163  xtensa_opcode opc;
164  xtensa_format fmt;
165  struct dis_private priv;
166  static bfd_byte *byte_buf = NULL;
167  static xtensa_insnbuf insn_buffer = NULL;
168  static xtensa_insnbuf slot_buffer = NULL;
169  int first, first_slot, valid_insn;
170 
171  if (!xtensa_default_isa) {
172  xtensa_default_isa = xtensa_isa_init (0, 0);
173  }
174 
175  info->target = 0;
176  maxsize = xtensa_isa_maxlength (xtensa_default_isa);
177 
178  /* Set bytes_per_line to control the amount of whitespace between the hex
179  values and the opcode. For Xtensa, we always print one "chunk" and we
180  vary bytes_per_chunk to determine how many bytes to print. (objdump
181  would apparently prefer that we set bytes_per_chunk to 1 and vary
182  bytes_per_line but that makes it hard to fit 64-bit instructions on
183  an 80-column screen.) The value of bytes_per_line here is not exactly
184  right, because objdump adds an extra space for each chunk so that the
185  amount of whitespace depends on the chunk size. Oh well, it's good
186  enough.... Note that we set the minimum size to 4 to accommodate
187  literal pools. */
188  info->bytes_per_line = MAX (maxsize, 4);
189 
190  /* Allocate buffers the first time through. */
191  if (!insn_buffer)
192  {
193  insn_buffer = xtensa_insnbuf_alloc (xtensa_default_isa);
194  slot_buffer = xtensa_insnbuf_alloc (xtensa_default_isa);
195  byte_buf = (bfd_byte *) xmalloc (MAX (maxsize, 4));
196  }
197 
198  priv.byte_buf = byte_buf;
199 
200  info->private_data = (void *) &priv;
201 #if 0
202  if (OPCODES_SIGSETJMP (priv.bailout) != 0)
203  /* Error return. */
204  return -1;
205 #endif
206 
207  /* Don't set "isa" before the setjmp to keep the compiler from griping. */
208  isa = xtensa_default_isa;
209  size = 0;
210  nslots = 0;
211 
212  /* Fetch the maximum size instruction. */
213  bytes_fetched = fetch_data (info, memaddr);
214 
215  /* Copy the bytes into the decode buffer. */
216  memset (insn_buffer, 0, (xtensa_insnbuf_size (isa) *
217  sizeof (xtensa_insnbuf_word)));
218  xtensa_insnbuf_from_chars (isa, insn_buffer, priv.byte_buf, bytes_fetched);
219 
220  fmt = xtensa_format_decode (isa, insn_buffer);
221  if (fmt == XTENSA_UNDEFINED || ((size = xtensa_format_length (isa, fmt)) > bytes_fetched)) {
222  valid_insn = 0;
223  } else {
224  /* Make sure all the opcodes are valid. */
225  valid_insn = 1;
226  nslots = xtensa_format_num_slots (isa, fmt);
227  for (n = 0; n < nslots; n++) {
228  xtensa_format_get_slot (isa, fmt, n, insn_buffer, slot_buffer);
229  if (xtensa_opcode_decode (isa, fmt, n, slot_buffer) == XTENSA_UNDEFINED) {
230  valid_insn = 0;
231  break;
232  }
233  }
234  }
235 
236  if (!valid_insn)
237  {
238  (*info->fprintf_func) (info->stream, ".byte %#02x", priv.byte_buf[0]);
239  return 1;
240  }
241 
242  if (nslots > 1) {
243  (*info->fprintf_func) (info->stream, "{ ");
244  }
245 
246  first_slot = 1;
247  for (n = 0; n < nslots; n++) {
248  if (first_slot) {
249  first_slot = 0;
250  } else {
251  (*info->fprintf_func) (info->stream, "; ");
252  }
253 
254  xtensa_format_get_slot (isa, fmt, n, insn_buffer, slot_buffer);
255  opc = xtensa_opcode_decode (isa, fmt, n, slot_buffer);
256  (*info->fprintf_func) (info->stream, "%s",
257  xtensa_opcode_name (isa, opc));
258 
259  /* Print the operands (if any). */
260  noperands = xtensa_opcode_num_operands (isa, opc);
261  first = 1;
262  for (i = 0; i < noperands; i++) {
263  if (xtensa_operand_is_visible (isa, opc, i) == 0) {
264  continue;
265  }
266  if (first) {
267  (*info->fprintf_func) (info->stream, " ");
268  first = 0;
269  } else {
270  (*info->fprintf_func) (info->stream, ", ");
271  }
272  (void)xtensa_operand_get_field (isa, opc, i, fmt, n,
273  slot_buffer, &operand_val);
274 
275  print_xtensa_operand (memaddr, info, opc, i, operand_val);
276  }
277  }
278 
279  if (nslots > 1) {
280  (*info->fprintf_func) (info->stream, " }");
281  }
282 
283  info->bytes_per_chunk = size;
284  info->display_endian = info->endian;
285 
286  return size;
287 }
xmalloc
#define xmalloc
Definition: disas-asm.h:43
dis_private
Definition: xtensa-dis.c:61
dis_private::byte_buf
bfd_byte * byte_buf
Definition: xtensa-dis.c:62
xtensa_isa_opaque
Definition: xtensa-isa.h:68
print_xtensa_operand
static void print_xtensa_operand(bfd_vma memaddr, struct disassemble_info *info, xtensa_opcode opc, int opnd, unsigned operand_val)
Definition: xtensa-dis.c:95
fetch_data
static int fetch_data(struct disassemble_info *info, bfd_vma memaddr)
Definition: xtensa-dis.c:68
OPCODES_SIGSETJMP
#define OPCODES_SIGSETJMP(buf)
Definition: xtensa-dis.c:49
xtensa_default_isa
xtensa_isa xtensa_default_isa
Definition: elf32-xtensa.c:147
MAX
#define MAX(a, b)
Definition: xtensa-dis.c:40
xtensa_format_get_slot
int xtensa_format_get_slot(xtensa_isa isa, xtensa_format fmt, int slot, const xtensa_insnbuf insn, xtensa_insnbuf slotbuf)
Definition: xtensa-isa.c:629
xtensa_opcode
int xtensa_opcode
Definition: xtensa-isa.h:83
xtensa_format
int xtensa_format
Definition: xtensa-isa.h:84
xtensa_format_num_slots
int xtensa_format_num_slots(xtensa_isa isa, xtensa_format fmt)
Definition: xtensa-isa.c:606
xtensa_insnbuf_word
uint32 xtensa_insnbuf_word
Definition: xtensa-isa.h:178
xtensa_opcode_decode
xtensa_opcode xtensa_opcode_decode(xtensa_isa isa, xtensa_format fmt, int slot, const xtensa_insnbuf slotbuf)
Definition: xtensa-isa.c:708
xtensa_opcode_num_operands
int xtensa_opcode_num_operands(xtensa_isa isa, xtensa_opcode opc)
Definition: xtensa-isa.c:816
xtensa_insnbuf
xtensa_insnbuf_word * xtensa_insnbuf
Definition: xtensa-isa.h:179
xtensa_insnbuf_size
int xtensa_insnbuf_size(xtensa_isa isa)
Definition: xtensa-isa.c:80
xtensa_operand_get_field
int xtensa_operand_get_field(xtensa_isa isa, xtensa_opcode opc, int opnd, xtensa_format fmt, int slot, const xtensa_insnbuf slotbuf, uint32 *valp)
Definition: xtensa-isa.c:975
xtensa_format_length
int xtensa_format_length(xtensa_isa isa, xtensa_format fmt)
Definition: xtensa-isa.c:597
XTENSA_UNDEFINED
#define XTENSA_UNDEFINED
Definition: xtensa-isa.h:93
xtensa_format_decode
xtensa_format xtensa_format_decode(xtensa_isa isa, const xtensa_insnbuf insn)
Definition: xtensa-isa.c:570
xtensa_insnbuf_from_chars
void xtensa_insnbuf_from_chars(xtensa_isa isa, xtensa_insnbuf insn, const unsigned char *cp, int num_chars)
Definition: xtensa-isa.c:196
xtensa_isa_init
xtensa_isa xtensa_isa_init(xtensa_isa_status *errno_p, char **error_msg_p)
Definition: xtensa-isa.c:248
xtensa_operand_is_visible
int xtensa_operand_is_visible(xtensa_isa isa, xtensa_opcode opc, int opnd)
Definition: xtensa-isa.c:924
xtensa_isa_maxlength
int xtensa_isa_maxlength(xtensa_isa isa)
Definition: xtensa-isa.c:405
xtensa_opcode_name
const char * xtensa_opcode_name(xtensa_isa isa, xtensa_opcode opc)
Definition: xtensa-isa.c:759
xtensa_insnbuf_alloc
xtensa_insnbuf xtensa_insnbuf_alloc(xtensa_isa isa)
Definition: xtensa-isa.c:88

References dis_private::bailout, dis_private::byte_buf, fetch_data(), i, info(), MAX, memset(), n, NULL, opc, OPCODES_SIGSETJMP, print_xtensa_operand(), xmalloc, xtensa_default_isa, xtensa_format_decode(), xtensa_format_get_slot(), xtensa_format_length(), xtensa_format_num_slots(), xtensa_insnbuf_alloc(), xtensa_insnbuf_from_chars(), xtensa_insnbuf_size(), xtensa_isa_init(), xtensa_isa_maxlength(), xtensa_opcode_decode(), xtensa_opcode_name(), xtensa_opcode_num_operands(), xtensa_operand_get_field(), xtensa_operand_is_visible(), and XTENSA_UNDEFINED.

Referenced by disassemble().

◆ print_insn_z80()

int print_insn_z80 ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_z8001()

int print_insn_z8001 ( bfd_vma  ,
disassemble_info *   
)

◆ print_insn_z8002()

int print_insn_z8002 ( bfd_vma  ,
disassemble_info *   
)

◆ print_mips_disassembler_options()

void print_mips_disassembler_options ( FILE *  stream)

Definition at line 2110 of file mips-dis.c.

2111 {
2112  unsigned int i;
2113 
2114  fprintf (stream, _("\n\
2115 The following MIPS specific disassembler options are supported for use\n\
2116 with the -M switch (multiple options should be separated by commas):\n"));
2117 
2118  fprintf (stream, _("\n\
2119  gpr-names=ABI Print GPR names according to specified ABI.\n\
2120  Default: based on binary being disassembled.\n"));
2121 
2122  fprintf (stream, _("\n\
2123  fpr-names=ABI Print FPR names according to specified ABI.\n\
2124  Default: numeric.\n"));
2125 
2126  fprintf (stream, _("\n\
2127  cp0-names=ARCH Print CP0 register names according to\n\
2128  specified architecture.\n\
2129  Default: based on binary being disassembled.\n"));
2130 
2131  fprintf (stream, _("\n\
2132  hwr-names=ARCH Print HWR names according to specified \n\
2133  architecture.\n\
2134  Default: based on binary being disassembled.\n"));
2135 
2136  fprintf (stream, _("\n\
2137  reg-names=ABI Print GPR and FPR names according to\n\
2138  specified ABI.\n"));
2139 
2140  fprintf (stream, _("\n\
2141  reg-names=ARCH Print CP0 register and HWR names according to\n\
2142  specified architecture.\n"));
2143 
2144  fprintf (stream, _("\n\
2145  For the options above, the following values are supported for \"ABI\":\n\
2146  "));
2147  for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++) {
2148  fprintf (stream, " %s", mips_abi_choices[i].name);
2149  }
2150  fprintf (stream, _("\n"));
2151 
2152  fprintf (stream, _("\n\
2153  For the options above, The following values are supported for \"ARCH\":\n\
2154  "));
2155  for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++) {
2156  if (*mips_arch_choices[i].name != '\0') {
2157  fprintf (stream, " %s", mips_arch_choices[i].name);
2158  }
2159  }
2160  fprintf (stream, _("\n"));
2161 
2162  fprintf (stream, _("\n"));
2163 }
ARRAY_SIZE
#define ARRAY_SIZE(a)
Definition: analysis_riscv.c:11
mips_arch_choices
const struct mips_arch_choice mips_arch_choices[]
Definition: mips-dis.c:347
mips_abi_choices
struct mips_abi_choice mips_abi_choices[]
Definition: mips-dis.c:326

References _, ARRAY_SIZE, i, mips_abi_choices, and mips_arch_choices.

◆ print_ppc_disassembler_options()

void print_ppc_disassembler_options ( FILE *  )

◆ print_riscv_disassembler_options()

void print_riscv_disassembler_options ( FILE *  )

◆ print_s390_disassembler_options()

void print_s390_disassembler_options ( FILE *  )

◆ remove_whitespace_and_extra_commas()

char* remove_whitespace_and_extra_commas ( char *  )

◆ rl78_get_disassembler()

disassembler_ftype rl78_get_disassembler ( bfd *  )