arc-dis.h File Reference

Go to the source code of this file.

Classes
struct	arcDisState

Macros
#define	__TRANSLATION_REQUIRED(state)   ((state).acnt != 0)

Enumerations
enum	NullifyMode { BR_exec_when_no_jump , BR_exec_always , BR_exec_when_jump }
enum	ARC_Debugger_OperandType {   ARC_UNDEFINED , ARC_LIMM , ARC_SHIMM , ARC_REGISTER ,   ARCOMPACT_REGISTER }
enum	Flow {   noflow , direct_jump , direct_call , indirect_jump ,   indirect_call , invalid_instr }
enum	{ no_reg = 99 }
enum	{ allOperandsSize = 256 }

Functions
int	ARCompact_decodeInstr (bfd_vma address, disassemble_info *info)

Macro Definition Documentation

__TRANSLATION_REQUIRED

#define __TRANSLATION_REQUIRED

(

state

)

((state).acnt != 0)

Definition at line 110 of file arc-dis.h.

Enumeration Type Documentation

anonymous enum

anonymous enum

Enumerator
no_reg

Definition at line 55 of file arc-dis.h.

{ no_reg = 99 };

anonymous enum

anonymous enum

Enumerator
allOperandsSize

Definition at line 56 of file arc-dis.h.

{ allOperandsSize = 256 };

ARC_Debugger_OperandType

enum ARC_Debugger_OperandType

Enumerator
ARC_UNDEFINED
ARC_LIMM
ARC_SHIMM
ARC_REGISTER
ARCOMPACT_REGISTER

Definition at line 34 of file arc-dis.h.

{
    ARC_UNDEFINED,
    ARC_LIMM,
    ARC_SHIMM,
    ARC_REGISTER,
    ARCOMPACT_REGISTER /* Valid only for the
                          registers allowed in
                          16 bit mode */
};

Flow

enum Flow

Enumerator
noflow
direct_jump
direct_call
indirect_jump
indirect_call
invalid_instr

Definition at line 45 of file arc-dis.h.

{
  noflow,
  direct_jump,
  direct_call,
  indirect_jump,
  indirect_call,
  invalid_instr
};

NullifyMode

enum NullifyMode

Enumerator
BR_exec_when_no_jump
BR_exec_always
BR_exec_when_jump

Definition at line 27 of file arc-dis.h.

{
  BR_exec_when_no_jump,
  BR_exec_always,
  BR_exec_when_jump
};

Function Documentation

ARCompact_decodeInstr()

int ARCompact_decodeInstr	(	bfd_vma	address,
		disassemble_info *	info
	)

Definition at line 3722 of file arcompact-dis.c.

                            {
    int status;
    bfd_byte buffer[4];
    struct arcDisState s; /* ARC Disassembler state */
    void *stream = info->stream; /* output stream */
    fprintf_ftype func = info->fprintf_func;
    int bytes;
    int lowbyte, highbyte;
    char buf[256];
 
    if (info->disassembler_options) {
        parse_disassembler_options(info->disassembler_options);
 
        /* To avoid repeated parsing of these options, we remove them here.  */
        info->disassembler_options = NULL;
    }
 
    lowbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 1 : 0);
    highbyte = ((info->endian == BFD_ENDIAN_LITTLE) ? 0 : 1);
 
    memset(&s, 0, sizeof(struct arcDisState));
 
    /* read first instruction */
    status = (*info->read_memory_func)(address, buffer, 2, info);
 
    if (status != 0) {
        (*info->memory_error_func)(status, address, info);
        return -1;
    }
 
    if (((buffer[lowbyte] & 0xf8) > 0x38) && ((buffer[lowbyte] & 0xf8) != 0x48)) {
        s.instructionLen = 2;
        s.words[0] = (buffer[lowbyte] << 8) | buffer[highbyte];
        (*info->read_memory_func)(address + 2, buffer, 4, info);
        if (info->endian == BFD_ENDIAN_LITTLE) {
            s.words[1] = bfd_getl32(buffer);
        } else {
            s.words[1] = bfd_getb32(buffer);
        }
    } else {
        s.instructionLen = 4;
        status = (*info->read_memory_func)(address + 2, &buffer[2], 2, info);
        if (status != 0) {
            (*info->memory_error_func)(status, address + 2, info);
            return -1;
        }
        if (info->endian == BFD_ENDIAN_LITTLE) {
            s.words[0] = bfd_getl32(buffer);
        } else {
            s.words[0] = bfd_getb32(buffer);
        }
 
        /* always read second word in case of limm */
        /* we ignore the result since last insn may not have a limm */
        (*info->read_memory_func)(address + 4, buffer, 4, info);
        if (info->endian == BFD_ENDIAN_LITTLE) {
            s.words[1] = bfd_getl32(buffer);
        } else {
            s.words[1] = bfd_getb32(buffer);
        }
    }
 
    s._this = &s;
    s.coreRegName = _coreRegName;
    s.auxRegName = _auxRegName;
    s.condCodeName = _condCodeName;
    s.instName = _instName;
 
    /* disassemble */
    bytes = dsmOneArcInst(address, (void *)&s, info);
 
    /* display the disassembled instruction */
    {
        char *instr = s.instrBuffer;
        char *operand = s.operandBuffer;
        char *space = strchr(instr, ' ');
 
        if (enable_insn_stream) {
            /* Show instruction stream from MSB to LSB*/
 
            if (s.instructionLen == 2) {
                (*func)(stream, "    %04x ", (unsigned int)s.words[0]);
            } else {
                (*func)(stream, "%08x ", (unsigned int)s.words[0]);
            }
 
            (*func)(stream, "    ");
        }
 
        /* if the operand is actually in the instruction buffer */
        if ((space != NULL) && (operand[0] == '\0')) {
            *space = '\0';
            operand = space + 1;
        }
 
        (*func)(stream, "%s ", instr);
 
        if (__TRANSLATION_REQUIRED(s)) {
            bfd_vma addr;
            char *tmpBuffer;
            int i = 1;
 
            if (operand[0] != '@') {
                /* Branch instruction with 3 operands, Translation is required
                   only for the third operand. Print the first 2 operands */
                strncpy(buf, operand, sizeof(buf));
                buf[sizeof(buf) - 1] = '\0';
                tmpBuffer = strtok(buf, "@");
                (*func)(stream, "%s", tmpBuffer);
                i = strlen(tmpBuffer) + 1;
            }
 
            addr = s.addresses[operand[i] - '0'];
            (*info->print_address_func)((bfd_vma)addr, info);
            //(*func) (stream, "\n");
        } else {
            (*func)(stream, "%s", operand);
        }
    }
 
    /* We print max bytes for instruction */
    info->bytes_per_line = 8;
 
    return bytes; // s.instructionLen;
}