#include "sysdep.h"
#include <assert.h>
#include <stdlib.h>
#include <stdio.h>
#include <stdint.h>
#include <stdarg.h>
#include <inttypes.h>
#include "opintl.h"
#include "libiberty.h"
#include "aarch64-opc.h"
#include "aarch64-tbl.h"

Classes
struct	operand_qualifier_data

struct	simd_imm_encoding

union	double_conv_t

union	single_conv_t

union	half_conv_t

Macros
#define	B(op, l, t) (((op) << 3) \| (((l) - 1) << 1) \| (t))

#define	TOTAL_IMM_NB 5334

#define	BANK(R, FOR31)

#define	R32(X) "w" #X

#define	R64(X) "x" #X

#define	ZS(X) "z" #X ".s"

#define	ZD(X) "z" #X ".d"

#define	CPENC(op0, op1, crn, crm, op2) ((((op0) << 19) \| ((op1) << 16) \| ((crn) << 12) \| ((crm) << 8) \| ((op2) << 5)) >> 5)

#define	CPEN_(op1, crm, op2) CPENC(3,(op1),4,(crm),(op2))

#define	CPENS(op1, crn, crm, op2) CPENC(1,(op1),(crn),(crm),(op2))

#define	C0 0

#define	C1 1

#define	C2 2

#define	C3 3

#define	C4 4

#define	C5 5

#define	C6 6

#define	C7 7

#define	C8 8

#define	C9 9

#define	C10 10

#define	C11 11

#define	C12 12

#define	C13 13

#define	C14 14

#define	C15 15

#define	BIT(INSN, BT) (((INSN) >> (BT)) & 1)

#define	BITS(INSN, HI, LO) (((INSN) >> (LO)) & ((1 << (((HI) - (LO)) + 1)) - 1))

#define	VERIFIER(x) verify_##x

Enumerations
enum	data_pattern { DP_UNKNOWN , DP_VECTOR_3SAME , DP_VECTOR_LONG , DP_VECTOR_WIDE , DP_VECTOR_ACROSS_LANES }

enum	operand_qualifier_kind { OQK_NIL , OQK_OPD_VARIANT , OQK_VALUE_IN_RANGE , OQK_MISC }

Functions
static bfd_boolean	vector_qualifier_p (enum aarch64_opnd_qualifier qualifier)

static bfd_boolean	fp_qualifier_p (enum aarch64_opnd_qualifier qualifier)

static enum data_pattern	get_data_pattern (const aarch64_opnd_qualifier_seq_t qualifiers)

int	aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *opcode)

enum aarch64_operand_class	aarch64_get_operand_class (enum aarch64_opnd type)

const char *	aarch64_get_operand_name (enum aarch64_opnd type)

const char *	aarch64_get_operand_desc (enum aarch64_opnd type)

const aarch64_cond *	get_cond_from_value (aarch64_insn value)

const aarch64_cond *	get_inverted_cond (const aarch64_cond *cond)

enum aarch64_modifier_kind	aarch64_get_operand_modifier (const struct aarch64_name_value_pair *desc)

aarch64_insn	aarch64_get_operand_modifier_value (enum aarch64_modifier_kind kind)

enum aarch64_modifier_kind	aarch64_get_operand_modifier_from_value (aarch64_insn value, bfd_boolean extend_p)

bfd_boolean	aarch64_extend_operator_p (enum aarch64_modifier_kind kind)

static bfd_boolean	aarch64_shift_operator_p (enum aarch64_modifier_kind kind)

static int	value_in_range_p (int64_t value, int low, int high)

static int	value_aligned_p (int64_t value, int align)

static int	value_fit_signed_field_p (int64_t value, unsigned width)

static int	value_fit_unsigned_field_p (int64_t value, unsigned width)

int	aarch64_stack_pointer_p (const aarch64_opnd_info *operand)

int	aarch64_zero_register_p (const aarch64_opnd_info *operand)

static int	operand_also_qualified_p (const struct aarch64_opnd_info *operand, aarch64_opnd_qualifier_t target)

aarch64_opnd_qualifier_t	aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *qseq_list, int idx, const aarch64_opnd_qualifier_t known_qlf, int known_idx)

static bfd_boolean	operand_variant_qualifier_p (aarch64_opnd_qualifier_t qualifier)

static bfd_boolean	qualifier_value_in_range_constraint_p (aarch64_opnd_qualifier_t qualifier)

const char *	aarch64_get_qualifier_name (aarch64_opnd_qualifier_t qualifier)

unsigned char	aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t qualifier)

unsigned char	aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t qualifier)

aarch64_insn	aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t qualifier)

static int	get_lower_bound (aarch64_opnd_qualifier_t qualifier)

static int	get_upper_bound (aarch64_opnd_qualifier_t qualifier)

int	aarch64_num_of_operands (const aarch64_opcode *opcode)

int	aarch64_find_best_match (const aarch64_inst inst, const aarch64_opnd_qualifier_seq_t qualifiers_list, int stop_at, aarch64_opnd_qualifier_t *ret)

static int	match_operands_qualifier (aarch64_inst *inst, bfd_boolean update_p)

bfd_boolean	aarch64_wide_constant_p (int64_t value, int is32, unsigned int *shift_amount)

static int	simd_imm_encoding_cmp (const void i1, const void i2)

static int	encode_immediate_bitfield (int is64, uint32_t s, uint32_t r)

static void	build_immediate_table (void)

bfd_boolean	aarch64_logical_immediate_p (uint64_t value, int esize, aarch64_insn *encoding)

int	aarch64_shrink_expanded_imm8 (uint64_t imm)

static void	set_error (aarch64_operand_error mismatch_detail, enum aarch64_operand_error_kind kind, int idx, const char error)

static void	set_syntax_error (aarch64_operand_error mismatch_detail, int idx, const char error)

static void	set_out_of_range_error (aarch64_operand_error mismatch_detail, int idx, int lower_bound, int upper_bound, const char error)

static void	set_imm_out_of_range_error (aarch64_operand_error *mismatch_detail, int idx, int lower_bound, int upper_bound)

static void	set_offset_out_of_range_error (aarch64_operand_error *mismatch_detail, int idx, int lower_bound, int upper_bound)

static void	set_regno_out_of_range_error (aarch64_operand_error *mismatch_detail, int idx, int lower_bound, int upper_bound)

static void	set_elem_idx_out_of_range_error (aarch64_operand_error *mismatch_detail, int idx, int lower_bound, int upper_bound)

static void	set_sft_amount_out_of_range_error (aarch64_operand_error *mismatch_detail, int idx, int lower_bound, int upper_bound)

static void	set_multiplier_out_of_range_error (aarch64_operand_error *mismatch_detail, int idx, int lower_bound, int upper_bound)

static void	set_unaligned_error (aarch64_operand_error *mismatch_detail, int idx, int alignment)

static void	set_reg_list_error (aarch64_operand_error *mismatch_detail, int idx, int expected_num)

static void	set_other_error (aarch64_operand_error mismatch_detail, int idx, const char error)

static int	operand_general_constraint_met_p (const aarch64_opnd_info opnds, int idx, enum aarch64_opnd type, const aarch64_opcode opcode, aarch64_operand_error *mismatch_detail)

int	aarch64_match_operands_constraint (aarch64_inst inst, aarch64_operand_error mismatch_detail)

const aarch64_opcode *	aarch64_replace_opcode (aarch64_inst inst, const aarch64_opcode opcode)

int	aarch64_operand_index (const enum aarch64_opnd *operands, enum aarch64_opnd operand)

static const char *	get_int_reg_name (int regno, aarch64_opnd_qualifier_t qualifier, int sp_reg_p)

static const char *	get_64bit_int_reg_name (int regno, int sp_reg_p)

static const char *	get_offset_int_reg_name (const aarch64_opnd_info *opnd)

static const char *	get_addr_sve_reg_name (int regno, aarch64_opnd_qualifier_t qualifier)

static uint64_t	expand_fp_imm (int size, uint32_t imm8)

static void	print_register_list (char buf, size_t size, const aarch64_opnd_info opnd, const char *prefix)

static void	print_immediate_offset_address (char buf, size_t size, const aarch64_opnd_info opnd, const char *base)

static void	print_register_offset_address (char buf, size_t size, const aarch64_opnd_info opnd, const char base, const char offset)

void	aarch64_print_operand (char buf, size_t size, bfd_vma pc, const aarch64_opcode opcode, const aarch64_opnd_info opnds, int idx, int pcrel_p, bfd_vma address, char *notes ATTRIBUTE_UNUSED)

bfd_boolean	aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *reg)

bfd_boolean	aarch64_sys_reg_supported_p (const aarch64_feature_set features, const aarch64_sys_reg *reg)

bfd_boolean	aarch64_pstatefield_supported_p (const aarch64_feature_set features, const aarch64_sys_reg *reg)

bfd_boolean	aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *sys_ins_reg)

bfd_boolean	aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features, const aarch64_sys_ins_reg *reg)

static bfd_boolean	verify_ldpsw (const struct aarch64_opcode *opcode ATTRIBUTE_UNUSED, const aarch64_insn insn)

bfd_boolean	aarch64_sve_dupm_mov_immediate_p (uint64_t uvalue, int esize)

Variables
const char *const	aarch64_sve_pattern_array [32]

const char *const	aarch64_sve_prfop_array [16]

static const char	significant_operand_index []

const aarch64_field	fields []

const aarch64_cond	aarch64_conds [16]

const struct aarch64_name_value_pair	aarch64_operand_modifiers []

const struct aarch64_name_value_pair	aarch64_barrier_options [16]

const struct aarch64_name_value_pair	aarch64_hint_options []

const struct aarch64_name_value_pair	aarch64_prfops [32]

struct operand_qualifier_data	aarch64_opnd_qualifiers []

static simd_imm_encoding	simd_immediates [TOTAL_IMM_NB]

static const char *	int_reg [2][2][32]

static const char *	sve_reg [2][32]

const aarch64_sys_reg	aarch64_sys_regs []

const aarch64_sys_reg	aarch64_pstatefields []

const aarch64_sys_ins_reg	aarch64_sys_regs_ic []

const aarch64_sys_ins_reg	aarch64_sys_regs_dc []

const aarch64_sys_ins_reg	aarch64_sys_regs_at []

const aarch64_sys_ins_reg	aarch64_sys_regs_tlbi []

Macro Definition Documentation

◆ B

#define B	(	op,
		l,
		t
	)	(((op) << 3) \| (((l) - 1) << 1) \| (t))

Definition at line 479 of file aarch64-opc.c.

◆ BANK

#define BANK	(	R,
		FOR31
	)

Value:

  { R  (0), R  (1), R  (2), R  (3), R  (4), R  (5), R  (6), R  (7), \
    R  (8), R  (9), R (10), R (11), R (12), R (13), R (14), R (15), \
    R (16), R (17), R (18), R (19), R (20), R (21), R (22), R (23), \
    R (24), R (25), R (26), R (27), R (28), R (29), R (30),  FOR31 }

Definition at line 2748 of file aarch64-opc.c.

◆ BIT

#define BIT	(	INSN,
		BT
	)	(((INSN) >> (BT)) & 1)

Definition at line 4488 of file aarch64-opc.c.

◆ BITS

#define BITS	(	INSN,
		HI,
		LO
	)	(((INSN) >> (LO)) & ((1 << (((HI) - (LO)) + 1)) - 1))

Definition at line 4489 of file aarch64-opc.c.

◆ C0

#define C0 0

Definition at line 3654 of file aarch64-opc.c.

◆ C1

#define C1 1

Definition at line 3655 of file aarch64-opc.c.

◆ C10

#define C10 10

Definition at line 3664 of file aarch64-opc.c.

◆ C11

#define C11 11

Definition at line 3665 of file aarch64-opc.c.

◆ C12

#define C12 12

Definition at line 3666 of file aarch64-opc.c.

◆ C13

#define C13 13

Definition at line 3667 of file aarch64-opc.c.

◆ C14

#define C14 14

Definition at line 3668 of file aarch64-opc.c.

◆ C15

#define C15 15

Definition at line 3669 of file aarch64-opc.c.

◆ C2

#define C2 2

Definition at line 3656 of file aarch64-opc.c.

◆ C3

#define C3 3

Definition at line 3657 of file aarch64-opc.c.

◆ C4

#define C4 4

Definition at line 3658 of file aarch64-opc.c.

◆ C5

#define C5 5

Definition at line 3659 of file aarch64-opc.c.

◆ C6

#define C6 6

Definition at line 3660 of file aarch64-opc.c.

◆ C7

#define C7 7

Definition at line 3661 of file aarch64-opc.c.

◆ C8

#define C8 8

Definition at line 3662 of file aarch64-opc.c.

◆ C9

#define C9 9

Definition at line 3663 of file aarch64-opc.c.

◆ CPEN_

#define CPEN_	(	op1,
		crm,
		op2
	)	CPENC(3,(op1),4,(crm),(op2))

Definition at line 3650 of file aarch64-opc.c.

◆ CPENC

#define CPENC	(	op0,
		op1,
		crn,
		crm,
		op2
	)	((((op0) << 19) \| ((op1) << 16) \| ((crn) << 12) \| ((crm) << 8) \| ((op2) << 5)) >> 5)

Definition at line 3647 of file aarch64-opc.c.

◆ CPENS

#define CPENS	(	op1,
		crn,
		crm,
		op2
	)	CPENC(1,(op1),(crn),(crm),(op2))

Definition at line 3652 of file aarch64-opc.c.

◆ R32

#define R32 ( X ) "w" #X

◆ R64

#define R64 ( X ) "x" #X

◆ TOTAL_IMM_NB

#define TOTAL_IMM_NB 5334

Definition at line 1095 of file aarch64-opc.c.

◆ VERIFIER

#define VERIFIER ( x ) verify_##x

Definition at line 4545 of file aarch64-opc.c.

◆ ZD

#define ZD ( X ) "z" #X ".d"

◆ ZS

#define ZS ( X ) "z" #X ".s"

Enumeration Type Documentation

◆ data_pattern

enum data_pattern

Enumerator
DP_UNKNOWN
DP_VECTOR_3SAME
DP_VECTOR_LONG
DP_VECTOR_WIDE
DP_VECTOR_ACROSS_LANES

Definition at line 124 of file aarch64-opc.c.

 {
   DP_UNKNOWN,
   DP_VECTOR_3SAME,
   DP_VECTOR_LONG,
   DP_VECTOR_WIDE,
   DP_VECTOR_ACROSS_LANES,
 };

◆ operand_qualifier_kind

enum operand_qualifier_kind

Enumerator
OQK_NIL
OQK_OPD_VARIANT
OQK_VALUE_IN_RANGE
OQK_MISC

Definition at line 664 of file aarch64-opc.c.

 {
   OQK_NIL,
   OQK_OPD_VARIANT,
   OQK_VALUE_IN_RANGE,
   OQK_MISC,
 };

Function Documentation

◆ aarch64_extend_operator_p()

bfd_boolean aarch64_extend_operator_p ( enum aarch64_modifier_kind kind )

Definition at line 430 of file aarch64-opc.c.

 {
   return (kind > AARCH64_MOD_LSL && kind <= AARCH64_MOD_SXTX)
     ? TRUE : FALSE;
 }

References AARCH64_MOD_LSL, AARCH64_MOD_SXTX, FALSE, and TRUE.

Referenced by operand_general_constraint_met_p().

◆ aarch64_find_best_match()

int aarch64_find_best_match	(	const aarch64_inst *	inst,
		const aarch64_opnd_qualifier_seq_t *	qualifiers_list,
		int	stop_at,
		aarch64_opnd_qualifier_t *	ret
	)

Definition at line 876 of file aarch64-opc.c.

 {
   int found = 0;
   int i, num_opnds;
   const aarch64_opnd_qualifier_t *qualifiers;
  
   num_opnds = aarch64_num_of_operands (inst->opcode);
   if (num_opnds == 0)
     {
       DEBUG_TRACE ("SUCCEED: no operand");
       return 1;
     }
  
   if (stop_at < 0 || stop_at >= num_opnds)
     stop_at = num_opnds - 1;
  
   /* For each pattern.  */
   for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
     {
       int j;
       qualifiers = *qualifiers_list;
  
       /* Start as positive.  */
       found = 1;
  
       DEBUG_TRACE ("%d", i);
 #ifdef DEBUG_AARCH64
       if (debug_dump)
     dump_match_qualifiers (inst->operands, qualifiers);
 #endif
  
       /* Most opcodes has much fewer patterns in the list.
      First NIL qualifier indicates the end in the list.   */
       if (empty_qualifier_sequence_p (qualifiers) == TRUE)
     {
       DEBUG_TRACE_IF (i == 0, "SUCCEED: empty qualifier list");
       if (i)
         found = 0;
       break;
     }
  
       for (j = 0; j < num_opnds && j <= stop_at; ++j, ++qualifiers)
     {
       if (inst->operands[j].qualifier == AARCH64_OPND_QLF_NIL)
         {
           /* Either the operand does not have qualifier, or the qualifier
          for the operand needs to be deduced from the qualifier
          sequence.
          In the latter case, any constraint checking related with
          the obtained qualifier should be done later in
          operand_general_constraint_met_p.  */
           continue;
         }
       else if (*qualifiers != inst->operands[j].qualifier)
         {
           /* Unless the target qualifier can also qualify the operand
          (which has already had a non-nil qualifier), non-equal
          qualifiers are generally un-matched.  */
           if (operand_also_qualified_p (inst->operands + j, *qualifiers))
         continue;
           else
         {
           found = 0;
           break;
         }
         }
       else
         continue;   /* Equal qualifiers are certainly matched.  */
     }
  
       /* Qualifiers established.  */
       if (found == 1)
     break;
     }
  
   if (found == 1)
     {
       /* Fill the result in *RET.  */
       int j;
       qualifiers = *qualifiers_list;
  
       DEBUG_TRACE ("complete qualifiers using list %d", i);
 #ifdef DEBUG_AARCH64
       if (debug_dump)
     dump_qualifier_sequence (qualifiers);
 #endif
  
       for (j = 0; j <= stop_at; ++j, ++qualifiers)
     ret[j] = *qualifiers;
       for (; j < AARCH64_MAX_OPND_NUM; ++j)
     ret[j] = AARCH64_OPND_QLF_NIL;
  
       DEBUG_TRACE ("SUCCESS");
       return 1;
     }
  
   DEBUG_TRACE ("FAIL");
   return 0;
 }

References AARCH64_MAX_OPND_NUM, AARCH64_MAX_QLF_SEQ_NUM, aarch64_num_of_operands(), AARCH64_OPND_QLF_NIL, DEBUG_TRACE, DEBUG_TRACE_IF, empty_qualifier_sequence_p(), found, i, aarch64_inst::opcode, operand_also_qualified_p(), aarch64_inst::operands, aarch64_opnd_info::qualifier, and TRUE.

Referenced by get_expected_qualifier(), and match_operands_qualifier().

◆ aarch64_get_expected_qualifier()

aarch64_opnd_qualifier_t aarch64_get_expected_qualifier	(	const aarch64_opnd_qualifier_seq_t *	qseq_list,
		int	idx,
		const aarch64_opnd_qualifier_t	known_qlf,
		int	known_idx
	)

Definition at line 621 of file aarch64-opc.c.

 {
   int i, saved_i;
  
   /* Special case.
  
      When the known qualifier is NIL, we have to assume that there is only
      one qualifier sequence in the *QSEQ_LIST and return the corresponding
      qualifier directly.  One scenario is that for instruction
     PRFM <prfop>, [<Xn|SP>, #:lo12:<symbol>]
      which has only one possible valid qualifier sequence
     NIL, S_D
      the caller may pass NIL in KNOWN_QLF to obtain S_D so that it can
      determine the correct relocation type (i.e. LDST64_LO12) for PRFM.
  
      Because the qualifier NIL has dual roles in the qualifier sequence:
      it can mean no qualifier for the operand, or the qualifer sequence is
      not in use (when all qualifiers in the sequence are NILs), we have to
      handle this special case here.  */
   if (known_qlf == AARCH64_OPND_NIL)
     {
       assert (qseq_list[0][known_idx] == AARCH64_OPND_NIL);
       return qseq_list[0][idx];
     }
  
   for (i = 0, saved_i = -1; i < AARCH64_MAX_QLF_SEQ_NUM; i++)
     {
       if (qseq_list[i][known_idx] == known_qlf)
     {
       if (saved_i != -1)
         /* More than one sequences are found to have KNOWN_QLF at
            KNOWN_IDX.  */
         return AARCH64_OPND_NIL;
       saved_i = i;
     }
     }
  
   return qseq_list[saved_i][idx];
 }

References AARCH64_MAX_QLF_SEQ_NUM, AARCH64_OPND_NIL, assert(), i, and setup::idx.

◆ aarch64_get_operand_class()

enum aarch64_operand_class aarch64_get_operand_class ( enum aarch64_opnd type )

Definition at line 205 of file aarch64-opc.c.

 {
   return aarch64_operands[type].op_class;
 }

Referenced by aarch64_ext_regrt_sysins(), aarch64_stack_pointer_p(), aarch64_zero_register_p(), do_special_decoding(), operand_general_constraint_met_p(), select_operand_for_fptype_field_coding(), select_operand_for_scalar_size_field_coding(), and select_operand_for_sf_field_coding().

◆ aarch64_get_operand_desc()

const char* aarch64_get_operand_desc ( enum aarch64_opnd type )

Definition at line 342 of file aarch64-opc.c.

 {
   return aarch64_operands[type].desc;
 }

References aarch64_operands, aarch64_operand::desc, and type.

◆ aarch64_get_operand_modifier()

enum aarch64_modifier_kind aarch64_get_operand_modifier ( const struct aarch64_name_value_pair * desc )

Definition at line 376 of file aarch64-opc.c.

 {
   return desc - aarch64_operand_modifiers;
 }

References aarch64_conds, and cond.

◆ aarch64_get_operand_modifier_from_value()

enum aarch64_modifier_kind aarch64_get_operand_modifier_from_value	(	aarch64_insn	value,
		bfd_boolean	extend_p
	)

Definition at line 414 of file aarch64-opc.c.

 {
   if (extend_p == TRUE)
     return AARCH64_MOD_UXTB + value;
   else
     return AARCH64_MOD_LSL - value;
 }

References aarch64_operand_modifiers, and aarch64_name_value_pair::value.

Referenced by aarch64_ext_addr_regoff(), aarch64_ext_reg_extended(), and aarch64_ext_reg_shifted().

◆ aarch64_get_operand_modifier_value()

aarch64_insn aarch64_get_operand_modifier_value ( enum aarch64_modifier_kind kind )

Definition at line 414 of file aarch64-opc.c.

 {
   return aarch64_operand_modifiers[kind].value;
 }

◆ aarch64_get_operand_name()

const char* aarch64_get_operand_name ( enum aarch64_opnd type )

Definition at line 334 of file aarch64-opc.c.

 {
   return aarch64_operands[type].name;
 }

References aarch64_operands, aarch64_operand::name, and type.

◆ aarch64_get_qualifier_esize()

unsigned char aarch64_get_qualifier_esize ( aarch64_opnd_qualifier_t qualifier )

Definition at line 766 of file aarch64-opc.c.

 {
   assert (operand_variant_qualifier_p (qualifier) == TRUE);
   return aarch64_opnd_qualifiers[qualifier].data0;
 }

References aarch64_opnd_qualifiers, assert(), operand_qualifier_data::data0, operand_variant_qualifier_p(), and TRUE.

Referenced by aarch64_ext_addr_regoff(), aarch64_ext_addr_simm(), aarch64_ext_addr_uimm12(), aarch64_ext_advsimd_imm_modified(), aarch64_ext_limm(), aarch64_ext_reglane(), aarch64_ext_simd_addr_post(), aarch64_ext_sve_limm_mov(), aarch64_print_operand(), get_int_reg_name(), operand_general_constraint_met_p(), and select_operand_for_scalar_size_field_coding().

◆ aarch64_get_qualifier_name()

const char* aarch64_get_qualifier_name ( aarch64_opnd_qualifier_t qualifier )

Definition at line 758 of file aarch64-opc.c.

 {
   return aarch64_opnd_qualifiers[qualifier].desc;
 }

References aarch64_opnd_qualifiers, and operand_qualifier_data::desc.

Referenced by aarch64_print_operand(), decode_sizeq(), match_operands_qualifier(), and print_register_list().

◆ aarch64_get_qualifier_nelem()

unsigned char aarch64_get_qualifier_nelem ( aarch64_opnd_qualifier_t qualifier )

Definition at line 773 of file aarch64-opc.c.

 {
   assert (operand_variant_qualifier_p (qualifier) == TRUE);
   return aarch64_opnd_qualifiers[qualifier].data1;
 }

References aarch64_opnd_qualifiers, assert(), operand_qualifier_data::data1, operand_variant_qualifier_p(), and TRUE.

Referenced by aarch64_ext_simd_addr_post(), and operand_general_constraint_met_p().

◆ aarch64_get_qualifier_standard_value()

aarch64_insn aarch64_get_qualifier_standard_value ( aarch64_opnd_qualifier_t qualifier )

Definition at line 780 of file aarch64-opc.c.

 {
   assert (operand_variant_qualifier_p (qualifier) == TRUE);
   return aarch64_opnd_qualifiers[qualifier].data2;
 }

References aarch64_opnd_qualifiers, assert(), operand_qualifier_data::data2, operand_variant_qualifier_p(), and TRUE.

◆ aarch64_logical_immediate_p()

bfd_boolean aarch64_logical_immediate_p	(	uint64_t	value,
		int	esize,
		aarch64_insn *	encoding
	)

Definition at line 1207 of file aarch64-opc.c.

 {
   simd_imm_encoding imm_enc;
   const simd_imm_encoding *imm_encoding;
   static bfd_boolean initialized = FALSE;
   uint64_t upper;
   int i;
  
   DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 "), esize: %d", value,
            value, esize);
  
   if (!initialized)
     {
       build_immediate_table ();
       initialized = TRUE;
     }
  
   /* Allow all zeros or all ones in top bits, so that
      constant expressions like ~1 are permitted.  */
   upper = (uint64_t) -1 << (esize * 4) << (esize * 4);
   if ((value & ~upper) != value && (value | upper) != value)
     return FALSE;
  
   /* Replicate to a full 64-bit value.  */
   value &= ~upper;
   for (i = esize * 8; i < 64; i *= 2)
     value |= (value << i);
  
   imm_enc.imm = value;
   imm_encoding = (const simd_imm_encoding *)
     bsearch(&imm_enc, simd_immediates, TOTAL_IMM_NB,
             sizeof(simd_immediates[0]), simd_imm_encoding_cmp);
   if (imm_encoding == NULL)
     {
       DEBUG_TRACE ("exit with FALSE");
       return FALSE;
     }
   if (encoding != NULL)
     *encoding = imm_encoding->encoding;
   DEBUG_TRACE ("exit with TRUE");
   return TRUE;
 }

References build_immediate_table(), DEBUG_TRACE, simd_imm_encoding::encoding, cmd_descs_generate::encoding, FALSE, i, simd_imm_encoding::imm, initialized, NULL, PRIx64, simd_imm_encoding_cmp(), simd_immediates, TOTAL_IMM_NB, TRUE, and value.

Referenced by operand_general_constraint_met_p().

◆ aarch64_match_operands_constraint()

int aarch64_match_operands_constraint	(	aarch64_inst *	inst,
		aarch64_operand_error *	mismatch_detail
	)

Definition at line 2632 of file aarch64-opc.c.

 {
   int i;
  
   DEBUG_TRACE ("enter");
  
   /* Check for cases where a source register needs to be the same as the
      destination register.  Do this before matching qualifiers since if
      an instruction has both invalid tying and invalid qualifiers,
      the error about qualifiers would suggest several alternative
      instructions that also have invalid tying.  */
   i = inst->opcode->tied_operand;
   if (i > 0 && (inst->operands[0].reg.regno != inst->operands[i].reg.regno))
     {
       if (mismatch_detail)
     {
       mismatch_detail->kind = AARCH64_OPDE_UNTIED_OPERAND;
       mismatch_detail->index = i;
       mismatch_detail->error = NULL;
     }
       return 0;
     }
  
   /* Match operands' qualifier.
      *INST has already had qualifier establish for some, if not all, of
      its operands; we need to find out whether these established
      qualifiers match one of the qualifier sequence in
      INST->OPCODE->QUALIFIERS_LIST.  If yes, we will assign each operand
      with the corresponding qualifier in such a sequence.
      Only basic operand constraint checking is done here; the more thorough
      constraint checking will carried out by operand_general_constraint_met_p,
      which has be to called after this in order to get all of the operands'
      qualifiers established.  */
   if (match_operands_qualifier (inst, TRUE /* update_p */) == 0)
     {
       DEBUG_TRACE ("FAIL on operand qualifier matching");
       if (mismatch_detail)
     {
       /* Return an error type to indicate that it is the qualifier
          matching failure; we don't care about which operand as there
          are enough information in the opcode table to reproduce it.  */
       mismatch_detail->kind = AARCH64_OPDE_INVALID_VARIANT;
       mismatch_detail->index = -1;
       mismatch_detail->error = NULL;
     }
       return 0;
     }
  
   /* Match operands' constraint.  */
   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
     {
       enum aarch64_opnd type = inst->opcode->operands[i];
       if (type == AARCH64_OPND_NIL)
     break;
       if (inst->operands[i].skip)
     {
       DEBUG_TRACE ("skip the incomplete operand %d", i);
       continue;
     }
       if (operand_general_constraint_met_p (inst->operands, i, type,
                         inst->opcode, mismatch_detail) == 0)
     {
       DEBUG_TRACE ("FAIL on operand %d", i);
       return 0;
     }
     }
  
   DEBUG_TRACE ("PASS");
  
   return 1;
 }

References AARCH64_MAX_OPND_NUM, AARCH64_OPDE_INVALID_VARIANT, AARCH64_OPDE_UNTIED_OPERAND, AARCH64_OPND_NIL, DEBUG_TRACE, aarch64_operand_error::error, i, aarch64_operand_error::index, aarch64_operand_error::kind, match_operands_qualifier(), NULL, aarch64_inst::opcode, operand_general_constraint_met_p(), aarch64_opcode::operands, aarch64_inst::operands, aarch64_opnd_info::reg, aarch64_opnd_info::skip, aarch64_opcode::tied_operand, TRUE, and type.

Referenced by aarch64_opcode_decode(), and determine_disassembling_preference().

◆ aarch64_num_of_operands()

int aarch64_num_of_operands ( const aarch64_opcode * opcode )

Definition at line 842 of file aarch64-opc.c.

 {
   int i = 0;
   const enum aarch64_opnd *opnds = opcode->operands;
   while (opnds[i++] != AARCH64_OPND_NIL)
     ;
   --i;
   assert (i >= 0 && i <= AARCH64_MAX_OPND_NUM);
   return i;
 }

References AARCH64_MAX_OPND_NUM, AARCH64_OPND_NIL, assert(), i, and aarch64_opcode::operands.

Referenced by aarch64_find_best_match(), determine_disassembling_preference(), and match_operands_qualifier().

◆ aarch64_operand_index()

int aarch64_operand_index	(	const enum aarch64_opnd *	operands,
		enum aarch64_opnd	operand
	)

Definition at line 2736 of file aarch64-opc.c.

 {
   int i;
   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
     if (operands[i] == operand)
       return i;
     else if (operands[i] == AARCH64_OPND_NIL)
       break;
   return -1;
 }

References AARCH64_MAX_OPND_NUM, AARCH64_OPND_NIL, and i.

Referenced by do_special_decoding().

◆ aarch64_print_operand()

void aarch64_print_operand	(	char *	buf,
		size_t	size,
		bfd_vma	pc,
		const aarch64_opcode *	opcode,
		const aarch64_opnd_info *	opnds,
		int	idx,
		int *	pcrel_p,
		bfd_vma *	address,
		char **notes	ATTRIBUTE_UNUSED
	)

Definition at line 3036 of file aarch64-opc.c.

 {
   unsigned int i, num_conds;
   const char *name = NULL;
   const aarch64_opnd_info *opnd = opnds + idx;
   enum aarch64_modifier_kind kind;
   uint64_t addr, enum_value;
  
   buf[0] = '\0';
   if (pcrel_p)
     *pcrel_p = 0;
  
   switch (opnd->type)
     {
     case AARCH64_OPND_Rd:
     case AARCH64_OPND_Rn:
     case AARCH64_OPND_Rm:
     case AARCH64_OPND_Rt:
     case AARCH64_OPND_Rt2:
     case AARCH64_OPND_Rs:
     case AARCH64_OPND_Ra:
     case AARCH64_OPND_Rt_SYS:
     case AARCH64_OPND_PAIRREG:
     case AARCH64_OPND_SVE_Rm:
       /* The optional-ness of <Xt> in e.g. IC <ic_op>{, <Xt>} is determined by
      the <ic_op>, therefore we use opnd->present to override the
      generic optional-ness information.  */
       if (opnd->type == AARCH64_OPND_Rt_SYS)
     {
       if (!opnd->present)
         break;
     }
       /* Omit the operand, e.g. RET.  */
       else if (optional_operand_p (opcode, idx)
            && (opnd->reg.regno
            == get_optional_operand_default_value (opcode)))
     break;
       assert (opnd->qualifier == AARCH64_OPND_QLF_W
           || opnd->qualifier == AARCH64_OPND_QLF_X);
       snprintf (buf, size, "%s",
         get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
       break;
  
     case AARCH64_OPND_Rd_SP:
     case AARCH64_OPND_Rn_SP:
     case AARCH64_OPND_SVE_Rn_SP:
     case AARCH64_OPND_Rm_SP:
       assert (opnd->qualifier == AARCH64_OPND_QLF_W
           || opnd->qualifier == AARCH64_OPND_QLF_WSP
           || opnd->qualifier == AARCH64_OPND_QLF_X
           || opnd->qualifier == AARCH64_OPND_QLF_SP);
       snprintf (buf, size, "%s",
         get_int_reg_name (opnd->reg.regno, opnd->qualifier, 1));
       break;
  
     case AARCH64_OPND_Rm_EXT:
       kind = opnd->shifter.kind;
       assert (idx == 1 || idx == 2);
       if ((aarch64_stack_pointer_p (opnds)
        || (idx == 2 && aarch64_stack_pointer_p (opnds + 1)))
       && ((opnd->qualifier == AARCH64_OPND_QLF_W
            && opnds[0].qualifier == AARCH64_OPND_QLF_W
            && kind == AARCH64_MOD_UXTW)
           || (opnd->qualifier == AARCH64_OPND_QLF_X
           && kind == AARCH64_MOD_UXTX)))
     {
       /* 'LSL' is the preferred form in this case.  */
       kind = AARCH64_MOD_LSL;
       if (opnd->shifter.amount == 0)
         {
           /* Shifter omitted.  */
           snprintf (buf, size, "%s",
             get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
           break;
         }
     }
       if (opnd->shifter.amount)
     snprintf (buf, size, "%s, %s #%" PRIi64,
           get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
           aarch64_operand_modifiers[kind].name,
           opnd->shifter.amount);
       else
     snprintf (buf, size, "%s, %s",
           get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
           aarch64_operand_modifiers[kind].name);
       break;
  
     case AARCH64_OPND_Rm_SFT:
       assert (opnd->qualifier == AARCH64_OPND_QLF_W
           || opnd->qualifier == AARCH64_OPND_QLF_X);
       if (opnd->shifter.amount == 0 && opnd->shifter.kind == AARCH64_MOD_LSL)
     snprintf (buf, size, "%s",
           get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
       else
     snprintf (buf, size, "%s, %s #%" PRIi64,
           get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
           aarch64_operand_modifiers[opnd->shifter.kind].name,
           opnd->shifter.amount);
       break;
  
     case AARCH64_OPND_Fd:
     case AARCH64_OPND_Fn:
     case AARCH64_OPND_Fm:
     case AARCH64_OPND_Fa:
     case AARCH64_OPND_Ft:
     case AARCH64_OPND_Ft2:
     case AARCH64_OPND_Sd:
     case AARCH64_OPND_Sn:
     case AARCH64_OPND_Sm:
     case AARCH64_OPND_SVE_VZn:
     case AARCH64_OPND_SVE_Vd:
     case AARCH64_OPND_SVE_Vm:
     case AARCH64_OPND_SVE_Vn:
       snprintf (buf, size, "%s%d", aarch64_get_qualifier_name (opnd->qualifier),
         opnd->reg.regno);
       break;
  
     case AARCH64_OPND_Va:
     case AARCH64_OPND_Vd:
     case AARCH64_OPND_Vn:
     case AARCH64_OPND_Vm:
       snprintf (buf, size, "v%d.%s", opnd->reg.regno,
         aarch64_get_qualifier_name (opnd->qualifier));
       break;
  
     case AARCH64_OPND_Ed:
     case AARCH64_OPND_En:
     case AARCH64_OPND_Em:
     case AARCH64_OPND_Em16:
     case AARCH64_OPND_SM3_IMM2:
       snprintf (buf, size, "v%d.%s[%" PRIi64 "]", opnd->reglane.regno,
         aarch64_get_qualifier_name (opnd->qualifier),
         opnd->reglane.index);
       break;
  
     case AARCH64_OPND_VdD1:
     case AARCH64_OPND_VnD1:
       snprintf (buf, size, "v%d.d[1]", opnd->reg.regno);
       break;
  
     case AARCH64_OPND_LVn:
     case AARCH64_OPND_LVt:
     case AARCH64_OPND_LVt_AL:
     case AARCH64_OPND_LEt:
       print_register_list (buf, size, opnd, "v");
       break;
  
     case AARCH64_OPND_SVE_Pd:
     case AARCH64_OPND_SVE_Pg3:
     case AARCH64_OPND_SVE_Pg4_5:
     case AARCH64_OPND_SVE_Pg4_10:
     case AARCH64_OPND_SVE_Pg4_16:
     case AARCH64_OPND_SVE_Pm:
     case AARCH64_OPND_SVE_Pn:
     case AARCH64_OPND_SVE_Pt:
       if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
     snprintf (buf, size, "p%d", opnd->reg.regno);
       else if (opnd->qualifier == AARCH64_OPND_QLF_P_Z
            || opnd->qualifier == AARCH64_OPND_QLF_P_M)
     snprintf (buf, size, "p%d/%s", opnd->reg.regno,
           aarch64_get_qualifier_name (opnd->qualifier));
       else
     snprintf (buf, size, "p%d.%s", opnd->reg.regno,
           aarch64_get_qualifier_name (opnd->qualifier));
       break;
  
     case AARCH64_OPND_SVE_Za_5:
     case AARCH64_OPND_SVE_Za_16:
     case AARCH64_OPND_SVE_Zd:
     case AARCH64_OPND_SVE_Zm_5:
     case AARCH64_OPND_SVE_Zm_16:
     case AARCH64_OPND_SVE_Zn:
     case AARCH64_OPND_SVE_Zt:
       if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
     snprintf (buf, size, "z%d", opnd->reg.regno);
       else
     snprintf (buf, size, "z%d.%s", opnd->reg.regno,
           aarch64_get_qualifier_name (opnd->qualifier));
       break;
  
     case AARCH64_OPND_SVE_ZnxN:
     case AARCH64_OPND_SVE_ZtxN:
       print_register_list (buf, size, opnd, "z");
       break;
  
     case AARCH64_OPND_SVE_Zm3_INDEX:
     case AARCH64_OPND_SVE_Zm3_22_INDEX:
     case AARCH64_OPND_SVE_Zm4_INDEX:
     case AARCH64_OPND_SVE_Zn_INDEX:
       snprintf (buf, size, "z%d.%s[%" PRIi64 "]", opnd->reglane.regno,
         aarch64_get_qualifier_name (opnd->qualifier),
         opnd->reglane.index);
       break;
  
     case AARCH64_OPND_CRn:
     case AARCH64_OPND_CRm:
       snprintf (buf, size, "C%" PRIi64, opnd->imm.value);
       break;
  
     case AARCH64_OPND_IDX:
     case AARCH64_OPND_MASK:
     case AARCH64_OPND_IMM:
     case AARCH64_OPND_IMM_2:
     case AARCH64_OPND_WIDTH:
     case AARCH64_OPND_UIMM3_OP1:
     case AARCH64_OPND_UIMM3_OP2:
     case AARCH64_OPND_BIT_NUM:
     case AARCH64_OPND_IMM_VLSL:
     case AARCH64_OPND_IMM_VLSR:
     case AARCH64_OPND_SHLL_IMM:
     case AARCH64_OPND_IMM0:
     case AARCH64_OPND_IMMR:
     case AARCH64_OPND_IMMS:
     case AARCH64_OPND_FBITS:
     case AARCH64_OPND_SIMM5:
     case AARCH64_OPND_SVE_SHLIMM_PRED:
     case AARCH64_OPND_SVE_SHLIMM_UNPRED:
     case AARCH64_OPND_SVE_SHRIMM_PRED:
     case AARCH64_OPND_SVE_SHRIMM_UNPRED:
     case AARCH64_OPND_SVE_SIMM5:
     case AARCH64_OPND_SVE_SIMM5B:
     case AARCH64_OPND_SVE_SIMM6:
     case AARCH64_OPND_SVE_SIMM8:
     case AARCH64_OPND_SVE_UIMM3:
     case AARCH64_OPND_SVE_UIMM7:
     case AARCH64_OPND_SVE_UIMM8:
     case AARCH64_OPND_SVE_UIMM8_53:
     case AARCH64_OPND_IMM_ROT1:
     case AARCH64_OPND_IMM_ROT2:
     case AARCH64_OPND_IMM_ROT3:
     case AARCH64_OPND_SVE_IMM_ROT1:
     case AARCH64_OPND_SVE_IMM_ROT2:
       snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
       break;
  
     case AARCH64_OPND_SVE_I1_HALF_ONE:
     case AARCH64_OPND_SVE_I1_HALF_TWO:
     case AARCH64_OPND_SVE_I1_ZERO_ONE:
       {
     single_conv_t c;
     c.i = opnd->imm.value;
     snprintf (buf, size, "#%.1f", c.f);
     break;
       }
  
     case AARCH64_OPND_SVE_PATTERN:
       if (optional_operand_p (opcode, idx)
       && opnd->imm.value == get_optional_operand_default_value (opcode))
     break;
       enum_value = opnd->imm.value;
       assert (enum_value < ARRAY_SIZE (aarch64_sve_pattern_array));
       if (aarch64_sve_pattern_array[enum_value])
     snprintf (buf, size, "%s", aarch64_sve_pattern_array[enum_value]);
       else
     snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
       break;
  
     case AARCH64_OPND_SVE_PATTERN_SCALED:
       if (optional_operand_p (opcode, idx)
       && !opnd->shifter.operator_present
       && opnd->imm.value == get_optional_operand_default_value (opcode))
     break;
       enum_value = opnd->imm.value;
       assert (enum_value < ARRAY_SIZE (aarch64_sve_pattern_array));
       if (aarch64_sve_pattern_array[opnd->imm.value])
     snprintf (buf, size, "%s", aarch64_sve_pattern_array[opnd->imm.value]);
       else
     snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
       if (opnd->shifter.operator_present)
     {
       size_t len = strlen (buf);
       snprintf (buf + len, size - len, ", %s #%" PRIi64,
             aarch64_operand_modifiers[opnd->shifter.kind].name,
             opnd->shifter.amount);
     }
       break;
  
     case AARCH64_OPND_SVE_PRFOP:
       enum_value = opnd->imm.value;
       assert (enum_value < ARRAY_SIZE (aarch64_sve_prfop_array));
       if (aarch64_sve_prfop_array[enum_value])
     snprintf (buf, size, "%s", aarch64_sve_prfop_array[enum_value]);
       else
     snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
       break;
  
     case AARCH64_OPND_IMM_MOV:
       switch (aarch64_get_qualifier_esize (opnds[0].qualifier))
     {
     case 4: /* e.g. MOV Wd, #<imm32>.  */
         {
           int imm32 = opnd->imm.value;
           snprintf (buf, size, "0x%x", imm32);
         }
       break;
     case 8: /* e.g. MOV Xd, #<imm64>.  */
       snprintf (buf, size, "0x%" PRIx64, opnd->imm.value);
       break;
     default: assert (0);
     }
       break;
  
     case AARCH64_OPND_FPIMM0:
       snprintf (buf, size, "0.0");
       break;
  
     case AARCH64_OPND_LIMM:
     case AARCH64_OPND_AIMM:
     case AARCH64_OPND_HALF:
     case AARCH64_OPND_SVE_INV_LIMM:
     case AARCH64_OPND_SVE_LIMM:
     case AARCH64_OPND_SVE_LIMM_MOV:
       if (opnd->shifter.amount)
     snprintf (buf, size, "0x%" PRIx64 ", lsl #%" PRIi64, opnd->imm.value,
           opnd->shifter.amount);
       else
     snprintf (buf, size, "0x%" PRIx64, opnd->imm.value);
       break;
  
     case AARCH64_OPND_SIMD_IMM:
     case AARCH64_OPND_SIMD_IMM_SFT:
       if ((! opnd->shifter.amount && opnd->shifter.kind == AARCH64_MOD_LSL)
       || opnd->shifter.kind == AARCH64_MOD_NONE)
     snprintf (buf, size, "0x%" PRIx64, opnd->imm.value);
       else
     snprintf (buf, size, "0x%" PRIx64 ", %s #%" PRIi64, opnd->imm.value,
           aarch64_operand_modifiers[opnd->shifter.kind].name,
           opnd->shifter.amount);
       break;
  
     case AARCH64_OPND_SVE_AIMM:
     case AARCH64_OPND_SVE_ASIMM:
       if (opnd->shifter.amount)
     snprintf (buf, size, "#%" PRIi64 ", lsl #%" PRIi64, opnd->imm.value,
           opnd->shifter.amount);
       else
     snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
       break;
  
     case AARCH64_OPND_FPIMM:
     case AARCH64_OPND_SIMD_FPIMM:
     case AARCH64_OPND_SVE_FPIMM8:
       switch (aarch64_get_qualifier_esize (opnds[0].qualifier))
     {
     case 2: /* e.g. FMOV <Hd>, #<imm>.  */
         {
           half_conv_t c;
           c.i = expand_fp_imm (2, opnd->imm.value);
           snprintf (buf, size,  "#%.18e", c.f);
         }
       break;
     case 4: /* e.g. FMOV <Vd>.4S, #<imm>.  */
         {
           single_conv_t c;
           c.i = expand_fp_imm (4, opnd->imm.value);
           snprintf (buf, size,  "#%.18e", c.f);
         }
       break;
     case 8: /* e.g. FMOV <Sd>, #<imm>.  */
         {
           double_conv_t c;
           c.i = expand_fp_imm (8, opnd->imm.value);
           snprintf (buf, size,  "#%.18e", c.d);
         }
       break;
     default: assert (0);
     }
       break;
  
     case AARCH64_OPND_CCMP_IMM:
     case AARCH64_OPND_NZCV:
     case AARCH64_OPND_EXCEPTION:
     case AARCH64_OPND_UIMM4:
     case AARCH64_OPND_UIMM7:
       if (optional_operand_p (opcode, idx) == TRUE
       && (opnd->imm.value ==
           (int64_t) get_optional_operand_default_value (opcode)))
     /* Omit the operand, e.g. DCPS1.  */
     break;
       snprintf (buf, size, "0x%x", (unsigned int)opnd->imm.value);
       break;
  
     case AARCH64_OPND_COND:
     case AARCH64_OPND_COND1:
       snprintf (buf, size, "%s", opnd->cond->names[0]);
       num_conds = ARRAY_SIZE (opnd->cond->names);
       for (i = 1; i < num_conds && opnd->cond->names[i]; ++i)
     {
       size_t len = strlen (buf);
       if (i == 1)
         snprintf (buf + len, size - len, "  // %s = %s",
               opnd->cond->names[0], opnd->cond->names[i]);
       else
         snprintf (buf + len, size - len, ", %s",
               opnd->cond->names[i]);
     }
       break;
  
     case AARCH64_OPND_ADDR_ADRP:
       addr = ((pc + AARCH64_PCREL_OFFSET) & ~(uint64_t)0xfff)
     + opnd->imm.value;
       if (pcrel_p)
     *pcrel_p = 1;
       if (address)
     *address = addr;
       /* This is not necessary during the disassembling, as print_address_func
      in the disassemble_info will take care of the printing.  But some
      other callers may be still interested in getting the string in *STR,
      so here we do snprintf regardless.  */
       snprintf (buf, size, "0x%" PRIx64, addr);
       break;
  
     case AARCH64_OPND_ADDR_PCREL14:
     case AARCH64_OPND_ADDR_PCREL19:
     case AARCH64_OPND_ADDR_PCREL21:
     case AARCH64_OPND_ADDR_PCREL26:
       addr = pc + AARCH64_PCREL_OFFSET + opnd->imm.value;
       if (pcrel_p)
     *pcrel_p = 1;
       if (address)
     *address = addr;
       /* This is not necessary during the disassembling, as print_address_func
      in the disassemble_info will take care of the printing.  But some
      other callers may be still interested in getting the string in *STR,
      so here we do snprintf regardless.  */
       snprintf (buf, size, "0x%" PRIx64, addr);
       break;
  
     case AARCH64_OPND_ADDR_SIMPLE:
     case AARCH64_OPND_SIMD_ADDR_SIMPLE:
     case AARCH64_OPND_SIMD_ADDR_POST:
       name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
       if (opnd->type == AARCH64_OPND_SIMD_ADDR_POST)
     {
       if (opnd->addr.offset.is_reg)
         snprintf (buf, size, "[%s], x%d", name, opnd->addr.offset.regno);
       else
         snprintf (buf, size, "[%s], #%d", name, opnd->addr.offset.imm);
     }
       else
     snprintf (buf, size, "[%s]", name);
       break;
  
     case AARCH64_OPND_ADDR_REGOFF:
     case AARCH64_OPND_SVE_ADDR_R:
     case AARCH64_OPND_SVE_ADDR_RR:
     case AARCH64_OPND_SVE_ADDR_RR_LSL1:
     case AARCH64_OPND_SVE_ADDR_RR_LSL2:
     case AARCH64_OPND_SVE_ADDR_RR_LSL3:
     case AARCH64_OPND_SVE_ADDR_RX:
     case AARCH64_OPND_SVE_ADDR_RX_LSL1:
     case AARCH64_OPND_SVE_ADDR_RX_LSL2:
     case AARCH64_OPND_SVE_ADDR_RX_LSL3:
       print_register_offset_address
     (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
      get_offset_int_reg_name (opnd));
       break;
  
     case AARCH64_OPND_SVE_ADDR_RZ:
     case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
     case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
     case AARCH64_OPND_SVE_ADDR_RZ_LSL3:
     case AARCH64_OPND_SVE_ADDR_RZ_XTW_14:
     case AARCH64_OPND_SVE_ADDR_RZ_XTW_22:
     case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14:
     case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22:
     case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14:
     case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22:
     case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14:
     case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22:
       print_register_offset_address
     (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
      get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier));
       break;
  
     case AARCH64_OPND_ADDR_SIMM7:
     case AARCH64_OPND_ADDR_SIMM9:
     case AARCH64_OPND_ADDR_SIMM9_2:
     case AARCH64_OPND_ADDR_SIMM10:
     case AARCH64_OPND_ADDR_OFFSET:
     case AARCH64_OPND_SVE_ADDR_RI_S4x16:
     case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
     case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
     case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
     case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL:
     case AARCH64_OPND_SVE_ADDR_RI_S6xVL:
     case AARCH64_OPND_SVE_ADDR_RI_S9xVL:
     case AARCH64_OPND_SVE_ADDR_RI_U6:
     case AARCH64_OPND_SVE_ADDR_RI_U6x2:
     case AARCH64_OPND_SVE_ADDR_RI_U6x4:
     case AARCH64_OPND_SVE_ADDR_RI_U6x8:
       print_immediate_offset_address
     (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1));
       break;
  
     case AARCH64_OPND_SVE_ADDR_ZI_U5:
     case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
     case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
     case AARCH64_OPND_SVE_ADDR_ZI_U5x8:
       print_immediate_offset_address
     (buf, size, opnd,
      get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier));
       break;
  
     case AARCH64_OPND_SVE_ADDR_ZZ_LSL:
     case AARCH64_OPND_SVE_ADDR_ZZ_SXTW:
     case AARCH64_OPND_SVE_ADDR_ZZ_UXTW:
       print_register_offset_address
     (buf, size, opnd,
      get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier),
      get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier));
       break;
  
     case AARCH64_OPND_ADDR_UIMM12:
       name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
       if (opnd->addr.offset.imm)
     snprintf (buf, size, "[%s, #%d]", name, opnd->addr.offset.imm);
       else
     snprintf (buf, size, "[%s]", name);
       break;
  
     case AARCH64_OPND_SYSREG:
       for (i = 0; aarch64_sys_regs[i].name; ++i)
     {
       bfd_boolean exact_match
         = (aarch64_sys_regs[i].flags & opnd->sysreg.flags)
            == opnd->sysreg.flags;
  
       /* Try and find an exact match, But if that fails, return the first
          partial match that was found.  */
       if (aarch64_sys_regs[i].value == opnd->sysreg.value
           && ! aarch64_sys_reg_deprecated_p (&aarch64_sys_regs[i])
           && (name == NULL || exact_match))
         {
           name = aarch64_sys_regs[i].name;
           if (exact_match)
         {
           if (notes)
             *notes = NULL;
           break;
         }
  
           /* If we didn't match exactly, that means the presense of a flag
          indicates what we didn't want for this instruction.  e.g. If
          F_REG_READ is there, that means we were looking for a write
          register.  See aarch64_ext_sysreg.  */
           if (aarch64_sys_regs[i].flags & F_REG_WRITE)
         *notes = _("reading from a write-only register.");
           else if (aarch64_sys_regs[i].flags & F_REG_READ)
         *notes = _("writing to a read-only register.");
         }
     }
  
       if (name)
     snprintf (buf, size, "%s", name);
       else
     {
       /* Implementation defined system register.  */
       unsigned int value = opnd->sysreg.value;
       snprintf (buf, size, "s%u_%u_c%u_c%u_%u", (value >> 14) & 0x3,
             (value >> 11) & 0x7, (value >> 7) & 0xf, (value >> 3) & 0xf,
             value & 0x7);
     }
       break;
  
     case AARCH64_OPND_PSTATEFIELD:
       for (i = 0; aarch64_pstatefields[i].name; ++i)
     if (aarch64_pstatefields[i].value == opnd->pstatefield)
       break;
       assert (aarch64_pstatefields[i].name);
       snprintf (buf, size, "%s", aarch64_pstatefields[i].name);
       break;
  
     case AARCH64_OPND_SYSREG_AT:
     case AARCH64_OPND_SYSREG_DC:
     case AARCH64_OPND_SYSREG_IC:
     case AARCH64_OPND_SYSREG_TLBI:
       snprintf (buf, size, "%s", opnd->sysins_op->name);
       break;
  
     case AARCH64_OPND_BARRIER:
       snprintf (buf, size, "%s", opnd->barrier->name);
       break;
  
     case AARCH64_OPND_BARRIER_ISB:
       /* Operand can be omitted, e.g. in DCPS1.  */
       if (! optional_operand_p (opcode, idx)
       || (opnd->barrier->value
           != get_optional_operand_default_value (opcode)))
     snprintf (buf, size, "0x%x", opnd->barrier->value);
       break;
  
     case AARCH64_OPND_PRFOP:
       if (opnd->prfop->name != NULL)
     snprintf (buf, size, "%s", opnd->prfop->name);
       else
     snprintf (buf, size, "0x%02x", opnd->prfop->value);
       break;
  
     case AARCH64_OPND_BARRIER_PSB:
       snprintf (buf, size, "%s", opnd->hint_option->name);
       break;
  
     default:
       assert (0);
     }
 }

Referenced by print_operands().

◆ aarch64_pstatefield_supported_p()

bfd_boolean aarch64_pstatefield_supported_p	(	const aarch64_feature_set	features,
		const aarch64_sys_reg *	reg
	)

Definition at line 4293 of file aarch64-opc.c.

 {
   if (!(reg->flags & F_ARCHEXT))
     return TRUE;
  
   /* PAN.  Values are from aarch64_pstatefields.  */
   if (reg->value == 0x04
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
     return FALSE;
  
   /* UAO.  Values are from aarch64_pstatefields.  */
   if (reg->value == 0x03
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
     return FALSE;
  
   /* DIT.  Values are from aarch64_pstatefields.  */
   if (reg->value == 0x1a
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
     return FALSE;
  
   return TRUE;
 }

References AARCH64_CPU_HAS_FEATURE, AARCH64_FEATURE_PAN, AARCH64_FEATURE_V8_2, AARCH64_FEATURE_V8_4, F_ARCHEXT, FALSE, features, reg, and TRUE.

◆ aarch64_replace_opcode()

const aarch64_opcode* aarch64_replace_opcode	(	aarch64_inst *	inst,
		const aarch64_opcode *	opcode
	)

Definition at line 2715 of file aarch64-opc.c.

 {
   int i;
   const aarch64_opcode *old = inst->opcode;
  
   inst->opcode = opcode;
  
   /* Update the operand types.  */
   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
     {
       inst->operands[i].type = opcode->operands[i];
       if (opcode->operands[i] == AARCH64_OPND_NIL)
     break;
     }
  
   DEBUG_TRACE ("replace %s with %s", old->name, opcode->name);
  
   return old;
 }

References AARCH64_MAX_OPND_NUM, AARCH64_OPND_NIL, DEBUG_TRACE, i, aarch64_opcode::name, aarch64_inst::opcode, aarch64_opcode::operands, aarch64_inst::operands, and aarch64_opnd_info::type.

Referenced by determine_disassembling_preference().

◆ aarch64_select_operand_for_sizeq_field_coding()

int aarch64_select_operand_for_sizeq_field_coding ( const aarch64_opcode * opcode )

Definition at line 199 of file aarch64-opc.c.

 {
   return
     significant_operand_index [get_data_pattern (opcode->qualifiers_list[0])];
 }

References get_data_pattern(), aarch64_opcode::qualifiers_list, and significant_operand_index.

Referenced by decode_sizeq().

◆ aarch64_shift_operator_p()

static bfd_boolean aarch64_shift_operator_p ( enum aarch64_modifier_kind kind )

inlinestatic

Definition at line 437 of file aarch64-opc.c.

 {
   return (kind >= AARCH64_MOD_ROR && kind <= AARCH64_MOD_LSL)
     ? TRUE : FALSE;
 }

Referenced by operand_general_constraint_met_p().

◆ aarch64_shrink_expanded_imm8()

int aarch64_shrink_expanded_imm8 ( uint64_t imm )

Definition at line 1255 of file aarch64-opc.c.

 {
   int i, ret;
   uint32_t byte;
  
   ret = 0;
   for (i = 0; i < 8; i++)
     {
       byte = (imm >> (8 * i)) & 0xff;
       if (byte == 0xff)
     ret |= 1 << i;
       else if (byte != 0x00)
     return -1;
     }
   return ret;
 }

References i, and imm.

Referenced by operand_general_constraint_met_p().

◆ aarch64_stack_pointer_p()

int aarch64_stack_pointer_p ( const aarch64_opnd_info * operand )

Definition at line 562 of file aarch64-opc.c.

 {
   return ((aarch64_get_operand_class (operand->type)
        == AARCH64_OPND_CLASS_INT_REG)
       && operand_maybe_stack_pointer (aarch64_operands + operand->type)
       && operand->reg.regno == 31);
 }

References aarch64_get_operand_class(), aarch64_operands, AARCH64_OPND_CLASS_INT_REG, and operand_maybe_stack_pointer().

Referenced by aarch64_print_operand(), operand_also_qualified_p(), and operand_general_constraint_met_p().

◆ aarch64_sve_dupm_mov_immediate_p()

bfd_boolean aarch64_sve_dupm_mov_immediate_p	(	uint64_t	uvalue,
		int	esize
	)

Definition at line 4521 of file aarch64-opc.c.

 {
   int64_t svalue = uvalue;
   uint64_t upper = (uint64_t) -1 << (esize * 4) << (esize * 4);
  
   if ((uvalue & ~upper) != uvalue && (uvalue | upper) != uvalue)
     return FALSE;
   if (esize <= 4 || (uint32_t) uvalue == (uint32_t) (uvalue >> 32))
     {
       svalue = (int32_t) uvalue;
       if (esize <= 2 || (uint16_t) uvalue == (uint16_t) (uvalue >> 16))
     {
       svalue = (int16_t) uvalue;
       if (esize == 1 || (uint8_t) uvalue == (uint8_t) (uvalue >> 8))
         return FALSE;
     }
     }
   if ((svalue & 0xff) == 0)
     svalue /= 256;
   return svalue < -128 || svalue >= 128;
 }

References FALSE.

Referenced by aarch64_ext_sve_limm_mov(), and operand_general_constraint_met_p().

◆ aarch64_sys_ins_reg_has_xt()

bfd_boolean aarch64_sys_ins_reg_has_xt ( const aarch64_sys_ins_reg * sys_ins_reg )

Definition at line 4445 of file aarch64-opc.c.

 {
   return (sys_ins_reg->flags & F_HASXT) != 0;
 }

References F_HASXT, and aarch64_sys_ins_reg::flags.

Referenced by aarch64_ext_regrt_sysins(), aarch64_ext_sysins_op(), and operand_general_constraint_met_p().

◆ aarch64_sys_ins_reg_supported_p()

bfd_boolean aarch64_sys_ins_reg_supported_p	(	const aarch64_feature_set	features,
		const aarch64_sys_ins_reg *	reg
	)

Definition at line 4451 of file aarch64-opc.c.

 {
   if (!(reg->flags & F_ARCHEXT))
     return TRUE;
  
   /* DC CVAP.  Values are from aarch64_sys_regs_dc.  */
   if (reg->value == CPENS (3, C7, C12, 1)
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
     return FALSE;
  
   /* AT S1E1RP, AT S1E1WP.  Values are from aarch64_sys_regs_at.  */
   if ((reg->value == CPENS (0, C7, C9, 0)
        || reg->value == CPENS (0, C7, C9, 1))
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
     return FALSE;
  
   return TRUE;
 }

References AARCH64_CPU_HAS_FEATURE, AARCH64_FEATURE_V8_2, C12, C7, C9, CPENS, F_ARCHEXT, FALSE, features, reg, and TRUE.

◆ aarch64_sys_reg_deprecated_p()

bfd_boolean aarch64_sys_reg_deprecated_p ( const aarch64_sys_reg * reg )

Definition at line 4067 of file aarch64-opc.c.

 {
   return (reg->flags & F_DEPRECATED) != 0;
 }

References F_DEPRECATED, and reg.

Referenced by aarch64_print_operand().

◆ aarch64_sys_reg_supported_p()

bfd_boolean aarch64_sys_reg_supported_p	(	const aarch64_feature_set	features,
		const aarch64_sys_reg *	reg
	)

Definition at line 4073 of file aarch64-opc.c.

 {
   if (!(reg->flags & F_ARCHEXT))
     return TRUE;
  
   /* PAN.  Values are from aarch64_sys_regs.  */
   if (reg->value == CPEN_(0,C2,3)
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
     return FALSE;
  
   /* Virtualization host extensions: system registers.  */
   if ((reg->value == CPENC (3, 4, C2, C0, 1)
        || reg->value == CPENC (3, 4, C13, C0, 1)
        || reg->value == CPENC (3, 4, C14, C3, 0)
        || reg->value == CPENC (3, 4, C14, C3, 1)
        || reg->value == CPENC (3, 4, C14, C3, 2))
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
       return FALSE;
  
   /* Virtualization host extensions: *_el12 names of *_el1 registers.  */
   if ((reg->value == CPEN_ (5, C0, 0)
        || reg->value == CPEN_ (5, C0, 1)
        || reg->value == CPENC (3, 5, C1, C0, 0)
        || reg->value == CPENC (3, 5, C1, C0, 2)
        || reg->value == CPENC (3, 5, C2, C0, 0)
        || reg->value == CPENC (3, 5, C2, C0, 1)
        || reg->value == CPENC (3, 5, C2, C0, 2)
        || reg->value == CPENC (3, 5, C5, C1, 0)
        || reg->value == CPENC (3, 5, C5, C1, 1)
        || reg->value == CPENC (3, 5, C5, C2, 0)
        || reg->value == CPENC (3, 5, C6, C0, 0)
        || reg->value == CPENC (3, 5, C10, C2, 0)
        || reg->value == CPENC (3, 5, C10, C3, 0)
        || reg->value == CPENC (3, 5, C12, C0, 0)
        || reg->value == CPENC (3, 5, C13, C0, 1)
        || reg->value == CPENC (3, 5, C14, C1, 0))
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
     return FALSE;
  
   /* Virtualization host extensions: *_el02 names of *_el0 registers.  */
   if ((reg->value == CPENC (3, 5, C14, C2, 0)
        || reg->value == CPENC (3, 5, C14, C2, 1)
        || reg->value == CPENC (3, 5, C14, C2, 2)
        || reg->value == CPENC (3, 5, C14, C3, 0)
        || reg->value == CPENC (3, 5, C14, C3, 1)
        || reg->value == CPENC (3, 5, C14, C3, 2))
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
     return FALSE;
  
   /* ARMv8.2 features.  */
  
   /* ID_AA64MMFR2_EL1.  */
   if (reg->value == CPENC (3, 0, C0, C7, 2)
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
     return FALSE;
  
   /* PSTATE.UAO.  */
   if (reg->value == CPEN_ (0, C2, 4)
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
     return FALSE;
  
   /* RAS extension.  */
  
   /* ERRIDR_EL1, ERRSELR_EL1, ERXFR_EL1, ERXCTLR_EL1, ERXSTATUS_EL, ERXADDR_EL1,
      ERXMISC0_EL1 AND ERXMISC1_EL1.  */
   if ((reg->value == CPENC (3, 0, C5, C3, 0)
        || reg->value == CPENC (3, 0, C5, C3, 1)
        || reg->value == CPENC (3, 0, C5, C3, 2)
        || reg->value == CPENC (3, 0, C5, C3, 3)
        || reg->value == CPENC (3, 0, C5, C4, 0)
        || reg->value == CPENC (3, 0, C5, C4, 1)
        || reg->value == CPENC (3, 0, C5, C4, 2)
        || reg->value == CPENC (3, 0, C5, C4, 3)
        || reg->value == CPENC (3, 0, C5, C5, 0)
        || reg->value == CPENC (3, 0, C5, C5, 1))
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
     return FALSE;
  
   /* VSESR_EL2, DISR_EL1 and VDISR_EL2.  */
   if ((reg->value == CPENC (3, 4, C5, C2, 3)
        || reg->value == CPENC (3, 0, C12, C1, 1)
        || reg->value == CPENC (3, 4, C12, C1, 1))
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
     return FALSE;
  
   /* Statistical Profiling extension.  */
   if ((reg->value == CPENC (3, 0, C9, C10, 0)
        || reg->value == CPENC (3, 0, C9, C10, 1)
        || reg->value == CPENC (3, 0, C9, C10, 3)
        || reg->value == CPENC (3, 0, C9, C10, 7)
        || reg->value == CPENC (3, 0, C9, C9, 0)
        || reg->value == CPENC (3, 0, C9, C9, 2)
        || reg->value == CPENC (3, 0, C9, C9, 3)
        || reg->value == CPENC (3, 0, C9, C9, 4)
        || reg->value == CPENC (3, 0, C9, C9, 5)
        || reg->value == CPENC (3, 0, C9, C9, 6)
        || reg->value == CPENC (3, 0, C9, C9, 7)
        || reg->value == CPENC (3, 4, C9, C9, 0)
        || reg->value == CPENC (3, 5, C9, C9, 0))
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PROFILE))
     return FALSE;
  
   /* ARMv8.3 Pointer authentication keys.  */
   if ((reg->value == CPENC (3, 0, C2, C1, 0)
        || reg->value == CPENC (3, 0, C2, C1, 1)
        || reg->value == CPENC (3, 0, C2, C1, 2)
        || reg->value == CPENC (3, 0, C2, C1, 3)
        || reg->value == CPENC (3, 0, C2, C2, 0)
        || reg->value == CPENC (3, 0, C2, C2, 1)
        || reg->value == CPENC (3, 0, C2, C2, 2)
        || reg->value == CPENC (3, 0, C2, C2, 3)
        || reg->value == CPENC (3, 0, C2, C3, 0)
        || reg->value == CPENC (3, 0, C2, C3, 1))
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_3))
     return FALSE;
  
   /* SVE.  */
   if ((reg->value == CPENC (3, 0, C0, C4, 4)
        || reg->value == CPENC (3, 0, C1, C2, 0)
        || reg->value == CPENC (3, 4, C1, C2, 0)
        || reg->value == CPENC (3, 6, C1, C2, 0)
        || reg->value == CPENC (3, 5, C1, C2, 0)
        || reg->value == CPENC (3, 0, C0, C0, 7))
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SVE))
     return FALSE;
  
   /* ARMv8.4 features.  */
  
   /* PSTATE.DIT.  */
   if (reg->value == CPEN_ (3, C2, 5)
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
     return FALSE;
  
   /* Virtualization extensions.  */
   if ((reg->value == CPENC(3, 4, C2, C6, 2)
        || reg->value == CPENC(3, 4, C2, C6, 0)
        || reg->value == CPENC(3, 4, C14, C4, 0)
        || reg->value == CPENC(3, 4, C14, C4, 2)
        || reg->value == CPENC(3, 4, C14, C4, 1)
        || reg->value == CPENC(3, 4, C14, C5, 0)
        || reg->value == CPENC(3, 4, C14, C5, 2)
        || reg->value == CPENC(3, 4, C14, C5, 1)
        || reg->value == CPENC(3, 4, C1, C3, 1)
        || reg->value == CPENC(3, 4, C2, C2, 0))
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
     return FALSE;
  
   /* ARMv8.4 TLB instructions.  */
   if ((reg->value == CPENS (0, C8, C1, 0)
        || reg->value == CPENS (0, C8, C1, 1)
        || reg->value == CPENS (0, C8, C1, 2)
        || reg->value == CPENS (0, C8, C1, 3)
        || reg->value == CPENS (0, C8, C1, 5)
        || reg->value == CPENS (0, C8, C1, 7)
        || reg->value == CPENS (4, C8, C4, 0)
        || reg->value == CPENS (4, C8, C4, 4)
        || reg->value == CPENS (4, C8, C1, 1)
        || reg->value == CPENS (4, C8, C1, 5)
        || reg->value == CPENS (4, C8, C1, 6)
        || reg->value == CPENS (6, C8, C1, 1)
        || reg->value == CPENS (6, C8, C1, 5)
        || reg->value == CPENS (4, C8, C1, 0)
        || reg->value == CPENS (4, C8, C1, 4)
        || reg->value == CPENS (6, C8, C1, 0)
        || reg->value == CPENS (0, C8, C6, 1)
        || reg->value == CPENS (0, C8, C6, 3)
        || reg->value == CPENS (0, C8, C6, 5)
        || reg->value == CPENS (0, C8, C6, 7)
        || reg->value == CPENS (0, C8, C2, 1)
        || reg->value == CPENS (0, C8, C2, 3)
        || reg->value == CPENS (0, C8, C2, 5)
        || reg->value == CPENS (0, C8, C2, 7)
        || reg->value == CPENS (0, C8, C5, 1)
        || reg->value == CPENS (0, C8, C5, 3)
        || reg->value == CPENS (0, C8, C5, 5)
        || reg->value == CPENS (0, C8, C5, 7)
        || reg->value == CPENS (4, C8, C0, 2)
        || reg->value == CPENS (4, C8, C0, 6)
        || reg->value == CPENS (4, C8, C4, 2)
        || reg->value == CPENS (4, C8, C4, 6)
        || reg->value == CPENS (4, C8, C4, 3)
        || reg->value == CPENS (4, C8, C4, 7)
        || reg->value == CPENS (4, C8, C6, 1)
        || reg->value == CPENS (4, C8, C6, 5)
        || reg->value == CPENS (4, C8, C2, 1)
        || reg->value == CPENS (4, C8, C2, 5)
        || reg->value == CPENS (4, C8, C5, 1)
        || reg->value == CPENS (4, C8, C5, 5)
        || reg->value == CPENS (6, C8, C6, 1)
        || reg->value == CPENS (6, C8, C6, 5)
        || reg->value == CPENS (6, C8, C2, 1)
        || reg->value == CPENS (6, C8, C2, 5)
        || reg->value == CPENS (6, C8, C5, 1)
        || reg->value == CPENS (6, C8, C5, 5))
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
     return FALSE;
  
   return TRUE;
 }

References AARCH64_CPU_HAS_FEATURE, AARCH64_FEATURE_PAN, AARCH64_FEATURE_PROFILE, AARCH64_FEATURE_RAS, AARCH64_FEATURE_SVE, AARCH64_FEATURE_V8_1, AARCH64_FEATURE_V8_2, AARCH64_FEATURE_V8_3, AARCH64_FEATURE_V8_4, C0, C1, C10, C12, C13, C14, C2, C3, C4, C5, C6, C7, C8, C9, CPEN_, CPENC, CPENS, F_ARCHEXT, FALSE, features, reg, and TRUE.

◆ aarch64_wide_constant_p()

bfd_boolean aarch64_wide_constant_p	(	int64_t	value,
		int	is32,
		unsigned int *	shift_amount
	)

Definition at line 1033 of file aarch64-opc.c.

 {
   int amount;
  
   DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
  
   if (is32)
     {
       /* Allow all zeros or all ones in top 32-bits, so that
      32-bit constant expressions like ~0x80000000 are
      permitted.  */
       uint64_t ext = value;
       if (ext >> 32 != 0 && ext >> 32 != (uint64_t) 0xffffffff)
     /* Immediate out of range.  */
     return FALSE;
       value &= (int64_t) 0xffffffff;
     }
  
   /* first, try movz then movn */
   amount = -1;
   if ((value & ((int64_t) 0xffff << 0)) == value)
     amount = 0;
   else if ((value & ((int64_t) 0xffff << 16)) == value)
     amount = 16;
   else if (!is32 && (value & ((int64_t) 0xffff << 32)) == value)
     amount = 32;
   else if (!is32 && (value & ((int64_t) 0xffff << 48)) == value)
     amount = 48;
  
   if (amount == -1)
     {
       DEBUG_TRACE ("exit FALSE with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
       return FALSE;
     }
  
   if (shift_amount != NULL)
     *shift_amount = amount;
  
   DEBUG_TRACE ("exit TRUE with amount %d", amount);
  
   return TRUE;
 }

References DEBUG_TRACE, ext, FALSE, NULL, PRIx64, TRUE, and value.

Referenced by convert_movebitmask_to_mov(), convert_movewide_to_mov(), and operand_general_constraint_met_p().

◆ aarch64_zero_register_p()

int aarch64_zero_register_p ( const aarch64_opnd_info * operand )

Definition at line 572 of file aarch64-opc.c.

 {
   return ((aarch64_get_operand_class (operand->type)
        == AARCH64_OPND_CLASS_INT_REG)
       && !operand_maybe_stack_pointer (aarch64_operands + operand->type)
       && operand->reg.regno == 31);
 }

References aarch64_get_operand_class(), aarch64_operands, AARCH64_OPND_CLASS_INT_REG, and operand_maybe_stack_pointer().

◆ build_immediate_table()

static void build_immediate_table ( void )

static

Definition at line 1133 of file aarch64-opc.c.

 {
   uint32_t log_e, e, s, r, s_mask;
   uint64_t mask, imm;
   int nb_imms;
   int is64;
  
   nb_imms = 0;
   for (log_e = 1; log_e <= 6; log_e++)
     {
       /* Get element size.  */
       e = 1u << log_e;
       if (log_e == 6)
     {
       is64 = 1;
       mask = 0xffffffffffffffffull;
       s_mask = 0;
     }
       else
     {
       is64 = 0;
       mask = (1ull << e) - 1;
       /* log_e  s_mask
          1     ((1 << 4) - 1) << 2 = 111100
          2     ((1 << 3) - 1) << 3 = 111000
          3     ((1 << 2) - 1) << 4 = 110000
          4     ((1 << 1) - 1) << 5 = 100000
          5     ((1 << 0) - 1) << 6 = 000000  */
       s_mask = ((1u << (5 - log_e)) - 1) << (log_e + 1);
     }
       for (s = 0; s < e - 1; s++)
     for (r = 0; r < e; r++)
       {
         /* s+1 consecutive bits to 1 (s < 63) */
         imm = (1ull << (s + 1)) - 1;
         /* rotate right by r */
         if (r != 0)
           imm = (imm >> r) | ((imm << (e - r)) & mask);
         /* replicate the constant depending on SIMD size */
         switch (log_e)
           {
           case 1: imm = (imm <<  2) | imm;
         /* Fall through.  */
           case 2: imm = (imm <<  4) | imm;
         /* Fall through.  */
           case 3: imm = (imm <<  8) | imm;
         /* Fall through.  */
           case 4: imm = (imm << 16) | imm;
         /* Fall through.  */
           case 5: imm = (imm << 32) | imm;
         /* Fall through.  */
           case 6: break;
           default: abort ();
           }
         simd_immediates[nb_imms].imm = imm;
         simd_immediates[nb_imms].encoding =
           encode_immediate_bitfield(is64, s | s_mask, r);
         nb_imms++;
       }
     }
   assert (nb_imms == TOTAL_IMM_NB);
   qsort(simd_immediates, nb_imms,
     sizeof(simd_immediates[0]), simd_imm_encoding_cmp);
 }

References assert(), e, encode_immediate_bitfield(), simd_imm_encoding::encoding, imm, simd_imm_encoding::imm, mask, qsort(), r, s, simd_imm_encoding_cmp(), simd_immediates, and TOTAL_IMM_NB.

Referenced by aarch64_logical_immediate_p().

◆ encode_immediate_bitfield()

static int encode_immediate_bitfield	(	int	is64,
		uint32_t	s,
		uint32_t	r
	)

inlinestatic

Definition at line 1127 of file aarch64-opc.c.

 {
   return (is64 << 12) | (r << 6) | s;
 }

References r, and s.

Referenced by build_immediate_table().

◆ expand_fp_imm()

static uint64_t expand_fp_imm	(	int	size,
		uint32_t	imm8
	)

static

Definition at line 2859 of file aarch64-opc.c.

 {
   uint64_t imm = 0;
   uint32_t imm8_7, imm8_6_0, imm8_6, imm8_6_repl4;
  
   imm8_7 = (imm8 >> 7) & 0x01;  /* imm8<7>   */
   imm8_6_0 = imm8 & 0x7f;   /* imm8<6:0> */
   imm8_6 = imm8_6_0 >> 6;   /* imm8<6>   */
   imm8_6_repl4 = (imm8_6 << 3) | (imm8_6 << 2)
     | (imm8_6 << 1) | imm8_6;   /* Replicate(imm8<6>,4) */
   if (size == 8)
     {
       imm = (imm8_7 << (63-32))     /* imm8<7>  */
     | ((imm8_6 ^ 1) << (62-32)) /* NOT(imm8<6)  */
     | (imm8_6_repl4 << (58-32)) | (imm8_6 << (57-32))
     | (imm8_6 << (56-32)) | (imm8_6 << (55-32)) /* Replicate(imm8<6>,7) */
     | (imm8_6_0 << (48-32));    /* imm8<6>:imm8<5:0>    */
       imm <<= 32;
     }
   else if (size == 4 || size == 2)
     {
       imm = (imm8_7 << 31)  /* imm8<7>              */
     | ((imm8_6 ^ 1) << 30)  /* NOT(imm8<6>)         */
     | (imm8_6_repl4 << 26)  /* Replicate(imm8<6>,4) */
     | (imm8_6_0 << 19); /* imm8<6>:imm8<5:0>    */
     }
   else
     {
       /* An unsupported size.  */
       assert (0);
     }
  
   return imm;
 }

References assert(), and imm.

Referenced by aarch64_print_operand().

◆ fp_qualifier_p()

static bfd_boolean fp_qualifier_p ( enum aarch64_opnd_qualifier qualifier )

inlinestatic

Definition at line 117 of file aarch64-opc.c.

 {
   return ((qualifier >= AARCH64_OPND_QLF_S_B
       && qualifier <= AARCH64_OPND_QLF_S_Q) ? TRUE
       : FALSE);
 }

References AARCH64_OPND_QLF_S_B, AARCH64_OPND_QLF_S_Q, FALSE, and TRUE.

◆ get_64bit_int_reg_name()

static const char* get_64bit_int_reg_name	(	int	regno,
		int	sp_reg_p
	)

inlinestatic

Definition at line 2792 of file aarch64-opc.c.

 {
   const int has_zr = sp_reg_p ? 0 : 1;
   return int_reg[has_zr][1][regno];
 }

References int_reg.

Referenced by aarch64_print_operand().

◆ get_addr_sve_reg_name()

static const char* get_addr_sve_reg_name	(	int	regno,
		aarch64_opnd_qualifier_t	qualifier
	)

inlinestatic

Definition at line 2823 of file aarch64-opc.c.

 {
   assert (qualifier == AARCH64_OPND_QLF_S_S
       || qualifier == AARCH64_OPND_QLF_S_D);
   return sve_reg[qualifier == AARCH64_OPND_QLF_S_D][regno];
 }

References AARCH64_OPND_QLF_S_D, AARCH64_OPND_QLF_S_S, assert(), and sve_reg.

Referenced by aarch64_print_operand().

◆ get_cond_from_value()

const aarch64_cond* get_cond_from_value ( aarch64_insn value )

Definition at line 369 of file aarch64-opc.c.

 {
   assert (value < 16);
   return &aarch64_conds[(unsigned int) value];
 }

References aarch64_conds, assert(), int, and value.

Referenced by aarch64_ext_cond(), and do_special_decoding().

◆ get_data_pattern()

static enum data_pattern get_data_pattern ( const aarch64_opnd_qualifier_seq_t qualifiers )

static

Definition at line 133 of file aarch64-opc.c.

 {
   if (vector_qualifier_p (qualifiers[0]) == TRUE)
     {
       /* e.g. v.4s, v.4s, v.4s
        or v.4h, v.4h, v.h[3].  */
       if (qualifiers[0] == qualifiers[1]
       && vector_qualifier_p (qualifiers[2]) == TRUE
       && (aarch64_get_qualifier_esize (qualifiers[0])
           == aarch64_get_qualifier_esize (qualifiers[1]))
       && (aarch64_get_qualifier_esize (qualifiers[0])
           == aarch64_get_qualifier_esize (qualifiers[2])))
     return DP_VECTOR_3SAME;
       /* e.g. v.8h, v.8b, v.8b.
            or v.4s, v.4h, v.h[2].
        or v.8h, v.16b.  */
       if (vector_qualifier_p (qualifiers[1]) == TRUE
       && aarch64_get_qualifier_esize (qualifiers[0]) != 0
       && (aarch64_get_qualifier_esize (qualifiers[0])
           == aarch64_get_qualifier_esize (qualifiers[1]) << 1))
     return DP_VECTOR_LONG;
       /* e.g. v.8h, v.8h, v.8b.  */
       if (qualifiers[0] == qualifiers[1]
       && vector_qualifier_p (qualifiers[2]) == TRUE
       && aarch64_get_qualifier_esize (qualifiers[0]) != 0
       && (aarch64_get_qualifier_esize (qualifiers[0])
           == aarch64_get_qualifier_esize (qualifiers[2]) << 1)
       && (aarch64_get_qualifier_esize (qualifiers[0])
           == aarch64_get_qualifier_esize (qualifiers[1])))
     return DP_VECTOR_WIDE;
     }
   else if (fp_qualifier_p (qualifiers[0]) == TRUE)
     {
       /* e.g. SADDLV <V><d>, <Vn>.<T>.  */
       if (vector_qualifier_p (qualifiers[1]) == TRUE
       && qualifiers[2] == AARCH64_OPND_QLF_NIL)
     return DP_VECTOR_ACROSS_LANES;
     }
  
   return DP_UNKNOWN;
 }

Referenced by aarch64_select_operand_for_sizeq_field_coding().

◆ get_int_reg_name()

static const char* get_int_reg_name	(	int	regno,
		aarch64_opnd_qualifier_t	qualifier,
		int	sp_reg_p
	)

inlinestatic

Definition at line 2782 of file aarch64-opc.c.

 {
   const int has_zr = sp_reg_p ? 0 : 1;
   const int is_64 = aarch64_get_qualifier_esize (qualifier) == 4 ? 0 : 1;
   return int_reg[has_zr][is_64][regno];
 }

References aarch64_get_qualifier_esize(), and int_reg.

Referenced by aarch64_print_operand(), and get_offset_int_reg_name().

◆ get_inverted_cond()

const aarch64_cond* get_inverted_cond ( const aarch64_cond * cond )

Definition at line 376 of file aarch64-opc.c.

 {
   return &aarch64_conds[cond->value ^ 0x1];
 }

Referenced by convert_csinc_to_cset(), and convert_from_csel().

◆ get_lower_bound()

static int get_lower_bound ( aarch64_opnd_qualifier_t qualifier )

static

Definition at line 787 of file aarch64-opc.c.

 {
   assert (qualifier_value_in_range_constraint_p (qualifier) == TRUE);
   return aarch64_opnd_qualifiers[qualifier].data0;
 }

References aarch64_opnd_qualifiers, assert(), operand_qualifier_data::data0, qualifier_value_in_range_constraint_p(), and TRUE.

Referenced by operand_general_constraint_met_p().

◆ get_offset_int_reg_name()

static const char* get_offset_int_reg_name ( const aarch64_opnd_info * opnd )

inlinestatic

Definition at line 2802 of file aarch64-opc.c.

 {
   switch (opnd->shifter.kind)
     {
     case AARCH64_MOD_UXTW:
     case AARCH64_MOD_SXTW:
       return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_W, 0);
  
     case AARCH64_MOD_LSL:
     case AARCH64_MOD_SXTX:
       return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_X, 0);
  
     default:
       abort ();
     }
 }

References AARCH64_MOD_LSL, AARCH64_MOD_SXTW, AARCH64_MOD_SXTX, AARCH64_MOD_UXTW, AARCH64_OPND_QLF_W, AARCH64_OPND_QLF_X, aarch64_opnd_info::addr, get_int_reg_name(), aarch64_opnd_info::kind, and aarch64_opnd_info::shifter.

Referenced by aarch64_print_operand().

◆ get_upper_bound()

static int get_upper_bound ( aarch64_opnd_qualifier_t qualifier )

static

Definition at line 794 of file aarch64-opc.c.

 {
   assert (qualifier_value_in_range_constraint_p (qualifier) == TRUE);
   return aarch64_opnd_qualifiers[qualifier].data1;
 }

References aarch64_opnd_qualifiers, assert(), operand_qualifier_data::data1, qualifier_value_in_range_constraint_p(), and TRUE.

Referenced by operand_general_constraint_met_p().

◆ match_operands_qualifier()

static int match_operands_qualifier	(	aarch64_inst *	inst,
		bfd_boolean	update_p
	)

static

Definition at line 987 of file aarch64-opc.c.

 {
   int i, nops;
   aarch64_opnd_qualifier_seq_t qualifiers = {0};
  
   if (!aarch64_find_best_match (inst, inst->opcode->qualifiers_list, -1,
                    qualifiers))
     {
       DEBUG_TRACE ("matching FAIL");
       return 0;
     }
  
   if (inst->opcode->flags & F_STRICT)
     {
       /* Require an exact qualifier match, even for NIL qualifiers.  */
       nops = aarch64_num_of_operands (inst->opcode);
       for (i = 0; i < nops; ++i)
     if (inst->operands[i].qualifier != qualifiers[i])
       return FALSE;
     }
  
   /* Update the qualifiers.  */
   if (update_p == TRUE)
     for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
       {
     if (inst->opcode->operands[i] == AARCH64_OPND_NIL)
       break;
     DEBUG_TRACE_IF (inst->operands[i].qualifier != qualifiers[i],
             "update %s with %s for operand %d",
             aarch64_get_qualifier_name (inst->operands[i].qualifier),
             aarch64_get_qualifier_name (qualifiers[i]), i);
     inst->operands[i].qualifier = qualifiers[i];
       }
  
   DEBUG_TRACE ("matching SUCCESS");
   return 1;
 }

References aarch64_find_best_match(), aarch64_get_qualifier_name(), AARCH64_MAX_OPND_NUM, aarch64_num_of_operands(), AARCH64_OPND_NIL, DEBUG_TRACE, DEBUG_TRACE_IF, F_STRICT, FALSE, aarch64_opcode::flags, i, aarch64_inst::opcode, aarch64_opcode::operands, aarch64_inst::operands, aarch64_opnd_info::qualifier, aarch64_opcode::qualifiers_list, and TRUE.

Referenced by aarch64_match_operands_constraint().

◆ operand_also_qualified_p()

static int operand_also_qualified_p	(	const struct aarch64_opnd_info *	operand,
		aarch64_opnd_qualifier_t	target
	)

inlinestatic

Definition at line 585 of file aarch64-opc.c.

 {
   switch (operand->qualifier)
     {
     case AARCH64_OPND_QLF_W:
       if (target == AARCH64_OPND_QLF_WSP && aarch64_stack_pointer_p (operand))
     return 1;
       break;
     case AARCH64_OPND_QLF_X:
       if (target == AARCH64_OPND_QLF_SP && aarch64_stack_pointer_p (operand))
     return 1;
       break;
     case AARCH64_OPND_QLF_WSP:
       if (target == AARCH64_OPND_QLF_W
       && operand_maybe_stack_pointer (aarch64_operands + operand->type))
     return 1;
       break;
     case AARCH64_OPND_QLF_SP:
       if (target == AARCH64_OPND_QLF_X
       && operand_maybe_stack_pointer (aarch64_operands + operand->type))
     return 1;
       break;
     default:
       break;
     }
  
   return 0;
 }

References aarch64_operands, AARCH64_OPND_QLF_SP, AARCH64_OPND_QLF_W, AARCH64_OPND_QLF_WSP, AARCH64_OPND_QLF_X, aarch64_stack_pointer_p(), and operand_maybe_stack_pointer().

Referenced by aarch64_find_best_match().

◆ operand_general_constraint_met_p()

static int operand_general_constraint_met_p	(	const aarch64_opnd_info *	opnds,
		int	idx,
		enum aarch64_opnd	type,
		const aarch64_opcode *	opcode,
		aarch64_operand_error *	mismatch_detail
	)

static

Definition at line 1415 of file aarch64-opc.c.

 {
   unsigned num, modifiers, shift;
   unsigned char size;
   int64_t imm, min_value, max_value;
   uint64_t uvalue, mask;
   const aarch64_opnd_info *opnd = opnds + idx;
   aarch64_opnd_qualifier_t qualifier = opnd->qualifier;
  
   assert (opcode->operands[idx] == opnd->type && opnd->type == type);
  
   switch (aarch64_operands[type].op_class)
     {
     case AARCH64_OPND_CLASS_INT_REG:
       /* Check pair reg constraints for cas* instructions.  */
       if (type == AARCH64_OPND_PAIRREG)
     {
       assert (idx == 1 || idx == 3);
       if (opnds[idx - 1].reg.regno % 2 != 0)
         {
           set_syntax_error (mismatch_detail, idx - 1,
                 _("reg pair must start from even reg"));
           return 0;
         }
       if (opnds[idx].reg.regno != opnds[idx - 1].reg.regno + 1)
         {
           set_syntax_error (mismatch_detail, idx,
                 _("reg pair must be contiguous"));
           return 0;
         }
       break;
     }
  
       /* <Xt> may be optional in some IC and TLBI instructions.  */
       if (type == AARCH64_OPND_Rt_SYS)
     {
       assert (idx == 1 && (aarch64_get_operand_class (opnds[0].type)
                    == AARCH64_OPND_CLASS_SYSTEM));
       if (opnds[1].present
           && !aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
         {
           set_other_error (mismatch_detail, idx, _("extraneous register"));
           return 0;
         }
       if (!opnds[1].present
           && aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
         {
           set_other_error (mismatch_detail, idx, _("missing register"));
           return 0;
         }
     }
       switch (qualifier)
     {
     case AARCH64_OPND_QLF_WSP:
     case AARCH64_OPND_QLF_SP:
       if (!aarch64_stack_pointer_p (opnd))
         {
           set_other_error (mismatch_detail, idx,
                    _("stack pointer register expected"));
           return 0;
         }
       break;
     default:
       break;
     }
       break;
  
     case AARCH64_OPND_CLASS_SVE_REG:
       switch (type)
     {
     case AARCH64_OPND_SVE_Zm3_INDEX:
     case AARCH64_OPND_SVE_Zm3_22_INDEX:
     case AARCH64_OPND_SVE_Zm4_INDEX:
       size = get_operand_fields_width (get_operand_from_code (type));
       shift = get_operand_specific_data (&aarch64_operands[type]);
       mask = (1 << shift) - 1;
       if (opnd->reg.regno > mask)
         {
           assert (mask == 7 || mask == 15);
           set_other_error (mismatch_detail, idx,
                    mask == 15
                    ? _("z0-z15 expected")
                    : _("z0-z7 expected"));
           return 0;
         }
       mask = (1 << (size - shift)) - 1;
       if (!value_in_range_p (opnd->reglane.index, 0, mask))
         {
           set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, mask);
           return 0;
         }
       break;
  
     case AARCH64_OPND_SVE_Zn_INDEX:
       size = aarch64_get_qualifier_esize (opnd->qualifier);
       if (!value_in_range_p (opnd->reglane.index, 0, 64 / size - 1))
         {
           set_elem_idx_out_of_range_error (mismatch_detail, idx,
                            0, 64 / size - 1);
           return 0;
         }
       break;
  
     case AARCH64_OPND_SVE_ZnxN:
     case AARCH64_OPND_SVE_ZtxN:
       if (opnd->reglist.num_regs != get_opcode_dependent_value (opcode))
         {
           set_other_error (mismatch_detail, idx,
                    _("invalid register list"));
           return 0;
         }
       break;
  
     default:
       break;
     }
       break;
  
     case AARCH64_OPND_CLASS_PRED_REG:
       if (opnd->reg.regno >= 8
       && get_operand_fields_width (get_operand_from_code (type)) == 3)
     {
       set_other_error (mismatch_detail, idx, _("p0-p7 expected"));
       return 0;
     }
       break;
  
     case AARCH64_OPND_CLASS_COND:
       if (type == AARCH64_OPND_COND1
       && (opnds[idx].cond->value & 0xe) == 0xe)
     {
       /* Not allow AL or NV.  */
       set_syntax_error (mismatch_detail, idx, NULL);
     }
       break;
  
     case AARCH64_OPND_CLASS_ADDRESS:
       /* Check writeback.  */
       switch (opcode->iclass)
     {
     case ldst_pos:
     case ldst_unscaled:
     case ldstnapair_offs:
     case ldstpair_off:
     case ldst_unpriv:
       if (opnd->addr.writeback == 1)
         {
           set_syntax_error (mismatch_detail, idx,
                 _("unexpected address writeback"));
           return 0;
         }
       break;
     case ldst_imm10:
       if (opnd->addr.writeback == 1 && opnd->addr.preind != 1)
         {
           set_syntax_error (mismatch_detail, idx,
                 _("unexpected address writeback"));
           return 0;
         }
       break;
     case ldst_imm9:
     case ldstpair_indexed:
     case asisdlsep:
     case asisdlsop:
       if (opnd->addr.writeback == 0)
         {
           set_syntax_error (mismatch_detail, idx,
                 _("address writeback expected"));
           return 0;
         }
       break;
     default:
       assert (opnd->addr.writeback == 0);
       break;
     }
       switch (type)
     {
     case AARCH64_OPND_ADDR_SIMM7:
       /* Scaled signed 7 bits immediate offset.  */
       /* Get the size of the data element that is accessed, which may be
          different from that of the source register size,
          e.g. in strb/ldrb.  */
       size = aarch64_get_qualifier_esize (opnd->qualifier);
       if (!value_in_range_p (opnd->addr.offset.imm, -64 * size, 63 * size))
         {
           set_offset_out_of_range_error (mismatch_detail, idx,
                          -64 * size, 63 * size);
           return 0;
         }
       if (!value_aligned_p (opnd->addr.offset.imm, size))
         {
           set_unaligned_error (mismatch_detail, idx, size);
           return 0;
         }
       break;
     case AARCH64_OPND_ADDR_OFFSET:
     case AARCH64_OPND_ADDR_SIMM9:
       /* Unscaled signed 9 bits immediate offset.  */
       if (!value_in_range_p (opnd->addr.offset.imm, -256, 255))
         {
           set_offset_out_of_range_error (mismatch_detail, idx, -256, 255);
           return 0;
         }
       break;
  
     case AARCH64_OPND_ADDR_SIMM9_2:
       /* Unscaled signed 9 bits immediate offset, which has to be negative
          or unaligned.  */
       size = aarch64_get_qualifier_esize (qualifier);
       if ((value_in_range_p (opnd->addr.offset.imm, 0, 255)
            && !value_aligned_p (opnd->addr.offset.imm, size))
           || value_in_range_p (opnd->addr.offset.imm, -256, -1))
         return 1;
       set_other_error (mismatch_detail, idx,
                _("negative or unaligned offset expected"));
       return 0;
  
     case AARCH64_OPND_ADDR_SIMM10:
       /* Scaled signed 10 bits immediate offset.  */
       if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4088))
         {
           set_offset_out_of_range_error (mismatch_detail, idx, -4096, 4088);
           return 0;
         }
       if (!value_aligned_p (opnd->addr.offset.imm, 8))
         {
           set_unaligned_error (mismatch_detail, idx, 8);
           return 0;
         }
       break;
  
     case AARCH64_OPND_SIMD_ADDR_POST:
       /* AdvSIMD load/store multiple structures, post-index.  */
       assert (idx == 1);
       if (opnd->addr.offset.is_reg)
         {
           if (value_in_range_p (opnd->addr.offset.regno, 0, 30))
         return 1;
           else
         {
           set_other_error (mismatch_detail, idx,
                    _("invalid register offset"));
           return 0;
         }
         }
       else
         {
           const aarch64_opnd_info *prev = &opnds[idx-1];
           unsigned num_bytes; /* total number of bytes transferred.  */
           /* The opcode dependent area stores the number of elements in
          each structure to be loaded/stored.  */
           int is_ld1r = get_opcode_dependent_value (opcode) == 1;
           if (opcode->operands[0] == AARCH64_OPND_LVt_AL)
         /* Special handling of loading single structure to all lane.  */
         num_bytes = (is_ld1r ? 1 : prev->reglist.num_regs)
           * aarch64_get_qualifier_esize (prev->qualifier);
           else
         num_bytes = prev->reglist.num_regs
           * aarch64_get_qualifier_esize (prev->qualifier)
           * aarch64_get_qualifier_nelem (prev->qualifier);
           if ((int) num_bytes != opnd->addr.offset.imm)
         {
           set_other_error (mismatch_detail, idx,
                    _("invalid post-increment amount"));
           return 0;
         }
         }
       break;
  
     case AARCH64_OPND_ADDR_REGOFF:
       /* Get the size of the data element that is accessed, which may be
          different from that of the source register size,
          e.g. in strb/ldrb.  */
       size = aarch64_get_qualifier_esize (opnd->qualifier);
       /* It is either no shift or shift by the binary logarithm of SIZE.  */
       if (opnd->shifter.amount != 0
           && opnd->shifter.amount != (int)get_logsz (size))
         {
           set_other_error (mismatch_detail, idx,
                    _("invalid shift amount"));
           return 0;
         }
       /* Only UXTW, LSL, SXTW and SXTX are the accepted extending
          operators.  */
       switch (opnd->shifter.kind)
         {
         case AARCH64_MOD_UXTW:
         case AARCH64_MOD_LSL:
         case AARCH64_MOD_SXTW:
         case AARCH64_MOD_SXTX: break;
         default:
           set_other_error (mismatch_detail, idx,
                    _("invalid extend/shift operator"));
           return 0;
         }
       break;
  
     case AARCH64_OPND_ADDR_UIMM12:
       imm = opnd->addr.offset.imm;
       /* Get the size of the data element that is accessed, which may be
          different from that of the source register size,
          e.g. in strb/ldrb.  */
       size = aarch64_get_qualifier_esize (qualifier);
       if (!value_in_range_p (imm, 0, 4095 * size))
         {
           set_offset_out_of_range_error (mismatch_detail, idx,
                          0, 4095 * size);
           return 0;
         }
       if (!value_aligned_p (imm, size))
         {
           set_unaligned_error (mismatch_detail, idx, size);
           return 0;
         }
       break;
  
     case AARCH64_OPND_ADDR_PCREL14:
     case AARCH64_OPND_ADDR_PCREL19:
     case AARCH64_OPND_ADDR_PCREL21:
     case AARCH64_OPND_ADDR_PCREL26:
       imm = opnd->imm.value;
       if (operand_need_shift_by_two (get_operand_from_code (type)))
         {
           /* The offset value in a PC-relative branch instruction is alway
          4-byte aligned and is encoded without the lowest 2 bits.  */
           if (!value_aligned_p (imm, 4))
         {
           set_unaligned_error (mismatch_detail, idx, 4);
           return 0;
         }
           /* Right shift by 2 so that we can carry out the following check
          canonically.  */
           imm >>= 2;
         }
       size = get_operand_fields_width (get_operand_from_code (type));
       if (!value_fit_signed_field_p (imm, size))
         {
           set_other_error (mismatch_detail, idx,
                    _("immediate out of range"));
           return 0;
         }
       break;
  
     case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
     case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
     case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
     case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL:
       min_value = -8;
       max_value = 7;
     sve_imm_offset_vl:
       assert (!opnd->addr.offset.is_reg);
       assert (opnd->addr.preind);
       num = 1 + get_operand_specific_data (&aarch64_operands[type]);
       min_value *= num;
       max_value *= num;
       if ((opnd->addr.offset.imm != 0 && !opnd->shifter.operator_present)
           || (opnd->shifter.operator_present
           && opnd->shifter.kind != AARCH64_MOD_MUL_VL))
         {
           set_other_error (mismatch_detail, idx,
                    _("invalid addressing mode"));
           return 0;
         }
       if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
         {
           set_offset_out_of_range_error (mismatch_detail, idx,
                          min_value, max_value);
           return 0;
         }
       if (!value_aligned_p (opnd->addr.offset.imm, num))
         {
           set_unaligned_error (mismatch_detail, idx, num);
           return 0;
         }
       break;
  
     case AARCH64_OPND_SVE_ADDR_RI_S6xVL:
       min_value = -32;
       max_value = 31;
       goto sve_imm_offset_vl;
  
     case AARCH64_OPND_SVE_ADDR_RI_S9xVL:
       min_value = -256;
       max_value = 255;
       goto sve_imm_offset_vl;
  
     case AARCH64_OPND_SVE_ADDR_RI_U6:
     case AARCH64_OPND_SVE_ADDR_RI_U6x2:
     case AARCH64_OPND_SVE_ADDR_RI_U6x4:
     case AARCH64_OPND_SVE_ADDR_RI_U6x8:
       min_value = 0;
       max_value = 63;
     sve_imm_offset:
       assert (!opnd->addr.offset.is_reg);
       assert (opnd->addr.preind);
       num = 1 << get_operand_specific_data (&aarch64_operands[type]);
       min_value *= num;
       max_value *= num;
       if (opnd->shifter.operator_present
           || opnd->shifter.amount_present)
         {
           set_other_error (mismatch_detail, idx,
                    _("invalid addressing mode"));
           return 0;
         }
       if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
         {
           set_offset_out_of_range_error (mismatch_detail, idx,
                          min_value, max_value);
           return 0;
         }
       if (!value_aligned_p (opnd->addr.offset.imm, num))
         {
           set_unaligned_error (mismatch_detail, idx, num);
           return 0;
         }
       break;
  
     case AARCH64_OPND_SVE_ADDR_RI_S4x16:
       min_value = -8;
       max_value = 7;
       goto sve_imm_offset;
  
     case AARCH64_OPND_SVE_ADDR_R:
     case AARCH64_OPND_SVE_ADDR_RR:
     case AARCH64_OPND_SVE_ADDR_RR_LSL1:
     case AARCH64_OPND_SVE_ADDR_RR_LSL2:
     case AARCH64_OPND_SVE_ADDR_RR_LSL3:
     case AARCH64_OPND_SVE_ADDR_RX:
     case AARCH64_OPND_SVE_ADDR_RX_LSL1:
     case AARCH64_OPND_SVE_ADDR_RX_LSL2:
     case AARCH64_OPND_SVE_ADDR_RX_LSL3:
     case AARCH64_OPND_SVE_ADDR_RZ:
     case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
     case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
     case AARCH64_OPND_SVE_ADDR_RZ_LSL3:
       modifiers = 1 << AARCH64_MOD_LSL;
     sve_rr_operand:
       assert (opnd->addr.offset.is_reg);
       assert (opnd->addr.preind);
       if ((aarch64_operands[type].flags & OPD_F_NO_ZR) != 0
           && opnd->addr.offset.regno == 31)
         {
           set_other_error (mismatch_detail, idx,
                    _("index register xzr is not allowed"));
           return 0;
         }
       if (((1 << opnd->shifter.kind) & modifiers) == 0
           || (opnd->shifter.amount
           != get_operand_specific_data (&aarch64_operands[type])))
         {
           set_other_error (mismatch_detail, idx,
                    _("invalid addressing mode"));
           return 0;
         }
       break;
  
     case AARCH64_OPND_SVE_ADDR_RZ_XTW_14:
     case AARCH64_OPND_SVE_ADDR_RZ_XTW_22:
     case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14:
     case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22:
     case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14:
     case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22:
     case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14:
     case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22:
       modifiers = (1 << AARCH64_MOD_SXTW) | (1 << AARCH64_MOD_UXTW);
       goto sve_rr_operand;
  
     case AARCH64_OPND_SVE_ADDR_ZI_U5:
     case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
     case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
     case AARCH64_OPND_SVE_ADDR_ZI_U5x8:
       min_value = 0;
       max_value = 31;
       goto sve_imm_offset;
  
     case AARCH64_OPND_SVE_ADDR_ZZ_LSL:
       modifiers = 1 << AARCH64_MOD_LSL;
     sve_zz_operand:
       assert (opnd->addr.offset.is_reg);
       assert (opnd->addr.preind);
       if (((1 << opnd->shifter.kind) & modifiers) == 0
           || opnd->shifter.amount < 0
           || opnd->shifter.amount > 3)
         {
           set_other_error (mismatch_detail, idx,
                    _("invalid addressing mode"));
           return 0;
         }
       break;
  
     case AARCH64_OPND_SVE_ADDR_ZZ_SXTW:
       modifiers = (1 << AARCH64_MOD_SXTW);
       goto sve_zz_operand;
  
     case AARCH64_OPND_SVE_ADDR_ZZ_UXTW:
       modifiers = 1 << AARCH64_MOD_UXTW;
       goto sve_zz_operand;
  
     default:
       break;
     }
       break;
  
     case AARCH64_OPND_CLASS_SIMD_REGLIST:
       if (type == AARCH64_OPND_LEt)
     {
       /* Get the upper bound for the element index.  */
       num = 16 / aarch64_get_qualifier_esize (qualifier) - 1;
       if (!value_in_range_p (opnd->reglist.index, 0, num))
         {
           set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, num);
           return 0;
         }
     }
       /* The opcode dependent area stores the number of elements in
      each structure to be loaded/stored.  */
       num = get_opcode_dependent_value (opcode);
       switch (type)
     {
     case AARCH64_OPND_LVt:
       assert (num >= 1 && num <= 4);
       /* Unless LD1/ST1, the number of registers should be equal to that
          of the structure elements.  */
       if (num != 1 && opnd->reglist.num_regs != num)
         {
           set_reg_list_error (mismatch_detail, idx, num);
           return 0;
         }
       break;
     case AARCH64_OPND_LVt_AL:
     case AARCH64_OPND_LEt:
       assert (num >= 1 && num <= 4);
       /* The number of registers should be equal to that of the structure
          elements.  */
       if (opnd->reglist.num_regs != num)
         {
           set_reg_list_error (mismatch_detail, idx, num);
           return 0;
         }
       break;
     default:
       break;
     }
       break;
  
     case AARCH64_OPND_CLASS_IMMEDIATE:
       /* Constraint check on immediate operand.  */
       imm = opnd->imm.value;
       /* E.g. imm_0_31 constrains value to be 0..31.  */
       if (qualifier_value_in_range_constraint_p (qualifier)
       && !value_in_range_p (imm, get_lower_bound (qualifier),
                 get_upper_bound (qualifier)))
     {
       set_imm_out_of_range_error (mismatch_detail, idx,
                       get_lower_bound (qualifier),
                       get_upper_bound (qualifier));
       return 0;
     }
  
       switch (type)
     {
     case AARCH64_OPND_AIMM:
       if (opnd->shifter.kind != AARCH64_MOD_LSL)
         {
           set_other_error (mismatch_detail, idx,
                    _("invalid shift operator"));
           return 0;
         }
       if (opnd->shifter.amount != 0 && opnd->shifter.amount != 12)
         {
           set_other_error (mismatch_detail, idx,
                    _("shift amount must be 0 or 12"));
           return 0;
         }
       if (!value_fit_unsigned_field_p (opnd->imm.value, 12))
         {
           set_other_error (mismatch_detail, idx,
                    _("immediate out of range"));
           return 0;
         }
       break;
  
     case AARCH64_OPND_HALF:
       assert (idx == 1 && opnds[0].type == AARCH64_OPND_Rd);
       if (opnd->shifter.kind != AARCH64_MOD_LSL)
         {
           set_other_error (mismatch_detail, idx,
                    _("invalid shift operator"));
           return 0;
         }
       size = aarch64_get_qualifier_esize (opnds[0].qualifier);
       if (!value_aligned_p (opnd->shifter.amount, 16))
         {
           set_other_error (mismatch_detail, idx,
                    _("shift amount must be a multiple of 16"));
           return 0;
         }
       if (!value_in_range_p (opnd->shifter.amount, 0, size * 8 - 16))
         {
           set_sft_amount_out_of_range_error (mismatch_detail, idx,
                          0, size * 8 - 16);
           return 0;
         }
       if (opnd->imm.value < 0)
         {
           set_other_error (mismatch_detail, idx,
                    _("negative immediate value not allowed"));
           return 0;
         }
       if (!value_fit_unsigned_field_p (opnd->imm.value, 16))
         {
           set_other_error (mismatch_detail, idx,
                    _("immediate out of range"));
           return 0;
         }
       break;
  
     case AARCH64_OPND_IMM_MOV:
         {
           int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
           imm = opnd->imm.value;
           assert (idx == 1);
           switch (opcode->op)
         {
         case OP_MOV_IMM_WIDEN:
           imm = ~imm;
           /* Fall through.  */
         case OP_MOV_IMM_WIDE:
           if (!aarch64_wide_constant_p (imm, esize == 4, NULL))
             {
               set_other_error (mismatch_detail, idx,
                        _("immediate out of range"));
               return 0;
             }
           break;
         case OP_MOV_IMM_LOG:
           if (!aarch64_logical_immediate_p (imm, esize, NULL))
             {
               set_other_error (mismatch_detail, idx,
                        _("immediate out of range"));
               return 0;
             }
           break;
         default:
           assert (0);
           return 0;
         }
         }
       break;
  
     case AARCH64_OPND_NZCV:
     case AARCH64_OPND_CCMP_IMM:
     case AARCH64_OPND_EXCEPTION:
     case AARCH64_OPND_UIMM4:
     case AARCH64_OPND_UIMM7:
     case AARCH64_OPND_UIMM3_OP1:
     case AARCH64_OPND_UIMM3_OP2:
     case AARCH64_OPND_SVE_UIMM3:
     case AARCH64_OPND_SVE_UIMM7:
     case AARCH64_OPND_SVE_UIMM8:
     case AARCH64_OPND_SVE_UIMM8_53:
       size = get_operand_fields_width (get_operand_from_code (type));
       assert (size < 32);
       if (!value_fit_unsigned_field_p (opnd->imm.value, size))
         {
           set_imm_out_of_range_error (mismatch_detail, idx, 0,
                       (1 << size) - 1);
           return 0;
         }
       break;
  
     case AARCH64_OPND_SIMM5:
     case AARCH64_OPND_SVE_SIMM5:
     case AARCH64_OPND_SVE_SIMM5B:
     case AARCH64_OPND_SVE_SIMM6:
     case AARCH64_OPND_SVE_SIMM8:
       size = get_operand_fields_width (get_operand_from_code (type));
       assert (size < 32);
       if (!value_fit_signed_field_p (opnd->imm.value, size))
         {
           set_imm_out_of_range_error (mismatch_detail, idx,
                       -(1 << (size - 1)),
                       (1 << (size - 1)) - 1);
           return 0;
         }
       break;
  
     case AARCH64_OPND_WIDTH:
       assert (idx > 1 && opnds[idx-1].type == AARCH64_OPND_IMM
           && opnds[0].type == AARCH64_OPND_Rd);
       size = get_upper_bound (qualifier);
       if (opnd->imm.value + opnds[idx-1].imm.value > size)
         /* lsb+width <= reg.size  */
         {
           set_imm_out_of_range_error (mismatch_detail, idx, 1,
                       size - opnds[idx-1].imm.value);
           return 0;
         }
       break;
  
     case AARCH64_OPND_LIMM:
     case AARCH64_OPND_SVE_LIMM:
       {
         int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
         uint64_t uimm = opnd->imm.value;
         if (opcode->op == OP_BIC)
           uimm = ~uimm;
         if (!aarch64_logical_immediate_p (uimm, esize, NULL))
           {
         set_other_error (mismatch_detail, idx,
                  _("immediate out of range"));
         return 0;
           }
       }
       break;
  
     case AARCH64_OPND_IMM0:
     case AARCH64_OPND_FPIMM0:
       if (opnd->imm.value != 0)
         {
           set_other_error (mismatch_detail, idx,
                    _("immediate zero expected"));
           return 0;
         }
       break;
  
     case AARCH64_OPND_IMM_ROT1:
     case AARCH64_OPND_IMM_ROT2:
     case AARCH64_OPND_SVE_IMM_ROT2:
       if (opnd->imm.value != 0
           && opnd->imm.value != 90
           && opnd->imm.value != 180
           && opnd->imm.value != 270)
         {
           set_other_error (mismatch_detail, idx,
                    _("rotate expected to be 0, 90, 180 or 270"));
           return 0;
         }
       break;
  
     case AARCH64_OPND_IMM_ROT3:
     case AARCH64_OPND_SVE_IMM_ROT1:
       if (opnd->imm.value != 90 && opnd->imm.value != 270)
         {
           set_other_error (mismatch_detail, idx,
                    _("rotate expected to be 90 or 270"));
           return 0;
         }
       break;
  
     case AARCH64_OPND_SHLL_IMM:
       assert (idx == 2);
       size = 8 * aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
       if (opnd->imm.value != size)
         {
           set_other_error (mismatch_detail, idx,
                    _("invalid shift amount"));
           return 0;
         }
       break;
  
     case AARCH64_OPND_IMM_VLSL:
       size = aarch64_get_qualifier_esize (qualifier);
       if (!value_in_range_p (opnd->imm.value, 0, size * 8 - 1))
         {
           set_imm_out_of_range_error (mismatch_detail, idx, 0,
                       size * 8 - 1);
           return 0;
         }
       break;
  
     case AARCH64_OPND_IMM_VLSR:
       size = aarch64_get_qualifier_esize (qualifier);
       if (!value_in_range_p (opnd->imm.value, 1, size * 8))
         {
           set_imm_out_of_range_error (mismatch_detail, idx, 1, size * 8);
           return 0;
         }
       break;
  
     case AARCH64_OPND_SIMD_IMM:
     case AARCH64_OPND_SIMD_IMM_SFT:
       /* Qualifier check.  */
       switch (qualifier)
         {
         case AARCH64_OPND_QLF_LSL:
           if (opnd->shifter.kind != AARCH64_MOD_LSL)
         {
           set_other_error (mismatch_detail, idx,
                    _("invalid shift operator"));
           return 0;
         }
           break;
         case AARCH64_OPND_QLF_MSL:
           if (opnd->shifter.kind != AARCH64_MOD_MSL)
         {
           set_other_error (mismatch_detail, idx,
                    _("invalid shift operator"));
           return 0;
         }
           break;
         case AARCH64_OPND_QLF_NIL:
           if (opnd->shifter.kind != AARCH64_MOD_NONE)
         {
           set_other_error (mismatch_detail, idx,
                    _("shift is not permitted"));
           return 0;
         }
           break;
         default:
           assert (0);
           return 0;
         }
       /* Is the immediate valid?  */
       assert (idx == 1);
       if (aarch64_get_qualifier_esize (opnds[0].qualifier) != 8)
         {
           /* uimm8 or simm8 */
           if (!value_in_range_p (opnd->imm.value, -128, 255))
         {
           set_imm_out_of_range_error (mismatch_detail, idx, -128, 255);
           return 0;
         }
         }
       else if (aarch64_shrink_expanded_imm8 (opnd->imm.value) < 0)
         {
           /* uimm64 is not
          'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeee
          ffffffffgggggggghhhhhhhh'.  */
           set_other_error (mismatch_detail, idx,
                    _("invalid value for immediate"));
           return 0;
         }
       /* Is the shift amount valid?  */
       switch (opnd->shifter.kind)
         {
         case AARCH64_MOD_LSL:
           size = aarch64_get_qualifier_esize (opnds[0].qualifier);
           if (!value_in_range_p (opnd->shifter.amount, 0, (size - 1) * 8))
         {
           set_sft_amount_out_of_range_error (mismatch_detail, idx, 0,
                              (size - 1) * 8);
           return 0;
         }
           if (!value_aligned_p (opnd->shifter.amount, 8))
         {
           set_unaligned_error (mismatch_detail, idx, 8);
           return 0;
         }
           break;
         case AARCH64_MOD_MSL:
           /* Only 8 and 16 are valid shift amount.  */
           if (opnd->shifter.amount != 8 && opnd->shifter.amount != 16)
         {
           set_other_error (mismatch_detail, idx,
                    _("shift amount must be 0 or 16"));
           return 0;
         }
           break;
         default:
           if (opnd->shifter.kind != AARCH64_MOD_NONE)
         {
           set_other_error (mismatch_detail, idx,
                    _("invalid shift operator"));
           return 0;
         }
           break;
         }
       break;
  
     case AARCH64_OPND_FPIMM:
     case AARCH64_OPND_SIMD_FPIMM:
     case AARCH64_OPND_SVE_FPIMM8:
       if (opnd->imm.is_fp == 0)
         {
           set_other_error (mismatch_detail, idx,
                    _("floating-point immediate expected"));
           return 0;
         }
       /* The value is expected to be an 8-bit floating-point constant with
          sign, 3-bit exponent and normalized 4 bits of precision, encoded
          in "a:b:c:d:e:f:g:h" or FLD_imm8 (depending on the type of the
          instruction).  */
       if (!value_in_range_p (opnd->imm.value, 0, 255))
         {
           set_other_error (mismatch_detail, idx,
                    _("immediate out of range"));
           return 0;
         }
       if (opnd->shifter.kind != AARCH64_MOD_NONE)
         {
           set_other_error (mismatch_detail, idx,
                    _("invalid shift operator"));
           return 0;
         }
       break;
  
     case AARCH64_OPND_SVE_AIMM:
       min_value = 0;
     sve_aimm:
       assert (opnd->shifter.kind == AARCH64_MOD_LSL);
       size = aarch64_get_qualifier_esize (opnds[0].qualifier);
       mask = ~((uint64_t) -1 << (size * 4) << (size * 4));
       uvalue = opnd->imm.value;
       shift = opnd->shifter.amount;
       if (size == 1)
         {
           if (shift != 0)
         {
           set_other_error (mismatch_detail, idx,
                    _("no shift amount allowed for"
                      " 8-bit constants"));
           return 0;
         }
         }
       else
         {
           if (shift != 0 && shift != 8)
         {
           set_other_error (mismatch_detail, idx,
                    _("shift amount must be 0 or 8"));
           return 0;
         }
           if (shift == 0 && (uvalue & 0xff) == 0)
         {
           shift = 8;
           uvalue = (int64_t) uvalue / 256;
         }
         }
       mask >>= shift;
       if ((uvalue & mask) != uvalue && (uvalue | ~mask) != uvalue)
         {
           set_other_error (mismatch_detail, idx,
                    _("immediate too big for element size"));
           return 0;
         }
       uvalue = (uvalue - min_value) & mask;
       if (uvalue > 0xff)
         {
           set_other_error (mismatch_detail, idx,
                    _("invalid arithmetic immediate"));
           return 0;
         }
       break;
  
     case AARCH64_OPND_SVE_ASIMM:
       min_value = -128;
       goto sve_aimm;
  
     case AARCH64_OPND_SVE_I1_HALF_ONE:
       assert (opnd->imm.is_fp);
       if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x3f800000)
         {
           set_other_error (mismatch_detail, idx,
                    _("floating-point value must be 0.5 or 1.0"));
           return 0;
         }
       break;
  
     case AARCH64_OPND_SVE_I1_HALF_TWO:
       assert (opnd->imm.is_fp);
       if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x40000000)
         {
           set_other_error (mismatch_detail, idx,
                    _("floating-point value must be 0.5 or 2.0"));
           return 0;
         }
       break;
  
     case AARCH64_OPND_SVE_I1_ZERO_ONE:
       assert (opnd->imm.is_fp);
       if (opnd->imm.value != 0 && opnd->imm.value != 0x3f800000)
         {
           set_other_error (mismatch_detail, idx,
                    _("floating-point value must be 0.0 or 1.0"));
           return 0;
         }
       break;
  
     case AARCH64_OPND_SVE_INV_LIMM:
       {
         int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
         uint64_t uimm = ~opnd->imm.value;
         if (!aarch64_logical_immediate_p (uimm, esize, NULL))
           {
         set_other_error (mismatch_detail, idx,
                  _("immediate out of range"));
         return 0;
           }
       }
       break;
  
     case AARCH64_OPND_SVE_LIMM_MOV:
       {
         int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
         uint64_t uimm = opnd->imm.value;
         if (!aarch64_logical_immediate_p (uimm, esize, NULL))
           {
         set_other_error (mismatch_detail, idx,
                  _("immediate out of range"));
         return 0;
           }
         if (!aarch64_sve_dupm_mov_immediate_p (uimm, esize))
           {
         set_other_error (mismatch_detail, idx,
                  _("invalid replicated MOV immediate"));
         return 0;
           }
       }
       break;
  
     case AARCH64_OPND_SVE_PATTERN_SCALED:
       assert (opnd->shifter.kind == AARCH64_MOD_MUL);
       if (!value_in_range_p (opnd->shifter.amount, 1, 16))
         {
           set_multiplier_out_of_range_error (mismatch_detail, idx, 1, 16);
           return 0;
         }
       break;
  
     case AARCH64_OPND_SVE_SHLIMM_PRED:
     case AARCH64_OPND_SVE_SHLIMM_UNPRED:
       size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
       if (!value_in_range_p (opnd->imm.value, 0, 8 * size - 1))
         {
           set_imm_out_of_range_error (mismatch_detail, idx,
                       0, 8 * size - 1);
           return 0;
         }
       break;
  
     case AARCH64_OPND_SVE_SHRIMM_PRED:
     case AARCH64_OPND_SVE_SHRIMM_UNPRED:
       size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
       if (!value_in_range_p (opnd->imm.value, 1, 8 * size))
         {
           set_imm_out_of_range_error (mismatch_detail, idx, 1, 8 * size);
           return 0;
         }
       break;
  
     default:
       break;
     }
       break;
  
     case AARCH64_OPND_CLASS_SYSTEM:
       switch (type)
     {
     case AARCH64_OPND_PSTATEFIELD:
       assert (idx == 0 && opnds[1].type == AARCH64_OPND_UIMM4);
       /* MSR UAO, #uimm4
          MSR PAN, #uimm4
          The immediate must be #0 or #1.  */
       if ((opnd->pstatefield == 0x03    /* UAO.  */
            || opnd->pstatefield == 0x04 /* PAN.  */
            || opnd->pstatefield == 0x1a)    /* DIT.  */
           && opnds[1].imm.value > 1)
         {
           set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
           return 0;
         }
       /* MSR SPSel, #uimm4
          Uses uimm4 as a control value to select the stack pointer: if
          bit 0 is set it selects the current exception level's stack
          pointer, if bit 0 is clear it selects shared EL0 stack pointer.
          Bits 1 to 3 of uimm4 are reserved and should be zero.  */
       if (opnd->pstatefield == 0x05 /* spsel */ && opnds[1].imm.value > 1)
         {
           set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
           return 0;
         }
       break;
     default:
       break;
     }
       break;
  
     case AARCH64_OPND_CLASS_SIMD_ELEMENT:
       /* Get the upper bound for the element index.  */
       if (opcode->op == OP_FCMLA_ELEM)
     /* FCMLA index range depends on the vector size of other operands
        and is halfed because complex numbers take two elements.  */
     num = aarch64_get_qualifier_nelem (opnds[0].qualifier)
           * aarch64_get_qualifier_esize (opnds[0].qualifier) / 2;
       else
     num = 16;
       num = num / aarch64_get_qualifier_esize (qualifier) - 1;
  
       /* Index out-of-range.  */
       if (!value_in_range_p (opnd->reglane.index, 0, num))
     {
       set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, num);
       return 0;
     }
       /* SMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>].
      <Vm>   Is the vector register (V0-V31) or (V0-V15), whose
      number is encoded in "size:M:Rm":
      size   <Vm>
      00     RESERVED
      01     0:Rm
      10     M:Rm
      11     RESERVED  */
       if (type == AARCH64_OPND_Em16 && qualifier == AARCH64_OPND_QLF_S_H
       && !value_in_range_p (opnd->reglane.regno, 0, 15))
     {
       set_regno_out_of_range_error (mismatch_detail, idx, 0, 15);
       return 0;
     }
       break;
  
     case AARCH64_OPND_CLASS_MODIFIED_REG:
       assert (idx == 1 || idx == 2);
       switch (type)
     {
     case AARCH64_OPND_Rm_EXT:
       if (!aarch64_extend_operator_p (opnd->shifter.kind)
           && opnd->shifter.kind != AARCH64_MOD_LSL)
         {
           set_other_error (mismatch_detail, idx,
                    _("extend operator expected"));
           return 0;
         }
       /* It is not optional unless at least one of "Rd" or "Rn" is '11111'
          (i.e. SP), in which case it defaults to LSL. The LSL alias is
          only valid when "Rd" or "Rn" is '11111', and is preferred in that
          case.  */
       if (!aarch64_stack_pointer_p (opnds + 0)
           && (idx != 2 || !aarch64_stack_pointer_p (opnds + 1)))
         {
           if (!opnd->shifter.operator_present)
         {
           set_other_error (mismatch_detail, idx,
                    _("missing extend operator"));
           return 0;
         }
           else if (opnd->shifter.kind == AARCH64_MOD_LSL)
         {
           set_other_error (mismatch_detail, idx,
                    _("'LSL' operator not allowed"));
           return 0;
         }
         }
       assert (opnd->shifter.operator_present    /* Default to LSL.  */
           || opnd->shifter.kind == AARCH64_MOD_LSL);
       if (!value_in_range_p (opnd->shifter.amount, 0, 4))
         {
           set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, 4);
           return 0;
         }
       /* In the 64-bit form, the final register operand is written as Wm
          for all but the (possibly omitted) UXTX/LSL and SXTX
          operators.
          N.B. GAS allows X register to be used with any operator as a
          programming convenience.  */
       if (qualifier == AARCH64_OPND_QLF_X
           && opnd->shifter.kind != AARCH64_MOD_LSL
           && opnd->shifter.kind != AARCH64_MOD_UXTX
           && opnd->shifter.kind != AARCH64_MOD_SXTX)
         {
           set_other_error (mismatch_detail, idx, _("W register expected"));
           return 0;
         }
       break;
  
     case AARCH64_OPND_Rm_SFT:
       /* ROR is not available to the shifted register operand in
          arithmetic instructions.  */
       if (!aarch64_shift_operator_p (opnd->shifter.kind))
         {
           set_other_error (mismatch_detail, idx,
                    _("shift operator expected"));
           return 0;
         }
       if (opnd->shifter.kind == AARCH64_MOD_ROR
           && opcode->iclass != log_shift)
         {
           set_other_error (mismatch_detail, idx,
                    _("'ROR' operator not allowed"));
           return 0;
         }
       num = qualifier == AARCH64_OPND_QLF_W ? 31 : 63;
       if (!value_in_range_p (opnd->shifter.amount, 0, num))
         {
           set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, num);
           return 0;
         }
       break;
  
     default:
       break;
     }
       break;
  
     default:
       break;
     }
  
   return 1;
 }

Referenced by aarch64_match_operands_constraint().

◆ operand_variant_qualifier_p()

static bfd_boolean operand_variant_qualifier_p ( aarch64_opnd_qualifier_t qualifier )

inlinestatic

Definition at line 744 of file aarch64-opc.c.

 {
   return (aarch64_opnd_qualifiers[qualifier].kind == OQK_OPD_VARIANT)
     ? TRUE : FALSE;
 }

References aarch64_opnd_qualifiers, FALSE, operand_qualifier_data::kind, OQK_OPD_VARIANT, and TRUE.

Referenced by aarch64_get_qualifier_esize(), aarch64_get_qualifier_nelem(), and aarch64_get_qualifier_standard_value().

◆ print_immediate_offset_address()

static void print_immediate_offset_address	(	char *	buf,
		size_t	size,
		const aarch64_opnd_info *	opnd,
		const char *	base
	)

static

Definition at line 2957 of file aarch64-opc.c.

 {
   if (opnd->addr.writeback)
     {
       if (opnd->addr.preind)
     snprintf (buf, size, "[%s, #%d]!", base, opnd->addr.offset.imm);
       else
     snprintf (buf, size, "[%s], #%d", base, opnd->addr.offset.imm);
     }
   else
     {
       if (opnd->shifter.operator_present)
     {
       assert (opnd->shifter.kind == AARCH64_MOD_MUL_VL);
       snprintf (buf, size, "[%s, #%d, mul vl]",
             base, opnd->addr.offset.imm);
     }
       else if (opnd->addr.offset.imm)
     snprintf (buf, size, "[%s, #%d]", base, opnd->addr.offset.imm);
       else
     snprintf (buf, size, "[%s]", base);
     }
 }

References AARCH64_MOD_MUL_VL, aarch64_opnd_info::addr, assert(), aarch64_opnd_info::kind, aarch64_opnd_info::operator_present, aarch64_opnd_info::shifter, and snprintf.

Referenced by aarch64_print_operand().

◆ print_register_list()

static void print_register_list	(	char *	buf,
		size_t	size,
		const aarch64_opnd_info *	opnd,
		const char *	prefix
	)

static

Definition at line 2898 of file aarch64-opc.c.

 {
   const int num_regs = opnd->reglist.num_regs;
   const int first_reg = opnd->reglist.first_regno;
   const int last_reg = (first_reg + num_regs - 1) & 0x1f;
   const char *qlf_name = aarch64_get_qualifier_name (opnd->qualifier);
   char tb[8];   /* Temporary buffer.  */
  
   assert (opnd->type != AARCH64_OPND_LEt || opnd->reglist.has_index);
   assert (num_regs >= 1 && num_regs <= 4);
  
   /* Prepare the index if any.  */
   if (opnd->reglist.has_index)
     /* PR 21096: The %100 is to silence a warning about possible truncation.  */
     snprintf (tb, 8, "[%" PRIi64 "]", (opnd->reglist.index % 100));
   else
     tb[0] = '\0';
  
   /* The hyphenated form is preferred for disassembly if there are
      more than two registers in the list, and the register numbers
      are monotonically increasing in increments of one.  */
   if (num_regs > 2 && last_reg > first_reg)
     snprintf (buf, size, "{%s%d.%s-%s%d.%s}%s", prefix, first_reg, qlf_name,
           prefix, last_reg, qlf_name, tb);
   else
     {
       const int reg0 = first_reg;
       const int reg1 = (first_reg + 1) & 0x1f;
       const int reg2 = (first_reg + 2) & 0x1f;
       const int reg3 = (first_reg + 3) & 0x1f;
  
       switch (num_regs)
     {
     case 1:
       snprintf (buf, size, "{%s%d.%s}%s", prefix, reg0, qlf_name, tb);
       break;
     case 2:
       snprintf (buf, size, "{%s%d.%s, %s%d.%s}%s", prefix, reg0, qlf_name,
             prefix, reg1, qlf_name, tb);
       break;
     case 3:
       snprintf (buf, size, "{%s%d.%s, %s%d.%s, %s%d.%s}%s",
             prefix, reg0, qlf_name, prefix, reg1, qlf_name,
             prefix, reg2, qlf_name, tb);
       break;
     case 4:
       snprintf (buf, size, "{%s%d.%s, %s%d.%s, %s%d.%s, %s%d.%s}%s",
             prefix, reg0, qlf_name, prefix, reg1, qlf_name,
             prefix, reg2, qlf_name, prefix, reg3, qlf_name, tb);
       break;
     }
     }
 }

References aarch64_get_qualifier_name(), AARCH64_OPND_LEt, assert(), prefix, aarch64_opnd_info::qualifier, aarch64_opnd_info::reglist, snprintf, and aarch64_opnd_info::type.

Referenced by aarch64_print_operand().

◆ print_register_offset_address()

static void print_register_offset_address	(	char *	buf,
		size_t	size,
		const aarch64_opnd_info *	opnd,
		const char *	base,
		const char *	offset
	)

static

Definition at line 2987 of file aarch64-opc.c.

 {
   char tb[16];          /* Temporary buffer.  */
   bfd_boolean print_extend_p = TRUE;
   bfd_boolean print_amount_p = TRUE;
   const char *shift_name = aarch64_operand_modifiers[opnd->shifter.kind].name;
  
   if (!opnd->shifter.amount && (opnd->qualifier != AARCH64_OPND_QLF_S_B
                 || !opnd->shifter.amount_present))
     {
       /* Not print the shift/extend amount when the amount is zero and
          when it is not the special case of 8-bit load/store instruction.  */
       print_amount_p = FALSE;
       /* Likewise, no need to print the shift operator LSL in such a
      situation.  */
       if (opnd->shifter.kind == AARCH64_MOD_LSL)
     print_extend_p = FALSE;
     }
  
   /* Prepare for the extend/shift.  */
   if (print_extend_p)
     {
       if (print_amount_p)
     snprintf (tb, sizeof (tb), ", %s #%" PRIi64, shift_name,
   /* PR 21096: The %100 is to silence a warning about possible truncation.  */
           (opnd->shifter.amount % 100));
       else
     snprintf (tb, sizeof (tb), ", %s", shift_name);
     }
   else
     tb[0] = '\0';
  
   snprintf (buf, size, "[%s, %s%s]", base, offset, tb);
 }

References AARCH64_MOD_LSL, aarch64_operand_modifiers, AARCH64_OPND_QLF_S_B, aarch64_opnd_info::amount, aarch64_opnd_info::amount_present, FALSE, aarch64_opnd_info::kind, aarch64_name_value_pair::name, aarch64_opnd_info::qualifier, aarch64_opnd_info::shifter, snprintf, and TRUE.

Referenced by aarch64_print_operand().

◆ qualifier_value_in_range_constraint_p()

static bfd_boolean qualifier_value_in_range_constraint_p ( aarch64_opnd_qualifier_t qualifier )

inlinestatic

Definition at line 751 of file aarch64-opc.c.

 {
   return (aarch64_opnd_qualifiers[qualifier].kind == OQK_VALUE_IN_RANGE)
     ? TRUE : FALSE;
 }

References aarch64_opnd_qualifiers, FALSE, operand_qualifier_data::kind, OQK_VALUE_IN_RANGE, and TRUE.

Referenced by get_lower_bound(), get_upper_bound(), and operand_general_constraint_met_p().

◆ set_elem_idx_out_of_range_error()

static void set_elem_idx_out_of_range_error	(	aarch64_operand_error *	mismatch_detail,
		int	idx,
		int	lower_bound,
		int	upper_bound
	)

inlinestatic

Definition at line 1338 of file aarch64-opc.c.

 {
   if (mismatch_detail == NULL)
     return;
   set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
               _("register element index"));
 }

References _, setup::idx, NULL, and set_out_of_range_error().

Referenced by operand_general_constraint_met_p().

◆ set_error()

static void set_error	(	aarch64_operand_error *	mismatch_detail,
		enum aarch64_operand_error_kind	kind,
		int	idx,
		const char *	error
	)

inlinestatic

Definition at line 1275 of file aarch64-opc.c.

 {
   if (mismatch_detail == NULL)
     return;
   mismatch_detail->kind = kind;
   mismatch_detail->index = idx;
   mismatch_detail->error = error;
 }

References aarch64_operand_error::error, error(), setup::idx, aarch64_operand_error::index, operand_qualifier_data::kind, aarch64_operand_error::kind, and NULL.

Referenced by set_other_error(), set_out_of_range_error(), set_reg_list_error(), set_syntax_error(), and set_unaligned_error().

◆ set_imm_out_of_range_error()

static void set_imm_out_of_range_error	(	aarch64_operand_error *	mismatch_detail,
		int	idx,
		int	lower_bound,
		int	upper_bound
	)

inlinestatic

Definition at line 1308 of file aarch64-opc.c.

 {
   if (mismatch_detail == NULL)
     return;
   set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
               _("immediate value"));
 }

References _, setup::idx, NULL, and set_out_of_range_error().

Referenced by operand_general_constraint_met_p().

◆ set_multiplier_out_of_range_error()

static void set_multiplier_out_of_range_error	(	aarch64_operand_error *	mismatch_detail,
		int	idx,
		int	lower_bound,
		int	upper_bound
	)

inlinestatic

Definition at line 1360 of file aarch64-opc.c.

 {
   if (mismatch_detail == NULL)
     return;
   set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
               _("multiplier"));
 }

References _, setup::idx, NULL, and set_out_of_range_error().

Referenced by operand_general_constraint_met_p().

◆ set_offset_out_of_range_error()

static void set_offset_out_of_range_error	(	aarch64_operand_error *	mismatch_detail,
		int	idx,
		int	lower_bound,
		int	upper_bound
	)

inlinestatic

Definition at line 1318 of file aarch64-opc.c.

 {
   if (mismatch_detail == NULL)
     return;
   set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
               _("immediate offset"));
 }

References _, setup::idx, NULL, and set_out_of_range_error().

Referenced by operand_general_constraint_met_p().

◆ set_other_error()

static void set_other_error	(	aarch64_operand_error *	mismatch_detail,
		int	idx,
		const char *	error
	)

inlinestatic

Definition at line 1390 of file aarch64-opc.c.

 {
   if (mismatch_detail == NULL)
     return;
   set_error (mismatch_detail, AARCH64_OPDE_OTHER_ERROR, idx, error);
 }

References AARCH64_OPDE_OTHER_ERROR, error(), setup::idx, NULL, and set_error().

Referenced by operand_general_constraint_met_p().

◆ set_out_of_range_error()

static void set_out_of_range_error	(	aarch64_operand_error *	mismatch_detail,
		int	idx,
		int	lower_bound,
		int	upper_bound,
		const char *	error
	)

inlinestatic

Definition at line 1296 of file aarch64-opc.c.

 {
   if (mismatch_detail == NULL)
     return;
   set_error (mismatch_detail, AARCH64_OPDE_OUT_OF_RANGE, idx, error);
   mismatch_detail->data[0] = lower_bound;
   mismatch_detail->data[1] = upper_bound;
 }

References AARCH64_OPDE_OUT_OF_RANGE, aarch64_operand_error::data, error(), setup::idx, NULL, and set_error().

Referenced by set_elem_idx_out_of_range_error(), set_imm_out_of_range_error(), set_multiplier_out_of_range_error(), set_offset_out_of_range_error(), set_regno_out_of_range_error(), and set_sft_amount_out_of_range_error().

◆ set_reg_list_error()

static void set_reg_list_error	(	aarch64_operand_error *	mismatch_detail,
		int	idx,
		int	expected_num
	)

inlinestatic

Definition at line 1380 of file aarch64-opc.c.

 {
   if (mismatch_detail == NULL)
     return;
   set_error (mismatch_detail, AARCH64_OPDE_REG_LIST, idx, NULL);
   mismatch_detail->data[0] = expected_num;
 }

References AARCH64_OPDE_REG_LIST, aarch64_operand_error::data, setup::idx, NULL, and set_error().

Referenced by operand_general_constraint_met_p().

◆ set_regno_out_of_range_error()

static void set_regno_out_of_range_error	(	aarch64_operand_error *	mismatch_detail,
		int	idx,
		int	lower_bound,
		int	upper_bound
	)

inlinestatic

Definition at line 1328 of file aarch64-opc.c.

 {
   if (mismatch_detail == NULL)
     return;
   set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
               _("register number"));
 }

References _, setup::idx, NULL, and set_out_of_range_error().

Referenced by operand_general_constraint_met_p().

◆ set_sft_amount_out_of_range_error()

static void set_sft_amount_out_of_range_error	(	aarch64_operand_error *	mismatch_detail,
		int	idx,
		int	lower_bound,
		int	upper_bound
	)

inlinestatic

Definition at line 1348 of file aarch64-opc.c.

 {
   if (mismatch_detail == NULL)
     return;
   set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
               _("shift amount"));
 }

References _, setup::idx, NULL, and set_out_of_range_error().

Referenced by operand_general_constraint_met_p().

◆ set_syntax_error()

static void set_syntax_error	(	aarch64_operand_error *	mismatch_detail,
		int	idx,
		const char *	error
	)

inlinestatic

Definition at line 1287 of file aarch64-opc.c.

 {
   if (mismatch_detail == NULL)
     return;
   set_error (mismatch_detail, AARCH64_OPDE_SYNTAX_ERROR, idx, error);
 }

References AARCH64_OPDE_SYNTAX_ERROR, error(), setup::idx, NULL, and set_error().

Referenced by operand_general_constraint_met_p().

◆ set_unaligned_error()

static void set_unaligned_error	(	aarch64_operand_error *	mismatch_detail,
		int	idx,
		int	alignment
	)

inlinestatic

Definition at line 1370 of file aarch64-opc.c.

 {
   if (mismatch_detail == NULL)
     return;
   set_error (mismatch_detail, AARCH64_OPDE_UNALIGNED, idx, NULL);
   mismatch_detail->data[0] = alignment;
 }

References AARCH64_OPDE_UNALIGNED, aarch64_operand_error::data, setup::idx, NULL, and set_error().

Referenced by operand_general_constraint_met_p().

◆ simd_imm_encoding_cmp()

static int simd_imm_encoding_cmp	(	const void *	i1,
		const void *	i2
	)

static

Definition at line 1106 of file aarch64-opc.c.

 {
   const simd_imm_encoding *imm1 = (const simd_imm_encoding *)i1;
   const simd_imm_encoding *imm2 = (const simd_imm_encoding *)i2;
  
   if (imm1->imm < imm2->imm)
     return -1;
   if (imm1->imm > imm2->imm)
     return +1;
   return 0;
 }

References i2, and simd_imm_encoding::imm.

Referenced by aarch64_logical_immediate_p(), and build_immediate_table().

◆ value_aligned_p()

static int value_aligned_p	(	int64_t	value,
		int	align
	)

inlinestatic

Definition at line 527 of file aarch64-opc.c.

 {
   return (value % align) == 0;
 }

References value.

Referenced by operand_general_constraint_met_p().

◆ value_fit_signed_field_p()

static int value_fit_signed_field_p	(	int64_t	value,
		unsigned	width
	)

inlinestatic

Definition at line 534 of file aarch64-opc.c.

 {
   assert (width < 32);
   if (width < sizeof (value) * 8)
     {
       int64_t lim = (int64_t)1 << (width - 1);
       if (value >= -lim && value < lim)
     return 1;
     }
   return 0;
 }

References assert(), value, and width.

Referenced by operand_general_constraint_met_p().

◆ value_fit_unsigned_field_p()

static int value_fit_unsigned_field_p	(	int64_t	value,
		unsigned	width
	)

inlinestatic

Definition at line 548 of file aarch64-opc.c.

 {
   assert (width < 32);
   if (width < sizeof (value) * 8)
     {
       int64_t lim = (int64_t)1 << width;
       if (value >= 0 && value < lim)
     return 1;
     }
   return 0;
 }

References assert(), value, and width.

Referenced by operand_general_constraint_met_p().

◆ value_in_range_p()

static int value_in_range_p	(	int64_t	value,
		int	low,
		int	high
	)

inlinestatic

Definition at line 520 of file aarch64-opc.c.

 {
   return (value >= low && value <= high) ? 1 : 0;
 }

References value.

Referenced by operand_general_constraint_met_p().

◆ vector_qualifier_p()

static bfd_boolean vector_qualifier_p ( enum aarch64_opnd_qualifier qualifier )

inlinestatic

Definition at line 109 of file aarch64-opc.c.

 {
   return ((qualifier >= AARCH64_OPND_QLF_V_8B
       && qualifier <= AARCH64_OPND_QLF_V_1Q) ? TRUE
       : FALSE);
 }

References AARCH64_OPND_QLF_V_1Q, AARCH64_OPND_QLF_V_8B, FALSE, and TRUE.

◆ verify_ldpsw()

static bfd_boolean verify_ldpsw	(	const struct aarch64_opcode *opcode	ATTRIBUTE_UNUSED,
		const aarch64_insn	insn
	)

static

Definition at line 4492 of file aarch64-opc.c.

 {
   int t  = BITS (insn, 4, 0);
   int n  = BITS (insn, 9, 5);
   int t2 = BITS (insn, 14, 10);
  
   if (BIT (insn, 23))
     {
       /* Write back enabled.  */
       if ((t == n || t2 == n) && n != 31)
     return FALSE;
     }
  
   if (BIT (insn, 22))
     {
       /* Load */
       if (t == t2)
     return FALSE;
     }
  
   return TRUE;
 }

References BIT, BITS, FALSE, n, and TRUE.

Variable Documentation

◆ aarch64_barrier_options

const struct aarch64_name_value_pair aarch64_barrier_options[16]

Initial value:

=
{
    { "#0x00", 0x0 },
    { "oshld", 0x1 },
    { "oshst", 0x2 },
    { "osh",   0x3 },
    { "#0x04", 0x4 },
    { "nshld", 0x5 },
    { "nshst", 0x6 },
    { "nsh",   0x7 },
    { "#0x08", 0x8 },
    { "ishld", 0x9 },
    { "ishst", 0xa },
    { "ish",   0xb },
    { "#0x0c", 0xc },
    { "ld",    0xd },
    { "st",    0xe },
    { "sy",    0xf },
}

Definition at line 437 of file aarch64-opc.c.

Referenced by aarch64_ext_barrier().

◆ aarch64_conds

const aarch64_cond aarch64_conds[16]

Initial value:

=
{
  {{"eq", "none"}, 0x0},
  {{"ne", "any"}, 0x1},
  {{"cs", "hs", "nlast"}, 0x2},
  {{"cc", "lo", "ul", "last"}, 0x3},
  {{"mi", "first"}, 0x4},
  {{"pl", "nfrst"}, 0x5},
  {{"vs"}, 0x6},
  {{"vc"}, 0x7},
  {{"hi", "pmore"}, 0x8},
  {{"ls", "plast"}, 0x9},
  {{"ge", "tcont"}, 0xa},
  {{"lt", "tstop"}, 0xb},
  {{"gt"}, 0xc},
  {{"le"}, 0xd},
  {{"al"}, 0xe},
  {{"nv"}, 0xf},
}

Definition at line 348 of file aarch64-opc.c.

Referenced by aarch64_get_operand_modifier(), and get_cond_from_value().

◆ aarch64_hint_options

const struct aarch64_name_value_pair aarch64_hint_options[]

Initial value:

=
{
  { "csync", 0x11 },    
  { NULL, 0x0 },
}

Definition at line 437 of file aarch64-opc.c.

Referenced by aarch64_ext_hint().

◆ aarch64_operand_modifiers

const struct aarch64_name_value_pair aarch64_operand_modifiers[]

Initial value:

=
{
    {"none", 0x0},
    {"msl",  0x0},
    {"ror",  0x3},
    {"asr",  0x2},
    {"lsr",  0x1},
    {"lsl",  0x0},
    {"uxtb", 0x0},
    {"uxth", 0x1},
    {"uxtw", 0x2},
    {"uxtx", 0x3},
    {"sxtb", 0x4},
    {"sxth", 0x5},
    {"sxtw", 0x6},
    {"sxtx", 0x7},
    {"mul", 0x0},
    {"mul vl", 0x0},
    {NULL, 0},
}

Definition at line 376 of file aarch64-opc.c.

Referenced by aarch64_get_operand_modifier_from_value(), aarch64_print_operand(), and print_register_offset_address().

◆ aarch64_opnd_qualifiers

struct operand_qualifier_data aarch64_opnd_qualifiers[]

Definition at line 621 of file aarch64-opc.c.

Referenced by aarch64_get_qualifier_esize(), aarch64_get_qualifier_name(), aarch64_get_qualifier_nelem(), aarch64_get_qualifier_standard_value(), get_lower_bound(), get_upper_bound(), operand_variant_qualifier_p(), and qualifier_value_in_range_constraint_p().

◆ aarch64_prfops

const struct aarch64_name_value_pair aarch64_prfops[32]

Definition at line 437 of file aarch64-opc.c.

Referenced by aarch64_ext_prfop().

◆ aarch64_pstatefields

const aarch64_sys_reg aarch64_pstatefields[]

Initial value:

=
{
  { "spsel",            0x05,   0 },
  { "daifset",          0x1e,   0 },
  { "daifclr",          0x1f,   0 },
  { "pan",      0x04,   F_ARCHEXT },
  { "uao",      0x03,   F_ARCHEXT },
  { "dit",      0x1a,   F_ARCHEXT },
  { 0,          CPENC(0,0,0,0,0), 0 },
}

Definition at line 4281 of file aarch64-opc.c.

Referenced by aarch64_ext_pstatefield(), and aarch64_print_operand().

◆ aarch64_sve_pattern_array

const char* const aarch64_sve_pattern_array[32]

Definition at line 43 of file aarch64-opc.c.

Referenced by aarch64_print_operand().

◆ aarch64_sve_prfop_array

const char* const aarch64_sve_prfop_array[16]

Initial value:

= {
  
  "pldl1keep",
  "pldl1strm",
  "pldl2keep",
  "pldl2strm",
  "pldl3keep",
  "pldl3strm",
  0,
  0,
  
  "pstl1keep",
  "pstl1strm",
  "pstl2keep",
  "pstl2strm",
  "pstl3keep",
  "pstl3strm",
  0,
  0
}

Definition at line 84 of file aarch64-opc.c.

Referenced by aarch64_print_operand().

◆ aarch64_sys_regs

const aarch64_sys_reg aarch64_sys_regs[]

Definition at line 3673 of file aarch64-opc.c.

Referenced by aarch64_print_operand().

◆ aarch64_sys_regs_at

const aarch64_sys_ins_reg aarch64_sys_regs_at[]

Initial value:

=
{
    { "s1e1r",      CPENS (0, C7, C8, 0), F_HASXT },
    { "s1e1w",      CPENS (0, C7, C8, 1), F_HASXT },
    { "s1e0r",      CPENS (0, C7, C8, 2), F_HASXT },
    { "s1e0w",      CPENS (0, C7, C8, 3), F_HASXT },
    { "s12e1r",     CPENS (4, C7, C8, 4), F_HASXT },
    { "s12e1w",     CPENS (4, C7, C8, 5), F_HASXT },
    { "s12e0r",     CPENS (4, C7, C8, 6), F_HASXT },
    { "s12e0w",     CPENS (4, C7, C8, 7), F_HASXT },
    { "s1e2r",      CPENS (4, C7, C8, 0), F_HASXT },
    { "s1e2w",      CPENS (4, C7, C8, 1), F_HASXT },
    { "s1e3r",      CPENS (6, C7, C8, 0), F_HASXT },
    { "s1e3w",      CPENS (6, C7, C8, 1), F_HASXT },
    { "s1e1rp",     CPENS (0, C7, C9, 0), F_HASXT | F_ARCHEXT },
    { "s1e1wp",     CPENS (0, C7, C9, 1), F_HASXT | F_ARCHEXT },
    { 0,       CPENS(0,0,0,0), 0 }
}

Definition at line 4339 of file aarch64-opc.c.

Referenced by aarch64_ext_sysins_op().

◆ aarch64_sys_regs_dc

const aarch64_sys_ins_reg aarch64_sys_regs_dc[]

Initial value:

=
{
    { "zva",        CPENS (3, C7, C4, 1),  F_HASXT },
    { "ivac",       CPENS (0, C7, C6, 1),  F_HASXT },
    { "isw",        CPENS (0, C7, C6, 2),  F_HASXT },
    { "cvac",       CPENS (3, C7, C10, 1), F_HASXT },
    { "csw",        CPENS (0, C7, C10, 2), F_HASXT },
    { "cvau",       CPENS (3, C7, C11, 1), F_HASXT },
    { "cvap",       CPENS (3, C7, C12, 1), F_HASXT | F_ARCHEXT },
    { "civac",      CPENS (3, C7, C14, 1), F_HASXT },
    { "cisw",       CPENS (0, C7, C14, 2), F_HASXT },
    { 0,       CPENS(0,0,0,0), 0 }
}

Definition at line 4325 of file aarch64-opc.c.

Referenced by aarch64_ext_sysins_op().

◆ aarch64_sys_regs_ic

const aarch64_sys_ins_reg aarch64_sys_regs_ic[]

Initial value:

=
{
    { "ialluis", CPENS(0,C7,C1,0), 0 },
    { "iallu",   CPENS(0,C7,C5,0), 0 },
    { "ivau",    CPENS (3, C7, C5, 1), F_HASXT },
    { 0, CPENS(0,0,0,0), 0 }
}

Definition at line 4317 of file aarch64-opc.c.

Referenced by aarch64_ext_sysins_op().

◆ aarch64_sys_regs_tlbi

const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[]

Definition at line 4358 of file aarch64-opc.c.

Referenced by aarch64_ext_sysins_op().

◆ fields

◆ int_reg

const char* int_reg[2][2][32]

static

Initial value:

= {
#define R32(X) 
#define R64(X) 
  { BANK (R32, "wsp"), BANK (R64, "sp") },
  { BANK (R32, "wzr"), BANK (R64, "xzr") }
 
 
}

Definition at line 2757 of file aarch64-opc.c.

Referenced by get_64bit_int_reg_name(), and get_int_reg_name().

◆ significant_operand_index

const char significant_operand_index[]

static

Initial value:

Definition at line 133 of file aarch64-opc.c.

Referenced by aarch64_select_operand_for_sizeq_field_coding().

◆ simd_immediates

simd_imm_encoding simd_immediates[TOTAL_IMM_NB]

static

Definition at line 1103 of file aarch64-opc.c.

Referenced by aarch64_logical_immediate_p(), and build_immediate_table().

◆ sve_reg

const char* sve_reg[2][32]

static

Initial value:

= {
#define ZS(X) 
#define ZD(X) 
  BANK (ZS, ZS (31)), BANK (ZD, ZD (31))
 
 
}

Definition at line 2769 of file aarch64-opc.c.

Referenced by get_addr_sve_reg_name().

Classes

Macros

Enumerations

Functions

Variables

Macro Definition Documentation

◆ B

◆ BANK

◆ BIT

◆ BITS

◆ C0

◆ C1

◆ C10

◆ C11

◆ C12

◆ C13

◆ C14

◆ C15

◆ C2

◆ C3

◆ C4

◆ C5

◆ C6

◆ C7

◆ C8

◆ C9

◆ CPEN_

◆ CPENC

◆ CPENS

◆ R32

◆ R64

◆ TOTAL_IMM_NB

◆ VERIFIER

◆ ZD

◆ ZS

Enumeration Type Documentation

◆ data_pattern

◆ operand_qualifier_kind

Function Documentation

◆ aarch64_extend_operator_p()

◆ aarch64_find_best_match()

◆ aarch64_get_expected_qualifier()

◆ aarch64_get_operand_class()

◆ aarch64_get_operand_desc()

◆ aarch64_get_operand_modifier()

◆ aarch64_get_operand_modifier_from_value()

◆ aarch64_get_operand_modifier_value()

◆ aarch64_get_operand_name()

◆ aarch64_get_qualifier_esize()

◆ aarch64_get_qualifier_name()

◆ aarch64_get_qualifier_nelem()

◆ aarch64_get_qualifier_standard_value()

◆ aarch64_logical_immediate_p()

◆ aarch64_match_operands_constraint()

◆ aarch64_num_of_operands()

◆ aarch64_operand_index()

◆ aarch64_print_operand()

◆ aarch64_pstatefield_supported_p()

◆ aarch64_replace_opcode()

◆ aarch64_select_operand_for_sizeq_field_coding()

◆ aarch64_shift_operator_p()

◆ aarch64_shrink_expanded_imm8()

◆ aarch64_stack_pointer_p()

◆ aarch64_sve_dupm_mov_immediate_p()

◆ aarch64_sys_ins_reg_has_xt()

◆ aarch64_sys_ins_reg_supported_p()

◆ aarch64_sys_reg_deprecated_p()

◆ aarch64_sys_reg_supported_p()

◆ aarch64_wide_constant_p()

◆ aarch64_zero_register_p()

◆ build_immediate_table()

◆ encode_immediate_bitfield()

◆ expand_fp_imm()

◆ fp_qualifier_p()

◆ get_64bit_int_reg_name()

◆ get_addr_sve_reg_name()

◆ get_cond_from_value()

◆ get_data_pattern()

◆ get_int_reg_name()

◆ get_inverted_cond()