aarch64-opc.h File Reference

#include <string.h>
#include <assert.h>
#include "aarch64.h"

Go to the source code of this file.

Classes
struct	aarch64_field
struct	aarch64_operand

Macros
#define	OPD_F_HAS_INSERTER   0x00000001
#define	OPD_F_HAS_EXTRACTOR   0x00000002
#define	OPD_F_SIGN_EXT_T   0x00000004 /* Require sign-extension. */
#define	OPD_F_SHIFT_BY_2
#define	OPD_F_MAYBE_SP   0x00000010 /* May potentially be SP. */
#define	OPD_F_OD_MASK   0x000000e0 /* Operand-dependent data. */
#define	OPD_F_OD_LSB   5
#define	OPD_F_NO_ZR   0x00000100 /* ZR index not allowed. */
#define	F_DEPRECATED   (1 << 0) /* Deprecated system register. */
#define	F_ARCHEXT   (1 << 1) /* Architecture dependent system register. */
#define	F_HASXT
#define	F_REG_READ
#define	F_REG_WRITE

Typedefs
typedef struct aarch64_field	aarch64_field
typedef struct aarch64_operand	aarch64_operand

Enumerations
enum	aarch64_field_kind {   FLD_NIL , FLD_cond2 , FLD_nzcv , FLD_defgh ,   FLD_abc , FLD_imm19 , FLD_immhi , FLD_immlo ,   FLD_size , FLD_vldst_size , FLD_op , FLD_Q ,   FLD_Rt , FLD_Rd , FLD_Rn , FLD_Rt2 ,   FLD_Ra , FLD_op2 , FLD_CRm , FLD_CRn ,   FLD_op1 , FLD_op0 , FLD_imm3 , FLD_cond ,   FLD_opcode , FLD_cmode , FLD_asisdlso_opcode , FLD_len ,   FLD_Rm , FLD_Rs , FLD_option , FLD_S ,   FLD_hw , FLD_opc , FLD_opc1 , FLD_shift ,   FLD_type , FLD_ldst_size , FLD_imm6 , FLD_imm6_2 ,   FLD_imm4 , FLD_imm4_2 , FLD_imm5 , FLD_imm7 ,   FLD_imm8 , FLD_imm9 , FLD_imm12 , FLD_imm14 ,   FLD_imm16 , FLD_imm26 , FLD_imms , FLD_immr ,   FLD_immb , FLD_immh , FLD_S_imm10 , FLD_N ,   FLD_index , FLD_index2 , FLD_sf , FLD_lse_sz ,   FLD_H , FLD_L , FLD_M , FLD_b5 ,   FLD_b40 , FLD_scale , FLD_SVE_M_4 , FLD_SVE_M_14 ,   FLD_SVE_M_16 , FLD_SVE_N , FLD_SVE_Pd , FLD_SVE_Pg3 ,   FLD_SVE_Pg4_5 , FLD_SVE_Pg4_10 , FLD_SVE_Pg4_16 , FLD_SVE_Pm ,   FLD_SVE_Pn , FLD_SVE_Pt , FLD_SVE_Rm , FLD_SVE_Rn ,   FLD_SVE_Vd , FLD_SVE_Vm , FLD_SVE_Vn , FLD_SVE_Za_5 ,   FLD_SVE_Za_16 , FLD_SVE_Zd , FLD_SVE_Zm_5 , FLD_SVE_Zm_16 ,   FLD_SVE_Zn , FLD_SVE_Zt , FLD_SVE_i1 , FLD_SVE_i3h ,   FLD_SVE_imm3 , FLD_SVE_imm4 , FLD_SVE_imm5 , FLD_SVE_imm5b ,   FLD_SVE_imm6 , FLD_SVE_imm7 , FLD_SVE_imm8 , FLD_SVE_imm9 ,   FLD_SVE_immr , FLD_SVE_imms , FLD_SVE_msz , FLD_SVE_pattern ,   FLD_SVE_prfop , FLD_SVE_rot1 , FLD_SVE_rot2 , FLD_SVE_sz ,   FLD_SVE_tsz , FLD_SVE_tszh , FLD_SVE_tszl_8 , FLD_SVE_tszl_19 ,   FLD_SVE_xs_14 , FLD_SVE_xs_22 , FLD_rotate1 , FLD_rotate2 ,   FLD_rotate3 , FLD_SM3_imm2 }

Functions
static bfd_boolean	operand_has_inserter (const aarch64_operand *operand)
static bfd_boolean	operand_has_extractor (const aarch64_operand *operand)
static bfd_boolean	operand_need_sign_extension (const aarch64_operand *operand)
static bfd_boolean	operand_need_shift_by_two (const aarch64_operand *operand)
static bfd_boolean	operand_maybe_stack_pointer (const aarch64_operand *operand)
static unsigned int	get_operand_specific_data (const aarch64_operand *operand)
static unsigned	get_operand_field_width (const aarch64_operand *operand, unsigned n)
static unsigned	get_operand_fields_width (const aarch64_operand *operand)
static const aarch64_operand *	get_operand_from_code (enum aarch64_opnd code)
int	aarch64_match_operands_constraint (aarch64_inst *, aarch64_operand_error *)
const char *	aarch64_get_qualifier_name (aarch64_opnd_qualifier_t)
unsigned char	aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t)
aarch64_insn	aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t)
int	aarch64_find_best_match (const aarch64_inst *, const aarch64_opnd_qualifier_seq_t *, int, aarch64_opnd_qualifier_t *)
static void	reset_operand_qualifier (aarch64_inst *inst, int idx)
static aarch64_insn	gen_mask (int width)
static int	gen_sub_field (enum aarch64_field_kind kind, int lsb_rel, int width, aarch64_field *ret)
static void	insert_field_2 (const aarch64_field *field, aarch64_insn *code, aarch64_insn value, aarch64_insn mask)
static aarch64_insn	extract_field_2 (const aarch64_field *field, aarch64_insn code, aarch64_insn mask)
static void	insert_field (enum aarch64_field_kind kind, aarch64_insn *code, aarch64_insn value, aarch64_insn mask)
static aarch64_insn	extract_field (enum aarch64_field_kind kind, aarch64_insn code, aarch64_insn mask)
aarch64_insn	extract_fields (aarch64_insn code, aarch64_insn mask,...)
static int	select_operand_for_sf_field_coding (const aarch64_opcode *opcode)
static int	select_operand_for_fptype_field_coding (const aarch64_opcode *opcode)
static int	select_operand_for_scalar_size_field_coding (const aarch64_opcode *opcode)
int	aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *)
aarch64_insn	aarch64_get_operand_modifier_value (enum aarch64_modifier_kind)
enum aarch64_modifier_kind	aarch64_get_operand_modifier_from_value (aarch64_insn, bfd_boolean)
bfd_boolean	aarch64_wide_constant_p (int64_t, int, unsigned int *)
bfd_boolean	aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *)
int	aarch64_shrink_expanded_imm8 (uint64_t)
static void	copy_operand_info (aarch64_inst *inst, int dst, int src)
static unsigned int	get_logsz (unsigned int size)

Variables
const aarch64_field	fields []
const aarch64_operand	aarch64_operands []

Macro Definition Documentation

F_ARCHEXT

#define F_ARCHEXT   (1 << 1) /* Architecture dependent system register. */

Definition at line 207 of file aarch64-opc.h.

F_DEPRECATED

#define F_DEPRECATED   (1 << 0) /* Deprecated system register. */

Definition at line 204 of file aarch64-opc.h.

F_HASXT

#define F_HASXT

Value:

                     (1 << 2)  /* System instruction register <Xt>
                     operand.  */

Definition at line 210 of file aarch64-opc.h.

F_REG_READ

#define F_REG_READ

Value:

                     (1 << 3)  /* Register can only be used to read values
                     out of.  */

Definition at line 213 of file aarch64-opc.h.

F_REG_WRITE

#define F_REG_WRITE

Value:

                     (1 << 4)  /* Register can only be written to but not
                     read from.  */

Definition at line 216 of file aarch64-opc.h.

OPD_F_HAS_EXTRACTOR

#define OPD_F_HAS_EXTRACTOR   0x00000002

Definition at line 193 of file aarch64-opc.h.

OPD_F_HAS_INSERTER

#define OPD_F_HAS_INSERTER   0x00000001

Definition at line 192 of file aarch64-opc.h.

OPD_F_MAYBE_SP

#define OPD_F_MAYBE_SP   0x00000010 /* May potentially be SP. */

Definition at line 196 of file aarch64-opc.h.

OPD_F_NO_ZR

#define OPD_F_NO_ZR   0x00000100 /* ZR index not allowed. */

Definition at line 199 of file aarch64-opc.h.

OPD_F_OD_LSB

#define OPD_F_OD_LSB   5

Definition at line 198 of file aarch64-opc.h.

OPD_F_OD_MASK

#define OPD_F_OD_MASK   0x000000e0 /* Operand-dependent data. */

Definition at line 197 of file aarch64-opc.h.

OPD_F_SHIFT_BY_2

#define OPD_F_SHIFT_BY_2

Value:

                           0x00000008   /* Need to left shift the field
                           value by 2 to get the value
                           of an immediate operand.  */

Definition at line 195 of file aarch64-opc.h.

OPD_F_SIGN_EXT_T

#define OPD_F_SIGN_EXT_T   0x00000004 /* Require sign-extension. */

Definition at line 194 of file aarch64-opc.h.

Typedef Documentation

aarch64_field

typedef struct aarch64_field aarch64_field

Definition at line 1 of file aarch64-opc.h.

aarch64_operand

typedef struct aarch64_operand aarch64_operand

Definition at line 164 of file aarch64-opc.h.

Enumeration Type Documentation

aarch64_field_kind

enum aarch64_field_kind

Enumerator
FLD_NIL
FLD_cond2
FLD_nzcv
FLD_defgh
FLD_abc
FLD_imm19
FLD_immhi
FLD_immlo
FLD_size
FLD_vldst_size
FLD_op
FLD_Q
FLD_Rt
FLD_Rd
FLD_Rn
FLD_Rt2
FLD_Ra
FLD_op2
FLD_CRm
FLD_CRn
FLD_op1
FLD_op0
FLD_imm3
FLD_cond
FLD_opcode
FLD_cmode
FLD_asisdlso_opcode
FLD_len
FLD_Rm
FLD_Rs
FLD_option
FLD_S
FLD_hw
FLD_opc
FLD_opc1
FLD_shift
FLD_type
FLD_ldst_size
FLD_imm6
FLD_imm6_2
FLD_imm4
FLD_imm4_2
FLD_imm5
FLD_imm7
FLD_imm8
FLD_imm9
FLD_imm12
FLD_imm14
FLD_imm16
FLD_imm26
FLD_imms
FLD_immr
FLD_immb
FLD_immh
FLD_S_imm10
FLD_N
FLD_index
FLD_index2
FLD_sf
FLD_lse_sz
FLD_H
FLD_L
FLD_M
FLD_b5
FLD_b40
FLD_scale
FLD_SVE_M_4
FLD_SVE_M_14
FLD_SVE_M_16
FLD_SVE_N
FLD_SVE_Pd
FLD_SVE_Pg3
FLD_SVE_Pg4_5
FLD_SVE_Pg4_10
FLD_SVE_Pg4_16
FLD_SVE_Pm
FLD_SVE_Pn
FLD_SVE_Pt
FLD_SVE_Rm
FLD_SVE_Rn
FLD_SVE_Vd
FLD_SVE_Vm
FLD_SVE_Vn
FLD_SVE_Za_5
FLD_SVE_Za_16
FLD_SVE_Zd
FLD_SVE_Zm_5
FLD_SVE_Zm_16
FLD_SVE_Zn
FLD_SVE_Zt
FLD_SVE_i1
FLD_SVE_i3h
FLD_SVE_imm3
FLD_SVE_imm4
FLD_SVE_imm5
FLD_SVE_imm5b
FLD_SVE_imm6
FLD_SVE_imm7
FLD_SVE_imm8
FLD_SVE_imm9
FLD_SVE_immr
FLD_SVE_imms
FLD_SVE_msz
FLD_SVE_pattern
FLD_SVE_prfop
FLD_SVE_rot1
FLD_SVE_rot2
FLD_SVE_sz
FLD_SVE_tsz
FLD_SVE_tszh
FLD_SVE_tszl_8
FLD_SVE_tszl_19
FLD_SVE_xs_14
FLD_SVE_xs_22
FLD_rotate1
FLD_rotate2
FLD_rotate3
FLD_SM3_imm2

Definition at line 33 of file aarch64-opc.h.

{
  FLD_NIL,
  FLD_cond2,
  FLD_nzcv,
  FLD_defgh,
  FLD_abc,
  FLD_imm19,
  FLD_immhi,
  FLD_immlo,
  FLD_size,
  FLD_vldst_size,
  FLD_op,
  FLD_Q,
  FLD_Rt,
  FLD_Rd,
  FLD_Rn,
  FLD_Rt2,
  FLD_Ra,
  FLD_op2,
  FLD_CRm,
  FLD_CRn,
  FLD_op1,
  FLD_op0,
  FLD_imm3,
  FLD_cond,
  FLD_opcode,
  FLD_cmode,
  FLD_asisdlso_opcode,
  FLD_len,
  FLD_Rm,
  FLD_Rs,
  FLD_option,
  FLD_S,
  FLD_hw,
  FLD_opc,
  FLD_opc1,
  FLD_shift,
  FLD_type,
  FLD_ldst_size,
  FLD_imm6,
  FLD_imm6_2,
  FLD_imm4,
  FLD_imm4_2,
  FLD_imm5,
  FLD_imm7,
  FLD_imm8,
  FLD_imm9,
  FLD_imm12,
  FLD_imm14,
  FLD_imm16,
  FLD_imm26,
  FLD_imms,
  FLD_immr,
  FLD_immb,
  FLD_immh,
  FLD_S_imm10,
  FLD_N,
  FLD_index,
  FLD_index2,
  FLD_sf,
  FLD_lse_sz,
  FLD_H,
  FLD_L,
  FLD_M,
  FLD_b5,
  FLD_b40,
  FLD_scale,
  FLD_SVE_M_4,
  FLD_SVE_M_14,
  FLD_SVE_M_16,
  FLD_SVE_N,
  FLD_SVE_Pd,
  FLD_SVE_Pg3,
  FLD_SVE_Pg4_5,
  FLD_SVE_Pg4_10,
  FLD_SVE_Pg4_16,
  FLD_SVE_Pm,
  FLD_SVE_Pn,
  FLD_SVE_Pt,
  FLD_SVE_Rm,
  FLD_SVE_Rn,
  FLD_SVE_Vd,
  FLD_SVE_Vm,
  FLD_SVE_Vn,
  FLD_SVE_Za_5,
  FLD_SVE_Za_16,
  FLD_SVE_Zd,
  FLD_SVE_Zm_5,
  FLD_SVE_Zm_16,
  FLD_SVE_Zn,
  FLD_SVE_Zt,
  FLD_SVE_i1,
  FLD_SVE_i3h,
  FLD_SVE_imm3,
  FLD_SVE_imm4,
  FLD_SVE_imm5,
  FLD_SVE_imm5b,
  FLD_SVE_imm6,
  FLD_SVE_imm7,
  FLD_SVE_imm8,
  FLD_SVE_imm9,
  FLD_SVE_immr,
  FLD_SVE_imms,
  FLD_SVE_msz,
  FLD_SVE_pattern,
  FLD_SVE_prfop,
  FLD_SVE_rot1,
  FLD_SVE_rot2,
  FLD_SVE_sz,
  FLD_SVE_tsz,
  FLD_SVE_tszh,
  FLD_SVE_tszl_8,
  FLD_SVE_tszl_19,
  FLD_SVE_xs_14,
  FLD_SVE_xs_22,
  FLD_rotate1,
  FLD_rotate2,
  FLD_rotate3,
  FLD_SM3_imm2
};

Function Documentation

aarch64_find_best_match()

int aarch64_find_best_match	(	const aarch64_inst *	inst,
		const aarch64_opnd_qualifier_seq_t *	qualifiers_list,
		int	stop_at,
		aarch64_opnd_qualifier_t *	ret
	)

Definition at line 876 of file aarch64-opc.c.

{
  int found = 0;
  int i, num_opnds;
  const aarch64_opnd_qualifier_t *qualifiers;
 
  num_opnds = aarch64_num_of_operands (inst->opcode);
  if (num_opnds == 0)
    {
      DEBUG_TRACE ("SUCCEED: no operand");
      return 1;
    }
 
  if (stop_at < 0 || stop_at >= num_opnds)
    stop_at = num_opnds - 1;
 
  /* For each pattern.  */
  for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
    {
      int j;
      qualifiers = *qualifiers_list;
 
      /* Start as positive.  */
      found = 1;
 
      DEBUG_TRACE ("%d", i);
#ifdef DEBUG_AARCH64
      if (debug_dump)
    dump_match_qualifiers (inst->operands, qualifiers);
#endif
 
      /* Most opcodes has much fewer patterns in the list.
     First NIL qualifier indicates the end in the list.   */
      if (empty_qualifier_sequence_p (qualifiers) == TRUE)
    {
      DEBUG_TRACE_IF (i == 0, "SUCCEED: empty qualifier list");
      if (i)
        found = 0;
      break;
    }
 
      for (j = 0; j < num_opnds && j <= stop_at; ++j, ++qualifiers)
    {
      if (inst->operands[j].qualifier == AARCH64_OPND_QLF_NIL)
        {
          /* Either the operand does not have qualifier, or the qualifier
         for the operand needs to be deduced from the qualifier
         sequence.
         In the latter case, any constraint checking related with
         the obtained qualifier should be done later in
         operand_general_constraint_met_p.  */
          continue;
        }
      else if (*qualifiers != inst->operands[j].qualifier)
        {
          /* Unless the target qualifier can also qualify the operand
         (which has already had a non-nil qualifier), non-equal
         qualifiers are generally un-matched.  */
          if (operand_also_qualified_p (inst->operands + j, *qualifiers))
        continue;
          else
        {
          found = 0;
          break;
        }
        }
      else
        continue;   /* Equal qualifiers are certainly matched.  */
    }
 
      /* Qualifiers established.  */
      if (found == 1)
    break;
    }
 
  if (found == 1)
    {
      /* Fill the result in *RET.  */
      int j;
      qualifiers = *qualifiers_list;
 
      DEBUG_TRACE ("complete qualifiers using list %d", i);
#ifdef DEBUG_AARCH64
      if (debug_dump)
    dump_qualifier_sequence (qualifiers);
#endif
 
      for (j = 0; j <= stop_at; ++j, ++qualifiers)
    ret[j] = *qualifiers;
      for (; j < AARCH64_MAX_OPND_NUM; ++j)
    ret[j] = AARCH64_OPND_QLF_NIL;
 
      DEBUG_TRACE ("SUCCESS");
      return 1;
    }
 
  DEBUG_TRACE ("FAIL");
  return 0;
}

References AARCH64_MAX_OPND_NUM, AARCH64_MAX_QLF_SEQ_NUM, aarch64_num_of_operands(), AARCH64_OPND_QLF_NIL, DEBUG_TRACE, DEBUG_TRACE_IF, empty_qualifier_sequence_p(), found, i, aarch64_inst::opcode, operand_also_qualified_p(), aarch64_inst::operands, aarch64_opnd_info::qualifier, and TRUE.

Referenced by get_expected_qualifier(), and match_operands_qualifier().

aarch64_get_operand_modifier_from_value()

enum aarch64_modifier_kind aarch64_get_operand_modifier_from_value	(	aarch64_insn	value,
		bfd_boolean	extend_p
	)

Definition at line 414 of file aarch64-opc.c.

{
  if (extend_p == TRUE)
    return AARCH64_MOD_UXTB + value;
  else
    return AARCH64_MOD_LSL - value;
}

References aarch64_operand_modifiers, and aarch64_name_value_pair::value.

Referenced by aarch64_ext_addr_regoff(), aarch64_ext_reg_extended(), and aarch64_ext_reg_shifted().

aarch64_get_operand_modifier_value()

aarch64_insn aarch64_get_operand_modifier_value

(

enum

aarch64_modifier_kind

)

Definition at line 414 of file aarch64-opc.c.

{
  return aarch64_operand_modifiers[kind].value;
}

aarch64_get_qualifier_name()

const char* aarch64_get_qualifier_name

(

aarch64_opnd_qualifier_t

qualifier

)

Definition at line 758 of file aarch64-opc.c.

{
  return aarch64_opnd_qualifiers[qualifier].desc;
}

References aarch64_opnd_qualifiers, and operand_qualifier_data::desc.

Referenced by aarch64_print_operand(), decode_sizeq(), match_operands_qualifier(), and print_register_list().

aarch64_get_qualifier_nelem()

unsigned char aarch64_get_qualifier_nelem

(

aarch64_opnd_qualifier_t

qualifier

)

Definition at line 773 of file aarch64-opc.c.

{
  assert (operand_variant_qualifier_p (qualifier) == TRUE);
  return aarch64_opnd_qualifiers[qualifier].data1;
}

References aarch64_opnd_qualifiers, assert(), operand_qualifier_data::data1, operand_variant_qualifier_p(), and TRUE.

Referenced by aarch64_ext_simd_addr_post(), and operand_general_constraint_met_p().

aarch64_get_qualifier_standard_value()

aarch64_insn aarch64_get_qualifier_standard_value

(

aarch64_opnd_qualifier_t

qualifier

)

Definition at line 780 of file aarch64-opc.c.

{
  assert (operand_variant_qualifier_p (qualifier) == TRUE);
  return aarch64_opnd_qualifiers[qualifier].data2;
}

References aarch64_opnd_qualifiers, assert(), operand_qualifier_data::data2, operand_variant_qualifier_p(), and TRUE.

aarch64_logical_immediate_p()

bfd_boolean aarch64_logical_immediate_p	(	uint64_t	value,
		int	esize,
		aarch64_insn *	encoding
	)

Definition at line 1207 of file aarch64-opc.c.

{
  simd_imm_encoding imm_enc;
  const simd_imm_encoding *imm_encoding;
  static bfd_boolean initialized = FALSE;
  uint64_t upper;
  int i;
 
  DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 "), esize: %d", value,
           value, esize);
 
  if (!initialized)
    {
      build_immediate_table ();
      initialized = TRUE;
    }
 
  /* Allow all zeros or all ones in top bits, so that
     constant expressions like ~1 are permitted.  */
  upper = (uint64_t) -1 << (esize * 4) << (esize * 4);
  if ((value & ~upper) != value && (value | upper) != value)
    return FALSE;
 
  /* Replicate to a full 64-bit value.  */
  value &= ~upper;
  for (i = esize * 8; i < 64; i *= 2)
    value |= (value << i);
 
  imm_enc.imm = value;
  imm_encoding = (const simd_imm_encoding *)
    bsearch(&imm_enc, simd_immediates, TOTAL_IMM_NB,
            sizeof(simd_immediates[0]), simd_imm_encoding_cmp);
  if (imm_encoding == NULL)
    {
      DEBUG_TRACE ("exit with FALSE");
      return FALSE;
    }
  if (encoding != NULL)
    *encoding = imm_encoding->encoding;
  DEBUG_TRACE ("exit with TRUE");
  return TRUE;
}

References build_immediate_table(), DEBUG_TRACE, simd_imm_encoding::encoding, cmd_descs_generate::encoding, FALSE, i, simd_imm_encoding::imm, initialized, NULL, PRIx64, simd_imm_encoding_cmp(), simd_immediates, TOTAL_IMM_NB, TRUE, and value.

Referenced by operand_general_constraint_met_p().

aarch64_match_operands_constraint()

int aarch64_match_operands_constraint	(	aarch64_inst *	inst,
		aarch64_operand_error *	mismatch_detail
	)

Definition at line 2632 of file aarch64-opc.c.

{
  int i;
 
  DEBUG_TRACE ("enter");
 
  /* Check for cases where a source register needs to be the same as the
     destination register.  Do this before matching qualifiers since if
     an instruction has both invalid tying and invalid qualifiers,
     the error about qualifiers would suggest several alternative
     instructions that also have invalid tying.  */
  i = inst->opcode->tied_operand;
  if (i > 0 && (inst->operands[0].reg.regno != inst->operands[i].reg.regno))
    {
      if (mismatch_detail)
    {
      mismatch_detail->kind = AARCH64_OPDE_UNTIED_OPERAND;
      mismatch_detail->index = i;
      mismatch_detail->error = NULL;
    }
      return 0;
    }
 
  /* Match operands' qualifier.
     *INST has already had qualifier establish for some, if not all, of
     its operands; we need to find out whether these established
     qualifiers match one of the qualifier sequence in
     INST->OPCODE->QUALIFIERS_LIST.  If yes, we will assign each operand
     with the corresponding qualifier in such a sequence.
     Only basic operand constraint checking is done here; the more thorough
     constraint checking will carried out by operand_general_constraint_met_p,
     which has be to called after this in order to get all of the operands'
     qualifiers established.  */
  if (match_operands_qualifier (inst, TRUE /* update_p */) == 0)
    {
      DEBUG_TRACE ("FAIL on operand qualifier matching");
      if (mismatch_detail)
    {
      /* Return an error type to indicate that it is the qualifier
         matching failure; we don't care about which operand as there
         are enough information in the opcode table to reproduce it.  */
      mismatch_detail->kind = AARCH64_OPDE_INVALID_VARIANT;
      mismatch_detail->index = -1;
      mismatch_detail->error = NULL;
    }
      return 0;
    }
 
  /* Match operands' constraint.  */
  for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
    {
      enum aarch64_opnd type = inst->opcode->operands[i];
      if (type == AARCH64_OPND_NIL)
    break;
      if (inst->operands[i].skip)
    {
      DEBUG_TRACE ("skip the incomplete operand %d", i);
      continue;
    }
      if (operand_general_constraint_met_p (inst->operands, i, type,
                        inst->opcode, mismatch_detail) == 0)
    {
      DEBUG_TRACE ("FAIL on operand %d", i);
      return 0;
    }
    }
 
  DEBUG_TRACE ("PASS");
 
  return 1;
}

References AARCH64_MAX_OPND_NUM, AARCH64_OPDE_INVALID_VARIANT, AARCH64_OPDE_UNTIED_OPERAND, AARCH64_OPND_NIL, DEBUG_TRACE, aarch64_operand_error::error, i, aarch64_operand_error::index, aarch64_operand_error::kind, match_operands_qualifier(), NULL, aarch64_inst::opcode, operand_general_constraint_met_p(), aarch64_opcode::operands, aarch64_inst::operands, aarch64_opnd_info::reg, aarch64_opnd_info::skip, aarch64_opcode::tied_operand, TRUE, and type.

Referenced by aarch64_opcode_decode(), and determine_disassembling_preference().

aarch64_select_operand_for_sizeq_field_coding()

int aarch64_select_operand_for_sizeq_field_coding

(

const aarch64_opcode *

opcode

)

Definition at line 199 of file aarch64-opc.c.

{
  return
    significant_operand_index [get_data_pattern (opcode->qualifiers_list[0])];
}

References get_data_pattern(), aarch64_opcode::qualifiers_list, and significant_operand_index.

Referenced by decode_sizeq().

aarch64_shrink_expanded_imm8()

int aarch64_shrink_expanded_imm8

(

uint64_t

imm

)

Definition at line 1255 of file aarch64-opc.c.

{
  int i, ret;
  uint32_t byte;
 
  ret = 0;
  for (i = 0; i < 8; i++)
    {
      byte = (imm >> (8 * i)) & 0xff;
      if (byte == 0xff)
    ret |= 1 << i;
      else if (byte != 0x00)
    return -1;
    }
  return ret;
}

References i, and imm.

Referenced by operand_general_constraint_met_p().

aarch64_wide_constant_p()

bfd_boolean aarch64_wide_constant_p	(	int64_t	value,
		int	is32,
		unsigned int *	shift_amount
	)

Definition at line 1033 of file aarch64-opc.c.

{
  int amount;
 
  DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
 
  if (is32)
    {
      /* Allow all zeros or all ones in top 32-bits, so that
     32-bit constant expressions like ~0x80000000 are
     permitted.  */
      uint64_t ext = value;
      if (ext >> 32 != 0 && ext >> 32 != (uint64_t) 0xffffffff)
    /* Immediate out of range.  */
    return FALSE;
      value &= (int64_t) 0xffffffff;
    }
 
  /* first, try movz then movn */
  amount = -1;
  if ((value & ((int64_t) 0xffff << 0)) == value)
    amount = 0;
  else if ((value & ((int64_t) 0xffff << 16)) == value)
    amount = 16;
  else if (!is32 && (value & ((int64_t) 0xffff << 32)) == value)
    amount = 32;
  else if (!is32 && (value & ((int64_t) 0xffff << 48)) == value)
    amount = 48;
 
  if (amount == -1)
    {
      DEBUG_TRACE ("exit FALSE with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
      return FALSE;
    }
 
  if (shift_amount != NULL)
    *shift_amount = amount;
 
  DEBUG_TRACE ("exit TRUE with amount %d", amount);
 
  return TRUE;
}

References DEBUG_TRACE, ext, FALSE, NULL, PRIx64, TRUE, and value.

Referenced by convert_movebitmask_to_mov(), convert_movewide_to_mov(), and operand_general_constraint_met_p().

copy_operand_info()

static void copy_operand_info ( aarch64_inst *  inst, int  dst, int  src  )

inlinestatic

Definition at line 463 of file aarch64-opc.h.

{
  assert (dst >= 0 && src >= 0 && dst < AARCH64_MAX_OPND_NUM

Referenced by convert_bfm_to_bfc(), convert_csinc_to_cset(), convert_extr_to_ror(), convert_from_csel(), and convert_movebitmask_to_mov().

extract_field()

static aarch64_insn extract_field ( enum aarch64_field_kind  kind, aarch64_insn  code, aarch64_insn  mask  )

inlinestatic

Definition at line 368 of file aarch64-opc.h.

{

References extract_field_2(), fields, and mask.

Referenced by aarch64_decode_variant_using_iclass(), aarch64_ext_addr_offset(), aarch64_ext_addr_regoff(), aarch64_ext_addr_simm(), aarch64_ext_addr_simm10(), aarch64_ext_addr_simple(), aarch64_ext_addr_uimm12(), aarch64_ext_advsimd_imm_shift(), aarch64_ext_aimm(), aarch64_ext_barrier(), aarch64_ext_cond(), aarch64_ext_fbits(), aarch64_ext_ft(), aarch64_ext_imm_half(), aarch64_ext_imm_rotate1(), aarch64_ext_imm_rotate2(), aarch64_ext_ldst_elemlist(), aarch64_ext_ldst_reglist(), aarch64_ext_ldst_reglist_r(), aarch64_ext_prfop(), aarch64_ext_reg_extended(), aarch64_ext_reg_shifted(), aarch64_ext_reglane(), aarch64_ext_reglist(), aarch64_ext_regno(), aarch64_ext_regrt_sysins(), aarch64_ext_shll_imm(), aarch64_ext_simd_addr_post(), aarch64_ext_sve_addr_reg_imm(), aarch64_ext_sve_addr_reg_mul_vl(), aarch64_ext_sve_addr_ri_s4(), aarch64_ext_sve_addr_ri_s4xvl(), aarch64_ext_sve_addr_ri_s6xvl(), aarch64_ext_sve_addr_ri_u6(), aarch64_ext_sve_addr_rr_lsl(), aarch64_ext_sve_addr_rz_xtw(), aarch64_ext_sve_addr_zi_u5(), aarch64_ext_sve_addr_zz(), aarch64_ext_sve_float_half_one(), aarch64_ext_sve_float_half_two(), aarch64_ext_sve_float_zero_one(), aarch64_ext_sve_index(), aarch64_ext_sve_reglist(), aarch64_ext_sve_scale(), do_misc_decoding(), do_special_decoding(), extract_all_fields(), and extract_fields().

extract_field_2()

static aarch64_insn extract_field_2 ( const aarch64_field *  field, aarch64_insn  code, aarch64_insn  mask  )

inlinestatic

Definition at line 344 of file aarch64-opc.h.

{
  aarch64_insn value;

References gen_mask(), aarch64_field::lsb, mask, value, and aarch64_field::width.

Referenced by aarch64_ext_advsimd_imm_modified(), aarch64_ext_ldst_elemlist(), decode_asimd_fcvt(), decode_asisd_fcvtxn(), decode_fcvt(), do_special_decoding(), and extract_field().

extract_fields()

aarch64_insn extract_fields	(	aarch64_insn	code,
		aarch64_insn	mask,
			...
	)

Definition at line 142 of file aarch64-dis.c.

{
  uint32_t num;
  const aarch64_field *field;
  enum aarch64_field_kind kind;
  va_list va;
 
  va_start (va, mask);
  num = va_arg (va, uint32_t);
  assert (num <= 5);
  aarch64_insn value = 0x0;
  while (num--)
    {
      kind = va_arg (va, enum aarch64_field_kind);
      field = &fields[kind];
      value <<= field->width;
      value |= extract_field (kind, code, mask);
    }
  va_end (va);
  return value;
}

References assert(), extract_field(), fields, mask, num, value, and aarch64_field::width.

Referenced by aarch64_decode_variant_using_iclass(), aarch64_ext_addr_offset(), aarch64_ext_addr_simm10(), aarch64_ext_advsimd_imm_modified(), aarch64_ext_advsimd_imm_shift(), aarch64_ext_ft(), aarch64_ext_hint(), aarch64_ext_ldst_elemlist(), aarch64_ext_limm(), aarch64_ext_pstatefield(), aarch64_ext_reglane(), aarch64_ext_sve_addr_ri_s9xvl(), aarch64_ext_sve_index(), aarch64_ext_sysins_op(), aarch64_ext_sysreg(), decode_sizeq(), and do_misc_decoding().

gen_mask()

static aarch64_insn gen_mask ( int  width )

inlinestatic

Definition at line 306 of file aarch64-opc.h.

{

Referenced by extract_field_2(), and insert_field_2().

gen_sub_field()

static int gen_sub_field ( enum aarch64_field_kind  kind, int  lsb_rel, int  width, aarch64_field *  ret  )

inlinestatic

Definition at line 313 of file aarch64-opc.h.

{
  const aarch64_field *field = &fields[kind];
  if (lsb_rel < 0 || width <= 0 || lsb_rel + width > field->width)

Referenced by aarch64_ext_advsimd_imm_modified(), aarch64_ext_ldst_elemlist(), decode_asimd_fcvt(), decode_asisd_fcvtxn(), and do_special_decoding().

get_logsz()

static unsigned int get_logsz ( unsigned int  size )

inlinestatic

Definition at line 475 of file aarch64-opc.h.

{
  const unsigned char ls[16] =
    {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
  if (size > 16)
    {
      assert (0);

Referenced by aarch64_ext_addr_regoff(), aarch64_ext_addr_uimm12(), aarch64_ext_reglane(), and operand_general_constraint_met_p().

get_operand_field_width()

static unsigned get_operand_field_width ( const aarch64_operand *  operand, unsigned  n  )

inlinestatic

Definition at line 257 of file aarch64-opc.h.

{

get_operand_fields_width()

static unsigned get_operand_fields_width ( const aarch64_operand *  operand )

inlinestatic

Definition at line 265 of file aarch64-opc.h.

{
  int i = 0;
  unsigned width = 0;

Referenced by aarch64_ext_imm(), and operand_general_constraint_met_p().

get_operand_from_code()

static const aarch64_operand* get_operand_from_code ( enum aarch64_opnd  code )

inlinestatic

Definition at line 276 of file aarch64-opc.h.

{

Referenced by operand_general_constraint_met_p().

get_operand_specific_data()

static unsigned int get_operand_specific_data ( const aarch64_operand *  operand )

inlinestatic

Definition at line 250 of file aarch64-opc.h.

                                                  : FALSE;
}
 
/* Return the value of the operand-specific data field (OPD_F_OD_MASK).  */

Referenced by aarch64_ext_sve_addr_reg_imm(), aarch64_ext_sve_addr_reg_mul_vl(), aarch64_ext_sve_addr_rr_lsl(), aarch64_ext_sve_addr_rz_xtw(), aarch64_ext_sve_quad_index(), and operand_general_constraint_met_p().

insert_field()

static void insert_field ( enum aarch64_field_kind  kind, aarch64_insn *  code, aarch64_insn  value, aarch64_insn  mask  )

inlinestatic

Definition at line 358 of file aarch64-opc.h.

{

References fields, insert_field_2(), mask, and value.

insert_field_2()

static void insert_field_2 ( const aarch64_field *  field, aarch64_insn *  code, aarch64_insn  value, aarch64_insn  mask  )

inlinestatic

Definition at line 327 of file aarch64-opc.h.

{
  assert (field->width < 32 && field->width >= 1 && field->lsb >= 0
      && field->lsb + field->width <= 32);
  value &= gen_mask (field->width);
  value <<= field->lsb;

References assert(), gen_mask(), aarch64_field::lsb, mask, value, and aarch64_field::width.

Referenced by insert_field().

operand_has_extractor()

static bfd_boolean operand_has_extractor ( const aarch64_operand *  operand )

inlinestatic

Definition at line 225 of file aarch64-opc.h.

{
  return (operand->flags & OPD_F_HAS_INSERTER) ? TRUE : FALSE;
}
 

References FALSE, OPD_F_HAS_INSERTER, and TRUE.

Referenced by aarch64_opcode_decode().

operand_has_inserter()

static bfd_boolean operand_has_inserter ( const aarch64_operand *  operand )

inlinestatic

Definition at line 219 of file aarch64-opc.h.

{

operand_maybe_stack_pointer()

static bfd_boolean operand_maybe_stack_pointer ( const aarch64_operand *  operand )

inlinestatic

Definition at line 243 of file aarch64-opc.h.

{
  return (operand->flags & OPD_F_SHIFT_BY_2) ? TRUE : FALSE;
}
 

References FALSE, OPD_F_SHIFT_BY_2, and TRUE.

Referenced by aarch64_stack_pointer_p(), aarch64_zero_register_p(), and operand_also_qualified_p().

operand_need_shift_by_two()

static bfd_boolean operand_need_shift_by_two ( const aarch64_operand *  operand )

inlinestatic

Definition at line 237 of file aarch64-opc.h.

{
  return (operand->flags & OPD_F_SIGN_EXT_T) ? TRUE : FALSE;
}
 

References FALSE, OPD_F_SIGN_EXT_T, and TRUE.

Referenced by aarch64_ext_imm(), and operand_general_constraint_met_p().

operand_need_sign_extension()

static bfd_boolean operand_need_sign_extension ( const aarch64_operand *  operand )

inlinestatic

Definition at line 231 of file aarch64-opc.h.

{
  return (operand->flags & OPD_F_HAS_EXTRACTOR) ? TRUE : FALSE;
}
 

References FALSE, OPD_F_HAS_EXTRACTOR, and TRUE.

Referenced by aarch64_ext_imm().

reset_operand_qualifier()

static void reset_operand_qualifier ( aarch64_inst *  inst, int  idx  )

inlinestatic

Definition at line 295 of file aarch64-opc.h.

{

Referenced by convert_bfm_to_bfc(), convert_bfm_to_bfi(), and convert_bfm_to_bfx().

select_operand_for_fptype_field_coding()

static int select_operand_for_fptype_field_coding ( const aarch64_opcode *  opcode )

inlinestatic

Definition at line 405 of file aarch64-opc.h.

{
  int idx;
  if (aarch64_get_operand_class (opcode->operands[1])
      == AARCH64_OPND_CLASS_FP_REG)
    /* normal case.  */
    idx = 1;
  else if (aarch64_get_operand_class (opcode->operands[0])
       == AARCH64_OPND_CLASS_FP_REG)
    /* e.g. float2fix.  */

References aarch64_get_operand_class(), AARCH64_OPND_CLASS_FP_REG, assert(), setup::idx, and aarch64_opcode::operands.

Referenced by do_special_decoding().

select_operand_for_scalar_size_field_coding()

static int select_operand_for_scalar_size_field_coding ( const aarch64_opcode *  opcode )

inlinestatic

Definition at line 427 of file aarch64-opc.h.

{
  int src_size = 0, dst_size = 0;
  if (aarch64_get_operand_class (opcode->operands[0])
      == AARCH64_OPND_CLASS_SISD_REG)
    dst_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][0]);
  if (aarch64_get_operand_class (opcode->operands[1])
      == AARCH64_OPND_CLASS_SISD_REG)
    src_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][1]);
  if (src_size == dst_size && src_size == 0)
    { assert (0); abort (); }
  /* When the result is not a sisd register or it is a long operantion.  */

References aarch64_get_operand_class(), aarch64_get_qualifier_esize(), AARCH64_OPND_CLASS_SISD_REG, assert(), aarch64_opcode::operands, and aarch64_opcode::qualifiers_list.

Referenced by do_special_decoding().

select_operand_for_sf_field_coding()

static int select_operand_for_sf_field_coding ( const aarch64_opcode *  opcode )

inlinestatic

Definition at line 384 of file aarch64-opc.h.

{
  int idx = -1;
  if (aarch64_get_operand_class (opcode->operands[0])
      == AARCH64_OPND_CLASS_INT_REG)
    /* normal case.  */
    idx = 0;
  else if (aarch64_get_operand_class (opcode->operands[1])
       == AARCH64_OPND_CLASS_INT_REG)
    /* e.g. float2fix.  */

References aarch64_get_operand_class(), AARCH64_OPND_CLASS_INT_REG, assert(), setup::idx, and aarch64_opcode::operands.

Referenced by do_special_decoding().

Variable Documentation

aarch64_operands

const aarch64_operand aarch64_operands[]

extern

Definition at line 1 of file aarch64-opc-2.c.

Referenced by aarch64_extract_operand(), aarch64_get_operand_desc(), aarch64_get_operand_name(), aarch64_opcode_decode(), aarch64_stack_pointer_p(), aarch64_zero_register_p(), operand_also_qualified_p(), and operand_general_constraint_met_p().

fields

const aarch64_field fields[]

extern

Definition at line 205 of file aarch64-opc.c.

Referenced by aarch64_ext_addr_simm(), ARC_CGEN_EXTRACT_FN(), arcompact_genops(), arcompact_op(), base_type_to_format_no_unfold(), base_type_to_format_unfold(), dex_resolve_fields_in_class(), dex_resolve_fields_in_class_as_symbols(), extract_all_fields(), extract_field(), extract_fields(), insert_field(), interpret_msrbank(), rz_base_type_as_format(), rz_bin_dex_fields(), rz_core_bin_fields_print(), rz_diff_fields_new(), rz_type_as_format_pair(), and type_to_format_pair().