Rizin
unix-like reverse engineering framework and cli tools
tricore-dis.c File Reference
#include <stdio.h>
#include <string.h>
#include <sys/types.h>
#include <stdbool.h>
#include "ansidecl.h"
#include "sysdep.h"
#include "opcode/tricore.h"
#include "disas-asm.h"
#include "libiberty.h"

Go to the source code of this file.

Classes

struct  insnlist
 
struct  pcplist
 
struct  sfrlist
 
struct  decoded_insn
 

Macros

#define REGPREFIX   ""
 
#define NUMOPCS   tricore_numopcodes
 
#define NUMSFRS   tricore_numsfrs
 
#define NUMPCPOPCS   pcp_numopcodes
 
#define MAX_OPS   5
 
#define MATCHES_ISA(isa)
 
#define NO_AREG   16
 
#define DPRINT   (*info->fprintf_func)
 
#define DFILE   info->stream
 
#define DPRINT   (*info->fprintf_func)
 
#define DFILE   info->stream
 

Typedefs

typedef struct tricore_opcode opcode_t
 
typedef struct pcp_opcode pcp_opcode_t
 
typedef const struct tricore_core_register sfr_t
 

Functions

static void decode_abs PARAMS ((void))
 
static const char *find_core_reg PARAMS ((unsigned long))
 
static void print_decoded_insn PARAMS ((bfd_vma, struct disassemble_info *))
 
static int decode_tricore_insn PARAMS ((bfd_vma, unsigned long, int, struct disassemble_info *))
 
static int decode_pcp_insn PARAMS ((bfd_vma, bfd_byte[4], struct disassemble_info *))
 
static unsigned long extract_off18 ()
 
static void decode_abs ()
 
static void decode_absb ()
 
static void decode_b ()
 
static void decode_bit ()
 
static void decode_bo ()
 
static void decode_bol ()
 
static void decode_brc ()
 
static void decode_brn ()
 
static void decode_brr ()
 
static void decode_rc ()
 
static void decode_rcpw ()
 
static void decode_rcr ()
 
static void decode_rcrr ()
 
static void decode_rcrw ()
 
static void decode_rlc ()
 
static void decode_rr ()
 
static void decode_rr1 ()
 
static void decode_rr2 ()
 
static void decode_rrpw ()
 
static void decode_rrr ()
 
static void decode_rrr1 ()
 
static void decode_rrr2 ()
 
static void decode_rrrr ()
 
static void decode_rrrw ()
 
static void decode_sys ()
 
static void decode_sb ()
 
static void decode_sbc ()
 
static void decode_sbr ()
 
static void decode_sbrn ()
 
static void decode_sc ()
 
static void decode_slr ()
 
static void decode_slro ()
 
static void decode_sr ()
 
static void decode_src ()
 
static void decode_sro ()
 
static void decode_srr ()
 
static void decode_srrs ()
 
static void decode_ssr ()
 
static void decode_ssro ()
 
static void init_hash_tables ()
 
static const char * find_core_reg (unsigned long addr)
 
static void print_decoded_insn (bfd_vma memaddr, struct disassemble_info *info)
 
static int decode_tricore_insn (bfd_vma memaddr, unsigned long insn, int len32, struct disassemble_info *info)
 
static int decode_pcp_insn (bfd_vma memaddr, buffer, struct disassemble_info *info)
 
int print_insn_tricore (bfd_vma memaddr, struct disassemble_info *info)
 

Variables

static struct insnlistinsns [64]
 
static struct insnlistinsnlink
 
static struct pcplistpcpinsns [32]
 
static struct pcplistpcplink
 
static struct sfrlistsfrs [256]
 
static struct sfrlistsfrlink
 
static int initialized = 0
 
static tricore_isa current_isa = TRICORE_RIDER_B
 
static struct decoded_insn dec_insn
 

Macro Definition Documentation

◆ DFILE [1/2]

#define DFILE   info->stream

◆ DFILE [2/2]

#define DFILE   info->stream

◆ DPRINT [1/2]

#define DPRINT   (*info->fprintf_func)

◆ DPRINT [2/2]

#define DPRINT   (*info->fprintf_func)

◆ MATCHES_ISA

#define MATCHES_ISA (   isa)
Value:
(((isa) == TRICORE_GENERIC) \
|| (((isa) & bfd_mach_rider_mask) & current_isa))
static tricore_isa current_isa
Definition: tricore-dis.c:100
@ TRICORE_GENERIC
Definition: tricore.h:29
#define bfd_mach_rider_mask
Definition: tricore.h:43

Definition at line 48 of file tricore-dis.c.

◆ MAX_OPS

#define MAX_OPS   5

Definition at line 47 of file tricore-dis.c.

◆ NO_AREG

#define NO_AREG   16

◆ NUMOPCS

#define NUMOPCS   tricore_numopcodes

Definition at line 44 of file tricore-dis.c.

◆ NUMPCPOPCS

#define NUMPCPOPCS   pcp_numopcodes

Definition at line 46 of file tricore-dis.c.

◆ NUMSFRS

#define NUMSFRS   tricore_numsfrs

Definition at line 45 of file tricore-dis.c.

◆ REGPREFIX

#define REGPREFIX   ""

Definition at line 41 of file tricore-dis.c.

Typedef Documentation

◆ opcode_t

typedef struct tricore_opcode opcode_t

Definition at line 1 of file tricore-dis.c.

◆ pcp_opcode_t

typedef struct pcp_opcode pcp_opcode_t

Definition at line 1 of file tricore-dis.c.

◆ sfr_t

Definition at line 1 of file tricore-dis.c.

Function Documentation

◆ decode_abs()

static void decode_abs ( )
static

Definition at line 204 of file tricore-dis.c.

205 {
206  int i;
207 
208  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
209  switch (dec_insn.code->fields[i]) {
210  case FMT_ABS_OFF18:
212  break;
213 
214  case FMT_ABS_S1_D:
215  dec_insn.regs[i] = (dec_insn.opcode & 0xf00) >> 8;
216  break;
217  }
218  }
219 }
lzma_index ** i
Definition: index.h:629
int regs[MAX_OPS]
Definition: tricore-dis.c:109
unsigned long opcode
Definition: tricore-dis.c:108
unsigned long cexp[MAX_OPS]
Definition: tricore-dis.c:110
opcode_t * code
Definition: tricore-dis.c:107
static unsigned long extract_off18()
Definition: tricore-dis.c:191
static struct decoded_insn dec_insn
Definition: tricore-dis.c:113
#define FMT_ABS_S1_D
Definition: tricore.h:265
#define FMT_ABS_OFF18
Definition: tricore.h:264

References decoded_insn::cexp, decoded_insn::code, dec_insn, extract_off18(), FMT_ABS_OFF18, FMT_ABS_S1_D, i, decoded_insn::opcode, and decoded_insn::regs.

◆ decode_absb()

static void decode_absb ( )
static

Definition at line 222 of file tricore-dis.c.

223 {
224  int i;
225 
226  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
227  switch (dec_insn.code->fields[i]) {
228  case FMT_ABSB_OFF18:
230  break;
231 
232  case FMT_ABSB_B:
233  dec_insn.cexp[i] = (dec_insn.opcode & 0x800) >> 11;
234  break;
235 
236  case FMT_ABSB_BPOS3:
237  dec_insn.cexp[i] = (dec_insn.opcode & 0x700) >> 8;
238  break;
239  }
240  }
241 }
#define FMT_ABSB_B
Definition: tricore.h:268
#define FMT_ABSB_OFF18
Definition: tricore.h:267
#define FMT_ABSB_BPOS3
Definition: tricore.h:269

References decoded_insn::cexp, decoded_insn::code, dec_insn, extract_off18(), FMT_ABSB_B, FMT_ABSB_BPOS3, FMT_ABSB_OFF18, i, and decoded_insn::opcode.

◆ decode_b()

static void decode_b ( )
static

Definition at line 244 of file tricore-dis.c.

245 {
246  int i;
247  unsigned long o1, o2;
248 
249  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
250  switch (dec_insn.code->fields[i]) {
251  case FMT_B_DISP24:
252  o1 = (dec_insn.opcode & 0xffff0000) >> 16;
253  o2 = (dec_insn.opcode & 0x0000ff00) << 8;
254  dec_insn.cexp[i] = o1 | o2;
255  break;
256  }
257  }
258 }
#define FMT_B_DISP24
Definition: tricore.h:271

References decoded_insn::cexp, decoded_insn::code, dec_insn, FMT_B_DISP24, i, o1, o2, and decoded_insn::opcode.

◆ decode_bit()

static void decode_bit ( )
static

Definition at line 261 of file tricore-dis.c.

262 {
263  int i;
264 
265  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
266  switch (dec_insn.code->fields[i]) {
267  case FMT_BIT_D:
268  dec_insn.regs[i] = (dec_insn.opcode & 0xf0000000) >> 28;
269  break;
270 
271  case FMT_BIT_P2:
272  dec_insn.cexp[i] = (dec_insn.opcode & 0x0f800000) >> 23;
273  break;
274 
275  case FMT_BIT_P1:
276  dec_insn.cexp[i] = (dec_insn.opcode & 0x001f0000) >> 16;
277  break;
278 
279  case FMT_BIT_S2:
280  dec_insn.regs[i] = (dec_insn.opcode & 0x0000f000) >> 12;
281  break;
282 
283  case FMT_BIT_S1:
284  dec_insn.regs[i] = (dec_insn.opcode & 0x00000f00) >> 8;
285  break;
286  }
287  }
288 }
#define FMT_BIT_P1
Definition: tricore.h:275
#define FMT_BIT_S2
Definition: tricore.h:276
#define FMT_BIT_P2
Definition: tricore.h:274
#define FMT_BIT_D
Definition: tricore.h:273
#define FMT_BIT_S1
Definition: tricore.h:277

References decoded_insn::cexp, decoded_insn::code, dec_insn, FMT_BIT_D, FMT_BIT_P1, FMT_BIT_P2, FMT_BIT_S1, FMT_BIT_S2, i, decoded_insn::opcode, and decoded_insn::regs.

◆ decode_bo()

static void decode_bo ( )
static

Definition at line 291 of file tricore-dis.c.

292 {
293  int i;
294  unsigned long o1, o2;
295 
296  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
297  switch (dec_insn.code->fields[i]) {
298  case FMT_BO_OFF10:
299  o1 = (dec_insn.opcode & 0x003f0000) >> 16;
300  o2 = (dec_insn.opcode & 0xf0000000) >> 22;
301  dec_insn.cexp[i] = o1 | o2;
302  break;
303 
304  case FMT_BO_S2:
305  dec_insn.regs[i] = (dec_insn.opcode & 0x0000f000) >> 12;
306  break;
307 
308  case FMT_BO_S1_D:
309  dec_insn.regs[i] = (dec_insn.opcode & 0x00000f00) >> 8;
310  break;
311  }
312  }
313 }
#define FMT_BO_OFF10
Definition: tricore.h:279
#define FMT_BO_S2
Definition: tricore.h:280
#define FMT_BO_S1_D
Definition: tricore.h:281

References decoded_insn::cexp, decoded_insn::code, dec_insn, FMT_BO_OFF10, FMT_BO_S1_D, FMT_BO_S2, i, o1, o2, decoded_insn::opcode, and decoded_insn::regs.

◆ decode_bol()

static void decode_bol ( )
static

Definition at line 316 of file tricore-dis.c.

317 {
318  int i;
319  unsigned long o1, o2, o3;
320 
321  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
322  switch (dec_insn.code->fields[i]) {
323  case FMT_BOL_OFF16:
324  o1 = (dec_insn.opcode & 0x003f0000) >> 16;
325  o2 = (dec_insn.opcode & 0xf0000000) >> 22;
326  o3 = (dec_insn.opcode & 0x0fc00000) >> 12;
327  dec_insn.cexp[i] = o1 | o2 | o3;
328  break;
329 
330  case FMT_BOL_S2:
331  dec_insn.regs[i] = (dec_insn.opcode & 0x0000f000) >> 12;
332  break;
333 
334  case FMT_BOL_S1_D:
335  dec_insn.regs[i] = (dec_insn.opcode & 0x00000f00) >> 8;
336  break;
337  }
338  }
339 }
#define FMT_BOL_S1_D
Definition: tricore.h:285
#define FMT_BOL_OFF16
Definition: tricore.h:283
#define FMT_BOL_S2
Definition: tricore.h:284

References decoded_insn::cexp, decoded_insn::code, dec_insn, FMT_BOL_OFF16, FMT_BOL_S1_D, FMT_BOL_S2, i, o1, o2, decoded_insn::opcode, and decoded_insn::regs.

◆ decode_brc()

static void decode_brc ( )
static

Definition at line 342 of file tricore-dis.c.

343 {
344  int i;
345 
346  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
347  switch (dec_insn.code->fields[i]) {
348  case FMT_BRC_DISP15:
349  dec_insn.cexp[i] = (dec_insn.opcode & 0x7fff0000) >> 16;
350  break;
351 
352  case FMT_BRC_CONST4:
353  dec_insn.cexp[i] = (dec_insn.opcode & 0x0000f000) >> 12;
354  break;
355 
356  case FMT_BRC_S1:
357  dec_insn.regs[i] = (dec_insn.opcode & 0x00000f00) >> 8;
358  break;
359  }
360  }
361 }
#define FMT_BRC_S1
Definition: tricore.h:289
#define FMT_BRC_DISP15
Definition: tricore.h:287
#define FMT_BRC_CONST4
Definition: tricore.h:288

References decoded_insn::cexp, decoded_insn::code, dec_insn, FMT_BRC_CONST4, FMT_BRC_DISP15, FMT_BRC_S1, i, decoded_insn::opcode, and decoded_insn::regs.

◆ decode_brn()

static void decode_brn ( )
static

Definition at line 364 of file tricore-dis.c.

365 {
366  int i;
367 
368  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
369  switch (dec_insn.code->fields[i]) {
370  case FMT_BRN_DISP15:
371  dec_insn.cexp[i] = (dec_insn.opcode & 0x7fff0000) >> 16;
372  break;
373 
374  case FMT_BRN_N:
375  dec_insn.cexp[i] = (dec_insn.opcode & 0x0000f000) >> 12;
376  dec_insn.cexp[i] |= (dec_insn.opcode & 0x00000080) >> 3;
377  break;
378 
379  case FMT_BRN_S1:
380  dec_insn.regs[i] = (dec_insn.opcode & 0x00000f00) >> 8;
381  break;
382  }
383  }
384 }
#define FMT_BRN_DISP15
Definition: tricore.h:291
#define FMT_BRN_S1
Definition: tricore.h:293
#define FMT_BRN_N
Definition: tricore.h:292

References decoded_insn::cexp, decoded_insn::code, dec_insn, FMT_BRN_DISP15, FMT_BRN_N, FMT_BRN_S1, i, decoded_insn::opcode, and decoded_insn::regs.

◆ decode_brr()

static void decode_brr ( )
static

Definition at line 387 of file tricore-dis.c.

388 {
389  int i;
390 
391  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
392  switch (dec_insn.code->fields[i]) {
393  case FMT_BRR_DISP15:
394  dec_insn.cexp[i] = (dec_insn.opcode & 0x7fff0000) >> 16;
395  break;
396 
397  case FMT_BRR_S2:
398  dec_insn.regs[i] = (dec_insn.opcode & 0x0000f000) >> 12;
399  break;
400 
401  case FMT_BRR_S1:
402  dec_insn.regs[i] = (dec_insn.opcode & 0x00000f00) >> 8;
403  break;
404  }
405  }
406 }
#define FMT_BRR_S1
Definition: tricore.h:297
#define FMT_BRR_DISP15
Definition: tricore.h:295
#define FMT_BRR_S2
Definition: tricore.h:296

References decoded_insn::cexp, decoded_insn::code, dec_insn, FMT_BRR_DISP15, FMT_BRR_S1, FMT_BRR_S2, i, decoded_insn::opcode, and decoded_insn::regs.

◆ decode_pcp_insn()

static int decode_pcp_insn ( bfd_vma  memaddr,
buffer  ,
struct disassemble_info info 
)
static

Definition at line 1596 of file tricore-dis.c.

1600 {
1601  unsigned long insn = 0, insn2 = 0, val;
1602  int idx, fail, rb, ra;
1603  struct pcplist *pinsn;
1604  pcp_opcode_t *pop = (pcp_opcode_t *) NULL;
1605  static const char *pcp_ccodes[] =
1606  {
1607  "uc", "z", "nz", "v", "c/ult", "ugt", "slt", "sgt", /* CONDCA */
1608  "n", "nn", "nv", "nc/uge", "sge", "sle", "cnz", "cnn" /* CONDCB */
1609  };
1610 #define DPRINT (*info->fprintf_func)
1611 #define DFILE info->stream
1612 
1613  /* Try to find the PCP instruction matching the given opcode. */
1614  insn = bfd_getl16 (buffer);
1615  idx = (insn >> 11) & 0x1f;
1616  for (pinsn = pcpinsns[idx]; pinsn != NULL; pinsn = pinsn->next)
1617  {
1618  if (((insn & pinsn->code->opcode) != pinsn->code->opcode) || (insn & pinsn->code->lose)) {
1619  continue;
1620  }
1621 
1622  /* A valid instruction was found. */
1623  pop = pinsn->code;
1624  if (pop->len32) {
1625  /* This is a 32-bit insn; try to read 2 more bytes. */
1626  fail = (*info->read_memory_func) (memaddr + 2, &buffer[2], 2, info);
1627  if (fail) {
1628  DPRINT (DFILE, ".hword 0x%04lx", insn);
1629  return 2;
1630  }
1631  insn2 = bfd_getl16 (buffer + 2);
1632  }
1633 
1634  break;
1635  }
1636 
1637  if (!pop)
1638  {
1639  /* No valid instruction was found; print it as a 16-bit word. */
1640  DPRINT (DFILE, ".hword 0x%04lx", (insn & 0xffff));
1641 
1642  return 2;
1643  }
1644 
1645  /* Print the instruction. */
1646  DPRINT (DFILE, "%s ", pop->name);
1647  switch (pop->fmt_group)
1648  {
1649  case 0:
1650  for (idx = 0; idx < pop->nr_operands; ++idx)
1651  {
1652  switch (pop->args[idx])
1653  {
1654  case 'd':
1655  val = (insn >> 9) & 0x3;
1656  if (val == 0) {
1657  DPRINT (DFILE, "dst");
1658  } else if (val == 1) {
1659  DPRINT (DFILE, "dst+");
1660  } else if (val == 2) {
1661  DPRINT (DFILE, "dst-");
1662  } else {
1663  DPRINT (DFILE, "dst *ILLEGAL*");
1664  }
1665  break;
1666 
1667  case 's':
1668  val = (insn >> 7) & 0x3;
1669  if (val == 0) {
1670  DPRINT (DFILE, "src");
1671  } else if (val == 1) {
1672  DPRINT (DFILE, "src+");
1673  } else if (val == 2) {
1674  DPRINT (DFILE, "src-");
1675  } else {
1676  DPRINT (DFILE, "src *ILLEGAL*");
1677  }
1678  break;
1679 
1680  case 'c':
1681  val = (insn >> 5) & 0x3;
1682  DPRINT (DFILE, "cnc=%lu", val);
1683  break;
1684 
1685  case 'n':
1686  if (!strcmp (pop->name, "copy")) {
1687  val = ((insn >> 2) & 0x7) + 1;
1688  } else {
1689  val = (insn >> 2) & 0x3;
1690  if (val == 0) {
1691  val = 8;
1692  } else if (val == 3) {
1693  val = 4;
1694  }
1695  }
1696  DPRINT (DFILE, "cnt0=%lu", val);
1697  break;
1698 
1699  case 'f':
1700  val = 8 << (insn & 0x3);
1701  DPRINT (DFILE, "size=%lu", val);
1702  break;
1703 
1704  case 'a':
1705  case 'b':
1706  val = insn & 0xf;
1707  DPRINT (DFILE, "cc_%s", pcp_ccodes[val]);
1708  break;
1709 
1710  case 'g':
1711  val = (insn >> 10) & 0x1;
1712  DPRINT (DFILE, "st=%lu", val);
1713  break;
1714 
1715  case 'i':
1716  val = (insn >> 9) & 0x1;
1717  DPRINT (DFILE, "int=%lu", val);
1718  break;
1719 
1720  case 'j':
1721  val = (insn >> 8) & 0x1;
1722  DPRINT (DFILE, "ep=%lu", val);
1723  break;
1724 
1725  case 'h':
1726  val = (insn >> 7) & 0x1;
1727  DPRINT (DFILE, "ec=%lu", val);
1728  break;
1729 
1730  default:
1731  DPRINT (DFILE, "***UNKNOWN OPERAND `%c'***", pop->args[idx]);
1732  break;
1733  }
1734  if (idx < (pop->nr_operands - 1)) {
1735  DPRINT (DFILE, ", ");
1736  }
1737  }
1738  break;
1739 
1740  case 1:
1741  rb = (insn >> 6) & 0x7;
1742  ra = (insn >> 3) & 0x7;
1743  val = 8 << (insn & 0x3);
1744  DPRINT (DFILE, "r%d, [r%d], size=%lu", rb, ra, val);
1745  break;
1746 
1747  case 2:
1748  ra = (insn >> 6) & 0x7;
1749  val = insn & 0x3f;
1750  DPRINT (DFILE, "r%d, [%lu]", ra, val);
1751  break;
1752 
1753  case 3:
1754  rb = (insn >> 6) & 0x7;
1755  ra = (insn >> 3) & 0x7;
1756  val = insn & 0x7;
1757  if (!strcmp (pop->name, "ld.p") || !strcmp (pop->name, "st.p")) {
1758  DPRINT (DFILE, "cc_%s, r%d, [r%d]", pcp_ccodes[val], rb, ra);
1759  } else {
1760  DPRINT (DFILE, "cc_%s, r%d, r%d", pcp_ccodes[val], rb, ra);
1761  }
1762  break;
1763 
1764  case 4:
1765  ra = (insn >> 6) & 0x7;
1766  val = insn & 0x3f;
1767  if (!strcmp (pop->name, "chkb")) {
1768  DPRINT (DFILE, "r%d, %lu, %s", ra, val & 0x1f,
1769  (val & 0x20) ? "set" : "clr");
1770  } else if (!strcmp (pop->name, "ldl.il")) {
1771  DPRINT (DFILE, "r%d, 0x....%04lx", ra, insn2);
1772  } else if (!strcmp (pop->name, "ldl.iu")) {
1773  DPRINT (DFILE, "r%d, 0x%04lx....", ra, insn2);
1774  } else {
1775  DPRINT (DFILE, "r%d, %lu", ra, val);
1776  }
1777  break;
1778 
1779  case 5:
1780  ra = (insn >> 6) & 0x7;
1781  val = 8 << (((insn >> 5) & 0x1) | ((insn >> 8) & 0x2));
1782  if ((!strcmp (pop->name, "set.f") || !strcmp (pop->name, "clr.f")) && ((insn & 0x1f) >= val)) {
1783  DPRINT (DFILE, "[r%d], %lu ***ILLEGAL VALUE***, size=%lu", ra,
1784  insn & 0x1f, val);
1785  } else {
1786  DPRINT (DFILE, "[r%d], %lu, size=%lu", ra, insn & 0x1f, val);
1787  }
1788  break;
1789 
1790  case 6:
1791  rb = (insn >> 6) & 0x7;
1792  ra = (insn >> 3) & 0x7;
1793  if ((rb == 0) || (ra == 0) || (rb == 7) || (ra == 7) || (rb == ra)) {
1794  DPRINT (DFILE, "r%d, r%d ***ILLEGAL REGISTER USE***", rb, ra);
1795  } else {
1796  DPRINT (DFILE, "r%d, r%d", rb, ra);
1797  }
1798  break;
1799 
1800  case 7:
1801  for (idx = 0; idx < pop->nr_operands; ++idx)
1802  {
1803  switch (pop->args[idx])
1804  {
1805  case 'r':
1806  case 'R':
1807  DPRINT (DFILE, "[r%lu]", (insn >> 3) & 0x7);
1808  break;
1809 
1810  case 'm':
1811  DPRINT (DFILE, "dac=%lu", (insn >> 3) & 0x1);
1812  break;
1813 
1814  case 'a':
1815  case 'b':
1816  DPRINT (DFILE, "cc_%s", pcp_ccodes[(insn >> 6) & 0xf]);
1817  break;
1818 
1819  case 'o':
1820  DPRINT (DFILE, "rta=%lu", (insn >> 2) & 0x1);
1821  break;
1822 
1823  case 'p':
1824  DPRINT (DFILE, "eda=%lu", (insn >> 1) & 0x1);
1825  break;
1826 
1827  case 'q':
1828  DPRINT (DFILE, "sdb=%lu", insn & 1);
1829  break;
1830 
1831  case 'e':
1832  if (!strcmp (pop->name, "jl"))
1833  {
1834  val = insn & 0x3ff;
1835  if (val & 0x200) {
1836  val |= ~0x3ff;
1837  }
1838  (*info->print_address_func) (memaddr + 2 + (val << 1), info);
1839  }
1840  else if (!strcmp (pop->name, "jc"))
1841  {
1842  val = insn & 0x3f;
1843  if (val & 0x20) {
1844  val |= ~0x3f;
1845  }
1846  (*info->print_address_func) (memaddr + 2 + (val << 1), info);
1847  } else if (!strcmp (pop->name, "jc.a")) {
1848  /* FIXME: address should be PCODE_BASE + (insn2 << 1). */
1849  (*info->print_address_func) ((memaddr & 0xffff0000) + (insn2 << 1), info);
1850  } else {
1851  DPRINT (DFILE, "***ILLEGAL expr FOR %s***", pop->name);
1852  }
1853  break;
1854 
1855  default:
1856  DPRINT (DFILE, "***UNKNOWN OPERAND `%c'***", pop->args[idx]);
1857  break;
1858  }
1859  if (idx < (pop->nr_operands - 1)) {
1860  DPRINT (DFILE, ", ");
1861  }
1862  }
1863  break;
1864 
1865  default:
1866  DPRINT (DFILE, "***ILLEGAL FORMAT GROUP %d***", pop->fmt_group);
1867  break;
1868  }
1869 
1870  return pop->len32 ? 4 : 2;
1871 #undef DPRINT
1872 #undef DFILE
1873 }
ut16 val
Definition: armass64_const.h:6
RzBinInfo * info(RzBinFile *bf)
Definition: bin_ne.c:86
#define NULL
Definition: cris-opc.c:27
static bfd_vma bfd_getl16(const void *p)
Definition: mybfd.h:4969
int idx
Definition: setup.py:197
Definition: buffer.h:15
const int nr_operands
Definition: tricore.h:188
const unsigned long lose
Definition: tricore.h:185
const char * args
Definition: tricore.h:189
const int len32
Definition: tricore.h:183
const char * name
Definition: tricore.h:182
const unsigned long opcode
Definition: tricore.h:184
const int fmt_group
Definition: tricore.h:186
struct pcplist * next
Definition: tricore-dis.c:77
pcp_opcode_t * code
Definition: tricore-dis.c:76
#define fail(test)
Definition: tests.h:29
#define DPRINT
static struct pcplist * pcpinsns[32]
Definition: tricore-dis.c:80
#define DFILE

References pcp_opcode::args, bfd_getl16(), pcplist::code, DFILE, DPRINT, fail, pcp_opcode::fmt_group, setup::idx, info(), pcp_opcode::len32, pcp_opcode::lose, pcp_opcode::name, pcplist::next, pcp_opcode::nr_operands, NULL, pcp_opcode::opcode, pcpinsns, and val.

Referenced by print_insn_tricore().

◆ decode_rc()

static void decode_rc ( )
static

Definition at line 409 of file tricore-dis.c.

410 {
411  int i;
412 
413  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
414  switch (dec_insn.code->fields[i]) {
415  case FMT_RC_D:
416  dec_insn.regs[i] = (dec_insn.opcode & 0xf0000000) >> 28;
417  break;
418 
419  case FMT_RC_CONST9:
420  dec_insn.cexp[i] = (dec_insn.opcode & 0x001ff000) >> 12;
421  break;
422 
423  case FMT_RC_S1:
424  dec_insn.regs[i] = (dec_insn.opcode & 0x00000f00) >> 8;
425  }
426  }
427 }
#define FMT_RC_D
Definition: tricore.h:299
#define FMT_RC_S1
Definition: tricore.h:301
#define FMT_RC_CONST9
Definition: tricore.h:300

References decoded_insn::cexp, decoded_insn::code, dec_insn, FMT_RC_CONST9, FMT_RC_D, FMT_RC_S1, i, decoded_insn::opcode, and decoded_insn::regs.

◆ decode_rcpw()

static void decode_rcpw ( )
static

Definition at line 430 of file tricore-dis.c.

431 {
432  int i;
433 
434  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
435  switch (dec_insn.code->fields[i]) {
436  case FMT_RCPW_D:
437  dec_insn.regs[i] = (dec_insn.opcode & 0xf0000000) >> 28;
438  break;
439 
440  case FMT_RCPW_P:
441  dec_insn.cexp[i] = (dec_insn.opcode & 0x0f800000) >> 23;
442  break;
443 
444  case FMT_RCPW_W:
445  dec_insn.cexp[i] = (dec_insn.opcode & 0x001f0000) >> 16;
446  break;
447 
448  case FMT_RCPW_CONST4:
449  dec_insn.cexp[i] = (dec_insn.opcode & 0x0000f000) >> 12;
450  break;
451 
452  case FMT_RCPW_S1:
453  dec_insn.regs[i] = (dec_insn.opcode & 0x00000f00) >> 8;
454  break;
455  }
456  }
457 }
#define FMT_RCPW_S1
Definition: tricore.h:307
#define FMT_RCPW_P
Definition: tricore.h:304
#define FMT_RCPW_CONST4
Definition: tricore.h:306
#define FMT_RCPW_D
Definition: tricore.h:303
#define FMT_RCPW_W
Definition: tricore.h:305

References decoded_insn::cexp, decoded_insn::code, dec_insn, FMT_RCPW_CONST4, FMT_RCPW_D, FMT_RCPW_P, FMT_RCPW_S1, FMT_RCPW_W, i, decoded_insn::opcode, and decoded_insn::regs.

◆ decode_rcr()

static void decode_rcr ( )
static

Definition at line 460 of file tricore-dis.c.

461 {
462  int i;
463 
464  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
465  switch (dec_insn.code->fields[i]) {
466  case FMT_RCR_D:
467  dec_insn.regs[i] = (dec_insn.opcode & 0xf0000000) >> 28;
468  break;
469 
470  case FMT_RCR_S3:
471  dec_insn.regs[i] = (dec_insn.opcode & 0x0f000000) >> 24;
472  break;
473 
474  case FMT_RCR_CONST9:
475  dec_insn.cexp[i] = (dec_insn.opcode & 0x001ff000) >> 12;
476  break;
477 
478  case FMT_RCR_S1:
479  dec_insn.regs[i] = (dec_insn.opcode & 0x00000f00) >> 8;
480  break;
481  }
482  }
483 }
#define FMT_RCR_CONST9
Definition: tricore.h:311
#define FMT_RCR_D
Definition: tricore.h:309
#define FMT_RCR_S1
Definition: tricore.h:312
#define FMT_RCR_S3
Definition: tricore.h:310

References decoded_insn::cexp, decoded_insn::code, dec_insn, FMT_RCR_CONST9, FMT_RCR_D, FMT_RCR_S1, FMT_RCR_S3, i, decoded_insn::opcode, and decoded_insn::regs.

◆ decode_rcrr()

static void decode_rcrr ( )
static

Definition at line 486 of file tricore-dis.c.

487 {
488  int i;
489 
490  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
491  switch (dec_insn.code->fields[i]) {
492  case FMT_RCRR_D:
493  dec_insn.regs[i] = (dec_insn.opcode & 0xf0000000) >> 28;
494  break;
495 
496  case FMT_RCRR_S3:
497  dec_insn.regs[i] = (dec_insn.opcode & 0x0f000000) >> 24;
498  break;
499 
500  case FMT_RCRR_CONST4:
501  dec_insn.cexp[i] = (dec_insn.opcode & 0x0000f000) >> 12;
502  break;
503 
504  case FMT_RCRR_S1:
505  dec_insn.regs[i] = (dec_insn.opcode & 0x00000f00) >> 8;
506  break;
507  }
508  }
509 }
#define FMT_RCRR_D
Definition: tricore.h:314
#define FMT_RCRR_CONST4
Definition: tricore.h:316
#define FMT_RCRR_S1
Definition: tricore.h:317
#define FMT_RCRR_S3
Definition: tricore.h:315

References decoded_insn::cexp, decoded_insn::code, dec_insn, FMT_RCRR_CONST4, FMT_RCRR_D, FMT_RCRR_S1, FMT_RCRR_S3, i, decoded_insn::opcode, and decoded_insn::regs.

◆ decode_rcrw()

static void decode_rcrw ( )
static

Definition at line 512 of file tricore-dis.c.

513 {
514  int i;
515 
516  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
517  switch (dec_insn.code->fields[i]) {
518  case FMT_RCRW_D:
519  dec_insn.regs[i] = (dec_insn.opcode & 0xf0000000) >> 28;
520  break;
521 
522  case FMT_RCRW_S3:
523  dec_insn.regs[i] = (dec_insn.opcode & 0x0f000000) >> 24;
524  break;
525 
526  case FMT_RCRW_W:
527  dec_insn.cexp[i] = (dec_insn.opcode & 0x001f0000) >> 16;
528  break;
529 
530  case FMT_RCRW_CONST4:
531  dec_insn.cexp[i] = (dec_insn.opcode & 0x0000f000) >> 12;
532  break;
533 
534  case FMT_RCRW_S1:
535  dec_insn.regs[i] = (dec_insn.opcode & 0x00000f00) >> 8;
536  break;
537  }
538  }
539 }
#define FMT_RCRW_D
Definition: tricore.h:319
#define FMT_RCRW_W
Definition: tricore.h:321
#define FMT_RCRW_CONST4
Definition: tricore.h:322
#define FMT_RCRW_S1
Definition: tricore.h:323
#define FMT_RCRW_S3
Definition: tricore.h:320

References decoded_insn::cexp, decoded_insn::code, dec_insn, FMT_RCRW_CONST4, FMT_RCRW_D, FMT_RCRW_S1, FMT_RCRW_S3, FMT_RCRW_W, i, decoded_insn::opcode, and decoded_insn::regs.

◆ decode_rlc()

static void decode_rlc ( )
static

Definition at line 542 of file tricore-dis.c.

543 {
544  int i;
545 
546  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
547  switch (dec_insn.code->fields[i]) {
548  case FMT_RLC_D:
549  dec_insn.regs[i] = (dec_insn.opcode & 0xf0000000) >> 28;
550  break;
551 
552  case FMT_RLC_CONST16:
553  dec_insn.cexp[i] = (dec_insn.opcode & 0x0ffff000) >> 12;
554  break;
555 
556  case FMT_RLC_S1:
557  dec_insn.regs[i] = (dec_insn.opcode & 0x00000f00) >> 8;
558  break;
559  }
560  }
561 }
#define FMT_RLC_CONST16
Definition: tricore.h:326
#define FMT_RLC_S1
Definition: tricore.h:327
#define FMT_RLC_D
Definition: tricore.h:325

References decoded_insn::cexp, decoded_insn::code, dec_insn, FMT_RLC_CONST16, FMT_RLC_D, FMT_RLC_S1, i, decoded_insn::opcode, and decoded_insn::regs.

◆ decode_rr()

static void decode_rr ( )
static

Definition at line 564 of file tricore-dis.c.

565 {
566  int i;
567 
568  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
569  switch (dec_insn.code->fields[i]) {
570  case FMT_RR_D:
571  dec_insn.regs[i] = (dec_insn.opcode & 0xf0000000) >> 28;
572  break;
573 
574  case FMT_RR_N:
575  dec_insn.cexp[i] = (dec_insn.opcode & 0x00030000) >> 16;
576  break;
577 
578  case FMT_RR_S2:
579  dec_insn.regs[i] = (dec_insn.opcode & 0x0000f000) >> 12;
580  break;
581 
582  case FMT_RR_S1:
583  dec_insn.regs[i] = (dec_insn.opcode & 0x00000f00) >> 8;
584  break;
585  }
586  }
587 }
#define FMT_RR_N
Definition: tricore.h:330
#define FMT_RR_S1
Definition: tricore.h:332
#define FMT_RR_D
Definition: tricore.h:329
#define FMT_RR_S2
Definition: tricore.h:331

References decoded_insn::cexp, decoded_insn::code, dec_insn, FMT_RR_D, FMT_RR_N, FMT_RR_S1, FMT_RR_S2, i, decoded_insn::opcode, and decoded_insn::regs.

◆ decode_rr1()

static void decode_rr1 ( )
static

Definition at line 590 of file tricore-dis.c.

591 {
592  int i;
593 
594  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
595  switch (dec_insn.code->fields[i]) {
596  case FMT_RR1_D:
597  dec_insn.regs[i] = (dec_insn.opcode & 0xf0000000) >> 28;
598  break;
599 
600  case FMT_RR1_N:
601  dec_insn.cexp[i] = (dec_insn.opcode & 0x00030000) >> 16;
602  break;
603 
604  case FMT_RR1_S2:
605  dec_insn.regs[i] = (dec_insn.opcode & 0x0000f000) >> 12;
606  break;
607 
608  case FMT_RR1_S1:
609  dec_insn.regs[i] = (dec_insn.opcode & 0x00000f00) >> 8;
610  break;
611  }
612  }
613 }
#define FMT_RR1_D
Definition: tricore.h:334
#define FMT_RR1_S2
Definition: tricore.h:336
#define FMT_RR1_S1
Definition: tricore.h:337
#define FMT_RR1_N
Definition: tricore.h:335

References decoded_insn::cexp, decoded_insn::code, dec_insn, FMT_RR1_D, FMT_RR1_N, FMT_RR1_S1, FMT_RR1_S2, i, decoded_insn::opcode, and decoded_insn::regs.

◆ decode_rr2()

static void decode_rr2 ( )
static

Definition at line 616 of file tricore-dis.c.

617 {
618  int i;
619 
620  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
621  switch (dec_insn.code->fields[i]) {
622  case FMT_RR2_D:
623  dec_insn.regs[i] = (dec_insn.opcode & 0xf0000000) >> 28;
624  break;
625 
626  case FMT_RR2_S2:
627  dec_insn.regs[i] = (dec_insn.opcode & 0x0000f000) >> 12;
628  break;
629 
630  case FMT_RR2_S1:
631  dec_insn.regs[i] = (dec_insn.opcode & 0x00000f00) >> 8;
632  break;
633  }
634  }
635 }
#define FMT_RR2_S2
Definition: tricore.h:340
#define FMT_RR2_S1
Definition: tricore.h:341
#define FMT_RR2_D
Definition: tricore.h:339

References decoded_insn::code, dec_insn, FMT_RR2_D, FMT_RR2_S1, FMT_RR2_S2, i, decoded_insn::opcode, and decoded_insn::regs.

◆ decode_rrpw()

static void decode_rrpw ( )
static

Definition at line 638 of file tricore-dis.c.

639 {
640  int i;
641 
642  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
643  switch (dec_insn.code->fields[i]) {
644  case FMT_RRPW_D:
645  dec_insn.regs[i] = (dec_insn.opcode & 0xf0000000) >> 28;
646  break;
647 
648  case FMT_RRPW_P:
649  dec_insn.cexp[i] = (dec_insn.opcode & 0x0f800000) >> 23;
650  break;
651 
652  case FMT_RRPW_W:
653  dec_insn.cexp[i] = (dec_insn.opcode & 0x001f0000) >> 16;
654  break;
655 
656  case FMT_RRPW_S2:
657  dec_insn.regs[i] = (dec_insn.opcode & 0x0000f000) >> 12;
658  break;
659 
660  case FMT_RRPW_S1:
661  dec_insn.regs[i] = (dec_insn.opcode & 0x00000f00) >> 8;
662  break;
663  }
664  }
665 }
#define FMT_RRPW_W
Definition: tricore.h:345
#define FMT_RRPW_S1
Definition: tricore.h:347
#define FMT_RRPW_P
Definition: tricore.h:344
#define FMT_RRPW_D
Definition: tricore.h:343
#define FMT_RRPW_S2
Definition: tricore.h:346

References decoded_insn::cexp, decoded_insn::code, dec_insn, FMT_RRPW_D, FMT_RRPW_P, FMT_RRPW_S1, FMT_RRPW_S2, FMT_RRPW_W, i, decoded_insn::opcode, and decoded_insn::regs.

◆ decode_rrr()

static void decode_rrr ( )
static

Definition at line 668 of file tricore-dis.c.

669 {
670  int i;
671 
672  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
673  switch (dec_insn.code->fields[i]) {
674  case FMT_RRR_D:
675  dec_insn.regs[i] = (dec_insn.opcode & 0xf0000000) >> 28;
676  break;
677 
678  case FMT_RRR_S3:
679  dec_insn.regs[i] = (dec_insn.opcode & 0x0f000000) >> 24;
680  break;
681 
682  case FMT_RRR_N:
683  dec_insn.cexp[i] = (dec_insn.opcode & 0x00030000) >> 16;
684  break;
685 
686  case FMT_RRR_S2:
687  dec_insn.regs[i] = (dec_insn.opcode & 0x0000f000) >> 12;
688  break;
689 
690  case FMT_RRR_S1:
691  dec_insn.regs[i] = (dec_insn.opcode & 0x00000f00) >> 8;
692  break;
693  }
694  }
695 }
#define FMT_RRR_N
Definition: tricore.h:351
#define FMT_RRR_S2
Definition: tricore.h:352
#define FMT_RRR_S1
Definition: tricore.h:353
#define FMT_RRR_D
Definition: tricore.h:349
#define FMT_RRR_S3
Definition: tricore.h:350

References decoded_insn::cexp, decoded_insn::code, dec_insn, FMT_RRR_D, FMT_RRR_N, FMT_RRR_S1, FMT_RRR_S2, FMT_RRR_S3, i, decoded_insn::opcode, and decoded_insn::regs.

◆ decode_rrr1()

static void decode_rrr1 ( )
static

Definition at line 698 of file tricore-dis.c.

699 {
700  int i;
701 
702  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
703  switch (dec_insn.code->fields[i]) {
704  case FMT_RRR1_D:
705  dec_insn.regs[i] = (dec_insn.opcode & 0xf0000000) >> 28;
706  break;
707 
708  case FMT_RRR1_S3:
709  dec_insn.regs[i] = (dec_insn.opcode & 0x0f000000) >> 24;
710  break;
711 
712  case FMT_RRR1_N:
713  dec_insn.cexp[i] = (dec_insn.opcode & 0x00030000) >> 16;
714  break;
715 
716  case FMT_RRR1_S2:
717  dec_insn.regs[i] = (dec_insn.opcode & 0x0000f000) >> 12;
718  break;
719 
720  case FMT_RRR1_S1:
721  dec_insn.regs[i] = (dec_insn.opcode & 0x00000f00) >> 8;
722  break;
723  }
724  }
725 }
#define FMT_RRR1_S1
Definition: tricore.h:359
#define FMT_RRR1_S3
Definition: tricore.h:356
#define FMT_RRR1_D
Definition: tricore.h:355
#define FMT_RRR1_S2
Definition: tricore.h:358
#define FMT_RRR1_N
Definition: tricore.h:357

References decoded_insn::cexp, decoded_insn::code, dec_insn, FMT_RRR1_D, FMT_RRR1_N, FMT_RRR1_S1, FMT_RRR1_S2, FMT_RRR1_S3, i, decoded_insn::opcode, and decoded_insn::regs.

◆ decode_rrr2()

static void decode_rrr2 ( )
static

Definition at line 728 of file tricore-dis.c.

729 {
730  int i;
731 
732  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
733  switch (dec_insn.code->fields[i]) {
734  case FMT_RRR2_D:
735  dec_insn.regs[i] = (dec_insn.opcode & 0xf0000000) >> 28;
736  break;
737 
738  case FMT_RRR2_S3:
739  dec_insn.regs[i] = (dec_insn.opcode & 0x0f000000) >> 24;
740  break;
741 
742  case FMT_RRR2_S2:
743  dec_insn.regs[i] = (dec_insn.opcode & 0x0000f000) >> 12;
744  break;
745 
746  case FMT_RRR2_S1:
747  dec_insn.regs[i] = (dec_insn.opcode & 0x00000f00) >> 8;
748  break;
749  }
750  }
751 }
#define FMT_RRR2_D
Definition: tricore.h:361
#define FMT_RRR2_S2
Definition: tricore.h:363
#define FMT_RRR2_S1
Definition: tricore.h:364
#define FMT_RRR2_S3
Definition: tricore.h:362

References decoded_insn::code, dec_insn, FMT_RRR2_D, FMT_RRR2_S1, FMT_RRR2_S2, FMT_RRR2_S3, i, decoded_insn::opcode, and decoded_insn::regs.

◆ decode_rrrr()

static void decode_rrrr ( )
static

Definition at line 754 of file tricore-dis.c.

755 {
756  int i;
757 
758  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
759  switch (dec_insn.code->fields[i]) {
760  case FMT_RRRR_D:
761  dec_insn.regs[i] = (dec_insn.opcode & 0xf0000000) >> 28;
762  break;
763 
764  case FMT_RRRR_S3:
765  dec_insn.regs[i] = (dec_insn.opcode & 0x0f000000) >> 24;
766  break;
767 
768  case FMT_RRRR_S2:
769  dec_insn.regs[i] = (dec_insn.opcode & 0x0000f000) >> 12;
770  break;
771 
772  case FMT_RRRR_S1:
773  dec_insn.regs[i] = (dec_insn.opcode & 0x00000f00) >> 8;
774  break;
775  }
776  }
777 }
#define FMT_RRRR_S3
Definition: tricore.h:367
#define FMT_RRRR_D
Definition: tricore.h:366
#define FMT_RRRR_S1
Definition: tricore.h:369
#define FMT_RRRR_S2
Definition: tricore.h:368

References decoded_insn::code, dec_insn, FMT_RRRR_D, FMT_RRRR_S1, FMT_RRRR_S2, FMT_RRRR_S3, i, decoded_insn::opcode, and decoded_insn::regs.

◆ decode_rrrw()

static void decode_rrrw ( )
static

Definition at line 780 of file tricore-dis.c.

781 {
782  int i;
783 
784  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
785  switch (dec_insn.code->fields[i]) {
786  case FMT_RRRW_D:
787  dec_insn.regs[i] = (dec_insn.opcode & 0xf0000000) >> 28;
788  break;
789 
790  case FMT_RRRW_S3:
791  dec_insn.regs[i] = (dec_insn.opcode & 0x0f000000) >> 24;
792  break;
793 
794  case FMT_RRRW_W:
795  dec_insn.cexp[i] = (dec_insn.opcode & 0x001f0000) >> 16;
796  break;
797 
798  case FMT_RRRW_S2:
799  dec_insn.regs[i] = (dec_insn.opcode & 0x0000f000) >> 12;
800  break;
801 
802  case FMT_RRRW_S1:
803  dec_insn.regs[i] = (dec_insn.opcode & 0x00000f00) >> 8;
804  break;
805  }
806  }
807 }
#define FMT_RRRW_S1
Definition: tricore.h:375
#define FMT_RRRW_S3
Definition: tricore.h:372
#define FMT_RRRW_S2
Definition: tricore.h:374
#define FMT_RRRW_D
Definition: tricore.h:371
#define FMT_RRRW_W
Definition: tricore.h:373

References decoded_insn::cexp, decoded_insn::code, dec_insn, FMT_RRRW_D, FMT_RRRW_S1, FMT_RRRW_S2, FMT_RRRW_S3, FMT_RRRW_W, i, decoded_insn::opcode, and decoded_insn::regs.

◆ decode_sb()

static void decode_sb ( )
static

Definition at line 824 of file tricore-dis.c.

825 {
826  int i;
827 
828  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
829  switch (dec_insn.code->fields[i]) {
830  case FMT_SB_DISP8:
831  dec_insn.cexp[i] = (dec_insn.opcode & 0xff00) >> 8;
832  break;
833  }
834  }
835 }
#define FMT_SB_DISP8
Definition: tricore.h:379

References decoded_insn::cexp, decoded_insn::code, dec_insn, FMT_SB_DISP8, i, and decoded_insn::opcode.

◆ decode_sbc()

static void decode_sbc ( )
static

Definition at line 838 of file tricore-dis.c.

839 {
840  int i;
841 
842  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
843  switch (dec_insn.code->fields[i]) {
844  case FMT_SBC_CONST4:
845  dec_insn.cexp[i] = (dec_insn.opcode & 0xf000) >> 12;
846  break;
847 
848  case FMT_SBC_DISP4:
849  dec_insn.cexp[i] = (dec_insn.opcode & 0x0f00) >> 8;
850  if (dec_insn.code->args[i] == 'x') {
851  dec_insn.cexp[i] += 0x10;
852  }
853  break;
854  }
855  }
856 }
#define FMT_SBC_DISP4
Definition: tricore.h:382
#define FMT_SBC_CONST4
Definition: tricore.h:381

References decoded_insn::cexp, decoded_insn::code, dec_insn, FMT_SBC_CONST4, FMT_SBC_DISP4, i, and decoded_insn::opcode.

◆ decode_sbr()

static void decode_sbr ( )
static

Definition at line 859 of file tricore-dis.c.

860 {
861  int i;
862 
863  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
864  switch (dec_insn.code->fields[i]) {
865  case FMT_SBR_S2:
866  dec_insn.regs[i] = (dec_insn.opcode & 0xf000) >> 12;
867  break;
868 
869  case FMT_SBR_DISP4:
870  dec_insn.cexp[i] = (dec_insn.opcode & 0x0f00) >> 8;
871  if (dec_insn.code->args[i] == 'x') {
872  dec_insn.cexp[i] += 0x10;
873  }
874  break;
875  }
876  }
877 }
#define FMT_SBR_S2
Definition: tricore.h:384
#define FMT_SBR_DISP4
Definition: tricore.h:385

References decoded_insn::cexp, decoded_insn::code, dec_insn, FMT_SBR_DISP4, FMT_SBR_S2, i, decoded_insn::opcode, and decoded_insn::regs.

◆ decode_sbrn()

static void decode_sbrn ( )
static

Definition at line 880 of file tricore-dis.c.

881 {
882  int i;
883 
884  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
885  switch (dec_insn.code->fields[i]) {
886  case FMT_SBRN_N:
887  if (dec_insn.code->args[i] == '5') {
888  dec_insn.cexp[i] = (dec_insn.opcode & 0xf000) >> 12;
889  dec_insn.cexp[i] |= (dec_insn.opcode & 0x0080) >> 3;
890  } else {
891  dec_insn.cexp[i] = (dec_insn.opcode & 0xf000) >> 12;
892  }
893  break;
894 
895  case FMT_SBRN_DISP4:
896  dec_insn.cexp[i] = (dec_insn.opcode & 0x0f00) >> 8;
897  break;
898  }
899  }
900 }
#define FMT_SBRN_DISP4
Definition: tricore.h:388
#define FMT_SBRN_N
Definition: tricore.h:387

References decoded_insn::cexp, decoded_insn::code, dec_insn, FMT_SBRN_DISP4, FMT_SBRN_N, i, and decoded_insn::opcode.

◆ decode_sc()

static void decode_sc ( )
static

Definition at line 903 of file tricore-dis.c.

904 {
905  int i;
906 
907  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
908  switch (dec_insn.code->fields[i]) {
909  case FMT_SC_CONST8:
910  dec_insn.cexp[i] = (dec_insn.opcode & 0xff00) >> 8;
911  break;
912  }
913  }
914 }
#define FMT_SC_CONST8
Definition: tricore.h:390

References decoded_insn::cexp, decoded_insn::code, dec_insn, FMT_SC_CONST8, i, and decoded_insn::opcode.

◆ decode_slr()

static void decode_slr ( )
static

Definition at line 917 of file tricore-dis.c.

918 {
919  int i;
920 
921  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
922  switch (dec_insn.code->fields[i]) {
923  case FMT_SLR_S2:
924  dec_insn.regs[i] = (dec_insn.opcode & 0xf000) >> 12;
925  break;
926 
927  case FMT_SLR_D:
928  dec_insn.regs[i] = (dec_insn.opcode & 0x0f00) >> 8;
929  break;
930  }
931  }
932 }
#define FMT_SLR_S2
Definition: tricore.h:392
#define FMT_SLR_D
Definition: tricore.h:393

References decoded_insn::code, dec_insn, FMT_SLR_D, FMT_SLR_S2, i, decoded_insn::opcode, and decoded_insn::regs.

◆ decode_slro()

static void decode_slro ( )
static

Definition at line 935 of file tricore-dis.c.

936 {
937  int i;
938 
939  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
940  switch (dec_insn.code->fields[i]) {
941  case FMT_SLRO_OFF4:
942  dec_insn.cexp[i] = (dec_insn.opcode & 0xf000) >> 12;
943  break;
944 
945  case FMT_SLRO_D:
946  dec_insn.regs[i] = (dec_insn.opcode & 0x0f00) >> 8;
947  break;
948  }
949  }
950 }
#define FMT_SLRO_D
Definition: tricore.h:396
#define FMT_SLRO_OFF4
Definition: tricore.h:395

References decoded_insn::cexp, decoded_insn::code, dec_insn, FMT_SLRO_D, FMT_SLRO_OFF4, i, decoded_insn::opcode, and decoded_insn::regs.

◆ decode_sr()

static void decode_sr ( )
static

Definition at line 953 of file tricore-dis.c.

954 {
955  int i;
956 
957  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
958  switch (dec_insn.code->fields[i]) {
959  case FMT_SR_S1_D:
960  dec_insn.regs[i] = (dec_insn.opcode & 0x0f00) >> 8;
961  break;
962  }
963  }
964 }
#define FMT_SR_S1_D
Definition: tricore.h:398

References decoded_insn::code, dec_insn, FMT_SR_S1_D, i, decoded_insn::opcode, and decoded_insn::regs.

◆ decode_src()

static void decode_src ( )
static

Definition at line 967 of file tricore-dis.c.

968 {
969  int i;
970 
971  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
972  switch (dec_insn.code->fields[i]) {
973  case FMT_SRC_CONST4:
974  dec_insn.cexp[i] = (dec_insn.opcode & 0xf000) >> 12;
975  break;
976 
977  case FMT_SRC_S1_D:
978  dec_insn.regs[i] = (dec_insn.opcode & 0x0f00) >> 8;
979  break;
980  }
981  }
982 }
#define FMT_SRC_S1_D
Definition: tricore.h:401
#define FMT_SRC_CONST4
Definition: tricore.h:400

References decoded_insn::cexp, decoded_insn::code, dec_insn, FMT_SRC_CONST4, FMT_SRC_S1_D, i, decoded_insn::opcode, and decoded_insn::regs.

◆ decode_sro()

static void decode_sro ( )
static

Definition at line 985 of file tricore-dis.c.

986 {
987  int i;
988 
989  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
990  switch (dec_insn.code->fields[i]) {
991  case FMT_SRO_S2:
992  dec_insn.regs[i] = (dec_insn.opcode & 0xf000) >> 12;
993  break;
994 
995  case FMT_SRO_OFF4:
996  dec_insn.cexp[i] = (dec_insn.opcode & 0x0f00) >> 8;
997  break;
998  }
999  }
1000 }
#define FMT_SRO_S2
Definition: tricore.h:403
#define FMT_SRO_OFF4
Definition: tricore.h:404

References decoded_insn::cexp, decoded_insn::code, dec_insn, FMT_SRO_OFF4, FMT_SRO_S2, i, decoded_insn::opcode, and decoded_insn::regs.

◆ decode_srr()

static void decode_srr ( )
static

Definition at line 1003 of file tricore-dis.c.

1004 {
1005  int i;
1006 
1007  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
1008  switch (dec_insn.code->fields[i]) {
1009  case FMT_SRR_S2:
1010  dec_insn.regs[i] = (dec_insn.opcode & 0xf000) >> 12;
1011  break;
1012 
1013  case FMT_SRR_S1_D:
1014  dec_insn.regs[i] = (dec_insn.opcode & 0x0f00) >> 8;
1015  break;
1016  }
1017  }
1018 }
#define FMT_SRR_S2
Definition: tricore.h:406
#define FMT_SRR_S1_D
Definition: tricore.h:407

References decoded_insn::code, dec_insn, FMT_SRR_S1_D, FMT_SRR_S2, i, decoded_insn::opcode, and decoded_insn::regs.

◆ decode_srrs()

static void decode_srrs ( )
static

Definition at line 1021 of file tricore-dis.c.

1022 {
1023  int i;
1024 
1025  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
1026  switch (dec_insn.code->fields[i]) {
1027  case FMT_SRRS_S2:
1028  dec_insn.regs[i] = (dec_insn.opcode & 0xf000) >> 12;
1029  break;
1030 
1031  case FMT_SRRS_S1_D:
1032  dec_insn.regs[i] = (dec_insn.opcode & 0x0f00) >> 8;
1033  break;
1034 
1035  case FMT_SRRS_N:
1036  dec_insn.cexp[i] = (dec_insn.opcode & 0x00c0) >> 6;
1037  break;
1038  }
1039  }
1040 }
#define FMT_SRRS_S2
Definition: tricore.h:409
#define FMT_SRRS_S1_D
Definition: tricore.h:410
#define FMT_SRRS_N
Definition: tricore.h:411

References decoded_insn::cexp, decoded_insn::code, dec_insn, FMT_SRRS_N, FMT_SRRS_S1_D, FMT_SRRS_S2, i, decoded_insn::opcode, and decoded_insn::regs.

◆ decode_ssr()

static void decode_ssr ( )
static

Definition at line 1043 of file tricore-dis.c.

1044 {
1045  int i;
1046 
1047  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
1048  switch (dec_insn.code->fields[i]) {
1049  case FMT_SSR_S2:
1050  dec_insn.regs[i] = (dec_insn.opcode & 0xf000) >> 12;
1051  break;
1052 
1053  case FMT_SSR_S1:
1054  dec_insn.regs[i] = (dec_insn.opcode & 0x0f00) >> 8;
1055  break;
1056  }
1057  }
1058 }
#define FMT_SSR_S2
Definition: tricore.h:413
#define FMT_SSR_S1
Definition: tricore.h:414

References decoded_insn::code, dec_insn, FMT_SSR_S1, FMT_SSR_S2, i, decoded_insn::opcode, and decoded_insn::regs.

◆ decode_ssro()

static void decode_ssro ( )
static

Definition at line 1061 of file tricore-dis.c.

1062 {
1063  int i;
1064 
1065  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
1066  switch (dec_insn.code->fields[i]) {
1067  case FMT_SSRO_OFF4:
1068  dec_insn.cexp[i] = (dec_insn.opcode & 0xf000) >> 12;
1069  break;
1070 
1071  case FMT_SSRO_S1:
1072  dec_insn.regs[i] = (dec_insn.opcode & 0x0f00) >> 8;
1073  break;
1074  }
1075  }
1076 }
#define FMT_SSRO_S1
Definition: tricore.h:417
#define FMT_SSRO_OFF4
Definition: tricore.h:416

References decoded_insn::cexp, decoded_insn::code, dec_insn, FMT_SSRO_OFF4, FMT_SSRO_S1, i, decoded_insn::opcode, and decoded_insn::regs.

◆ decode_sys()

static void decode_sys ( )
static

Definition at line 810 of file tricore-dis.c.

811 {
812  int i;
813 
814  for (i = 0; i < dec_insn.code->nr_operands; ++i) {
815  switch (dec_insn.code->fields[i]) {
816  case FMT_SYS_S1_D:
817  dec_insn.regs[i] = (dec_insn.opcode & 0x00000f00) >> 8;
818  break;
819  }
820  }
821 }
#define FMT_SYS_S1_D
Definition: tricore.h:377

References decoded_insn::code, dec_insn, FMT_SYS_S1_D, i, decoded_insn::opcode, and decoded_insn::regs.

◆ decode_tricore_insn()

static int decode_tricore_insn ( bfd_vma  memaddr,
unsigned long  insn,
int  len32,
struct disassemble_info info 
)
static

Definition at line 1547 of file tricore-dis.c.

1552 {
1553  int idx = insn & 0x3f;
1554  struct insnlist *pinsn;
1555  unsigned long mask;
1556  tricore_fmt fmt;
1557 
1558  /* Try to find the instruction matching the given opcode. */
1559  for (pinsn = insns[idx]; pinsn != NULL; pinsn = pinsn->next)
1560  {
1561  if ((pinsn->code->len32 != len32) || (insn & pinsn->code->lose)) {
1562  continue;
1563  }
1564 
1565  fmt = pinsn->code->format;
1566  mask = tricore_opmask[fmt];
1567  if ((insn & mask) != pinsn->code->opcode) {
1568  continue;
1569  }
1570 
1571  /* A valid instruction was found. Go print it. */
1572  dec_insn.code = pinsn->code;
1573  dec_insn.opcode = insn;
1574  decode[fmt]();
1575  print_decoded_insn (memaddr, info);
1576  return len32 ? 4 : 2;
1577  }
1578 
1579  /* Oops -- this isn't a valid TriCore insn! Since we know that
1580  MEMADDR is an even address (otherwise it already would have
1581  been handled by print_insn_tricore below) and that TriCore
1582  insns can only start at even addresses, we just print the
1583  lower 16 bits of INSN as a .hword pseudo-opcode and return 2,
1584  no matter what LEN32 says. */
1585  (*info->fprintf_func) (info->stream, ".hword 0x%04lx", (insn & 0xffff));
1586 
1587  return 2;
1588 }
#define mask()
int(* decode)(const ut8 *, ebc_command_t *cmd)
Definition: ebc_disas.c:88
struct insnlist * next
Definition: tricore-dis.c:63
opcode_t * code
Definition: tricore-dis.c:62
static void print_decoded_insn(bfd_vma memaddr, struct disassemble_info *info)
Definition: tricore-dis.c:1158
static struct insnlist * insns[64]
Definition: tricore-dis.c:69
enum _tricore_fmt tricore_fmt
unsigned long tricore_opmask[]
Definition: tricore.h:177

References insnlist::code, decoded_insn::code, dec_insn, setup::idx, info(), insns, mask, insnlist::next, NULL, decoded_insn::opcode, print_decoded_insn(), and tricore_opmask.

Referenced by print_insn_tricore().

◆ extract_off18()

static unsigned long extract_off18 ( )
static

Definition at line 191 of file tricore-dis.c.

192 {
193  unsigned long o1, o2, o3, o4;
194  unsigned long val = dec_insn.opcode;
195 
196  o1 = (val & 0x003f0000) >> 16;
197  o2 = (val & 0xf0000000) >> 22;
198  o3 = (val & 0x03c00000) >> 12;
199  o4 = (val & 0x0000f000) << 2;
200  return o1 | o2 | o3 | o4;
201 }

References dec_insn, o1, o2, o4, decoded_insn::opcode, and val.

Referenced by decode_abs(), and decode_absb().

◆ find_core_reg()

static const char* find_core_reg ( unsigned long  addr)
static

Definition at line 1140 of file tricore-dis.c.

1142 {
1143  struct sfrlist *psfr;
1144  int idx = addr & 0xff;
1145 
1146  for (psfr = sfrs[idx]; psfr != NULL; psfr = psfr->next) {
1147  if ((psfr->sfr->addr == addr) && MATCHES_ISA (psfr->sfr->isa)) {
1148  return psfr->sfr->name;
1149  }
1150  }
1151 
1152  return (char *) 0;
1153 }
sfr_t * sfr
Definition: tricore-dis.c:87
struct sfrlist * next
Definition: tricore-dis.c:88
const tricore_isa isa
Definition: tricore.h:203
const char * name
Definition: tricore.h:201
const unsigned long addr
Definition: tricore.h:202
#define MATCHES_ISA(isa)
Definition: tricore-dis.c:48
static struct sfrlist * sfrs[256]
Definition: tricore-dis.c:91
static int addr
Definition: z80asm.c:58

References tricore_core_register::addr, addr, setup::idx, tricore_core_register::isa, MATCHES_ISA, tricore_core_register::name, sfrlist::next, NULL, sfrlist::sfr, and sfrs.

Referenced by print_decoded_insn().

◆ init_hash_tables()

static void init_hash_tables ( )
static

Definition at line 1081 of file tricore-dis.c.

1082 {
1083  opcode_t *pop;
1084  pcp_opcode_t *ppop;
1085  sfr_t *psfr;
1086  int i, idx;
1087 
1088  insnlink = (struct insnlist *) xmalloc (NUMOPCS * sizeof (struct insnlist));
1089  pcplink = (struct pcplist *) xmalloc (NUMPCPOPCS * sizeof (struct pcplist));
1090  sfrlink = (struct sfrlist *) xmalloc (NUMSFRS * sizeof (struct sfrlist));
1091  memset ((char *) insns, 0, sizeof (insns));
1092  memset ((char *) insnlink, 0, NUMOPCS * sizeof (struct insnlist));
1093  memset ((char *) pcpinsns, 0, sizeof (pcpinsns));
1094  memset ((char *) pcplink, 0, NUMPCPOPCS * sizeof (struct pcplist));
1095  memset ((char *) sfrs, 0, sizeof (sfrs));
1096  memset ((char *) sfrlink, 0, NUMSFRS * sizeof (struct sfrlist));
1097 
1098  for (i = 0, pop = tricore_opcodes; i < NUMOPCS; ++i, ++pop)
1099  {
1100  if (!MATCHES_ISA (pop->isa)) {
1101  continue;
1102  }
1103 
1104  idx = pop->opcode & 0x3f;
1105  if (insns[idx]) {
1106  insnlink[i].next = insns[idx];
1107  }
1108  insns[idx] = &insnlink[i];
1109  insnlink[i].code = pop;
1110  }
1111 
1112  for (i = 0, ppop = pcp_opcodes; i < NUMPCPOPCS; ++i, ++ppop)
1113  {
1114  idx = (ppop->opcode >> 11) & 0x1f;
1115  if (pcpinsns[idx]) {
1116  pcplink[i].next = pcpinsns[idx];
1117  }
1118  pcpinsns[idx] = &pcplink[i];
1119  pcplink[i].code = ppop;
1120  }
1121 
1122  for (i = 0, psfr = tricore_sfrs; i < NUMSFRS; ++i, ++psfr)
1123  {
1124  if (!MATCHES_ISA (psfr->isa)) {
1125  continue;
1126  }
1127 
1128  idx = psfr->addr & 0xff;
1129  if (sfrs[idx]) {
1130  sfrlink[i].next = sfrs[idx];
1131  }
1132  sfrs[idx] = &sfrlink[i];
1133  sfrlink[i].sfr = psfr;
1134  }
1135 }
#define xmalloc
Definition: disas-asm.h:43
return memset(p, 0, total)
static struct sfrlist * sfrlink
Definition: tricore-dis.c:92
static struct insnlist * insnlink
Definition: tricore-dis.c:70
#define NUMPCPOPCS
Definition: tricore-dis.c:46
#define NUMOPCS
Definition: tricore-dis.c:44
#define NUMSFRS
Definition: tricore-dis.c:45
static struct pcplist * pcplink
Definition: tricore-dis.c:81
const struct tricore_core_register tricore_sfrs[]
Definition: tricore-opc.c:29
struct tricore_opcode tricore_opcodes[]
Definition: tricore-opc.c:308
struct pcp_opcode pcp_opcodes[]
Definition: tricore-opc.c:2386

References tricore_core_register::addr, insnlist::code, pcplist::code, i, setup::idx, insnlink, insns, tricore_core_register::isa, MATCHES_ISA, memset(), insnlist::next, pcplist::next, sfrlist::next, NUMOPCS, NUMPCPOPCS, NUMSFRS, pcp_opcode::opcode, pcp_opcodes, pcpinsns, pcplink, sfrlist::sfr, sfrlink, sfrs, tricore_opcodes, tricore_sfrs, and xmalloc.

Referenced by print_insn_tricore().

◆ PARAMS() [1/5]

static int decode_pcp_insn PARAMS ( (bfd_vma, bfd_byte[4], struct disassemble_info *)  )
static

◆ PARAMS() [2/5]

static void print_decoded_insn PARAMS ( (bfd_vma, struct disassemble_info *)  )
static

◆ PARAMS() [3/5]

static int decode_tricore_insn PARAMS ( (bfd_vma, unsigned long, int, struct disassemble_info *)  )
static

◆ PARAMS() [4/5]

static const char* find_core_reg PARAMS ( (unsigned long )
static

◆ PARAMS() [5/5]

static void init_hash_tables PARAMS ( (void)  )
static
Initial value:
=
{
}
static void decode_rrrw()
Definition: tricore-dis.c:780
static void decode_rr2()
Definition: tricore-dis.c:616
static void decode_sbr()
Definition: tricore-dis.c:859
static void decode_brc()
Definition: tricore-dis.c:342
static void decode_sbc()
Definition: tricore-dis.c:838
static void decode_rr1()
Definition: tricore-dis.c:590
static void decode_rc()
Definition: tricore-dis.c:409
static void decode_rrrr()
Definition: tricore-dis.c:754
static void decode_rcr()
Definition: tricore-dis.c:460
static void decode_slro()
Definition: tricore-dis.c:935
static void decode_src()
Definition: tricore-dis.c:967
static void decode_sbrn()
Definition: tricore-dis.c:880
static void decode_b()
Definition: tricore-dis.c:244
static void decode_brn()
Definition: tricore-dis.c:364
static void decode_rcrw()
Definition: tricore-dis.c:512
static void decode_rcrr()
Definition: tricore-dis.c:486
static void decode_rrr()
Definition: tricore-dis.c:668
static void decode_rr()
Definition: tricore-dis.c:564
static void decode_sb()
Definition: tricore-dis.c:824
static void decode_sro()
Definition: tricore-dis.c:985
static void decode_rrr1()
Definition: tricore-dis.c:698
static void decode_rrr2()
Definition: tricore-dis.c:728
static void decode_ssr()
Definition: tricore-dis.c:1043
static void decode_slr()
Definition: tricore-dis.c:917
static void decode_bit()
Definition: tricore-dis.c:261
static void decode_bo()
Definition: tricore-dis.c:291
static void decode_rlc()
Definition: tricore-dis.c:542
static void decode_absb()
Definition: tricore-dis.c:222
static void decode_abs()
Definition: tricore-dis.c:204
static void decode_brr()
Definition: tricore-dis.c:387
static void decode_ssro()
Definition: tricore-dis.c:1061
static void decode_srrs()
Definition: tricore-dis.c:1021
static void decode_sys()
Definition: tricore-dis.c:810
static void decode_rcpw()
Definition: tricore-dis.c:430
static void decode_srr()
Definition: tricore-dis.c:1003
static void decode_sc()
Definition: tricore-dis.c:903
static void decode_sr()
Definition: tricore-dis.c:953
static void decode_bol()
Definition: tricore-dis.c:316
static void decode_rrpw()
Definition: tricore-dis.c:638

◆ print_decoded_insn()

static void print_decoded_insn ( bfd_vma  memaddr,
struct disassemble_info info 
)
static

Definition at line 1158 of file tricore-dis.c.

1161 {
1162  opcode_t *insn = dec_insn.code;
1163  int i, needs_creg = 0, need_comma;
1164  const char *creg;
1165  bfd_vma abs;
1166  static bfd_vma next_addr = 0;
1167  static bool expect_lea = false;
1168 #define NO_AREG 16
1169  static int load_areg[NO_AREG] = {false,false,false,false,false,false,false,false,false,false,false,false,false,false,false,false};
1170  static unsigned long load_hi_addr[NO_AREG] = {0};
1171  static unsigned long load_addr = 0;
1172  static bool print_symbolic_address = false;
1173 #define DPRINT (*info->fprintf_func)
1174 #define DFILE info->stream
1175 
1176  /* Special cases: "nor %dn" / "nor %dn,%dn,0" -> "not %dn" */
1177  if (((*insn->name == 'n') && !strcmp (insn->name, "nor"))
1178  && ((insn->nr_operands == 1)
1179  || ((insn->nr_operands == 3)
1180  && (insn->args[2] == 'n')
1181  && (dec_insn.regs[0] == dec_insn.regs[1])
1182  && (dec_insn.cexp[2] == 0))))
1183  {
1184  DPRINT (DFILE, "not "REGPREFIX"d%d", dec_insn.regs[0]);
1185  return;
1186  } else {
1187  DPRINT (DFILE, "%s ", insn->name);
1188  }
1189 
1190  /* Being a child of the RISC generation, a TriCore-based CPU generally
1191  must load a 32-bit wide address in two steps, usually by executing
1192  an instruction sequence like "movh.a %an,hi:sym; lea %am,[%an]lo:sym"
1193  (an optimizing compiler performing instruction scheduling, such as
1194  GCC, may insert other instructions between "movh.a" and "lea", but
1195  that doesn't matter at all, because it doesn't change the execution
1196  order of the two instructions, and this function can only disassemble
1197  a single instruction at a time, anyway). We would like to see which
1198  address is being loaded (or, more precisely, which symbol lives at
1199  the address being loaded), so we keep track of "movh.a" and "lea"
1200  instructions, and print the symbolic address after a "lea" insn
1201  if we can be reasonably sure that it is part of the load sequence
1202  described above. Note that "lea" is used here as a generic insn;
1203  it actually may also be any load or store instruction. */
1204  if (memaddr != next_addr) {
1205  expect_lea = print_symbolic_address = false;
1206  }
1207  next_addr = memaddr + (insn->len32 ? 4 : 2);
1208 
1209  if (!strcmp (insn->name, "movh.a"))
1210  {
1211  load_areg[dec_insn.regs[0]] = true;
1212  load_hi_addr[dec_insn.regs[0]] = dec_insn.cexp[1] << 16;
1213  expect_lea = true;
1214  print_symbolic_address = false;
1215  }
1216  else if (expect_lea
1217  && (!strcmp (insn->name, "lea")
1218  || !strncmp (insn->name, "ld.", 3)
1219  || !strncmp (insn->name, "st.", 3)
1220  || !strncmp (insn->name, "swap", 4)
1221  || !strcmp (insn->name, "ldmst")))
1222  {
1223  if (insn->nr_operands == 3)
1224  {
1225  if ((!strcmp (insn->name, "lea")
1226  || !strncmp (insn->name, "ld.", 3)
1227  || !strcmp (insn->name, "ldmst"))
1228  ) {
1229  if ((true == load_areg[dec_insn.regs[1]]))
1230  {
1231  load_addr = load_hi_addr[dec_insn.regs[1]] + (short) dec_insn.cexp[2];
1232  print_symbolic_address = true;
1233  }
1234  }
1235  else if (true == load_areg[dec_insn.regs[0]])
1236  {
1237  load_addr = load_hi_addr[dec_insn.regs[0]] + (short) dec_insn.cexp[1];
1238  print_symbolic_address = true;
1239  }
1240  }
1241  } else {
1242  print_symbolic_address = false;
1243  }
1244 
1245  if (!strncmp (insn->name, "ld.a", 4)) {
1246  load_areg[dec_insn.regs[0]] = false;
1247  } else if (!strncmp (insn->name, "add.a", 5) || !strncmp (insn->name, "sub.a", 5) || !strcmp (insn->name, "mov.a") || !strncmp (insn->name, "addsc.a", 7)) {
1248  load_areg[dec_insn.regs[0]] = false;
1249  } else if (!strcmp (insn->name, "mov.aa")) {
1250  load_areg[dec_insn.regs[0]] = load_areg[dec_insn.regs[1]];
1251  } else if (!strncmp (insn->name, "call", 4)) {
1252  int i = 0;
1253  for (i = 2; i < 8; i++) {
1254  load_areg[i] = false;
1255  }
1256  }
1257  else
1258  if (!strncmp(insn->name,"ret",3)) {
1259  int i = 0;
1260  for (i = 2; i < 8; i++) {
1261  load_areg[i] = false;
1262  }
1263  for (i = 10; i < 16; i++) {
1264  load_areg[i] = false;
1265  }
1266  }
1267 
1268  if (!strcmp (insn->name, "mfcr") || !strcmp (insn->name, "mtcr")) {
1269  needs_creg = 1;
1270  }
1271 
1272  for (i = 0; i < insn->nr_operands; ++i)
1273  {
1274  need_comma = (i < (insn->nr_operands - 1));
1275  switch (insn->args[i])
1276  {
1277  case 'd':
1278  DPRINT (DFILE, ""REGPREFIX"d%d", dec_insn.regs[i]);
1279  break;
1280 
1281  case 'g':
1282  DPRINT (DFILE, ""REGPREFIX"d%dl", dec_insn.regs[i]);
1283  break;
1284 
1285  case 'G':
1286  DPRINT (DFILE, ""REGPREFIX"d%du", dec_insn.regs[i]);
1287  break;
1288 
1289  case '-':
1290  DPRINT (DFILE, ""REGPREFIX"d%dll", dec_insn.regs[i]);
1291  break;
1292 
1293  case '+':
1294  DPRINT (DFILE, ""REGPREFIX"d%duu", dec_insn.regs[i]);
1295  break;
1296 
1297  case 'l':
1298  DPRINT (DFILE, ""REGPREFIX"d%dlu", dec_insn.regs[i]);
1299  break;
1300 
1301  case 'L':
1302  DPRINT (DFILE, ""REGPREFIX"d%dul", dec_insn.regs[i]);
1303  break;
1304 
1305  case 'D':
1306  DPRINT (DFILE, ""REGPREFIX"e%d", dec_insn.regs[i]);
1307  break;
1308 
1309  case 'i':
1310  DPRINT (DFILE, ""REGPREFIX"d15");
1311  break;
1312 
1313  case 'a':
1314  case 'A':
1315  if (dec_insn.regs[i] == 10) {
1316  DPRINT (DFILE, ""REGPREFIX"sp");
1317  } else {
1318  DPRINT (DFILE, "" REGPREFIX "a%d", dec_insn.regs[i]);
1319  }
1320  break;
1321 
1322  case 'I':
1323  DPRINT (DFILE, ""REGPREFIX"a15");
1324  break;
1325 
1326  case 'P':
1327  DPRINT (DFILE, ""REGPREFIX"sp");
1328  break;
1329 
1330  case 'k':
1331  case '6':
1332  dec_insn.cexp[i] <<= 1;
1333  /* Fall through. */
1334  case 'v':
1335  dec_insn.cexp[i] <<= 1;
1336  /* Fall through. */
1337  case '1':
1338  case '2':
1339  case '3':
1340  case 'f':
1341  case '5':
1342  case '8':
1343  case 'n':
1344  case 'M':
1345  DPRINT (DFILE, "%lu", dec_insn.cexp[i]);
1346  break;
1347 
1348  case '4':
1349  if (dec_insn.cexp[i] & 0x8) {
1350  dec_insn.cexp[i] |= ~0xf;
1351  }
1352  DPRINT (DFILE, "%ld", dec_insn.cexp[i]);
1353  break;
1354 
1355  case 'F':
1356  if (dec_insn.cexp[i] & 0x10) {
1357  dec_insn.cexp[i] |= ~0x1f;
1358  }
1359  DPRINT (DFILE, "%ld", dec_insn.cexp[i]);
1360  break;
1361 
1362  case '9':
1363  if (dec_insn.cexp[i] & 0x100) {
1364  dec_insn.cexp[i] |= ~0x1ff;
1365  }
1366  DPRINT (DFILE, "%ld", dec_insn.cexp[i]);
1367  break;
1368 
1369  case '0':
1370  if (dec_insn.cexp[i] & 0x200) {
1371  dec_insn.cexp[i] |= ~0x3ff;
1372  }
1373  DPRINT (DFILE, "%ld", dec_insn.cexp[i]);
1374  if (print_symbolic_address) {
1375  DPRINT (DFILE, " <");
1376  (*info->print_address_func) (load_addr, info);
1377  DPRINT (DFILE, ">");
1378  }
1379  break;
1380 
1381  case 'w':
1382  if (dec_insn.cexp[i] & 0x8000) {
1383  dec_insn.cexp[i] |= ~0xffff;
1384  }
1385  DPRINT (DFILE, "%ld", dec_insn.cexp[i]);
1386  if (print_symbolic_address) {
1387  DPRINT (DFILE, " <");
1388  (*info->print_address_func) (load_addr, info);
1389  DPRINT (DFILE, ">");
1390  }
1391  break;
1392 
1393  case 't':
1394  abs = (dec_insn.cexp[i] & 0x00003fff);
1395  abs |= (dec_insn.cexp[i] & 0x0003c000) << 14;
1396  (*info->print_address_func) (abs, info);
1397  break;
1398 
1399  case 'T':
1400  abs = (dec_insn.cexp[i] & 0x000fffff) << 1;
1401  abs |= (dec_insn.cexp[i] & 0x00f00000) << 8;
1402  (*info->print_address_func) (abs, info);
1403  break;
1404 
1405  case 'o':
1406  if (dec_insn.cexp[i] & 0x4000) {
1407  dec_insn.cexp[i] |= ~0x7fff;
1408  }
1409  abs = (dec_insn.cexp[i] << 1) + memaddr;
1410  (*info->print_address_func) (abs, info);
1411  break;
1412 
1413  case 'O':
1414  if (dec_insn.cexp[i] & 0x800000) {
1415  dec_insn.cexp[i] |= ~0xffffff;
1416  }
1417  abs = (dec_insn.cexp[i] << 1) + memaddr;
1418  (*info->print_address_func) (abs, info);
1419  break;
1420 
1421  case 'R':
1422  if (dec_insn.cexp[i] & 0x80) {
1423  dec_insn.cexp[i] |= ~0xff;
1424  }
1425  abs = (dec_insn.cexp[i] << 1) + memaddr;
1426  (*info->print_address_func) (abs, info);
1427  break;
1428 
1429  case 'r':
1430  dec_insn.cexp[i] |= ~0xf;
1431  /* Fall through. */
1432  case 'm':
1433  case 'x':
1434  abs = (dec_insn.cexp[i] << 1) + memaddr;
1435  (*info->print_address_func) (abs, info);
1436  break;
1437 
1438  case 'c':
1439  needs_creg = 1;
1440  /* Fall through. */
1441  case 'W':
1442  if (needs_creg)
1443  {
1445  if (creg) {
1446 #ifdef RESOLVE_SFR_NAMES
1447  DPRINT (DFILE, "%s", creg);
1448 #else
1449  DPRINT (DFILE, "#0x%04lx", dec_insn.cexp[i]);
1450 #endif
1451  } else {
1452  DPRINT (DFILE, "$0x%04lx (unknown SFR)", dec_insn.cexp[i]);
1453  }
1454  } else {
1455  DPRINT (DFILE, "%ld", dec_insn.cexp[i]);
1456  }
1457  break;
1458 
1459  case '&':
1460  dec_insn.regs[i] = 10;
1461  /* Fall through. */
1462  case '@':
1463  if (dec_insn.regs[i] == 10) {
1464  DPRINT (DFILE, "[" REGPREFIX "sp]");
1465  } else {
1466  DPRINT (DFILE, "[" REGPREFIX "a%d]", dec_insn.regs[i]);
1467  }
1468  if (need_comma) {
1469  if ((insn->args[i + 1] == 'a') || (insn->args[i + 1] == 'd')) {
1470  need_comma = 1;
1471  } else {
1472  need_comma = 0;
1473  }
1474  }
1475  break;
1476 
1477  case '<':
1478  if (dec_insn.regs[i] == 10) {
1479  DPRINT (DFILE, "[+" REGPREFIX "sp]");
1480  } else {
1481  DPRINT (DFILE, "[+" REGPREFIX "a%d]", dec_insn.regs[i]);
1482  }
1483  need_comma = 0;
1484  break;
1485 
1486  case '>':
1487  if (dec_insn.regs[i] == 10) {
1488  DPRINT (DFILE, "[" REGPREFIX "sp+]");
1489  } else {
1490  DPRINT (DFILE, "[" REGPREFIX "a%d+]", dec_insn.regs[i]);
1491  }
1492  if (need_comma) {
1493  if ((insn->args[i + 1] == 'a') || (insn->args[i + 1] == 'd')) {
1494  need_comma = 1;
1495  } else {
1496  need_comma = 0;
1497  }
1498  }
1499  break;
1500 
1501  case '*':
1502  if (dec_insn.regs[i] == 10) {
1503  DPRINT (DFILE, "[" REGPREFIX "sp+c]");
1504  } else {
1505  DPRINT (DFILE, "[" REGPREFIX "a%d+c]", dec_insn.regs[i]);
1506  }
1507  need_comma = 0;
1508  break;
1509 
1510  case '#':
1511  if (dec_insn.regs[i] == 10) {
1512  DPRINT (DFILE, "[" REGPREFIX "sp+r]");
1513  } else {
1514  DPRINT (DFILE, "[" REGPREFIX "a%d+r]", dec_insn.regs[i]);
1515  }
1516  break;
1517 
1518  case '?':
1519  if (dec_insn.regs[i] == 10) {
1520  DPRINT (DFILE, "[" REGPREFIX "sp+i]");
1521  } else {
1522  DPRINT (DFILE, "[" REGPREFIX "a%d+i]", dec_insn.regs[i]);
1523  }
1524  break;
1525 
1526  case 'S':
1527  DPRINT (DFILE, "["REGPREFIX"a15]");
1528  need_comma = 0;
1529  break;
1530  }
1531 
1532  if (need_comma) {
1533  DPRINT (DFILE, ", ");
1534  }
1535  }
1536 
1537 #undef DPRINT
1538 #undef DFILE
1539 }
BFD_HOST_U_64_BIT bfd_vma
Definition: mybfd.h:111
#define creg(n)
char * name
Definition: i8080dis.c:51
static const char * find_core_reg(unsigned long addr)
Definition: tricore-dis.c:1140
#define NO_AREG
#define REGPREFIX
Definition: tricore-dis.c:41

References decoded_insn::cexp, decoded_insn::code, creg, dec_insn, DFILE, DPRINT, find_core_reg(), i, info(), opcode_t::name, NO_AREG, REGPREFIX, and decoded_insn::regs.

Referenced by decode_tricore_insn().

◆ print_insn_tricore()

int print_insn_tricore ( bfd_vma  memaddr,
struct disassemble_info info 
)

Definition at line 1884 of file tricore-dis.c.

1887 {
1888  bfd_byte buffer[4];
1889  int len32 = 0, failure;
1890  unsigned long insn = 0;
1891 
1892  if (!initialized)
1893  {
1894  /* Set the current instruction set architecture. */
1895  switch (info->mach & bfd_mach_rider_mask)
1896  {
1897  case bfd_mach_rider_a:
1899  break;
1900 
1901  case bfd_mach_rider_b: /* Matches also rider_d! */
1903  break;
1904 
1905  case bfd_mach_rider_2:
1907  break;
1908  }
1909 
1910  /* Initialize architecture-dependent variables. */
1911  tricore_init_arch_vars (info->mach);
1912 
1913  /* Initialize the hash tables. */
1914  init_hash_tables ();
1915  initialized = 1;
1916  }
1917 
1918  memset ((char *) buffer, 0, sizeof (buffer));
1919  failure = (*info->read_memory_func) (memaddr, buffer, 1, info);
1920  if (failure)
1921  {
1922  (*info->memory_error_func) (failure, memaddr, info);
1923  return -1;
1924  }
1925 
1926  /* Try to read the 2nd byte. */
1927  failure = (*info->read_memory_func) (memaddr + 1, &buffer[1], 1, info);
1928  if (failure)
1929  {
1930  /* Maybe MEMADDR isn't even and we reached the end of a section. */
1931  (*info->fprintf_func) (info->stream, ".byte 0x%02x", buffer[0]);
1932  return 1;
1933  }
1934 
1935  /* Check if we're disassembling .pcp{text,data} sections. */
1936  if (info->section && (info->section->flags & SEC_ARCH_BIT_0)) {
1937  return decode_pcp_insn (memaddr, buffer, info);
1938  }
1939 
1940  /* Handle TriCore sections. */
1941  if (buffer[0] & 1) {
1942  /* Looks like this is a 32-bit insn; try to read 2 more bytes. */
1943  failure = (*info->read_memory_func) (memaddr + 2, &buffer[2], 2, info);
1944  if (failure) {
1945  insn = bfd_getl16 (buffer);
1946  (*info->fprintf_func) (info->stream, ".hword 0x%04lx", insn);
1947  return 2;
1948  } else {
1949  len32 = 1;
1950  }
1951  }
1952 
1953  if (len32) {
1954  insn = bfd_getl32 (buffer);
1955  } else {
1956  insn = bfd_getl16 (buffer);
1957  }
1958 
1959  return decode_tricore_insn (memaddr, insn, len32, info);
1960 }
void tricore_init_arch_vars(unsigned long mach)
Definition: cpu-tricore.c:187
unsigned char bfd_byte
Definition: mybfd.h:176
static bfd_vma bfd_getl32(const void *p)
Definition: mybfd.h:4990
static int decode_tricore_insn(bfd_vma memaddr, unsigned long insn, int len32, struct disassemble_info *info)
Definition: tricore-dis.c:1547
static void init_hash_tables()
Definition: tricore-dis.c:1081
static int decode_pcp_insn(bfd_vma memaddr, buffer, struct disassemble_info *info)
Definition: tricore-dis.c:1596
static int initialized
Definition: tricore-dis.c:96
#define bfd_mach_rider_2
Definition: tricore.h:41
@ TRICORE_RIDER_A
Definition: tricore.h:30
@ TRICORE_RIDER_B
Definition: tricore.h:31
@ TRICORE_V2
Definition: tricore.h:33
#define SEC_ARCH_BIT_0
Definition: tricore.h:45
#define bfd_mach_rider_a
Definition: tricore.h:38
#define bfd_mach_rider_b
Definition: tricore.h:39

References bfd_getl16(), bfd_getl32(), bfd_mach_rider_2, bfd_mach_rider_a, bfd_mach_rider_b, bfd_mach_rider_mask, current_isa, decode_pcp_insn(), decode_tricore_insn(), info(), init_hash_tables(), initialized, memset(), SEC_ARCH_BIT_0, tricore_init_arch_vars(), TRICORE_RIDER_A, TRICORE_RIDER_B, and TRICORE_V2.

Referenced by disassemble().

Variable Documentation

◆ current_isa

tricore_isa current_isa = TRICORE_RIDER_B
static

Definition at line 100 of file tricore-dis.c.

Referenced by print_insn_tricore().

◆ dec_insn

◆ initialized

int initialized = 0
static

◆ insnlink

struct insnlist* insnlink
static

Definition at line 70 of file tricore-dis.c.

Referenced by init_hash_tables().

◆ insns

struct insnlist* insns[64]
static

Definition at line 69 of file tricore-dis.c.

Referenced by decode_tricore_insn(), init_hash_tables(), insn_find(), and make_id2insn().

◆ pcpinsns

struct pcplist* pcpinsns[32]
static

Definition at line 80 of file tricore-dis.c.

Referenced by decode_pcp_insn(), and init_hash_tables().

◆ pcplink

struct pcplist* pcplink
static

Definition at line 81 of file tricore-dis.c.

Referenced by init_hash_tables().

◆ sfrlink

struct sfrlist* sfrlink
static

Definition at line 92 of file tricore-dis.c.

Referenced by init_hash_tables().

◆ sfrs

struct sfrlist* sfrs[256]
static

Definition at line 91 of file tricore-dis.c.

Referenced by find_core_reg(), and init_hash_tables().