Rizin
unix-like reverse engineering framework and cli tools
windows-arm64.h
Go to the documentation of this file.
1 // SPDX-FileCopyrightText: 2020 GustavoLCR <gugulcr@gmail.com>
2 // SPDX-License-Identifier: LGPL-3.0-only
3 
4 if (dbg->bits == RZ_SYS_BITS_64) {
5  return strdup(
6  "=PC pc\n"
7  "=SP sp\n"
8  "=BP fp\n"
9  "=LR lr\n"
10  "=A0 x0\n"
11  "=A1 x1\n"
12  "=A2 x2\n"
13  "=A3 x3\n"
14  "=ZF zf\n"
15  "=SF nf\n"
16  "=OF vf\n"
17  "=CF cf\n"
18  "=SN x16\n"
19  "flg cpsr .32 4 0 _____tfiae_____________j__qvczn\n"
20  "flg vf .1 4.28 0 overflow\n"
21  "flg cf .1 4.29 0 carry\n"
22  "flg zf .1 4.30 0 zero\n"
23  "flg nf .1 4.31 0 sign\n"
24  "gpr x0 .64 8 0\n"
25  "gpr x1 .64 16 0\n"
26  "gpr x2 .64 24 0\n"
27  "gpr x3 .64 32 0\n"
28  "gpr x4 .64 40 0\n"
29  "gpr x5 .64 48 0\n"
30  "gpr x6 .64 56 0\n"
31  "gpr x7 .64 64 0\n"
32  "gpr x8 .64 72 0\n"
33  "gpr x9 .64 80 0\n"
34  "gpr x10 .64 88 0\n"
35  "gpr x11 .64 96 0\n"
36  "gpr x12 .64 104 0\n"
37  "gpr x13 .64 112 0\n"
38  "gpr x14 .64 120 0\n"
39  "gpr x15 .64 128 0\n"
40  "gpr x16 .64 136 0\n"
41  "gpr x17 .64 144 0\n"
42  "gpr x18 .64 152 0\n"
43  "gpr x19 .64 160 0\n"
44  "gpr x20 .64 168 0\n"
45  "gpr x21 .64 176 0\n"
46  "gpr x22 .64 184 0\n"
47  "gpr x23 .64 192 0\n"
48  "gpr x24 .64 200 0\n"
49  "gpr x25 .64 208 0\n"
50  "gpr x26 .64 216 0\n"
51  "gpr x27 .64 224 0\n"
52  "gpr x28 .64 232 0\n"
53  "gpr w0 .32 8 0\n"
54  "gpr w1 .32 16 0\n"
55  "gpr w2 .32 24 0\n"
56  "gpr w3 .32 32 0\n"
57  "gpr w4 .32 40 0\n"
58  "gpr w5 .32 48 0\n"
59  "gpr w6 .32 56 0\n"
60  "gpr w7 .32 64 0\n"
61  "gpr w8 .32 72 0\n"
62  "gpr w9 .32 80 0\n"
63  "gpr w10 .32 88 0\n"
64  "gpr w11 .32 96 0\n"
65  "gpr w12 .32 104 0\n"
66  "gpr w13 .32 112 0\n"
67  "gpr w14 .32 120 0\n"
68  "gpr w15 .32 128 0\n"
69  "gpr w16 .32 136 0\n"
70  "gpr w17 .32 144 0\n"
71  "gpr w18 .32 152 0\n"
72  "gpr w19 .32 160 0\n"
73  "gpr w20 .32 168 0\n"
74  "gpr w21 .32 176 0\n"
75  "gpr w22 .32 184 0\n"
76  "gpr w23 .32 192 0\n"
77  "gpr w24 .32 200 0\n"
78  "gpr w25 .32 208 0\n"
79  "gpr w26 .32 216 0\n"
80  "gpr w27 .32 224 0\n"
81  "gpr w28 .32 232 0\n"
82  "gpr fp .64 240 0\n"
83  "gpr lr .64 248 0\n"
84  "gpr sp .64 256 0\n"
85  "gpr pc .64 264 0\n"
86  "fpu v0 .128 272 0\n"
87  "fpu v1 .128 288 0\n"
88  "fpu v2 .128 304 0\n"
89  "fpu v3 .128 320 0\n"
90  "fpu v4 .128 336 0\n"
91  "fpu v5 .128 352 0\n"
92  "fpu v6 .128 368 0\n"
93  "fpu v7 .128 384 0\n"
94  "fpu v8 .128 400 0\n"
95  "fpu v9 .128 416 0\n"
96  "fpu v10 .128 432 0\n"
97  "fpu v11 .128 448 0\n"
98  "fpu v12 .128 464 0\n"
99  "fpu v13 .128 480 0\n"
100  "fpu v14 .128 496 0\n"
101  "fpu v15 .128 512 0\n"
102  "fpu v16 .128 528 0\n"
103  "fpu v17 .128 544 0\n"
104  "fpu v18 .128 560 0\n"
105  "fpu v19 .128 576 0\n"
106  "fpu v20 .128 592 0\n"
107  "fpu v21 .128 608 0\n"
108  "fpu v22 .128 624 0\n"
109  "fpu v23 .128 640 0\n"
110  "fpu v24 .128 656 0\n"
111  "fpu v25 .128 672 0\n"
112  "fpu v26 .128 688 0\n"
113  "fpu v27 .128 704 0\n"
114  "fpu v28 .128 720 0\n"
115  "fpu v29 .128 736 0\n"
116  "fpu v30 .128 752 0\n"
117  "fpu v31 .128 768 0\n"
118  "flg fpcr .32 784 0\n"
119  "flg fpsr .32 788 0\n"
120  "flg fvf .1 788.28 0 overflow\n"
121  "flg fcf .1 788.29 0 carry\n"
122  "flg fzf .1 788.30 0 zero\n"
123  "flg fnf .1 788.31 0 sign\n"
124  "drx bcr0 .32 792 0\n"
125  "drx bcr1 .32 796 0\n"
126  "drx bcr2 .32 800 0\n"
127  "drx bcr3 .32 804 0\n"
128  "drx bcr4 .32 808 0\n"
129  "drx bcr5 .32 812 0\n"
130  "drx bcr6 .32 816 0\n"
131  "drx bcr7 .32 820 0\n"
132  "drx bvr0 .64 824 0\n"
133  "drx bvr1 .64 832 0\n"
134  "drx bvr2 .64 840 0\n"
135  "drx bvr3 .64 848 0\n"
136  "drx bvr4 .64 856 0\n"
137  "drx bvr5 .64 864 0\n"
138  "drx bvr6 .64 872 0\n"
139  "drx bvr7 .64 880 0\n"
140  "drx wcr0 .32 888 0\n"
141  "drx wcr1 .32 892 0\n"
142  "drx wvr0 .64 896 0\n"
143  "drx wvr1 .64 904 0\n");
144 } else {
145  return strdup(
146  "=PC pc\n"
147  "=SP sp\n"
148  "=BP fp\n"
149  "=LR lr\n"
150  "=A0 r0\n"
151  "=A1 r1\n"
152  "=A2 r2\n"
153  "=A3 r3\n"
154  "=ZF zf\n"
155  "=SF nf\n"
156  "=OF vf\n"
157  "=CF cf\n"
158  "flg cpsr .32 4 0 _____tfiae_____________j__qvczn\n"
159  "flg vf .1 4.28 0 overflow\n"
160  "flg cf .1 4.29 0 carry\n"
161  "flg zf .1 4.30 0 zero\n"
162  "flg nf .1 4.31 0 sign\n"
163  "gpr r0 .32 8 0\n"
164  "gpr r1 .32 16 0\n"
165  "gpr r2 .32 24 0\n"
166  "gpr r3 .32 32 0\n"
167  "gpr r4 .32 40 0\n"
168  "gpr r5 .32 48 0\n"
169  "gpr r6 .32 56 0\n"
170  "gpr r7 .32 64 0\n"
171  "gpr r8 .32 72 0\n"
172  "gpr r9 .32 80 0\n"
173  "gpr r10 .32 88 0\n"
174  "gpr fp .32 96 0\n"
175  "gpr ip .32 104 0\n"
176  "gpr sp .32 112 0\n"
177  "gpr lr .32 120 0\n"
178  "gpr pc .64 264 0\n"
179  "fpu v0 .128 272 0\n"
180  "fpu v1 .128 288 0\n"
181  "fpu v2 .128 304 0\n"
182  "fpu v3 .128 320 0\n"
183  "fpu v4 .128 336 0\n"
184  "fpu v5 .128 352 0\n"
185  "fpu v6 .128 368 0\n"
186  "fpu v7 .128 384 0\n"
187  "fpu v8 .128 400 0\n"
188  "fpu v9 .128 416 0\n"
189  "fpu v10 .128 432 0\n"
190  "fpu v11 .128 448 0\n"
191  "fpu v12 .128 464 0\n"
192  "fpu v13 .128 480 0\n"
193  "fpu v14 .128 496 0\n"
194  "fpu v15 .128 512 0\n"
195  "fpu v16 .128 528 0\n"
196  "fpu v17 .128 544 0\n"
197  "fpu v18 .128 560 0\n"
198  "fpu v19 .128 576 0\n"
199  "fpu v20 .128 592 0\n"
200  "fpu v21 .128 608 0\n"
201  "fpu v22 .128 624 0\n"
202  "fpu v23 .128 640 0\n"
203  "fpu v24 .128 656 0\n"
204  "fpu v25 .128 672 0\n"
205  "fpu v26 .128 688 0\n"
206  "fpu v27 .128 704 0\n"
207  "fpu v28 .128 720 0\n"
208  "fpu v29 .128 736 0\n"
209  "fpu v30 .128 752 0\n"
210  "fpu v31 .128 768 0\n"
211  "gpr fpcr .32 784 0\n"
212  "gpr fpsr .32 788 0\n"
213  "drx bcr0 .32 792 0\n"
214  "drx bcr1 .32 796 0\n"
215  "drx bcr2 .32 800 0\n"
216  "drx bcr3 .32 804 0\n"
217  "drx bcr4 .32 808 0\n"
218  "drx bcr5 .32 812 0\n"
219  "drx bcr6 .32 816 0\n"
220  "drx bcr7 .32 820 0\n"
221  "drx bvr0 .64 824 0\n"
222  "drx bvr1 .64 832 0\n"
223  "drx bvr2 .64 840 0\n"
224  "drx bvr3 .64 848 0\n"
225  "drx bvr4 .64 856 0\n"
226  "drx bvr5 .64 864 0\n"
227  "drx bvr6 .64 872 0\n"
228  "drx bvr7 .64 880 0\n"
229  "drx wcr0 .32 888 0\n"
230  "drx wcr1 .32 892 0\n"
231  "drx wvr0 .64 896 0\n"
232  "drx wvr1 .64 904 0\n");
233 }
dbg
RzDebug * dbg
Definition: desil.c:30
strdup
return strdup("=SP r13\n" "=LR r14\n" "=PC r15\n" "=A0 r0\n" "=A1 r1\n" "=A2 r2\n" "=A3 r3\n" "=ZF zf\n" "=SF nf\n" "=OF vf\n" "=CF cf\n" "=SN or0\n" "gpr lr .32 56 0\n" "gpr pc .32 60 0\n" "gpr cpsr .32 64 0 ____tfiae_________________qvczn\n" "gpr or0 .32 68 0\n" "gpr tf .1 64.5 0 thumb\n" "gpr ef .1 64.9 0 endian\n" "gpr jf .1 64.24 0 java\n" "gpr qf .1 64.27 0 sticky_overflow\n" "gpr vf .1 64.28 0 overflow\n" "gpr cf .1 64.29 0 carry\n" "gpr zf .1 64.30 0 zero\n" "gpr nf .1 64.31 0 negative\n" "gpr itc .4 64.10 0 if_then_count\n" "gpr gef .4 64.16 0 great_or_equal\n" "gpr r0 .32 0 0\n" "gpr r1 .32 4 0\n" "gpr r2 .32 8 0\n" "gpr r3 .32 12 0\n" "gpr r4 .32 16 0\n" "gpr r5 .32 20 0\n" "gpr r6 .32 24 0\n" "gpr r7 .32 28 0\n" "gpr r8 .32 32 0\n" "gpr r9 .32 36 0\n" "gpr r10 .32 40 0\n" "gpr r11 .32 44 0\n" "gpr r12 .32 48 0\n" "gpr r13 .32 52 0\n" "gpr r14 .32 56 0\n" "gpr r15 .32 60 0\n" "gpr r16 .32 64 0\n" "gpr r17 .32 68 0\n")
RZ_SYS_BITS_64
@ RZ_SYS_BITS_64
Definition: rz_sys.h:21
rz_debug_t::bits
int bits
Definition: rz_debug.h:243