#include "mybfd.h"
#include <stdint.h>
#include <stdlib.h>

Go to the source code of this file.

Classes
struct	aarch64_opcode

struct	aarch64_name_value_pair

struct	aarch64_sys_reg

struct	aarch64_sys_ins_reg

struct	aarch64_cond

struct	aarch64_opnd_info

struct	aarch64_inst

struct	aarch64_operand_error

Macros
#define	AARCH64_PCREL_OFFSET 0

#define	AARCH64_FEATURE_SHA2 0x200000000ULL /* SHA2 instructions. */

#define	AARCH64_FEATURE_AES 0x800000000ULL /* AES instructions. */

#define	AARCH64_FEATURE_V8_4 0x000000800ULL /* ARMv8.4 processors. */

#define	AARCH64_FEATURE_SM4 0x100000000ULL /* SM3 & SM4 instructions. */

#define	AARCH64_FEATURE_SHA3 0x400000000ULL /* SHA3 instructions. */

#define	AARCH64_FEATURE_V8 0x00000001 /* All processors. */

#define	AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */

#define	AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */

#define	AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */

#define	AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */

#define	AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */

#define	AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */

#define	AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */

#define	AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */

#define	AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */

#define	AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */

#define	AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */

#define	AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */

#define	AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */

#define	AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */

#define	AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */

#define	AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */

#define	AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */

#define	AARCH64_FEATURE_DOTPROD 0x080000000 /* Dot Product instructions. */

#define	AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins. */

#define	AARCH64_ARCH_V8

#define	AARCH64_ARCH_V8_1

#define	AARCH64_ARCH_V8_2

#define	AARCH64_ARCH_V8_3

#define	AARCH64_ARCH_V8_4

#define	AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)

#define	AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */

#define	AARCH64_CPU_HAS_ALL_FEATURES(CPU, FEAT) ((~(CPU) & (FEAT)) == 0)

#define	AARCH64_CPU_HAS_ANY_FEATURES(CPU, FEAT) (((CPU) & (FEAT)) != 0)

#define	AARCH64_CPU_HAS_FEATURE(CPU, FEAT) AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)

#define	AARCH64_MERGE_FEATURE_SETS(TARG, F1, F2)

#define	AARCH64_CLEAR_FEATURE(TARG, F1, F2)

#define	AARCH64_FEATURE(core, coproc) ((core) \| (coproc))

#define	AARCH64_MAX_OPND_NUM 6

#define	AARCH64_MAX_QLF_SEQ_NUM 10

#define	F_ALIAS (1 << 0)

#define	F_HAS_ALIAS (1 << 1)

#define	F_P1 (1 << 2)

#define	F_P2 (2 << 2)

#define	F_P3 (3 << 2)

#define	F_COND (1 << 4)

#define	F_SF (1 << 5)

#define	F_SIZEQ (1 << 6)

#define	F_FPTYPE (1 << 7)

#define	F_SSIZE (1 << 8)

#define	F_T (1 << 9)

#define	F_GPRSIZE_IN_Q (1 << 10)

#define	F_LDS_SIZE (1 << 11)

#define	F_OPD0_OPT (1 << 12)

#define	F_OPD1_OPT (2 << 12)

#define	F_OPD2_OPT (3 << 12)

#define	F_OPD3_OPT (4 << 12)

#define	F_OPD4_OPT (5 << 12)

#define	F_DEFAULT(X) (((X) & 0x1f) << 15)

#define	F_CONV (1 << 20)

#define	F_PSEUDO (1 << 21)

#define	F_MISC (1 << 22)

#define	F_N (1 << 23)

#define	F_OD(X) (((X) & 0x7) << 24)

#define	F_LSE_SZ (1 << 27)

#define	F_STRICT (1ULL << 28)

#define	F_SYS_READ (1ULL << 29)

#define	F_SYS_WRITE (1ULL << 30)

#define	DEBUG_TRACE(M, ...) ;

#define	DEBUG_TRACE_IF(C, M, ...) ;

Typedefs
typedef uint32_t	aarch64_insn

typedef unsigned long long	aarch64_feature_set

typedef unsigned char	aarch64_opnd_qualifier_t

typedef aarch64_opnd_qualifier_t	aarch64_opnd_qualifier_seq_t[AARCH64_MAX_OPND_NUM]

typedef struct aarch64_opcode	aarch64_opcode

typedef struct aarch64_opnd_info	aarch64_opnd_info

typedef struct aarch64_inst	aarch64_inst

typedef struct aarch64_operand_error	aarch64_operand_error

Enumerations
enum	aarch64_operand_class { AARCH64_OPND_CLASS_NIL , AARCH64_OPND_CLASS_INT_REG , AARCH64_OPND_CLASS_MODIFIED_REG , AARCH64_OPND_CLASS_FP_REG , AARCH64_OPND_CLASS_SIMD_REG , AARCH64_OPND_CLASS_SIMD_ELEMENT , AARCH64_OPND_CLASS_SISD_REG , AARCH64_OPND_CLASS_SIMD_REGLIST , AARCH64_OPND_CLASS_SVE_REG , AARCH64_OPND_CLASS_PRED_REG , AARCH64_OPND_CLASS_ADDRESS , AARCH64_OPND_CLASS_IMMEDIATE , AARCH64_OPND_CLASS_SYSTEM , AARCH64_OPND_CLASS_COND }

enum	aarch64_opnd { AARCH64_OPND_NIL , AARCH64_OPND_Rd , AARCH64_OPND_Rn , AARCH64_OPND_Rm , AARCH64_OPND_Rt , AARCH64_OPND_Rt2 , AARCH64_OPND_Rs , AARCH64_OPND_Ra , AARCH64_OPND_Rt_SYS , AARCH64_OPND_Rd_SP , AARCH64_OPND_Rn_SP , AARCH64_OPND_Rm_SP , AARCH64_OPND_PAIRREG , AARCH64_OPND_Rm_EXT , AARCH64_OPND_Rm_SFT , AARCH64_OPND_Fd , AARCH64_OPND_Fn , AARCH64_OPND_Fm , AARCH64_OPND_Fa , AARCH64_OPND_Ft , AARCH64_OPND_Ft2 , AARCH64_OPND_Sd , AARCH64_OPND_Sn , AARCH64_OPND_Sm , AARCH64_OPND_Va , AARCH64_OPND_Vd , AARCH64_OPND_Vn , AARCH64_OPND_Vm , AARCH64_OPND_VdD1 , AARCH64_OPND_VnD1 , AARCH64_OPND_Ed , AARCH64_OPND_En , AARCH64_OPND_Em , AARCH64_OPND_Em16 , AARCH64_OPND_LVn , AARCH64_OPND_LVt , AARCH64_OPND_LVt_AL , AARCH64_OPND_LEt , AARCH64_OPND_CRn , AARCH64_OPND_CRm , AARCH64_OPND_IDX , AARCH64_OPND_MASK , AARCH64_OPND_IMM_VLSL , AARCH64_OPND_IMM_VLSR , AARCH64_OPND_SIMD_IMM , AARCH64_OPND_SIMD_IMM_SFT , AARCH64_OPND_SIMD_FPIMM , AARCH64_OPND_SHLL_IMM , AARCH64_OPND_IMM0 , AARCH64_OPND_FPIMM0 , AARCH64_OPND_FPIMM , AARCH64_OPND_IMMR , AARCH64_OPND_IMMS , AARCH64_OPND_WIDTH , AARCH64_OPND_IMM , AARCH64_OPND_IMM_2 , AARCH64_OPND_UIMM3_OP1 , AARCH64_OPND_UIMM3_OP2 , AARCH64_OPND_UIMM4 , AARCH64_OPND_UIMM7 , AARCH64_OPND_BIT_NUM , AARCH64_OPND_EXCEPTION , AARCH64_OPND_CCMP_IMM , AARCH64_OPND_SIMM5 , AARCH64_OPND_NZCV , AARCH64_OPND_LIMM , AARCH64_OPND_AIMM , AARCH64_OPND_HALF , AARCH64_OPND_FBITS , AARCH64_OPND_IMM_MOV , AARCH64_OPND_IMM_ROT1 , AARCH64_OPND_IMM_ROT2 , AARCH64_OPND_IMM_ROT3 , AARCH64_OPND_COND , AARCH64_OPND_COND1 , AARCH64_OPND_ADDR_ADRP , AARCH64_OPND_ADDR_PCREL14 , AARCH64_OPND_ADDR_PCREL19 , AARCH64_OPND_ADDR_PCREL21 , AARCH64_OPND_ADDR_PCREL26 , AARCH64_OPND_ADDR_SIMPLE , AARCH64_OPND_ADDR_REGOFF , AARCH64_OPND_ADDR_SIMM7 , AARCH64_OPND_ADDR_SIMM9 , AARCH64_OPND_ADDR_SIMM9_2 , AARCH64_OPND_ADDR_SIMM10 , AARCH64_OPND_ADDR_UIMM12 , AARCH64_OPND_SIMD_ADDR_SIMPLE , AARCH64_OPND_ADDR_OFFSET , AARCH64_OPND_SIMD_ADDR_POST , AARCH64_OPND_SYSREG , AARCH64_OPND_PSTATEFIELD , AARCH64_OPND_SYSREG_AT , AARCH64_OPND_SYSREG_DC , AARCH64_OPND_SYSREG_IC , AARCH64_OPND_SYSREG_TLBI , AARCH64_OPND_BARRIER , AARCH64_OPND_BARRIER_ISB , AARCH64_OPND_PRFOP , AARCH64_OPND_BARRIER_PSB , AARCH64_OPND_SVE_ADDR_RI_S4x16 , AARCH64_OPND_SVE_ADDR_RI_S4xVL , AARCH64_OPND_SVE_ADDR_RI_S4x2xVL , AARCH64_OPND_SVE_ADDR_RI_S4x3xVL , AARCH64_OPND_SVE_ADDR_RI_S4x4xVL , AARCH64_OPND_SVE_ADDR_RI_S6xVL , AARCH64_OPND_SVE_ADDR_RI_S9xVL , AARCH64_OPND_SVE_ADDR_RI_U6 , AARCH64_OPND_SVE_ADDR_RI_U6x2 , AARCH64_OPND_SVE_ADDR_RI_U6x4 , AARCH64_OPND_SVE_ADDR_RI_U6x8 , AARCH64_OPND_SVE_ADDR_R , AARCH64_OPND_SVE_ADDR_RR , AARCH64_OPND_SVE_ADDR_RR_LSL1 , AARCH64_OPND_SVE_ADDR_RR_LSL2 , AARCH64_OPND_SVE_ADDR_RR_LSL3 , AARCH64_OPND_SVE_ADDR_RX , AARCH64_OPND_SVE_ADDR_RX_LSL1 , AARCH64_OPND_SVE_ADDR_RX_LSL2 , AARCH64_OPND_SVE_ADDR_RX_LSL3 , AARCH64_OPND_SVE_ADDR_RZ , AARCH64_OPND_SVE_ADDR_RZ_LSL1 , AARCH64_OPND_SVE_ADDR_RZ_LSL2 , AARCH64_OPND_SVE_ADDR_RZ_LSL3 , AARCH64_OPND_SVE_ADDR_RZ_XTW_14 , AARCH64_OPND_SVE_ADDR_RZ_XTW_22 , AARCH64_OPND_SVE_ADDR_RZ_XTW1_14 , AARCH64_OPND_SVE_ADDR_RZ_XTW1_22 , AARCH64_OPND_SVE_ADDR_RZ_XTW2_14 , AARCH64_OPND_SVE_ADDR_RZ_XTW2_22 , AARCH64_OPND_SVE_ADDR_RZ_XTW3_14 , AARCH64_OPND_SVE_ADDR_RZ_XTW3_22 , AARCH64_OPND_SVE_ADDR_ZI_U5 , AARCH64_OPND_SVE_ADDR_ZI_U5x2 , AARCH64_OPND_SVE_ADDR_ZI_U5x4 , AARCH64_OPND_SVE_ADDR_ZI_U5x8 , AARCH64_OPND_SVE_ADDR_ZZ_LSL , AARCH64_OPND_SVE_ADDR_ZZ_SXTW , AARCH64_OPND_SVE_ADDR_ZZ_UXTW , AARCH64_OPND_SVE_AIMM , AARCH64_OPND_SVE_ASIMM , AARCH64_OPND_SVE_FPIMM8 , AARCH64_OPND_SVE_I1_HALF_ONE , AARCH64_OPND_SVE_I1_HALF_TWO , AARCH64_OPND_SVE_I1_ZERO_ONE , AARCH64_OPND_SVE_IMM_ROT1 , AARCH64_OPND_SVE_IMM_ROT2 , AARCH64_OPND_SVE_INV_LIMM , AARCH64_OPND_SVE_LIMM , AARCH64_OPND_SVE_LIMM_MOV , AARCH64_OPND_SVE_PATTERN , AARCH64_OPND_SVE_PATTERN_SCALED , AARCH64_OPND_SVE_PRFOP , AARCH64_OPND_SVE_Pd , AARCH64_OPND_SVE_Pg3 , AARCH64_OPND_SVE_Pg4_5 , AARCH64_OPND_SVE_Pg4_10 , AARCH64_OPND_SVE_Pg4_16 , AARCH64_OPND_SVE_Pm , AARCH64_OPND_SVE_Pn , AARCH64_OPND_SVE_Pt , AARCH64_OPND_SVE_Rm , AARCH64_OPND_SVE_Rn_SP , AARCH64_OPND_SVE_SHLIMM_PRED , AARCH64_OPND_SVE_SHLIMM_UNPRED , AARCH64_OPND_SVE_SHRIMM_PRED , AARCH64_OPND_SVE_SHRIMM_UNPRED , AARCH64_OPND_SVE_SIMM5 , AARCH64_OPND_SVE_SIMM5B , AARCH64_OPND_SVE_SIMM6 , AARCH64_OPND_SVE_SIMM8 , AARCH64_OPND_SVE_UIMM3 , AARCH64_OPND_SVE_UIMM7 , AARCH64_OPND_SVE_UIMM8 , AARCH64_OPND_SVE_UIMM8_53 , AARCH64_OPND_SVE_VZn , AARCH64_OPND_SVE_Vd , AARCH64_OPND_SVE_Vm , AARCH64_OPND_SVE_Vn , AARCH64_OPND_SVE_Za_5 , AARCH64_OPND_SVE_Za_16 , AARCH64_OPND_SVE_Zd , AARCH64_OPND_SVE_Zm_5 , AARCH64_OPND_SVE_Zm_16 , AARCH64_OPND_SVE_Zm3_INDEX , AARCH64_OPND_SVE_Zm3_22_INDEX , AARCH64_OPND_SVE_Zm4_INDEX , AARCH64_OPND_SVE_Zn , AARCH64_OPND_SVE_Zn_INDEX , AARCH64_OPND_SVE_ZnxN , AARCH64_OPND_SVE_Zt , AARCH64_OPND_SVE_ZtxN , AARCH64_OPND_SM3_IMM2 }

enum	aarch64_opnd_qualifier { AARCH64_OPND_QLF_NIL , AARCH64_OPND_QLF_W , AARCH64_OPND_QLF_X , AARCH64_OPND_QLF_WSP , AARCH64_OPND_QLF_SP , AARCH64_OPND_QLF_S_B , AARCH64_OPND_QLF_S_H , AARCH64_OPND_QLF_S_S , AARCH64_OPND_QLF_S_D , AARCH64_OPND_QLF_S_Q , AARCH64_OPND_QLF_S_4B , AARCH64_OPND_QLF_V_4B , AARCH64_OPND_QLF_V_8B , AARCH64_OPND_QLF_V_16B , AARCH64_OPND_QLF_V_2H , AARCH64_OPND_QLF_V_4H , AARCH64_OPND_QLF_V_8H , AARCH64_OPND_QLF_V_2S , AARCH64_OPND_QLF_V_4S , AARCH64_OPND_QLF_V_1D , AARCH64_OPND_QLF_V_2D , AARCH64_OPND_QLF_V_1Q , AARCH64_OPND_QLF_P_Z , AARCH64_OPND_QLF_P_M , AARCH64_OPND_QLF_CR , AARCH64_OPND_QLF_imm_0_7 , AARCH64_OPND_QLF_imm_0_15 , AARCH64_OPND_QLF_imm_0_31 , AARCH64_OPND_QLF_imm_0_63 , AARCH64_OPND_QLF_imm_1_32 , AARCH64_OPND_QLF_imm_1_64 , AARCH64_OPND_QLF_LSL , AARCH64_OPND_QLF_MSL , AARCH64_OPND_QLF_RETRIEVE }

enum	aarch64_insn_class { addsub_carry , addsub_ext , addsub_imm , addsub_shift , asimdall , asimddiff , asimdelem , asimdext , asimdimm , asimdins , asimdmisc , asimdperm , asimdsame , asimdshf , asimdtbl , asisddiff , asisdelem , asisdlse , asisdlsep , asisdlso , asisdlsop , asisdmisc , asisdone , asisdpair , asisdsame , asisdshf , bitfield , branch_imm , branch_reg , compbranch , condbranch , condcmp_imm , condcmp_reg , condsel , cryptoaes , cryptosha2 , cryptosha3 , dp_1src , dp_2src , dp_3src , exception , extract , float2fix , float2int , floatccmp , floatcmp , floatdp1 , floatdp2 , floatdp3 , floatimm , floatsel , ldst_immpost , ldst_immpre , ldst_imm9 , ldst_imm10 , ldst_pos , ldst_regoff , ldst_unpriv , ldst_unscaled , ldstexcl , ldstnapair_offs , ldstpair_off , ldstpair_indexed , loadlit , log_imm , log_shift , lse_atomic , movewide , pcreladdr , ic_system , sve_cpy , sve_index , sve_limm , sve_misc , sve_movprfx , sve_pred_zm , sve_shift_pred , sve_shift_unpred , sve_size_bhs , sve_size_bhsd , sve_size_hsd , sve_size_sd , testbranch , cryptosm3 , cryptosm4 , dotproduct }

enum	aarch64_op { OP_NIL , OP_STRB_POS , OP_LDRB_POS , OP_LDRSB_POS , OP_STRH_POS , OP_LDRH_POS , OP_LDRSH_POS , OP_STR_POS , OP_LDR_POS , OP_STRF_POS , OP_LDRF_POS , OP_LDRSW_POS , OP_PRFM_POS , OP_STURB , OP_LDURB , OP_LDURSB , OP_STURH , OP_LDURH , OP_LDURSH , OP_STUR , OP_LDUR , OP_STURV , OP_LDURV , OP_LDURSW , OP_PRFUM , OP_LDR_LIT , OP_LDRV_LIT , OP_LDRSW_LIT , OP_PRFM_LIT , OP_ADD , OP_B , OP_BL , OP_MOVN , OP_MOVZ , OP_MOVK , OP_MOV_IMM_LOG , OP_MOV_IMM_WIDE , OP_MOV_IMM_WIDEN , OP_MOV_V , OP_ASR_IMM , OP_LSR_IMM , OP_LSL_IMM , OP_BIC , OP_UBFX , OP_BFXIL , OP_SBFX , OP_SBFIZ , OP_BFI , OP_BFC , OP_UBFIZ , OP_UXTB , OP_UXTH , OP_UXTW , OP_CINC , OP_CINV , OP_CNEG , OP_CSET , OP_CSETM , OP_FCVT , OP_FCVTN , OP_FCVTN2 , OP_FCVTL , OP_FCVTL2 , OP_FCVTXN_S , OP_ROR_IMM , OP_SXTL , OP_SXTL2 , OP_UXTL , OP_UXTL2 , OP_MOV_P_P , OP_MOV_Z_P_Z , OP_MOV_Z_V , OP_MOV_Z_Z , OP_MOV_Z_Zi , OP_MOVM_P_P_P , OP_MOVS_P_P , OP_MOVZS_P_P_P , OP_MOVZ_P_P_P , OP_NOTS_P_P_P_Z , OP_NOT_P_P_P_Z , OP_FCMLA_ELEM , OP_TOTAL_NUM }

enum	aarch64_modifier_kind { AARCH64_MOD_NONE , AARCH64_MOD_MSL , AARCH64_MOD_ROR , AARCH64_MOD_ASR , AARCH64_MOD_LSR , AARCH64_MOD_LSL , AARCH64_MOD_UXTB , AARCH64_MOD_UXTH , AARCH64_MOD_UXTW , AARCH64_MOD_UXTX , AARCH64_MOD_SXTB , AARCH64_MOD_SXTH , AARCH64_MOD_SXTW , AARCH64_MOD_SXTX , AARCH64_MOD_MUL , AARCH64_MOD_MUL_VL }

enum	aarch64_operand_error_kind { AARCH64_OPDE_NIL , AARCH64_OPDE_RECOVERABLE , AARCH64_OPDE_SYNTAX_ERROR , AARCH64_OPDE_FATAL_SYNTAX_ERROR , AARCH64_OPDE_INVALID_VARIANT , AARCH64_OPDE_UNTIED_OPERAND , AARCH64_OPDE_OUT_OF_RANGE , AARCH64_OPDE_UNALIGNED , AARCH64_OPDE_REG_LIST , AARCH64_OPDE_OTHER_ERROR }

Functions
static bfd_boolean	empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)

static bfd_boolean	alias_opcode_p (const aarch64_opcode *opcode)

static bfd_boolean	opcode_has_alias (const aarch64_opcode *opcode)

static int	opcode_priority (const aarch64_opcode *opcode)

static bfd_boolean	pseudo_opcode_p (const aarch64_opcode *opcode)

static bfd_boolean	optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)

static aarch64_insn	get_optional_operand_default_value (const aarch64_opcode *opcode)

static unsigned int	get_opcode_dependent_value (const aarch64_opcode *opcode)

static bfd_boolean	opcode_has_special_coder (const aarch64_opcode *opcode)

bfd_boolean	aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *)

bfd_boolean	aarch64_sys_reg_supported_p (const aarch64_feature_set, const aarch64_sys_reg *)

bfd_boolean	aarch64_pstatefield_supported_p (const aarch64_feature_set, const aarch64_sys_reg *)

bfd_boolean	aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *)

bfd_boolean	aarch64_sys_ins_reg_supported_p (const aarch64_feature_set, const aarch64_sys_ins_reg *)

bfd_boolean	aarch64_extend_operator_p (enum aarch64_modifier_kind)

enum aarch64_modifier_kind	aarch64_get_operand_modifier (const struct aarch64_name_value_pair *)

const aarch64_cond *	get_cond_from_value (aarch64_insn value)

const aarch64_cond *	get_inverted_cond (const aarch64_cond *cond)

int	aarch64_opcode_encode (const aarch64_opcode , const aarch64_inst , aarch64_insn , aarch64_opnd_qualifier_t , aarch64_operand_error *)

const aarch64_opcode *	aarch64_replace_opcode (struct aarch64_inst , const aarch64_opcode )

const aarch64_opcode *	aarch64_get_opcode (enum aarch64_op)

void	aarch64_print_operand (char , size_t, bfd_vma, const aarch64_opcode , const aarch64_opnd_info , int, int , bfd_vma , char *)

int	aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd)

aarch64_opnd_qualifier_t	aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int, const aarch64_opnd_qualifier_t, int)

int	aarch64_num_of_operands (const aarch64_opcode *)

int	aarch64_stack_pointer_p (const aarch64_opnd_info *)

int	aarch64_zero_register_p (const aarch64_opnd_info *)

int	aarch64_decode_insn (aarch64_insn, aarch64_inst , bfd_boolean, aarch64_operand_error errors)

unsigned char	aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t)

enum aarch64_operand_class	aarch64_get_operand_class (enum aarch64_opnd)

const char *	aarch64_get_operand_name (enum aarch64_opnd)

const char *	aarch64_get_operand_desc (enum aarch64_opnd)

bfd_boolean	aarch64_sve_dupm_mov_immediate_p (uint64_t, int)

Variables
aarch64_opcode	aarch64_opcode_table []

const struct aarch64_name_value_pair	aarch64_operand_modifiers []

const struct aarch64_name_value_pair	aarch64_barrier_options [16]

const struct aarch64_name_value_pair	aarch64_prfops [32]

const struct aarch64_name_value_pair	aarch64_hint_options []

const aarch64_sys_reg	aarch64_sys_regs []

const aarch64_sys_reg	aarch64_pstatefields []

const aarch64_sys_ins_reg	aarch64_sys_regs_ic []

const aarch64_sys_ins_reg	aarch64_sys_regs_dc []

const aarch64_sys_ins_reg	aarch64_sys_regs_at []

const aarch64_sys_ins_reg	aarch64_sys_regs_tlbi []

const aarch64_cond	aarch64_conds [16]

const char *const	aarch64_sve_pattern_array [32]

const char *const	aarch64_sve_prfop_array [16]

Macro Definition Documentation

◆ AARCH64_ANY

#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */

Definition at line 93 of file aarch64.h.

◆ AARCH64_ARCH_NONE

#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)

Definition at line 92 of file aarch64.h.

◆ AARCH64_ARCH_V8

#define AARCH64_ARCH_V8

Value:

                         AARCH64_FEATURE (AARCH64_FEATURE_V8, \
                         AARCH64_FEATURE_FP  \
                         | AARCH64_FEATURE_SIMD)

Definition at line 70 of file aarch64.h.

◆ AARCH64_ARCH_V8_1

#define AARCH64_ARCH_V8_1

Value:

                         AARCH64_FEATURE (AARCH64_ARCH_V8, \
                         AARCH64_FEATURE_CRC    \
                         | AARCH64_FEATURE_V8_1 \
                         | AARCH64_FEATURE_LSE  \
                         | AARCH64_FEATURE_PAN  \
                         | AARCH64_FEATURE_LOR  \
                         | AARCH64_FEATURE_RDMA)

Definition at line 73 of file aarch64.h.

◆ AARCH64_ARCH_V8_2

#define AARCH64_ARCH_V8_2

Value:

                         AARCH64_FEATURE (AARCH64_ARCH_V8_1,    \
                         AARCH64_FEATURE_V8_2   \
                         | AARCH64_FEATURE_RAS)

Definition at line 80 of file aarch64.h.

◆ AARCH64_ARCH_V8_3

#define AARCH64_ARCH_V8_3

Value:

                         AARCH64_FEATURE (AARCH64_ARCH_V8_2,    \
                         AARCH64_FEATURE_V8_3   \
                         | AARCH64_FEATURE_RCPC \
                         | AARCH64_FEATURE_COMPNUM)

Definition at line 83 of file aarch64.h.

◆ AARCH64_ARCH_V8_4

#define AARCH64_ARCH_V8_4

Value:

                         AARCH64_FEATURE (AARCH64_ARCH_V8_3,    \
                         AARCH64_FEATURE_V8_4   \
                         | AARCH64_FEATURE_DOTPROD \
                         | AARCH64_FEATURE_F16_FML)

Definition at line 87 of file aarch64.h.

◆ AARCH64_CLEAR_FEATURE

#define AARCH64_CLEAR_FEATURE	(	TARG,
		F1,
		F2
	)

Value:

  do                        \
    {                       \
      (TARG) = (F1) &~ (F2);            \
    }                       \
  while (0)

Definition at line 114 of file aarch64.h.

◆ AARCH64_CPU_HAS_ALL_FEATURES

#define AARCH64_CPU_HAS_ALL_FEATURES	(	CPU,
		FEAT
	)	((~(CPU) & (FEAT)) == 0)

Definition at line 98 of file aarch64.h.

◆ AARCH64_CPU_HAS_ANY_FEATURES

#define AARCH64_CPU_HAS_ANY_FEATURES	(	CPU,
		FEAT
	)	(((CPU) & (FEAT)) != 0)

Definition at line 101 of file aarch64.h.

◆ AARCH64_CPU_HAS_FEATURE

#define AARCH64_CPU_HAS_FEATURE	(	CPU,
		FEAT
	)	AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)

Definition at line 104 of file aarch64.h.

◆ AARCH64_FEATURE

#define AARCH64_FEATURE	(	core,
		coproc
	)	((core) \| (coproc))

Definition at line 121 of file aarch64.h.

◆ AARCH64_FEATURE_AES

#define AARCH64_FEATURE_AES 0x800000000ULL /* AES instructions. */

Definition at line 44 of file aarch64.h.

◆ AARCH64_FEATURE_COMPNUM

#define AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */

Definition at line 65 of file aarch64.h.

◆ AARCH64_FEATURE_CRC

#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */

Definition at line 54 of file aarch64.h.

◆ AARCH64_FEATURE_CRYPTO

#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */

Definition at line 51 of file aarch64.h.

◆ AARCH64_FEATURE_DOTPROD

#define AARCH64_FEATURE_DOTPROD 0x080000000 /* Dot Product instructions. */

Definition at line 66 of file aarch64.h.

◆ AARCH64_FEATURE_F16

#define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */

Definition at line 60 of file aarch64.h.

◆ AARCH64_FEATURE_F16_FML

#define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins. */

Definition at line 67 of file aarch64.h.

◆ AARCH64_FEATURE_FP

#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */

Definition at line 52 of file aarch64.h.

◆ AARCH64_FEATURE_LOR

#define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */

Definition at line 57 of file aarch64.h.

◆ AARCH64_FEATURE_LSE

#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */

Definition at line 55 of file aarch64.h.

◆ AARCH64_FEATURE_PAN

#define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */

Definition at line 56 of file aarch64.h.

◆ AARCH64_FEATURE_PROFILE

#define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */

Definition at line 62 of file aarch64.h.

◆ AARCH64_FEATURE_RAS

#define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */

Definition at line 61 of file aarch64.h.

◆ AARCH64_FEATURE_RCPC

#define AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */

Definition at line 64 of file aarch64.h.

◆ AARCH64_FEATURE_RDMA

#define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */

Definition at line 58 of file aarch64.h.

◆ AARCH64_FEATURE_SHA2

#define AARCH64_FEATURE_SHA2 0x200000000ULL /* SHA2 instructions. */

Definition at line 43 of file aarch64.h.

◆ AARCH64_FEATURE_SHA3

#define AARCH64_FEATURE_SHA3 0x400000000ULL /* SHA3 instructions. */

Definition at line 47 of file aarch64.h.

◆ AARCH64_FEATURE_SIMD

#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */

Definition at line 53 of file aarch64.h.

◆ AARCH64_FEATURE_SM4

#define AARCH64_FEATURE_SM4 0x100000000ULL /* SM3 & SM4 instructions. */

Definition at line 46 of file aarch64.h.

◆ AARCH64_FEATURE_SVE

#define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */

Definition at line 63 of file aarch64.h.

◆ AARCH64_FEATURE_V8

#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */

Definition at line 48 of file aarch64.h.

◆ AARCH64_FEATURE_V8_1

#define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */

Definition at line 59 of file aarch64.h.

◆ AARCH64_FEATURE_V8_2

#define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */

Definition at line 49 of file aarch64.h.

◆ AARCH64_FEATURE_V8_3

#define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */

Definition at line 50 of file aarch64.h.

◆ AARCH64_FEATURE_V8_4

#define AARCH64_FEATURE_V8_4 0x000000800ULL /* ARMv8.4 processors. */

Definition at line 45 of file aarch64.h.

◆ AARCH64_MAX_OPND_NUM

#define AARCH64_MAX_OPND_NUM 6

Definition at line 648 of file aarch64.h.

◆ AARCH64_MAX_QLF_SEQ_NUM

#define AARCH64_MAX_QLF_SEQ_NUM 10

Definition at line 650 of file aarch64.h.

◆ AARCH64_MERGE_FEATURE_SETS

#define AARCH64_MERGE_FEATURE_SETS	(	TARG,
		F1,
		F2
	)

Value:

  do                        \
    {                       \
      (TARG) = (F1) | (F2);         \
    }                       \
  while (0)

Definition at line 107 of file aarch64.h.

◆ AARCH64_PCREL_OFFSET

#define AARCH64_PCREL_OFFSET 0

Definition at line 38 of file aarch64.h.

◆ DEBUG_TRACE

#define DEBUG_TRACE	(	M,
		...
	)	;

Definition at line 1198 of file aarch64.h.

◆ DEBUG_TRACE_IF

#define DEBUG_TRACE_IF	(	C,
		M,
		...
	)	;

Definition at line 1199 of file aarch64.h.

◆ F_ALIAS

#define F_ALIAS (1 << 0)

Definition at line 722 of file aarch64.h.

◆ F_COND

#define F_COND (1 << 4)

Definition at line 730 of file aarch64.h.

◆ F_CONV

#define F_CONV (1 << 20)

Definition at line 758 of file aarch64.h.

◆ F_DEFAULT

#define F_DEFAULT ( X ) (((X) & 0x1f) << 15)

Definition at line 752 of file aarch64.h.

◆ F_FPTYPE

#define F_FPTYPE (1 << 7)

Definition at line 736 of file aarch64.h.

◆ F_GPRSIZE_IN_Q

#define F_GPRSIZE_IN_Q (1 << 10)

Definition at line 742 of file aarch64.h.

◆ F_HAS_ALIAS

#define F_HAS_ALIAS (1 << 1)

Definition at line 723 of file aarch64.h.

◆ F_LDS_SIZE

#define F_LDS_SIZE (1 << 11)

Definition at line 744 of file aarch64.h.

◆ F_LSE_SZ

#define F_LSE_SZ (1 << 27)

Definition at line 770 of file aarch64.h.

◆ F_MISC

#define F_MISC (1 << 22)

Definition at line 764 of file aarch64.h.

◆ F_N

#define F_N (1 << 23)

Definition at line 766 of file aarch64.h.

◆ F_OD

#define F_OD ( X ) (((X) & 0x7) << 24)

Definition at line 768 of file aarch64.h.

◆ F_OPD0_OPT

#define F_OPD0_OPT (1 << 12)

Definition at line 746 of file aarch64.h.

◆ F_OPD1_OPT

#define F_OPD1_OPT (2 << 12)

Definition at line 747 of file aarch64.h.

◆ F_OPD2_OPT

#define F_OPD2_OPT (3 << 12)

Definition at line 748 of file aarch64.h.

◆ F_OPD3_OPT

#define F_OPD3_OPT (4 << 12)

Definition at line 749 of file aarch64.h.

◆ F_OPD4_OPT

#define F_OPD4_OPT (5 << 12)

Definition at line 750 of file aarch64.h.

◆ F_P1

#define F_P1 (1 << 2)

Definition at line 726 of file aarch64.h.

◆ F_P2

#define F_P2 (2 << 2)

Definition at line 727 of file aarch64.h.

◆ F_P3

#define F_P3 (3 << 2)

Definition at line 728 of file aarch64.h.

◆ F_PSEUDO

#define F_PSEUDO (1 << 21)

Definition at line 762 of file aarch64.h.

◆ F_SF

#define F_SF (1 << 5)

Definition at line 732 of file aarch64.h.

◆ F_SIZEQ

#define F_SIZEQ (1 << 6)

Definition at line 734 of file aarch64.h.

◆ F_SSIZE

#define F_SSIZE (1 << 8)

Definition at line 738 of file aarch64.h.

◆ F_STRICT

#define F_STRICT (1ULL << 28)

Definition at line 772 of file aarch64.h.

◆ F_SYS_READ

#define F_SYS_READ (1ULL << 29)

Definition at line 774 of file aarch64.h.

◆ F_SYS_WRITE

#define F_SYS_WRITE (1ULL << 30)

Definition at line 776 of file aarch64.h.

◆ F_T

#define F_T (1 << 9)

Definition at line 740 of file aarch64.h.

Typedef Documentation

◆ aarch64_feature_set

typedef unsigned long long aarch64_feature_set

Definition at line 96 of file aarch64.h.

◆ aarch64_insn

typedef uint32_t aarch64_insn

Definition at line 40 of file aarch64.h.

◆ aarch64_inst

typedef struct aarch64_inst aarch64_inst

Definition at line 914 of file aarch64.h.

◆ aarch64_opcode

typedef struct aarch64_opcode aarch64_opcode

Definition at line 659 of file aarch64.h.

◆ aarch64_operand_error

typedef struct aarch64_operand_error aarch64_operand_error

Definition at line 914 of file aarch64.h.

◆ aarch64_opnd_info

typedef struct aarch64_opnd_info aarch64_opnd_info

Definition at line 914 of file aarch64.h.

◆ aarch64_opnd_qualifier_seq_t

typedef aarch64_opnd_qualifier_t aarch64_opnd_qualifier_seq_t[AARCH64_MAX_OPND_NUM]

Definition at line 655 of file aarch64.h.

◆ aarch64_opnd_qualifier_t

typedef unsigned char aarch64_opnd_qualifier_t

Definition at line 652 of file aarch64.h.

Enumeration Type Documentation

◆ aarch64_insn_class

enum aarch64_insn_class

Enumerator
addsub_carry
addsub_ext
addsub_imm
addsub_shift
asimdall
asimddiff
asimdelem
asimdext
asimdimm
asimdins
asimdmisc
asimdperm
asimdsame
asimdshf
asimdtbl
asisddiff
asisdelem
asisdlse
asisdlsep
asisdlso
asisdlsop
asisdmisc
asisdone
asisdpair
asisdsame
asisdshf
bitfield
branch_imm
branch_reg
compbranch
condbranch
condcmp_imm
condcmp_reg
condsel
cryptoaes
cryptosha2
cryptosha3
dp_1src
dp_2src
dp_3src
exception
extract
float2fix
float2int
floatccmp
floatcmp
floatdp1
floatdp2
floatdp3
floatimm
floatsel
ldst_immpost
ldst_immpre
ldst_imm9
ldst_imm10
ldst_pos
ldst_regoff
ldst_unpriv
ldst_unscaled
ldstexcl
ldstnapair_offs
ldstpair_off
ldstpair_indexed
loadlit
log_imm
log_shift
lse_atomic
movewide
pcreladdr
ic_system
sve_cpy
sve_index
sve_limm
sve_misc
sve_movprfx
sve_pred_zm
sve_shift_pred
sve_shift_unpred
sve_size_bhs
sve_size_bhsd
sve_size_hsd
sve_size_sd
testbranch
cryptosm3
cryptosm4
dotproduct

Definition at line 453 of file aarch64.h.

 {
   addsub_carry,
   addsub_ext,
   addsub_imm,
   addsub_shift,
   asimdall,
   asimddiff,
   asimdelem,
   asimdext,
   asimdimm,
   asimdins,
   asimdmisc,
   asimdperm,
   asimdsame,
   asimdshf,
   asimdtbl,
   asisddiff,
   asisdelem,
   asisdlse,
   asisdlsep,
   asisdlso,
   asisdlsop,
   asisdmisc,
   asisdone,
   asisdpair,
   asisdsame,
   asisdshf,
   bitfield,
   branch_imm,
   branch_reg,
   compbranch,
   condbranch,
   condcmp_imm,
   condcmp_reg,
   condsel,
   cryptoaes,
   cryptosha2,
   cryptosha3,
   dp_1src,
   dp_2src,
   dp_3src,
   exception,
   extract,
   float2fix,
   float2int,
   floatccmp,
   floatcmp,
   floatdp1,
   floatdp2,
   floatdp3,
   floatimm,
   floatsel,
   ldst_immpost,
   ldst_immpre,
   ldst_imm9,    /* immpost or immpre */
   ldst_imm10,   /* LDRAA/LDRAB */
   ldst_pos,
   ldst_regoff,
   ldst_unpriv,
   ldst_unscaled,
   ldstexcl,
   ldstnapair_offs,
   ldstpair_off,
   ldstpair_indexed,
   loadlit,
   log_imm,
   log_shift,
   lse_atomic,
   movewide,
   pcreladdr,
   ic_system,
   sve_cpy,
   sve_index,
   sve_limm,
   sve_misc,
   sve_movprfx,
   sve_pred_zm,
   sve_shift_pred,
   sve_shift_unpred,
   sve_size_bhs,
   sve_size_bhsd,
   sve_size_hsd,
   sve_size_sd,
   testbranch,
   cryptosm3,
   cryptosm4,
   dotproduct,
 };

◆ aarch64_modifier_kind

enum aarch64_modifier_kind

Enumerator
AARCH64_MOD_NONE
AARCH64_MOD_MSL
AARCH64_MOD_ROR
AARCH64_MOD_ASR
AARCH64_MOD_LSR
AARCH64_MOD_LSL
AARCH64_MOD_UXTB
AARCH64_MOD_UXTH
AARCH64_MOD_UXTW
AARCH64_MOD_UXTX
AARCH64_MOD_SXTB
AARCH64_MOD_SXTH
AARCH64_MOD_SXTW
AARCH64_MOD_SXTX
AARCH64_MOD_MUL
AARCH64_MOD_MUL_VL

Definition at line 876 of file aarch64.h.

 {
   AARCH64_MOD_NONE,
   AARCH64_MOD_MSL,
   AARCH64_MOD_ROR,
   AARCH64_MOD_ASR,
   AARCH64_MOD_LSR,
   AARCH64_MOD_LSL,
   AARCH64_MOD_UXTB,
   AARCH64_MOD_UXTH,
   AARCH64_MOD_UXTW,
   AARCH64_MOD_UXTX,
   AARCH64_MOD_SXTB,
   AARCH64_MOD_SXTH,
   AARCH64_MOD_SXTW,
   AARCH64_MOD_SXTX,
   AARCH64_MOD_MUL,
   AARCH64_MOD_MUL_VL,
 };

◆ aarch64_op

enum aarch64_op

Enumerator
OP_NIL
OP_STRB_POS
OP_LDRB_POS
OP_LDRSB_POS
OP_STRH_POS
OP_LDRH_POS
OP_LDRSH_POS
OP_STR_POS
OP_LDR_POS
OP_STRF_POS
OP_LDRF_POS
OP_LDRSW_POS
OP_PRFM_POS
OP_STURB
OP_LDURB
OP_LDURSB
OP_STURH
OP_LDURH
OP_LDURSH
OP_STUR
OP_LDUR
OP_STURV
OP_LDURV
OP_LDURSW
OP_PRFUM
OP_LDR_LIT
OP_LDRV_LIT
OP_LDRSW_LIT
OP_PRFM_LIT
OP_ADD
OP_B
OP_BL
OP_MOVN
OP_MOVZ
OP_MOVK
OP_MOV_IMM_LOG
OP_MOV_IMM_WIDE
OP_MOV_IMM_WIDEN
OP_MOV_V
OP_ASR_IMM
OP_LSR_IMM
OP_LSL_IMM
OP_BIC
OP_UBFX
OP_BFXIL
OP_SBFX
OP_SBFIZ
OP_BFI
OP_BFC
OP_UBFIZ
OP_UXTB
OP_UXTH
OP_UXTW
OP_CINC
OP_CINV
OP_CNEG
OP_CSET
OP_CSETM
OP_FCVT
OP_FCVTN
OP_FCVTN2
OP_FCVTL
OP_FCVTL2
OP_FCVTXN_S
OP_ROR_IMM
OP_SXTL
OP_SXTL2
OP_UXTL
OP_UXTL2
OP_MOV_P_P
OP_MOV_Z_P_Z
OP_MOV_Z_V
OP_MOV_Z_Z
OP_MOV_Z_Zi
OP_MOVM_P_P_P
OP_MOVS_P_P
OP_MOVZS_P_P_P
OP_MOVZ_P_P_P
OP_NOTS_P_P_P_Z
OP_NOT_P_P_P_Z
OP_FCMLA_ELEM
OP_TOTAL_NUM

Definition at line 545 of file aarch64.h.

 {
   OP_NIL,
   OP_STRB_POS,
   OP_LDRB_POS,
   OP_LDRSB_POS,
   OP_STRH_POS,
   OP_LDRH_POS,
   OP_LDRSH_POS,
   OP_STR_POS,
   OP_LDR_POS,
   OP_STRF_POS,
   OP_LDRF_POS,
   OP_LDRSW_POS,
   OP_PRFM_POS,
  
   OP_STURB,
   OP_LDURB,
   OP_LDURSB,
   OP_STURH,
   OP_LDURH,
   OP_LDURSH,
   OP_STUR,
   OP_LDUR,
   OP_STURV,
   OP_LDURV,
   OP_LDURSW,
   OP_PRFUM,
  
   OP_LDR_LIT,
   OP_LDRV_LIT,
   OP_LDRSW_LIT,
   OP_PRFM_LIT,
  
   OP_ADD,
   OP_B,
   OP_BL,
  
   OP_MOVN,
   OP_MOVZ,
   OP_MOVK,
  
   OP_MOV_IMM_LOG,   /* MOV alias for moving bitmask immediate.  */
   OP_MOV_IMM_WIDE,  /* MOV alias for moving wide immediate.  */
   OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated).  */
  
   OP_MOV_V,     /* MOV alias for moving vector register.  */
  
   OP_ASR_IMM,
   OP_LSR_IMM,
   OP_LSL_IMM,
  
   OP_BIC,
  
   OP_UBFX,
   OP_BFXIL,
   OP_SBFX,
   OP_SBFIZ,
   OP_BFI,
   OP_BFC,       /* ARMv8.2.  */
   OP_UBFIZ,
   OP_UXTB,
   OP_UXTH,
   OP_UXTW,
  
   OP_CINC,
   OP_CINV,
   OP_CNEG,
   OP_CSET,
   OP_CSETM,
  
   OP_FCVT,
   OP_FCVTN,
   OP_FCVTN2,
   OP_FCVTL,
   OP_FCVTL2,
   OP_FCVTXN_S,      /* Scalar version.  */
  
   OP_ROR_IMM,
  
   OP_SXTL,
   OP_SXTL2,
   OP_UXTL,
   OP_UXTL2,
  
   OP_MOV_P_P,
   OP_MOV_Z_P_Z,
   OP_MOV_Z_V,
   OP_MOV_Z_Z,
   OP_MOV_Z_Zi,
   OP_MOVM_P_P_P,
   OP_MOVS_P_P,
   OP_MOVZS_P_P_P,
   OP_MOVZ_P_P_P,
   OP_NOTS_P_P_P_Z,
   OP_NOT_P_P_P_Z,
  
   OP_FCMLA_ELEM,    /* ARMv8.3, indexed element version.  */
  
   OP_TOTAL_NUM,     /* Pseudo.  */
 };

◆ aarch64_operand_class

enum aarch64_operand_class

Enumerator
AARCH64_OPND_CLASS_NIL
AARCH64_OPND_CLASS_INT_REG
AARCH64_OPND_CLASS_MODIFIED_REG
AARCH64_OPND_CLASS_FP_REG
AARCH64_OPND_CLASS_SIMD_REG
AARCH64_OPND_CLASS_SIMD_ELEMENT
AARCH64_OPND_CLASS_SISD_REG
AARCH64_OPND_CLASS_SIMD_REGLIST
AARCH64_OPND_CLASS_SVE_REG
AARCH64_OPND_CLASS_PRED_REG
AARCH64_OPND_CLASS_ADDRESS
AARCH64_OPND_CLASS_IMMEDIATE
AARCH64_OPND_CLASS_SYSTEM
AARCH64_OPND_CLASS_COND

Definition at line 123 of file aarch64.h.

 {
   AARCH64_OPND_CLASS_NIL,
   AARCH64_OPND_CLASS_INT_REG,
   AARCH64_OPND_CLASS_MODIFIED_REG,
   AARCH64_OPND_CLASS_FP_REG,
   AARCH64_OPND_CLASS_SIMD_REG,
   AARCH64_OPND_CLASS_SIMD_ELEMENT,
   AARCH64_OPND_CLASS_SISD_REG,
   AARCH64_OPND_CLASS_SIMD_REGLIST,
   AARCH64_OPND_CLASS_SVE_REG,
   AARCH64_OPND_CLASS_PRED_REG,
   AARCH64_OPND_CLASS_ADDRESS,
   AARCH64_OPND_CLASS_IMMEDIATE,
   AARCH64_OPND_CLASS_SYSTEM,
   AARCH64_OPND_CLASS_COND,
 };

◆ aarch64_operand_error_kind

enum aarch64_operand_error_kind

Enumerator
AARCH64_OPDE_NIL
AARCH64_OPDE_RECOVERABLE
AARCH64_OPDE_SYNTAX_ERROR
AARCH64_OPDE_FATAL_SYNTAX_ERROR
AARCH64_OPDE_INVALID_VARIANT
AARCH64_OPDE_UNTIED_OPERAND
AARCH64_OPDE_OUT_OF_RANGE
AARCH64_OPDE_UNALIGNED
AARCH64_OPDE_REG_LIST
AARCH64_OPDE_OTHER_ERROR

Definition at line 1092 of file aarch64.h.

 {
   AARCH64_OPDE_NIL,
   AARCH64_OPDE_RECOVERABLE,
   AARCH64_OPDE_SYNTAX_ERROR,
   AARCH64_OPDE_FATAL_SYNTAX_ERROR,
   AARCH64_OPDE_INVALID_VARIANT,
   AARCH64_OPDE_UNTIED_OPERAND,
   AARCH64_OPDE_OUT_OF_RANGE,
   AARCH64_OPDE_UNALIGNED,
   AARCH64_OPDE_REG_LIST,
   AARCH64_OPDE_OTHER_ERROR
 };

◆ aarch64_opnd

enum aarch64_opnd

Enumerator
AARCH64_OPND_NIL
AARCH64_OPND_Rd
AARCH64_OPND_Rn
AARCH64_OPND_Rm
AARCH64_OPND_Rt
AARCH64_OPND_Rt2
AARCH64_OPND_Rs
AARCH64_OPND_Ra
AARCH64_OPND_Rt_SYS
AARCH64_OPND_Rd_SP
AARCH64_OPND_Rn_SP
AARCH64_OPND_Rm_SP
AARCH64_OPND_PAIRREG
AARCH64_OPND_Rm_EXT
AARCH64_OPND_Rm_SFT
AARCH64_OPND_Fd
AARCH64_OPND_Fn
AARCH64_OPND_Fm
AARCH64_OPND_Fa
AARCH64_OPND_Ft
AARCH64_OPND_Ft2
AARCH64_OPND_Sd
AARCH64_OPND_Sn
AARCH64_OPND_Sm
AARCH64_OPND_Va
AARCH64_OPND_Vd
AARCH64_OPND_Vn
AARCH64_OPND_Vm
AARCH64_OPND_VdD1
AARCH64_OPND_VnD1
AARCH64_OPND_Ed
AARCH64_OPND_En
AARCH64_OPND_Em
AARCH64_OPND_Em16
AARCH64_OPND_LVn
AARCH64_OPND_LVt
AARCH64_OPND_LVt_AL
AARCH64_OPND_LEt
AARCH64_OPND_CRn
AARCH64_OPND_CRm
AARCH64_OPND_IDX
AARCH64_OPND_MASK
AARCH64_OPND_IMM_VLSL
AARCH64_OPND_IMM_VLSR
AARCH64_OPND_SIMD_IMM
AARCH64_OPND_SIMD_IMM_SFT
AARCH64_OPND_SIMD_FPIMM
AARCH64_OPND_SHLL_IMM
AARCH64_OPND_IMM0
AARCH64_OPND_FPIMM0
AARCH64_OPND_FPIMM
AARCH64_OPND_IMMR
AARCH64_OPND_IMMS
AARCH64_OPND_WIDTH
AARCH64_OPND_IMM
AARCH64_OPND_IMM_2
AARCH64_OPND_UIMM3_OP1
AARCH64_OPND_UIMM3_OP2
AARCH64_OPND_UIMM4
AARCH64_OPND_UIMM7
AARCH64_OPND_BIT_NUM
AARCH64_OPND_EXCEPTION
AARCH64_OPND_CCMP_IMM
AARCH64_OPND_SIMM5
AARCH64_OPND_NZCV
AARCH64_OPND_LIMM
AARCH64_OPND_AIMM
AARCH64_OPND_HALF
AARCH64_OPND_FBITS
AARCH64_OPND_IMM_MOV
AARCH64_OPND_IMM_ROT1
AARCH64_OPND_IMM_ROT2
AARCH64_OPND_IMM_ROT3
AARCH64_OPND_COND
AARCH64_OPND_COND1
AARCH64_OPND_ADDR_ADRP
AARCH64_OPND_ADDR_PCREL14
AARCH64_OPND_ADDR_PCREL19
AARCH64_OPND_ADDR_PCREL21
AARCH64_OPND_ADDR_PCREL26
AARCH64_OPND_ADDR_SIMPLE
AARCH64_OPND_ADDR_REGOFF
AARCH64_OPND_ADDR_SIMM7
AARCH64_OPND_ADDR_SIMM9
AARCH64_OPND_ADDR_SIMM9_2
AARCH64_OPND_ADDR_SIMM10
AARCH64_OPND_ADDR_UIMM12
AARCH64_OPND_SIMD_ADDR_SIMPLE
AARCH64_OPND_ADDR_OFFSET
AARCH64_OPND_SIMD_ADDR_POST
AARCH64_OPND_SYSREG
AARCH64_OPND_PSTATEFIELD
AARCH64_OPND_SYSREG_AT
AARCH64_OPND_SYSREG_DC
AARCH64_OPND_SYSREG_IC
AARCH64_OPND_SYSREG_TLBI
AARCH64_OPND_BARRIER
AARCH64_OPND_BARRIER_ISB
AARCH64_OPND_PRFOP
AARCH64_OPND_BARRIER_PSB
AARCH64_OPND_SVE_ADDR_RI_S4x16
AARCH64_OPND_SVE_ADDR_RI_S4xVL
AARCH64_OPND_SVE_ADDR_RI_S4x2xVL
AARCH64_OPND_SVE_ADDR_RI_S4x3xVL
AARCH64_OPND_SVE_ADDR_RI_S4x4xVL
AARCH64_OPND_SVE_ADDR_RI_S6xVL
AARCH64_OPND_SVE_ADDR_RI_S9xVL
AARCH64_OPND_SVE_ADDR_RI_U6
AARCH64_OPND_SVE_ADDR_RI_U6x2
AARCH64_OPND_SVE_ADDR_RI_U6x4
AARCH64_OPND_SVE_ADDR_RI_U6x8
AARCH64_OPND_SVE_ADDR_R
AARCH64_OPND_SVE_ADDR_RR
AARCH64_OPND_SVE_ADDR_RR_LSL1
AARCH64_OPND_SVE_ADDR_RR_LSL2
AARCH64_OPND_SVE_ADDR_RR_LSL3
AARCH64_OPND_SVE_ADDR_RX
AARCH64_OPND_SVE_ADDR_RX_LSL1
AARCH64_OPND_SVE_ADDR_RX_LSL2
AARCH64_OPND_SVE_ADDR_RX_LSL3
AARCH64_OPND_SVE_ADDR_RZ
AARCH64_OPND_SVE_ADDR_RZ_LSL1
AARCH64_OPND_SVE_ADDR_RZ_LSL2
AARCH64_OPND_SVE_ADDR_RZ_LSL3
AARCH64_OPND_SVE_ADDR_RZ_XTW_14
AARCH64_OPND_SVE_ADDR_RZ_XTW_22
AARCH64_OPND_SVE_ADDR_RZ_XTW1_14
AARCH64_OPND_SVE_ADDR_RZ_XTW1_22
AARCH64_OPND_SVE_ADDR_RZ_XTW2_14
AARCH64_OPND_SVE_ADDR_RZ_XTW2_22
AARCH64_OPND_SVE_ADDR_RZ_XTW3_14
AARCH64_OPND_SVE_ADDR_RZ_XTW3_22
AARCH64_OPND_SVE_ADDR_ZI_U5
AARCH64_OPND_SVE_ADDR_ZI_U5x2
AARCH64_OPND_SVE_ADDR_ZI_U5x4
AARCH64_OPND_SVE_ADDR_ZI_U5x8
AARCH64_OPND_SVE_ADDR_ZZ_LSL
AARCH64_OPND_SVE_ADDR_ZZ_SXTW
AARCH64_OPND_SVE_ADDR_ZZ_UXTW
AARCH64_OPND_SVE_AIMM
AARCH64_OPND_SVE_ASIMM
AARCH64_OPND_SVE_FPIMM8
AARCH64_OPND_SVE_I1_HALF_ONE
AARCH64_OPND_SVE_I1_HALF_TWO
AARCH64_OPND_SVE_I1_ZERO_ONE
AARCH64_OPND_SVE_IMM_ROT1
AARCH64_OPND_SVE_IMM_ROT2
AARCH64_OPND_SVE_INV_LIMM
AARCH64_OPND_SVE_LIMM
AARCH64_OPND_SVE_LIMM_MOV
AARCH64_OPND_SVE_PATTERN
AARCH64_OPND_SVE_PATTERN_SCALED
AARCH64_OPND_SVE_PRFOP
AARCH64_OPND_SVE_Pd
AARCH64_OPND_SVE_Pg3
AARCH64_OPND_SVE_Pg4_5
AARCH64_OPND_SVE_Pg4_10
AARCH64_OPND_SVE_Pg4_16
AARCH64_OPND_SVE_Pm
AARCH64_OPND_SVE_Pn
AARCH64_OPND_SVE_Pt
AARCH64_OPND_SVE_Rm
AARCH64_OPND_SVE_Rn_SP
AARCH64_OPND_SVE_SHLIMM_PRED
AARCH64_OPND_SVE_SHLIMM_UNPRED
AARCH64_OPND_SVE_SHRIMM_PRED
AARCH64_OPND_SVE_SHRIMM_UNPRED
AARCH64_OPND_SVE_SIMM5
AARCH64_OPND_SVE_SIMM5B
AARCH64_OPND_SVE_SIMM6
AARCH64_OPND_SVE_SIMM8
AARCH64_OPND_SVE_UIMM3
AARCH64_OPND_SVE_UIMM7
AARCH64_OPND_SVE_UIMM8
AARCH64_OPND_SVE_UIMM8_53
AARCH64_OPND_SVE_VZn
AARCH64_OPND_SVE_Vd
AARCH64_OPND_SVE_Vm
AARCH64_OPND_SVE_Vn
AARCH64_OPND_SVE_Za_5
AARCH64_OPND_SVE_Za_16
AARCH64_OPND_SVE_Zd
AARCH64_OPND_SVE_Zm_5
AARCH64_OPND_SVE_Zm_16
AARCH64_OPND_SVE_Zm3_INDEX
AARCH64_OPND_SVE_Zm3_22_INDEX
AARCH64_OPND_SVE_Zm4_INDEX
AARCH64_OPND_SVE_Zn
AARCH64_OPND_SVE_Zn_INDEX
AARCH64_OPND_SVE_ZnxN
AARCH64_OPND_SVE_Zt
AARCH64_OPND_SVE_ZtxN
AARCH64_OPND_SM3_IMM2

Definition at line 144 of file aarch64.h.

 {
   AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
  
   AARCH64_OPND_Rd,  /* Integer register as destination.  */
   AARCH64_OPND_Rn,  /* Integer register as source.  */
   AARCH64_OPND_Rm,  /* Integer register as source.  */
   AARCH64_OPND_Rt,  /* Integer register used in ld/st instructions.  */
   AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions.  */
   AARCH64_OPND_Rs,  /* Integer register used in ld/st exclusive.  */
   AARCH64_OPND_Ra,  /* Integer register used in ddp_3src instructions.  */
   AARCH64_OPND_Rt_SYS,  /* Integer register used in system instructions.  */
  
   AARCH64_OPND_Rd_SP,   /* Integer Rd or SP.  */
   AARCH64_OPND_Rn_SP,   /* Integer Rn or SP.  */
   AARCH64_OPND_Rm_SP,   /* Integer Rm or SP.  */
   AARCH64_OPND_PAIRREG, /* Paired register operand.  */
   AARCH64_OPND_Rm_EXT,  /* Integer Rm extended.  */
   AARCH64_OPND_Rm_SFT,  /* Integer Rm shifted.  */
  
   AARCH64_OPND_Fd,  /* Floating-point Fd.  */
   AARCH64_OPND_Fn,  /* Floating-point Fn.  */
   AARCH64_OPND_Fm,  /* Floating-point Fm.  */
   AARCH64_OPND_Fa,  /* Floating-point Fa.  */
   AARCH64_OPND_Ft,  /* Floating-point Ft.  */
   AARCH64_OPND_Ft2, /* Floating-point Ft2.  */
  
   AARCH64_OPND_Sd,  /* AdvSIMD Scalar Sd.  */
   AARCH64_OPND_Sn,  /* AdvSIMD Scalar Sn.  */
   AARCH64_OPND_Sm,  /* AdvSIMD Scalar Sm.  */
  
   AARCH64_OPND_Va,  /* AdvSIMD Vector Va.  */
   AARCH64_OPND_Vd,  /* AdvSIMD Vector Vd.  */
   AARCH64_OPND_Vn,  /* AdvSIMD Vector Vn.  */
   AARCH64_OPND_Vm,  /* AdvSIMD Vector Vm.  */
   AARCH64_OPND_VdD1,    /* AdvSIMD <Vd>.D[1]; for FMOV only.  */
   AARCH64_OPND_VnD1,    /* AdvSIMD <Vn>.D[1]; for FMOV only.  */
   AARCH64_OPND_Ed,  /* AdvSIMD Vector Element Vd.  */
   AARCH64_OPND_En,  /* AdvSIMD Vector Element Vn.  */
   AARCH64_OPND_Em,  /* AdvSIMD Vector Element Vm.  */
   AARCH64_OPND_Em16,    /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
                qualifier is S_H.  */
   AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL.  */
   AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st.  */
   AARCH64_OPND_LVt_AL,  /* AdvSIMD Vector register list for loading single
                structure to all lanes.  */
   AARCH64_OPND_LEt, /* AdvSIMD Vector Element list.  */
  
   AARCH64_OPND_CRn, /* Co-processor register in CRn field.  */
   AARCH64_OPND_CRm, /* Co-processor register in CRm field.  */
  
   AARCH64_OPND_IDX, /* AdvSIMD EXT index operand.  */
   AARCH64_OPND_MASK,    /* AdvSIMD EXT index operand.  */
   AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left.  */
   AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right.  */
   AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift.  */
   AARCH64_OPND_SIMD_IMM_SFT,    /* AdvSIMD modified immediate with shift.  */
   AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate.  */
   AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
                (no encoding).  */
   AARCH64_OPND_IMM0,    /* Immediate for #0.  */
   AARCH64_OPND_FPIMM0,  /* Immediate for #0.0.  */
   AARCH64_OPND_FPIMM,   /* Floating-point Immediate.  */
   AARCH64_OPND_IMMR,    /* Immediate #<immr> in e.g. BFM.  */
   AARCH64_OPND_IMMS,    /* Immediate #<imms> in e.g. BFM.  */
   AARCH64_OPND_WIDTH,   /* Immediate #<width> in e.g. BFI.  */
   AARCH64_OPND_IMM, /* Immediate.  */
   AARCH64_OPND_IMM_2,   /* Immediate.  */
   AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field.  */
   AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field.  */
   AARCH64_OPND_UIMM4,   /* Unsigned 4-bit immediate in the CRm field.  */
   AARCH64_OPND_UIMM7,   /* Unsigned 7-bit immediate in the CRm:op2 fields.  */
   AARCH64_OPND_BIT_NUM, /* Immediate.  */
   AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions.  */
   AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions.  */
   AARCH64_OPND_SIMM5,   /* 5-bit signed immediate in the imm5 field.  */
   AARCH64_OPND_NZCV,    /* Flag bit specifier giving an alternative value for
                each condition flag.  */
  
   AARCH64_OPND_LIMM,    /* Logical Immediate.  */
   AARCH64_OPND_AIMM,    /* Arithmetic immediate.  */
   AARCH64_OPND_HALF,    /* #<imm16>{, LSL #<shift>} operand in move wide.  */
   AARCH64_OPND_FBITS,   /* FP #<fbits> operand in e.g. SCVTF */
   AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias.  */
   AARCH64_OPND_IMM_ROT1,    /* Immediate rotate operand for FCMLA.  */
   AARCH64_OPND_IMM_ROT2,    /* Immediate rotate operand for indexed FCMLA.  */
   AARCH64_OPND_IMM_ROT3,    /* Immediate rotate operand for FCADD.  */
  
   AARCH64_OPND_COND,    /* Standard condition as the last operand.  */
   AARCH64_OPND_COND1,   /* Same as the above, but excluding AL and NV.  */
  
   AARCH64_OPND_ADDR_ADRP,   /* Memory address for ADRP */
   AARCH64_OPND_ADDR_PCREL14,    /* 14-bit PC-relative address for e.g. TBZ.  */
   AARCH64_OPND_ADDR_PCREL19,    /* 19-bit PC-relative address for e.g. LDR.  */
   AARCH64_OPND_ADDR_PCREL21,    /* 21-bit PC-relative address for e.g. ADR.  */
   AARCH64_OPND_ADDR_PCREL26,    /* 26-bit PC-relative address for e.g. BL.  */
  
   AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive.  */
   AARCH64_OPND_ADDR_REGOFF, /* Address of register offset.  */
   AARCH64_OPND_ADDR_SIMM7,  /* Address of signed 7-bit immediate.  */
   AARCH64_OPND_ADDR_SIMM9,  /* Address of signed 9-bit immediate.  */
   AARCH64_OPND_ADDR_SIMM9_2,    /* Same as the above, but the immediate is
                    negative or unaligned and there is
                    no writeback allowed.  This operand code
                    is only used to support the programmer-
                    friendly feature of using LDR/STR as the
                    the mnemonic name for LDUR/STUR instructions
                    wherever there is no ambiguity.  */
   AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate.  */
   AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate.  */
   AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures.  */
   AARCH64_OPND_ADDR_OFFSET,     /* Address with an optional 9-bit immediate.  */
   AARCH64_OPND_SIMD_ADDR_POST,  /* Address of ld/st multiple post-indexed.  */
  
   AARCH64_OPND_SYSREG,      /* System register operand.  */
   AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand.  */
   AARCH64_OPND_SYSREG_AT,   /* System register <at_op> operand.  */
   AARCH64_OPND_SYSREG_DC,   /* System register <dc_op> operand.  */
   AARCH64_OPND_SYSREG_IC,   /* System register <ic_op> operand.  */
   AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand.  */
   AARCH64_OPND_BARRIER,     /* Barrier operand.  */
   AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB.  */
   AARCH64_OPND_PRFOP,       /* Prefetch operation.  */
   AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB.  */
  
   AARCH64_OPND_SVE_ADDR_RI_S4x16,   /* SVE [<Xn|SP>, #<simm4>*16].  */
   AARCH64_OPND_SVE_ADDR_RI_S4xVL,   /* SVE [<Xn|SP>, #<simm4>, MUL VL].  */
   AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL].  */
   AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL].  */
   AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL].  */
   AARCH64_OPND_SVE_ADDR_RI_S6xVL,   /* SVE [<Xn|SP>, #<simm6>, MUL VL].  */
   AARCH64_OPND_SVE_ADDR_RI_S9xVL,   /* SVE [<Xn|SP>, #<simm9>, MUL VL].  */
   AARCH64_OPND_SVE_ADDR_RI_U6,      /* SVE [<Xn|SP>, #<uimm6>].  */
   AARCH64_OPND_SVE_ADDR_RI_U6x2,    /* SVE [<Xn|SP>, #<uimm6>*2].  */
   AARCH64_OPND_SVE_ADDR_RI_U6x4,    /* SVE [<Xn|SP>, #<uimm6>*4].  */
   AARCH64_OPND_SVE_ADDR_RI_U6x8,    /* SVE [<Xn|SP>, #<uimm6>*8].  */
   AARCH64_OPND_SVE_ADDR_R,      /* SVE [<Xn|SP>].  */
   AARCH64_OPND_SVE_ADDR_RR,     /* SVE [<Xn|SP>, <Xm|XZR>].  */
   AARCH64_OPND_SVE_ADDR_RR_LSL1,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1].  */
   AARCH64_OPND_SVE_ADDR_RR_LSL2,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2].  */
   AARCH64_OPND_SVE_ADDR_RR_LSL3,    /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3].  */
   AARCH64_OPND_SVE_ADDR_RX,     /* SVE [<Xn|SP>, <Xm>].  */
   AARCH64_OPND_SVE_ADDR_RX_LSL1,    /* SVE [<Xn|SP>, <Xm>, LSL #1].  */
   AARCH64_OPND_SVE_ADDR_RX_LSL2,    /* SVE [<Xn|SP>, <Xm>, LSL #2].  */
   AARCH64_OPND_SVE_ADDR_RX_LSL3,    /* SVE [<Xn|SP>, <Xm>, LSL #3].  */
   AARCH64_OPND_SVE_ADDR_RZ,     /* SVE [<Xn|SP>, Zm.D].  */
   AARCH64_OPND_SVE_ADDR_RZ_LSL1,    /* SVE [<Xn|SP>, Zm.D, LSL #1].  */
   AARCH64_OPND_SVE_ADDR_RZ_LSL2,    /* SVE [<Xn|SP>, Zm.D, LSL #2].  */
   AARCH64_OPND_SVE_ADDR_RZ_LSL3,    /* SVE [<Xn|SP>, Zm.D, LSL #3].  */
   AARCH64_OPND_SVE_ADDR_RZ_XTW_14,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
                        Bit 14 controls S/U choice.  */
   AARCH64_OPND_SVE_ADDR_RZ_XTW_22,  /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
                        Bit 22 controls S/U choice.  */
   AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
                        Bit 14 controls S/U choice.  */
   AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
                        Bit 22 controls S/U choice.  */
   AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
                        Bit 14 controls S/U choice.  */
   AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
                        Bit 22 controls S/U choice.  */
   AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
                        Bit 14 controls S/U choice.  */
   AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
                        Bit 22 controls S/U choice.  */
   AARCH64_OPND_SVE_ADDR_ZI_U5,      /* SVE [Zn.<T>, #<uimm5>].  */
   AARCH64_OPND_SVE_ADDR_ZI_U5x2,    /* SVE [Zn.<T>, #<uimm5>*2].  */
   AARCH64_OPND_SVE_ADDR_ZI_U5x4,    /* SVE [Zn.<T>, #<uimm5>*4].  */
   AARCH64_OPND_SVE_ADDR_ZI_U5x8,    /* SVE [Zn.<T>, #<uimm5>*8].  */
   AARCH64_OPND_SVE_ADDR_ZZ_LSL,     /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>].  */
   AARCH64_OPND_SVE_ADDR_ZZ_SXTW,    /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>].  */
   AARCH64_OPND_SVE_ADDR_ZZ_UXTW,    /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>].  */
   AARCH64_OPND_SVE_AIMM,    /* SVE unsigned arithmetic immediate.  */
   AARCH64_OPND_SVE_ASIMM,   /* SVE signed arithmetic immediate.  */
   AARCH64_OPND_SVE_FPIMM8,  /* SVE 8-bit floating-point immediate.  */
   AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0.  */
   AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0.  */
   AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0.  */
   AARCH64_OPND_SVE_IMM_ROT1,    /* SVE 1-bit rotate operand (90 or 270).  */
   AARCH64_OPND_SVE_IMM_ROT2,    /* SVE 2-bit rotate operand (N*90).  */
   AARCH64_OPND_SVE_INV_LIMM,    /* SVE inverted logical immediate.  */
   AARCH64_OPND_SVE_LIMM,    /* SVE logical immediate.  */
   AARCH64_OPND_SVE_LIMM_MOV,    /* SVE logical immediate for MOV.  */
   AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration.  */
   AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor.  */
   AARCH64_OPND_SVE_PRFOP,   /* SVE prefetch operation.  */
   AARCH64_OPND_SVE_Pd,      /* SVE p0-p15 in Pd.  */
   AARCH64_OPND_SVE_Pg3,     /* SVE p0-p7 in Pg.  */
   AARCH64_OPND_SVE_Pg4_5,   /* SVE p0-p15 in Pg, bits [8,5].  */
   AARCH64_OPND_SVE_Pg4_10,  /* SVE p0-p15 in Pg, bits [13,10].  */
   AARCH64_OPND_SVE_Pg4_16,  /* SVE p0-p15 in Pg, bits [19,16].  */
   AARCH64_OPND_SVE_Pm,      /* SVE p0-p15 in Pm.  */
   AARCH64_OPND_SVE_Pn,      /* SVE p0-p15 in Pn.  */
   AARCH64_OPND_SVE_Pt,      /* SVE p0-p15 in Pt.  */
   AARCH64_OPND_SVE_Rm,      /* Integer Rm or ZR, alt. SVE position.  */
   AARCH64_OPND_SVE_Rn_SP,   /* Integer Rn or SP, alt. SVE position.  */
   AARCH64_OPND_SVE_SHLIMM_PRED,   /* SVE shift left amount (predicated).  */
   AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated).  */
   AARCH64_OPND_SVE_SHRIMM_PRED,   /* SVE shift right amount (predicated).  */
   AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated).  */
   AARCH64_OPND_SVE_SIMM5,   /* SVE signed 5-bit immediate.  */
   AARCH64_OPND_SVE_SIMM5B,  /* SVE secondary signed 5-bit immediate.  */
   AARCH64_OPND_SVE_SIMM6,   /* SVE signed 6-bit immediate.  */
   AARCH64_OPND_SVE_SIMM8,   /* SVE signed 8-bit immediate.  */
   AARCH64_OPND_SVE_UIMM3,   /* SVE unsigned 3-bit immediate.  */
   AARCH64_OPND_SVE_UIMM7,   /* SVE unsigned 7-bit immediate.  */
   AARCH64_OPND_SVE_UIMM8,   /* SVE unsigned 8-bit immediate.  */
   AARCH64_OPND_SVE_UIMM8_53,    /* SVE split unsigned 8-bit immediate.  */
   AARCH64_OPND_SVE_VZn,     /* Scalar SIMD&FP register in Zn field.  */
   AARCH64_OPND_SVE_Vd,      /* Scalar SIMD&FP register in Vd.  */
   AARCH64_OPND_SVE_Vm,      /* Scalar SIMD&FP register in Vm.  */
   AARCH64_OPND_SVE_Vn,      /* Scalar SIMD&FP register in Vn.  */
   AARCH64_OPND_SVE_Za_5,    /* SVE vector register in Za, bits [9,5].  */
   AARCH64_OPND_SVE_Za_16,   /* SVE vector register in Za, bits [20,16].  */
   AARCH64_OPND_SVE_Zd,      /* SVE vector register in Zd.  */
   AARCH64_OPND_SVE_Zm_5,    /* SVE vector register in Zm, bits [9,5].  */
   AARCH64_OPND_SVE_Zm_16,   /* SVE vector register in Zm, bits [20,16].  */
   AARCH64_OPND_SVE_Zm3_INDEX,   /* z0-z7[0-3] in Zm, bits [20,16].  */
   AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22.  */
   AARCH64_OPND_SVE_Zm4_INDEX,   /* z0-z15[0-1] in Zm, bits [20,16].  */
   AARCH64_OPND_SVE_Zn,      /* SVE vector register in Zn.  */
   AARCH64_OPND_SVE_Zn_INDEX,    /* Indexed SVE vector register, for DUP.  */
   AARCH64_OPND_SVE_ZnxN,    /* SVE vector register list in Zn.  */
   AARCH64_OPND_SVE_Zt,      /* SVE vector register in Zt.  */
   AARCH64_OPND_SVE_ZtxN,    /* SVE vector register list in Zt.  */
   AARCH64_OPND_SM3_IMM2,    /* SM3 encodes lane in bits [13, 14].  */
 };

◆ aarch64_opnd_qualifier

enum aarch64_opnd_qualifier

Enumerator
AARCH64_OPND_QLF_NIL
AARCH64_OPND_QLF_W
AARCH64_OPND_QLF_X
AARCH64_OPND_QLF_WSP
AARCH64_OPND_QLF_SP
AARCH64_OPND_QLF_S_B
AARCH64_OPND_QLF_S_H
AARCH64_OPND_QLF_S_S
AARCH64_OPND_QLF_S_D
AARCH64_OPND_QLF_S_Q
AARCH64_OPND_QLF_S_4B
AARCH64_OPND_QLF_V_4B
AARCH64_OPND_QLF_V_8B
AARCH64_OPND_QLF_V_16B
AARCH64_OPND_QLF_V_2H
AARCH64_OPND_QLF_V_4H
AARCH64_OPND_QLF_V_8H
AARCH64_OPND_QLF_V_2S
AARCH64_OPND_QLF_V_4S
AARCH64_OPND_QLF_V_1D
AARCH64_OPND_QLF_V_2D
AARCH64_OPND_QLF_V_1Q
AARCH64_OPND_QLF_P_Z
AARCH64_OPND_QLF_P_M
AARCH64_OPND_QLF_CR
AARCH64_OPND_QLF_imm_0_7
AARCH64_OPND_QLF_imm_0_15
AARCH64_OPND_QLF_imm_0_31
AARCH64_OPND_QLF_imm_0_63
AARCH64_OPND_QLF_imm_1_32
AARCH64_OPND_QLF_imm_1_64
AARCH64_OPND_QLF_LSL
AARCH64_OPND_QLF_MSL
AARCH64_OPND_QLF_RETRIEVE

Definition at line 377 of file aarch64.h.

 {
   /* Indicating no further qualification on an operand.  */
   AARCH64_OPND_QLF_NIL,
  
   /* Qualifying an operand which is a general purpose (integer) register;
      indicating the operand data size or a specific register.  */
   AARCH64_OPND_QLF_W,   /* Wn, WZR or WSP.  */
   AARCH64_OPND_QLF_X,   /* Xn, XZR or XSP.  */
   AARCH64_OPND_QLF_WSP, /* WSP.  */
   AARCH64_OPND_QLF_SP,  /* SP.  */
  
   /* Qualifying an operand which is a floating-point register, a SIMD
      vector element or a SIMD vector element list; indicating operand data
      size or the size of each SIMD vector element in the case of a SIMD
      vector element list.
      These qualifiers are also used to qualify an address operand to
      indicate the size of data element a load/store instruction is
      accessing.
      They are also used for the immediate shift operand in e.g. SSHR.  Such
      a use is only for the ease of operand encoding/decoding and qualifier
      sequence matching; such a use should not be applied widely; use the value
      constraint qualifiers for immediate operands wherever possible.  */
   AARCH64_OPND_QLF_S_B,
   AARCH64_OPND_QLF_S_H,
   AARCH64_OPND_QLF_S_S,
   AARCH64_OPND_QLF_S_D,
   AARCH64_OPND_QLF_S_Q,
   /* This type qualifier has a special meaning in that it means that 4 x 1 byte
      are selected by the instruction.  Other than that it has no difference
      with AARCH64_OPND_QLF_S_B in encoding.  It is here purely for syntactical
      reasons and is an exception from normal AArch64 disassembly scheme.  */
   AARCH64_OPND_QLF_S_4B,
  
   /* Qualifying an operand which is a SIMD vector register or a SIMD vector
      register list; indicating register shape.
      They are also used for the immediate shift operand in e.g. SSHR.  Such
      a use is only for the ease of operand encoding/decoding and qualifier
      sequence matching; such a use should not be applied widely; use the value
      constraint qualifiers for immediate operands wherever possible.  */
   AARCH64_OPND_QLF_V_4B,
   AARCH64_OPND_QLF_V_8B,
   AARCH64_OPND_QLF_V_16B,
   AARCH64_OPND_QLF_V_2H,
   AARCH64_OPND_QLF_V_4H,
   AARCH64_OPND_QLF_V_8H,
   AARCH64_OPND_QLF_V_2S,
   AARCH64_OPND_QLF_V_4S,
   AARCH64_OPND_QLF_V_1D,
   AARCH64_OPND_QLF_V_2D,
   AARCH64_OPND_QLF_V_1Q,
  
   AARCH64_OPND_QLF_P_Z,
   AARCH64_OPND_QLF_P_M,
  
   /* Constraint on value.  */
   AARCH64_OPND_QLF_CR,      /* CRn, CRm. */
   AARCH64_OPND_QLF_imm_0_7,
   AARCH64_OPND_QLF_imm_0_15,
   AARCH64_OPND_QLF_imm_0_31,
   AARCH64_OPND_QLF_imm_0_63,
   AARCH64_OPND_QLF_imm_1_32,
   AARCH64_OPND_QLF_imm_1_64,
  
   /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
      or shift-ones.  */
   AARCH64_OPND_QLF_LSL,
   AARCH64_OPND_QLF_MSL,
  
   /* Special qualifier helping retrieve qualifier information during the
      decoding time (currently not in use).  */
   AARCH64_OPND_QLF_RETRIEVE,
 };

Function Documentation

◆ aarch64_decode_insn()

int aarch64_decode_insn	(	aarch64_insn	insn,
		aarch64_inst *	inst,
		bfd_boolean	noaliases_p,
		aarch64_operand_error *	errors
	)

Definition at line 2958 of file aarch64-dis.c.

 {
   const aarch64_opcode *opcode = aarch64_opcode_lookup (insn);
  
 #ifdef DEBUG_AARCH64
   if (debug_dump)
     {
       const aarch64_opcode *tmp = opcode;
       printf ("\n");
       DEBUG_TRACE ("opcode lookup:");
       while (tmp != NULL)
     {
       aarch64_verbose ("  %s", tmp->name);
       tmp = aarch64_find_next_opcode (tmp);
     }
     }
 #endif /* DEBUG_AARCH64 */
  
   /* A list of opcodes may have been found, as aarch64_opcode_lookup cannot
      distinguish some opcodes, e.g. SSHR and MOVI, which almost share the same
      opcode field and value, apart from the difference that one of them has an
      extra field as part of the opcode, but such a field is used for operand
      encoding in other opcode(s) ('immh' in the case of the example).  */
   while (opcode != NULL)
     {
       /* But only one opcode can be decoded successfully for, as the
      decoding routine will check the constraint carefully.  */
       if (aarch64_opcode_decode (opcode, insn, inst, noaliases_p, errors) == 1)
     return ERR_OK;
       opcode = aarch64_find_next_opcode (opcode);
     }
  
   return ERR_UND;
 }

References aarch64_find_next_opcode(), aarch64_opcode_decode(), aarch64_opcode_lookup(), DEBUG_TRACE, ERR_OK, ERR_UND, NULL, printf(), and autogen_x86imm::tmp.

Referenced by print_insn_aarch64_word().

◆ aarch64_extend_operator_p()

bfd_boolean aarch64_extend_operator_p ( enum aarch64_modifier_kind )

Definition at line 430 of file aarch64-opc.c.

 {
   return (kind > AARCH64_MOD_LSL && kind <= AARCH64_MOD_SXTX)
     ? TRUE : FALSE;
 }

References AARCH64_MOD_LSL, AARCH64_MOD_SXTX, FALSE, and TRUE.

Referenced by operand_general_constraint_met_p().

◆ aarch64_get_expected_qualifier()

aarch64_opnd_qualifier_t aarch64_get_expected_qualifier	(	const aarch64_opnd_qualifier_seq_t *	qseq_list,
		int	idx,
		const	aarch64_opnd_qualifier_t,
		int	known_idx
	)

Definition at line 621 of file aarch64-opc.c.

 {
   int i, saved_i;
  
   /* Special case.
  
      When the known qualifier is NIL, we have to assume that there is only
      one qualifier sequence in the *QSEQ_LIST and return the corresponding
      qualifier directly.  One scenario is that for instruction
     PRFM <prfop>, [<Xn|SP>, #:lo12:<symbol>]
      which has only one possible valid qualifier sequence
     NIL, S_D
      the caller may pass NIL in KNOWN_QLF to obtain S_D so that it can
      determine the correct relocation type (i.e. LDST64_LO12) for PRFM.
  
      Because the qualifier NIL has dual roles in the qualifier sequence:
      it can mean no qualifier for the operand, or the qualifer sequence is
      not in use (when all qualifiers in the sequence are NILs), we have to
      handle this special case here.  */
   if (known_qlf == AARCH64_OPND_NIL)
     {
       assert (qseq_list[0][known_idx] == AARCH64_OPND_NIL);
       return qseq_list[0][idx];
     }
  
   for (i = 0, saved_i = -1; i < AARCH64_MAX_QLF_SEQ_NUM; i++)
     {
       if (qseq_list[i][known_idx] == known_qlf)
     {
       if (saved_i != -1)
         /* More than one sequences are found to have KNOWN_QLF at
            KNOWN_IDX.  */
         return AARCH64_OPND_NIL;
       saved_i = i;
     }
     }
  
   return qseq_list[saved_i][idx];
 }

References AARCH64_MAX_QLF_SEQ_NUM, AARCH64_OPND_NIL, assert(), i, and setup::idx.

◆ aarch64_get_opcode()

const aarch64_opcode* aarch64_get_opcode ( enum aarch64_op )

Definition at line 318 of file aarch64-opc-2.c.

 {
   return aarch64_opcode_table + op_enum_table[op];
 }

References aarch64_opcode_table, op, and op_enum_table.

◆ aarch64_get_operand_class()

enum aarch64_operand_class aarch64_get_operand_class ( enum aarch64_opnd )

Definition at line 205 of file aarch64-opc.c.

 {
   return aarch64_operands[type].op_class;
 }

Referenced by aarch64_ext_regrt_sysins(), aarch64_stack_pointer_p(), aarch64_zero_register_p(), do_special_decoding(), operand_general_constraint_met_p(), select_operand_for_fptype_field_coding(), select_operand_for_scalar_size_field_coding(), and select_operand_for_sf_field_coding().

◆ aarch64_get_operand_desc()

const char* aarch64_get_operand_desc ( enum aarch64_opnd )

Definition at line 342 of file aarch64-opc.c.

 {
   return aarch64_operands[type].desc;
 }

References aarch64_operands, aarch64_operand::desc, and type.

◆ aarch64_get_operand_modifier()

enum aarch64_modifier_kind aarch64_get_operand_modifier ( const struct aarch64_name_value_pair * desc )

Definition at line 376 of file aarch64-opc.c.

 {
   return desc - aarch64_operand_modifiers;
 }

References aarch64_conds, and cond.

◆ aarch64_get_operand_name()

const char* aarch64_get_operand_name ( enum aarch64_opnd )

Definition at line 334 of file aarch64-opc.c.

 {
   return aarch64_operands[type].name;
 }

References aarch64_operands, aarch64_operand::name, and type.

◆ aarch64_get_qualifier_esize()

unsigned char aarch64_get_qualifier_esize ( aarch64_opnd_qualifier_t qualifier )

Definition at line 766 of file aarch64-opc.c.

 {
   assert (operand_variant_qualifier_p (qualifier) == TRUE);
   return aarch64_opnd_qualifiers[qualifier].data0;
 }

References aarch64_opnd_qualifiers, assert(), operand_qualifier_data::data0, operand_variant_qualifier_p(), and TRUE.

Referenced by aarch64_ext_addr_regoff(), aarch64_ext_addr_simm(), aarch64_ext_addr_uimm12(), aarch64_ext_advsimd_imm_modified(), aarch64_ext_limm(), aarch64_ext_reglane(), aarch64_ext_simd_addr_post(), aarch64_ext_sve_limm_mov(), aarch64_print_operand(), get_int_reg_name(), operand_general_constraint_met_p(), and select_operand_for_scalar_size_field_coding().

◆ aarch64_num_of_operands()

int aarch64_num_of_operands ( const aarch64_opcode * opcode )

Definition at line 842 of file aarch64-opc.c.

 {
   int i = 0;
   const enum aarch64_opnd *opnds = opcode->operands;
   while (opnds[i++] != AARCH64_OPND_NIL)
     ;
   --i;
   assert (i >= 0 && i <= AARCH64_MAX_OPND_NUM);
   return i;
 }

References AARCH64_MAX_OPND_NUM, AARCH64_OPND_NIL, assert(), i, and aarch64_opcode::operands.

Referenced by aarch64_find_best_match(), determine_disassembling_preference(), and match_operands_qualifier().

◆ aarch64_opcode_encode()

int aarch64_opcode_encode	(	const aarch64_opcode *	,
		const aarch64_inst *	,
		aarch64_insn *	,
		aarch64_opnd_qualifier_t *	,
		aarch64_operand_error *
	)

◆ aarch64_operand_index()

int aarch64_operand_index	(	const enum aarch64_opnd *	operands,
		enum	aarch64_opnd
	)

Definition at line 2736 of file aarch64-opc.c.

 {
   int i;
   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
     if (operands[i] == operand)
       return i;
     else if (operands[i] == AARCH64_OPND_NIL)
       break;
   return -1;
 }

References AARCH64_MAX_OPND_NUM, AARCH64_OPND_NIL, and i.

Referenced by do_special_decoding().

◆ aarch64_print_operand()

void aarch64_print_operand	(	char *	,
		size_t	,
		bfd_vma	,
		const aarch64_opcode *	,
		const aarch64_opnd_info *	,
		int	,
		int *	,
		bfd_vma *	,
		char **
	)

◆ aarch64_pstatefield_supported_p()

bfd_boolean aarch64_pstatefield_supported_p	(	const	aarch64_feature_set,
		const aarch64_sys_reg *	reg
	)

Definition at line 4293 of file aarch64-opc.c.

 {
   if (!(reg->flags & F_ARCHEXT))
     return TRUE;
  
   /* PAN.  Values are from aarch64_pstatefields.  */
   if (reg->value == 0x04
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
     return FALSE;
  
   /* UAO.  Values are from aarch64_pstatefields.  */
   if (reg->value == 0x03
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
     return FALSE;
  
   /* DIT.  Values are from aarch64_pstatefields.  */
   if (reg->value == 0x1a
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
     return FALSE;
  
   return TRUE;
 }

References AARCH64_CPU_HAS_FEATURE, AARCH64_FEATURE_PAN, AARCH64_FEATURE_V8_2, AARCH64_FEATURE_V8_4, F_ARCHEXT, FALSE, features, reg, and TRUE.

◆ aarch64_replace_opcode()

const aarch64_opcode* aarch64_replace_opcode	(	struct aarch64_inst *	inst,
		const aarch64_opcode *	opcode
	)

Definition at line 2715 of file aarch64-opc.c.

 {
   int i;
   const aarch64_opcode *old = inst->opcode;
  
   inst->opcode = opcode;
  
   /* Update the operand types.  */
   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
     {
       inst->operands[i].type = opcode->operands[i];
       if (opcode->operands[i] == AARCH64_OPND_NIL)
     break;
     }
  
   DEBUG_TRACE ("replace %s with %s", old->name, opcode->name);
  
   return old;
 }

References AARCH64_MAX_OPND_NUM, AARCH64_OPND_NIL, DEBUG_TRACE, i, aarch64_opcode::name, aarch64_inst::opcode, aarch64_opcode::operands, aarch64_inst::operands, and aarch64_opnd_info::type.

Referenced by determine_disassembling_preference().

◆ aarch64_stack_pointer_p()

int aarch64_stack_pointer_p ( const aarch64_opnd_info * operand )

Definition at line 562 of file aarch64-opc.c.

 {
   return ((aarch64_get_operand_class (operand->type)
        == AARCH64_OPND_CLASS_INT_REG)
       && operand_maybe_stack_pointer (aarch64_operands + operand->type)
       && operand->reg.regno == 31);
 }

References aarch64_get_operand_class(), aarch64_operands, AARCH64_OPND_CLASS_INT_REG, and operand_maybe_stack_pointer().

Referenced by aarch64_print_operand(), operand_also_qualified_p(), and operand_general_constraint_met_p().

◆ aarch64_sve_dupm_mov_immediate_p()

bfd_boolean aarch64_sve_dupm_mov_immediate_p	(	uint64_t	uvalue,
		int	esize
	)

Definition at line 4521 of file aarch64-opc.c.

 {
   int64_t svalue = uvalue;
   uint64_t upper = (uint64_t) -1 << (esize * 4) << (esize * 4);
  
   if ((uvalue & ~upper) != uvalue && (uvalue | upper) != uvalue)
     return FALSE;
   if (esize <= 4 || (uint32_t) uvalue == (uint32_t) (uvalue >> 32))
     {
       svalue = (int32_t) uvalue;
       if (esize <= 2 || (uint16_t) uvalue == (uint16_t) (uvalue >> 16))
     {
       svalue = (int16_t) uvalue;
       if (esize == 1 || (uint8_t) uvalue == (uint8_t) (uvalue >> 8))
         return FALSE;
     }
     }
   if ((svalue & 0xff) == 0)
     svalue /= 256;
   return svalue < -128 || svalue >= 128;
 }

References FALSE.

Referenced by aarch64_ext_sve_limm_mov(), and operand_general_constraint_met_p().

◆ aarch64_sys_ins_reg_has_xt()

bfd_boolean aarch64_sys_ins_reg_has_xt ( const aarch64_sys_ins_reg * sys_ins_reg )

Definition at line 4445 of file aarch64-opc.c.

 {
   return (sys_ins_reg->flags & F_HASXT) != 0;
 }

References F_HASXT, and aarch64_sys_ins_reg::flags.

Referenced by aarch64_ext_regrt_sysins(), aarch64_ext_sysins_op(), and operand_general_constraint_met_p().

◆ aarch64_sys_ins_reg_supported_p()

bfd_boolean aarch64_sys_ins_reg_supported_p	(	const	aarch64_feature_set,
		const aarch64_sys_ins_reg *	reg
	)

Definition at line 4451 of file aarch64-opc.c.

 {
   if (!(reg->flags & F_ARCHEXT))
     return TRUE;
  
   /* DC CVAP.  Values are from aarch64_sys_regs_dc.  */
   if (reg->value == CPENS (3, C7, C12, 1)
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
     return FALSE;
  
   /* AT S1E1RP, AT S1E1WP.  Values are from aarch64_sys_regs_at.  */
   if ((reg->value == CPENS (0, C7, C9, 0)
        || reg->value == CPENS (0, C7, C9, 1))
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
     return FALSE;
  
   return TRUE;
 }

References AARCH64_CPU_HAS_FEATURE, AARCH64_FEATURE_V8_2, C12, C7, C9, CPENS, F_ARCHEXT, FALSE, features, reg, and TRUE.

◆ aarch64_sys_reg_deprecated_p()

bfd_boolean aarch64_sys_reg_deprecated_p ( const aarch64_sys_reg * reg )

Definition at line 4067 of file aarch64-opc.c.

 {
   return (reg->flags & F_DEPRECATED) != 0;
 }

References F_DEPRECATED, and reg.

Referenced by aarch64_print_operand().

◆ aarch64_sys_reg_supported_p()

bfd_boolean aarch64_sys_reg_supported_p	(	const	aarch64_feature_set,
		const aarch64_sys_reg *	reg
	)

Definition at line 4073 of file aarch64-opc.c.

 {
   if (!(reg->flags & F_ARCHEXT))
     return TRUE;
  
   /* PAN.  Values are from aarch64_sys_regs.  */
   if (reg->value == CPEN_(0,C2,3)
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
     return FALSE;
  
   /* Virtualization host extensions: system registers.  */
   if ((reg->value == CPENC (3, 4, C2, C0, 1)
        || reg->value == CPENC (3, 4, C13, C0, 1)
        || reg->value == CPENC (3, 4, C14, C3, 0)
        || reg->value == CPENC (3, 4, C14, C3, 1)
        || reg->value == CPENC (3, 4, C14, C3, 2))
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
       return FALSE;
  
   /* Virtualization host extensions: *_el12 names of *_el1 registers.  */
   if ((reg->value == CPEN_ (5, C0, 0)
        || reg->value == CPEN_ (5, C0, 1)
        || reg->value == CPENC (3, 5, C1, C0, 0)
        || reg->value == CPENC (3, 5, C1, C0, 2)
        || reg->value == CPENC (3, 5, C2, C0, 0)
        || reg->value == CPENC (3, 5, C2, C0, 1)
        || reg->value == CPENC (3, 5, C2, C0, 2)
        || reg->value == CPENC (3, 5, C5, C1, 0)
        || reg->value == CPENC (3, 5, C5, C1, 1)
        || reg->value == CPENC (3, 5, C5, C2, 0)
        || reg->value == CPENC (3, 5, C6, C0, 0)
        || reg->value == CPENC (3, 5, C10, C2, 0)
        || reg->value == CPENC (3, 5, C10, C3, 0)
        || reg->value == CPENC (3, 5, C12, C0, 0)
        || reg->value == CPENC (3, 5, C13, C0, 1)
        || reg->value == CPENC (3, 5, C14, C1, 0))
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
     return FALSE;
  
   /* Virtualization host extensions: *_el02 names of *_el0 registers.  */
   if ((reg->value == CPENC (3, 5, C14, C2, 0)
        || reg->value == CPENC (3, 5, C14, C2, 1)
        || reg->value == CPENC (3, 5, C14, C2, 2)
        || reg->value == CPENC (3, 5, C14, C3, 0)
        || reg->value == CPENC (3, 5, C14, C3, 1)
        || reg->value == CPENC (3, 5, C14, C3, 2))
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
     return FALSE;
  
   /* ARMv8.2 features.  */
  
   /* ID_AA64MMFR2_EL1.  */
   if (reg->value == CPENC (3, 0, C0, C7, 2)
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
     return FALSE;
  
   /* PSTATE.UAO.  */
   if (reg->value == CPEN_ (0, C2, 4)
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
     return FALSE;
  
   /* RAS extension.  */
  
   /* ERRIDR_EL1, ERRSELR_EL1, ERXFR_EL1, ERXCTLR_EL1, ERXSTATUS_EL, ERXADDR_EL1,
      ERXMISC0_EL1 AND ERXMISC1_EL1.  */
   if ((reg->value == CPENC (3, 0, C5, C3, 0)
        || reg->value == CPENC (3, 0, C5, C3, 1)
        || reg->value == CPENC (3, 0, C5, C3, 2)
        || reg->value == CPENC (3, 0, C5, C3, 3)
        || reg->value == CPENC (3, 0, C5, C4, 0)
        || reg->value == CPENC (3, 0, C5, C4, 1)
        || reg->value == CPENC (3, 0, C5, C4, 2)
        || reg->value == CPENC (3, 0, C5, C4, 3)
        || reg->value == CPENC (3, 0, C5, C5, 0)
        || reg->value == CPENC (3, 0, C5, C5, 1))
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
     return FALSE;
  
   /* VSESR_EL2, DISR_EL1 and VDISR_EL2.  */
   if ((reg->value == CPENC (3, 4, C5, C2, 3)
        || reg->value == CPENC (3, 0, C12, C1, 1)
        || reg->value == CPENC (3, 4, C12, C1, 1))
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
     return FALSE;
  
   /* Statistical Profiling extension.  */
   if ((reg->value == CPENC (3, 0, C9, C10, 0)
        || reg->value == CPENC (3, 0, C9, C10, 1)
        || reg->value == CPENC (3, 0, C9, C10, 3)
        || reg->value == CPENC (3, 0, C9, C10, 7)
        || reg->value == CPENC (3, 0, C9, C9, 0)
        || reg->value == CPENC (3, 0, C9, C9, 2)
        || reg->value == CPENC (3, 0, C9, C9, 3)
        || reg->value == CPENC (3, 0, C9, C9, 4)
        || reg->value == CPENC (3, 0, C9, C9, 5)
        || reg->value == CPENC (3, 0, C9, C9, 6)
        || reg->value == CPENC (3, 0, C9, C9, 7)
        || reg->value == CPENC (3, 4, C9, C9, 0)
        || reg->value == CPENC (3, 5, C9, C9, 0))
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PROFILE))
     return FALSE;
  
   /* ARMv8.3 Pointer authentication keys.  */
   if ((reg->value == CPENC (3, 0, C2, C1, 0)
        || reg->value == CPENC (3, 0, C2, C1, 1)
        || reg->value == CPENC (3, 0, C2, C1, 2)
        || reg->value == CPENC (3, 0, C2, C1, 3)
        || reg->value == CPENC (3, 0, C2, C2, 0)
        || reg->value == CPENC (3, 0, C2, C2, 1)
        || reg->value == CPENC (3, 0, C2, C2, 2)
        || reg->value == CPENC (3, 0, C2, C2, 3)
        || reg->value == CPENC (3, 0, C2, C3, 0)
        || reg->value == CPENC (3, 0, C2, C3, 1))
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_3))
     return FALSE;
  
   /* SVE.  */
   if ((reg->value == CPENC (3, 0, C0, C4, 4)
        || reg->value == CPENC (3, 0, C1, C2, 0)
        || reg->value == CPENC (3, 4, C1, C2, 0)
        || reg->value == CPENC (3, 6, C1, C2, 0)
        || reg->value == CPENC (3, 5, C1, C2, 0)
        || reg->value == CPENC (3, 0, C0, C0, 7))
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SVE))
     return FALSE;
  
   /* ARMv8.4 features.  */
  
   /* PSTATE.DIT.  */
   if (reg->value == CPEN_ (3, C2, 5)
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
     return FALSE;
  
   /* Virtualization extensions.  */
   if ((reg->value == CPENC(3, 4, C2, C6, 2)
        || reg->value == CPENC(3, 4, C2, C6, 0)
        || reg->value == CPENC(3, 4, C14, C4, 0)
        || reg->value == CPENC(3, 4, C14, C4, 2)
        || reg->value == CPENC(3, 4, C14, C4, 1)
        || reg->value == CPENC(3, 4, C14, C5, 0)
        || reg->value == CPENC(3, 4, C14, C5, 2)
        || reg->value == CPENC(3, 4, C14, C5, 1)
        || reg->value == CPENC(3, 4, C1, C3, 1)
        || reg->value == CPENC(3, 4, C2, C2, 0))
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
     return FALSE;
  
   /* ARMv8.4 TLB instructions.  */
   if ((reg->value == CPENS (0, C8, C1, 0)
        || reg->value == CPENS (0, C8, C1, 1)
        || reg->value == CPENS (0, C8, C1, 2)
        || reg->value == CPENS (0, C8, C1, 3)
        || reg->value == CPENS (0, C8, C1, 5)
        || reg->value == CPENS (0, C8, C1, 7)
        || reg->value == CPENS (4, C8, C4, 0)
        || reg->value == CPENS (4, C8, C4, 4)
        || reg->value == CPENS (4, C8, C1, 1)
        || reg->value == CPENS (4, C8, C1, 5)
        || reg->value == CPENS (4, C8, C1, 6)
        || reg->value == CPENS (6, C8, C1, 1)
        || reg->value == CPENS (6, C8, C1, 5)
        || reg->value == CPENS (4, C8, C1, 0)
        || reg->value == CPENS (4, C8, C1, 4)
        || reg->value == CPENS (6, C8, C1, 0)
        || reg->value == CPENS (0, C8, C6, 1)
        || reg->value == CPENS (0, C8, C6, 3)
        || reg->value == CPENS (0, C8, C6, 5)
        || reg->value == CPENS (0, C8, C6, 7)
        || reg->value == CPENS (0, C8, C2, 1)
        || reg->value == CPENS (0, C8, C2, 3)
        || reg->value == CPENS (0, C8, C2, 5)
        || reg->value == CPENS (0, C8, C2, 7)
        || reg->value == CPENS (0, C8, C5, 1)
        || reg->value == CPENS (0, C8, C5, 3)
        || reg->value == CPENS (0, C8, C5, 5)
        || reg->value == CPENS (0, C8, C5, 7)
        || reg->value == CPENS (4, C8, C0, 2)
        || reg->value == CPENS (4, C8, C0, 6)
        || reg->value == CPENS (4, C8, C4, 2)
        || reg->value == CPENS (4, C8, C4, 6)
        || reg->value == CPENS (4, C8, C4, 3)
        || reg->value == CPENS (4, C8, C4, 7)
        || reg->value == CPENS (4, C8, C6, 1)
        || reg->value == CPENS (4, C8, C6, 5)
        || reg->value == CPENS (4, C8, C2, 1)
        || reg->value == CPENS (4, C8, C2, 5)
        || reg->value == CPENS (4, C8, C5, 1)
        || reg->value == CPENS (4, C8, C5, 5)
        || reg->value == CPENS (6, C8, C6, 1)
        || reg->value == CPENS (6, C8, C6, 5)
        || reg->value == CPENS (6, C8, C2, 1)
        || reg->value == CPENS (6, C8, C2, 5)
        || reg->value == CPENS (6, C8, C5, 1)
        || reg->value == CPENS (6, C8, C5, 5))
       && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
     return FALSE;
  
   return TRUE;
 }

References AARCH64_CPU_HAS_FEATURE, AARCH64_FEATURE_PAN, AARCH64_FEATURE_PROFILE, AARCH64_FEATURE_RAS, AARCH64_FEATURE_SVE, AARCH64_FEATURE_V8_1, AARCH64_FEATURE_V8_2, AARCH64_FEATURE_V8_3, AARCH64_FEATURE_V8_4, C0, C1, C10, C12, C13, C14, C2, C3, C4, C5, C6, C7, C8, C9, CPEN_, CPENC, CPENS, F_ARCHEXT, FALSE, features, reg, and TRUE.

◆ aarch64_zero_register_p()

int aarch64_zero_register_p ( const aarch64_opnd_info * operand )

Definition at line 572 of file aarch64-opc.c.

 {
   return ((aarch64_get_operand_class (operand->type)
        == AARCH64_OPND_CLASS_INT_REG)
       && !operand_maybe_stack_pointer (aarch64_operands + operand->type)
       && operand->reg.regno == 31);
 }

References aarch64_get_operand_class(), aarch64_operands, AARCH64_OPND_CLASS_INT_REG, and operand_maybe_stack_pointer().

◆ alias_opcode_p()

static bfd_boolean alias_opcode_p ( const aarch64_opcode * opcode )

inlinestatic

Definition at line 780 of file aarch64.h.

 {
   return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
 }

References F_ALIAS, FALSE, aarch64_opcode::opcode, and TRUE.

Referenced by determine_disassembling_preference().

◆ empty_qualifier_sequence_p()

static bfd_boolean empty_qualifier_sequence_p ( const aarch64_opnd_qualifier_t * qualifiers )

inlinestatic

Definition at line 659 of file aarch64.h.

 {
   int i;
   for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
     if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
       return FALSE;
   return TRUE;
 }

Referenced by aarch64_find_best_match().

◆ get_cond_from_value()

const aarch64_cond* get_cond_from_value ( aarch64_insn value )

Definition at line 369 of file aarch64-opc.c.

 {
   assert (value < 16);
   return &aarch64_conds[(unsigned int) value];
 }

References aarch64_conds, assert(), int, and value.

Referenced by aarch64_ext_cond(), and do_special_decoding().

◆ get_inverted_cond()

const aarch64_cond* get_inverted_cond ( const aarch64_cond * cond )

Definition at line 376 of file aarch64-opc.c.

 {
   return &aarch64_conds[cond->value ^ 0x1];
 }

Referenced by convert_csinc_to_cset(), and convert_from_csel().

◆ get_opcode_dependent_value()

static unsigned int get_opcode_dependent_value ( const aarch64_opcode * opcode )

inlinestatic

Definition at line 818 of file aarch64.h.

 {
   return (opcode->flags >> 24) & 0x7;
 }

References aarch64_opcode::opcode.

Referenced by aarch64_ext_ldst_elemlist(), aarch64_ext_ldst_reglist(), aarch64_ext_ldst_reglist_r(), aarch64_ext_simd_addr_post(), aarch64_ext_sve_reglist(), and operand_general_constraint_met_p().

◆ get_optional_operand_default_value()

static aarch64_insn get_optional_operand_default_value ( const aarch64_opcode * opcode )

inlinestatic

Definition at line 812 of file aarch64.h.

 {
   return (opcode->flags >> 15) & 0x1f;
 }

References aarch64_opcode::opcode.

Referenced by aarch64_print_operand().

◆ opcode_has_alias()

static bfd_boolean opcode_has_alias ( const aarch64_opcode * opcode )

inlinestatic

Definition at line 786 of file aarch64.h.

 {
   return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
 }

References F_HAS_ALIAS, FALSE, aarch64_opcode::opcode, and TRUE.

Referenced by determine_disassembling_preference().

◆ opcode_has_special_coder()

static bfd_boolean opcode_has_special_coder ( const aarch64_opcode * opcode )

inlinestatic

Definition at line 824 of file aarch64.h.

 {
   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
       | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
     : FALSE;
 }

References F_COND, F_FPTYPE, F_GPRSIZE_IN_Q, F_LDS_SIZE, F_LSE_SZ, F_MISC, F_N, F_SF, F_SIZEQ, F_SSIZE, F_T, FALSE, aarch64_opcode::opcode, and TRUE.

Referenced by aarch64_opcode_decode().

◆ opcode_priority()

static int opcode_priority ( const aarch64_opcode * opcode )

inlinestatic

Definition at line 793 of file aarch64.h.

 {
   return (opcode->flags >> 2) & 0x3;
 }

References aarch64_opcode::opcode.

◆ optional_operand_p()

static bfd_boolean optional_operand_p	(	const aarch64_opcode *	opcode,
		unsigned int	idx
	)

inlinestatic

Definition at line 805 of file aarch64.h.

 {
   return (((opcode->flags >> 12) & 0x7) == idx + 1)
     ? TRUE : FALSE;
 }

References FALSE, setup::idx, aarch64_opcode::opcode, and TRUE.

Referenced by aarch64_print_operand().

◆ pseudo_opcode_p()

static bfd_boolean pseudo_opcode_p ( const aarch64_opcode * opcode )

inlinestatic

Definition at line 799 of file aarch64.h.

 {
   return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
 }

References F_PSEUDO, FALSE, aarch64_opcode::opcode, and TRUE.

Referenced by determine_disassembling_preference().

Variable Documentation

◆ aarch64_barrier_options

const struct aarch64_name_value_pair aarch64_barrier_options[16]

extern

Definition at line 437 of file aarch64-opc.c.

Referenced by aarch64_ext_barrier().

◆ aarch64_conds

const aarch64_cond aarch64_conds[16]

extern

Definition at line 348 of file aarch64-opc.c.

Referenced by aarch64_get_operand_modifier(), and get_cond_from_value().

◆ aarch64_hint_options

const struct aarch64_name_value_pair aarch64_hint_options[]

extern

Definition at line 437 of file aarch64-opc.c.

Referenced by aarch64_ext_hint().

◆ aarch64_opcode_table

aarch64_opcode aarch64_opcode_table[]

extern

Definition at line 2162 of file aarch64-tbl.h.

Referenced by aarch64_find_alias_opcode(), aarch64_find_next_alias_opcode(), aarch64_find_next_opcode(), aarch64_get_opcode(), and aarch64_opcode_lookup().

◆ aarch64_operand_modifiers

const struct aarch64_name_value_pair aarch64_operand_modifiers[]

extern

Definition at line 376 of file aarch64-opc.c.

Referenced by aarch64_get_operand_modifier_from_value(), aarch64_print_operand(), and print_register_offset_address().

◆ aarch64_prfops

const struct aarch64_name_value_pair aarch64_prfops[32]

extern

Definition at line 437 of file aarch64-opc.c.

Referenced by aarch64_ext_prfop().

◆ aarch64_pstatefields

const aarch64_sys_reg aarch64_pstatefields[]

extern

Definition at line 4281 of file aarch64-opc.c.

Referenced by aarch64_ext_pstatefield(), and aarch64_print_operand().

◆ aarch64_sve_pattern_array

const char* const aarch64_sve_pattern_array[32]

extern

Definition at line 43 of file aarch64-opc.c.

Referenced by aarch64_print_operand().

◆ aarch64_sve_prfop_array

const char* const aarch64_sve_prfop_array[16]

extern

Definition at line 84 of file aarch64-opc.c.

Referenced by aarch64_print_operand().

◆ aarch64_sys_regs

const aarch64_sys_reg aarch64_sys_regs[]

extern

Definition at line 3673 of file aarch64-opc.c.

Referenced by aarch64_print_operand().

◆ aarch64_sys_regs_at

const aarch64_sys_ins_reg aarch64_sys_regs_at[]

extern

Definition at line 4339 of file aarch64-opc.c.

Referenced by aarch64_ext_sysins_op().

◆ aarch64_sys_regs_dc

const aarch64_sys_ins_reg aarch64_sys_regs_dc[]

extern

Definition at line 4325 of file aarch64-opc.c.

Referenced by aarch64_ext_sysins_op().

◆ aarch64_sys_regs_ic

const aarch64_sys_ins_reg aarch64_sys_regs_ic[]

extern

Definition at line 4317 of file aarch64-opc.c.

Referenced by aarch64_ext_sysins_op().

◆ aarch64_sys_regs_tlbi

const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[]

extern

Definition at line 4358 of file aarch64-opc.c.

Referenced by aarch64_ext_sysins_op().

Classes

Macros

Typedefs

Enumerations

Functions

Variables

Macro Definition Documentation

◆ AARCH64_ANY

◆ AARCH64_ARCH_NONE

◆ AARCH64_ARCH_V8

◆ AARCH64_ARCH_V8_1

◆ AARCH64_ARCH_V8_2

◆ AARCH64_ARCH_V8_3

◆ AARCH64_ARCH_V8_4

◆ AARCH64_CLEAR_FEATURE

◆ AARCH64_CPU_HAS_ALL_FEATURES

◆ AARCH64_CPU_HAS_ANY_FEATURES

◆ AARCH64_CPU_HAS_FEATURE

◆ AARCH64_FEATURE

◆ AARCH64_FEATURE_AES

◆ AARCH64_FEATURE_COMPNUM

◆ AARCH64_FEATURE_CRC

◆ AARCH64_FEATURE_CRYPTO

◆ AARCH64_FEATURE_DOTPROD

◆ AARCH64_FEATURE_F16

◆ AARCH64_FEATURE_F16_FML

◆ AARCH64_FEATURE_FP

◆ AARCH64_FEATURE_LOR

◆ AARCH64_FEATURE_LSE

◆ AARCH64_FEATURE_PAN

◆ AARCH64_FEATURE_PROFILE

◆ AARCH64_FEATURE_RAS

◆ AARCH64_FEATURE_RCPC

◆ AARCH64_FEATURE_RDMA

◆ AARCH64_FEATURE_SHA2

◆ AARCH64_FEATURE_SHA3

◆ AARCH64_FEATURE_SIMD

◆ AARCH64_FEATURE_SM4

◆ AARCH64_FEATURE_SVE

◆ AARCH64_FEATURE_V8

◆ AARCH64_FEATURE_V8_1

◆ AARCH64_FEATURE_V8_2

◆ AARCH64_FEATURE_V8_3

◆ AARCH64_FEATURE_V8_4

◆ AARCH64_MAX_OPND_NUM

◆ AARCH64_MAX_QLF_SEQ_NUM

◆ AARCH64_MERGE_FEATURE_SETS

◆ AARCH64_PCREL_OFFSET

◆ DEBUG_TRACE

◆ DEBUG_TRACE_IF

◆ F_ALIAS

◆ F_COND

◆ F_CONV

◆ F_DEFAULT

◆ F_FPTYPE

◆ F_GPRSIZE_IN_Q

◆ F_HAS_ALIAS

◆ F_LDS_SIZE

◆ F_LSE_SZ

◆ F_MISC

◆ F_N

◆ F_OD

◆ F_OPD0_OPT

◆ F_OPD1_OPT

◆ F_OPD2_OPT

◆ F_OPD3_OPT

◆ F_OPD4_OPT

◆ F_P1

◆ F_P2

◆ F_P3

◆ F_PSEUDO

◆ F_SF

◆ F_SIZEQ

◆ F_SSIZE

◆ F_STRICT

◆ F_SYS_READ

◆ F_SYS_WRITE

◆ F_T

Typedef Documentation

◆ aarch64_feature_set