aarch64-dis.c File Reference

#include "sysdep.h"
#include "disas-asm.h"
#include "libiberty.h"
#include "opintl.h"
#include "aarch64-dis.h"
#include "elf-bfd.h"

Go to the source code of this file.

Macros
#define	ERR_OK   0
#define	ERR_UND   -1
#define	ERR_UNP   -3
#define	ERR_NYI   -5
#define	INSNLEN   4

Enumerations
enum	map_type { MAP_INSN , MAP_DATA }

Functions
static void	set_default_aarch64_dis_options (struct disassemble_info *info ATTRIBUTE_UNUSED)
static void	parse_aarch64_dis_option (const char *option, unsigned int len ATTRIBUTE_UNUSED)
static void	parse_aarch64_dis_options (const char *options)
aarch64_insn	extract_fields (aarch64_insn code, aarch64_insn mask,...)
static aarch64_insn	extract_all_fields (const aarch64_operand *self, aarch64_insn code)
static int32_t	sign_extend (aarch64_insn value, unsigned i)
static enum aarch64_opnd_qualifier	get_greg_qualifier_from_value (aarch64_insn value)
static enum aarch64_opnd_qualifier	get_vreg_qualifier_from_value (aarch64_insn value)
static enum aarch64_opnd_qualifier	get_sreg_qualifier_from_value (aarch64_insn value)
static aarch64_opnd_qualifier_t	get_expected_qualifier (const aarch64_inst *inst, int i)
bfd_boolean	aarch64_ext_regno (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_regno_pair (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, const aarch64_insn code ATTRIBUTE_UNUSED, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_regrt_sysins (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_reglist (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, const aarch64_insn code, const aarch64_inst *inst, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_ldst_reglist_r (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, const aarch64_insn code, const aarch64_inst *inst, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, const aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_advsimd_imm_shift (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, const aarch64_insn code, const aarch64_inst *inst, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_shll_imm (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, const aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_imm (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_imm_half (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors)
bfd_boolean	aarch64_ext_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, const aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_fpimm (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_imm_rotate1 (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_imm_rotate2 (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_fbits (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, const aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_aimm (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, const aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
static bfd_boolean	decode_limm (uint32_t esize, aarch64_insn value, int64_t *result)
bfd_boolean	aarch64_ext_limm (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, const aarch64_inst *inst, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_inv_limm (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, const aarch64_inst *inst, aarch64_operand_error *errors)
bfd_boolean	aarch64_ext_ft (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, const aarch64_insn code, const aarch64_inst *inst, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_addr_offset (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_addr_simm (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_addr_uimm12 (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_addr_simm10 (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_simd_addr_post (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_cond (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_sysreg (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_pstatefield (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_barrier (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_prfop (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_hint (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_reg_extended (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
static bfd_boolean	aarch64_ext_sve_addr_reg_mul_vl (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, int64_t offset)
bfd_boolean	aarch64_ext_sve_addr_ri_s4xvl (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_sve_addr_ri_s6xvl (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_sve_addr_ri_s9xvl (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
static bfd_boolean	aarch64_ext_sve_addr_reg_imm (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, int64_t offset)
bfd_boolean	aarch64_ext_sve_addr_ri_s4 (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_sve_addr_ri_u6 (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_sve_addr_rr_lsl (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_sve_addr_rz_xtw (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_sve_addr_zi_u5 (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
static bfd_boolean	aarch64_ext_sve_addr_zz (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, enum aarch64_modifier_kind kind)
bfd_boolean	aarch64_ext_sve_addr_zz_lsl (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_sve_addr_zz_sxtw (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_sve_addr_zz_uxtw (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
static bfd_boolean	decode_sve_aimm (aarch64_opnd_info *info, int64_t value)
bfd_boolean	aarch64_ext_sve_aimm (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, const aarch64_inst *inst, aarch64_operand_error *errors)
bfd_boolean	aarch64_ext_sve_asimm (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, const aarch64_inst *inst, aarch64_operand_error *errors)
bfd_boolean	aarch64_ext_sve_float_half_one (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_sve_float_half_two (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_sve_float_zero_one (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_sve_index (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_sve_limm_mov (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, const aarch64_inst *inst, aarch64_operand_error *errors)
bfd_boolean	aarch64_ext_sve_quad_index (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_sve_reglist (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
bfd_boolean	aarch64_ext_sve_scale (const aarch64_operand *self, aarch64_opnd_info *info, aarch64_insn code, const aarch64_inst *inst, aarch64_operand_error *errors)
static uint64_t	get_top_bit (uint64_t value)
bfd_boolean	aarch64_ext_sve_shlimm (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, const aarch64_inst *inst, aarch64_operand_error *errors)
bfd_boolean	aarch64_ext_sve_shrimm (const aarch64_operand *self, aarch64_opnd_info *info, const aarch64_insn code, const aarch64_inst *inst, aarch64_operand_error *errors)
static enum aarch64_opnd_qualifier	get_qualifier_from_partial_encoding (aarch64_insn value, const enum aarch64_opnd_qualifier *candidates, aarch64_insn mask)
static void	get_operand_possible_qualifiers (int idx, const aarch64_opnd_qualifier_seq_t *list, enum aarch64_opnd_qualifier *qualifiers)
static int	decode_sizeq (aarch64_inst *inst)
static int	decode_asimd_fcvt (aarch64_inst *inst)
static int	decode_asisd_fcvtxn (aarch64_inst *inst)
static int	decode_fcvt (aarch64_inst *inst)
static int	do_misc_decoding (aarch64_inst *inst)
static int	do_special_decoding (aarch64_inst *inst)
static int	convert_extr_to_ror (aarch64_inst *inst)
static int	convert_shll_to_xtl (aarch64_inst *inst)
static int	convert_bfm_to_sr (aarch64_inst *inst)
static int	convert_orr_to_mov (aarch64_inst *inst)
static int	convert_bfm_to_bfx (aarch64_inst *inst)
static int	convert_bfm_to_bfi (aarch64_inst *inst)
static int	convert_bfm_to_bfc (aarch64_inst *inst)
static int	convert_ubfm_to_lsl (aarch64_inst *inst)
static int	convert_from_csel (aarch64_inst *inst)
static int	convert_csinc_to_cset (aarch64_inst *inst)
static int	convert_movewide_to_mov (aarch64_inst *inst)
static int	convert_movebitmask_to_mov (aarch64_inst *inst)
static int	convert_to_alias (aarch64_inst *inst, const aarch64_opcode *alias)
static bfd_boolean	aarch64_opcode_decode (const aarch64_opcode *, const aarch64_insn, aarch64_inst *, int, aarch64_operand_error *errors)
static void	determine_disassembling_preference (struct aarch64_inst *inst, aarch64_operand_error *errors)
static bfd_boolean	aarch64_decode_variant_using_iclass (aarch64_inst *inst)
static void	user_friendly_fixup (aarch64_inst *inst)
int	aarch64_decode_insn (aarch64_insn insn, aarch64_inst *inst, bfd_boolean noaliases_p, aarch64_operand_error *errors)
static void	print_operands (bfd_vma pc, const aarch64_opcode *opcode, const aarch64_opnd_info *opnds, struct disassemble_info *info)
static void	remove_dot_suffix (char *name, const aarch64_inst *inst)
static void	print_mnemonic_name (const aarch64_inst *inst, struct disassemble_info *info)
static void	print_comment (const aarch64_inst *inst, struct disassemble_info *info)
static void	print_aarch64_insn (bfd_vma pc, const aarch64_inst *inst, struct disassemble_info *info)
static void	print_insn_aarch64_word (bfd_vma pc, uint32_t word, struct disassemble_info *info, aarch64_operand_error *errors)
bfd_boolean	aarch64_symbol_is_valid (asymbol *sym, struct disassemble_info *info ATTRIBUTE_UNUSED)
static void	print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED, uint32_t word, struct disassemble_info *info, aarch64_operand_error *errors ATTRIBUTE_UNUSED)
static int	get_sym_code_type (struct disassemble_info *info, int n, enum map_type *map_type)
int	print_insn_aarch64 (bfd_vma pc, struct disassemble_info *info)
void	print_aarch64_disassembler_options (FILE *stream)

Variables
static enum map_type	last_type
static int	last_mapping_sym = -1
static bfd_vma	last_mapping_addr = 0
static int	no_aliases = 0
static int	no_notes = 1

Macro Definition Documentation

ERR_NYI

#define ERR_NYI   -5

Definition at line 34 of file aarch64-dis.c.

ERR_OK

#define ERR_OK   0

Definition at line 31 of file aarch64-dis.c.

ERR_UND

#define ERR_UND   -1

Definition at line 32 of file aarch64-dis.c.

ERR_UNP

#define ERR_UNP   -3

Definition at line 33 of file aarch64-dis.c.

INSNLEN

#define INSNLEN   4

Definition at line 36 of file aarch64-dis.c.

Enumeration Type Documentation

map_type

enum map_type

Enumerator
MAP_INSN
MAP_DATA

Definition at line 39 of file aarch64-dis.c.

{
  MAP_INSN,
  MAP_DATA
};

Function Documentation

aarch64_decode_insn()

int aarch64_decode_insn	(	aarch64_insn	insn,
		aarch64_inst *	inst,
		bfd_boolean	noaliases_p,
		aarch64_operand_error *	errors
	)

Definition at line 2958 of file aarch64-dis.c.

{
  const aarch64_opcode *opcode = aarch64_opcode_lookup (insn);
 
#ifdef DEBUG_AARCH64
  if (debug_dump)
    {
      const aarch64_opcode *tmp = opcode;
      printf ("\n");
      DEBUG_TRACE ("opcode lookup:");
      while (tmp != NULL)
    {
      aarch64_verbose ("  %s", tmp->name);
      tmp = aarch64_find_next_opcode (tmp);
    }
    }
#endif /* DEBUG_AARCH64 */
 
  /* A list of opcodes may have been found, as aarch64_opcode_lookup cannot
     distinguish some opcodes, e.g. SSHR and MOVI, which almost share the same
     opcode field and value, apart from the difference that one of them has an
     extra field as part of the opcode, but such a field is used for operand
     encoding in other opcode(s) ('immh' in the case of the example).  */
  while (opcode != NULL)
    {
      /* But only one opcode can be decoded successfully for, as the
     decoding routine will check the constraint carefully.  */
      if (aarch64_opcode_decode (opcode, insn, inst, noaliases_p, errors) == 1)
    return ERR_OK;
      opcode = aarch64_find_next_opcode (opcode);
    }
 
  return ERR_UND;
}

References aarch64_find_next_opcode(), aarch64_opcode_decode(), aarch64_opcode_lookup(), DEBUG_TRACE, ERR_OK, ERR_UND, NULL, printf(), and autogen_x86imm::tmp.

Referenced by print_insn_aarch64_word().

aarch64_decode_variant_using_iclass()

static bfd_boolean aarch64_decode_variant_using_iclass ( aarch64_inst *  inst )

static

Definition at line 2734 of file aarch64-dis.c.

{
  int i, variant;
 
  variant = 0;
  switch (inst->opcode->iclass)
    {
    case sve_cpy:
      variant = extract_fields (inst->value, 0, 2, FLD_size, FLD_SVE_M_14);
      break;
 
    case sve_index:
      i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5);
      if ((i & 31) == 0)
    return FALSE;
      while ((i & 1) == 0)
    {
      i >>= 1;
      variant += 1;
    }
      break;
 
    case sve_limm:
      /* Pick the smallest applicable element size.  */
      if ((inst->value & 0x20600) == 0x600)
    variant = 0;
      else if ((inst->value & 0x20400) == 0x400)
    variant = 1;
      else if ((inst->value & 0x20000) == 0)
    variant = 2;
      else
    variant = 3;
      break;
 
    case sve_misc:
      /* sve_misc instructions have only a single variant.  */
      break;
 
    case sve_movprfx:
      variant = extract_fields (inst->value, 0, 2, FLD_size, FLD_SVE_M_16);
      break;
 
    case sve_pred_zm:
      variant = extract_field (FLD_SVE_M_4, inst->value, 0);
      break;
 
    case sve_shift_pred:
      i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_SVE_tszl_8);
    sve_shift:
      if (i == 0)
    return FALSE;
      while (i != 1)
    {
      i >>= 1;
      variant += 1;
    }
      break;
 
    case sve_shift_unpred:
      i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_SVE_tszl_19);
      goto sve_shift;
 
    case sve_size_bhs:
      variant = extract_field (FLD_size, inst->value, 0);
      if (variant >= 3)
    return FALSE;
      break;
 
    case sve_size_bhsd:
      variant = extract_field (FLD_size, inst->value, 0);
      break;
 
    case sve_size_hsd:
      i = extract_field (FLD_size, inst->value, 0);
      if (i < 1)
    return FALSE;
      variant = i - 1;
      break;
 
    case sve_size_sd:
      variant = extract_field (FLD_SVE_sz, inst->value, 0);
      break;
 
    default:
      /* No mapping between instruction class and qualifiers.  */
      return TRUE;
    }
 
  for (i = 0; i < AARCH64_MAX_OPND_NUM; i++)
    inst->operands[i].qualifier = inst->opcode->qualifiers_list[variant][i];
  return TRUE;
}

References AARCH64_MAX_OPND_NUM, extract_field(), extract_fields(), FALSE, FLD_imm5, FLD_size, FLD_SVE_M_14, FLD_SVE_M_16, FLD_SVE_M_4, FLD_SVE_sz, FLD_SVE_tszh, FLD_SVE_tszl_19, FLD_SVE_tszl_8, i, aarch64_opcode::iclass, aarch64_inst::opcode, aarch64_inst::operands, aarch64_opnd_info::qualifier, aarch64_opcode::qualifiers_list, sve_cpy, sve_index, sve_limm, sve_misc, sve_movprfx, sve_pred_zm, sve_shift_pred, sve_shift_unpred, sve_size_bhs, sve_size_bhsd, sve_size_hsd, sve_size_sd, TRUE, and aarch64_inst::value.

Referenced by aarch64_opcode_decode().

aarch64_ext_addr_offset()

bfd_boolean aarch64_ext_addr_offset	(	const aarch64_operand *self	ATTRIBUTE_UNUSED,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *	inst,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 1003 of file aarch64-dis.c.

{
  info->qualifier = get_expected_qualifier (inst, info->idx);
 
  /* Rn */
  info->addr.base_regno = extract_field (self->fields[0], code, 0);
 
  /* simm9 */
  aarch64_insn imm = extract_fields (code, 0, 1, self->fields[1]);
  info->addr.offset.imm = sign_extend (imm, 8);
  if (extract_field (self->fields[2], code, 0) == 1) {
    info->addr.writeback = 1;
    info->addr.preind = 1;
  }
  return TRUE;
}

References extract_field(), extract_fields(), get_expected_qualifier(), imm, info(), sign_extend(), and TRUE.

Referenced by aarch64_extract_operand().

aarch64_ext_addr_regoff()

bfd_boolean aarch64_ext_addr_regoff	(	const aarch64_operand *self	ATTRIBUTE_UNUSED,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *	inst,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 1026 of file aarch64-dis.c.

{
  aarch64_insn S, value;
 
  /* Rn */
  info->addr.base_regno = extract_field (FLD_Rn, code, 0);
  /* Rm */
  info->addr.offset.regno = extract_field (FLD_Rm, code, 0);
  /* option */
  value = extract_field (FLD_option, code, 0);
  info->shifter.kind =
    aarch64_get_operand_modifier_from_value (value, TRUE /* extend_p */);
  /* Fix-up the shifter kind; although the table-driven approach is
     efficient, it is slightly inflexible, thus needing this fix-up.  */
  if (info->shifter.kind == AARCH64_MOD_UXTX)
    info->shifter.kind = AARCH64_MOD_LSL;
  /* S */
  S = extract_field (FLD_S, code, 0);
  if (S == 0)
    {
      info->shifter.amount = 0;
      info->shifter.amount_present = 0;
    }
  else
    {
      int size;
      /* Need information in other operand(s) to help achieve the decoding
     from 'S' field.  */
      info->qualifier = get_expected_qualifier (inst, info->idx);
      /* Get the size of the data element that is accessed, which may be
     different from that of the source register size, e.g. in strb/ldrb.  */
      size = aarch64_get_qualifier_esize (info->qualifier);
      info->shifter.amount = get_logsz (size);
      info->shifter.amount_present = 1;
    }
 
  return TRUE;
}

References aarch64_get_operand_modifier_from_value(), aarch64_get_qualifier_esize(), AARCH64_MOD_LSL, AARCH64_MOD_UXTX, extract_field(), FLD_option, FLD_Rm, FLD_Rn, FLD_S, get_expected_qualifier(), get_logsz(), info(), S, TRUE, and value.

Referenced by aarch64_extract_operand().

aarch64_ext_addr_simm()

bfd_boolean aarch64_ext_addr_simm	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *	inst,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 1070 of file aarch64-dis.c.

{
  aarch64_insn imm;
  info->qualifier = get_expected_qualifier (inst, info->idx);
 
  /* Rn */
  info->addr.base_regno = extract_field (FLD_Rn, code, 0);
  /* simm (imm9 or imm7)  */
  imm = extract_field (self->fields[0], code, 0);
  info->addr.offset.imm = sign_extend (imm, fields[self->fields[0]].width - 1);
  if (self->fields[0] == FLD_imm7)
    /* scaled immediate in ld/st pair instructions.  */
    info->addr.offset.imm *= aarch64_get_qualifier_esize (info->qualifier);
  /* qualifier */
  if (inst->opcode->iclass == ldst_unscaled
      || inst->opcode->iclass == ldstnapair_offs
      || inst->opcode->iclass == ldstpair_off
      || inst->opcode->iclass == ldst_unpriv)
    info->addr.writeback = 0;
  else
    {
      /* pre/post- index */
      info->addr.writeback = 1;
      if (extract_field (self->fields[1], code, 0) == 1)
    info->addr.preind = 1;
      else
    info->addr.postind = 1;
    }
 
  return TRUE;
}

References aarch64_get_qualifier_esize(), extract_field(), fields, FLD_imm7, FLD_Rn, get_expected_qualifier(), aarch64_opcode::iclass, imm, info(), ldst_unpriv, ldst_unscaled, ldstnapair_offs, ldstpair_off, aarch64_inst::opcode, sign_extend(), TRUE, and aarch64_field::width.

Referenced by aarch64_extract_operand().

aarch64_ext_addr_simm10()

bfd_boolean aarch64_ext_addr_simm10	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 1123 of file aarch64-dis.c.

{
  aarch64_insn imm;
 
  info->qualifier = get_expected_qualifier (inst, info->idx);
  /* Rn */
  info->addr.base_regno = extract_field (self->fields[0], code, 0);
  /* simm10 */
  imm = extract_fields (code, 0, 2, self->fields[1], self->fields[2]);
  info->addr.offset.imm = sign_extend (imm, 9) << 3;
  if (extract_field (self->fields[3], code, 0) == 1) {
    info->addr.writeback = 1;
    info->addr.preind = 1;
  }
  return TRUE;
}

References extract_field(), extract_fields(), get_expected_qualifier(), imm, info(), sign_extend(), and TRUE.

Referenced by aarch64_extract_operand().

aarch64_ext_addr_simple()

bfd_boolean aarch64_ext_addr_simple	(	const aarch64_operand *self	ATTRIBUTE_UNUSED,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 989 of file aarch64-dis.c.

{
  /* Rn */
  info->addr.base_regno = extract_field (FLD_Rn, code, 0);
  return TRUE;
}

References extract_field(), FLD_Rn, info(), and TRUE.

Referenced by aarch64_extract_operand().

aarch64_ext_addr_uimm12()

bfd_boolean aarch64_ext_addr_uimm12	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 1106 of file aarch64-dis.c.

{
  int shift;
  info->qualifier = get_expected_qualifier (inst, info->idx);
  shift = get_logsz (aarch64_get_qualifier_esize (info->qualifier));
  /* Rn */
  info->addr.base_regno = extract_field (self->fields[0], code, 0);
  /* uimm12 */
  info->addr.offset.imm = extract_field (self->fields[1], code, 0) << shift;
  return TRUE;
}

References aarch64_get_qualifier_esize(), extract_field(), get_expected_qualifier(), get_logsz(), info(), shift(), and TRUE.

Referenced by aarch64_extract_operand().

aarch64_ext_advsimd_imm_modified()

bfd_boolean aarch64_ext_advsimd_imm_modified	(	const aarch64_operand *self	ATTRIBUTE_UNUSED,
		aarch64_opnd_info *	info,
		const aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 697 of file aarch64-dis.c.

{
  uint64_t imm;
  enum aarch64_opnd_qualifier opnd0_qualifier = inst->operands[0].qualifier;
  aarch64_field field = {0, 0};
 
  assert (info->idx == 1);
 
  if (info->type == AARCH64_OPND_SIMD_FPIMM)
    info->imm.is_fp = 1;
 
  /* a:b:c:d:e:f:g:h */
  imm = extract_fields (code, 0, 2, FLD_abc, FLD_defgh);
  if (!info->imm.is_fp && aarch64_get_qualifier_esize (opnd0_qualifier) == 8)
    {
      /* Either MOVI <Dd>, #<imm>
     or     MOVI <Vd>.2D, #<imm>.
     <imm> is a 64-bit immediate
     'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh',
     encoded in "a:b:c:d:e:f:g:h".  */
      int i;
      unsigned abcdefgh = imm;
      for (imm = 0ull, i = 0; i < 8; i++)
    if (((abcdefgh >> i) & 0x1) != 0)
      imm |= 0xffull << (8 * i);
    }
  info->imm.value = imm;
 
  /* cmode */
  info->qualifier = get_expected_qualifier (inst, info->idx);
  switch (info->qualifier)
    {
    case AARCH64_OPND_QLF_NIL:
      /* no shift */
      info->shifter.kind = AARCH64_MOD_NONE;
      return 1;
    case AARCH64_OPND_QLF_LSL:
      /* shift zeros */
      info->shifter.kind = AARCH64_MOD_LSL;
      switch (aarch64_get_qualifier_esize (opnd0_qualifier))
    {
    case 4: gen_sub_field (FLD_cmode, 1, 2, &field); break; /* per word */
    case 2: gen_sub_field (FLD_cmode, 1, 1, &field); break; /* per half */
    case 1: gen_sub_field (FLD_cmode, 1, 0, &field); break; /* per byte */
    default: assert (0); return FALSE;
    }
      /* 00: 0; 01: 8; 10:16; 11:24.  */
      info->shifter.amount = extract_field_2 (&field, code, 0) << 3;
      break;
    case AARCH64_OPND_QLF_MSL:
      /* shift ones */
      info->shifter.kind = AARCH64_MOD_MSL;
      gen_sub_field (FLD_cmode, 0, 1, &field);      /* per word */
      info->shifter.amount = extract_field_2 (&field, code, 0) ? 16 : 8;
      break;
    default:
      assert (0);
      return FALSE;
    }
 
  return TRUE;
}

References aarch64_get_qualifier_esize(), AARCH64_MOD_LSL, AARCH64_MOD_MSL, AARCH64_MOD_NONE, AARCH64_OPND_QLF_LSL, AARCH64_OPND_QLF_MSL, AARCH64_OPND_QLF_NIL, AARCH64_OPND_SIMD_FPIMM, assert(), extract_field_2(), extract_fields(), FALSE, FLD_abc, FLD_cmode, FLD_defgh, gen_sub_field(), get_expected_qualifier(), i, imm, info(), TRUE, and rz_bin_info_t::type.

Referenced by aarch64_extract_operand().

aarch64_ext_advsimd_imm_shift()

bfd_boolean aarch64_ext_advsimd_imm_shift	(	const aarch64_operand *self	ATTRIBUTE_UNUSED,
		aarch64_opnd_info *	info,
		const aarch64_insn	code,
		const aarch64_inst *	inst,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 573 of file aarch64-dis.c.

{
  int pos;
  aarch64_insn Q, imm, immh;
  enum aarch64_insn_class iclass = inst->opcode->iclass;
 
  immh = extract_field (FLD_immh, code, 0);
  if (immh == 0)
    return FALSE;
  imm = extract_fields (code, 0, 2, FLD_immh, FLD_immb);
  pos = 4;
  /* Get highest set bit in immh.  */
  while (--pos >= 0 && (immh & 0x8) == 0)
    immh <<= 1;
 
  assert ((iclass == asimdshf || iclass == asisdshf)
      && (info->type == AARCH64_OPND_IMM_VLSR
          || info->type == AARCH64_OPND_IMM_VLSL));
 
  if (iclass == asimdshf)
    {
      Q = extract_field (FLD_Q, code, 0);
      /* immh   Q   <T>
     0000   x   SEE AdvSIMD modified immediate
     0001   0   8B
     0001   1   16B
     001x   0   4H
     001x   1   8H
     01xx   0   2S
     01xx   1   4S
     1xxx   0   RESERVED
     1xxx   1   2D  */
      info->qualifier =
    get_vreg_qualifier_from_value ((pos << 1) | (int) Q);
    }
  else
    info->qualifier = get_sreg_qualifier_from_value (pos);
 
  if (info->type == AARCH64_OPND_IMM_VLSR)
    /* immh <shift>
       0000 SEE AdvSIMD modified immediate
       0001 (16-UInt(immh:immb))
       001x (32-UInt(immh:immb))
       01xx (64-UInt(immh:immb))
       1xxx (128-UInt(immh:immb))  */
    info->imm.value = (16 << pos) - imm;
  else
    /* immh:immb
       immh <shift>
       0000 SEE AdvSIMD modified immediate
       0001 (UInt(immh:immb)-8)
       001x (UInt(immh:immb)-16)
       01xx (UInt(immh:immb)-32)
       1xxx (UInt(immh:immb)-64)  */
    info->imm.value = imm - (8 << pos);
 
  return TRUE;
}

References AARCH64_OPND_IMM_VLSL, AARCH64_OPND_IMM_VLSR, asimdshf, asisdshf, assert(), extract_field(), extract_fields(), FALSE, FLD_immb, FLD_immh, FLD_Q, get_sreg_qualifier_from_value(), get_vreg_qualifier_from_value(), aarch64_opcode::iclass, imm, info(), aarch64_inst::opcode, pos, Q, TRUE, and rz_bin_info_t::type.

Referenced by aarch64_extract_operand().

aarch64_ext_aimm()

bfd_boolean aarch64_ext_aimm	(	const aarch64_operand *self	ATTRIBUTE_UNUSED,
		aarch64_opnd_info *	info,
		const aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 816 of file aarch64-dis.c.

{
  aarch64_insn value;
 
  info->shifter.kind = AARCH64_MOD_LSL;
  /* shift */
  value = extract_field (FLD_shift, code, 0);
  if (value >= 2)
    return FALSE;
  info->shifter.amount = value ? 12 : 0;
  /* imm12 (unsigned) */
  info->imm.value = extract_field (FLD_imm12, code, 0);
 
  return TRUE;
}

References AARCH64_MOD_LSL, extract_field(), FALSE, FLD_imm12, FLD_shift, info(), TRUE, and value.

Referenced by aarch64_extract_operand().

aarch64_ext_barrier()

bfd_boolean aarch64_ext_barrier	(	const aarch64_operand *self	ATTRIBUTE_UNUSED,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 1280 of file aarch64-dis.c.

{
  /* CRm */
  info->barrier = aarch64_barrier_options + extract_field (FLD_CRm, code, 0);
  return TRUE;
}

References aarch64_barrier_options, extract_field(), FLD_CRm, info(), and TRUE.

Referenced by aarch64_extract_operand().

aarch64_ext_cond()

bfd_boolean aarch64_ext_cond	(	const aarch64_operand *self	ATTRIBUTE_UNUSED,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 1180 of file aarch64-dis.c.

{
  aarch64_insn value;
  /* cond */
  value = extract_field (FLD_cond, code, 0);
  info->cond = get_cond_from_value (value);
  return TRUE;
}

References extract_field(), FLD_cond, get_cond_from_value(), info(), TRUE, and value.

Referenced by aarch64_extract_operand().

aarch64_ext_fbits()

bfd_boolean aarch64_ext_fbits	(	const aarch64_operand *self	ATTRIBUTE_UNUSED,
		aarch64_opnd_info *	info,
		const aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 804 of file aarch64-dis.c.

{
  info->imm.value = 64- extract_field (FLD_scale, code, 0);
  return TRUE;
}

References extract_field(), FLD_scale, info(), and TRUE.

Referenced by aarch64_extract_operand().

aarch64_ext_fpimm()

bfd_boolean aarch64_ext_fpimm	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		const aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 766 of file aarch64-dis.c.

{
  info->imm.value = extract_all_fields (self, code);
  info->imm.is_fp = 1;
  return TRUE;
}

References extract_all_fields(), info(), and TRUE.

Referenced by aarch64_extract_operand().

aarch64_ext_ft()

bfd_boolean aarch64_ext_ft	(	const aarch64_operand *self	ATTRIBUTE_UNUSED,
		aarch64_opnd_info *	info,
		const aarch64_insn	code,
		const aarch64_inst *	inst,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 948 of file aarch64-dis.c.

{
  aarch64_insn value;
 
  /* Rt */
  info->reg.regno = extract_field (FLD_Rt, code, 0);
 
  /* size */
  value = extract_field (FLD_ldst_size, code, 0);
  if (inst->opcode->iclass == ldstpair_indexed
      || inst->opcode->iclass == ldstnapair_offs
      || inst->opcode->iclass == ldstpair_off
      || inst->opcode->iclass == loadlit)
    {
      enum aarch64_opnd_qualifier qualifier;
      switch (value)
    {
    case 0: qualifier = AARCH64_OPND_QLF_S_S; break;
    case 1: qualifier = AARCH64_OPND_QLF_S_D; break;
    case 2: qualifier = AARCH64_OPND_QLF_S_Q; break;
    default: return FALSE;
    }
      info->qualifier = qualifier;
    }
  else
    {
      /* opc1:size */
      value = extract_fields (code, 0, 2, FLD_opc1, FLD_ldst_size);
      if (value > 0x4)
    return FALSE;
      info->qualifier = get_sreg_qualifier_from_value (value);
    }
 
  return TRUE;
}

References AARCH64_OPND_QLF_S_D, AARCH64_OPND_QLF_S_Q, AARCH64_OPND_QLF_S_S, extract_field(), extract_fields(), FALSE, FLD_ldst_size, FLD_opc1, FLD_Rt, get_sreg_qualifier_from_value(), aarch64_opcode::iclass, info(), ldstnapair_offs, ldstpair_indexed, ldstpair_off, loadlit, aarch64_inst::opcode, TRUE, and value.

Referenced by aarch64_extract_operand().

aarch64_ext_hint()

bfd_boolean aarch64_ext_hint	(	const aarch64_operand *self	ATTRIBUTE_UNUSED,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 1309 of file aarch64-dis.c.

{
  /* CRm:op2.  */
  unsigned hint_number;
  int i;
 
  hint_number = extract_fields (code, 0, 2, FLD_CRm, FLD_op2);
 
  for (i = 0; aarch64_hint_options[i].name != NULL; i++)
    {
      if (hint_number == aarch64_hint_options[i].value)
    {
      info->hint_option = &(aarch64_hint_options[i]);
      return TRUE;
    }
    }
 
  return FALSE;
}

References aarch64_hint_options, extract_fields(), FALSE, FLD_CRm, FLD_op2, i, info(), aarch64_name_value_pair::name, NULL, TRUE, and value.

Referenced by aarch64_extract_operand().

aarch64_ext_imm()

bfd_boolean aarch64_ext_imm	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		const aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 659 of file aarch64-dis.c.

{
  int64_t imm;
 
  imm = extract_all_fields (self, code);
 
  if (operand_need_sign_extension (self))
    imm = sign_extend (imm, get_operand_fields_width (self) - 1);
 
  if (operand_need_shift_by_two (self))
    imm <<= 2;
 
  if (info->type == AARCH64_OPND_ADDR_ADRP)
    imm <<= 12;
 
  info->imm.value = imm;
  return TRUE;
}

References AARCH64_OPND_ADDR_ADRP, extract_all_fields(), get_operand_fields_width(), imm, info(), operand_need_shift_by_two(), operand_need_sign_extension(), sign_extend(), TRUE, and rz_bin_info_t::type.

Referenced by aarch64_ext_imm_half(), aarch64_ext_sve_aimm(), aarch64_ext_sve_asimm(), aarch64_ext_sve_scale(), aarch64_ext_sve_shlimm(), aarch64_ext_sve_shrimm(), and aarch64_extract_operand().

aarch64_ext_imm_half()

bfd_boolean aarch64_ext_imm_half	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		const aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *	errors
	)

Definition at line 683 of file aarch64-dis.c.

{
  aarch64_ext_imm (self, info, code, inst, errors);
  info->shifter.kind = AARCH64_MOD_LSL;
  info->shifter.amount = extract_field (FLD_hw, code, 0) << 4;
  return TRUE;
}

References aarch64_ext_imm(), AARCH64_MOD_LSL, extract_field(), FLD_hw, info(), and TRUE.

Referenced by aarch64_extract_operand().

aarch64_ext_imm_rotate1()

bfd_boolean aarch64_ext_imm_rotate1	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		const aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 778 of file aarch64-dis.c.

{
  uint64_t rot = extract_field (self->fields[0], code, 0);
  assert (rot < 2U);
  info->imm.value = rot * 180 + 90;
  return TRUE;
}

References assert(), extract_field(), info(), and TRUE.

Referenced by aarch64_extract_operand().

aarch64_ext_imm_rotate2()

bfd_boolean aarch64_ext_imm_rotate2	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		const aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 791 of file aarch64-dis.c.

{
  uint64_t rot = extract_field (self->fields[0], code, 0);
  assert (rot < 4U);
  info->imm.value = rot * 90;
  return TRUE;
}

References assert(), extract_field(), info(), and TRUE.

Referenced by aarch64_extract_operand().

aarch64_ext_inv_limm()

bfd_boolean aarch64_ext_inv_limm	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		const aarch64_insn	code,
		const aarch64_inst *	inst,
		aarch64_operand_error *	errors
	)

Definition at line 934 of file aarch64-dis.c.

{
  if (!aarch64_ext_limm (self, info, code, inst, errors))
    return FALSE;
  info->imm.value = ~info->imm.value;
  return TRUE;
}

References aarch64_ext_limm(), FALSE, info(), and TRUE.

Referenced by aarch64_extract_operand().

aarch64_ext_ldst_elemlist()

bfd_boolean aarch64_ext_ldst_elemlist	(	const aarch64_operand *self	ATTRIBUTE_UNUSED,
		aarch64_opnd_info *	info,
		const aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 503 of file aarch64-dis.c.

{
  aarch64_field field = {0, 0};
  aarch64_insn QSsize;      /* fields Q:S:size.  */
  aarch64_insn opcodeh2;    /* opcode<2:1> */
 
  /* Rt */
  info->reglist.first_regno = extract_field (FLD_Rt, code, 0);
 
  /* Decode the index, opcode<2:1> and size.  */
  gen_sub_field (FLD_asisdlso_opcode, 1, 2, &field);
  opcodeh2 = extract_field_2 (&field, code, 0);
  QSsize = extract_fields (code, 0, 3, FLD_Q, FLD_S, FLD_vldst_size);
  switch (opcodeh2)
    {
    case 0x0:
      info->qualifier = AARCH64_OPND_QLF_S_B;
      /* Index encoded in "Q:S:size".  */
      info->reglist.index = QSsize;
      break;
    case 0x1:
      if (QSsize & 0x1)
    /* UND.  */
    return FALSE;
      info->qualifier = AARCH64_OPND_QLF_S_H;
      /* Index encoded in "Q:S:size<1>".  */
      info->reglist.index = QSsize >> 1;
      break;
    case 0x2:
      if ((QSsize >> 1) & 0x1)
    /* UND.  */
    return FALSE;
      if ((QSsize & 0x1) == 0)
    {
      info->qualifier = AARCH64_OPND_QLF_S_S;
      /* Index encoded in "Q:S".  */
      info->reglist.index = QSsize >> 2;
    }
      else
    {
      if (extract_field (FLD_S, code, 0))
        /* UND */
        return FALSE;
      info->qualifier = AARCH64_OPND_QLF_S_D;
      /* Index encoded in "Q".  */
      info->reglist.index = QSsize >> 3;
    }
      break;
    default:
      return FALSE;
    }
 
  info->reglist.has_index = 1;
  info->reglist.num_regs = 0;
  /* Number of registers is equal to the number of elements in
     each structure to be loaded/stored.  */
  info->reglist.num_regs = get_opcode_dependent_value (inst->opcode);
  assert (info->reglist.num_regs >= 1 && info->reglist.num_regs <= 4);
 
  return TRUE;
}

References AARCH64_OPND_QLF_S_B, AARCH64_OPND_QLF_S_D, AARCH64_OPND_QLF_S_H, AARCH64_OPND_QLF_S_S, assert(), extract_field(), extract_field_2(), extract_fields(), FALSE, FLD_asisdlso_opcode, FLD_Q, FLD_Rt, FLD_S, FLD_vldst_size, gen_sub_field(), get_opcode_dependent_value(), info(), and TRUE.

Referenced by aarch64_extract_operand().

aarch64_ext_ldst_reglist()

bfd_boolean aarch64_ext_ldst_reglist	(	const aarch64_operand *self	ATTRIBUTE_UNUSED,
		aarch64_opnd_info *	info,
		const aarch64_insn	code,
		const aarch64_inst *	inst,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 431 of file aarch64-dis.c.

{
  aarch64_insn value;
  /* Number of elements in each structure to be loaded/stored.  */
  unsigned expected_num = get_opcode_dependent_value (inst->opcode);
 
  struct
    {
      unsigned is_reserved;
      unsigned num_regs;
      unsigned num_elements;
    } data [] =
  {   {0, 4, 4},
      {1, 4, 4},
      {0, 4, 1},
      {0, 4, 2},
      {0, 3, 3},
      {1, 3, 3},
      {0, 3, 1},
      {0, 1, 1},
      {0, 2, 2},
      {1, 2, 2},
      {0, 2, 1},
  };
 
  /* Rt */
  info->reglist.first_regno = extract_field (FLD_Rt, code, 0);
  /* opcode */
  value = extract_field (FLD_opcode, code, 0);
  /* PR 21595: Check for a bogus value.  */
  if (value >= ARRAY_SIZE (data))
    return FALSE;
  if (expected_num != data[value].num_elements || data[value].is_reserved)
    return FALSE;
  info->reglist.num_regs = data[value].num_regs;
 
  return TRUE;
}

References ARRAY_SIZE, extract_field(), FALSE, FLD_opcode, FLD_Rt, get_opcode_dependent_value(), info(), aarch64_inst::opcode, TRUE, and value.

Referenced by aarch64_extract_operand().

aarch64_ext_ldst_reglist_r()

bfd_boolean aarch64_ext_ldst_reglist_r	(	const aarch64_operand *self	ATTRIBUTE_UNUSED,
		aarch64_opnd_info *	info,
		const aarch64_insn	code,
		const aarch64_inst *	inst,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 476 of file aarch64-dis.c.

{
  aarch64_insn value;
 
  /* Rt */
  info->reglist.first_regno = extract_field (FLD_Rt, code, 0);
  /* S */
  value = extract_field (FLD_S, code, 0);
 
  /* Number of registers is equal to the number of elements in
     each structure to be loaded/stored.  */
  info->reglist.num_regs = get_opcode_dependent_value (inst->opcode);
  assert (info->reglist.num_regs >= 1 && info->reglist.num_regs <= 4);
 
  /* Except when it is LD1R.  */
  if (info->reglist.num_regs == 1 && value == (aarch64_insn) 1)
    info->reglist.num_regs = 2;
 
  return TRUE;
}

References assert(), extract_field(), FLD_Rt, FLD_S, get_opcode_dependent_value(), info(), aarch64_inst::opcode, TRUE, and value.

Referenced by aarch64_extract_operand().

aarch64_ext_limm()

bfd_boolean aarch64_ext_limm	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		const aarch64_insn	code,
		const aarch64_inst *	inst,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 918 of file aarch64-dis.c.

{
  uint32_t esize;
  aarch64_insn value;
 
  value = extract_fields (code, 0, 3, self->fields[0], self->fields[1],
              self->fields[2]);
  esize = aarch64_get_qualifier_esize (inst->operands[0].qualifier);
  return decode_limm (esize, value, &info->imm.value);
}

References aarch64_get_qualifier_esize(), decode_limm(), extract_fields(), info(), aarch64_inst::operands, aarch64_opnd_info::qualifier, and value.

Referenced by aarch64_ext_inv_limm(), aarch64_ext_sve_limm_mov(), and aarch64_extract_operand().

aarch64_ext_prfop()

bfd_boolean aarch64_ext_prfop	(	const aarch64_operand *self	ATTRIBUTE_UNUSED,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 1295 of file aarch64-dis.c.

{
  /* prfop in Rt */
  info->prfop = aarch64_prfops + extract_field (FLD_Rt, code, 0);
  return TRUE;
}

References aarch64_prfops, extract_field(), FLD_Rt, info(), and TRUE.

Referenced by aarch64_extract_operand().

aarch64_ext_pstatefield()

bfd_boolean aarch64_ext_pstatefield	(	const aarch64_operand *self	ATTRIBUTE_UNUSED,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 1223 of file aarch64-dis.c.

{
  int i;
  /* op1:op2 */
  info->pstatefield = extract_fields (code, 0, 2, FLD_op1, FLD_op2);
  for (i = 0; aarch64_pstatefields[i].name; i++)
    if (aarch64_pstatefields[i].value == (aarch64_insn)info->pstatefield)
      return TRUE;
  /* Reserved value in <pstatefield>.  */
  return FALSE;
}

References aarch64_pstatefields, extract_fields(), FALSE, FLD_op1, FLD_op2, i, info(), aarch64_sys_reg::name, TRUE, and value.

Referenced by aarch64_extract_operand().

aarch64_ext_reg_extended()

bfd_boolean aarch64_ext_reg_extended	(	const aarch64_operand *self	ATTRIBUTE_UNUSED,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 1336 of file aarch64-dis.c.

{
  aarch64_insn value;
 
  /* Rm */
  info->reg.regno = extract_field (FLD_Rm, code, 0);
  /* option */
  value = extract_field (FLD_option, code, 0);
  info->shifter.kind =
    aarch64_get_operand_modifier_from_value (value, TRUE /* extend_p */);
  /* imm3 */
  info->shifter.amount = extract_field (FLD_imm3, code,  0);
 
  /* This makes the constraint checking happy.  */
  info->shifter.operator_present = 1;
 
  /* Assume inst->operands[0].qualifier has been resolved.  */
  assert (inst->operands[0].qualifier != AARCH64_OPND_QLF_NIL);
  info->qualifier = AARCH64_OPND_QLF_W;
  if (inst->operands[0].qualifier == AARCH64_OPND_QLF_X
      && (info->shifter.kind == AARCH64_MOD_UXTX
      || info->shifter.kind == AARCH64_MOD_SXTX))
    info->qualifier = AARCH64_OPND_QLF_X;
 
  return TRUE;
}

References aarch64_get_operand_modifier_from_value(), AARCH64_MOD_SXTX, AARCH64_MOD_UXTX, AARCH64_OPND_QLF_NIL, AARCH64_OPND_QLF_W, AARCH64_OPND_QLF_X, assert(), extract_field(), FLD_imm3, FLD_option, FLD_Rm, info(), TRUE, and value.

Referenced by aarch64_extract_operand().

aarch64_ext_reg_shifted()

bfd_boolean aarch64_ext_reg_shifted	(	const aarch64_operand *self	ATTRIBUTE_UNUSED,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 1370 of file aarch64-dis.c.

{
  aarch64_insn value;
 
  /* Rm */
  info->reg.regno = extract_field (FLD_Rm, code, 0);
  /* shift */
  value = extract_field (FLD_shift, code, 0);
  info->shifter.kind =
    aarch64_get_operand_modifier_from_value (value, FALSE /* extend_p */);
  if (info->shifter.kind == AARCH64_MOD_ROR
      && inst->opcode->iclass != log_shift)
    /* ROR is not available for the shifted register operand in arithmetic
       instructions.  */
    return FALSE;
  /* imm6 */
  info->shifter.amount = extract_field (FLD_imm6, code,  0);
 
  /* This makes the constraint checking happy.  */
  info->shifter.operator_present = 1;
 
  return TRUE;
}

References aarch64_get_operand_modifier_from_value(), AARCH64_MOD_ROR, extract_field(), FALSE, FLD_imm6, FLD_Rm, FLD_shift, info(), log_shift, TRUE, and value.

Referenced by aarch64_extract_operand().

aarch64_ext_reglane()

bfd_boolean aarch64_ext_reglane	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		const aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 304 of file aarch64-dis.c.

{
  /* regno */
  info->reglane.regno = extract_field (self->fields[0], code,
                       inst->opcode->mask);
 
  /* Index and/or type.  */
  if (inst->opcode->iclass == asisdone
    || inst->opcode->iclass == asimdins)
    {
      if (info->type == AARCH64_OPND_En
      && inst->opcode->operands[0] == AARCH64_OPND_Ed)
    {
      unsigned shift;
      /* index2 for e.g. INS <Vd>.<Ts>[<index1>], <Vn>.<Ts>[<index2>].  */
      assert (info->idx == 1);  /* Vn */
      aarch64_insn value = extract_field (FLD_imm4, code, 0);
      /* Depend on AARCH64_OPND_Ed to determine the qualifier.  */
      info->qualifier = get_expected_qualifier (inst, info->idx);
      shift = get_logsz (aarch64_get_qualifier_esize (info->qualifier));
      info->reglane.index = value >> shift;
    }
      else
    {
      /* index and type for e.g. DUP <V><d>, <Vn>.<T>[<index>].
         imm5<3:0>  <V>
         0000   RESERVED
         xxx1   B
         xx10   H
         x100   S
         1000   D  */
      int pos = -1;
      aarch64_insn value = extract_field (FLD_imm5, code, 0);
      while (++pos <= 3 && (value & 0x1) == 0)
        value >>= 1;
      if (pos > 3)
        return FALSE;
      info->qualifier = get_sreg_qualifier_from_value (pos);
      info->reglane.index = (unsigned) (value >> 1);
    }
    }
  else if (inst->opcode->iclass == dotproduct)
    {
      /* Need information in other operand(s) to help decoding.  */
      info->qualifier = get_expected_qualifier (inst, info->idx);
      switch (info->qualifier)
    {
    case AARCH64_OPND_QLF_S_4B:
      /* L:H */
      info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L);
      info->reglane.regno &= 0x1f;
      break;
    default:
      return FALSE;
    }
    }
  else if (inst->opcode->iclass == cryptosm3)
    {
      /* index for e.g. SM3TT2A <Vd>.4S, <Vn>.4S, <Vm>S[<imm2>].  */
      info->reglane.index = extract_field (FLD_SM3_imm2, code, 0);
    }
  else
    {
      /* Index only for e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]
         or SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>].  */
 
      /* Need information in other operand(s) to help decoding.  */
      info->qualifier = get_expected_qualifier (inst, info->idx);
      switch (info->qualifier)
    {
    case AARCH64_OPND_QLF_S_H:
      if (info->type == AARCH64_OPND_Em16)
        {
          /* h:l:m */
          info->reglane.index = extract_fields (code, 0, 3, FLD_H, FLD_L,
                            FLD_M);
          info->reglane.regno &= 0xf;
        }
      else
        {
          /* h:l */
          info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L);
        }
      break;
    case AARCH64_OPND_QLF_S_S:
      /* h:l */
      info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L);
      break;
    case AARCH64_OPND_QLF_S_D:
      /* H */
      info->reglane.index = extract_field (FLD_H, code, 0);
      break;
    default:
      return FALSE;
    }
 
      if (inst->opcode->op == OP_FCMLA_ELEM
      && info->qualifier != AARCH64_OPND_QLF_S_H)
    {
      /* Complex operand takes two elements.  */
      if (info->reglane.index & 1)
        return FALSE;
      info->reglane.index /= 2;
    }
    }
 
  return TRUE;
}

References aarch64_get_qualifier_esize(), AARCH64_OPND_Ed, AARCH64_OPND_Em16, AARCH64_OPND_En, AARCH64_OPND_QLF_S_4B, AARCH64_OPND_QLF_S_D, AARCH64_OPND_QLF_S_H, AARCH64_OPND_QLF_S_S, asimdins, asisdone, assert(), cryptosm3, dotproduct, extract_field(), extract_fields(), FALSE, FLD_H, FLD_imm4, FLD_imm5, FLD_L, FLD_M, FLD_SM3_imm2, get_expected_qualifier(), get_logsz(), get_sreg_qualifier_from_value(), info(), OP_FCMLA_ELEM, pos, shift(), TRUE, rz_bin_info_t::type, unsigned, and value.

Referenced by aarch64_extract_operand().

aarch64_ext_reglist()

bfd_boolean aarch64_ext_reglist	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		const aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 417 of file aarch64-dis.c.

{
  /* R */
  info->reglist.first_regno = extract_field (self->fields[0], code, 0);
  /* len */
  info->reglist.num_regs = extract_field (FLD_len, code, 0) + 1;
  return TRUE;
}

References extract_field(), FLD_len, info(), and TRUE.

Referenced by aarch64_extract_operand().

aarch64_ext_regno()

bfd_boolean aarch64_ext_regno	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		const aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 262 of file aarch64-dis.c.

{
  info->reg.regno = extract_field (self->fields[0], code, 0);
  return TRUE;
}

References extract_field(), info(), and TRUE.

Referenced by aarch64_extract_operand().

aarch64_ext_regno_pair()

bfd_boolean aarch64_ext_regno_pair	(	const aarch64_operand *self	ATTRIBUTE_UNUSED,
		aarch64_opnd_info *	info,
		const aarch64_insn code	ATTRIBUTE_UNUSED,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 272 of file aarch64-dis.c.

{
  assert (info->idx == 1
      || info->idx ==3);
  info->reg.regno = inst->operands[info->idx - 1].reg.regno + 1;
  return TRUE;
}

References assert(), info(), and TRUE.

Referenced by aarch64_extract_operand().

aarch64_ext_regrt_sysins()

bfd_boolean aarch64_ext_regrt_sysins	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		const aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 285 of file aarch64-dis.c.

{
  info->reg.regno = extract_field (self->fields[0], code, 0);
  assert (info->idx == 1
      && (aarch64_get_operand_class (inst->operands[0].type)
          == AARCH64_OPND_CLASS_SYSTEM));
  /* This will make the constraint checking happy and more importantly will
     help the disassembler determine whether this operand is optional or
     not.  */
  info->present = aarch64_sys_ins_reg_has_xt (inst->operands[0].sysins_op);
 
  return TRUE;
}

References aarch64_get_operand_class(), AARCH64_OPND_CLASS_SYSTEM, aarch64_sys_ins_reg_has_xt(), assert(), extract_field(), info(), and TRUE.

Referenced by aarch64_extract_operand().

aarch64_ext_shll_imm()

bfd_boolean aarch64_ext_shll_imm	(	const aarch64_operand *self	ATTRIBUTE_UNUSED,
		aarch64_opnd_info *	info,
		const aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 637 of file aarch64-dis.c.

{
  int64_t imm;
  aarch64_insn val;
  val = extract_field (FLD_size, code, 0);
  switch (val)
    {
    case 0: imm = 8; break;
    case 1: imm = 16; break;
    case 2: imm = 32; break;
    default: return FALSE;
    }
  info->imm.value = imm;
  return TRUE;
}

References extract_field(), FALSE, FLD_size, imm, info(), TRUE, and val.

Referenced by aarch64_extract_operand().

aarch64_ext_simd_addr_post()

bfd_boolean aarch64_ext_simd_addr_post	(	const aarch64_operand *self	ATTRIBUTE_UNUSED,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *	inst,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 1146 of file aarch64-dis.c.

{
  /* The opcode dependent area stores the number of elements in
     each structure to be loaded/stored.  */
  int is_ld1r = get_opcode_dependent_value (inst->opcode) == 1;
 
  /* Rn */
  info->addr.base_regno = extract_field (FLD_Rn, code, 0);
  /* Rm | #<amount>  */
  info->addr.offset.regno = extract_field (FLD_Rm, code, 0);
  if (info->addr.offset.regno == 31)
    {
      if (inst->opcode->operands[0] == AARCH64_OPND_LVt_AL)
    /* Special handling of loading single structure to all lane.  */
    info->addr.offset.imm = (is_ld1r ? 1
                 : inst->operands[0].reglist.num_regs)
      * aarch64_get_qualifier_esize (inst->operands[0].qualifier);
      else
    info->addr.offset.imm = inst->operands[0].reglist.num_regs
      * aarch64_get_qualifier_esize (inst->operands[0].qualifier)
      * aarch64_get_qualifier_nelem (inst->operands[0].qualifier);
    }
  else
    info->addr.offset.is_reg = 1;
  info->addr.writeback = 1;
 
  return TRUE;
}

References aarch64_get_qualifier_esize(), aarch64_get_qualifier_nelem(), AARCH64_OPND_LVt_AL, extract_field(), FLD_Rm, FLD_Rn, get_opcode_dependent_value(), info(), aarch64_inst::opcode, aarch64_opcode::operands, aarch64_inst::operands, aarch64_opnd_info::qualifier, aarch64_opnd_info::reglist, and TRUE.

Referenced by aarch64_extract_operand().

aarch64_ext_sve_addr_reg_imm()

static bfd_boolean aarch64_ext_sve_addr_reg_imm ( const aarch64_operand *  self, aarch64_opnd_info *  info, aarch64_insn  code, int64_t  offset  )

static

Definition at line 1477 of file aarch64-dis.c.

{
  info->addr.base_regno = extract_field (self->fields[0], code, 0);
  info->addr.offset.imm = offset * (1 << get_operand_specific_data (self));
  info->addr.offset.is_reg = FALSE;
  info->addr.writeback = FALSE;
  info->addr.preind = TRUE;
  info->shifter.operator_present = FALSE;
  info->shifter.amount_present = FALSE;
  return TRUE;
}

References extract_field(), FALSE, get_operand_specific_data(), info(), and TRUE.

Referenced by aarch64_ext_sve_addr_ri_s4(), aarch64_ext_sve_addr_ri_u6(), and aarch64_ext_sve_addr_zi_u5().

aarch64_ext_sve_addr_reg_mul_vl()

static bfd_boolean aarch64_ext_sve_addr_reg_mul_vl ( const aarch64_operand *  self, aarch64_opnd_info *  info, aarch64_insn  code, int64_t  offset  )

static

Definition at line 1403 of file aarch64-dis.c.

{
  info->addr.base_regno = extract_field (self->fields[0], code, 0);
  info->addr.offset.imm = offset * (1 + get_operand_specific_data (self));
  info->addr.offset.is_reg = FALSE;
  info->addr.writeback = FALSE;
  info->addr.preind = TRUE;
  if (offset != 0)
    info->shifter.kind = AARCH64_MOD_MUL_VL;
  info->shifter.amount = 1;
  info->shifter.operator_present = (info->addr.offset.imm != 0);
  info->shifter.amount_present = FALSE;
  return TRUE;
}

References AARCH64_MOD_MUL_VL, extract_field(), FALSE, get_operand_specific_data(), info(), and TRUE.

Referenced by aarch64_ext_sve_addr_ri_s4xvl(), aarch64_ext_sve_addr_ri_s6xvl(), and aarch64_ext_sve_addr_ri_s9xvl().

aarch64_ext_sve_addr_ri_s4()

bfd_boolean aarch64_ext_sve_addr_ri_s4	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 1495 of file aarch64-dis.c.

{
  int offset = sign_extend (extract_field (FLD_SVE_imm4, code, 0), 3);
  return aarch64_ext_sve_addr_reg_imm (self, info, code, offset);
}

References aarch64_ext_sve_addr_reg_imm(), extract_field(), FLD_SVE_imm4, info(), and sign_extend().

Referenced by aarch64_extract_operand().

aarch64_ext_sve_addr_ri_s4xvl()

bfd_boolean aarch64_ext_sve_addr_ri_s4xvl	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 1425 of file aarch64-dis.c.

{
  int offset;
 
  offset = extract_field (FLD_SVE_imm4, code, 0);
  offset = ((offset + 8) & 15) - 8;
  return aarch64_ext_sve_addr_reg_mul_vl (self, info, code, offset);
}

References aarch64_ext_sve_addr_reg_mul_vl(), extract_field(), FLD_SVE_imm4, and info().

Referenced by aarch64_extract_operand().

aarch64_ext_sve_addr_ri_s6xvl()

bfd_boolean aarch64_ext_sve_addr_ri_s6xvl	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 1442 of file aarch64-dis.c.

{
  int offset;
 
  offset = extract_field (FLD_SVE_imm6, code, 0);
  offset = (((offset + 32) & 63) - 32);
  return aarch64_ext_sve_addr_reg_mul_vl (self, info, code, offset);
}

References aarch64_ext_sve_addr_reg_mul_vl(), extract_field(), FLD_SVE_imm6, and info().

Referenced by aarch64_extract_operand().

aarch64_ext_sve_addr_ri_s9xvl()

bfd_boolean aarch64_ext_sve_addr_ri_s9xvl	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 1460 of file aarch64-dis.c.

{
  int offset;
 
  offset = extract_fields (code, 0, 2, FLD_SVE_imm6, FLD_imm3);
  offset = (((offset + 256) & 511) - 256);
  return aarch64_ext_sve_addr_reg_mul_vl (self, info, code, offset);
}

References aarch64_ext_sve_addr_reg_mul_vl(), extract_fields(), FLD_imm3, FLD_SVE_imm6, and info().

Referenced by aarch64_extract_operand().

aarch64_ext_sve_addr_ri_u6()

bfd_boolean aarch64_ext_sve_addr_ri_u6	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 1508 of file aarch64-dis.c.

{
  int offset = extract_field (FLD_SVE_imm6, code, 0);
  return aarch64_ext_sve_addr_reg_imm (self, info, code, offset);
}

References aarch64_ext_sve_addr_reg_imm(), extract_field(), FLD_SVE_imm6, and info().

Referenced by aarch64_extract_operand().

aarch64_ext_sve_addr_rr_lsl()

bfd_boolean aarch64_ext_sve_addr_rr_lsl	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 1521 of file aarch64-dis.c.

{
  int index_regno;
 
  index_regno = extract_field (self->fields[1], code, 0);
  if (index_regno == 31 && (self->flags & OPD_F_NO_ZR) != 0)
    return FALSE;
 
  info->addr.base_regno = extract_field (self->fields[0], code, 0);
  info->addr.offset.regno = index_regno;
  info->addr.offset.is_reg = TRUE;
  info->addr.writeback = FALSE;
  info->addr.preind = TRUE;
  info->shifter.kind = AARCH64_MOD_LSL;
  info->shifter.amount = get_operand_specific_data (self);
  info->shifter.operator_present = (info->shifter.amount != 0);
  info->shifter.amount_present = (info->shifter.amount != 0);
  return TRUE;
}

References AARCH64_MOD_LSL, extract_field(), FALSE, get_operand_specific_data(), info(), OPD_F_NO_ZR, and TRUE.

Referenced by aarch64_extract_operand().

aarch64_ext_sve_addr_rz_xtw()

bfd_boolean aarch64_ext_sve_addr_rz_xtw	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 1549 of file aarch64-dis.c.

{
  info->addr.base_regno = extract_field (self->fields[0], code, 0);
  info->addr.offset.regno = extract_field (self->fields[1], code, 0);
  info->addr.offset.is_reg = TRUE;
  info->addr.writeback = FALSE;
  info->addr.preind = TRUE;
  if (extract_field (self->fields[2], code, 0))
    info->shifter.kind = AARCH64_MOD_SXTW;
  else
    info->shifter.kind = AARCH64_MOD_UXTW;
  info->shifter.amount = get_operand_specific_data (self);
  info->shifter.operator_present = TRUE;
  info->shifter.amount_present = (info->shifter.amount != 0);
  return TRUE;
}

References AARCH64_MOD_SXTW, AARCH64_MOD_UXTW, extract_field(), FALSE, get_operand_specific_data(), info(), and TRUE.

Referenced by aarch64_extract_operand().

aarch64_ext_sve_addr_zi_u5()

bfd_boolean aarch64_ext_sve_addr_zi_u5	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 1573 of file aarch64-dis.c.

{
  int offset = extract_field (FLD_imm5, code, 0);
  return aarch64_ext_sve_addr_reg_imm (self, info, code, offset);
}

References aarch64_ext_sve_addr_reg_imm(), extract_field(), FLD_imm5, and info().

Referenced by aarch64_extract_operand().

aarch64_ext_sve_addr_zz()

static bfd_boolean aarch64_ext_sve_addr_zz ( const aarch64_operand *  self, aarch64_opnd_info *  info, aarch64_insn  code, enum aarch64_modifier_kind  kind  )

static

Definition at line 1587 of file aarch64-dis.c.

{
  info->addr.base_regno = extract_field (self->fields[0], code, 0);
  info->addr.offset.regno = extract_field (self->fields[1], code, 0);
  info->addr.offset.is_reg = TRUE;
  info->addr.writeback = FALSE;
  info->addr.preind = TRUE;
  info->shifter.kind = kind;
  info->shifter.amount = extract_field (FLD_SVE_msz, code, 0);
  info->shifter.operator_present = (kind != AARCH64_MOD_LSL
                    || info->shifter.amount != 0);
  info->shifter.amount_present = (info->shifter.amount != 0);
  return TRUE;
}

References AARCH64_MOD_LSL, extract_field(), FALSE, FLD_SVE_msz, info(), and TRUE.

Referenced by aarch64_ext_sve_addr_zz_lsl(), aarch64_ext_sve_addr_zz_sxtw(), and aarch64_ext_sve_addr_zz_uxtw().

aarch64_ext_sve_addr_zz_lsl()

bfd_boolean aarch64_ext_sve_addr_zz_lsl	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 1607 of file aarch64-dis.c.

{
  return aarch64_ext_sve_addr_zz (self, info, code, AARCH64_MOD_LSL);
}

References aarch64_ext_sve_addr_zz(), AARCH64_MOD_LSL, and info().

Referenced by aarch64_extract_operand().

aarch64_ext_sve_addr_zz_sxtw()

bfd_boolean aarch64_ext_sve_addr_zz_sxtw	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 1619 of file aarch64-dis.c.

{
  return aarch64_ext_sve_addr_zz (self, info, code, AARCH64_MOD_SXTW);
}

References aarch64_ext_sve_addr_zz(), AARCH64_MOD_SXTW, and info().

Referenced by aarch64_extract_operand().

aarch64_ext_sve_addr_zz_uxtw()

bfd_boolean aarch64_ext_sve_addr_zz_uxtw	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 1631 of file aarch64-dis.c.

{
  return aarch64_ext_sve_addr_zz (self, info, code, AARCH64_MOD_UXTW);
}

References aarch64_ext_sve_addr_zz(), AARCH64_MOD_UXTW, and info().

Referenced by aarch64_extract_operand().

aarch64_ext_sve_aimm()

bfd_boolean aarch64_ext_sve_aimm	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		const aarch64_insn	code,
		const aarch64_inst *	inst,
		aarch64_operand_error *	errors
	)

Definition at line 1662 of file aarch64-dis.c.

{
  return (aarch64_ext_imm (self, info, code, inst, errors)
      && decode_sve_aimm (info, (uint8_t) info->imm.value));
}

References aarch64_ext_imm(), decode_sve_aimm(), and info().

Referenced by aarch64_extract_operand().

aarch64_ext_sve_asimm()

bfd_boolean aarch64_ext_sve_asimm	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		const aarch64_insn	code,
		const aarch64_inst *	inst,
		aarch64_operand_error *	errors
	)

Definition at line 1673 of file aarch64-dis.c.

{
  return (aarch64_ext_imm (self, info, code, inst, errors)
      && decode_sve_aimm (info, (int8_t) info->imm.value));
}

References aarch64_ext_imm(), decode_sve_aimm(), and info().

Referenced by aarch64_extract_operand().

aarch64_ext_sve_float_half_one()

bfd_boolean aarch64_ext_sve_float_half_one	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 1685 of file aarch64-dis.c.

{
  if (extract_field (self->fields[0], code, 0))
    info->imm.value = 0x3f800000;
  else
    info->imm.value = 0x3f000000;
  info->imm.is_fp = TRUE;
  return TRUE;
}

References extract_field(), info(), and TRUE.

Referenced by aarch64_extract_operand().

aarch64_ext_sve_float_half_two()

bfd_boolean aarch64_ext_sve_float_half_two	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 1701 of file aarch64-dis.c.

{
  if (extract_field (self->fields[0], code, 0))
    info->imm.value = 0x40000000;
  else
    info->imm.value = 0x3f000000;
  info->imm.is_fp = TRUE;
  return TRUE;
}

References extract_field(), info(), and TRUE.

Referenced by aarch64_extract_operand().

aarch64_ext_sve_float_zero_one()

bfd_boolean aarch64_ext_sve_float_zero_one	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 1717 of file aarch64-dis.c.

{
  if (extract_field (self->fields[0], code, 0))
    info->imm.value = 0x3f800000;
  else
    info->imm.value = 0x0;
  info->imm.is_fp = TRUE;
  return TRUE;
}

References extract_field(), info(), and TRUE.

Referenced by aarch64_extract_operand().

aarch64_ext_sve_index()

bfd_boolean aarch64_ext_sve_index	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 1735 of file aarch64-dis.c.

{
  int val;
 
  info->reglane.regno = extract_field (self->fields[0], code, 0);
  val = extract_fields (code, 0, 2, FLD_SVE_tszh, FLD_imm5);
  if ((val & 31) == 0)
    return 0;
  while ((val & 1) == 0)
    val /= 2;
  info->reglane.index = val / 2;
  return TRUE;
}

References extract_field(), extract_fields(), FLD_imm5, FLD_SVE_tszh, info(), TRUE, and val.

Referenced by aarch64_extract_operand().

aarch64_ext_sve_limm_mov()

bfd_boolean aarch64_ext_sve_limm_mov	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		const aarch64_insn	code,
		const aarch64_inst *	inst,
		aarch64_operand_error *	errors
	)

Definition at line 1754 of file aarch64-dis.c.

{
  int esize = aarch64_get_qualifier_esize (inst->operands[0].qualifier);
  return (aarch64_ext_limm (self, info, code, inst, errors)
      && aarch64_sve_dupm_mov_immediate_p (info->imm.value, esize));
}

References aarch64_ext_limm(), aarch64_get_qualifier_esize(), aarch64_sve_dupm_mov_immediate_p(), info(), aarch64_inst::operands, and aarch64_opnd_info::qualifier.

Referenced by aarch64_extract_operand().

aarch64_ext_sve_quad_index()

bfd_boolean aarch64_ext_sve_quad_index	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 1768 of file aarch64-dis.c.

{
  unsigned int reg_bits = get_operand_specific_data (self);
  unsigned int val = extract_all_fields (self, code);
  info->reglane.regno = val & ((1 << reg_bits) - 1);
  info->reglane.index = val >> reg_bits;
  return TRUE;
}

References extract_all_fields(), get_operand_specific_data(), info(), reg_bits(), TRUE, and val.

Referenced by aarch64_extract_operand().

aarch64_ext_sve_reglist()

bfd_boolean aarch64_ext_sve_reglist	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 1784 of file aarch64-dis.c.

{
  info->reglist.first_regno = extract_field (self->fields[0], code, 0);
  info->reglist.num_regs = get_opcode_dependent_value (inst->opcode);
  return TRUE;
}

References extract_field(), get_opcode_dependent_value(), info(), and TRUE.

Referenced by aarch64_extract_operand().

aarch64_ext_sve_scale()

bfd_boolean aarch64_ext_sve_scale	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *	inst,
		aarch64_operand_error *	errors
	)

Definition at line 1798 of file aarch64-dis.c.

{
  int val;
 
  if (!aarch64_ext_imm (self, info, code, inst, errors))
    return FALSE;
  val = extract_field (FLD_SVE_imm4, code, 0);
  info->shifter.kind = AARCH64_MOD_MUL;
  info->shifter.amount = val + 1;
  info->shifter.operator_present = (val != 0);
  info->shifter.amount_present = (val != 0);
  return TRUE;
}

References aarch64_ext_imm(), AARCH64_MOD_MUL, extract_field(), FALSE, FLD_SVE_imm4, info(), TRUE, and val.

Referenced by aarch64_extract_operand().

aarch64_ext_sve_shlimm()

bfd_boolean aarch64_ext_sve_shlimm	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		const aarch64_insn	code,
		const aarch64_inst *	inst,
		aarch64_operand_error *	errors
	)

Definition at line 1826 of file aarch64-dis.c.

{
  if (!aarch64_ext_imm (self, info, code, inst, errors)
      || info->imm.value == 0)
    return FALSE;
 
  info->imm.value -= get_top_bit (info->imm.value);
  return TRUE;
}

References aarch64_ext_imm(), FALSE, get_top_bit(), info(), and TRUE.

Referenced by aarch64_extract_operand().

aarch64_ext_sve_shrimm()

bfd_boolean aarch64_ext_sve_shrimm	(	const aarch64_operand *	self,
		aarch64_opnd_info *	info,
		const aarch64_insn	code,
		const aarch64_inst *	inst,
		aarch64_operand_error *	errors
	)

Definition at line 1840 of file aarch64-dis.c.

{
  if (!aarch64_ext_imm (self, info, code, inst, errors)
      || info->imm.value == 0)
    return FALSE;
 
  info->imm.value = get_top_bit (info->imm.value) * 2 - info->imm.value;
  return TRUE;
}

References aarch64_ext_imm(), FALSE, get_top_bit(), info(), and TRUE.

Referenced by aarch64_extract_operand().

aarch64_ext_sysins_op()

bfd_boolean aarch64_ext_sysins_op	(	const aarch64_operand *self	ATTRIBUTE_UNUSED,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 1240 of file aarch64-dis.c.

{
  int i;
  aarch64_insn value;
  const aarch64_sys_ins_reg *sysins_ops;
  /* op0:op1:CRn:CRm:op2 */
  value = extract_fields (code, 0, 5,
              FLD_op0, FLD_op1, FLD_CRn,
              FLD_CRm, FLD_op2);
 
  switch (info->type)
    {
    case AARCH64_OPND_SYSREG_AT: sysins_ops = aarch64_sys_regs_at; break;
    case AARCH64_OPND_SYSREG_DC: sysins_ops = aarch64_sys_regs_dc; break;
    case AARCH64_OPND_SYSREG_IC: sysins_ops = aarch64_sys_regs_ic; break;
    case AARCH64_OPND_SYSREG_TLBI: sysins_ops = aarch64_sys_regs_tlbi; break;
    default: assert (0); return FALSE;
    }
 
  for (i = 0; sysins_ops[i].name; i++)
    if (sysins_ops[i].value == value)
      {
    info->sysins_op = sysins_ops + i;
    DEBUG_TRACE ("%s found value: %x, has_xt: %d, i: %d.",
             info->sysins_op->name,
             (unsigned)info->sysins_op->value,
             aarch64_sys_ins_reg_has_xt (info->sysins_op), i);
    return TRUE;
      }
 
  return FALSE;
}

References AARCH64_OPND_SYSREG_AT, AARCH64_OPND_SYSREG_DC, AARCH64_OPND_SYSREG_IC, AARCH64_OPND_SYSREG_TLBI, aarch64_sys_ins_reg_has_xt(), aarch64_sys_regs_at, aarch64_sys_regs_dc, aarch64_sys_regs_ic, aarch64_sys_regs_tlbi, assert(), DEBUG_TRACE, extract_fields(), FALSE, FLD_CRm, FLD_CRn, FLD_op0, FLD_op1, FLD_op2, i, info(), aarch64_sys_ins_reg::name, TRUE, rz_bin_info_t::type, and value.

Referenced by aarch64_extract_operand().

aarch64_ext_sysreg()

bfd_boolean aarch64_ext_sysreg	(	const aarch64_operand *self	ATTRIBUTE_UNUSED,
		aarch64_opnd_info *	info,
		aarch64_insn	code,
		const aarch64_inst *inst	ATTRIBUTE_UNUSED,
		aarch64_operand_error *errors	ATTRIBUTE_UNUSED
	)

Definition at line 1194 of file aarch64-dis.c.

{
  /* op0:op1:CRn:CRm:op2 */
  info->sysreg.value = extract_fields (code, 0, 5, FLD_op0, FLD_op1, FLD_CRn,
                       FLD_CRm, FLD_op2);
  info->sysreg.flags = 0;
 
  /* If a system instruction, check which restrictions should be on the register
     value during decoding, these will be enforced then.  */
  if (inst->opcode->iclass == ic_system)
    {
      /* Check to see if it's read-only, else check if it's write only.
     if it's both or unspecified don't care.  */
      if ((inst->opcode->flags & (F_SYS_READ | F_SYS_WRITE)) == F_SYS_READ)
    info->sysreg.flags = F_REG_READ;
      else if ((inst->opcode->flags & (F_SYS_READ | F_SYS_WRITE))
           == F_SYS_WRITE)
    info->sysreg.flags = F_REG_WRITE;
    }
 
  return TRUE;
}

References extract_fields(), F_REG_READ, F_REG_WRITE, F_SYS_READ, F_SYS_WRITE, FLD_CRm, FLD_CRn, FLD_op0, FLD_op1, FLD_op2, ic_system, info(), and TRUE.

Referenced by aarch64_extract_operand().

aarch64_opcode_decode()

static bfd_boolean aarch64_opcode_decode ( const aarch64_opcode *  opcode, const aarch64_insn  code, aarch64_inst *  inst, int  noaliases_p, aarch64_operand_error *  errors  )

static

Definition at line 2835 of file aarch64-dis.c.

{
  int i;
 
  DEBUG_TRACE ("enter with %s", opcode->name);
 
  assert (opcode && inst);
 
  /* Clear inst.  */
  memset (inst, '\0', sizeof (aarch64_inst));
 
  /* Check the base opcode.  */
  if ((code & opcode->mask) != (opcode->opcode & opcode->mask))
    {
      DEBUG_TRACE ("base opcode match FAIL");
      goto decode_fail;
    }
 
  inst->opcode = opcode;
  inst->value = code;
 
  /* Assign operand codes and indexes.  */
  for (i = 0; i < AARCH64_MAX_OPND_NUM; i++)
    {
      if (opcode->operands[i] == AARCH64_OPND_NIL)
    break;
      inst->operands[i].type = opcode->operands[i];
      inst->operands[i].idx = i;
    }
 
  /* Call the opcode decoder indicated by flags.  */
  if (opcode_has_special_coder (opcode) && do_special_decoding (inst) == 0)
    {
      DEBUG_TRACE ("opcode flag-based decoder FAIL");
      goto decode_fail;
    }
 
  /* Possibly use the instruction class to determine the correct
     qualifier.  */
  if (!aarch64_decode_variant_using_iclass (inst))
    {
      DEBUG_TRACE ("iclass-based decoder FAIL");
      goto decode_fail;
    }
 
  /* Call operand decoders.  */
  for (i = 0; i < AARCH64_MAX_OPND_NUM; i++)
    {
      const aarch64_operand *opnd;
      enum aarch64_opnd type;
 
      type = opcode->operands[i];
      if (type == AARCH64_OPND_NIL)
    break;
      opnd = &aarch64_operands[type];
      if (operand_has_extractor (opnd)
      && (! aarch64_extract_operand (opnd, &inst->operands[i], code, inst,
                     errors)))
    {
      DEBUG_TRACE ("operand decoder FAIL at operand %d", i);
      goto decode_fail;
    }
    }
 
  /* If the opcode has a verifier, then check it now.  */
  if (opcode->verifier && ! opcode->verifier (opcode, code))
    {
      DEBUG_TRACE ("operand verifier FAIL");
      goto decode_fail;
    }
 
  /* Match the qualifiers.  */
  if (aarch64_match_operands_constraint (inst, NULL) == 1)
    {
      /* Arriving here, the CODE has been determined as a valid instruction
     of OPCODE and *INST has been filled with information of this OPCODE
     instruction.  Before the return, check if the instruction has any
     alias and should be disassembled in the form of its alias instead.
     If the answer is yes, *INST will be updated.  */
      if (!noaliases_p)
    determine_disassembling_preference (inst, errors);
      DEBUG_TRACE ("SUCCESS");
      return TRUE;
    }
  else
    {
      DEBUG_TRACE ("constraint matching FAIL");
    }
 
decode_fail:
  return FALSE;
}

References aarch64_decode_variant_using_iclass(), aarch64_extract_operand(), aarch64_match_operands_constraint(), AARCH64_MAX_OPND_NUM, aarch64_operands, AARCH64_OPND_NIL, assert(), code, DEBUG_TRACE, determine_disassembling_preference(), do_special_decoding(), FALSE, i, aarch64_opnd_info::idx, aarch64_opcode::mask, memset(), aarch64_opcode::name, NULL, aarch64_opcode::opcode, aarch64_inst::opcode, opcode_has_special_coder(), operand_has_extractor(), aarch64_opcode::operands, aarch64_inst::operands, TRUE, aarch64_opnd_info::type, type, aarch64_inst::value, and aarch64_opcode::verifier.

Referenced by aarch64_decode_insn(), and determine_disassembling_preference().

aarch64_symbol_is_valid()

bfd_boolean aarch64_symbol_is_valid	(	asymbol *	sym,
		struct disassemble_info *info	ATTRIBUTE_UNUSED
	)

Definition at line 3167 of file aarch64-dis.c.

{
  const char * name;
 
  if (sym == NULL)
    return FALSE;
 
  name = bfd_asymbol_name (sym);
 
  return name
    && (name[0] != '$'
    || (name[1] != 'x' && name[1] != 'd')
    || (name[2] != '\0' && name[2] != '.'));
}

References bfd_asymbol_name, FALSE, name, and NULL.

convert_bfm_to_bfc()

static int convert_bfm_to_bfc ( aarch64_inst *  inst )

static

Definition at line 2370 of file aarch64-dis.c.

{
  int64_t immr, imms, val;
 
  /* Should have been assured by the base opcode value.  */
  assert (inst->operands[1].reg.regno == 0x1f);
 
  immr = inst->operands[2].imm.value;
  imms = inst->operands[3].imm.value;
  val = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 32 : 64;
  if (imms < immr)
    {
      /* Drop XZR from the second operand.  */
      copy_operand_info (inst, 1, 2);
      copy_operand_info (inst, 2, 3);
      inst->operands[3].type = AARCH64_OPND_NIL;
 
      /* Recalculate the immediates.  */
      inst->operands[1].imm.value = (val - immr) & (val - 1);
      inst->operands[2].imm.value = imms + 1;
 
      /* The two opcodes have different qualifiers for the operands; reset to
     help the checking.  */
      reset_operand_qualifier (inst, 1);
      reset_operand_qualifier (inst, 2);
      reset_operand_qualifier (inst, 3);
 
      return 1;
    }
 
  return 0;
}

References AARCH64_OPND_NIL, AARCH64_OPND_QLF_imm_0_31, assert(), copy_operand_info(), aarch64_opnd_info::imm, aarch64_inst::operands, aarch64_opnd_info::qualifier, aarch64_opnd_info::reg, reset_operand_qualifier(), aarch64_opnd_info::type, and val.

Referenced by convert_to_alias().

convert_bfm_to_bfi()

static int convert_bfm_to_bfi ( aarch64_inst *  inst )

static

Definition at line 2343 of file aarch64-dis.c.

{
  int64_t immr, imms, val;
 
  immr = inst->operands[2].imm.value;
  imms = inst->operands[3].imm.value;
  val = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 32 : 64;
  if (imms < immr)
    {
      inst->operands[2].imm.value = (val - immr) & (val - 1);
      inst->operands[3].imm.value = imms + 1;
      /* The two opcodes have different qualifiers for
     the immediate operands; reset to help the checking.  */
      reset_operand_qualifier (inst, 2);
      reset_operand_qualifier (inst, 3);
      return 1;
    }
 
  return 0;
}

References AARCH64_OPND_QLF_imm_0_31, aarch64_opnd_info::imm, aarch64_inst::operands, aarch64_opnd_info::qualifier, reset_operand_qualifier(), and val.

Referenced by convert_to_alias().

convert_bfm_to_bfx()

static int convert_bfm_to_bfx ( aarch64_inst *  inst )

static

Definition at line 2316 of file aarch64-dis.c.

{
  int64_t immr, imms;
 
  immr = inst->operands[2].imm.value;
  imms = inst->operands[3].imm.value;
  if (imms >= immr)
    {
      int64_t lsb = immr;
      inst->operands[2].imm.value = lsb;
      inst->operands[3].imm.value = imms + 1 - lsb;
      /* The two opcodes have different qualifiers for
     the immediate operands; reset to help the checking.  */
      reset_operand_qualifier (inst, 2);
      reset_operand_qualifier (inst, 3);
      return 1;
    }
 
  return 0;
}

References aarch64_opnd_info::imm, aarch64_inst::operands, and reset_operand_qualifier().

Referenced by convert_to_alias().

convert_bfm_to_sr()

static int convert_bfm_to_sr ( aarch64_inst *  inst )

static

Definition at line 2280 of file aarch64-dis.c.

{
  int64_t imms, val;
 
  imms = inst->operands[3].imm.value;
  val = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 31 : 63;
  if (imms == val)
    {
      inst->operands[3].type = AARCH64_OPND_NIL;
      return 1;
    }
 
  return 0;
}

References AARCH64_OPND_NIL, AARCH64_OPND_QLF_imm_0_31, aarch64_opnd_info::imm, aarch64_inst::operands, aarch64_opnd_info::qualifier, aarch64_opnd_info::type, and val.

Referenced by convert_to_alias().

convert_csinc_to_cset()

static int convert_csinc_to_cset ( aarch64_inst *  inst )

static

Definition at line 2451 of file aarch64-dis.c.

{
  if (inst->operands[1].reg.regno == 0x1f
      && inst->operands[2].reg.regno == 0x1f
      && (inst->operands[3].cond->value & 0xe) != 0xe)
    {
      copy_operand_info (inst, 1, 3);
      inst->operands[1].cond = get_inverted_cond (inst->operands[3].cond);
      inst->operands[3].type = AARCH64_OPND_NIL;
      inst->operands[2].type = AARCH64_OPND_NIL;
      return 1;
    }
  return 0;
}

References AARCH64_OPND_NIL, aarch64_opnd_info::cond, copy_operand_info(), get_inverted_cond(), aarch64_inst::operands, aarch64_opnd_info::reg, aarch64_opnd_info::type, and aarch64_cond::value.

Referenced by convert_to_alias().

convert_extr_to_ror()

static int convert_extr_to_ror ( aarch64_inst *  inst )

static

Definition at line 2250 of file aarch64-dis.c.

{
  if (inst->operands[1].reg.regno == inst->operands[2].reg.regno)
    {
      copy_operand_info (inst, 2, 3);
      inst->operands[3].type = AARCH64_OPND_NIL;
      return 1;
    }
  return 0;
}

References AARCH64_OPND_NIL, copy_operand_info(), aarch64_inst::operands, aarch64_opnd_info::reg, and aarch64_opnd_info::type.

Referenced by convert_to_alias().

convert_from_csel()

static int convert_from_csel ( aarch64_inst *  inst )

static

Definition at line 2432 of file aarch64-dis.c.

{
  if (inst->operands[1].reg.regno == inst->operands[2].reg.regno
      && (inst->operands[3].cond->value & 0xe) != 0xe)
    {
      copy_operand_info (inst, 2, 3);
      inst->operands[2].cond = get_inverted_cond (inst->operands[3].cond);
      inst->operands[3].type = AARCH64_OPND_NIL;
      return 1;
    }
  return 0;
}

References AARCH64_OPND_NIL, aarch64_opnd_info::cond, copy_operand_info(), get_inverted_cond(), aarch64_inst::operands, aarch64_opnd_info::reg, aarch64_opnd_info::type, and aarch64_cond::value.

Referenced by convert_to_alias().

convert_movebitmask_to_mov()

static int convert_movebitmask_to_mov ( aarch64_inst *  inst )

static

Definition at line 2512 of file aarch64-dis.c.

{
  int is32;
  uint64_t value;
 
  /* Should have been assured by the base opcode value.  */
  assert (inst->operands[1].reg.regno == 0x1f);
  copy_operand_info (inst, 1, 2);
  is32 = inst->operands[0].qualifier == AARCH64_OPND_QLF_W;
  inst->operands[1].type = AARCH64_OPND_IMM_MOV;
  value = inst->operands[1].imm.value;
  /* ORR has an immediate that could be generated by a MOVZ or MOVN
     instruction.  */
  if (inst->operands[0].reg.regno != 0x1f
      && (aarch64_wide_constant_p (value, is32, NULL)
      || aarch64_wide_constant_p (~value, is32, NULL)))
    return 0;
 
  inst->operands[2].type = AARCH64_OPND_NIL;
  return 1;
}

References AARCH64_OPND_IMM_MOV, AARCH64_OPND_NIL, AARCH64_OPND_QLF_W, aarch64_wide_constant_p(), assert(), copy_operand_info(), aarch64_opnd_info::imm, NULL, aarch64_inst::operands, aarch64_opnd_info::qualifier, aarch64_opnd_info::reg, aarch64_opnd_info::type, and value.

Referenced by convert_to_alias().

convert_movewide_to_mov()

static int convert_movewide_to_mov ( aarch64_inst *  inst )

static

Definition at line 2477 of file aarch64-dis.c.

{
  uint64_t value = inst->operands[1].imm.value;
  /* MOVZ/MOVN #0 have a shift amount other than LSL #0.  */
  if (value == 0 && inst->operands[1].shifter.amount != 0)
    return 0;
  inst->operands[1].type = AARCH64_OPND_IMM_MOV;
  inst->operands[1].shifter.kind = AARCH64_MOD_NONE;
  value <<= inst->operands[1].shifter.amount;
  /* As an alias convertor, it has to be clear that the INST->OPCODE
     is the opcode of the real instruction.  */
  if (inst->opcode->op == OP_MOVN)
    {
      int is32 = inst->operands[0].qualifier == AARCH64_OPND_QLF_W;
      value = ~value;
      /* A MOVN has an immediate that could be encoded by MOVZ.  */
      if (aarch64_wide_constant_p (value, is32, NULL))
    return 0;
    }
  inst->operands[1].imm.value = value;
  inst->operands[1].shifter.amount = 0;
  return 1;
}

References AARCH64_MOD_NONE, AARCH64_OPND_IMM_MOV, AARCH64_OPND_QLF_W, aarch64_wide_constant_p(), aarch64_opnd_info::amount, aarch64_opnd_info::imm, aarch64_opnd_info::kind, NULL, aarch64_opcode::op, OP_MOVN, aarch64_inst::opcode, aarch64_inst::operands, aarch64_opnd_info::qualifier, aarch64_opnd_info::shifter, aarch64_opnd_info::type, and value.

Referenced by convert_to_alias().

convert_orr_to_mov()

static int convert_orr_to_mov ( aarch64_inst *  inst )

static

Definition at line 2297 of file aarch64-dis.c.

{
  /* MOV <Vd>.<T>, <Vn>.<T>
     is equivalent to:
     ORR <Vd>.<T>, <Vn>.<T>, <Vn>.<T>.  */
  if (inst->operands[1].reg.regno == inst->operands[2].reg.regno)
    {
      inst->operands[2].type = AARCH64_OPND_NIL;
      return 1;
    }
  return 0;
}

References AARCH64_OPND_NIL, aarch64_inst::operands, aarch64_opnd_info::reg, and aarch64_opnd_info::type.

Referenced by convert_to_alias().

convert_shll_to_xtl()

static int convert_shll_to_xtl ( aarch64_inst *  inst )

static

Definition at line 2265 of file aarch64-dis.c.

{
  if (inst->operands[2].imm.value == 0)
    {
      inst->operands[2].type = AARCH64_OPND_NIL;
      return 1;
    }
  return 0;
}

References AARCH64_OPND_NIL, aarch64_opnd_info::imm, aarch64_inst::operands, and aarch64_opnd_info::type.

Referenced by convert_to_alias().

convert_to_alias()

static int convert_to_alias ( aarch64_inst *  inst, const aarch64_opcode *  alias  )

static

Definition at line 2538 of file aarch64-dis.c.

{
  switch (alias->op)
    {
    case OP_ASR_IMM:
    case OP_LSR_IMM:
      return convert_bfm_to_sr (inst);
    case OP_LSL_IMM:
      return convert_ubfm_to_lsl (inst);
    case OP_CINC:
    case OP_CINV:
    case OP_CNEG:
      return convert_from_csel (inst);
    case OP_CSET:
    case OP_CSETM:
      return convert_csinc_to_cset (inst);
    case OP_UBFX:
    case OP_BFXIL:
    case OP_SBFX:
      return convert_bfm_to_bfx (inst);
    case OP_SBFIZ:
    case OP_BFI:
    case OP_UBFIZ:
      return convert_bfm_to_bfi (inst);
    case OP_BFC:
      return convert_bfm_to_bfc (inst);
    case OP_MOV_V:
      return convert_orr_to_mov (inst);
    case OP_MOV_IMM_WIDE:
    case OP_MOV_IMM_WIDEN:
      return convert_movewide_to_mov (inst);
    case OP_MOV_IMM_LOG:
      return convert_movebitmask_to_mov (inst);
    case OP_ROR_IMM:
      return convert_extr_to_ror (inst);
    case OP_SXTL:
    case OP_SXTL2:
    case OP_UXTL:
    case OP_UXTL2:
      return convert_shll_to_xtl (inst);
    default:
      return 0;
    }
}

References convert_bfm_to_bfc(), convert_bfm_to_bfi(), convert_bfm_to_bfx(), convert_bfm_to_sr(), convert_csinc_to_cset(), convert_extr_to_ror(), convert_from_csel(), convert_movebitmask_to_mov(), convert_movewide_to_mov(), convert_orr_to_mov(), convert_shll_to_xtl(), convert_ubfm_to_lsl(), aarch64_opcode::op, OP_ASR_IMM, OP_BFC, OP_BFI, OP_BFXIL, OP_CINC, OP_CINV, OP_CNEG, OP_CSET, OP_CSETM, OP_LSL_IMM, OP_LSR_IMM, OP_MOV_IMM_LOG, OP_MOV_IMM_WIDE, OP_MOV_IMM_WIDEN, OP_MOV_V, OP_ROR_IMM, OP_SBFIZ, OP_SBFX, OP_SXTL, OP_SXTL2, OP_UBFIZ, OP_UBFX, OP_UXTL, and OP_UXTL2.

Referenced by determine_disassembling_preference().

convert_ubfm_to_lsl()

static int convert_ubfm_to_lsl ( aarch64_inst *  inst )

static

Definition at line 2409 of file aarch64-dis.c.

{
  int64_t immr = inst->operands[2].imm.value;
  int64_t imms = inst->operands[3].imm.value;
  int64_t val
    = inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31 ? 31 : 63;
 
  if ((immr == 0 && imms == val) || immr == imms + 1)
    {
      inst->operands[3].type = AARCH64_OPND_NIL;
      inst->operands[2].imm.value = val - imms;
      return 1;
    }
 
  return 0;
}

References AARCH64_OPND_NIL, AARCH64_OPND_QLF_imm_0_31, aarch64_opnd_info::imm, aarch64_inst::operands, aarch64_opnd_info::qualifier, aarch64_opnd_info::type, and val.

Referenced by convert_to_alias().

decode_asimd_fcvt()

static int decode_asimd_fcvt ( aarch64_inst *  inst )

static

Definition at line 1978 of file aarch64-dis.c.

{
  aarch64_field field = {0, 0};
  aarch64_insn value;
  enum aarch64_opnd_qualifier qualifier;
 
  gen_sub_field (FLD_size, 0, 1, &field);
  value = extract_field_2 (&field, inst->value, 0);
  qualifier = value == 0 ? AARCH64_OPND_QLF_V_4S
    : AARCH64_OPND_QLF_V_2D;
  switch (inst->opcode->op)
    {
    case OP_FCVTN:
    case OP_FCVTN2:
      /* FCVTN<Q> <Vd>.<Tb>, <Vn>.<Ta>.  */
      inst->operands[1].qualifier = qualifier;
      break;
    case OP_FCVTL:
    case OP_FCVTL2:
      /* FCVTL<Q> <Vd>.<Ta>, <Vn>.<Tb>.  */
      inst->operands[0].qualifier = qualifier;
      break;
    default:
      assert (0);
      return 0;
    }
 
  return 1;
}

References AARCH64_OPND_QLF_V_2D, AARCH64_OPND_QLF_V_4S, assert(), extract_field_2(), FLD_size, gen_sub_field(), aarch64_opcode::op, OP_FCVTL, OP_FCVTL2, OP_FCVTN, OP_FCVTN2, aarch64_inst::opcode, aarch64_inst::operands, aarch64_opnd_info::qualifier, aarch64_inst::value, and value.

Referenced by do_misc_decoding().

decode_asisd_fcvtxn()

static int decode_asisd_fcvtxn ( aarch64_inst *  inst )

static

Definition at line 2012 of file aarch64-dis.c.

{
  aarch64_field field = {0, 0};
  gen_sub_field (FLD_size, 0, 1, &field);
  if (!extract_field_2 (&field, inst->value, 0))
    return 0;
  inst->operands[0].qualifier = AARCH64_OPND_QLF_S_S;
  return 1;
}

References AARCH64_OPND_QLF_S_S, extract_field_2(), FLD_size, gen_sub_field(), aarch64_inst::operands, aarch64_opnd_info::qualifier, and aarch64_inst::value.

Referenced by do_misc_decoding().

decode_fcvt()

static int decode_fcvt ( aarch64_inst *  inst )

static

Definition at line 2024 of file aarch64-dis.c.

{
  enum aarch64_opnd_qualifier qualifier;
  aarch64_insn value;
  const aarch64_field field = {15, 2};
 
  /* opc dstsize */
  value = extract_field_2 (&field, inst->value, 0);
  switch (value)
    {
    case 0: qualifier = AARCH64_OPND_QLF_S_S; break;
    case 1: qualifier = AARCH64_OPND_QLF_S_D; break;
    case 3: qualifier = AARCH64_OPND_QLF_S_H; break;
    default: return 0;
    }
  inst->operands[0].qualifier = qualifier;
 
  return 1;
}

References AARCH64_OPND_QLF_S_D, AARCH64_OPND_QLF_S_H, AARCH64_OPND_QLF_S_S, extract_field_2(), aarch64_inst::operands, aarch64_opnd_info::qualifier, aarch64_inst::value, and value.

Referenced by do_misc_decoding().

decode_limm()

static bfd_boolean decode_limm ( uint32_t  esize, aarch64_insn  value, int64_t *  result  )

static

Definition at line 839 of file aarch64-dis.c.

{
  uint64_t imm, mask;
  uint32_t N, R, S;
  unsigned simd_size;
 
  /* value is N:immr:imms.  */
  S = value & 0x3f;
  R = (value >> 6) & 0x3f;
  N = (value >> 12) & 0x1;
 
  /* The immediate value is S+1 bits to 1, left rotated by SIMDsize - R
     (in other words, right rotated by R), then replicated.  */
  if (N != 0)
    {
      simd_size = 64;
      mask = 0xffffffffffffffffull;
    }
  else
    {
#ifdef _MSC_VER
      if (S >= 0x00 && S <= 0x1f) { simd_size = 32; }
      else if (S >= 0x20 && S <= 0x2f) { simd_size = 16; S &= 0xf; }
      else if (S >= 0x30 && S <= 0x37) { simd_size = 8; S &= 0x7; }
      else if (S >= 0x38 && S <= 0x3b) { simd_size = 4; S &= 0x3; }
      else if (S >= 0x3c && S <= 0x3d) { simd_size = 2; S &= 0x1; }
      else { return 0; }
#else
      switch (S)
    {
    case 0x00 ... 0x1f: /* 0xxxxx */ simd_size = 32;           break;
    case 0x20 ... 0x2f: /* 10xxxx */ simd_size = 16; S &= 0xf; break;
    case 0x30 ... 0x37: /* 110xxx */ simd_size =  8; S &= 0x7; break;
    case 0x38 ... 0x3b: /* 1110xx */ simd_size =  4; S &= 0x3; break;
    case 0x3c ... 0x3d: /* 11110x */ simd_size =  2; S &= 0x1; break;
    default: return FALSE;
    }
#endif
      mask = (1ull << simd_size) - 1;
      /* Top bits are IGNORED.  */
      R &= simd_size - 1;
    }
 
  if (simd_size > esize * 8)
    return FALSE;
 
  /* NOTE: if S = simd_size - 1 we get 0xf..f which is rejected.  */
  if (S == simd_size - 1)
    return FALSE;
  /* S+1 consecutive bits to 1.  */
  /* NOTE: S can't be 63 due to detection above.  */
  imm = (1ull << (S + 1)) - 1;
  /* Rotate to the left by simd_size - R.  */
  if (R != 0)
    imm = ((imm << (simd_size - R)) & mask) | (imm >> R);
  /* Replicate the value according to SIMD size.  */
  switch (simd_size)
    {
    case  2: imm = (imm <<  2) | imm;
      /* Fall through.  */
    case  4: imm = (imm <<  4) | imm;
      /* Fall through.  */
    case  8: imm = (imm <<  8) | imm;
      /* Fall through.  */
    case 16: imm = (imm << 16) | imm;
      /* Fall through.  */
    case 32: imm = (imm << 32) | imm;
      /* Fall through.  */
    case 64: break;
    default: assert (0); return 0;
    }
 
  *result = imm & ~((uint64_t) -1 << (esize * 4) << (esize * 4));
 
  return TRUE;
}

References assert(), FALSE, imm, mask, N, R, S, TRUE, and value.

Referenced by aarch64_ext_limm().

decode_sizeq()

static int decode_sizeq ( aarch64_inst *  inst )

static

Definition at line 1913 of file aarch64-dis.c.

{
  int idx;
  enum aarch64_opnd_qualifier qualifier;
  aarch64_insn code;
  aarch64_insn value, mask;
  enum aarch64_field_kind fld_sz;
  enum aarch64_opnd_qualifier candidates[AARCH64_MAX_QLF_SEQ_NUM];
 
  if (inst->opcode->iclass == asisdlse
     || inst->opcode->iclass == asisdlsep
     || inst->opcode->iclass == asisdlso
     || inst->opcode->iclass == asisdlsop)
    fld_sz = FLD_vldst_size;
  else
    fld_sz = FLD_size;
 
  code = inst->value;
  value = extract_fields (code, inst->opcode->mask, 2, fld_sz, FLD_Q);
  /* Obtain the info that which bits of fields Q and size are actually
     available for operand encoding.  Opcodes like FMAXNM and FMLA have
     size[1] unavailable.  */
  mask = extract_fields (~inst->opcode->mask, 0, 2, fld_sz, FLD_Q);
 
  /* The index of the operand we are going to tag a qualifier and the qualifer
     itself are reasoned from the value of the size and Q fields and the
     possible valid qualifier lists.  */
  idx = aarch64_select_operand_for_sizeq_field_coding (inst->opcode);
  DEBUG_TRACE ("key idx: %d", idx);
 
  /* For most related instruciton, size:Q are fully available for operand
     encoding.  */
  if (mask == 0x7)
    {
      inst->operands[idx].qualifier = get_vreg_qualifier_from_value (value);
      return 1;
    }
 
  get_operand_possible_qualifiers (idx, inst->opcode->qualifiers_list,
                   candidates);
#ifdef DEBUG_AARCH64
  if (debug_dump)
    {
      int i;
      for (i = 0; candidates[i] != AARCH64_OPND_QLF_NIL
       && i < AARCH64_MAX_QLF_SEQ_NUM; i++)
    DEBUG_TRACE ("qualifier %d: %s", i,
             aarch64_get_qualifier_name(candidates[i]));
      DEBUG_TRACE ("%d, %d", (int)value, (int)mask);
    }
#endif /* DEBUG_AARCH64 */
 
  qualifier = get_qualifier_from_partial_encoding (value, candidates, mask);
 
  if (qualifier == AARCH64_OPND_QLF_NIL)
    return 0;
 
  inst->operands[idx].qualifier = qualifier;
  return 1;
}

References aarch64_get_qualifier_name(), AARCH64_MAX_QLF_SEQ_NUM, AARCH64_OPND_QLF_NIL, aarch64_select_operand_for_sizeq_field_coding(), asisdlse, asisdlsep, asisdlso, asisdlsop, code, DEBUG_TRACE, extract_fields(), FLD_Q, FLD_size, FLD_vldst_size, get_operand_possible_qualifiers(), get_qualifier_from_partial_encoding(), get_vreg_qualifier_from_value(), i, aarch64_opcode::iclass, setup::idx, mask, aarch64_opcode::mask, aarch64_inst::opcode, aarch64_inst::operands, aarch64_opnd_info::qualifier, aarch64_opcode::qualifiers_list, aarch64_inst::value, and value.

Referenced by do_special_decoding().

decode_sve_aimm()

static bfd_boolean decode_sve_aimm ( aarch64_opnd_info *  info, int64_t  value  )

static

Definition at line 1642 of file aarch64-dis.c.

{
  info->shifter.kind = AARCH64_MOD_LSL;
  info->shifter.amount = 0;
  if (info->imm.value & 0x100)
    {
      if (value == 0)
    /* Decode 0x100 as #0, LSL #8.  */
    info->shifter.amount = 8;
      else
    value *= 256;
    }
  info->shifter.operator_present = (info->shifter.amount != 0);
  info->shifter.amount_present = (info->shifter.amount != 0);
  info->imm.value = value;
  return TRUE;
}

References AARCH64_MOD_LSL, info(), TRUE, and value.

Referenced by aarch64_ext_sve_aimm(), and aarch64_ext_sve_asimm().

determine_disassembling_preference()

static void determine_disassembling_preference ( struct aarch64_inst *  inst, aarch64_operand_error *  errors  )

static

Definition at line 2641 of file aarch64-dis.c.

{
  const aarch64_opcode *opcode;
  const aarch64_opcode *alias;
 
  opcode = inst->opcode;
 
  /* This opcode does not have an alias, so use itself.  */
  if (!opcode_has_alias (opcode))
    return;
 
  alias = aarch64_find_alias_opcode (opcode);
  assert (alias);
 
#ifdef DEBUG_AARCH64
  if (debug_dump)
    {
      const aarch64_opcode *tmp = alias;
      printf ("####   LIST    orderd: ");
      while (tmp)
    {
      printf ("%s, ", tmp->name);
      tmp = aarch64_find_next_alias_opcode (tmp);
    }
      printf ("\n");
    }
#endif /* DEBUG_AARCH64 */
 
  for (; alias; alias = aarch64_find_next_alias_opcode (alias))
    {
      DEBUG_TRACE ("try %s", alias->name);
      assert (alias_opcode_p (alias) || opcode_has_alias (opcode));
 
      /* An alias can be a pseudo opcode which will never be used in the
     disassembly, e.g. BIC logical immediate is such a pseudo opcode
     aliasing AND.  */
      if (pseudo_opcode_p (alias))
    {
      DEBUG_TRACE ("skip pseudo %s", alias->name);
      continue;
    }
 
      if ((inst->value & alias->mask) != alias->opcode)
    {
      DEBUG_TRACE ("skip %s as base opcode not match", alias->name);
      continue;
    }
      /* No need to do any complicated transformation on operands, if the alias
     opcode does not have any operand.  */
      if (aarch64_num_of_operands (alias) == 0 && alias->opcode == inst->value)
    {
      DEBUG_TRACE ("succeed with 0-operand opcode %s", alias->name);
      aarch64_replace_opcode (inst, alias);
      return;
    }
      if (alias->flags & F_CONV)
    {
      aarch64_inst copy;
      memcpy (&copy, inst, sizeof (aarch64_inst));
      /* ALIAS is the preference as long as the instruction can be
         successfully converted to the form of ALIAS.  */
      if (convert_to_alias (&copy, alias) == 1)
        {
          aarch64_replace_opcode (&copy, alias);
          assert (aarch64_match_operands_constraint (&copy, NULL));
          DEBUG_TRACE ("succeed with %s via conversion", alias->name);
          memcpy (inst, &copy, sizeof (aarch64_inst));
          return;
        }
    }
      else
    {
      /* Directly decode the alias opcode.  */
      aarch64_inst temp;
      memset (&temp, '\0', sizeof (aarch64_inst));
      if (aarch64_opcode_decode (alias, inst->value, &temp, 1, errors) == 1)
        {
          DEBUG_TRACE ("succeed with %s via direct decoding", alias->name);
          memcpy (inst, &temp, sizeof (aarch64_inst));
          return;
        }
    }
    }
}

References aarch64_find_alias_opcode(), aarch64_find_next_alias_opcode(), aarch64_match_operands_constraint(), aarch64_num_of_operands(), aarch64_opcode_decode(), aarch64_replace_opcode(), alias_opcode_p(), assert(), convert_to_alias(), DEBUG_TRACE, F_CONV, aarch64_opcode::flags, aarch64_opcode::mask, memcpy(), memset(), aarch64_opcode::name, NULL, aarch64_opcode::opcode, aarch64_inst::opcode, opcode_has_alias(), printf(), pseudo_opcode_p(), autogen_x86imm::tmp, and aarch64_inst::value.

Referenced by aarch64_opcode_decode().

do_misc_decoding()

static int do_misc_decoding ( aarch64_inst *  inst )

static

Definition at line 2048 of file aarch64-dis.c.

{
  unsigned int value;
  switch (inst->opcode->op)
    {
    case OP_FCVT:
      return decode_fcvt (inst);
 
    case OP_FCVTN:
    case OP_FCVTN2:
    case OP_FCVTL:
    case OP_FCVTL2:
      return decode_asimd_fcvt (inst);
 
    case OP_FCVTXN_S:
      return decode_asisd_fcvtxn (inst);
 
    case OP_MOV_P_P:
    case OP_MOVS_P_P:
      value = extract_field (FLD_SVE_Pn, inst->value, 0);
      return (value == extract_field (FLD_SVE_Pm, inst->value, 0)
          && value == extract_field (FLD_SVE_Pg4_10, inst->value, 0));
 
    case OP_MOV_Z_P_Z:
      return (extract_field (FLD_SVE_Zd, inst->value, 0)
          == extract_field (FLD_SVE_Zm_16, inst->value, 0));
 
    case OP_MOV_Z_V:
      /* Index must be zero.  */
      value = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5);
      return value > 0 && value <= 16 && value == (value & -value);
 
    case OP_MOV_Z_Z:
      return (extract_field (FLD_SVE_Zn, inst->value, 0)
          == extract_field (FLD_SVE_Zm_16, inst->value, 0));
 
    case OP_MOV_Z_Zi:
      /* Index must be nonzero.  */
      value = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_imm5);
      return value > 0 && value != (value & -value);
 
    case OP_MOVM_P_P_P:
      return (extract_field (FLD_SVE_Pd, inst->value, 0)
          == extract_field (FLD_SVE_Pm, inst->value, 0));
 
    case OP_MOVZS_P_P_P:
    case OP_MOVZ_P_P_P:
      return (extract_field (FLD_SVE_Pn, inst->value, 0)
          == extract_field (FLD_SVE_Pm, inst->value, 0));
 
    case OP_NOTS_P_P_P_Z:
    case OP_NOT_P_P_P_Z:
      return (extract_field (FLD_SVE_Pm, inst->value, 0)
          == extract_field (FLD_SVE_Pg4_10, inst->value, 0));
 
    default:
      return 0;
    }
}

References decode_asimd_fcvt(), decode_asisd_fcvtxn(), decode_fcvt(), extract_field(), extract_fields(), FLD_imm5, FLD_SVE_Pd, FLD_SVE_Pg4_10, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_tszh, FLD_SVE_Zd, FLD_SVE_Zm_16, FLD_SVE_Zn, aarch64_opcode::op, OP_FCVT, OP_FCVTL, OP_FCVTL2, OP_FCVTN, OP_FCVTN2, OP_FCVTXN_S, OP_MOV_P_P, OP_MOV_Z_P_Z, OP_MOV_Z_V, OP_MOV_Z_Z, OP_MOV_Z_Zi, OP_MOVM_P_P_P, OP_MOVS_P_P, OP_MOVZ_P_P_P, OP_MOVZS_P_P_P, OP_NOT_P_P_P_Z, OP_NOTS_P_P_P_Z, aarch64_inst::opcode, aarch64_inst::value, and value.

Referenced by do_special_decoding().

do_special_decoding()

static int do_special_decoding ( aarch64_inst *  inst )

static

Definition at line 2115 of file aarch64-dis.c.

{
  int idx;
  aarch64_insn value;
  /* Condition for truly conditional executed instructions, e.g. b.cond.  */
  if (inst->opcode->flags & F_COND)
    {
      value = extract_field (FLD_cond2, inst->value, 0);
      inst->cond = get_cond_from_value (value);
    }
  /* 'sf' field.  */
  if (inst->opcode->flags & F_SF)
    {
      idx = select_operand_for_sf_field_coding (inst->opcode);
      value = extract_field (FLD_sf, inst->value, 0);
      inst->operands[idx].qualifier = get_greg_qualifier_from_value (value);
      if ((inst->opcode->flags & F_N)
      && extract_field (FLD_N, inst->value, 0) != value)
    return 0;
    }
  /* 'sf' field.  */
  if (inst->opcode->flags & F_LSE_SZ)
    {
      idx = select_operand_for_sf_field_coding (inst->opcode);
      value = extract_field (FLD_lse_sz, inst->value, 0);
      inst->operands[idx].qualifier = get_greg_qualifier_from_value (value);
    }
  /* size:Q fields.  */
  if (inst->opcode->flags & F_SIZEQ)
    return decode_sizeq (inst);
 
  if (inst->opcode->flags & F_FPTYPE)
    {
      idx = select_operand_for_fptype_field_coding (inst->opcode);
      value = extract_field (FLD_type, inst->value, 0);
      switch (value)
    {
    case 0: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_S; break;
    case 1: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_D; break;
    case 3: inst->operands[idx].qualifier = AARCH64_OPND_QLF_S_H; break;
    default: return 0;
    }
    }
 
  if (inst->opcode->flags & F_SSIZE)
    {
      /* N.B. some opcodes like FCMGT <V><d>, <V><n>, #0 have the size[1] as part
     of the base opcode.  */
      aarch64_insn mask;
      enum aarch64_opnd_qualifier candidates[AARCH64_MAX_QLF_SEQ_NUM];
      idx = select_operand_for_scalar_size_field_coding (inst->opcode);
      value = extract_field (FLD_size, inst->value, inst->opcode->mask);
      mask = extract_field (FLD_size, ~inst->opcode->mask, 0);
      /* For most related instruciton, the 'size' field is fully available for
     operand encoding.  */
      if (mask == 0x3)
    inst->operands[idx].qualifier = get_sreg_qualifier_from_value (value);
      else
    {
      get_operand_possible_qualifiers (idx, inst->opcode->qualifiers_list,
                       candidates);
      inst->operands[idx].qualifier
        = get_qualifier_from_partial_encoding (value, candidates, mask);
    }
    }
 
  if (inst->opcode->flags & F_T)
    {
      /* Num of consecutive '0's on the right side of imm5<3:0>.  */
      int num = 0;
      unsigned val, Q;
      assert (aarch64_get_operand_class (inst->opcode->operands[0])
          == AARCH64_OPND_CLASS_SIMD_REG);
      /* imm5<3:0>  q   <t>
     0000       x   reserved
     xxx1       0   8b
     xxx1       1   16b
     xx10       0   4h
     xx10       1   8h
     x100       0   2s
     x100       1   4s
     1000       0   reserved
     1000       1   2d  */
      val = extract_field (FLD_imm5, inst->value, 0);
      while ((val & 0x1) == 0 && ++num <= 3)
    val >>= 1;
      if (num > 3)
    return 0;
      Q = (unsigned) extract_field (FLD_Q, inst->value, inst->opcode->mask);
      inst->operands[0].qualifier =
    get_vreg_qualifier_from_value ((num << 1) | Q);
    }
 
  if (inst->opcode->flags & F_GPRSIZE_IN_Q)
    {
      /* Use Rt to encode in the case of e.g.
     STXP <Ws>, <Xt1>, <Xt2>, [<Xn|SP>{,#0}].  */
      idx = aarch64_operand_index (inst->opcode->operands, AARCH64_OPND_Rt);
      if (idx == -1)
    {
      /* Otherwise use the result operand, which has to be a integer
         register.  */
      assert (aarch64_get_operand_class (inst->opcode->operands[0])
          == AARCH64_OPND_CLASS_INT_REG);
      idx = 0;
    }
      assert (idx == 0 || idx == 1);
      value = extract_field (FLD_Q, inst->value, 0);
      inst->operands[idx].qualifier = get_greg_qualifier_from_value (value);
    }
 
  if (inst->opcode->flags & F_LDS_SIZE)
    {
      aarch64_field field = {0, 0};
      assert (aarch64_get_operand_class (inst->opcode->operands[0])
          == AARCH64_OPND_CLASS_INT_REG);
      gen_sub_field (FLD_opc, 0, 1, &field);
      value = extract_field_2 (&field, inst->value, 0);
      inst->operands[0].qualifier
    = value ? AARCH64_OPND_QLF_W : AARCH64_OPND_QLF_X;
    }
 
  /* Miscellaneous decoding; done as the last step.  */
  if (inst->opcode->flags & F_MISC)
    return do_misc_decoding (inst);
 
  return 1;
}

References aarch64_get_operand_class(), AARCH64_MAX_QLF_SEQ_NUM, aarch64_operand_index(), AARCH64_OPND_CLASS_INT_REG, AARCH64_OPND_CLASS_SIMD_REG, AARCH64_OPND_QLF_S_D, AARCH64_OPND_QLF_S_H, AARCH64_OPND_QLF_S_S, AARCH64_OPND_QLF_W, AARCH64_OPND_QLF_X, AARCH64_OPND_Rt, assert(), aarch64_inst::cond, decode_sizeq(), do_misc_decoding(), extract_field(), extract_field_2(), F_COND, F_FPTYPE, F_GPRSIZE_IN_Q, F_LDS_SIZE, F_LSE_SZ, F_MISC, F_N, F_SF, F_SIZEQ, F_SSIZE, F_T, aarch64_opcode::flags, FLD_cond2, FLD_imm5, FLD_lse_sz, FLD_N, FLD_opc, FLD_Q, FLD_sf, FLD_size, FLD_type, gen_sub_field(), get_cond_from_value(), get_greg_qualifier_from_value(), get_operand_possible_qualifiers(), get_qualifier_from_partial_encoding(), get_sreg_qualifier_from_value(), get_vreg_qualifier_from_value(), setup::idx, mask, aarch64_opcode::mask, num, aarch64_inst::opcode, aarch64_opcode::operands, aarch64_inst::operands, Q, aarch64_opnd_info::qualifier, aarch64_opcode::qualifiers_list, select_operand_for_fptype_field_coding(), select_operand_for_scalar_size_field_coding(), select_operand_for_sf_field_coding(), unsigned, val, aarch64_inst::value, and value.

Referenced by aarch64_opcode_decode().

extract_all_fields()

static aarch64_insn extract_all_fields ( const aarch64_operand *  self, aarch64_insn  code  )

static

Definition at line 168 of file aarch64-dis.c.

{
  aarch64_insn value;
  unsigned int i;
  enum aarch64_field_kind kind;
 
  value = 0;
  for (i = 0; i < ARRAY_SIZE (self->fields) && self->fields[i] != FLD_NIL; i++)
    {
      kind = self->fields[i];
      value <<= fields[kind].width;
      value |= extract_field (kind, code, 0);
    }
  return value;
}

References ARRAY_SIZE, extract_field(), fields, FLD_NIL, i, value, and aarch64_field::width.

Referenced by aarch64_ext_fpimm(), aarch64_ext_imm(), and aarch64_ext_sve_quad_index().

extract_fields()

aarch64_insn extract_fields	(	aarch64_insn	code,
		aarch64_insn	mask,
			...
	)

Definition at line 142 of file aarch64-dis.c.

{
  uint32_t num;
  const aarch64_field *field;
  enum aarch64_field_kind kind;
  va_list va;
 
  va_start (va, mask);
  num = va_arg (va, uint32_t);
  assert (num <= 5);
  aarch64_insn value = 0x0;
  while (num--)
    {
      kind = va_arg (va, enum aarch64_field_kind);
      field = &fields[kind];
      value <<= field->width;
      value |= extract_field (kind, code, mask);
    }
  va_end (va);
  return value;
}

References assert(), extract_field(), fields, mask, num, value, and aarch64_field::width.

Referenced by aarch64_decode_variant_using_iclass(), aarch64_ext_addr_offset(), aarch64_ext_addr_simm10(), aarch64_ext_advsimd_imm_modified(), aarch64_ext_advsimd_imm_shift(), aarch64_ext_ft(), aarch64_ext_hint(), aarch64_ext_ldst_elemlist(), aarch64_ext_limm(), aarch64_ext_pstatefield(), aarch64_ext_reglane(), aarch64_ext_sve_addr_ri_s9xvl(), aarch64_ext_sve_index(), aarch64_ext_sysins_op(), aarch64_ext_sysreg(), decode_sizeq(), and do_misc_decoding().

get_expected_qualifier()

static aarch64_opnd_qualifier_t get_expected_qualifier ( const aarch64_inst *  inst, int  i  )

static

Definition at line 247 of file aarch64-dis.c.

{
  aarch64_opnd_qualifier_seq_t qualifiers;
  /* Should not be called if the qualifier is known.  */
  assert (inst->operands[i].qualifier == AARCH64_OPND_QLF_NIL);
  if (aarch64_find_best_match (inst, inst->opcode->qualifiers_list,
                   i, qualifiers))
    return qualifiers[i];
  else
    return AARCH64_OPND_QLF_NIL;
}

References aarch64_find_best_match(), AARCH64_OPND_QLF_NIL, assert(), i, aarch64_inst::opcode, aarch64_inst::operands, aarch64_opnd_info::qualifier, and aarch64_opcode::qualifiers_list.

Referenced by aarch64_ext_addr_offset(), aarch64_ext_addr_regoff(), aarch64_ext_addr_simm(), aarch64_ext_addr_simm10(), aarch64_ext_addr_uimm12(), aarch64_ext_advsimd_imm_modified(), and aarch64_ext_reglane().

get_greg_qualifier_from_value()

static enum aarch64_opnd_qualifier get_greg_qualifier_from_value ( aarch64_insn  value )

inlinestatic

Definition at line 186 of file aarch64-dis.c.

{
  enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_W + value;
  assert (value <= 0x1
      && aarch64_get_qualifier_standard_value (qualifier) == value);
  return qualifier;
}

References assert(), i, val, and value.

Referenced by do_special_decoding().

get_operand_possible_qualifiers()

static void get_operand_possible_qualifiers ( int  idx, const aarch64_opnd_qualifier_seq_t *  list, enum aarch64_opnd_qualifier *  qualifiers  )

static

Definition at line 1897 of file aarch64-dis.c.

{
  int i;
  for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; i++)
    if ((qualifiers[i] = list[i][idx]) == AARCH64_OPND_QLF_NIL)
      break;
}

References AARCH64_MAX_QLF_SEQ_NUM, AARCH64_OPND_QLF_NIL, i, setup::idx, and list().

Referenced by decode_sizeq(), and do_special_decoding().

get_qualifier_from_partial_encoding()

static enum aarch64_opnd_qualifier get_qualifier_from_partial_encoding ( aarch64_insn  value, const enum aarch64_opnd_qualifier *  candidates, aarch64_insn  mask  )

static

Definition at line 1840 of file aarch64-dis.c.

{
  int i;
  DEBUG_TRACE ("enter with value: %d, mask: %d", (int)value, (int)mask);
  for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; i++)
    {
      aarch64_insn standard_value;
      if (candidates[i] == AARCH64_OPND_QLF_NIL)
    break;
      standard_value = aarch64_get_qualifier_standard_value (candidates[i]);
      if ((standard_value & mask) == (value & mask))
    return candidates[i];
    }
  return AARCH64_OPND_QLF_NIL;
}

Referenced by decode_sizeq(), and do_special_decoding().

get_sreg_qualifier_from_value()

static enum aarch64_opnd_qualifier get_sreg_qualifier_from_value ( aarch64_insn  value )

inlinestatic

Definition at line 186 of file aarch64-dis.c.

{
  enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_S_B + value;
 
  assert (value <= 0x4
      && aarch64_get_qualifier_standard_value (qualifier) == value);
  return qualifier;
}

Referenced by aarch64_ext_advsimd_imm_shift(), aarch64_ext_ft(), aarch64_ext_reglane(), and do_special_decoding().

get_sym_code_type()

static int get_sym_code_type ( struct disassemble_info *  info, int  n, enum map_type *  map_type  )

static

Definition at line 3211 of file aarch64-dis.c.

{
  elf_symbol_type *es;
  unsigned int type;
  const char *name;
 
  /* If the symbol is in a different section, ignore it.  */
  if (info->section != NULL && info->section != info->symtab[n]->section)
    return FALSE;
 
  es = *(elf_symbol_type **)(info->symtab + n);
  type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
 
  /* If the symbol has function type then use that.  */
  if (type == STT_FUNC)
    {
      *map_type = MAP_INSN;
      return TRUE;
    }
 
  /* Check for mapping symbols.  */
  name = bfd_asymbol_name(info->symtab[n]);
  if (name[0] == '$'
      && (name[1] == 'x' || name[1] == 'd')
      && (name[2] == '\0' || name[2] == '.'))
    {
      *map_type = (name[1] == 'x' ? MAP_INSN : MAP_DATA);
      return TRUE;
    }
 
  return FALSE;
}

References bfd_asymbol_name, ELF_ST_TYPE, FALSE, info(), elf_symbol_type::internal_elf_sym, MAP_DATA, MAP_INSN, n, name, NULL, elf_internal_sym::st_info, STT_FUNC, TRUE, and type.

Referenced by print_insn_aarch64().

get_top_bit()

static uint64_t get_top_bit ( uint64_t  value )

static

Definition at line 1817 of file aarch64-dis.c.

{
  while ((value & -value) != value)
    value -= value & -value;
  return value;
}

References value.

Referenced by aarch64_ext_sve_shlimm(), and aarch64_ext_sve_shrimm().

get_vreg_qualifier_from_value()

static enum aarch64_opnd_qualifier get_vreg_qualifier_from_value ( aarch64_insn  value )

inlinestatic

Definition at line 186 of file aarch64-dis.c.

{
  enum aarch64_opnd_qualifier qualifier = AARCH64_OPND_QLF_V_8B + value;
 
  /* Instructions using vector type 2H should not call this function.  Skip over
     the 2H qualifier.  */
  if (qualifier >= AARCH64_OPND_QLF_V_2H)
    qualifier += 1;
 
  assert (value <= 0x8
      && aarch64_get_qualifier_standard_value (qualifier) == value);
  return qualifier;
}

Referenced by aarch64_ext_advsimd_imm_shift(), decode_sizeq(), and do_special_decoding().

parse_aarch64_dis_option()

static void parse_aarch64_dis_option ( const char *  option, unsigned int len  ATTRIBUTE_UNUSED  )

static

Definition at line 60 of file aarch64-dis.c.

{
  /* Try to match options that are simple flags */
  if (CONST_STRNEQ (option, "no-aliases"))
    {
      no_aliases = 1;
      return;
    }
 
  if (CONST_STRNEQ (option, "aliases"))
    {
      no_aliases = 0;
      return;
    }
 
  if (CONST_STRNEQ (option, "no-notes"))
    {
      no_notes = 1;
      return;
    }
 
  if (CONST_STRNEQ (option, "notes"))
    {
      no_notes = 0;
      return;
    }
 
#ifdef DEBUG_AARCH64
  if (CONST_STRNEQ (option, "debug_dump"))
    {
      debug_dump = 1;
      return;
    }
#endif /* DEBUG_AARCH64 */
 
  /* Invalid option.  */
  fprintf (stderr, _("unrecognised disassembler option: %s"), option);
}

References _, CONST_STRNEQ, no_aliases, and no_notes.

Referenced by parse_aarch64_dis_options().

parse_aarch64_dis_options()

static void parse_aarch64_dis_options ( const char *  options )

static

Definition at line 100 of file aarch64-dis.c.

{
  const char *option_end;
 
  if (options == NULL)
    return;
 
  while (*options != '\0')
    {
      /* Skip empty options.  */
      if (*options == ',')
    {
      options++;
      continue;
    }
 
      /* We know that *options is neither NUL or a comma.  */
      option_end = options + 1;
      while (*option_end != ',' && *option_end != '\0')
    option_end++;
 
      parse_aarch64_dis_option (options, option_end - options);
 
      /* Go on to the next one.  If option_end points to a comma, it
     will be skipped above.  */
      options = option_end;
    }
}

References NULL, options, and parse_aarch64_dis_option().

Referenced by print_insn_aarch64().

print_aarch64_disassembler_options()

void print_aarch64_disassembler_options

(

FILE *

stream

)

Definition at line 3381 of file aarch64-dis.c.

{
  fprintf (stream, _("\n\
The following AARCH64 specific disassembler options are supported for use\n\
with the -M switch (multiple options should be separated by commas):\n"));
 
  fprintf (stream, _("\n\
  no-aliases         Don't print instruction aliases.\n"));
 
  fprintf (stream, _("\n\
  aliases            Do print instruction aliases.\n"));
 
  fprintf (stream, _("\n\
  no-notes         Don't print instruction notes.\n"));
 
  fprintf (stream, _("\n\
  notes            Do print instruction notes.\n"));
 
#ifdef DEBUG_AARCH64
  fprintf (stream, _("\n\
  debug_dump         Temp switch for debug trace.\n"));
#endif /* DEBUG_AARCH64 */
 
  fprintf (stream, _("\n"));
}

References _.

print_aarch64_insn()

static void print_aarch64_insn ( bfd_vma  pc, const aarch64_inst *  inst, struct disassemble_info *  info  )

static

Definition at line 3094 of file aarch64-dis.c.

{
  print_mnemonic_name (inst, info);
  print_operands (pc, inst->opcode, inst->operands, info);
  print_comment (inst, info);
}

References info(), aarch64_inst::opcode, aarch64_inst::operands, pc, print_comment(), print_mnemonic_name(), and print_operands().

Referenced by print_insn_aarch64_word().

print_comment()

static void print_comment ( const aarch64_inst *  inst, struct disassemble_info *  info  )

static

Definition at line 3074 of file aarch64-dis.c.

{
return;
  if (inst->opcode->flags & F_COND)
    {
      char name[8];
      unsigned int i, num_conds;
 
      remove_dot_suffix (name, inst);
      num_conds = ARRAY_SIZE (inst->cond->names);
      for (i = 1; i < num_conds && inst->cond->names[i]; i++)
    (*info->fprintf_func) (info->stream, "%s %s.%s",
                   i == 1 ? "  //" : ",",
                   name, inst->cond->names[i]);
    }
}

References ARRAY_SIZE, aarch64_inst::cond, F_COND, aarch64_opcode::flags, i, info(), name, aarch64_cond::names, aarch64_inst::opcode, and remove_dot_suffix().

Referenced by do_ref_search(), print_aarch64_insn(), and rz_analysis_xrefs_to_list_handler().

print_insn_aarch64()

int print_insn_aarch64	(	bfd_vma	pc,
		struct disassemble_info *	info
	)

Definition at line 3248 of file aarch64-dis.c.

{
  bfd_byte  buffer[INSNLEN];
  int       status;
  void      (*printer) (bfd_vma, uint32_t, struct disassemble_info *,
                aarch64_operand_error *);
  bfd_boolean   found = FALSE;
  unsigned int  size = 4;
  unsigned long data;
  aarch64_operand_error errors;
 
  if (info->disassembler_options)
    {
      set_default_aarch64_dis_options (info);
 
      parse_aarch64_dis_options (info->disassembler_options);
 
      /* To avoid repeated parsing of these options, we remove them here.  */
      info->disassembler_options = NULL;
    }
 
  /* Aarch64 instructions are always little-endian */
  info->endian_code = BFD_ENDIAN_LITTLE;
 
  /* First check the full symtab for a mapping symbol, even if there
     are no usable non-mapping symbols for this address.  */
  if (info->symtab_size != 0
      && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
    {
      enum map_type type = MAP_INSN;
      int last_sym = -1;
      bfd_vma addr;
      int n;
 
      if (pc <= last_mapping_addr)
    last_mapping_sym = -1;
 
      /* Start scanning at the start of the function, or wherever
     we finished last time.  */
      n = info->symtab_pos + 1;
      if (n < last_mapping_sym)
    n = last_mapping_sym;
 
      /* Scan up to the location being disassembled.  */
      for (; n < info->symtab_size; n++)
    {
      addr = bfd_asymbol_value (info->symtab[n]);
      if (addr > pc)
        break;
      if (get_sym_code_type (info, n, &type))
        {
          last_sym = n;
          found = TRUE;
        }
    }
 
      if (!found)
    {
      n = info->symtab_pos;
      if (n < last_mapping_sym)
        n = last_mapping_sym;
 
      /* No mapping symbol found at this address.  Look backwards
         for a preceeding one.  */
      for (; n >= 0; n--)
        {
          if (get_sym_code_type (info, n, &type))
        {
          last_sym = n;
          break;
        }
        }
    }
 
      last_mapping_sym = last_sym;
      last_type = type;
 
      /* Look a little bit ahead to see if we should print out
     less than four bytes of data.  If there's a symbol,
     mapping or otherwise, after two bytes then don't
     print more.  */
      if (last_type == MAP_DATA)
    {
      size = 4 - (pc & 3);
      for (n = last_sym + 1; n < info->symtab_size; n++)
        {
          addr = bfd_asymbol_value (info->symtab[n]);
          if (addr > pc)
        {
          if (addr - pc < size)
            size = addr - pc;
          break;
        }
        }
      /* If the next symbol is after three bytes, we need to
         print only part of the data, so that we can use either
         .byte or .short.  */
      if (size == 3)
        size = (pc & 1) ? 1 : 2;
    }
    }
 
  if (last_type == MAP_DATA)
    {
      /* size was set above.  */
      info->bytes_per_chunk = size;
      info->display_endian = info->endian;
      printer = print_insn_data;
    }
  else
    {
      info->bytes_per_chunk = size = INSNLEN;
      info->display_endian = info->endian_code;
      printer = print_insn_aarch64_word;
    }
 
  status = (*info->read_memory_func) (pc, buffer, size, info);
  if (status != 0)
    {
      (*info->memory_error_func) (status, pc, info);
      return -1;
    }
 
  data = bfd_get_bits (buffer, size * 8,
               info->display_endian == BFD_ENDIAN_BIG);
 
  (*printer) (pc, data, info, &errors);
 
  return size;
}

References addr, bfd_asymbol_flavour, bfd_asymbol_value, BFD_ENDIAN_BIG, BFD_ENDIAN_LITTLE, bfd_get_bits(), bfd_target_elf_flavour, FALSE, found, get_sym_code_type(), info(), INSNLEN, last_mapping_addr, last_mapping_sym, last_type, MAP_DATA, MAP_INSN, n, NULL, parse_aarch64_dis_options(), pc, print_insn_aarch64_word(), print_insn_data(), set_default_aarch64_dis_options(), status, TRUE, and type.

print_insn_aarch64_word()

static void print_insn_aarch64_word ( bfd_vma  pc, uint32_t  word, struct disassemble_info *  info, aarch64_operand_error *  errors  )

static

Definition at line 3105 of file aarch64-dis.c.

{
  static const char *err_msg[6] =
    {
      [ERR_OK]   = "_",
      [-ERR_UND] = "undefined",
      [-ERR_UNP] = "unpredictable",
      [-ERR_NYI] = "not-yet-implemented"
    };
 
  int ret;
  aarch64_inst inst;
 
  info->insn_info_valid = 1;
  info->branch_delay_insns = 0;
  info->data_size = 0;
  info->target = 0;
  info->target2 = 0;
 
  if (info->flags & INSN_HAS_RELOC)
    /* If the instruction has a reloc associated with it, then
       the offset field in the instruction will actually be the
       addend for the reloc.  (If we are using REL type relocs).
       In such cases, we can ignore the pc when computing
       addresses, since the addend is not currently pc-relative.  */
    pc = 0;
 
  ret = aarch64_decode_insn (word, &inst, no_aliases, errors);
 
  if (((word >> 21) & 0x3ff) == 1)
    {
      /* RESERVED for ALES.  */
      assert (ret != ERR_OK);
      ret = ERR_NYI;
    }
 
  switch (ret)
    {
    case ERR_UND:
    case ERR_UNP:
    case ERR_NYI:
      /* Handle undefined instructions.  */
      info->insn_type = dis_noninsn;
      // (*info->fprintf_func) (info->stream,".inst 0x%08x ; %s", word, err_msg[-ret]);
      (*info->fprintf_func) (info->stream,"%s", err_msg[-ret]);
      break;
    case ERR_OK:
      user_friendly_fixup (&inst);
      print_aarch64_insn (pc, &inst, info);
      break;
    default:
      abort ();
    }
}

References aarch64_decode_insn(), assert(), dis_noninsn, ERR_NYI, ERR_OK, ERR_UND, ERR_UNP, info(), INSN_HAS_RELOC, no_aliases, pc, print_aarch64_insn(), and user_friendly_fixup().

Referenced by print_insn_aarch64().

print_insn_data()

static void print_insn_data ( bfd_vma pc  ATTRIBUTE_UNUSED, uint32_t  word, struct disassemble_info *  info, aarch64_operand_error *errors  ATTRIBUTE_UNUSED  )

static

Definition at line 3186 of file aarch64-dis.c.

{
  switch (info->bytes_per_chunk)
    {
    case 1:
      info->fprintf_func (info->stream, ".byte 0x%02x", word);
      break;
    case 2:
      info->fprintf_func (info->stream, ".short 0x%04x", word);
      break;
    case 4:
      info->fprintf_func (info->stream, ".word 0x%08x", word);
      break;
    default:
      abort ();
    }
}

References info().

Referenced by print_insn_aarch64().

print_mnemonic_name()

static void print_mnemonic_name ( const aarch64_inst *  inst, struct disassemble_info *  info  )

static

Definition at line 3054 of file aarch64-dis.c.

{
  if (inst->opcode->flags & F_COND)
    {
      /* For instructions that are truly conditionally executed, e.g. b.cond,
     prepare the full mnemonic name with the corresponding condition
     suffix.  */
      char name[8];
 
      remove_dot_suffix (name, inst);
      (*info->fprintf_func) (info->stream, "%s.%s", name, inst->cond->names[0]);
    }
  else
    (*info->fprintf_func) (info->stream, "%s", inst->opcode->name);
}

References aarch64_inst::cond, F_COND, aarch64_opcode::flags, info(), aarch64_opcode::name, aarch64_cond::names, aarch64_inst::opcode, and remove_dot_suffix().

Referenced by print_aarch64_insn().

print_operands()

static void print_operands ( bfd_vma  pc, const aarch64_opcode *  opcode, const aarch64_opnd_info *  opnds, struct disassemble_info *  info  )

static

Definition at line 2998 of file aarch64-dis.c.

{
  int i, pcrel_p, num_printed;
  char *notes = NULL;
  for (i = 0, num_printed = 0; i < AARCH64_MAX_OPND_NUM; i++)
    {
      char str[128];
      /* We regard the opcode operand info more, however we also look into
     the inst->operands to support the disassembling of the optional
     operand.
     The two operand code should be the same in all cases, apart from
     when the operand can be optional.  */
      if (opcode->operands[i] == AARCH64_OPND_NIL
      || opnds[i].type == AARCH64_OPND_NIL)
    break;
 
      /* Generate the operand string in STR.  */
      aarch64_print_operand (str, sizeof (str), pc, opcode, opnds, i, &pcrel_p,
                 &info->target, &notes);
 
      /* Print the delimiter (taking account of omitted operand(s)).  */
      if (str[0] != '\0')
    (*info->fprintf_func) (info->stream, "%s",
                   num_printed++ == 0 ? " " : ", ");
 
      /* Print the operand.  */
      if (pcrel_p)
    (*info->print_address_func) (info->target, info);
      else
    (*info->fprintf_func) (info->stream, "%s", str);
    }
 
    if (notes && !no_notes)
      (*info->fprintf_func) (info->stream, " ; note: %s", notes);
}

References AARCH64_MAX_OPND_NUM, AARCH64_OPND_NIL, aarch64_print_operand(), i, info(), no_notes, NULL, aarch64_opcode::operands, pc, cmd_descs_generate::str, and aarch64_opnd_info::type.

Referenced by print_aarch64_insn().

remove_dot_suffix()

static void remove_dot_suffix ( char *  name, const aarch64_inst *  inst  )

static

Definition at line 3038 of file aarch64-dis.c.

{
  char *ptr;
  size_t len;
 
  ptr = strchr (inst->opcode->name, '.');
  assert (ptr && inst->cond);
  len = ptr - inst->opcode->name;
  assert (len < 8);
  strncpy (name, inst->opcode->name, len);
  name[len] = '\0';
}

References assert(), aarch64_inst::cond, len, aarch64_opcode::name, and aarch64_inst::opcode.

Referenced by print_comment(), and print_mnemonic_name().

set_default_aarch64_dis_options()

static void set_default_aarch64_dis_options ( struct disassemble_info *info  ATTRIBUTE_UNUSED )

static

Definition at line 55 of file aarch64-dis.c.

{
}

Referenced by print_insn_aarch64().

sign_extend()

static int32_t sign_extend ( aarch64_insn  value, unsigned  i  )

inlinestatic

Definition at line 186 of file aarch64-dis.c.

{
  uint32_t ret = value;
 
  assert (i < 32);
  if ((value >> i) & 0x1)
    {
      uint32_t val = (uint32_t)(-1) << i;
      ret = ret | val;
    }
  return (int32_t) ret;
}

Referenced by aarch64_ext_addr_offset(), aarch64_ext_addr_simm(), aarch64_ext_addr_simm10(), aarch64_ext_imm(), and aarch64_ext_sve_addr_ri_s4().

user_friendly_fixup()

static void user_friendly_fixup ( aarch64_inst *  inst )

static

Definition at line 2935 of file aarch64-dis.c.

{
  switch (inst->opcode->iclass)
    {
    case testbranch:
      /* TBNZ Xn|Wn, #uimm6, label
     Test and Branch Not Zero: conditionally jumps to label if bit number
     uimm6 in register Xn is not zero.  The bit number implies the width of
     the register, which may be written and should be disassembled as Wn if
     uimm is less than 32. Limited to a branch offset range of +/- 32KiB.
     */
      if (inst->operands[1].imm.value < 32)
    inst->operands[0].qualifier = AARCH64_OPND_QLF_W;
      break;
    default: break;
    }
}

References AARCH64_OPND_QLF_W, aarch64_opcode::iclass, aarch64_opnd_info::imm, aarch64_inst::opcode, aarch64_inst::operands, aarch64_opnd_info::qualifier, and testbranch.

Referenced by print_insn_aarch64_word().

Variable Documentation

last_mapping_addr

bfd_vma last_mapping_addr = 0

static

Definition at line 47 of file aarch64-dis.c.

Referenced by print_insn_aarch64().

last_mapping_sym

int last_mapping_sym = -1

static

Definition at line 46 of file aarch64-dis.c.

Referenced by print_insn_aarch64().

last_type

enum map_type last_type

static

Definition at line 1 of file aarch64-dis.c.

Referenced by parseOperand(), and print_insn_aarch64().

no_aliases

int no_aliases = 0

static

Definition at line 50 of file aarch64-dis.c.

Referenced by parse_aarch64_dis_option(), and print_insn_aarch64_word().

no_notes

int no_notes = 1

static

Definition at line 51 of file aarch64-dis.c.

Referenced by parse_aarch64_dis_option(), and print_operands().