arm_cs.h File Reference

#include <rz_analysis.h>
#include <capstone/capstone.h>

Go to the source code of this file.

Functions
RZ_IPI int	rz_arm_cs_analysis_op_32_esil (RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, csh *handle, cs_insn *insn, bool thumb)
RZ_IPI int	rz_arm_cs_analysis_op_64_esil (RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, csh *handle, cs_insn *insn)
RZ_IPI const char *	rz_arm_cs_esil_prefix_cond (RzAnalysisOp *op, int cond_type)
RZ_IPI RzILOpEffect *	rz_arm_cs_32_il (csh *handle, cs_insn *insn, bool thumb)
RZ_IPI RzAnalysisILConfig *	rz_arm_cs_32_il_config (bool big_endian)
RZ_IPI RzILOpEffect *	rz_arm_cs_64_il (csh *handle, cs_insn *insn)
RZ_IPI RzAnalysisILConfig *	rz_arm_cs_64_il_config (bool big_endian)

Function Documentation

rz_arm_cs_32_il()

RZ_IPI RzILOpEffect* rz_arm_cs_32_il	(	csh *	handle,
		cs_insn *	insn,
		bool	thumb
	)

Definition at line 2647 of file arm_il32.c.

                                                                             {
    if (insn->id == ARM_INS_IT) {
        // Note: IT is **not** a conditional branch!
        // It's currently handled in analysis_arm_cs.c using ArmCSContext as a hack to turn the following instructions
        // into conditional ones. So in the IL, we don't do anything for IT.
        return NOP();
    }
    RzILOpEffect *eff = il_unconditional(handle, insn, thumb);
    if (!eff) {
        return NULL;
    }
    RzILOpBool *c = cond(insn->detail->arm.cc);
    if (c) {
        return BRANCH(c, eff, NOP());
    }
    return eff;
}

References ARM_INS_IT, BRANCH, c, cond(), handle, il_unconditional(), NOP, and NULL.

Referenced by analysis_op().

rz_arm_cs_32_il_config()

RZ_IPI RzAnalysisILConfig* rz_arm_cs_32_il_config

(

bool

big_endian

)

Definition at line 2667 of file arm_il32.c.

                                                                   {
    RzAnalysisILConfig *r = rz_analysis_il_config_new(32, big_endian, 32);
    r->reg_bindings = regs_bound_32;
    RzILEffectLabel *svc_label = rz_il_effect_label_new("svc", EFFECT_LABEL_SYSCALL);
    svc_label->hook = label_svc;
    rz_analysis_il_config_add_label(r, svc_label);
    RzILEffectLabel *hvc_label = rz_il_effect_label_new("hvc", EFFECT_LABEL_SYSCALL);
    hvc_label->hook = label_hvc;
    rz_analysis_il_config_add_label(r, hvc_label);
    return r;
}

References EFFECT_LABEL_SYSCALL, rz_il_effect_label_t::hook, label_hvc(), label_svc(), r, regs_bound_32, rz_analysis_il_config_add_label(), rz_analysis_il_config_new(), and rz_il_effect_label_new().

Referenced by il_config().

rz_arm_cs_64_il()

RZ_IPI RzILOpEffect* rz_arm_cs_64_il	(	csh *	handle,
		cs_insn *	insn
	)

Lift an AArch64 instruction to RzIL

Currently unimplemented:

FEAT_MTE/FEAT_MTE2/FEAT_MTE3: Memory Tagging Extension

Plausible to represent by adding another memory with a 60bit keys and 4bit values to hold the memory tags. Instructions:

• ADDG, SUBG, SUBP, SUBPS
• CMPP
• GMI
• IRG
• LDG, LDGM
• ST2G, STZ2G
• STG, STGM, STGP, STZG, STZGM

FEAT_PAuth: Pointer Authentication

Extremely complex internal calculations. Different options to implement it include:

• Fully implementing it in IL (probably theoretically possible, but may not be worth it)
• Implementing the complex parts in uninterpreted functions and the simpler ones (e.g. stripping of auth bits) in IL. Might be a very good final solution since all data flow is correctly represented.
• Implementing only stripping in IL and leaving everything else as nop. Might be useful as an interims solution to be able to strip pointers, but always unconditionally succeed authentication. Unimplemented Instructions:
• AUTDA, AUTDZA
• AUTDB, AUTDZB
• AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA
• AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB
• PACDA, PACDZA
• PACDB, PACDZB
• PACGA
• PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA
• PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB
• BLRAA, BLRAAZ, BLRAB, BLRABZ
• BRAA, BRAAZ, BRAB, BRABZ
• XPACD, XPACI, XPACLRI Stub-implemented Instructions:
• LDRAA, LDRAB: currently behave like regular ldr

Cache maintenance, tlb maintenance and address translation

• AT
• CFP
• CPP
• SYS, SYSL
• DC
• DVP
• IC
• TLBI

Miscellaneous

• BRK: causes a breakpoint instruction exception
• BTI: FEAT_BTI/Branch Target Identification
• CLREX: clears the local monitor
• CRC32B, CRC32H, CRC32W, CRC32X, CRC32CB, CRC32CH, CRC32CW, CRC32CX: does crc32
• CSDB, DMB, DSB, ESB, ISB, PSB CSYNC, PSSBB, SB, SSBB, TSB CSYNC: synchronization, memory barriers
• DCPS1, DCPS2, DCPS3, DRPS, HLT: debug
• ERET, ERETAA, ERETAB: exception return
• SMC: secure monitor call
• UDF: permanently undefined

Not supported by capstone v4 or v5 at the time of writing

• AXFLAG, XAFLAG
• FEAT_MTE (see above)
• DGH
• LD64B
• ST64B
• ST64BV
• ST64BV0
• WFET

Definition at line 2316 of file arm_il64.c.

                                                                 {
    switch (insn->id) {
    case ARM64_INS_NOP:
    case ARM64_INS_HINT:
    case ARM64_INS_PRFM:
    case ARM64_INS_PRFUM:
    case ARM64_INS_SEV:
    case ARM64_INS_SEVL:
    case ARM64_INS_WFE:
    case ARM64_INS_WFI:
    case ARM64_INS_YIELD:
        return NOP();
    case ARM64_INS_ADD:
    case ARM64_INS_ADC:
    case ARM64_INS_SUB:
    case ARM64_INS_SBC:
#if CS_API_MAJOR > 4
    case ARM64_INS_ADDS:
    case ARM64_INS_SUBS:
    case ARM64_INS_ADCS:
    case ARM64_INS_SBCS:
#endif
        return add_sub(insn);
    case ARM64_INS_ADR:
    case ARM64_INS_ADRP:
        return adr(insn);
    case ARM64_INS_AND:
#if CS_API_MAJOR > 4
    case ARM64_INS_ANDS:
#endif
    case ARM64_INS_EOR:
    case ARM64_INS_EON:
    case ARM64_INS_ORN:
    case ARM64_INS_ORR:
        return bitwise(insn);
    case ARM64_INS_ASR:
    case ARM64_INS_LSL:
    case ARM64_INS_LSR:
    case ARM64_INS_ROR:
        return shift(insn);
    case ARM64_INS_B:
    case ARM64_INS_BR:
    case ARM64_INS_RET:
#if CS_API_MAJOR > 4
    case ARM64_INS_BRAA:
    case ARM64_INS_BRAAZ:
    case ARM64_INS_BRAB:
    case ARM64_INS_BRABZ:
    case ARM64_INS_RETAA:
    case ARM64_INS_RETAB:
#endif
        return branch(insn);
    case ARM64_INS_BL:
    case ARM64_INS_BLR:
#if CS_API_MAJOR > 4
    case ARM64_INS_BLRAA:
    case ARM64_INS_BLRAAZ:
    case ARM64_INS_BLRAB:
    case ARM64_INS_BLRABZ:
#endif
        return bl(insn);
    case ARM64_INS_BFM:
    case ARM64_INS_BFI:
    case ARM64_INS_BFXIL:
        return bfm(insn);
    case ARM64_INS_BIC:
#if CS_API_MAJOR > 4
    case ARM64_INS_BICS:
#endif
        return bic(insn);
#if CS_API_MAJOR > 4
    case ARM64_INS_CAS:
    case ARM64_INS_CASA:
    case ARM64_INS_CASAL:
    case ARM64_INS_CASL:
    case ARM64_INS_CASB:
    case ARM64_INS_CASAB:
    case ARM64_INS_CASALB:
    case ARM64_INS_CASLB:
    case ARM64_INS_CASH:
    case ARM64_INS_CASAH:
    case ARM64_INS_CASALH:
    case ARM64_INS_CASLH:
        return cas(insn);
    case ARM64_INS_CASP:
    case ARM64_INS_CASPA:
    case ARM64_INS_CASPAL:
    case ARM64_INS_CASPL:
        return casp(insn);
#endif
    case ARM64_INS_CBZ:
    case ARM64_INS_CBNZ:
        return cbz(insn);
    case ARM64_INS_CMP:
    case ARM64_INS_CMN:
    case ARM64_INS_CCMP:
    case ARM64_INS_CCMN:
        return cmp(insn);
#if CS_API_MAJOR > 4
    case ARM64_INS_CFINV:
        return SETG("cf", INV(VARG("cf")));
#endif
    case ARM64_INS_CINC:
    case ARM64_INS_CSINC:
    case ARM64_INS_CINV:
    case ARM64_INS_CSINV:
    case ARM64_INS_CNEG:
    case ARM64_INS_CSNEG:
    case ARM64_INS_CSEL:
        return csinc(insn);
    case ARM64_INS_CSET:
    case ARM64_INS_CSETM:
        return cset(insn);
    case ARM64_INS_CLS:
        return cls(insn);
    case ARM64_INS_CLZ:
        return clz(insn);
    case ARM64_INS_EXTR:
        return extr(insn);
    case ARM64_INS_HVC:
        return hvc(insn);
    case ARM64_INS_SVC:
        return svc(insn);
    case ARM64_INS_LDR:
    case ARM64_INS_LDRB:
    case ARM64_INS_LDRH:
    case ARM64_INS_LDUR:
    case ARM64_INS_LDURB:
    case ARM64_INS_LDURH:
    case ARM64_INS_LDRSW:
    case ARM64_INS_LDRSB:
    case ARM64_INS_LDRSH:
    case ARM64_INS_LDURSW:
    case ARM64_INS_LDURSB:
    case ARM64_INS_LDURSH:
    case ARM64_INS_LDAR:
    case ARM64_INS_LDARB:
    case ARM64_INS_LDARH:
    case ARM64_INS_LDAXP:
    case ARM64_INS_LDXP:
    case ARM64_INS_LDAXR:
    case ARM64_INS_LDAXRB:
    case ARM64_INS_LDAXRH:
    case ARM64_INS_LDP:
    case ARM64_INS_LDNP:
    case ARM64_INS_LDPSW:
    case ARM64_INS_LDTR:
    case ARM64_INS_LDTRB:
    case ARM64_INS_LDTRH:
    case ARM64_INS_LDTRSW:
    case ARM64_INS_LDTRSB:
    case ARM64_INS_LDTRSH:
    case ARM64_INS_LDXR:
    case ARM64_INS_LDXRB:
    case ARM64_INS_LDXRH:
#if CS_API_MAJOR > 4
    case ARM64_INS_LDAPR:
    case ARM64_INS_LDAPRB:
    case ARM64_INS_LDAPRH:
    case ARM64_INS_LDAPUR:
    case ARM64_INS_LDAPURB:
    case ARM64_INS_LDAPURH:
    case ARM64_INS_LDAPURSB:
    case ARM64_INS_LDAPURSH:
    case ARM64_INS_LDAPURSW:
    case ARM64_INS_LDLAR:
    case ARM64_INS_LDLARB:
    case ARM64_INS_LDLARH:
    case ARM64_INS_LDRAA:
    case ARM64_INS_LDRAB:
#endif
        return ldr(insn);
#if CS_API_MAJOR > 4
    case ARM64_INS_LDADD:
    case ARM64_INS_LDADDA:
    case ARM64_INS_LDADDAL:
    case ARM64_INS_LDADDL:
    case ARM64_INS_LDADDB:
    case ARM64_INS_LDADDAB:
    case ARM64_INS_LDADDALB:
    case ARM64_INS_LDADDLB:
    case ARM64_INS_LDADDH:
    case ARM64_INS_LDADDAH:
    case ARM64_INS_LDADDALH:
    case ARM64_INS_LDADDLH:
    case ARM64_INS_STADD:
    case ARM64_INS_STADDL:
    case ARM64_INS_STADDB:
    case ARM64_INS_STADDLB:
    case ARM64_INS_STADDH:
    case ARM64_INS_STADDLH:
    case ARM64_INS_LDCLRB:
    case ARM64_INS_LDCLRAB:
    case ARM64_INS_LDCLRALB:
    case ARM64_INS_LDCLRLB:
    case ARM64_INS_LDCLRH:
    case ARM64_INS_LDCLRAH:
    case ARM64_INS_LDCLRALH:
    case ARM64_INS_LDCLRLH:
    case ARM64_INS_LDCLR:
    case ARM64_INS_LDCLRA:
    case ARM64_INS_LDCLRAL:
    case ARM64_INS_LDCLRL:
    case ARM64_INS_STCLR:
    case ARM64_INS_STCLRL:
    case ARM64_INS_STCLRB:
    case ARM64_INS_STCLRLB:
    case ARM64_INS_STCLRH:
    case ARM64_INS_STCLRLH:
    case ARM64_INS_LDEORB:
    case ARM64_INS_LDEORAB:
    case ARM64_INS_LDEORALB:
    case ARM64_INS_LDEORLB:
    case ARM64_INS_LDEORH:
    case ARM64_INS_LDEORAH:
    case ARM64_INS_LDEORALH:
    case ARM64_INS_LDEORLH:
    case ARM64_INS_LDEOR:
    case ARM64_INS_LDEORA:
    case ARM64_INS_LDEORAL:
    case ARM64_INS_LDEORL:
    case ARM64_INS_STEOR:
    case ARM64_INS_STEORL:
    case ARM64_INS_STEORB:
    case ARM64_INS_STEORLB:
    case ARM64_INS_STEORH:
    case ARM64_INS_STEORLH:
    case ARM64_INS_LDSETB:
    case ARM64_INS_LDSETAB:
    case ARM64_INS_LDSETALB:
    case ARM64_INS_LDSETLB:
    case ARM64_INS_LDSETH:
    case ARM64_INS_LDSETAH:
    case ARM64_INS_LDSETALH:
    case ARM64_INS_LDSETLH:
    case ARM64_INS_LDSET:
    case ARM64_INS_LDSETA:
    case ARM64_INS_LDSETAL:
    case ARM64_INS_LDSETL:
    case ARM64_INS_STSET:
    case ARM64_INS_STSETL:
    case ARM64_INS_STSETB:
    case ARM64_INS_STSETLB:
    case ARM64_INS_STSETH:
    case ARM64_INS_STSETLH:
    case ARM64_INS_LDSMAXB:
    case ARM64_INS_LDSMAXAB:
    case ARM64_INS_LDSMAXALB:
    case ARM64_INS_LDSMAXLB:
    case ARM64_INS_LDSMAXH:
    case ARM64_INS_LDSMAXAH:
    case ARM64_INS_LDSMAXALH:
    case ARM64_INS_LDSMAXLH:
    case ARM64_INS_LDSMAX:
    case ARM64_INS_LDSMAXA:
    case ARM64_INS_LDSMAXAL:
    case ARM64_INS_LDSMAXL:
    case ARM64_INS_STSMAX:
    case ARM64_INS_STSMAXL:
    case ARM64_INS_STSMAXB:
    case ARM64_INS_STSMAXLB:
    case ARM64_INS_STSMAXH:
    case ARM64_INS_STSMAXLH:
    case ARM64_INS_LDSMINB:
    case ARM64_INS_LDSMINAB:
    case ARM64_INS_LDSMINALB:
    case ARM64_INS_LDSMINLB:
    case ARM64_INS_LDSMINH:
    case ARM64_INS_LDSMINAH:
    case ARM64_INS_LDSMINALH:
    case ARM64_INS_LDSMINLH:
    case ARM64_INS_LDSMIN:
    case ARM64_INS_LDSMINA:
    case ARM64_INS_LDSMINAL:
    case ARM64_INS_LDSMINL:
    case ARM64_INS_STSMIN:
    case ARM64_INS_STSMINL:
    case ARM64_INS_STSMINB:
    case ARM64_INS_STSMINLB:
    case ARM64_INS_STSMINH:
    case ARM64_INS_STSMINLH:
    case ARM64_INS_LDUMAXB:
    case ARM64_INS_LDUMAXAB:
    case ARM64_INS_LDUMAXALB:
    case ARM64_INS_LDUMAXLB:
    case ARM64_INS_LDUMAXH:
    case ARM64_INS_LDUMAXAH:
    case ARM64_INS_LDUMAXALH:
    case ARM64_INS_LDUMAXLH:
    case ARM64_INS_LDUMAX:
    case ARM64_INS_LDUMAXA:
    case ARM64_INS_LDUMAXAL:
    case ARM64_INS_LDUMAXL:
    case ARM64_INS_STUMAX:
    case ARM64_INS_STUMAXL:
    case ARM64_INS_STUMAXB:
    case ARM64_INS_STUMAXLB:
    case ARM64_INS_STUMAXH:
    case ARM64_INS_STUMAXLH:
    case ARM64_INS_LDUMINB:
    case ARM64_INS_LDUMINAB:
    case ARM64_INS_LDUMINALB:
    case ARM64_INS_LDUMINLB:
    case ARM64_INS_LDUMINH:
    case ARM64_INS_LDUMINAH:
    case ARM64_INS_LDUMINALH:
    case ARM64_INS_LDUMINLH:
    case ARM64_INS_LDUMIN:
    case ARM64_INS_LDUMINA:
    case ARM64_INS_LDUMINAL:
    case ARM64_INS_LDUMINL:
    case ARM64_INS_STUMIN:
    case ARM64_INS_STUMINL:
    case ARM64_INS_STUMINB:
    case ARM64_INS_STUMINLB:
    case ARM64_INS_STUMINH:
    case ARM64_INS_STUMINLH:
        return ldadd(insn);
#endif
    case ARM64_INS_MADD:
    case ARM64_INS_MSUB:
        return madd(insn);
    case ARM64_INS_MUL:
    case ARM64_INS_MNEG:
        return mul(insn);
    case ARM64_INS_MOV:
    case ARM64_INS_MOVZ:
        return mov(insn);
    case ARM64_INS_MOVK:
        return movk(insn);
    case ARM64_INS_MOVN:
        return movn(insn);
    case ARM64_INS_MSR:
        return msr(insn);
    case ARM64_INS_MRS:
        return mrs(insn);
    case ARM64_INS_MVN:
    case ARM64_INS_NEG:
    case ARM64_INS_NGC:
#if CS_API_MAJOR > 3
    case ARM64_INS_NEGS:
    case ARM64_INS_NGCS:
#endif
        return mvn(insn);
    case ARM64_INS_RBIT:
        return rbit(insn);
    case ARM64_INS_REV:
    case ARM64_INS_REV32:
    case ARM64_INS_REV16:
        return rev(insn);
#if CS_API_MAJOR > 4
    case ARM64_INS_RMIF:
        return rmif(insn);
#endif
    case ARM64_INS_SBFIZ:
    case ARM64_INS_SBFX:
    case ARM64_INS_UBFIZ:
    case ARM64_INS_UBFX:
        return sbfx(insn);
    case ARM64_INS_SDIV:
        return sdiv(insn);
#if CS_API_MAJOR > 4
    case ARM64_INS_SETF8:
    case ARM64_INS_SETF16:
        return setf(insn);
#endif
    case ARM64_INS_SMADDL:
    case ARM64_INS_SMSUBL:
    case ARM64_INS_UMADDL:
    case ARM64_INS_UMSUBL:
        return smaddl(insn);
    case ARM64_INS_SMULL:
    case ARM64_INS_SMNEGL:
    case ARM64_INS_UMULL:
    case ARM64_INS_UMNEGL:
        return smull(insn);
    case ARM64_INS_SMULH:
    case ARM64_INS_UMULH:
        return smulh(insn);
    case ARM64_INS_STR:
    case ARM64_INS_STUR:
    case ARM64_INS_STRB:
    case ARM64_INS_STURB:
    case ARM64_INS_STRH:
    case ARM64_INS_STURH:
    case ARM64_INS_STLR:
    case ARM64_INS_STLRB:
    case ARM64_INS_STLRH:
    case ARM64_INS_STP:
    case ARM64_INS_STNP:
    case ARM64_INS_STXR:
    case ARM64_INS_STXRB:
    case ARM64_INS_STXRH:
    case ARM64_INS_STXP:
    case ARM64_INS_STLXR:
    case ARM64_INS_STLXRB:
    case ARM64_INS_STLXRH:
    case ARM64_INS_STLXP:
    case ARM64_INS_STTR:
    case ARM64_INS_STTRB:
    case ARM64_INS_STTRH:
#if CS_API_MAJOR > 4
    case ARM64_INS_STLLR:
    case ARM64_INS_STLLRB:
    case ARM64_INS_STLLRH:
    case ARM64_INS_STLUR:
    case ARM64_INS_STLURB:
    case ARM64_INS_STLURH:
#endif
        return str(insn);
#if CS_API_MAJOR > 4
    case ARM64_INS_SWP:
    case ARM64_INS_SWPA:
    case ARM64_INS_SWPAL:
    case ARM64_INS_SWPL:
    case ARM64_INS_SWPB:
    case ARM64_INS_SWPAB:
    case ARM64_INS_SWPALB:
    case ARM64_INS_SWPLB:
    case ARM64_INS_SWPH:
    case ARM64_INS_SWPAH:
    case ARM64_INS_SWPALH:
    case ARM64_INS_SWPLH:
        return swp(insn);
#endif
    case ARM64_INS_SXTB:
    case ARM64_INS_SXTH:
    case ARM64_INS_SXTW:
    case ARM64_INS_UXTB:
    case ARM64_INS_UXTH:
        return sxt(insn);
    case ARM64_INS_TBNZ:
    case ARM64_INS_TBZ:
        return tbz(insn);
    case ARM64_INS_TST:
        return tst(insn);
    case ARM64_INS_UDIV:
        return udiv(insn);
    default:
        break;
    }
    return NULL;
}

References add_sub(), adr(), ARM64_INS_ADC, ARM64_INS_ADD, ARM64_INS_ADR, ARM64_INS_ADRP, ARM64_INS_AND, ARM64_INS_ASR, ARM64_INS_B, ARM64_INS_BFI, ARM64_INS_BFM, ARM64_INS_BFXIL, ARM64_INS_BIC, ARM64_INS_BL, ARM64_INS_BLR, ARM64_INS_BR, ARM64_INS_CBNZ, ARM64_INS_CBZ, ARM64_INS_CCMN, ARM64_INS_CCMP, ARM64_INS_CINC, ARM64_INS_CINV, ARM64_INS_CLS, ARM64_INS_CLZ, ARM64_INS_CMN, ARM64_INS_CMP, ARM64_INS_CNEG, ARM64_INS_CSEL, ARM64_INS_CSET, ARM64_INS_CSETM, ARM64_INS_CSINC, ARM64_INS_CSINV, ARM64_INS_CSNEG, ARM64_INS_EON, ARM64_INS_EOR, ARM64_INS_EXTR, ARM64_INS_HINT, ARM64_INS_HVC, ARM64_INS_LDAR, ARM64_INS_LDARB, ARM64_INS_LDARH, ARM64_INS_LDAXP, ARM64_INS_LDAXR, ARM64_INS_LDAXRB, ARM64_INS_LDAXRH, ARM64_INS_LDNP, ARM64_INS_LDP, ARM64_INS_LDPSW, ARM64_INS_LDR, ARM64_INS_LDRB, ARM64_INS_LDRH, ARM64_INS_LDRSB, ARM64_INS_LDRSH, ARM64_INS_LDRSW, ARM64_INS_LDTR, ARM64_INS_LDTRB, ARM64_INS_LDTRH, ARM64_INS_LDTRSB, ARM64_INS_LDTRSH, ARM64_INS_LDTRSW, ARM64_INS_LDUR, ARM64_INS_LDURB, ARM64_INS_LDURH, ARM64_INS_LDURSB, ARM64_INS_LDURSH, ARM64_INS_LDURSW, ARM64_INS_LDXP, ARM64_INS_LDXR, ARM64_INS_LDXRB, ARM64_INS_LDXRH, ARM64_INS_LSL, ARM64_INS_LSR, ARM64_INS_MADD, ARM64_INS_MNEG, ARM64_INS_MOV, ARM64_INS_MOVK, ARM64_INS_MOVN, ARM64_INS_MOVZ, ARM64_INS_MRS, ARM64_INS_MSR, ARM64_INS_MSUB, ARM64_INS_MUL, ARM64_INS_MVN, ARM64_INS_NEG, ARM64_INS_NEGS, ARM64_INS_NGC, ARM64_INS_NGCS, ARM64_INS_NOP, ARM64_INS_ORN, ARM64_INS_ORR, ARM64_INS_PRFM, ARM64_INS_PRFUM, ARM64_INS_RBIT, ARM64_INS_RET, ARM64_INS_REV, ARM64_INS_REV16, ARM64_INS_REV32, ARM64_INS_ROR, ARM64_INS_SBC, ARM64_INS_SBFIZ, ARM64_INS_SBFX, ARM64_INS_SDIV, ARM64_INS_SEV, ARM64_INS_SEVL, ARM64_INS_SMADDL, ARM64_INS_SMNEGL, ARM64_INS_SMSUBL, ARM64_INS_SMULH, ARM64_INS_SMULL, ARM64_INS_STLR, ARM64_INS_STLRB, ARM64_INS_STLRH, ARM64_INS_STLXP, ARM64_INS_STLXR, ARM64_INS_STLXRB, ARM64_INS_STLXRH, ARM64_INS_STNP, ARM64_INS_STP, ARM64_INS_STR, ARM64_INS_STRB, ARM64_INS_STRH, ARM64_INS_STTR, ARM64_INS_STTRB, ARM64_INS_STTRH, ARM64_INS_STUR, ARM64_INS_STURB, ARM64_INS_STURH, ARM64_INS_STXP, ARM64_INS_STXR, ARM64_INS_STXRB, ARM64_INS_STXRH, ARM64_INS_SUB, ARM64_INS_SVC, ARM64_INS_SXTB, ARM64_INS_SXTH, ARM64_INS_SXTW, ARM64_INS_TBNZ, ARM64_INS_TBZ, ARM64_INS_TST, ARM64_INS_UBFIZ, ARM64_INS_UBFX, ARM64_INS_UDIV, ARM64_INS_UMADDL, ARM64_INS_UMNEGL, ARM64_INS_UMSUBL, ARM64_INS_UMULH, ARM64_INS_UMULL, ARM64_INS_UXTB, ARM64_INS_UXTH, ARM64_INS_WFE, ARM64_INS_WFI, ARM64_INS_YIELD, bfm(), bic(), bitwise(), bl(), branch(), cbz(), cls(), clz(), cmp(), cset(), csinc(), extr(), hvc(), INV, ldr(), madd(), mov(), movk(), movn(), mrs(), msr(), mul(), mvn(), NOP, NULL, rbit(), rev(), sbfx(), sdiv(), SETG, shift(), smaddl(), smulh(), smull(), str(), svc(), sxt(), tbz(), tst(), udiv(), and VARG.

Referenced by analysis_op().

rz_arm_cs_64_il_config()

RZ_IPI RzAnalysisILConfig* rz_arm_cs_64_il_config

(

bool

big_endian

)

Definition at line 2762 of file arm_il64.c.

                                                                   {
    RzAnalysisILConfig *r = rz_analysis_il_config_new(64, big_endian, 64);
    r->reg_bindings = regs_bound;
    RzILEffectLabel *svc_label = rz_il_effect_label_new("svc", EFFECT_LABEL_SYSCALL);
    svc_label->hook = label_svc;
    rz_analysis_il_config_add_label(r, svc_label);
    RzILEffectLabel *hvc_label = rz_il_effect_label_new("hvc", EFFECT_LABEL_SYSCALL);
    hvc_label->hook = label_hvc;
    rz_analysis_il_config_add_label(r, hvc_label);
    return r;
}

References EFFECT_LABEL_SYSCALL, rz_il_effect_label_t::hook, label_hvc(), label_svc(), r, regs_bound, rz_analysis_il_config_add_label(), rz_analysis_il_config_new(), and rz_il_effect_label_new().

Referenced by il_config().

rz_arm_cs_analysis_op_32_esil()

RZ_IPI int rz_arm_cs_analysis_op_32_esil	(	RzAnalysis *	a,
		RzAnalysisOp *	op,
		ut64	addr,
		const ut8 *	buf,
		int	len,
		csh *	handle,
		cs_insn *	insn,
		bool	thumb
	)

Definition at line 239 of file arm_esil32.c.

                                                                                                                                                      {
    int i;
    const char *postfix = NULL;
    char str[32][32];
    int msr_flags;
    int pcdelta = (thumb ? 4 : 8);
    ut32 mask = UT32_MAX;
    int str_ldr_bytes = 4;
    unsigned int width = 0;
 
    rz_strbuf_init(&op->esil);
    rz_strbuf_set(&op->esil, "");
    postfix = rz_arm_cs_esil_prefix_cond(op, insn->detail->arm.cc);
 
    switch (insn->id) {
    case ARM_INS_CLZ:
        rz_strbuf_appendf(&op->esil, "%s,!,?{,32,%s,=,BREAK,},0,%s,=,%s,%s,<<,0x80000000,&,!,?{,1,%s,+=,11,GOTO,}", REG(1), REG(0), REG(0), REG(0), REG(1), REG(0));
        break;
    case ARM_INS_IT:
        rz_strbuf_appendf(&op->esil, "2,$$,+,pc,=");
        break;
    case ARM_INS_BKPT:
        rz_strbuf_setf(&op->esil, "%d,%d,TRAP", IMM(0), IMM(0));
        break;
    case ARM_INS_NOP:
        rz_strbuf_setf(&op->esil, ",");
        break;
    case ARM_INS_BL:
    case ARM_INS_BLX:
        rz_strbuf_appendf(&op->esil, "pc,%d,+,lr,=,", thumb);
        /* fallthrough */
    case ARM_INS_BX:
    case ARM_INS_BXJ:
    case ARM_INS_B:
        if (ISREG(0) && REGID(0) == ARM_REG_PC) {
            rz_strbuf_appendf(&op->esil, "0x%" PFMT64x ",pc,=", (addr & ~3LL) + pcdelta);
        } else {
            if (ISIMM(0)) {
                rz_strbuf_appendf(&op->esil, "%s,pc,=", ARG(0));
            } else {
                rz_strbuf_appendf(&op->esil, "%d,%s,-,pc,=", thumb, ARG(0));
            }
        }
        break;
    case ARM_INS_UDF:
        rz_strbuf_setf(&op->esil, "%s,TRAP", ARG(0));
        break;
    case ARM_INS_SADD16:
    case ARM_INS_SADD8:
        MATH32AS("+");
        break;
    case ARM_INS_ADDW:
    case ARM_INS_ADD:
        MATH32("+");
        break;
    case ARM_INS_ADC:
        if (OPCOUNT() == 2) {
            rz_strbuf_appendf(&op->esil, "cf,%s,+=,%s,%s,+=", ARG(0), ARG(1), ARG(0));
        } else {
            rz_strbuf_appendf(&op->esil, "cf,%s,+=,%s,%s,+,%s,+=", ARG(0), ARG(2), ARG(1), ARG(0));
        }
        break;
    case ARM_INS_SSUB16:
    case ARM_INS_SSUB8:
        MATH32AS("-");
        break;
    case ARM_INS_SUBW:
    case ARM_INS_SUB:
        MATH32("-");
        break;
    case ARM_INS_SBC:
        if (OPCOUNT() == 2) {
            rz_strbuf_appendf(&op->esil, "cf,%s,-=,%s,%s,-=", ARG(0), ARG(1), ARG(0));
        } else {
            rz_strbuf_appendf(&op->esil, "cf,%s,-=,%s,%s,+,%s,-=", ARG(0), ARG(2), ARG(1), ARG(0));
        }
        break;
    case ARM_INS_MUL:
        MATH32("*");
        break;
    case ARM_INS_AND:
        MATH32("&");
        break;
    case ARM_INS_ORR:
        MATH32("|");
        break;
    case ARM_INS_EOR:
        MATH32("^");
        break;
    case ARM_INS_ORN:
        MATH32_NEG("|");
        break;
    case ARM_INS_LSR:
        if (insn->detail->arm.update_flags) {
            if (OPCOUNT() == 2) {
                rz_strbuf_appendf(&op->esil, "%s,!,!,?{,%s,1,%s,-,0x1,<<,&,!,!,cf,:=,},", ARG(1), ARG(0), ARG(1));
            } else {
                rz_strbuf_appendf(&op->esil, "%s,!,!,?{,%s,1,%s,-,0x1,<<,&,!,!,cf,:=,},", ARG(2), ARG(1), ARG(2));
            }
        }
        MATH32(">>");
        break;
    case ARM_INS_LSL:
        if (insn->detail->arm.update_flags) {
            if (OPCOUNT() == 2) {
                rz_strbuf_appendf(&op->esil, "%s,!,!,?{,%s,32,-,%s,>>,cf,:=,},", ARG(1), ARG(1), ARG(0));
            } else {
                rz_strbuf_appendf(&op->esil, "%s,!,!,?{,%s,32,-,%s,>>,cf,:=,},", ARG(2), ARG(2), ARG(1));
            }
        }
        MATH32("<<");
        break;
    case ARM_INS_SVC:
        rz_strbuf_setf(&op->esil, "%s,$", ARG(0));
        break;
    case ARM_INS_PUSH:
#if 0
PUSH { r4, r5, r6, r7, lr }
4,sp,-=,lr,sp,=[4],
4,sp,-=,r7,sp,=[4],
4,sp,-=,r6,sp,=[4],
4,sp,-=,r5,sp,=[4],
4,sp,-=,r4,sp,=[4]
 
20,sp,-=,lr,r7,r6,r5,r4,5,sp,=[*]
#endif
        rz_strbuf_appendf(&op->esil, "%d,sp,-=,",
            4 * insn->detail->arm.op_count);
        for (i = insn->detail->arm.op_count; i > 0; i--) {
            rz_strbuf_appendf(&op->esil, "%s,", REG(i - 1));
        }
        rz_strbuf_appendf(&op->esil, "%d,sp,=[*]",
            insn->detail->arm.op_count);
        break;
    case ARM_INS_STMDA:
    case ARM_INS_STMDB:
    case ARM_INS_STM:
    case ARM_INS_STMIB: {
        int direction = (insn->id == ARM_INS_STMDA || insn->id == ARM_INS_STMDB ? -1 : 1);
        int offset = direction > 0 ? -1 : -insn->detail->arm.op_count;
        if (insn->id == ARM_INS_STMDA || insn->id == ARM_INS_STMIB) {
            offset++;
        }
        for (i = 1; i < insn->detail->arm.op_count; i++) {
            rz_strbuf_appendf(&op->esil, "%s,%s,%d,+,=[4],",
                REG(i), ARG(0), (i + offset) * 4);
        }
        if (insn->detail->arm.writeback == true) { // writeback, reg should be incremented
            rz_strbuf_appendf(&op->esil, "%d,%s,+=,",
                direction * (insn->detail->arm.op_count - 1) * 4, ARG(0));
        }
        break;
    }
    case ARM_INS_VSTMIA:
        rz_strbuf_set(&op->esil, "");
        width = 0;
        for (i = 1; i < insn->detail->arm.op_count; i++) {
            rz_strbuf_appendf(&op->esil, "%s,%d,%s,+,=[%d],",
                REG(i), width, ARG(0), REGSIZE32(i));
            width += REGSIZE32(i);
        }
        // increment if writeback
        if (insn->detail->arm.writeback) {
            rz_strbuf_appendf(&op->esil, "%d,%s,+=,", width, ARG(0));
        }
        break;
    case ARM_INS_VSTMDB:
        rz_strbuf_set(&op->esil, "");
        width = 0;
        for (i = insn->detail->arm.op_count - 1; i > 0; i--) {
            width += REGSIZE32(i);
            rz_strbuf_appendf(&op->esil, "%s,%d,%s,-,=[%d],",
                REG(i), width, ARG(0), REGSIZE32(i));
        }
        // decrement writeback is mandatory for VSTMDB
        rz_strbuf_appendf(&op->esil, "%d,%s,-=,", width, ARG(0));
        break;
    case ARM_INS_VLDMIA:
        rz_strbuf_set(&op->esil, "");
        width = 0;
        for (i = 1; i < insn->detail->arm.op_count; i++) {
            rz_strbuf_appendf(&op->esil, "%d,%s,+,[%d],%s,=,",
                width, ARG(0), REGSIZE32(i), REG(i));
            width += REGSIZE32(i);
        }
        // increment if writeback
        if (insn->detail->arm.writeback) {
            rz_strbuf_appendf(&op->esil, "%d,%s,+=,", width, ARG(0));
        }
        break;
    case ARM_INS_VLDMDB:
        rz_strbuf_set(&op->esil, "");
        width = 0;
        for (i = insn->detail->arm.op_count - 1; i > 0; i--) {
            width += REGSIZE32(i);
            rz_strbuf_appendf(&op->esil, "%d,%s,-,[%d],%s,=,",
                width, ARG(0), REGSIZE32(i), REG(i));
        }
        // decrement writeback is mandatory for VLDMDB
        rz_strbuf_appendf(&op->esil, "%d,%s,-=,", width, ARG(0));
        break;
    case ARM_INS_ASR:
        // suffix 'S' forces conditional flag to be updated
        if (insn->detail->arm.update_flags) {
            if (OPCOUNT() == 2) {
                rz_strbuf_appendf(&op->esil, "%s,!,!,?{,%s,1,%s,-,0x1,<<,&,!,!,cf,:=,},", ARG(1), ARG(0), ARG(1));
            } else if (OPCOUNT() == 3) {
                rz_strbuf_appendf(&op->esil, "%s,!,!,?{,%s,1,%s,-,0x1,<<,&,!,!,cf,:=,},", ARG(2), ARG(1), ARG(2));
            }
        }
        if (OPCOUNT() == 2) {
            if (ISSHIFTED(1)) {
                rz_strbuf_appendf(&op->esil, "%s,%s,=", ARG(1), ARG(0));
            } else {
                rz_strbuf_appendf(&op->esil, "%s,%s,>>>>,%s,=", ARG(1), ARG(0), ARG(0));
            }
        } else if (OPCOUNT() == 3) {
            rz_strbuf_appendf(&op->esil, "%s,%s,>>>>,%s,=", ARG(2), ARG(1), ARG(0));
        }
        break;
    case ARM_INS_POP:
#if 0
POP { r4,r5, r6}
r6,r5,r4,3,sp,[*],12,sp,+=
#endif
        for (i = insn->detail->arm.op_count; i > 0; i--) {
            rz_strbuf_appendf(&op->esil, "%s,", REG(i - 1));
        }
        rz_strbuf_appendf(&op->esil, "%d,sp,[*],",
            insn->detail->arm.op_count);
        rz_strbuf_appendf(&op->esil, "%d,sp,+=",
            4 * insn->detail->arm.op_count);
        break;
    case ARM_INS_LDMDA:
    case ARM_INS_LDMDB:
    case ARM_INS_LDM:
    case ARM_INS_LDMIB: {
        int direction = (insn->id == ARM_INS_LDMDA || insn->id == ARM_INS_LDMDB) ? -1 : 1;
        int offset = direction > 0 ? -1 : -insn->detail->arm.op_count;
        if (insn->id == ARM_INS_LDMDA || insn->id == ARM_INS_LDMIB) {
            offset++;
        }
        for (i = 1; i < insn->detail->arm.op_count; i++) {
            rz_strbuf_appendf(&op->esil, "%s,%d,+,[4],%s,=,", ARG(0), (i + offset) * 4, REG(i));
        }
        if (insn->detail->arm.writeback) {
            rz_strbuf_appendf(&op->esil, "%d,%s,+=,",
                direction * (insn->detail->arm.op_count - 1) * 4, ARG(0));
        }
        break;
    }
    case ARM_INS_CMP:
        rz_strbuf_appendf(&op->esil, "%s,%s,==", ARG(1), ARG(0));
        break;
    case ARM_INS_CMN:
        rz_strbuf_appendf(&op->esil, "%s,%s,^,!,!,zf,=", ARG(1), ARG(0));
        break;
    case ARM_INS_MOVT:
        rz_strbuf_appendf(&op->esil, "16,%s,<<,%s,|=", ARG(1), REG(0));
        break;
    case ARM_INS_ADR:
        rz_strbuf_appendf(&op->esil, "%d,$$,+,%s,+,0xfffffffc,&,%s,=",
            pcdelta, ARG(1), REG(0));
        break;
    case ARM_INS_MOV:
    case ARM_INS_VMOV:
    case ARM_INS_MOVW:
        rz_strbuf_appendf(&op->esil, "%s,%s,=", ARG(1), REG(0));
        break;
    case ARM_INS_CBZ:
        rz_strbuf_appendf(&op->esil, "%s,!,?{,%" PFMT32u ",pc,=,}",
            REG(0), IMM(1));
        break;
    case ARM_INS_CBNZ:
        rz_strbuf_appendf(&op->esil, "%s,?{,%" PFMT32u ",pc,=,}",
            REG(0), IMM(1));
        break;
        // Encapsulated STR/H/B into a code section
    case ARM_INS_STRT:
    case ARM_INS_STR:
    case ARM_INS_STRHT:
    case ARM_INS_STRH:
    case ARM_INS_STRBT:
    case ARM_INS_STRB:
    case ARM_INS_STRD:
        // case ARM_INS_STLXRB: // capstone has no STLXR?
        switch (insn->id) {
        case ARM_INS_STRD:
            str_ldr_bytes = 8; // just an indication, won't be used in esil code
            break;
        case ARM_INS_STRHT:
        case ARM_INS_STRH:
            str_ldr_bytes = 2;
            break;
        case ARM_INS_STRBT:
        case ARM_INS_STRB:
            str_ldr_bytes = 1;
            break;
        default:
            str_ldr_bytes = 4;
        }
        if (OPCOUNT() == 2) {
            if (ISMEM(1) && !HASMEMINDEX(1)) {
                int disp = MEMDISP(1);
                char sign = disp >= 0 ? '+' : '-';
                disp = disp >= 0 ? disp : -disp;
                rz_strbuf_appendf(&op->esil, "%s,0x%x,%s,%c,0xffffffff,&,=[%d]",
                    REG(0), disp, MEMBASE(1), sign, str_ldr_bytes);
                if (insn->detail->arm.writeback) {
                    rz_strbuf_appendf(&op->esil, ",%d,%s,%c,%s,=",
                        disp, MEMBASE(1), sign, MEMBASE(1));
                }
            }
            if (HASMEMINDEX(1)) { // e.g. 'str r2, [r3, r1]'
                if (ISSHIFTED(1)) { // e.g. 'str r2, [r3, r1, lsl 4]'
                    switch (SHIFTTYPE(1)) {
                    case ARM_SFT_LSL:
                        rz_strbuf_appendf(&op->esil, "%s,%s,%d,%s,<<,+,0xffffffff,&,=[%d]",
                            REG(0), MEMBASE(1), SHIFTVALUE(1), MEMINDEX(1), str_ldr_bytes);
                        if (insn->detail->arm.writeback) { // e.g. 'str r2, [r3, r1, lsl 4]!'
                            rz_strbuf_appendf(&op->esil, ",%s,%d,%s,<<,+,%s,=",
                                MEMBASE(1), SHIFTVALUE(1), MEMINDEX(1), MEMBASE(1));
                        }
                        break;
                    case ARM_SFT_LSR:
                        rz_strbuf_appendf(&op->esil, "%s,%s,%d,%s,>>,+,0xffffffff,&,=[%d]",
                            REG(0), MEMBASE(1), SHIFTVALUE(1), MEMINDEX(1), str_ldr_bytes);
                        if (insn->detail->arm.writeback) {
                            rz_strbuf_appendf(&op->esil, ",%s,%d,%s,>>,+,%s,=",
                                MEMBASE(1), SHIFTVALUE(1), MEMINDEX(1), MEMBASE(1));
                        }
                        break;
                    case ARM_SFT_ASR:
                        rz_strbuf_appendf(&op->esil, "%s,%s,%d,%s,>>>>,+,0xffffffff,&,=[%d]",
                            REG(0), MEMBASE(1), SHIFTVALUE(1), MEMINDEX(1), str_ldr_bytes);
                        if (insn->detail->arm.writeback) {
                            rz_strbuf_appendf(&op->esil, ",%s,%d,%s,>>>>,+,%s,=",
                                MEMBASE(1), SHIFTVALUE(1), MEMINDEX(1), MEMBASE(1));
                        }
                        break;
                    case ARM_SFT_ROR:
                        rz_strbuf_appendf(&op->esil, "%s,%s,%d,%s,>>>,+,0xffffffff,&,=[%d]",
                            REG(0), MEMBASE(1), SHIFTVALUE(1), MEMINDEX(1), str_ldr_bytes);
                        if (insn->detail->arm.writeback) {
                            rz_strbuf_appendf(&op->esil, ",%s,%d,%s,>>>,+,%s,=",
                                MEMBASE(1), SHIFTVALUE(1), MEMINDEX(1), MEMBASE(1));
                        }
                        break;
                    case ARM_SFT_RRX: // ROR with single bit shift, using previous cf rather than new cf
                        // TODO: r2 doesn't mark this as a shift, it falls through to no shift
                        break;
                    default:
                        // Hopefully nothing here
                        break;
                    }
                } else { // No shift
                    rz_strbuf_appendf(&op->esil, "%s,%s,%s,+,0xffffffff,&,=[%d]",
                        REG(0), MEMINDEX(1), MEMBASE(1), str_ldr_bytes);
                    if (insn->detail->arm.writeback) {
                        rz_strbuf_appendf(&op->esil, ",%s,%s,+,%s,=",
                            MEMINDEX(1), MEMBASE(1), MEMBASE(1));
                    }
                }
            }
        }
        if (OPCOUNT() == 3) { // e.g. 'str r2, [r3], 4
            if (ISIMM(2)) { // e.g. 'str r2, [r3], 4
                rz_strbuf_appendf(&op->esil, "%s,%s,0xffffffff,&,=[%d],%d,%s,+=",
                    REG(0), MEMBASE(1), str_ldr_bytes, IMM(2), MEMBASE(1));
            }
            if (ISREG(2)) { // e.g. 'str r2, [r3], r1
                if (ISSHIFTED(2)) { // e.g. 'str r2, [r3], r1, lsl 4'
                    switch (SHIFTTYPE(2)) {
                    case ARM_SFT_LSL:
                        rz_strbuf_appendf(&op->esil, "%s,%s,0xffffffff,&,=[%d],%s,%d,%s,<<,+,%s,=",
                            REG(0), MEMBASE(1), str_ldr_bytes, MEMBASE(1), SHIFTVALUE(2), REG(2), MEMBASE(1));
                        break;
                    case ARM_SFT_LSR:
                        rz_strbuf_appendf(&op->esil, "%s,%s,0xffffffff,&,=[%d],%s,%d,%s,>>,+,%s,=",
                            REG(0), MEMBASE(1), str_ldr_bytes, MEMBASE(1), SHIFTVALUE(2), REG(2), MEMBASE(1));
                        break;
                    case ARM_SFT_ASR:
                        rz_strbuf_appendf(&op->esil, "%s,%s,0xffffffff,&,=[%d],%s,%d,%s,>>>>,+,%s,=",
                            REG(0), MEMBASE(1), str_ldr_bytes, MEMBASE(1), SHIFTVALUE(2), REG(2), MEMBASE(1));
                        break;
                    case ARM_SFT_ROR:
                        rz_strbuf_appendf(&op->esil, "%s,%s,0xffffffff,&,=[%d],%s,%d,%s,>>>,+,%s,=",
                            REG(0), MEMBASE(1), str_ldr_bytes, MEMBASE(1), SHIFTVALUE(2), REG(2), MEMBASE(1));
                        break;
                    case ARM_SFT_RRX:
                        // TODO
                        break;
                    default:
                        // Hopefully nothing here
                        break;
                    }
                } else { // No shift
                    rz_strbuf_appendf(&op->esil, "%s,%s,0xffffffff,&,=[%d],%s,%s,+=",
                        REG(0), MEMBASE(1), str_ldr_bytes, REG(2), MEMBASE(1));
                }
            }
            if (ISREG(1) && str_ldr_bytes == 8) { // e.g. 'strd r2, r3, [r4]', normally should be the only case for ISREG(1).
                if (!HASMEMINDEX(2)) {
                    int disp = MEMDISP(2);
                    char sign = disp >= 0 ? '+' : '-';
                    disp = disp >= 0 ? disp : -disp;
                    rz_strbuf_appendf(&op->esil, "%s,%d,%s,%c,0xffffffff,&,=[4],%s,4,%d,+,%s,%c,0xffffffff,&,=[4]",
                        REG(0), disp, MEMBASE(2), sign, REG(1), disp, MEMBASE(2), sign);
                    if (insn->detail->arm.writeback) {
                        rz_strbuf_appendf(&op->esil, ",%d,%s,%c,%s,=",
                            disp, MEMBASE(2), sign, MEMBASE(2));
                    }
                } else {
                    if (ISSHIFTED(2)) {
                        // it seems strd does not support SHIFT which is good, but have a check nonetheless
                    } else {
                        rz_strbuf_appendf(&op->esil, "%s,%s,%s,+,0xffffffff,&,=[4],%s,4,%s,+,%s,+,0xffffffff,&,=[4]",
                            REG(0), MEMINDEX(2), MEMBASE(2), REG(1), MEMINDEX(2), MEMBASE(2));
                        if (insn->detail->arm.writeback) {
                            rz_strbuf_appendf(&op->esil, ",%s,%s,+,%s,=",
                                MEMINDEX(2), MEMBASE(2), MEMBASE(2));
                        }
                    }
                }
            }
        }
        if (OPCOUNT() == 4) { // e.g. 'strd r2, r3, [r4], 4' or 'strd r2, r3, [r4], r5'
            if (ISIMM(3)) { // e.g. 'strd r2, r3, [r4], 4'
                rz_strbuf_appendf(&op->esil, "%s,%s,0xffffffff,&,=[%d],%s,4,%s,+,0xffffffff,&,=[%d],%d,%s,+=,",
                    REG(0), MEMBASE(2), str_ldr_bytes, REG(1), MEMBASE(2), str_ldr_bytes, IMM(3), MEMBASE(2));
            }
            if (ISREG(3)) { // e.g. 'strd r2, r3, [r4], r5'
                if (ISSHIFTED(3)) {
                    // same as above
                } else {
                    rz_strbuf_appendf(&op->esil, "%s,%s,0xffffffff,&,=[%d],%s,4,%s,+,0xffffffff,&,=[%d],%s,%s,+=",
                        REG(0), MEMBASE(2), str_ldr_bytes, REG(1), MEMBASE(2), str_ldr_bytes, REG(3), MEMBASE(2));
                }
            }
        }
        break;
    case ARM_INS_TST:
        rz_strbuf_appendf(&op->esil, "0,%s,%s,&,==", ARG(1), ARG(0));
        break;
    case ARM_INS_LDRD:
        addr &= ~3LL;
        if (MEMDISP(2) < 0) {
            const char *pc = "$$";
            if (REGBASE(2) == ARM_REG_PC) {
                op->refptr = 4;
                op->ptr = addr + pcdelta + MEMDISP(2);
                rz_strbuf_appendf(&op->esil, "0x%" PFMT64x ",2,2,%s,%d,+,>>,<<,+,0xffffffff,&,DUP,[4],%s,=,4,+,[4],%s,=",
                    (ut64)MEMDISP(2), pc, pcdelta, REG(0), REG(1));
            } else {
                int disp = MEMDISP(2);
                // not refptr, because we can't grab the reg value statically op->refptr = 4;
                if (disp < 0) {
                    rz_strbuf_appendf(&op->esil, "0x%" PFMT64x ",%s,-,0xffffffff,&,DUP,[4],%s,=,4,+,[4],%s,=",
                        (ut64)-disp, MEMBASE(2), REG(0), REG(1));
                } else {
                    rz_strbuf_appendf(&op->esil, "0x%" PFMT64x ",%s,+,0xffffffff,&,DUP,[4],%s,=,4,+,[4],%s,=",
                        (ut64)disp, MEMBASE(2), REG(0), REG(1));
                }
            }
        } else {
            if (REGBASE(2) == ARM_REG_PC) {
                const char *pc = "$$";
                op->refptr = 4;
                op->ptr = addr + pcdelta + MEMDISP(2);
                if (HASMEMINDEX(2) || ISREG(2)) {
                    const char op_index = ISMEMINDEXSUB(2) ? '-' : '+';
                    rz_strbuf_appendf(&op->esil, "%s,2,2,%d,%s,+,>>,<<,%c,0xffffffff,&,DUP,[4],%s,=,4,+,[4],%s,=",
                        MEMINDEX(2), pcdelta, pc, op_index, REG(0), REG(1));
                } else {
                    rz_strbuf_appendf(&op->esil, "2,2,%d,%s,+,>>,<<,%d,+,0xffffffff,&,DUP,[4],%s,=,4,+,[4],%s,=",
                        pcdelta, pc, MEMDISP(2), REG(0), REG(1));
                }
            } else {
                if (HASMEMINDEX(2)) { // e.g. `ldrd r2, r3 [r4, r1]`
                    const char op_index = ISMEMINDEXSUB(2) ? '-' : '+';
                    rz_strbuf_appendf(&op->esil, "%s,%s,%c,0xffffffff,&,DUP,[4],%s,=,4,+,[4],%s,=",
                        MEMINDEX(2), MEMBASE(2), op_index, REG(0), REG(1));
                } else {
                    rz_strbuf_appendf(&op->esil, "%d,%s,+,0xffffffff,&,DUP,[4],%s,=,4,+,[4],%s,=",
                        MEMDISP(2), MEMBASE(2), REG(0), REG(1));
                }
                if (insn->detail->arm.writeback) {
                    if (ISPOSTINDEX32()) {
                        if (ISIMM(3)) {
                            rz_strbuf_appendf(&op->esil, ",%s,%d,+,%s,=",
                                MEMBASE(2), IMM(3), MEMBASE(2));
                        } else {
                            const char op_index = ISMEMINDEXSUB(3) ? '-' : '+';
                            rz_strbuf_appendf(&op->esil, ",%s,%s,%c,%s,=",
                                REG(3), MEMBASE(2), op_index, MEMBASE(2));
                        }
                    } else if (ISPREINDEX32()) {
                        if (HASMEMINDEX(2)) {
                            const char op_index = ISMEMINDEXSUB(2) ? '-' : '+';
                            rz_strbuf_appendf(&op->esil, ",%s,%s,%c,%s,=",
                                MEMINDEX(2), MEMBASE(2), op_index, MEMBASE(2));
                        } else {
                            rz_strbuf_appendf(&op->esil, ",%s,%d,+,%s,=",
                                MEMBASE(2), MEMDISP(2), MEMBASE(2));
                        }
                    }
                }
            }
        }
        break;
    case ARM_INS_LDRB:
        if (ISMEM(1) && LSHIFT2(1)) {
            rz_strbuf_appendf(&op->esil, "%s,%d,%s,<<,+,0xffffffff,&,[1],0x%x,&,%s,=",
                MEMBASE(1), LSHIFT2(1), MEMINDEX(1), mask, REG(0));
        } else if (HASMEMINDEX(1)) {
            rz_strbuf_appendf(&op->esil, "%s,%s,+,0xffffffff,&,[1],%s,=",
                MEMINDEX(1), MEMBASE(1), REG(0));
        } else {
            rz_strbuf_appendf(&op->esil, "%s,%d,+,[1],%s,=",
                MEMBASE(1), MEMDISP(1), REG(0));
        }
        if (insn->detail->arm.writeback) {
            if (ISIMM(2)) {
                rz_strbuf_appendf(&op->esil, ",%s,%d,+,%s,=",
                    MEMBASE(1), IMM(2), MEMBASE(1));
            } else {
                rz_strbuf_appendf(&op->esil, ",%s,%d,+,%s,=",
                    MEMBASE(1), MEMDISP(1), MEMBASE(1));
            }
        }
        break;
    case ARM_INS_SXTH:
        rz_strbuf_appendf(&op->esil,
            "15,%s,>>,1,&,?{,15,-1,<<,%s,0xffff,&,|,%s,:=,}{,%s,0xffff,%s,:=,}",
            REG(1), REG(1), REG(0), REG(1), REG(0));
        break;
    case ARM_INS_SXTB:
        rz_strbuf_appendf(&op->esil,
            "7,%s,>>,1,&,?{,7,-1,<<,%s,0xff,&,|,%s,:=,}{,%s,0xff,&,%s,:=,}",
            REG(1), REG(1), REG(0), REG(1), REG(0));
        break;
    case ARM_INS_LDREX:
    case ARM_INS_LDREXB:
    case ARM_INS_LDREXD:
    case ARM_INS_LDREXH:
        op->family = RZ_ANALYSIS_OP_FAMILY_THREAD;
        // intentional fallthrough
    case ARM_INS_LDRHT:
    case ARM_INS_LDRH:
    case ARM_INS_LDRT:
    case ARM_INS_LDRBT:
    case ARM_INS_LDRSB:
    case ARM_INS_LDRSBT:
    case ARM_INS_LDRSH:
    case ARM_INS_LDRSHT:
    case ARM_INS_LDR:
        switch (insn->id) {
        case ARM_INS_LDRHT:
        case ARM_INS_LDRH:
        case ARM_INS_LDRSH:
        case ARM_INS_LDRSHT:
            mask = UT16_MAX;
            break;
        default:
            mask = UT32_MAX;
            break;
        }
        addr &= ~3LL;
        if (MEMDISP(1) < 0) {
            const char *pc = "$$";
            if (REGBASE(1) == ARM_REG_PC) {
                op->refptr = 4;
                op->ptr = addr + pcdelta + MEMDISP(1);
                rz_strbuf_appendf(&op->esil, "0x%" PFMT64x ",2,2,%s,>>,<<,+,0xffffffff,&,[4],0x%x,&,%s,=",
                    (ut64)MEMDISP(1), pc, mask, REG(0));
            } else {
                int disp = MEMDISP(1);
                // not refptr, because we can't grab the reg value statically op->refptr = 4;
                if (disp < 0) {
                    rz_strbuf_appendf(&op->esil, "0x%" PFMT64x ",%s,-,0xffffffff,&,[4],0x%x,&,%s,=",
                        (ut64)-disp, MEMBASE(1), mask, REG(0));
                } else {
                    rz_strbuf_appendf(&op->esil, "0x%" PFMT64x ",%s,+,0xffffffff,&,[4],0x%x,&,%s,=",
                        (ut64)disp, MEMBASE(1), mask, REG(0));
                }
            }
        } else {
            if (ISMEM(1) && REGBASE(1) == ARM_REG_PC) {
                const char *pc = "$$";
                if (HASMEMINDEX(1)) {
                    if (LSHIFT2(1)) {
                        rz_strbuf_appendf(&op->esil, "2,2,%d,%s,+,>>,<<,%d,%s,<<,+,0xffffffff,&,[4],0x%x,&,%s,=",
                            pcdelta, pc, LSHIFT2(1), MEMINDEX(1), mask, REG(0));
                    } else {
                        rz_strbuf_appendf(&op->esil, "2,2,%d,%s,+,>>,<<,%s,+,0xffffffff,&,[4],0x%x,&,%s,=",
                            pcdelta, pc, MEMINDEX(1), mask, REG(0));
                    }
                } else {
                    op->refptr = 4;
                    op->ptr = addr + pcdelta + MEMDISP(1);
                    rz_strbuf_appendf(&op->esil, "2,2,%d,%s,+,>>,<<,%d,+,0xffffffff,&,[4],0x%x,&,%s,=",
                        pcdelta, pc, MEMDISP(1), mask, REG(0));
                }
            } else {
                if (ISMEM(1) && LSHIFT2(1)) {
                    rz_strbuf_appendf(&op->esil, "%s,%d,%s,<<,+,0xffffffff,&,[4],0x%x,&,%s,=",
                        MEMBASE(1), LSHIFT2(1), MEMINDEX(1), mask, REG(0));
                } else if (HASMEMINDEX(1)) { // e.g. `ldr r2, [r3, r1]`
                    rz_strbuf_appendf(&op->esil, "%s,%s,+,0xffffffff,&,[4],0x%x,&,%s,=",
                        MEMINDEX(1), MEMBASE(1), mask, REG(0));
                } else {
                    rz_strbuf_appendf(&op->esil, "%d,%s,+,0xffffffff,&,[4],0x%x,&,%s,=",
                        MEMDISP(1), MEMBASE(1), mask, REG(0));
                }
                if (insn->detail->arm.writeback) {
                    if (ISIMM(2)) {
                        rz_strbuf_appendf(&op->esil, ",%s,%d,+,%s,=",
                            MEMBASE(1), IMM(2), MEMBASE(1));
                    } else {
                        rz_strbuf_appendf(&op->esil, ",%s,%d,+,%s,=",
                            MEMBASE(1), MEMDISP(1), MEMBASE(1));
                    }
                }
            }
        }
        break;
    case ARM_INS_MRS:
        // TODO: esil for MRS
        break;
    case ARM_INS_MSR:
        msr_flags = insn->detail->arm.operands[0].reg >> 4;
        rz_strbuf_appendf(&op->esil, "0,");
        if (msr_flags & 1) {
            rz_strbuf_appendf(&op->esil, "0xFF,|,");
        }
        if (msr_flags & 2) {
            rz_strbuf_appendf(&op->esil, "0xFF00,|,");
        }
        if (msr_flags & 4) {
            rz_strbuf_appendf(&op->esil, "0xFF0000,|,");
        }
        if (msr_flags & 8) {
            rz_strbuf_appendf(&op->esil, "0xFF000000,|,");
        }
        rz_strbuf_appendf(&op->esil, "DUP,!,SWAP,&,%s,SWAP,cpsr,&,|,cpsr,=", REG(1));
        break;
    case ARM_INS_UBFX:
        if (IMM(3) > 0 && IMM(3) <= 32 - IMM(2)) {
            rz_strbuf_appendf(&op->esil, "%d,%s,%d,%" PFMT64u ",<<,&,>>,%s,=",
                IMM(2), REG(1), IMM(2), rz_num_bitmask((ut8)IMM(3)), REG(0));
        }
        break;
    case ARM_INS_UXTB:
        rz_strbuf_appendf(&op->esil, "%s,0xff,&,%s,=", ARG(1), REG(0));
        break;
    case ARM_INS_RSB:
        if (OPCOUNT() == 2) {
            rz_strbuf_appendf(&op->esil, "%s,%s,-=", ARG(0), ARG(1));
        } else if (OPCOUNT() == 3) {
            rz_strbuf_appendf(&op->esil, "%s,%s,-,%s,=", ARG(1), ARG(2), ARG(0));
        }
        break;
    case ARM_INS_BIC:
        if (OPCOUNT() == 2) {
            rz_strbuf_appendf(&op->esil, "%s,0xffffffff,^,%s,&=", ARG(1), ARG(0));
        } else {
            rz_strbuf_appendf(&op->esil, "%s,0xffffffff,^,%s,&,%s,=", ARG(2), ARG(1), ARG(0));
        }
        break;
    case ARM_INS_SMMLA:
        rz_strbuf_appendf(&op->esil, "32,%s,%s,*,>>,%s,+,0xffffffff,&,%s,=",
            REG(1), REG(2), REG(3), REG(0));
        break;
    case ARM_INS_SMMLAR:
        rz_strbuf_appendf(&op->esil, "32,0x80000000,%s,%s,*,+,>>,%s,+,0xffffffff,&,%s,=",
            REG(1), REG(2), REG(3), REG(0));
        break;
    case ARM_INS_UMULL:
        rz_strbuf_appendf(&op->esil, "32,%s,%s,*,DUP,0xffffffff,&,%s,=,>>,%s,=",
            REG(2), REG(3), REG(0), REG(1));
        break;
    case ARM_INS_MLS:
        rz_strbuf_appendf(&op->esil, "%s,%s,*,%s,-,0xffffffff,&,%s,=",
            REG(1), REG(2), REG(3), REG(0));
        break;
    case ARM_INS_MLA:
        rz_strbuf_appendf(&op->esil, "%s,%s,*,%s,+,0xffffffff,&,%s,=",
            REG(1), REG(2), REG(3), REG(0));
        break;
    case ARM_INS_MVN:
        rz_strbuf_appendf(&op->esil, "-1,%s,^,0xffffffff,&,%s,=",
            ARG(1), REG(0));
        break;
    case ARM_INS_BFI: {
        if (OPCOUNT() >= 3 && ISIMM(3) && IMM(3) > 0 && IMM(3) < 64) {
            ut64 mask = rz_num_bitmask((ut8)IMM(3));
            ut64 shift = IMM(2);
            ut64 notmask = ~(mask << shift);
            // notmask,dst,&,lsb,mask,src,&,<<,|,dst,=
            rz_strbuf_setf(&op->esil, "%" PFMT64u ",%s,&,%" PFMT64u ",%" PFMT64u ",%s,&,<<,|,0xffffffff,&,%s,=",
                notmask, REG(0), shift, mask, REG(1), REG(0));
        }
        break;
    }
    case ARM_INS_BFC: {
        if (OPCOUNT() >= 2 && ISIMM(2) && IMM(2) > 0 && IMM(2) < 64) {
            ut64 mask = rz_num_bitmask((ut8)IMM(2));
            ut64 shift = IMM(1);
            ut64 notmask = ~(mask << shift);
            // notmask,dst,&,dst,=
            rz_strbuf_setf(&op->esil, "%" PFMT64u ",%s,&,0xffffffff,&,%s,=",
                notmask, REG(0), REG(0));
        }
        break;
    }
    case ARM_INS_REV: {
        const char *r0 = REG(0);
        const char *r1 = REG(1);
        rz_strbuf_setf(&op->esil,
            "24,0xff,%s,&,<<,%s,=,"
            "16,0xff,8,%s,>>,&,<<,%s,|=,"
            "8,0xff,16,%s,>>,&,<<,%s,|=,"
            "0xff,24,%s,>>,&,%s,|=,",
            r1, r0, r1, r0, r1, r0, r1, r0);
        break;
    }
    case ARM_INS_REV16: {
        const char *r0 = REG(0);
        const char *r1 = REG(1);
        rz_strbuf_setf(&op->esil,
            "8,0xff00ff00,%s,&,>>,%s,=,"
            "8,0x00ff00ff,%s,&,<<,%s,|=,",
            r1, r0, r1, r0);
        break;
    }
    case ARM_INS_REVSH: {
        const char *r0 = REG(0);
        const char *r1 = REG(1);
        rz_strbuf_setf(&op->esil,
            "8,0xff00,%s,&,>>,%s,=,"
            "8,0x00ff,%s,&,<<,%s,|=,"
            "0x8000,%s,&,?{,"
            "0xffff0000,%s,|=,"
            "}",
            r1, r0, r1, r0, r0, r0);
        break;
    }
    case ARM_INS_TBB:
        rz_strbuf_appendf(&op->esil, "%s,%s,+,0xffffffff,&,DUP,[1],1,SWAP,<<,+,pc,+=",
            MEMBASE(0), MEMINDEX(0));
        break;
    case ARM_INS_TBH:
        rz_strbuf_appendf(&op->esil, "%s,%d,%s,<<,+,0xffffffff,&,[2],1,SWAP,<<,pc,+=",
            MEMBASE(0), LSHIFT2(0), MEMINDEX(0));
        break;
    default:
        break;
    }
    // Update flags if required...TODO different instructions update different flags, but this should fix
    // many errors
    if (insn->detail->arm.update_flags) {
        switch (insn->id) {
        case ARM_INS_CMP:
            rz_strbuf_appendf(&op->esil, ",$z,zf,:=,31,$s,nf,:=,32,$b,!,cf,:=,31,$o,vf,:=");
            break;
        case ARM_INS_ADD:
        case ARM_INS_RSB:
        case ARM_INS_SUB:
        case ARM_INS_SBC:
        case ARM_INS_ADC:
        case ARM_INS_CMN:
            rz_strbuf_appendf(&op->esil, ",$z,zf,:=,31,$s,nf,:=,31,$c,cf,:=,31,$o,vf,:=");
            break;
        default:
            rz_strbuf_appendf(&op->esil, ",$z,zf,:=,31,$s,nf,:=");
        }
    }
 
    rz_strbuf_append(&op->esil, postfix);
 
    return 0;
}

References addr, ARG, ARM_INS_ADC, ARM_INS_ADD, ARM_INS_ADDW, ARM_INS_ADR, ARM_INS_AND, ARM_INS_ASR, ARM_INS_B, ARM_INS_BFC, ARM_INS_BFI, ARM_INS_BIC, ARM_INS_BKPT, ARM_INS_BL, ARM_INS_BLX, ARM_INS_BX, ARM_INS_BXJ, ARM_INS_CBNZ, ARM_INS_CBZ, ARM_INS_CLZ, ARM_INS_CMN, ARM_INS_CMP, ARM_INS_EOR, ARM_INS_IT, ARM_INS_LDM, ARM_INS_LDMDA, ARM_INS_LDMDB, ARM_INS_LDMIB, ARM_INS_LDR, ARM_INS_LDRB, ARM_INS_LDRBT, ARM_INS_LDRD, ARM_INS_LDREX, ARM_INS_LDREXB, ARM_INS_LDREXD, ARM_INS_LDREXH, ARM_INS_LDRH, ARM_INS_LDRHT, ARM_INS_LDRSB, ARM_INS_LDRSBT, ARM_INS_LDRSH, ARM_INS_LDRSHT, ARM_INS_LDRT, ARM_INS_LSL, ARM_INS_LSR, ARM_INS_MLA, ARM_INS_MLS, ARM_INS_MOV, ARM_INS_MOVT, ARM_INS_MOVW, ARM_INS_MRS, ARM_INS_MSR, ARM_INS_MUL, ARM_INS_MVN, ARM_INS_NOP, ARM_INS_ORN, ARM_INS_ORR, ARM_INS_POP, ARM_INS_PUSH, ARM_INS_REV, ARM_INS_REV16, ARM_INS_REVSH, ARM_INS_RSB, ARM_INS_SADD16, ARM_INS_SADD8, ARM_INS_SBC, ARM_INS_SMMLA, ARM_INS_SMMLAR, ARM_INS_SSUB16, ARM_INS_SSUB8, ARM_INS_STM, ARM_INS_STMDA, ARM_INS_STMDB, ARM_INS_STMIB, ARM_INS_STR, ARM_INS_STRB, ARM_INS_STRBT, ARM_INS_STRD, ARM_INS_STRH, ARM_INS_STRHT, ARM_INS_STRT, ARM_INS_SUB, ARM_INS_SUBW, ARM_INS_SVC, ARM_INS_SXTB, ARM_INS_SXTH, ARM_INS_TBB, ARM_INS_TBH, ARM_INS_TST, ARM_INS_UBFX, ARM_INS_UDF, ARM_INS_UMULL, ARM_INS_UXTB, ARM_INS_VLDMDB, ARM_INS_VLDMIA, ARM_INS_VMOV, ARM_INS_VSTMDB, ARM_INS_VSTMIA, ARM_REG_PC, ARM_SFT_ASR, ARM_SFT_LSL, ARM_SFT_LSR, ARM_SFT_ROR, ARM_SFT_RRX, HASMEMINDEX, i, IMM, ISIMM, ISMEM, ISMEMINDEXSUB, ISPOSTINDEX32, ISPREINDEX32, ISREG, ISSHIFTED, lr, LSHIFT2, mask, MATH32, MATH32_NEG, MATH32AS, MEMBASE, MEMDISP, MEMINDEX, NULL, OPCOUNT, pc, PFMT32u, PFMT64u, PFMT64x, r0, r1, r4, r5, r6, r7, REG, REGBASE, REGID, REGSIZE32, RZ_ANALYSIS_OP_FAMILY_THREAD, rz_arm_cs_esil_prefix_cond(), rz_num_bitmask(), rz_strbuf_append(), rz_strbuf_appendf(), rz_strbuf_init(), rz_strbuf_set(), rz_strbuf_setf(), shift(), SHIFTTYPE, SHIFTVALUE, sp, cmd_descs_generate::str, UT16_MAX, UT32_MAX, ut64(), and width.

Referenced by analysis_op().

rz_arm_cs_analysis_op_64_esil()

RZ_IPI int rz_arm_cs_analysis_op_64_esil	(	RzAnalysis *	a,
		RzAnalysisOp *	op,
		ut64	addr,
		const ut8 *	buf,
		int	len,
		csh *	handle,
		cs_insn *	insn
	)

Definition at line 202 of file arm_esil64.c.

                                                                                                                                          {
    const char *postfix = NULL;
 
    rz_strbuf_init(&op->esil);
    rz_strbuf_set(&op->esil, "");
 
    postfix = rz_arm_cs_esil_prefix_cond(op, insn->detail->arm64.cc);
 
    switch (insn->id) {
    case ARM64_INS_REV:
        // these REV* instructions were almost right, except in the cases like rev x0, x0
        // where the use of |= caused copies of the value to be erroneously present
        {
            const char *r0 = REG64(0);
            const char *r1 = REG64(1);
            int size = REGSIZE64(1);
#if 0
        rz_strbuf_setf (&op->esil,
            "0,%s,=,"                        // dst = 0
            "%d,"                            // initial counter = size
            "DUP,"                           // counter: size -> 0 (repeat here)
                "DUP,1,SWAP,-,8,*,"          // counter to bits in source
                    "DUP,0xff,<<,%s,&,>>,"   // src byte moved to LSB
                "SWAP,%d,-,8,*,"             // invert counter, calc dst bit
                "SWAP,<<,%s,|=,"             // shift left to there and insert
            "4,REPEAT",                      // goto 5th instruction
            r0, size, r1, size, r0);
#endif
            if (size == 8) {
                rz_strbuf_setf(&op->esil,
                    "56,0xff,%s,&,<<,tmp,=,"
                    "48,0xff,8,%s,>>,&,<<,tmp,|=,"
                    "40,0xff,16,%s,>>,&,<<,tmp,|=,"
                    "32,0xff,24,%s,>>,&,<<,tmp,|=,"
                    "24,0xff,32,%s,>>,&,<<,tmp,|=,"
                    "16,0xff,40,%s,>>,&,<<,tmp,|=,"
                    "8,0xff,48,%s,>>,&,<<,tmp,|=,"
                    "0xff,56,%s,>>,&,tmp,|=,tmp,%s,=",
                    r1, r1, r1, r1,
                    r1, r1, r1, r1, r0);
            } else {
                rz_strbuf_setf(&op->esil,
                    "24,0xff,%s,&,<<,tmp,=,"
                    "16,0xff,8,%s,>>,&,<<,tmp,|=,"
                    "8,0xff,16,%s,>>,&,<<,tmp,|=,"
                    "0xff,24,%s,>>,&,tmp,|=,tmp,%s,=",
                    r1, r1, r1, r1, r0);
            }
            break;
        }
    case ARM64_INS_REV32: {
        const char *r0 = REG64(0);
        const char *r1 = REG64(1);
        rz_strbuf_setf(&op->esil,
            "24,0x000000ff000000ff,%s,&,<<,tmp,=,"
            "16,0x000000ff000000ff,8,%s,>>,&,<<,tmp,|=,"
            "8,0x000000ff000000ff,16,%s,>>,&,<<,tmp,|=,"
            "0x000000ff000000ff,24,%s,>>,&,tmp,|=,tmp,%s,=",
            r1, r1, r1, r1, r0);
        break;
    }
    case ARM64_INS_REV16: {
        const char *r0 = REG64(0);
        const char *r1 = REG64(1);
        rz_strbuf_setf(&op->esil,
            "8,0xff00ff00ff00ff00,%s,&,>>,tmp,=,"
            "8,0x00ff00ff00ff00ff,%s,&,<<,tmp,|=,tmp,%s,=",
            r1, r1, r0);
        break;
    }
    case ARM64_INS_ADR:
        // TODO: must be 21bit signed
        rz_strbuf_setf(&op->esil,
            "%" PFMT64d ",%s,=", IMM64(1), REG64(0));
        break;
    case ARM64_INS_SMADDL: {
        int size = REGSIZE64(1) * 8;
        rz_strbuf_setf(&op->esil, "%d,%s,~,%d,%s,~,*,%s,+,%s,=",
            size, REG64(2), size, REG64(1), REG64(3), REG64(0));
        break;
    }
    case ARM64_INS_UMADDL:
    case ARM64_INS_FMADD:
    case ARM64_INS_MADD:
        rz_strbuf_setf(&op->esil, "%s,%s,*,%s,+,%s,=",
            REG64(2), REG64(1), REG64(3), REG64(0));
        break;
    case ARM64_INS_MSUB:
        rz_strbuf_setf(&op->esil, "%s,%s,*,%s,-,%s,=",
            REG64(2), REG64(1), REG64(3), REG64(0));
        break;
    case ARM64_INS_MNEG:
        rz_strbuf_setf(&op->esil, "%s,%s,*,0,-,%s,=",
            REG64(2), REG64(1), REG64(0));
        break;
    case ARM64_INS_ADD:
    case ARM64_INS_ADC: // Add with carry.
        // case ARM64_INS_ADCS: // Add with carry.
        OPCALL("+");
        break;
    case ARM64_INS_SUB:
        OPCALL("-");
        break;
    case ARM64_INS_SBC:
        // TODO have to check this more, VEX does not work
        rz_strbuf_setf(&op->esil, "%s,cf,+,%s,-,%s,=",
            REG64(2), REG64(1), REG64(0));
        break;
    case ARM64_INS_SMULL: {
        int size = REGSIZE64(1) * 8;
        rz_strbuf_setf(&op->esil, "%d,%s,~,%d,%s,~,*,%s,=",
            size, REG64(2), size, REG64(1), REG64(0));
        break;
    }
    case ARM64_INS_MUL:
        OPCALL("*");
        break;
    case ARM64_INS_AND:
        OPCALL("&");
        break;
    case ARM64_INS_ORR:
        OPCALL("|");
        break;
    case ARM64_INS_EOR:
        OPCALL("^");
        break;
    case ARM64_INS_ORN:
        OPCALL_NEG("|");
        break;
    case ARM64_INS_EON:
        OPCALL_NEG("^");
        break;
    case ARM64_INS_LSR: {
        const char *r0 = REG64(0);
        const char *r1 = REG64(1);
        const int size = REGSIZE64(0) * 8;
 
        if (ISREG64(2)) {
            if (LSHIFT2_64(2) || EXT64(2)) {
                SHIFTED_REG64_APPEND(&op->esil, 2);
                rz_strbuf_appendf(&op->esil, ",%d,%%,%s,>>,%s,=", size, r1, r0);
            } else {
                const char *r2 = REG64(2);
                rz_strbuf_setf(&op->esil, "%d,%s,%%,%s,>>,%s,=", size, r2, r1, r0);
            }
        } else {
            ut64 i2 = IMM64(2);
            rz_strbuf_setf(&op->esil, "%" PFMT64d ",%s,>>,%s,=", i2 % (ut64)size, r1, r0);
        }
        break;
    }
    case ARM64_INS_LSL: {
        const char *r0 = REG64(0);
        const char *r1 = REG64(1);
        const int size = REGSIZE64(0) * 8;
 
        if (ISREG64(2)) {
            if (LSHIFT2_64(2) || EXT64(2)) {
                SHIFTED_REG64_APPEND(&op->esil, 2);
                rz_strbuf_appendf(&op->esil, ",%d,%%,%s,<<,%s,=", size, r1, r0);
            } else {
                const char *r2 = REG64(2);
                rz_strbuf_setf(&op->esil, "%d,%s,%%,%s,<<,%s,=", size, r2, r1, r0);
            }
        } else {
            ut64 i2 = IMM64(2);
            rz_strbuf_setf(&op->esil, "%" PFMT64d ",%s,<<,%s,=", i2 % (ut64)size, r1, r0);
        }
        break;
    }
    case ARM64_INS_ROR:
        OPCALL(">>>");
        break;
    case ARM64_INS_NOP:
        rz_strbuf_setf(&op->esil, ",");
        break;
    case ARM64_INS_FDIV:
        break;
    case ARM64_INS_SDIV: {
        /* TODO: support WZR XZR to specify 32, 64bit op */
        int size = REGSIZE64(1) * 8;
        if (ISREG64(2)) {
            rz_strbuf_setf(&op->esil, "%d,%s,~,%d,%s,~,~/,%s,=", size, REG64(2), size, REG64(1), REG64(0));
        } else {
            rz_strbuf_setf(&op->esil, "%d,%s,~,%d,%s,~,~/,%s,=", size, REG64(1), size, REG64(0), REG64(0));
        }
        break;
    }
    case ARM64_INS_UDIV:
        /* TODO: support WZR XZR to specify 32, 64bit op */
        if ISREG64 (2) {
            rz_strbuf_setf(&op->esil, "%s,%s,/,%s,=", REG64(2), REG64(1), REG64(0));
        } else {
            rz_strbuf_setf(&op->esil, "%s,%s,/=", REG64(1), REG64(0));
        }
        break;
    case ARM64_INS_BR:
        rz_strbuf_setf(&op->esil, "%s,pc,=", REG64(0));
        break;
    case ARM64_INS_B:
        /* capstone precompute resulting address, using PC + IMM */
        rz_strbuf_appendf(&op->esil, "%" PFMT64d ",pc,=", IMM64(0));
        break;
    case ARM64_INS_BL:
        rz_strbuf_setf(&op->esil, "pc,lr,=,%" PFMT64d ",pc,=", IMM64(0));
        break;
    case ARM64_INS_BLR:
        rz_strbuf_setf(&op->esil, "pc,lr,=,%s,pc,=", REG64(0));
        break;
    case ARM64_INS_CLZ:;
        int size = 8 * REGSIZE64(0);
 
        // expression is much more concise with GOTO, but GOTOs should be minimized
        // rz_strbuf_setf (&op->esil, "%s,%s,=,0,DUP,%d,1,<<,%s,&,%d,>,&,?{,%s,=,}{,1,%s,<<=,1,+,4,GOTO,}",
        //  REG64 (1), REG64 (0), size*8 - 1, REG64 (0), REG64 (0), REG64 (0));
 
        /*
        from https://en.wikipedia.org/wiki/Find_first_set modified for up to size 64
        function clz3 (x)
            if x = 0 return 32
            n ← 0
            if (x & 0xFFFF0000) = 0: n ← n + 16, x ← x << 16
            if (x & 0xFF000000) = 0: n ← n +  8, x ← x <<  8
            if (x & 0xF0000000) = 0: n ← n +  4, x ← x <<  4
            if (x & 0xC0000000) = 0: n ← n +  2, x ← x <<  2
            if (x & 0x80000000) = 0: n ← n +  1
            return n
        */
 
        const char *r0 = REG64(0);
        const char *r1 = REG64(1);
 
        if (size == 32) {
            rz_strbuf_setf(&op->esil,
                "%s,tmp,=,0,"
                "tmp,0xffff0000,&,!,?{,16,tmp,<<=,16,+,},"
                "tmp,0xff000000,&,!,?{,8,tmp,<<=,8,+,},"
                "tmp,0xf0000000,&,!,?{,4,tmp,<<=,4,+,},"
                "tmp,0xc0000000,&,!,?{,2,tmp,<<=,2,+,},"
                "tmp,0x80000000,&,!,?{,1,+,},"
                "%s,!,?{,32,%s,=,}{,%s,=,}",
                r1, r1, r0, r0);
        } else {
            rz_strbuf_setf(&op->esil,
                "%s,tmp,=,0,"
                "tmp,0xffffffff00000000,&,!,?{,32,tmp,<<=,32,+,},"
                "tmp,0xffff000000000000,&,!,?{,16,tmp,<<=,16,+,},"
                "tmp,0xff00000000000000,&,!,?{,8,tmp,<<=,8,+,},"
                "tmp,0xf000000000000000,&,!,?{,4,tmp,<<=,4,+,},"
                "tmp,0xc000000000000000,&,!,?{,2,tmp,<<=,2,+,},"
                "tmp,0x8000000000000000,&,!,?{,1,+,},"
                "%s,!,?{,64,%s,=,}{,%s,=,}",
                r1, r1, r0, r0);
        }
 
        break;
    case ARM64_INS_LDRH:
    case ARM64_INS_LDUR:
    case ARM64_INS_LDURB:
    case ARM64_INS_LDURH:
    case ARM64_INS_LDR:
    // case ARM64_INS_LDRSB:
    // case ARM64_INS_LDRSH:
    case ARM64_INS_LDRB:
    // case ARM64_INS_LDRSW:
    // case ARM64_INS_LDURSW:
    case ARM64_INS_LDXR:
    case ARM64_INS_LDXRB:
    case ARM64_INS_LDXRH:
    case ARM64_INS_LDAXR:
    case ARM64_INS_LDAXRB:
    case ARM64_INS_LDAXRH:
    case ARM64_INS_LDAR:
    case ARM64_INS_LDARB:
    case ARM64_INS_LDARH: {
        int size = REGSIZE64(0);
        switch (insn->id) {
        case ARM64_INS_LDRB:
        case ARM64_INS_LDARB:
        case ARM64_INS_LDAXRB:
        case ARM64_INS_LDXRB:
        case ARM64_INS_LDURB:
            size = 1;
            break;
        case ARM64_INS_LDRH:
        case ARM64_INS_LDARH:
        case ARM64_INS_LDXRH:
        case ARM64_INS_LDAXRH:
        case ARM64_INS_LDURH:
            size = 2;
            break;
        case ARM64_INS_LDRSW:
        case ARM64_INS_LDURSW:
            size = 4;
            break;
        default:
            break;
        }
 
        if (ISMEM64(1)) {
            if (HASMEMINDEX64(1)) {
                if (LSHIFT2_64(1) || EXT64(1)) {
                    SHIFTED_REG64_APPEND(&op->esil, 1);
                    rz_strbuf_appendf(&op->esil, ",%s,+,[%d],%s,=", MEMBASE64(1), size, REG64(0));
                } else {
                    rz_strbuf_appendf(&op->esil, "%s,%s,+,[%d],%s,=",
                        MEMBASE64(1), MEMINDEX64(1), size, REG64(0));
                }
            } else {
                // I really don't like the DUP / tmp approach but its better than doubling the calculation
                if (LSHIFT2_64(1)) {
                    rz_strbuf_appendf(&op->esil, "%s,%d,%" PFMT64d ",%s,+",
                        MEMBASE64(1), LSHIFT2_64(1), MEMDISP64(1), DECODE_SHIFT64(1));
                } else if ((int)MEMDISP64(1) < 0) {
                    rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%s,-",
                        -(st64)MEMDISP64(1), MEMBASE64(1));
                } else {
                    rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%s,+",
                        MEMDISP64(1), MEMBASE64(1));
                }
 
                rz_strbuf_append(&op->esil, ",DUP,tmp,=");
 
                // I assume the DUPs here previously were to handle preindexing
                // but it was never finished?
                if (ISPREINDEX64()) {
                    rz_strbuf_appendf(&op->esil, ",tmp,%s,=", REG64(1));
                }
 
                rz_strbuf_appendf(&op->esil, ",[%d],%s,=", size, REG64(0));
 
                if (ISPOSTINDEX64()) {
                    if (ISREG64(2)) { // not sure if register valued post indexing exists?
                        rz_strbuf_appendf(&op->esil, ",tmp,%s,+,%s,=", REG64(2), REG64(1));
                    } else {
                        rz_strbuf_appendf(&op->esil, ",tmp,%" PFMT64d ",+,%s,=", IMM64(2), REG64(1));
                    }
                }
            }
            op->refptr = 4;
        } else {
            if (ISREG64(1)) {
                if (OPCOUNT64() == 2) {
                    rz_strbuf_setf(&op->esil, "%s,[%d],%s,=",
                        REG64(1), size, REG64(0));
                } else if (OPCOUNT64() == 3) {
                    /*
                        This seems like a capstone bug:
                        instructions like
                            ldr x16, [x13, x9]
                            ldrb w2, [x19, x23]
                        are not detected as ARM64_OP_MEM type and
                        fall in this case instead.
                    */
                    if (ISREG64(2)) {
                        rz_strbuf_setf(&op->esil, "%s,%s,+,[%d],%s,=",
                            REG64(1), REG64(2), size, REG64(0));
                    }
                }
            } else {
                rz_strbuf_setf(&op->esil, "%" PFMT64d ",[%d],%s,=",
                    IMM64(1), size, REG64(0));
            }
        }
        break;
    }
    case ARM64_INS_LDRSB:
    case ARM64_INS_LDRSH:
    case ARM64_INS_LDRSW:
    case ARM64_INS_LDURSB:
    case ARM64_INS_LDURSH:
    case ARM64_INS_LDURSW: {
        // handle the sign extended instrs here
        int size = REGSIZE64(0);
        switch (insn->id) {
        case ARM64_INS_LDRSB:
        case ARM64_INS_LDURSB:
            size = 1;
            break;
        case ARM64_INS_LDRSH:
        case ARM64_INS_LDURSH:
            size = 2;
            break;
        case ARM64_INS_LDRSW:
        case ARM64_INS_LDURSW:
            size = 4;
            break;
        default:
            break;
        }
 
        if (ISMEM64(1)) {
            if (HASMEMINDEX64(1)) {
                if (LSHIFT2_64(1) || EXT64(1)) {
                    rz_strbuf_appendf(&op->esil, "%d,%s,", size * 8, MEMBASE64(1));
                    SHIFTED_REG64_APPEND(&op->esil, 1);
                    rz_strbuf_appendf(&op->esil, ",+,[%d],~,%s,=", size, REG64(0));
                } else {
                    rz_strbuf_appendf(&op->esil, "%d,%s,%s,+,[%d],~,%s,=",
                        size * 8, MEMBASE64(1), MEMINDEX64(1), size, REG64(0));
                }
            } else {
                if (LSHIFT2_64(1)) {
                    rz_strbuf_appendf(&op->esil, "%d,%s,%d,%" PFMT64d ",%s",
                        size * 8, MEMBASE64(1), LSHIFT2_64(1), MEMDISP64(1), DECODE_SHIFT64(1));
                } else if ((int)MEMDISP64(1) < 0) {
                    rz_strbuf_appendf(&op->esil, "%d,%" PFMT64d ",%s,-",
                        size * 8, -(st64)MEMDISP64(1), MEMBASE64(1));
                } else {
                    rz_strbuf_appendf(&op->esil, "%d,%" PFMT64d ",%s,+",
                        size * 8, MEMDISP64(1), MEMBASE64(1));
                }
 
                rz_strbuf_append(&op->esil, ",DUP,tmp,=");
 
                // I assume the DUPs here previously were to handle preindexing
                // but it was never finished?
                if (ISPREINDEX64()) {
                    rz_strbuf_appendf(&op->esil, ",tmp,%s,=", REG64(1));
                }
 
                rz_strbuf_appendf(&op->esil, ",[%d],~,%s,=", size, REG64(0));
 
                if (ISPOSTINDEX64()) {
                    if (ISREG64(2)) { // not sure if register valued post indexing exists?
                        rz_strbuf_appendf(&op->esil, ",tmp,%s,+,%s,=", REG64(2), REG64(1));
                    } else {
                        rz_strbuf_appendf(&op->esil, ",tmp,%" PFMT64d ",+,%s,=", IMM64(2), REG64(1));
                    }
                }
            }
            op->refptr = 4;
        } else {
            if (ISREG64(1)) {
                if (OPCOUNT64() == 2) {
                    rz_strbuf_setf(&op->esil, "%d,%s,[%d],~,%s,=",
                        size * 8, REG64(1), size, REG64(0));
                } else if (OPCOUNT64() == 3) {
                    /*
                        This seems like a capstone bug:
                        instructions like
                            ldr x16, [x13, x9]
                            ldrb w2, [x19, x23]
                        are not detected as ARM64_OP_MEM type and
                        fall in this case instead.
                    */
                    if (ISREG64(2)) {
                        rz_strbuf_setf(&op->esil, "%d,%s,%s,+,[%d],~,%s,=",
                            size * 8, REG64(1), REG64(2), size, REG64(0));
                    }
                }
            } else {
                rz_strbuf_setf(&op->esil, "%d,%" PFMT64d ",[%d],~,%s,=",
                    size * 8, IMM64(1), size, REG64(0));
            }
        }
        break;
    }
    case ARM64_INS_FCMP:
    case ARM64_INS_CCMP:
    case ARM64_INS_CCMN:
    case ARM64_INS_TST: // cmp w8, 0xd
    case ARM64_INS_CMP: // cmp w8, 0xd
    case ARM64_INS_CMN: // cmp w8, 0xd
    {
        // update esil, cpu flags
        int bits = arm64_reg_width(REGID64(0));
        if (ISIMM64(1)) {
            rz_strbuf_setf(&op->esil, "%" PFMT64d ",%s,==,$z,zf,:=,%d,$s,nf,:=,%d,$b,!,cf,:=,%d,$o,vf,:=", IMM64(1) << LSHIFT2_64(1), REG64(0), bits - 1, bits, bits - 1);
        } else {
            // cmp w10, w11
            SHIFTED_REG64_APPEND(&op->esil, 1);
            rz_strbuf_appendf(&op->esil, ",%s,==,$z,zf,:=,%d,$s,nf,:=,%d,$b,!,cf,:=,%d,$o,vf,:=", REG64(0), bits - 1, bits, bits - 1);
        }
        break;
    }
    case ARM64_INS_FCSEL:
    case ARM64_INS_CSEL: // csel Wd, Wn, Wm --> Wd := (cond) ? Wn : Wm
        rz_strbuf_appendf(&op->esil, "%s,}{,%s,},%s,=", REG64(1), REG64(2), REG64(0));
        postfix = "";
        break;
    case ARM64_INS_CSET: // cset Wd --> Wd := (cond) ? 1 : 0
        rz_strbuf_appendf(&op->esil, "1,}{,0,},%s,=", REG64(0));
        postfix = "";
        break;
    case ARM64_INS_CINC: // cinc Wd, Wn --> Wd := (cond) ? (Wn+1) : Wn
        rz_strbuf_appendf(&op->esil, "1,%s,+,}{,%s,},%s,=", REG64(1), REG64(1), REG64(0));
        postfix = "";
        break;
    case ARM64_INS_CSINC: // csinc Wd, Wn, Wm --> Wd := (cond) ? Wn : (Wm+1)
        rz_strbuf_appendf(&op->esil, "%s,}{,1,%s,+,},%s,=", REG64(1), REG64(2), REG64(0));
        postfix = "";
        break;
    case ARM64_INS_STXRB:
    case ARM64_INS_STXRH:
    case ARM64_INS_STXR: {
        int size = REGSIZE64(1);
        if (insn->id == ARM64_INS_STXRB) {
            size = 1;
        } else if (insn->id == ARM64_INS_STXRH) {
            size = 2;
        }
        rz_strbuf_setf(&op->esil, "0,%s,=,%s,%s,%" PFMT64d ",+,=[%d]",
            REG64(0), REG64(1), MEMBASE64(1), MEMDISP64(1), size);
        break;
    }
    case ARM64_INS_STRB:
    case ARM64_INS_STRH:
    case ARM64_INS_STUR:
    case ARM64_INS_STURB:
    case ARM64_INS_STURH:
    case ARM64_INS_STR: // str x6, [x6,0xf90]
    {
        int size = REGSIZE64(0);
        if (insn->id == ARM64_INS_STRB || insn->id == ARM64_INS_STURB) {
            size = 1;
        } else if (insn->id == ARM64_INS_STRH || insn->id == ARM64_INS_STURH) {
            size = 2;
        }
        if (ISMEM64(1)) {
            if (HASMEMINDEX64(1)) {
                if (LSHIFT2_64(1) || EXT64(1)) {
                    rz_strbuf_appendf(&op->esil, "%s,%s,", REG64(0), MEMBASE64(1));
                    SHIFTED_REG64_APPEND(&op->esil, 1);
                    rz_strbuf_appendf(&op->esil, ",+,=[%d]", size);
                } else {
                    rz_strbuf_appendf(&op->esil, "%s,%s,%s,+,=[%d]",
                        REG64(0), MEMBASE64(1), MEMINDEX64(1), size);
                }
            } else {
                if (LSHIFT2_64(1)) {
                    rz_strbuf_appendf(&op->esil, "%s,%s,%d,%" PFMT64d ",%s,+",
                        REG64(0), MEMBASE64(1), LSHIFT2_64(1), MEMDISP64(1), DECODE_SHIFT64(1));
                } else if ((int)MEMDISP64(1) < 0) {
                    rz_strbuf_appendf(&op->esil, "%s,%" PFMT64d ",%s,-",
                        REG64(0), -(st64)MEMDISP64(1), MEMBASE64(1));
                } else {
                    rz_strbuf_appendf(&op->esil, "%s,%" PFMT64d ",%s,+",
                        REG64(0), MEMDISP64(1), MEMBASE64(1));
                }
 
                rz_strbuf_append(&op->esil, ",DUP,tmp,=");
 
                // I assume the DUPs here previously were to handle preindexing
                // but it was never finished?
                if (ISPREINDEX64()) {
                    rz_strbuf_appendf(&op->esil, ",tmp,%s,=", REG64(1));
                }
 
                rz_strbuf_appendf(&op->esil, ",=[%d]", size);
 
                if (ISPOSTINDEX64()) {
                    if (ISREG64(2)) { // not sure if register valued post indexing exists?
                        rz_strbuf_appendf(&op->esil, ",tmp,%s,+,%s,=", REG64(2), REG64(1));
                    } else {
                        rz_strbuf_appendf(&op->esil, ",tmp,%" PFMT64d ",+,%s,=", IMM64(2), REG64(1));
                    }
                }
            }
            op->refptr = 4;
        } else {
            if (ISREG64(1)) {
                if (OPCOUNT64() == 2) {
                    rz_strbuf_setf(&op->esil, "%s,%s,=[%d]",
                        REG64(0), REG64(1), size);
                } else if (OPCOUNT64() == 3) {
                    /*
                        This seems like a capstone bug:
                        instructions like
                            ldr x16, [x13, x9]
                            ldrb w2, [x19, x23]
                        are not detected as ARM64_OP_MEM type and
                        fall in this case instead.
                    */
                    if (ISREG64(2)) {
                        rz_strbuf_setf(&op->esil, "%s,%s,%s,+,=[%d]",
                            REG64(0), REG64(1), REG64(2), size);
                    }
                }
            } else {
                rz_strbuf_setf(&op->esil, "%s,%" PFMT64d ",=[%d]",
                    REG64(0), IMM64(1), size);
            }
        }
        break;
    }
    case ARM64_INS_BIC:
        if (OPCOUNT64() == 2) {
            if (REGSIZE64(0) == 4) {
                rz_strbuf_appendf(&op->esil, "%s,0xffffffff,^,%s,&=", REG64(1), REG64(0));
            } else {
                rz_strbuf_appendf(&op->esil, "%s,0xffffffffffffffff,^,%s,&=", REG64(1), REG64(0));
            }
        } else {
            if (REGSIZE64(0) == 4) {
                rz_strbuf_appendf(&op->esil, "%s,0xffffffff,^,%s,&,%s,=", REG64(2), REG64(1), REG64(0));
            } else {
                rz_strbuf_appendf(&op->esil, "%s,0xffffffffffffffff,^,%s,&,%s,=", REG64(2), REG64(1), REG64(0));
            }
        }
        break;
    case ARM64_INS_CBZ:
        rz_strbuf_setf(&op->esil, "%s,!,?{,%" PFMT64d ",pc,=,}",
            REG64(0), IMM64(1));
        break;
    case ARM64_INS_CBNZ:
        rz_strbuf_setf(&op->esil, "%s,?{,%" PFMT64d ",pc,=,}",
            REG64(0), IMM64(1));
        break;
    case ARM64_INS_TBZ:
        // tbnz x0, 4, label
        // if ((1<<4) & x0) goto label;
        rz_strbuf_setf(&op->esil, "%" PFMT64d ",1,<<,%s,&,!,?{,%" PFMT64d ",pc,=,}",
            IMM64(1), REG64(0), IMM64(2));
        break;
    case ARM64_INS_TBNZ:
        // tbnz x0, 4, label
        // if ((1<<4) & x0) goto label;
        rz_strbuf_setf(&op->esil, "%" PFMT64d ",1,<<,%s,&,?{,%" PFMT64d ",pc,=,}",
            IMM64(1), REG64(0), IMM64(2));
        break;
    case ARM64_INS_STNP:
    case ARM64_INS_STP: // stp x6, x7, [x6,0xf90]
    {
        int disp = (int)MEMDISP64(2);
        char sign = disp >= 0 ? '+' : '-';
        ut64 abs = disp >= 0 ? MEMDISP64(2) : -MEMDISP64(2);
        int size = REGSIZE64(0);
        // Pre-index case
        if (ISPREINDEX64()) {
            // "stp x2, x3, [x8, 0x20]!
            // "32,x8,+=,x2,x8,=[8],x3,x8,8,+,=[8]",
            rz_strbuf_setf(&op->esil,
                "%" PFMT64d ",%s,%c=,%s,%s,=[%d],%s,%s,%d,+,=[%d]",
                abs, MEMBASE64(2), sign,
                REG64(0), MEMBASE64(2), size,
                REG64(1), MEMBASE64(2), size, size);
            // Post-index case
        } else if (ISPOSTINDEX64()) {
            int val = IMM64(3);
            sign = val >= 0 ? '+' : '-';
            abs = val >= 0 ? val : -val;
            // "stp x4, x5, [x8], 0x10"
            // "x4,x8,=[],x5,x8,8,+,=[],16,x8,+="
            rz_strbuf_setf(&op->esil,
                "%s,%s,=[%d],%s,%s,%d,+,=[%d],%" PFMT64d ",%s,%c=",
                REG64(0), MEMBASE64(2), size,
                REG64(1), MEMBASE64(2), size, size,
                abs, MEMBASE64(2), sign);
            // Everything else
        } else {
            rz_strbuf_setf(&op->esil,
                "%s,%s,%" PFMT64d ",%c,=[%d],"
                "%s,%s,%" PFMT64d ",%c,%d,+,=[%d]",
                REG64(0), MEMBASE64(2), abs, sign, size,
                REG64(1), MEMBASE64(2), abs, sign, size, size);
        }
    } break;
    case ARM64_INS_LDP: // ldp x29, x30, [sp], 0x10
    {
        int disp = (int)MEMDISP64(2);
        char sign = disp >= 0 ? '+' : '-';
        ut64 abs = disp >= 0 ? MEMDISP64(2) : -MEMDISP64(2);
        int size = REGSIZE64(0);
        // Pre-index case
        // x2,x8,32,+,=[8],x3,x8,32,+,8,+,=[8]
        if (ISPREINDEX64()) {
            // "ldp x0, x1, [x8, -0x10]!"
            // 16,x8,-=,x8,[8],x0,=,x8,8,+,[8],x1,=
            rz_strbuf_setf(&op->esil,
                "%" PFMT64d ",%s,%c=,"
                "%s,[%d],%s,=,"
                "%d,%s,+,[%d],%s,=",
                abs, MEMBASE64(2), sign,
                MEMBASE64(2), size, REG64(0),
                size, MEMBASE64(2), size, REG64(1));
            // Post-index case
        } else if (ISPOSTINDEX64()) {
            int val = IMM64(3);
            sign = val >= 0 ? '+' : '-';
            abs = val >= 0 ? val : -val;
            // ldp x4, x5, [x8], -0x10
            // x8,[8],x4,=,x8,8,+,[8],x5,=,16,x8,+=
            rz_strbuf_setf(&op->esil,
                "%s,[%d],%s,=,"
                "%s,%d,+,[%d],%s,=,"
                "%" PFMT64d ",%s,%c=",
                MEMBASE64(2), size, REG64(0),
                MEMBASE64(2), size, size, REG64(1),
                abs, MEMBASE64(2), sign);
        } else {
            rz_strbuf_setf(&op->esil,
                "%" PFMT64d ",%s,%c,[%d],%s,=,"
                "%d,%" PFMT64d ",%s,%c,+,[%d],%s,=",
                abs, MEMBASE64(2), sign, size, REG64(0),
                size, abs, MEMBASE64(2), sign, size, REG64(1));
        }
    } break;
    case ARM64_INS_ADRP:
        rz_strbuf_setf(&op->esil, "%" PFMT64d ",%s,=",
            IMM64(1), REG64(0));
        break;
    case ARM64_INS_MOV:
        if (ISREG64(1)) {
            rz_strbuf_setf(&op->esil, "%s,%s,=", REG64(1), REG64(0));
        } else {
            rz_strbuf_setf(&op->esil, "%" PFMT64d ",%s,=", IMM64(1), REG64(0));
        }
        break;
    case ARM64_INS_EXTR:
        // from VEX
        /*
            01 | t0 = GET:I64(x4)
            02 | t1 = GET:I64(x0)
            03 | t4 = Shr64(t1,0x20)
            04 | t5 = Shl64(t0,0x20)
            05 | t3 = Or64(t5,t4)
            06 | PUT(x4) = t3
        */
        rz_strbuf_setf(&op->esil, "%" PFMT64d ",%s,>>,%" PFMT64d ",%s,<<,|,%s,=",
            IMM64(3), REG64(2), IMM64(3), REG64(1), REG64(0));
        break;
    case ARM64_INS_RBIT:
        // this expression reverses the bits. it does. do not scroll right.
        // Derived from VEX
        rz_strbuf_setf(&op->esil, "0xffffffff00000000,0x20,0xffff0000ffff0000,0x10,0xff00ff00ff00ff00,0x8,0xf0f0f0f0f0f0f0f0,0x4,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,<<,&,0x4,0xf0f0f0f0f0f0f0f0,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,&,>>,|,<<,&,0x8,0xff00ff00ff00ff00,0xf0f0f0f0f0f0f0f0,0x4,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,<<,&,0x4,0xf0f0f0f0f0f0f0f0,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,&,>>,|,&,>>,|,<<,&,0x10,0xffff0000ffff0000,0xff00ff00ff00ff00,0x8,0xf0f0f0f0f0f0f0f0,0x4,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,<<,&,0x4,0xf0f0f0f0f0f0f0f0,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,&,>>,|,<<,&,0x8,0xff00ff00ff00ff00,0xf0f0f0f0f0f0f0f0,0x4,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,<<,&,0x4,0xf0f0f0f0f0f0f0f0,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,&,>>,|,&,>>,|,&,>>,|,<<,&,0x20,0xffffffff00000000,0xffff0000ffff0000,0x10,0xff00ff00ff00ff00,0x8,0xf0f0f0f0f0f0f0f0,0x4,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,<<,&,0x4,0xf0f0f0f0f0f0f0f0,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,&,>>,|,<<,&,0x8,0xff00ff00ff00ff00,0xf0f0f0f0f0f0f0f0,0x4,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,<<,&,0x4,0xf0f0f0f0f0f0f0f0,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,&,>>,|,&,>>,|,<<,&,0x10,0xffff0000ffff0000,0xff00ff00ff00ff00,0x8,0xf0f0f0f0f0f0f0f0,0x4,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,<<,&,0x4,0xf0f0f0f0f0f0f0f0,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,&,>>,|,<<,&,0x8,0xff00ff00ff00ff00,0xf0f0f0f0f0f0f0f0,0x4,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,<<,&,0x4,0xf0f0f0f0f0f0f0f0,0xcccccccccccccccc,0x2,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,<<,&,0x2,0xcccccccccccccccc,0xaaaaaaaaaaaaaaaa,0x1,%1$s,<<,&,0x1,0xaaaaaaaaaaaaaaaa,%1$s,&,>>,|,&,>>,|,&,>>,|,&,>>,|,&,>>,|,&,>>,|,%2$s,=",
            REG64(1), REG64(0));
        break;
    case ARM64_INS_MVN:
    case ARM64_INS_MOVN:
        if (ISREG64(1)) {
            rz_strbuf_setf(&op->esil, "%d,%s,-1,^,<<,%s,=", LSHIFT2_64(1), REG64(1), REG64(0));
        } else {
            rz_strbuf_setf(&op->esil, "%d,%" PFMT64d ",<<,-1,^,%s,=", LSHIFT2_64(1), IMM64(1), REG64(0));
        }
        break;
    case ARM64_INS_MOVK: // movk w8, 0x1290
    {
        ut64 shift = LSHIFT2_64(1);
        if (shift < 0) {
            shift = 0;
        } else if (shift > 48) {
            shift = 48;
        }
        ut64 shifted_imm = IMM64(1) << shift;
        ut64 mask = ~(0xffffLL << shift);
 
        rz_strbuf_setf(&op->esil, "0x%" PFMT64x ",%s,&,%" PFMT64u ",|,%s,=",
            mask,
            REG64(0),
            shifted_imm,
            REG64(0));
 
        break;
    }
    case ARM64_INS_MOVZ:
        rz_strbuf_setf(&op->esil, "%" PFMT64u ",%s,=",
            IMM64(1) << LSHIFT2_64(1),
            REG64(0));
        break;
    /* ASR, SXTB, SXTH and SXTW are alias for SBFM */
    case ARM64_INS_ASR: {
        // OPCALL(">>>>");
        const char *r0 = REG64(0);
        const char *r1 = REG64(1);
        const int size = REGSIZE64(0) * 8;
 
        if (ISREG64(2)) {
            if (LSHIFT2_64(2)) {
                SHIFTED_REG64_APPEND(&op->esil, 2);
                rz_strbuf_appendf(&op->esil, ",%d,%%,%s,>>>>,%s,=", size, r1, r0);
            } else {
                const char *r2 = REG64(2);
                rz_strbuf_setf(&op->esil, "%d,%s,%%,%s,>>>>,%s,=", size, r2, r1, r0);
            }
        } else {
            ut64 i2 = IMM64(2);
            rz_strbuf_setf(&op->esil, "%" PFMT64d ",%s,>>>>,%s,=", i2 % (ut64)size, r1, r0);
        }
        break;
    }
    case ARM64_INS_SXTB:
        if (arm64_reg_width(REGID64(0)) == 32) {
            rz_strbuf_setf(&op->esil, "0xffffffff,8,0xff,%s,&,~,&,%s,=",
                REG64(1), REG64(0));
        } else {
            rz_strbuf_setf(&op->esil, "8,0xff,%s,&,~,%s,=",
                REG64(1), REG64(0));
        }
        break;
    case ARM64_INS_SXTH: /* halfword */
        if (arm64_reg_width(REGID64(0)) == 32) {
            rz_strbuf_setf(&op->esil, "0xffffffff,16,0xffff,%s,&,~,&,%s,=",
                REG64(1), REG64(0));
        } else {
            rz_strbuf_setf(&op->esil, "16,0xffff,%s,&,~,%s,=",
                REG64(1), REG64(0));
        }
        break;
    case ARM64_INS_SXTW: /* word */
        rz_strbuf_setf(&op->esil, "32,0xffffffff,%s,&,~,%s,=",
            REG64(1), REG64(0));
        break;
    case ARM64_INS_UXTB:
        rz_strbuf_setf(&op->esil, "%s,0xff,&,%s,=", REG64(1), REG64(0));
        break;
    case ARM64_INS_UMULL:
        rz_strbuf_setf(&op->esil, "%s,%s,*,%s,=", REG64(1), REG64(2), REG64(0));
        break;
    case ARM64_INS_UXTH:
        rz_strbuf_setf(&op->esil, "%s,0xffff,&,%s,=", REG64(1), REG64(0));
        break;
    case ARM64_INS_RET:
        rz_strbuf_setf(&op->esil, "lr,pc,=");
        break;
    case ARM64_INS_ERET:
        rz_strbuf_setf(&op->esil, "lr,pc,=");
        break;
    case ARM64_INS_BFI: // bfi w8, w8, 2, 1
    case ARM64_INS_BFXIL: {
        if (OPCOUNT64() >= 3 && ISIMM64(3) && IMM64(3) > 0) {
            ut64 mask = rz_num_bitmask((ut8)IMM64(3));
            ut64 shift = IMM64(2);
            ut64 notmask = ~(mask << shift);
            // notmask,dst,&,lsb,mask,src,&,<<,|,dst,=
            rz_strbuf_setf(&op->esil, "%" PFMT64u ",%s,&,%" PFMT64u ",%" PFMT64u ",%s,&,<<,|,%s,=",
                notmask, REG64(0), shift, mask, REG64(1), REG64(0));
        }
        break;
    }
    case ARM64_INS_SBFIZ:
        if (IMM64(3) > 0 && IMM64(3) <= 64 - IMM64(2)) {
            rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%" PFMT64d ",%s,%" PFMT64u ",&,~,<<,%s,=",
                IMM64(2), IMM64(3), REG64(1), rz_num_bitmask((ut8)IMM64(3)), REG64(0));
        }
        break;
    case ARM64_INS_UBFIZ:
        if (IMM64(3) > 0 && IMM64(3) <= 64 - IMM64(2)) {
            rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%s,%" PFMT64u ",&,<<,%s,=",
                IMM64(2), REG64(1), rz_num_bitmask((ut8)IMM64(3)), REG64(0));
        }
        break;
    case ARM64_INS_SBFX:
        if (IMM64(3) > 0 && IMM64(3) <= 64 - IMM64(2)) {
            rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%" PFMT64d ",%s,%" PFMT64d ",%" PFMT64u ",<<,&,>>,~,%s,=",
                IMM64(3), IMM64(2), REG64(1), IMM64(2), rz_num_bitmask((ut8)IMM64(3)), REG64(0));
        }
        break;
    case ARM64_INS_UBFX:
        if (IMM64(3) > 0 && IMM64(3) <= 64 - IMM64(2)) {
            rz_strbuf_appendf(&op->esil, "%" PFMT64d ",%s,%" PFMT64d ",%" PFMT64u ",<<,&,>>,%s,=",
                IMM64(2), REG64(1), IMM64(2), rz_num_bitmask((ut8)IMM64(3)), REG64(0));
        }
        break;
    case ARM64_INS_NEG:
#if CS_API_MAJOR > 3
    case ARM64_INS_NEGS:
#endif
        if (LSHIFT2_64(1)) {
            SHIFTED_REG64_APPEND(&op->esil, 1);
        } else {
            rz_strbuf_appendf(&op->esil, "%s", REG64(1));
        }
        rz_strbuf_appendf(&op->esil, ",0,-,%s,=", REG64(0));
        break;
    case ARM64_INS_SVC:
        rz_strbuf_setf(&op->esil, "%" PFMT64u ",$", IMM64(0));
        break;
    }
 
    rz_strbuf_append(&op->esil, postfix);
 
    return 0;
}

References ARM64_INS_ADC, ARM64_INS_ADD, ARM64_INS_ADR, ARM64_INS_ADRP, ARM64_INS_AND, ARM64_INS_ASR, ARM64_INS_B, ARM64_INS_BFI, ARM64_INS_BFXIL, ARM64_INS_BIC, ARM64_INS_BL, ARM64_INS_BLR, ARM64_INS_BR, ARM64_INS_CBNZ, ARM64_INS_CBZ, ARM64_INS_CCMN, ARM64_INS_CCMP, ARM64_INS_CINC, ARM64_INS_CLZ, ARM64_INS_CMN, ARM64_INS_CMP, ARM64_INS_CSEL, ARM64_INS_CSET, ARM64_INS_CSINC, ARM64_INS_EON, ARM64_INS_EOR, ARM64_INS_ERET, ARM64_INS_EXTR, ARM64_INS_FCMP, ARM64_INS_FCSEL, ARM64_INS_FDIV, ARM64_INS_FMADD, ARM64_INS_LDAR, ARM64_INS_LDARB, ARM64_INS_LDARH, ARM64_INS_LDAXR, ARM64_INS_LDAXRB, ARM64_INS_LDAXRH, ARM64_INS_LDP, ARM64_INS_LDR, ARM64_INS_LDRB, ARM64_INS_LDRH, ARM64_INS_LDRSB, ARM64_INS_LDRSH, ARM64_INS_LDRSW, ARM64_INS_LDUR, ARM64_INS_LDURB, ARM64_INS_LDURH, ARM64_INS_LDURSB, ARM64_INS_LDURSH, ARM64_INS_LDURSW, ARM64_INS_LDXR, ARM64_INS_LDXRB, ARM64_INS_LDXRH, ARM64_INS_LSL, ARM64_INS_LSR, ARM64_INS_MADD, ARM64_INS_MNEG, ARM64_INS_MOV, ARM64_INS_MOVK, ARM64_INS_MOVN, ARM64_INS_MOVZ, ARM64_INS_MSUB, ARM64_INS_MUL, ARM64_INS_MVN, ARM64_INS_NEG, ARM64_INS_NEGS, ARM64_INS_NOP, ARM64_INS_ORN, ARM64_INS_ORR, ARM64_INS_RBIT, ARM64_INS_RET, ARM64_INS_REV, ARM64_INS_REV16, ARM64_INS_REV32, ARM64_INS_ROR, ARM64_INS_SBC, ARM64_INS_SBFIZ, ARM64_INS_SBFX, ARM64_INS_SDIV, ARM64_INS_SMADDL, ARM64_INS_SMULL, ARM64_INS_STNP, ARM64_INS_STP, ARM64_INS_STR, ARM64_INS_STRB, ARM64_INS_STRH, ARM64_INS_STUR, ARM64_INS_STURB, ARM64_INS_STURH, ARM64_INS_STXR, ARM64_INS_STXRB, ARM64_INS_STXRH, ARM64_INS_SUB, ARM64_INS_SVC, ARM64_INS_SXTB, ARM64_INS_SXTH, ARM64_INS_SXTW, ARM64_INS_TBNZ, ARM64_INS_TBZ, ARM64_INS_TST, ARM64_INS_UBFIZ, ARM64_INS_UBFX, ARM64_INS_UDIV, ARM64_INS_UMADDL, ARM64_INS_UMULL, ARM64_INS_UXTB, ARM64_INS_UXTH, arm64_reg_width(), bits(), DECODE_SHIFT64, EXT64, HASMEMINDEX64, i2, IMM64, int, ISIMM64, ISMEM64, ISPOSTINDEX64, ISPREINDEX64, ISREG64, LSHIFT2_64, mask, MEMBASE64, MEMDISP64, MEMINDEX64, NULL, OPCALL, OPCALL_NEG, OPCOUNT64, PFMT64d, PFMT64u, PFMT64x, r0, r1, r2, REG64, REGID64, REGSIZE64, rz_arm_cs_esil_prefix_cond(), rz_num_bitmask(), rz_strbuf_append(), rz_strbuf_appendf(), rz_strbuf_init(), rz_strbuf_set(), rz_strbuf_setf(), shift(), SHIFTED_REG64_APPEND, st64, ut64(), and val.

Referenced by analysis_op().

rz_arm_cs_esil_prefix_cond()

RZ_IPI const char* rz_arm_cs_esil_prefix_cond	(	RzAnalysisOp *	op,
		int	cond_type
	)

Definition at line 63 of file arm_esil32.c.

                                                                               {
    const char *close_cond[2];
    close_cond[0] = "\0";
    close_cond[1] = ",}\0";
    int close_type = 0;
    switch (cond_type) {
    case ARM_CC_EQ:
        close_type = 1;
        rz_strbuf_setf(&op->esil, "zf,?{,");
        break;
    case ARM_CC_NE:
        close_type = 1;
        rz_strbuf_setf(&op->esil, "zf,!,?{,");
        break;
    case ARM_CC_HS:
        close_type = 1;
        rz_strbuf_setf(&op->esil, "cf,?{,");
        break;
    case ARM_CC_LO:
        close_type = 1;
        rz_strbuf_setf(&op->esil, "cf,!,?{,");
        break;
    case ARM_CC_MI:
        close_type = 1;
        rz_strbuf_setf(&op->esil, "nf,?{,");
        break;
    case ARM_CC_PL:
        close_type = 1;
        rz_strbuf_setf(&op->esil, "nf,!,?{,");
        break;
    case ARM_CC_VS:
        close_type = 1;
        rz_strbuf_setf(&op->esil, "vf,?{,");
        break;
    case ARM_CC_VC:
        close_type = 1;
        rz_strbuf_setf(&op->esil, "vf,!,?{,");
        break;
    case ARM_CC_HI:
        close_type = 1;
        rz_strbuf_setf(&op->esil, "cf,zf,!,&,?{,");
        break;
    case ARM_CC_LS:
        close_type = 1;
        rz_strbuf_setf(&op->esil, "cf,!,zf,|,?{,");
        break;
    case ARM_CC_GE:
        close_type = 1;
        rz_strbuf_setf(&op->esil, "nf,vf,^,!,?{,");
        break;
    case ARM_CC_LT:
        close_type = 1;
        rz_strbuf_setf(&op->esil, "nf,vf,^,?{,");
        break;
    case ARM_CC_GT:
        // zf == 0 && nf == vf
        close_type = 1;
        rz_strbuf_setf(&op->esil, "zf,!,nf,vf,^,!,&,?{,");
        break;
    case ARM_CC_LE:
        // zf == 1 || nf != vf
        close_type = 1;
        rz_strbuf_setf(&op->esil, "zf,nf,vf,^,|,?{,");
        break;
    case ARM_CC_AL:
        // always executed
        break;
    default:
        break;
    }
    return close_cond[close_type];
}

References ARM_CC_AL, ARM_CC_EQ, ARM_CC_GE, ARM_CC_GT, ARM_CC_HI, ARM_CC_HS, ARM_CC_LE, ARM_CC_LO, ARM_CC_LS, ARM_CC_LT, ARM_CC_MI, ARM_CC_NE, ARM_CC_PL, ARM_CC_VC, ARM_CC_VS, and rz_strbuf_setf().

Referenced by rz_arm_cs_analysis_op_32_esil(), and rz_arm_cs_analysis_op_64_esil().