Rizin
unix-like reverse engineering framework and cli tools
analysis_arm_cs.c
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1 // SPDX-FileCopyrightText: 2013-2021 pancake <pancake@nopcode.org>
2 // SPDX-License-Identifier: LGPL-3.0-only
3 
4 #include <rz_analysis.h>
5 #include <rz_lib.h>
6 #include <ht_uu.h>
7 #include <capstone/capstone.h>
8 #include <capstone/arm.h>
9 #include <rz_util/rz_assert.h>
10 #include "./analysis_arm_hacks.inc"
11 
12 #include "../arch/arm/arm_cs.h"
13 #include "../arch/arm/arm_accessors32.h"
14 #include "../arch/arm/arm_accessors64.h"
15 #include "../../asm/arch/arm/arm_it.h"
16 
17 typedef struct arm_cs_context_t {
18  RzArmITContext it;
19  csh handle;
20  int omode;
21  int obits;
22 } ArmCSContext;
23 
24 static const char *shift_type_name(arm_shifter type) {
25  switch (type) {
26  case ARM_SFT_ASR:
27  return "asr";
28  case ARM_SFT_LSL:
29  return "lsl";
30  case ARM_SFT_LSR:
31  return "lsr";
32  case ARM_SFT_ROR:
33  return "ror";
34  case ARM_SFT_RRX:
35  return "rrx";
36  case ARM_SFT_ASR_REG:
37  return "asr_reg";
38  case ARM_SFT_LSL_REG:
39  return "lsl_reg";
40  case ARM_SFT_LSR_REG:
41  return "lsr_reg";
42  case ARM_SFT_ROR_REG:
43  return "ror_reg";
44  case ARM_SFT_RRX_REG:
45  return "rrx_reg";
46  default:
47  return "";
48  }
49 }
50 
51 static const char *vector_data_type_name(arm_vectordata_type type) {
52  switch (type) {
53  case ARM_VECTORDATA_I8:
54  return "i8";
55  case ARM_VECTORDATA_I16:
56  return "i16";
57  case ARM_VECTORDATA_I32:
58  return "i32";
59  case ARM_VECTORDATA_I64:
60  return "i64";
61  case ARM_VECTORDATA_S8:
62  return "s8";
63  case ARM_VECTORDATA_S16:
64  return "s16";
65  case ARM_VECTORDATA_S32:
66  return "s32";
67  case ARM_VECTORDATA_S64:
68  return "s64";
69  case ARM_VECTORDATA_U8:
70  return "u8";
71  case ARM_VECTORDATA_U16:
72  return "u16";
73  case ARM_VECTORDATA_U32:
74  return "u32";
75  case ARM_VECTORDATA_U64:
76  return "u64";
77  case ARM_VECTORDATA_P8:
78  return "p8";
79  case ARM_VECTORDATA_F32:
80  return "f32";
81  case ARM_VECTORDATA_F64:
82  return "f64";
83  case ARM_VECTORDATA_F16F64:
84  return "f16.f64";
85  case ARM_VECTORDATA_F64F16:
86  return "f64.f16";
87  case ARM_VECTORDATA_F32F16:
88  return "f32.f16";
89  case ARM_VECTORDATA_F16F32:
90  return "f16.f32";
91  case ARM_VECTORDATA_F64F32:
92  return "f64.f32";
93  case ARM_VECTORDATA_F32F64:
94  return "f32.f64";
95  case ARM_VECTORDATA_S32F32:
96  return "s32.f32";
97  case ARM_VECTORDATA_U32F32:
98  return "u32.f32";
99  case ARM_VECTORDATA_F32S32:
100  return "f32.s32";
101  case ARM_VECTORDATA_F32U32:
102  return "f32.u32";
103  case ARM_VECTORDATA_F64S16:
104  return "f64.s16";
105  case ARM_VECTORDATA_F32S16:
106  return "f32.s16";
107  case ARM_VECTORDATA_F64S32:
108  return "f64.s32";
109  case ARM_VECTORDATA_S16F64:
110  return "s16.f64";
111  case ARM_VECTORDATA_S16F32:
112  return "s16.f64";
113  case ARM_VECTORDATA_S32F64:
114  return "s32.f64";
115  case ARM_VECTORDATA_U16F64:
116  return "u16.f64";
117  case ARM_VECTORDATA_U16F32:
118  return "u16.f32";
119  case ARM_VECTORDATA_U32F64:
120  return "u32.f64";
121  case ARM_VECTORDATA_F64U16:
122  return "f64.u16";
123  case ARM_VECTORDATA_F32U16:
124  return "f32.u16";
125  case ARM_VECTORDATA_F64U32:
126  return "f64.u32";
127  default:
128  return "";
129  }
130 }
131 
132 static const char *cc_name(arm_cc cc) {
133  switch (cc) {
134  case ARM_CC_EQ: // Equal Equal
135  return "eq";
136  case ARM_CC_NE: // Not equal Not equal, or unordered
137  return "ne";
138  case ARM_CC_HS: // Carry set >, ==, or unordered
139  return "hs";
140  case ARM_CC_LO: // Carry clear Less than
141  return "lo";
142  case ARM_CC_MI: // Minus, negative Less than
143  return "mi";
144  case ARM_CC_PL: // Plus, positive or zero >, ==, or unordered
145  return "pl";
146  case ARM_CC_VS: // Overflow Unordered
147  return "vs";
148  case ARM_CC_VC: // No overflow Not unordered
149  return "vc";
150  case ARM_CC_HI: // Unsigned higher Greater than, or unordered
151  return "hi";
152  case ARM_CC_LS: // Unsigned lower or same Less than or equal
153  return "ls";
154  case ARM_CC_GE: // Greater than or equal Greater than or equal
155  return "ge";
156  case ARM_CC_LT: // Less than Less than, or unordered
157  return "lt";
158  case ARM_CC_GT: // Greater than Greater than
159  return "gt";
160  case ARM_CC_LE: // Less than or equal <, ==, or unordered
161  return "le";
162  default:
163  return "";
164  }
165 }
166 
167 static void opex(RzStrBuf *buf, csh handle, cs_insn *insn) {
168  int i;
169  PJ *pj = pj_new();
170  if (!pj) {
171  return;
172  }
173  pj_o(pj);
174  pj_ka(pj, "operands");
175  cs_arm *x = &insn->detail->arm;
176  for (i = 0; i < x->op_count; i++) {
177  cs_arm_op *op = x->operands + i;
178  pj_o(pj);
179  switch (op->type) {
180  case ARM_OP_REG:
181  pj_ks(pj, "type", "reg");
182  pj_ks(pj, "value", cs_reg_name(handle, op->reg));
183  break;
184  case ARM_OP_IMM:
185  pj_ks(pj, "type", "imm");
186  pj_ki(pj, "value", op->imm);
187  break;
188  case ARM_OP_MEM:
189  pj_ks(pj, "type", "mem");
190  if (op->mem.base != ARM_REG_INVALID) {
191  pj_ks(pj, "base", cs_reg_name(handle, op->mem.base));
192  }
193  if (op->mem.index != ARM_REG_INVALID) {
194  pj_ks(pj, "index", cs_reg_name(handle, op->mem.index));
195  }
196  pj_ki(pj, "scale", op->mem.scale);
197  pj_ki(pj, "disp", op->mem.disp);
198  break;
199  case ARM_OP_FP:
200  pj_ks(pj, "type", "fp");
201  pj_kd(pj, "value", op->fp);
202  break;
203  case ARM_OP_CIMM:
204  pj_ks(pj, "type", "cimm");
205  pj_ki(pj, "value", op->imm);
206  break;
207  case ARM_OP_PIMM:
208  pj_ks(pj, "type", "pimm");
209  pj_ki(pj, "value", op->imm);
210  break;
211  case ARM_OP_SETEND:
212  pj_ks(pj, "type", "setend");
213  switch (op->setend) {
214  case ARM_SETEND_BE:
215  pj_ks(pj, "value", "be");
216  break;
217  case ARM_SETEND_LE:
218  pj_ks(pj, "value", "le");
219  break;
220  default:
221  pj_ks(pj, "value", "invalid");
222  break;
223  }
224  break;
225  case ARM_OP_SYSREG: {
226  pj_ks(pj, "type", "sysreg");
227  const char *reg = cs_reg_name(handle, op->reg);
228  if (reg) {
229  pj_ks(pj, "value", reg);
230  }
231  break;
232  }
233  default:
234  pj_ks(pj, "type", "invalid");
235  break;
236  }
237  if (op->shift.type != ARM_SFT_INVALID) {
238  pj_ko(pj, "shift");
239  switch (op->shift.type) {
240  case ARM_SFT_ASR:
241  case ARM_SFT_LSL:
242  case ARM_SFT_LSR:
243  case ARM_SFT_ROR:
244  case ARM_SFT_RRX:
245  pj_ks(pj, "type", shift_type_name(op->shift.type));
246  pj_kn(pj, "value", (ut64)op->shift.value);
247  break;
248  case ARM_SFT_ASR_REG:
249  case ARM_SFT_LSL_REG:
250  case ARM_SFT_LSR_REG:
251  case ARM_SFT_ROR_REG:
252  case ARM_SFT_RRX_REG:
253  pj_ks(pj, "type", shift_type_name(op->shift.type));
254  pj_ks(pj, "value", cs_reg_name(handle, op->shift.value));
255  break;
256  default:
257  break;
258  }
259  pj_end(pj); /* o shift */
260  }
261  if (op->vector_index != -1) {
262  pj_ki(pj, "vector_index", op->vector_index);
263  }
264  if (op->subtracted) {
265  pj_kb(pj, "subtracted", true);
266  }
267  pj_end(pj); /* o operand */
268  }
269  pj_end(pj); /* a operands */
270  if (x->usermode) {
271  pj_kb(pj, "usermode", true);
272  }
273  if (x->update_flags) {
274  pj_kb(pj, "update_flags", true);
275  }
276  if (x->writeback) {
277  pj_kb(pj, "writeback", true);
278  }
279  if (x->vector_size) {
280  pj_ki(pj, "vector_size", x->vector_size);
281  }
282  if (x->vector_data != ARM_VECTORDATA_INVALID) {
283  pj_ks(pj, "vector_data", vector_data_type_name(x->vector_data));
284  }
285  if (x->cps_mode != ARM_CPSMODE_INVALID) {
286  pj_ki(pj, "cps_mode", x->cps_mode);
287  }
288  if (x->cps_flag != ARM_CPSFLAG_INVALID) {
289  pj_ki(pj, "cps_flag", x->cps_flag);
290  }
291  if (x->cc != ARM_CC_INVALID && x->cc != ARM_CC_AL) {
292  pj_ks(pj, "cc", cc_name(x->cc));
293  }
294  if (x->mem_barrier != ARM_MB_INVALID) {
295  pj_ki(pj, "mem_barrier", x->mem_barrier - 1);
296  }
297  pj_end(pj);
298 
299  rz_strbuf_init(buf);
300  rz_strbuf_append(buf, pj_string(pj));
301  pj_free(pj);
302 }
303 
304 static const char *cc_name64(arm64_cc cc) {
305  switch (cc) {
306  case ARM64_CC_EQ: // Equal
307  return "eq";
308  case ARM64_CC_NE: // Not equal: Not equal, or unordered
309  return "ne";
310  case ARM64_CC_HS: // Unsigned higher or same: >, ==, or unordered
311  return "hs";
312  case ARM64_CC_LO: // Unsigned lower or same: Less than
313  return "lo";
314  case ARM64_CC_MI: // Minus, negative: Less than
315  return "mi";
316  case ARM64_CC_PL: // Plus, positive or zero: >, ==, or unordered
317  return "pl";
318  case ARM64_CC_VS: // Overflow: Unordered
319  return "vs";
320  case ARM64_CC_VC: // No overflow: Ordered
321  return "vc";
322  case ARM64_CC_HI: // Unsigned higher: Greater than, or unordered
323  return "hi";
324  case ARM64_CC_LS: // Unsigned lower or same: Less than or equal
325  return "ls";
326  case ARM64_CC_GE: // Greater than or equal: Greater than or equal
327  return "ge";
328  case ARM64_CC_LT: // Less than: Less than, or unordered
329  return "lt";
330  case ARM64_CC_GT: // Signed greater than: Greater than
331  return "gt";
332  case ARM64_CC_LE: // Signed less than or equal: <, ==, or unordered
333  return "le";
334  default:
335  return "";
336  }
337 }
338 
339 static const char *extender_name(arm64_extender extender) {
340  switch (extender) {
341  case ARM64_EXT_UXTB:
342  return "uxtb";
343  case ARM64_EXT_UXTH:
344  return "uxth";
345  case ARM64_EXT_UXTW:
346  return "uxtw";
347  case ARM64_EXT_UXTX:
348  return "uxtx";
349  case ARM64_EXT_SXTB:
350  return "sxtb";
351  case ARM64_EXT_SXTH:
352  return "sxth";
353  case ARM64_EXT_SXTW:
354  return "sxtw";
355  case ARM64_EXT_SXTX:
356  return "sxtx";
357  default:
358  return "";
359  }
360 }
361 
362 static const char *vas_name(arm64_vas vas) {
363  switch (vas) {
364  case ARM64_VAS_8B:
365  return "8b";
366  case ARM64_VAS_16B:
367  return "16b";
368  case ARM64_VAS_4H:
369  return "4h";
370  case ARM64_VAS_8H:
371  return "8h";
372  case ARM64_VAS_2S:
373  return "2s";
374  case ARM64_VAS_4S:
375  return "4s";
376  case ARM64_VAS_2D:
377  return "2d";
378  case ARM64_VAS_1D:
379  return "1d";
380  case ARM64_VAS_1Q:
381  return "1q";
382 #if CS_API_MAJOR > 4
383  case ARM64_VAS_1B:
384  return "8b";
385  case ARM64_VAS_4B:
386  return "8b";
387  case ARM64_VAS_2H:
388  return "2h";
389  case ARM64_VAS_1H:
390  return "1h";
391  case ARM64_VAS_1S:
392  return "1s";
393 #endif
394  default:
395  return "";
396  }
397 }
398 
399 #if CS_API_MAJOR == 4
400 static const char *vess_name(arm64_vess vess) {
401  switch (vess) {
402  case ARM64_VESS_B:
403  return "b";
404  case ARM64_VESS_H:
405  return "h";
406  case ARM64_VESS_S:
407  return "s";
408  case ARM64_VESS_D:
409  return "d";
410  default:
411  return "";
412  }
413 }
414 #endif
415 
416 static void opex64(RzStrBuf *buf, csh handle, cs_insn *insn) {
417  int i;
418  PJ *pj = pj_new();
419  if (!pj) {
420  return;
421  }
422  pj_o(pj);
423  pj_ka(pj, "operands");
424  cs_arm64 *x = &insn->detail->arm64;
425  for (i = 0; i < x->op_count; i++) {
426  cs_arm64_op *op = x->operands + i;
427  pj_o(pj);
428  switch (op->type) {
429  case ARM64_OP_REG:
430  pj_ks(pj, "type", "reg");
431  pj_ks(pj, "value", cs_reg_name(handle, op->reg));
432  break;
433  case ARM64_OP_REG_MRS:
434  pj_ks(pj, "type", "reg_mrs");
435  // TODO value
436  break;
437  case ARM64_OP_REG_MSR:
438  pj_ks(pj, "type", "reg_msr");
439  // TODO value
440  break;
441  case ARM64_OP_IMM:
442  pj_ks(pj, "type", "imm");
443  pj_kN(pj, "value", op->imm);
444  break;
445  case ARM64_OP_MEM:
446  pj_ks(pj, "type", "mem");
447  if (op->mem.base != ARM64_REG_INVALID) {
448  pj_ks(pj, "base", cs_reg_name(handle, op->mem.base));
449  }
450  if (op->mem.index != ARM64_REG_INVALID) {
451  pj_ks(pj, "index", cs_reg_name(handle, op->mem.index));
452  }
453  pj_ki(pj, "disp", op->mem.disp);
454  break;
455  case ARM64_OP_FP:
456  pj_ks(pj, "type", "fp");
457  pj_kd(pj, "value", op->fp);
458  break;
459  case ARM64_OP_CIMM:
460  pj_ks(pj, "type", "cimm");
461  pj_kN(pj, "value", op->imm);
462  break;
463  case ARM64_OP_PSTATE:
464  pj_ks(pj, "type", "pstate");
465  switch (op->pstate) {
466  case ARM64_PSTATE_SPSEL:
467  pj_ks(pj, "value", "spsel");
468  break;
469  case ARM64_PSTATE_DAIFSET:
470  pj_ks(pj, "value", "daifset");
471  break;
472  case ARM64_PSTATE_DAIFCLR:
473  pj_ks(pj, "value", "daifclr");
474  break;
475  default:
476  pj_ki(pj, "value", op->pstate);
477  }
478  break;
479  case ARM64_OP_SYS:
480  pj_ks(pj, "type", "sys");
481  pj_kn(pj, "value", (ut64)op->sys);
482  break;
483  case ARM64_OP_PREFETCH:
484  pj_ks(pj, "type", "prefetch");
485  pj_ki(pj, "value", op->prefetch - 1);
486  break;
487  case ARM64_OP_BARRIER:
488  pj_ks(pj, "type", "prefetch");
489  pj_ki(pj, "value", op->barrier - 1);
490  break;
491  default:
492  pj_ks(pj, "type", "invalid");
493  break;
494  }
495  if (op->shift.type != ARM64_SFT_INVALID) {
496  pj_ko(pj, "shift");
497  switch (op->shift.type) {
498  case ARM64_SFT_LSL:
499  pj_ks(pj, "type", "lsl");
500  break;
501  case ARM64_SFT_MSL:
502  pj_ks(pj, "type", "msl");
503  break;
504  case ARM64_SFT_LSR:
505  pj_ks(pj, "type", "lsr");
506  break;
507  case ARM64_SFT_ASR:
508  pj_ks(pj, "type", "asr");
509  break;
510  case ARM64_SFT_ROR:
511  pj_ks(pj, "type", "ror");
512  break;
513  default:
514  break;
515  }
516  pj_kn(pj, "value", (ut64)op->shift.value);
517  pj_end(pj);
518  }
519  if (op->ext != ARM64_EXT_INVALID) {
520  pj_ks(pj, "ext", extender_name(op->ext));
521  }
522  if (op->vector_index != -1) {
523  pj_ki(pj, "vector_index", op->vector_index);
524  }
525  if (op->vas != ARM64_VAS_INVALID) {
526  pj_ks(pj, "vas", vas_name(op->vas));
527  }
528 #if CS_API_MAJOR == 4
529  if (op->vess != ARM64_VESS_INVALID) {
530  pj_ks(pj, "vess", vess_name(op->vess));
531  }
532 #endif
533  pj_end(pj);
534  }
535  pj_end(pj);
536  if (x->update_flags) {
537  pj_kb(pj, "update_flags", true);
538  }
539  if (x->writeback) {
540  pj_kb(pj, "writeback", true);
541  }
542  if (x->cc != ARM64_CC_INVALID && x->cc != ARM64_CC_AL && x->cc != ARM64_CC_NV) {
543  pj_ks(pj, "cc", cc_name64(x->cc));
544  }
545  pj_end(pj);
546 
547  rz_strbuf_init(buf);
548  rz_strbuf_append(buf, pj_string(pj));
549  pj_free(pj);
550 }
551 
552 static int cond_cs2r2(int cc) {
553  if (cc == ARM_CC_AL || cc < 0) {
554  cc = RZ_TYPE_COND_AL;
555  } else {
556  switch (cc) {
557  case ARM_CC_EQ: cc = RZ_TYPE_COND_EQ; break;
558  case ARM_CC_NE: cc = RZ_TYPE_COND_NE; break;
559  case ARM_CC_HS: cc = RZ_TYPE_COND_HS; break;
560  case ARM_CC_LO: cc = RZ_TYPE_COND_LO; break;
561  case ARM_CC_MI: cc = RZ_TYPE_COND_MI; break;
562  case ARM_CC_PL: cc = RZ_TYPE_COND_PL; break;
563  case ARM_CC_VS: cc = RZ_TYPE_COND_VS; break;
564  case ARM_CC_VC: cc = RZ_TYPE_COND_VC; break;
565  case ARM_CC_HI: cc = RZ_TYPE_COND_HI; break;
566  case ARM_CC_LS: cc = RZ_TYPE_COND_LS; break;
567  case ARM_CC_GE: cc = RZ_TYPE_COND_GE; break;
568  case ARM_CC_LT: cc = RZ_TYPE_COND_LT; break;
569  case ARM_CC_GT: cc = RZ_TYPE_COND_GT; break;
570  case ARM_CC_LE: cc = RZ_TYPE_COND_LE; break;
571  }
572  }
573  return cc;
574 }
575 
576 static void anop64(ArmCSContext *ctx, RzAnalysisOp *op, cs_insn *insn) {
577  csh handle = ctx->handle;
578  ut64 addr = op->addr;
579 
580  /* grab family */
581  if (cs_insn_group(handle, insn, ARM64_GRP_CRYPTO)) {
582  op->family = RZ_ANALYSIS_OP_FAMILY_CRYPTO;
583  } else if (cs_insn_group(handle, insn, ARM64_GRP_CRC)) {
584  op->family = RZ_ANALYSIS_OP_FAMILY_CRYPTO;
585 #if CS_API_MAJOR >= 4
586  } else if (cs_insn_group(handle, insn, ARM64_GRP_PRIVILEGE)) {
587  op->family = RZ_ANALYSIS_OP_FAMILY_PRIV;
588 #endif
589  } else if (cs_insn_group(handle, insn, ARM64_GRP_NEON)) {
590  op->family = RZ_ANALYSIS_OP_FAMILY_MMX;
591  } else if (cs_insn_group(handle, insn, ARM64_GRP_FPARMV8)) {
592  op->family = RZ_ANALYSIS_OP_FAMILY_FPU;
593  } else {
594  op->family = RZ_ANALYSIS_OP_FAMILY_CPU;
595  }
596 
597  op->cond = cond_cs2r2(insn->detail->arm64.cc);
598  if (op->cond == RZ_TYPE_COND_NV) {
599  op->type = RZ_ANALYSIS_OP_TYPE_NOP;
600  return;
601  }
602 
603  switch (insn->detail->arm64.cc) {
604  case ARM64_CC_GE:
605  case ARM64_CC_GT:
606  case ARM64_CC_LE:
607  case ARM64_CC_LT:
608  op->sign = true;
609  break;
610  default:
611  break;
612  }
613 
614  switch (insn->id) {
615 #if CS_API_MAJOR > 4
616  case ARM64_INS_PACDA:
617  case ARM64_INS_PACDB:
618  case ARM64_INS_PACDZA:
619  case ARM64_INS_PACDZB:
620  case ARM64_INS_PACGA:
621  case ARM64_INS_PACIA:
622  case ARM64_INS_PACIA1716:
623  case ARM64_INS_PACIASP:
624  case ARM64_INS_PACIAZ:
625  case ARM64_INS_PACIB:
626  case ARM64_INS_PACIB1716:
627  case ARM64_INS_PACIBSP:
628  case ARM64_INS_PACIBZ:
629  case ARM64_INS_PACIZA:
630  case ARM64_INS_PACIZB:
631  case ARM64_INS_AUTDA:
632  case ARM64_INS_AUTDB:
633  case ARM64_INS_AUTDZA:
634  case ARM64_INS_AUTDZB:
635  case ARM64_INS_AUTIA:
636  case ARM64_INS_AUTIA1716:
637  case ARM64_INS_AUTIASP:
638  case ARM64_INS_AUTIAZ:
639  case ARM64_INS_AUTIB:
640  case ARM64_INS_AUTIB1716:
641  case ARM64_INS_AUTIBSP:
642  case ARM64_INS_AUTIBZ:
643  case ARM64_INS_AUTIZA:
644  case ARM64_INS_AUTIZB:
645  case ARM64_INS_XPACD:
646  case ARM64_INS_XPACI:
647  case ARM64_INS_XPACLRI:
648  op->type = RZ_ANALYSIS_OP_TYPE_CMP;
649  op->family = RZ_ANALYSIS_OP_FAMILY_SECURITY;
650  break;
651 #endif
652  case ARM64_INS_SVC:
653  op->type = RZ_ANALYSIS_OP_TYPE_SWI;
654  op->val = IMM64(0);
655  break;
656  case ARM64_INS_ADRP:
657  case ARM64_INS_ADR:
658  op->type = RZ_ANALYSIS_OP_TYPE_LEA;
659  op->ptr = IMM64(1);
660  break;
661  case ARM64_INS_NOP:
662  op->type = RZ_ANALYSIS_OP_TYPE_NOP;
663  op->cycles = 1;
664  break;
665  case ARM64_INS_SUB:
666  if (ISREG64(0) && REGID64(0) == ARM64_REG_SP) {
667  op->stackop = RZ_ANALYSIS_STACK_INC;
668  if (ISIMM64(1)) {
669  // sub sp, 0x54
670  op->stackptr = IMM(1);
671  } else if (ISIMM64(2) && ISREG64(1) && REGID64(1) == ARM64_REG_SP) {
672  // sub sp, sp, 0x10
673  op->stackptr = IMM64(2);
674  }
675  op->val = op->stackptr;
676  } else {
677  op->stackop = RZ_ANALYSIS_STACK_RESET;
678  op->stackptr = 0;
679  }
680  op->cycles = 1;
681  /* fallthru */
682  case ARM64_INS_MSUB:
683  op->type = RZ_ANALYSIS_OP_TYPE_SUB;
684  break;
685  case ARM64_INS_FDIV:
686  case ARM64_INS_SDIV:
687  case ARM64_INS_UDIV:
688  op->cycles = 4;
689  op->type = RZ_ANALYSIS_OP_TYPE_DIV;
690  break;
691  case ARM64_INS_MUL:
692  case ARM64_INS_SMULL:
693  case ARM64_INS_FMUL:
694  case ARM64_INS_UMULL:
695  /* TODO: if next instruction is also a MUL, cycles are /=2 */
696  /* also known as Register Indexing Addressing */
697  op->cycles = 4;
698  op->type = RZ_ANALYSIS_OP_TYPE_MUL;
699  break;
700  case ARM64_INS_ADD:
701  if (ISREG64(0) && REGID64(0) == ARM64_REG_SP) {
702  op->stackop = RZ_ANALYSIS_STACK_INC;
703  if (ISIMM64(1)) {
704  // add sp, 0x54
705  op->stackptr = -IMM(1);
706  } else if (ISIMM64(2) && ISREG64(1) && REGID64(1) == ARM64_REG_SP) {
707  // add sp, sp, 0x10
708  op->stackptr = -IMM64(2);
709  }
710  op->val = op->stackptr;
711  } else {
712  op->stackop = RZ_ANALYSIS_STACK_RESET;
713  op->stackptr = 0;
714  if (ISIMM64(2)) {
715  op->val = IMM64(2);
716  }
717  }
718  op->cycles = 1;
719  /* fallthru */
720  case ARM64_INS_ADC:
721  // case ARM64_INS_ADCS:
722  case ARM64_INS_UMADDL:
723  case ARM64_INS_SMADDL:
724  case ARM64_INS_FMADD:
725  case ARM64_INS_MADD:
726  op->type = RZ_ANALYSIS_OP_TYPE_ADD;
727  break;
728  case ARM64_INS_CSEL:
729  case ARM64_INS_FCSEL:
730  case ARM64_INS_CSET:
731  case ARM64_INS_CINC:
732  op->type = RZ_ANALYSIS_OP_TYPE_CMOV;
733  break;
734  case ARM64_INS_MOV:
735  if (REGID64(0) == ARM64_REG_SP) {
736  op->stackop = RZ_ANALYSIS_STACK_RESET;
737  op->stackptr = 0;
738  }
739  if (ISIMM64(1)) {
740  op->val = IMM64(1);
741  }
742  op->cycles = 1;
743  /* fallthru */
744  case ARM64_INS_MOVI:
745  case ARM64_INS_MOVK:
746  case ARM64_INS_MOVN:
747  case ARM64_INS_SMOV:
748  case ARM64_INS_UMOV:
749  case ARM64_INS_FMOV:
750  case ARM64_INS_SBFX:
751  case ARM64_INS_UBFX:
752  case ARM64_INS_UBFM:
753  case ARM64_INS_SBFIZ:
754  case ARM64_INS_UBFIZ:
755  case ARM64_INS_BIC:
756  case ARM64_INS_BFI:
757  case ARM64_INS_BFXIL:
758  op->type = RZ_ANALYSIS_OP_TYPE_MOV;
759  break;
760  case ARM64_INS_MRS:
761  case ARM64_INS_MSR:
762  op->type = RZ_ANALYSIS_OP_TYPE_MOV;
763  op->family = RZ_ANALYSIS_OP_FAMILY_PRIV;
764  break;
765  case ARM64_INS_MOVZ:
766  op->type = RZ_ANALYSIS_OP_TYPE_MOV;
767  op->ptr = 0LL;
768  op->ptrsize = 8;
769  op->val = IMM64(1);
770  break;
771  case ARM64_INS_UXTB:
772  case ARM64_INS_SXTB:
773  op->type = RZ_ANALYSIS_OP_TYPE_CAST;
774  op->ptr = 0LL;
775  op->ptrsize = 1;
776  break;
777  case ARM64_INS_UXTH:
778  case ARM64_INS_SXTH:
779  op->type = RZ_ANALYSIS_OP_TYPE_MOV;
780  op->ptr = 0LL;
781  op->ptrsize = 2;
782  break;
783  case ARM64_INS_UXTW:
784  case ARM64_INS_SXTW:
785  op->type = RZ_ANALYSIS_OP_TYPE_MOV;
786  op->ptr = 0LL;
787  op->ptrsize = 4;
788  break;
789  case ARM64_INS_BRK:
790  case ARM64_INS_HLT:
791  op->type = RZ_ANALYSIS_OP_TYPE_TRAP;
792  // hlt stops the process, not skips some cycles like in x86
793  break;
794  case ARM64_INS_DMB:
795  case ARM64_INS_DSB:
796  case ARM64_INS_ISB:
797  op->family = RZ_ANALYSIS_OP_FAMILY_THREAD;
798  // intentional fallthrough
799  case ARM64_INS_IC: // instruction cache invalidate
800  case ARM64_INS_DC: // data cache invalidate
801  op->type = RZ_ANALYSIS_OP_TYPE_SYNC; // or cache
802  break;
803  // XXX unimplemented instructions
804  case ARM64_INS_DUP:
805  case ARM64_INS_XTN:
806  case ARM64_INS_XTN2:
807  case ARM64_INS_REV64:
808  case ARM64_INS_EXT:
809  case ARM64_INS_INS:
810  op->type = RZ_ANALYSIS_OP_TYPE_MOV;
811  break;
812  case ARM64_INS_LSL:
813  op->cycles = 1;
814  /* fallthru */
815  case ARM64_INS_SHL:
816  case ARM64_INS_USHLL:
817  op->type = RZ_ANALYSIS_OP_TYPE_SHL;
818  break;
819  case ARM64_INS_LSR:
820  op->cycles = 1;
821  op->type = RZ_ANALYSIS_OP_TYPE_SHR;
822  break;
823  case ARM64_INS_ASR:
824  op->cycles = 1;
825  op->type = RZ_ANALYSIS_OP_TYPE_SAR;
826  break;
827  case ARM64_INS_NEG:
828 #if CS_API_MAJOR > 3
829  case ARM64_INS_NEGS:
830 #endif
831  op->type = RZ_ANALYSIS_OP_TYPE_NOT;
832  break;
833  case ARM64_INS_FCMP:
834  case ARM64_INS_CCMP:
835  case ARM64_INS_CCMN:
836  case ARM64_INS_CMP:
837  case ARM64_INS_CMN:
838  case ARM64_INS_TST:
839  op->type = RZ_ANALYSIS_OP_TYPE_CMP;
840  break;
841  case ARM64_INS_ROR:
842  op->cycles = 1;
843  op->type = RZ_ANALYSIS_OP_TYPE_ROR;
844  break;
845  case ARM64_INS_AND:
846  op->type = RZ_ANALYSIS_OP_TYPE_AND;
847  break;
848  case ARM64_INS_ORR:
849  case ARM64_INS_ORN:
850  op->type = RZ_ANALYSIS_OP_TYPE_OR;
851  if (ISIMM64(2)) {
852  op->val = IMM64(2);
853  }
854  break;
855  case ARM64_INS_EOR:
856  case ARM64_INS_EON:
857  op->type = RZ_ANALYSIS_OP_TYPE_XOR;
858  break;
859  case ARM64_INS_STRB:
860  case ARM64_INS_STURB:
861  case ARM64_INS_STUR:
862  case ARM64_INS_STR:
863  case ARM64_INS_STP:
864  case ARM64_INS_STNP:
865  case ARM64_INS_STXR:
866  case ARM64_INS_STXRH:
867  case ARM64_INS_STLXR:
868  case ARM64_INS_STLXRH:
869  case ARM64_INS_STXRB:
870  op->type = RZ_ANALYSIS_OP_TYPE_STORE;
871  if (ISPREINDEX64() && REGBASE64(2) == ARM64_REG_SP) {
872  op->stackop = RZ_ANALYSIS_STACK_INC;
873  op->stackptr = -MEMDISP64(2);
874  } else if (ISPOSTINDEX64() && REGID64(2) == ARM64_REG_SP) {
875  op->stackop = RZ_ANALYSIS_STACK_INC;
876  op->stackptr = -IMM64(3);
877  } else if (ISPREINDEX64() && REGBASE64(1) == ARM64_REG_SP) {
878  op->stackop = RZ_ANALYSIS_STACK_INC;
879  op->stackptr = -MEMDISP64(1);
880  } else if (ISPOSTINDEX64() && REGID64(1) == ARM64_REG_SP) {
881  op->stackop = RZ_ANALYSIS_STACK_INC;
882  op->stackptr = -IMM64(2);
883  }
884  break;
885  case ARM64_INS_LDUR:
886  case ARM64_INS_LDURB:
887  case ARM64_INS_LDRSW:
888  case ARM64_INS_LDRSB:
889  case ARM64_INS_LDRSH:
890  case ARM64_INS_LDR:
891  case ARM64_INS_LDURSW:
892  case ARM64_INS_LDP:
893  case ARM64_INS_LDNP:
894  case ARM64_INS_LDPSW:
895  case ARM64_INS_LDRH:
896  case ARM64_INS_LDRB:
897  if (ISPREINDEX64() && REGBASE64(2) == ARM64_REG_SP) {
898  op->stackop = RZ_ANALYSIS_STACK_INC;
899  op->stackptr = -MEMDISP64(2);
900  } else if (ISPOSTINDEX64() && REGID64(2) == ARM64_REG_SP) {
901  op->stackop = RZ_ANALYSIS_STACK_INC;
902  op->stackptr = -IMM64(3);
903  } else if (ISPREINDEX64() && REGBASE64(1) == ARM64_REG_SP) {
904  op->stackop = RZ_ANALYSIS_STACK_INC;
905  op->stackptr = -MEMDISP64(1);
906  } else if (ISPOSTINDEX64() && REGID64(1) == ARM64_REG_SP) {
907  op->stackop = RZ_ANALYSIS_STACK_INC;
908  op->stackptr = -IMM64(2);
909  }
910  if (REGID(0) == ARM_REG_PC) {
911  op->type = RZ_ANALYSIS_OP_TYPE_UJMP;
912  if (insn->detail->arm.cc != ARM_CC_AL) {
913  // op->type = RZ_ANALYSIS_OP_TYPE_MCJMP;
914  op->type = RZ_ANALYSIS_OP_TYPE_UCJMP;
915  }
916  } else {
917  op->type = RZ_ANALYSIS_OP_TYPE_LOAD;
918  }
919  switch (insn->id) {
920  case ARM64_INS_LDPSW:
921  case ARM64_INS_LDRSW:
922  case ARM64_INS_LDRSH:
923  case ARM64_INS_LDRSB:
924  op->sign = true;
925  break;
926  }
927  if (REGBASE64(1) == ARM64_REG_X29) {
928  op->stackop = RZ_ANALYSIS_STACK_GET;
929  op->stackptr = 0;
930  op->ptr = MEMDISP64(1);
931  } else {
932  if (ISIMM64(1)) {
933  op->type = RZ_ANALYSIS_OP_TYPE_LEA;
934  op->ptr = IMM64(1);
935  op->refptr = 8;
936  } else {
937  int d = (int)MEMDISP64(1);
938  op->ptr = (d < 0) ? -d : d;
939  op->refptr = 4;
940  }
941  }
942  break;
943 #if CS_API_MAJOR > 4
944  case ARM64_INS_BLRAA:
945  case ARM64_INS_BLRAAZ:
946  case ARM64_INS_BLRAB:
947  case ARM64_INS_BLRABZ:
948  op->family = RZ_ANALYSIS_OP_FAMILY_SECURITY;
949  op->type = RZ_ANALYSIS_OP_TYPE_RCALL;
950  break;
951  case ARM64_INS_BRAA:
952  case ARM64_INS_BRAAZ:
953  case ARM64_INS_BRAB:
954  case ARM64_INS_BRABZ:
955  op->family = RZ_ANALYSIS_OP_FAMILY_SECURITY;
956  op->type = RZ_ANALYSIS_OP_TYPE_RJMP;
957  break;
958  case ARM64_INS_LDRAA:
959  case ARM64_INS_LDRAB:
960  op->family = RZ_ANALYSIS_OP_FAMILY_SECURITY;
961  op->type = RZ_ANALYSIS_OP_TYPE_LOAD;
962  break;
963  case ARM64_INS_RETAA:
964  case ARM64_INS_RETAB:
965  case ARM64_INS_ERETAA:
966  case ARM64_INS_ERETAB:
967  op->family = RZ_ANALYSIS_OP_FAMILY_SECURITY;
968  op->type = RZ_ANALYSIS_OP_TYPE_RET;
969  break;
970 #endif
971  case ARM64_INS_ERET:
972  op->family = RZ_ANALYSIS_OP_FAMILY_PRIV;
973  op->type = RZ_ANALYSIS_OP_TYPE_RET;
974  break;
975  case ARM64_INS_RET:
976  op->type = RZ_ANALYSIS_OP_TYPE_RET;
977  break;
978  case ARM64_INS_BL: // bl 0x89480
979  op->type = RZ_ANALYSIS_OP_TYPE_CALL;
980  op->jump = IMM64(0);
981  op->fail = addr + 4;
982  break;
983  case ARM64_INS_BLR: // blr x0
984  op->type = RZ_ANALYSIS_OP_TYPE_RCALL;
985  op->reg = cs_reg_name(handle, REGID64(0));
986  op->fail = addr + 4;
987  // op->jump = IMM64(0);
988  break;
989  case ARM64_INS_CBZ:
990  case ARM64_INS_CBNZ:
991  op->type = RZ_ANALYSIS_OP_TYPE_CJMP;
992  op->jump = IMM64(1);
993  op->fail = addr + op->size;
994  break;
995  case ARM64_INS_TBZ:
996  case ARM64_INS_TBNZ:
997  op->type = RZ_ANALYSIS_OP_TYPE_CJMP;
998  op->jump = IMM64(2);
999  op->fail = addr + op->size;
1000  break;
1001  case ARM64_INS_BR:
1002  op->type = RZ_ANALYSIS_OP_TYPE_RJMP;
1003  op->reg = cs_reg_name(handle, REGID64(0));
1004  op->eob = true;
1005  break;
1006  case ARM64_INS_B:
1007  // BX LR == RET
1008  if (insn->detail->arm64.operands[0].reg == ARM64_REG_LR) {
1009  op->type = RZ_ANALYSIS_OP_TYPE_RET;
1010  } else if (insn->detail->arm64.cc) {
1011  op->type = RZ_ANALYSIS_OP_TYPE_CJMP;
1012  op->jump = IMM64(0);
1013  op->fail = addr + op->size;
1014  } else {
1015  op->type = RZ_ANALYSIS_OP_TYPE_JMP;
1016  op->jump = IMM64(0);
1017  }
1018  break;
1019  default:
1020  RZ_LOG_DEBUG("ARM64 analysis: Op type %d at 0x%" PFMT64x " not handled\n", insn->id, op->addr);
1021  break;
1022  }
1023 }
1024 
1025 static void anop32(RzAnalysis *a, csh handle, RzAnalysisOp *op, cs_insn *insn, bool thumb, const ut8 *buf, int len) {
1026  ArmCSContext *ctx = (ArmCSContext *)a->plugin_data;
1027  const ut64 addr = op->addr;
1028  const int pcdelta = thumb ? 4 : 8;
1029  int i;
1030 
1031  op->cond = cond_cs2r2(insn->detail->arm.cc);
1032  if (op->cond == RZ_TYPE_COND_NV) {
1033  op->type = RZ_ANALYSIS_OP_TYPE_NOP;
1034  return;
1035  }
1036  op->cycles = 1;
1037  /* grab family */
1038  if (cs_insn_group(handle, insn, ARM_GRP_CRYPTO)) {
1039  op->family = RZ_ANALYSIS_OP_FAMILY_CRYPTO;
1040  } else if (cs_insn_group(handle, insn, ARM_GRP_CRC)) {
1041  op->family = RZ_ANALYSIS_OP_FAMILY_CRYPTO;
1042 #if CS_API_MAJOR >= 4
1043  } else if (cs_insn_group(handle, insn, ARM_GRP_PRIVILEGE)) {
1044  op->family = RZ_ANALYSIS_OP_FAMILY_PRIV;
1045  } else if (cs_insn_group(handle, insn, ARM_GRP_VIRTUALIZATION)) {
1046  op->family = RZ_ANALYSIS_OP_FAMILY_VIRT;
1047 #endif
1048  } else if (cs_insn_group(handle, insn, ARM_GRP_NEON)) {
1049  op->family = RZ_ANALYSIS_OP_FAMILY_MMX;
1050  } else if (cs_insn_group(handle, insn, ARM_GRP_FPARMV8)) {
1051  op->family = RZ_ANALYSIS_OP_FAMILY_FPU;
1052  } else if (cs_insn_group(handle, insn, ARM_GRP_THUMB2DSP)) {
1053  op->family = RZ_ANALYSIS_OP_FAMILY_MMX;
1054  } else {
1055  op->family = RZ_ANALYSIS_OP_FAMILY_CPU;
1056  }
1057 
1058  if (insn->id != ARM_INS_IT) {
1059  rz_arm_it_update_nonblock(&ctx->it, insn);
1060  }
1061 
1062  switch (insn->id) {
1063 #if 0
1064 
1065 If PC is specified for Rn, the value used is the address of the instruction plus 4.
1066 
1067 These instructions cause a PC-relative forward branch using a table of single byte offsets (TBB) or halfword offsets (TBH). Rn provides a pointer to the table, and Rm supplies an index into the table. The branch length is twice the value of the byte (TBB) or the halfword (TBH) returned from the table. The target of the branch table must be in the same execution state.
1068 
1069 jmp $$ + 4 + ( [delta] * 2 )
1070 
1071 #endif
1072  case ARM_INS_TBH: // half word table
1073  op->type = RZ_ANALYSIS_OP_TYPE_UJMP;
1074  op->cycles = 2;
1075  op->ptrsize = 2;
1076  op->ireg = rz_str_get_null(cs_reg_name(handle, INSOP(0).mem.index));
1077  break;
1078  case ARM_INS_TBB: // byte jump table
1079  op->type = RZ_ANALYSIS_OP_TYPE_UJMP;
1080  op->cycles = 2;
1081  op->ptrsize = 1;
1082  op->ireg = rz_str_get_null(cs_reg_name(handle, INSOP(0).mem.index));
1083  break;
1084  case ARM_INS_PLD:
1085  op->type = RZ_ANALYSIS_OP_TYPE_LEA; // not really a lea, just a prefetch
1086  if (ISMEM(0)) {
1087  int regBase = REGBASE(0);
1088  int delta = MEMDISP(0);
1089  if (regBase == ARM_REG_PC) {
1090  op->ptr = addr + 4 + delta;
1091  } else {
1092  // exotic pld
1093  }
1094  }
1095  break;
1096  case ARM_INS_IT:
1097  rz_arm_it_update_block(&ctx->it, insn);
1098  op->cycles = 2;
1099  break;
1100  case ARM_INS_BKPT:
1101  op->type = RZ_ANALYSIS_OP_TYPE_TRAP;
1102  op->cycles = 4;
1103  break;
1104  case ARM_INS_NOP:
1105  op->type = RZ_ANALYSIS_OP_TYPE_NOP;
1106  op->cycles = 1;
1107  break;
1108  case ARM_INS_POP:
1109  op->stackop = RZ_ANALYSIS_STACK_INC;
1110  op->stackptr = -4LL * insn->detail->arm.op_count;
1111  // fallthrough
1112  case ARM_INS_FLDMDBX:
1113  case ARM_INS_FLDMIAX:
1114  case ARM_INS_LDMDA:
1115  case ARM_INS_LDMDB:
1116  case ARM_INS_LDMIB:
1117  case ARM_INS_LDM:
1118  op->type = RZ_ANALYSIS_OP_TYPE_POP;
1119  op->cycles = 2;
1120  for (i = 0; i < insn->detail->arm.op_count; i++) {
1121  if (insn->detail->arm.operands[i].type == ARM_OP_REG &&
1122  insn->detail->arm.operands[i].reg == ARM_REG_PC) {
1123  if (insn->detail->arm.cc == ARM_CC_AL) {
1124  op->type = RZ_ANALYSIS_OP_TYPE_RET;
1125  } else {
1126  op->type = RZ_ANALYSIS_OP_TYPE_CRET;
1127  }
1128  break;
1129  }
1130  }
1131  break;
1132  case ARM_INS_SUB:
1133  if (ISREG(0) && REGID(0) == ARM_REG_SP) {
1134  op->stackop = RZ_ANALYSIS_STACK_INC;
1135  if (ISIMM(1)) {
1136  // 0x0000bf4e 95b0 sub sp, 0x54
1137  op->stackptr = IMM(1);
1138  } else if (ISIMM(2) && ISREG(1) && REGID(1) == ARM_REG_SP) {
1139  // 0x00008254 10d04de2 sub sp, sp, 0x10
1140  op->stackptr = IMM(2);
1141  }
1142  op->val = op->stackptr;
1143  }
1144  op->cycles = 1;
1145  /* fall-thru */
1146  case ARM_INS_SUBW:
1147  case ARM_INS_SSUB8:
1148  case ARM_INS_SSUB16:
1149  op->type = RZ_ANALYSIS_OP_TYPE_SUB;
1150  break;
1151  case ARM_INS_ADD:
1152  if (ISREG(0) && REGID(0) == ARM_REG_SP) {
1153  op->stackop = RZ_ANALYSIS_STACK_INC;
1154  if (ISIMM(1)) {
1155  // add sp, 0x54
1156  op->stackptr = -IMM(1);
1157  } else if (ISIMM(2) && ISREG(1) && REGID(1) == ARM_REG_SP) {
1158  // add sp, sp, 0x10
1159  op->stackptr = -IMM(2);
1160  }
1161  op->val = op->stackptr;
1162  }
1163  // fallthrough
1164  case ARM_INS_ADC:
1165  op->type = RZ_ANALYSIS_OP_TYPE_ADD;
1166  if (REGID(0) == ARM_REG_PC) {
1167  op->type = RZ_ANALYSIS_OP_TYPE_UJMP;
1168  if (REGID(1) == ARM_REG_PC && insn->detail->arm.cc != ARM_CC_AL) {
1169  // op->type = RZ_ANALYSIS_OP_TYPE_RCJMP;
1170  op->type = RZ_ANALYSIS_OP_TYPE_UCJMP;
1171  op->fail = addr + op->size;
1172  op->jump = ((addr & ~3LL) + (thumb ? 4 : 8) + MEMDISP(1)) & UT64_MAX;
1173  op->ptr = (addr & ~3LL) + (thumb ? 4 : 8) + MEMDISP(1);
1174  op->refptr = 4;
1175  op->reg = rz_str_get_null(cs_reg_name(handle, INSOP(2).reg));
1176  break;
1177  }
1178  }
1179  op->cycles = 1;
1180  break;
1181  /* fall-thru */
1182  case ARM_INS_ADDW:
1183  case ARM_INS_SADD8:
1184  case ARM_INS_SADD16:
1185  op->type = RZ_ANALYSIS_OP_TYPE_ADD;
1186  break;
1187  case ARM_INS_SDIV:
1188  case ARM_INS_UDIV:
1189  op->cycles = 4;
1190  /* fall-thru */
1191  case ARM_INS_VDIV:
1192  op->type = RZ_ANALYSIS_OP_TYPE_DIV;
1193  break;
1194  case ARM_INS_MUL:
1195  case ARM_INS_SMULL:
1196  case ARM_INS_UMULL:
1197  /* TODO: if next instruction is also a MUL, cycles are /=2 */
1198  /* also known as Register Indexing Addressing */
1199  op->cycles = 4;
1200  /* fall-thru */
1201  case ARM_INS_VMUL:
1202  op->type = RZ_ANALYSIS_OP_TYPE_MUL;
1203  break;
1204  case ARM_INS_TRAP:
1205  op->type = RZ_ANALYSIS_OP_TYPE_TRAP;
1206  op->cycles = 2;
1207  break;
1208  case ARM_INS_MOV:
1209  if (REGID(0) == ARM_REG_PC) {
1210  if (REGID(1) == ARM_REG_LR) {
1211  op->type = RZ_ANALYSIS_OP_TYPE_RET;
1212  } else {
1213  op->type = RZ_ANALYSIS_OP_TYPE_UJMP;
1214  }
1215  }
1216  if (ISIMM(1)) {
1217  op->val = IMM(1);
1218  }
1219  /* fall-thru */
1220  case ARM_INS_MOVT:
1221  case ARM_INS_MOVW:
1222  case ARM_INS_VMOVL:
1223  case ARM_INS_VMOVN:
1224  case ARM_INS_VQMOVUN:
1225  case ARM_INS_VQMOVN:
1226  case ARM_INS_SBFX:
1227  case ARM_INS_UBFX:
1228  case ARM_INS_BIC:
1229  case ARM_INS_BFI:
1230  op->type = RZ_ANALYSIS_OP_TYPE_MOV;
1231  break;
1232  case ARM_INS_VMOV:
1233  op->type = RZ_ANALYSIS_OP_TYPE_MOV;
1234  op->family = RZ_ANALYSIS_OP_FAMILY_FPU;
1235  op->cycles = 2;
1236  break;
1237  case ARM_INS_UDF:
1238  op->type = RZ_ANALYSIS_OP_TYPE_TRAP;
1239  op->cycles = 4;
1240  break;
1241  case ARM_INS_SVC:
1242  op->type = RZ_ANALYSIS_OP_TYPE_SWI;
1243  op->val = IMM(0);
1244  break;
1245  case ARM_INS_ROR:
1246  case ARM_INS_RRX:
1247  op->cycles = 1;
1248  op->type = RZ_ANALYSIS_OP_TYPE_ROR;
1249  break;
1250  case ARM_INS_AND:
1251  op->type = RZ_ANALYSIS_OP_TYPE_AND;
1252  break;
1253  case ARM_INS_ORR:
1254  case ARM_INS_ORN:
1255  op->type = RZ_ANALYSIS_OP_TYPE_OR;
1256  break;
1257  case ARM_INS_EOR:
1258  op->type = RZ_ANALYSIS_OP_TYPE_XOR;
1259  break;
1260  case ARM_INS_CMP:
1261  case ARM_INS_CMN:
1262  case ARM_INS_TST:
1263  if (ISIMM(1)) {
1264  op->ptr = IMM(1);
1265  }
1266  op->reg = rz_str_get_null(cs_reg_name(handle, INSOP(0).reg));
1267  /* fall-thru */
1268  case ARM_INS_VCMP:
1269  op->type = RZ_ANALYSIS_OP_TYPE_CMP;
1270  break;
1271  case ARM_INS_LSL:
1272  op->cycles = 1;
1273  op->type = RZ_ANALYSIS_OP_TYPE_SHL;
1274  break;
1275  case ARM_INS_LSR:
1276  op->cycles = 1;
1277  op->type = RZ_ANALYSIS_OP_TYPE_SHR;
1278  break;
1279  case ARM_INS_ASR:
1280  op->cycles = 1;
1281  op->type = RZ_ANALYSIS_OP_TYPE_SAR;
1282  break;
1283  case ARM_INS_PUSH:
1284  op->stackop = RZ_ANALYSIS_STACK_INC;
1285  op->stackptr = 4LL * insn->detail->arm.op_count;
1286  // fallthrough
1287  case ARM_INS_STM:
1288  case ARM_INS_STMDA:
1289  case ARM_INS_STMDB:
1290  op->type = RZ_ANALYSIS_OP_TYPE_PUSH;
1291  // 0x00008160 04202de5 str r2, [sp, -4]!
1292  // 0x000082a0 28000be5 str r0, [fp, -0x28]
1293  if (REGBASE(1) == ARM_REG_FP) {
1294  op->stackop = RZ_ANALYSIS_STACK_SET;
1295  op->stackptr = 0;
1296  op->ptr = MEMDISP(1);
1297  }
1298  break;
1299  case ARM_INS_STREX:
1300  case ARM_INS_STREXB:
1301  case ARM_INS_STREXD:
1302  case ARM_INS_STREXH:
1303  op->family = RZ_ANALYSIS_OP_FAMILY_THREAD;
1304  /* fall-thru */
1305  case ARM_INS_STR:
1306  case ARM_INS_STRB:
1307  case ARM_INS_STRD:
1308  case ARM_INS_STRBT:
1309  case ARM_INS_STRH:
1310  case ARM_INS_STRHT:
1311  case ARM_INS_STRT:
1312  op->cycles = 4;
1313  op->type = RZ_ANALYSIS_OP_TYPE_STORE;
1314  if (REGBASE(1) == ARM_REG_FP) {
1315  op->stackop = RZ_ANALYSIS_STACK_SET;
1316  op->stackptr = 0;
1317  op->ptr = -MEMDISP(1);
1318  }
1319  break;
1320  case ARM_INS_SXTB:
1321  case ARM_INS_SXTH:
1322  op->cycles = 1;
1323  op->type = RZ_ANALYSIS_OP_TYPE_MOV;
1324  break;
1325  case ARM_INS_LDREX:
1326  case ARM_INS_LDREXB:
1327  case ARM_INS_LDREXD:
1328  case ARM_INS_LDREXH:
1329  op->family = RZ_ANALYSIS_OP_FAMILY_THREAD;
1330  /* fall-thru */
1331  case ARM_INS_LDR:
1332  case ARM_INS_LDRD:
1333  case ARM_INS_LDRB:
1334  case ARM_INS_LDRBT:
1335  case ARM_INS_LDRH:
1336  case ARM_INS_LDRHT:
1337  case ARM_INS_LDRSB:
1338  case ARM_INS_LDRSBT:
1339  case ARM_INS_LDRSH:
1340  case ARM_INS_LDRSHT:
1341  case ARM_INS_LDRT:
1342  op->cycles = 4;
1343  // 0x000082a8 28301be5 ldr r3, [fp, -0x28]
1344  if (INSOP(1).mem.scale != -1) {
1345  op->scale = INSOP(1).mem.scale << LSHIFT(1);
1346  }
1347  op->ireg = cs_reg_name(handle, REGBASE(1));
1348  op->disp = MEMDISP(1);
1349  if (REGID(0) == ARM_REG_PC) {
1350  op->type = RZ_ANALYSIS_OP_TYPE_UJMP;
1351  if (insn->detail->arm.cc != ARM_CC_AL) {
1352  // op->type = RZ_ANALYSIS_OP_TYPE_MCJMP;
1353  op->type = RZ_ANALYSIS_OP_TYPE_UCJMP;
1354  }
1355  } else {
1356  op->type = RZ_ANALYSIS_OP_TYPE_LOAD;
1357  }
1358  switch (insn->id) {
1359  case ARM_INS_LDRB:
1360  op->ptrsize = 1;
1361  break;
1362  case ARM_INS_LDRH:
1363  case ARM_INS_LDRHT:
1364  op->ptrsize = 2;
1365  break;
1366  }
1367  if (REGBASE(1) == ARM_REG_FP) {
1368  op->stackop = RZ_ANALYSIS_STACK_GET;
1369  op->stackptr = 0;
1370  op->ptr = -MEMDISP(1);
1371  } else if (REGBASE(1) == ARM_REG_PC) {
1372  op->ptr = (addr & ~3LL) + (thumb ? 4 : 8) + MEMDISP(1);
1373  op->refptr = 4;
1374  if (REGID(0) == ARM_REG_PC && insn->detail->arm.cc != ARM_CC_AL) {
1375  // op->type = RZ_ANALYSIS_OP_TYPE_MCJMP;
1376  op->type = RZ_ANALYSIS_OP_TYPE_UCJMP;
1377  op->fail = addr + op->size;
1378  op->jump = ((addr & ~3LL) + (thumb ? 4 : 8) + MEMDISP(1)) & UT64_MAX;
1379  op->ireg = rz_str_get_null(cs_reg_name(handle, INSOP(1).mem.index));
1380  break;
1381  }
1382  }
1383  break;
1384  case ARM_INS_MRS:
1385  case ARM_INS_MSR:
1386  op->type = RZ_ANALYSIS_OP_TYPE_MOV;
1387  op->family = RZ_ANALYSIS_OP_FAMILY_PRIV;
1388  break;
1389  case ARM_INS_BLX:
1390  op->cycles = 4;
1391  if (ISREG(0)) {
1392  /* blx reg */
1393  op->type = RZ_ANALYSIS_OP_TYPE_RCALL;
1394  op->reg = cs_reg_name(handle, REGID(0));
1395  } else {
1396  /* blx label */
1397  op->type = RZ_ANALYSIS_OP_TYPE_CALL;
1398  op->jump = IMM(0) & UT32_MAX;
1399  op->fail = addr + op->size;
1400  op->hint.new_bits = (a->bits == 32) ? 16 : 32;
1401  // switch instruction set always with blx label
1402  // rz_analysis_hint_set_bits (a, op->jump, a->bits == 32? 16 : 32);
1403  }
1404  break;
1405  case ARM_INS_BL:
1406  /* bl label */
1407  op->cycles = 4;
1408  op->type = RZ_ANALYSIS_OP_TYPE_CALL;
1409  op->jump = IMM(0) & UT32_MAX;
1410  op->fail = addr + op->size;
1411  op->hint.new_bits = a->bits;
1412  break;
1413  case ARM_INS_CBZ:
1414  case ARM_INS_CBNZ:
1415  op->cycles = 4;
1416  op->type = RZ_ANALYSIS_OP_TYPE_CJMP;
1417  op->jump = IMM(1) & UT32_MAX;
1418  op->fail = addr + op->size;
1419  if (op->jump == op->fail) {
1420  op->type = RZ_ANALYSIS_OP_TYPE_JMP;
1421  op->fail = UT64_MAX;
1422  }
1423  break;
1424  case ARM_INS_B:
1425  /* b.cc label */
1426  op->cycles = 4;
1427  if (insn->detail->arm.cc == ARM_CC_INVALID) {
1428  op->type = RZ_ANALYSIS_OP_TYPE_ILL;
1429  op->fail = addr + op->size;
1430  } else if (insn->detail->arm.cc == ARM_CC_AL) {
1431  op->type = RZ_ANALYSIS_OP_TYPE_JMP;
1432  op->fail = UT64_MAX;
1433  } else {
1434  op->type = RZ_ANALYSIS_OP_TYPE_CJMP;
1435  op->fail = addr + op->size;
1436  }
1437  op->jump = IMM(0) & UT32_MAX;
1438  // propagate bits to create correctly hints ranges
1439  op->hint.new_bits = a->bits;
1440  break;
1441  case ARM_INS_BX:
1442  case ARM_INS_BXJ:
1443  /* bx reg */
1444  op->cycles = 4;
1445  op->reg = cs_reg_name(handle, REGID(0));
1446  switch (REGID(0)) {
1447  case ARM_REG_LR:
1448  op->type = RZ_ANALYSIS_OP_TYPE_RET;
1449  break;
1450  case ARM_REG_IP:
1451  op->type = RZ_ANALYSIS_OP_TYPE_RJMP;
1452  break;
1453  case ARM_REG_PC:
1454  // bx pc is well known without ESIL
1455  op->type = RZ_ANALYSIS_OP_TYPE_RJMP;
1456  op->jump = (addr & ~3LL) + pcdelta;
1457  op->hint.new_bits = 32;
1458  break;
1459  default:
1460  op->type = RZ_ANALYSIS_OP_TYPE_RJMP;
1461  op->eob = true;
1462  break;
1463  }
1464  break;
1465  case ARM_INS_ADR:
1466  op->cycles = 2;
1467  op->type = RZ_ANALYSIS_OP_TYPE_LEA;
1468  // Set the pointer address and align it
1469  op->ptr = IMM(1) + addr + 4 - (addr % 4);
1470  op->refptr = 1;
1471  break;
1472  case ARM_INS_UXTAB:
1473  case ARM_INS_UXTAB16:
1474  op->type = RZ_ANALYSIS_OP_TYPE_ADD;
1475  op->ptr = 0LL;
1476  op->ptrsize = 1;
1477  break;
1478  case ARM_INS_UXTAH:
1479  op->type = RZ_ANALYSIS_OP_TYPE_ADD;
1480  op->ptr = 0LL;
1481  op->ptrsize = 2;
1482  break;
1483  case ARM_INS_UXTB:
1484  case ARM_INS_UXTB16:
1485  op->type = RZ_ANALYSIS_OP_TYPE_CAST;
1486  op->ptr = 0LL;
1487  op->ptrsize = 1;
1488  break;
1489  case ARM_INS_UXTH:
1490  op->type = RZ_ANALYSIS_OP_TYPE_CAST;
1491  op->ptr = 0LL;
1492  op->ptrsize = 2;
1493  break;
1494  default:
1495  RZ_LOG_DEBUG("ARM analysis: Op type %d at 0x%" PFMT64x " not handled\n", insn->id, op->addr);
1496  break;
1497  }
1498  if (thumb && rz_arm_it_apply_cond(&ctx->it, insn)) {
1499  op->mnemonic = rz_str_newf("%s%s%s%s",
1500  rz_analysis_optype_to_string(op->type),
1501  cc_name(insn->detail->arm.cc),
1502  insn->op_str[0] ? " " : "",
1503  insn->op_str);
1504  op->cond = (RzTypeCond)insn->detail->arm.cc;
1505  }
1506 }
1507 
1508 static bool is_valid(arm_reg reg) {
1509  return reg != ARM_REG_INVALID;
1510 }
1511 
1512 static int parse_reg_name(RzReg *reg, RzRegItem **reg_base, RzRegItem **reg_delta, csh handle, cs_insn *insn, int reg_num) {
1513  cs_arm_op armop = INSOP(reg_num);
1514  switch (armop.type) {
1515  case ARM_OP_REG:
1516  *reg_base = rz_reg_get(reg, cs_reg_name(handle, armop.reg), RZ_REG_TYPE_ANY);
1517  break;
1518  case ARM_OP_MEM:
1519  if (is_valid(armop.mem.base) && is_valid(armop.mem.index)) {
1520  *reg_base = rz_reg_get(reg, cs_reg_name(handle, armop.mem.base), RZ_REG_TYPE_ANY);
1521  *reg_delta = rz_reg_get(reg, cs_reg_name(handle, armop.mem.index), RZ_REG_TYPE_ANY);
1522  } else if (is_valid(armop.mem.base)) {
1523  *reg_base = rz_reg_get(reg, cs_reg_name(handle, armop.mem.base), RZ_REG_TYPE_ANY);
1524  } else if (is_valid(armop.mem.index)) {
1525  *reg_base = rz_reg_get(reg, cs_reg_name(handle, armop.mem.index), RZ_REG_TYPE_ANY);
1526  }
1527  break;
1528  default:
1529  break;
1530  }
1531  return 0;
1532 }
1533 
1534 static bool is_valid64(arm64_reg reg) {
1535  return reg != ARM64_REG_INVALID;
1536 }
1537 
1538 static char *reg_list[] = {
1539  "x0", "x1", "x2", "x3", "x4",
1540  "x5", "x6", "x7", "x8", "x9",
1541  "x10", "x11", "x12", "x13", "x14",
1542  "x15", "x16", "x17", "x18", "x19",
1543  "x20", "x21", "x22", "x23", "x24",
1544  "x25", "x26", "x27", "x28", "x29",
1545  "x30"
1546 };
1547 
1548 static int parse_reg64_name(RzReg *reg, RzRegItem **reg_base, RzRegItem **reg_delta, csh handle, cs_insn *insn, int reg_num) {
1549  cs_arm64_op armop = INSOP64(reg_num);
1550  switch (armop.type) {
1551  case ARM64_OP_REG:
1552  *reg_base = rz_reg_get(reg, cs_reg_name(handle, armop.reg), RZ_REG_TYPE_ANY);
1553  break;
1554  case ARM64_OP_MEM:
1555  if (is_valid64(armop.mem.base) && is_valid64(armop.mem.index)) {
1556  *reg_base = rz_reg_get(reg, cs_reg_name(handle, armop.mem.base), RZ_REG_TYPE_ANY);
1557  *reg_delta = rz_reg_get(reg, cs_reg_name(handle, armop.mem.index), RZ_REG_TYPE_ANY);
1558  } else if (is_valid64(armop.mem.base)) {
1559  *reg_base = rz_reg_get(reg, cs_reg_name(handle, armop.mem.base), RZ_REG_TYPE_ANY);
1560  } else if (is_valid64(armop.mem.index)) {
1561  *reg_base = rz_reg_get(reg, cs_reg_name(handle, armop.mem.index), RZ_REG_TYPE_ANY);
1562  }
1563  break;
1564  default:
1565  break;
1566  }
1567  if (*reg_base && *(*reg_base)->name == 'w') {
1568  *reg_base = rz_reg_get(reg, reg_list[atoi((*reg_base)->name + 1)], RZ_REG_TYPE_ANY);
1569  }
1570  return 0;
1571 }
1572 
1573 static void set_opdir(RzAnalysisOp *op) {
1574  switch (op->type & RZ_ANALYSIS_OP_TYPE_MASK) {
1575  case RZ_ANALYSIS_OP_TYPE_LOAD:
1576  op->direction = RZ_ANALYSIS_OP_DIR_READ;
1577  break;
1578  case RZ_ANALYSIS_OP_TYPE_STORE:
1579  op->direction = RZ_ANALYSIS_OP_DIR_WRITE;
1580  break;
1581  case RZ_ANALYSIS_OP_TYPE_LEA:
1582  op->direction = RZ_ANALYSIS_OP_DIR_REF;
1583  break;
1584  case RZ_ANALYSIS_OP_TYPE_CALL:
1585  case RZ_ANALYSIS_OP_TYPE_JMP:
1586  case RZ_ANALYSIS_OP_TYPE_UJMP:
1587  case RZ_ANALYSIS_OP_TYPE_UCALL:
1588  op->direction = RZ_ANALYSIS_OP_DIR_EXEC;
1589  break;
1590  default:
1591  break;
1592  }
1593 }
1594 
1595 static void set_src_dst(RzAnalysisValue *val, RzReg *reg, csh *handle, cs_insn *insn, int x, int bits) {
1596  cs_arm_op armop = INSOP(x);
1597  cs_arm64_op arm64op = INSOP64(x);
1598  if (bits == 64) {
1599  parse_reg64_name(reg, &val->reg, &val->regdelta, *handle, insn, x);
1600  } else {
1601  parse_reg_name(reg, &val->reg, &val->regdelta, *handle, insn, x);
1602  }
1603  if (bits == 64) {
1604  switch (arm64op.type) {
1605  case ARM64_OP_REG:
1606  val->type = RZ_ANALYSIS_VAL_REG;
1607  break;
1608  case ARM64_OP_MEM:
1609  val->type = RZ_ANALYSIS_VAL_MEM;
1610  val->delta = arm64op.mem.disp;
1611  break;
1612  case ARM64_OP_IMM:
1613  val->type = RZ_ANALYSIS_VAL_IMM;
1614  val->imm = arm64op.imm;
1615  break;
1616  default:
1617  break;
1618  }
1619  } else {
1620  switch (armop.type) {
1621  case ARM_OP_REG:
1622  val->type = RZ_ANALYSIS_VAL_REG;
1623  break;
1624  case ARM_OP_MEM:
1625  val->type = RZ_ANALYSIS_VAL_MEM;
1626 #if CS_API_MAJOR > 3
1627  val->mul = armop.mem.scale << armop.mem.lshift;
1628 #endif
1629  val->delta = armop.mem.disp;
1630  break;
1631  case ARM_OP_IMM:
1632  val->type = RZ_ANALYSIS_VAL_IMM;
1633  val->imm = armop.imm;
1634  break;
1635  default:
1636  break;
1637  }
1638  }
1639 }
1640 
1641 static void create_src_dst(RzAnalysisOp *op) {
1642  op->src[0] = rz_analysis_value_new();
1643  op->src[1] = rz_analysis_value_new();
1644  op->src[2] = rz_analysis_value_new();
1645  op->dst = rz_analysis_value_new();
1646 }
1647 
1648 static void op_fillval(RzAnalysis *analysis, RzAnalysisOp *op, csh handle, cs_insn *insn, int bits) {
1649  create_src_dst(op);
1650  int i, j;
1651  int count = bits == 64 ? insn->detail->arm64.op_count : insn->detail->arm.op_count;
1652  switch (op->type & RZ_ANALYSIS_OP_TYPE_MASK) {
1653  case RZ_ANALYSIS_OP_TYPE_MOV:
1654  case RZ_ANALYSIS_OP_TYPE_CMP:
1655  case RZ_ANALYSIS_OP_TYPE_ADD:
1656  case RZ_ANALYSIS_OP_TYPE_SUB:
1657  case RZ_ANALYSIS_OP_TYPE_MUL:
1658  case RZ_ANALYSIS_OP_TYPE_DIV:
1659  case RZ_ANALYSIS_OP_TYPE_SHR:
1660  case RZ_ANALYSIS_OP_TYPE_SHL:
1661  case RZ_ANALYSIS_OP_TYPE_SAL:
1662  case RZ_ANALYSIS_OP_TYPE_SAR:
1663  case RZ_ANALYSIS_OP_TYPE_OR:
1664  case RZ_ANALYSIS_OP_TYPE_AND:
1665  case RZ_ANALYSIS_OP_TYPE_XOR:
1666  case RZ_ANALYSIS_OP_TYPE_NOR:
1667  case RZ_ANALYSIS_OP_TYPE_NOT:
1668  case RZ_ANALYSIS_OP_TYPE_LOAD:
1669  case RZ_ANALYSIS_OP_TYPE_LEA:
1670  case RZ_ANALYSIS_OP_TYPE_ROR:
1671  case RZ_ANALYSIS_OP_TYPE_ROL:
1672  case RZ_ANALYSIS_OP_TYPE_CAST:
1673  for (i = 1; i < count; i++) {
1674 #if CS_API_MAJOR > 3
1675  if (bits == 64) {
1676  cs_arm64_op arm64op = INSOP64(i);
1677  if (arm64op.access == CS_AC_WRITE) {
1678  continue;
1679  }
1680  } else {
1681  cs_arm_op armop = INSOP(i);
1682 
1683  if (armop.access == CS_AC_WRITE) {
1684  continue;
1685  }
1686  }
1687 #endif
1688  break;
1689  }
1690  for (j = 0; j < 3; j++, i++) {
1691  set_src_dst(op->src[j], analysis->reg, &handle, insn, i, bits);
1692  }
1693  set_src_dst(op->dst, analysis->reg, &handle, insn, 0, bits);
1694  break;
1695  case RZ_ANALYSIS_OP_TYPE_STORE:
1696  if (count > 2) {
1697  if (bits == 64) {
1698  cs_arm64_op arm64op = INSOP64(count - 1);
1699  if (arm64op.type == ARM64_OP_IMM) {
1700  count--;
1701  }
1702  } else {
1703  cs_arm_op armop = INSOP(count - 1);
1704  if (armop.type == ARM_OP_IMM) {
1705  count--;
1706  }
1707  }
1708  }
1709  set_src_dst(op->dst, analysis->reg, &handle, insn, --count, bits);
1710  for (j = 0; j < 3 && j < count; j++) {
1711  set_src_dst(op->src[j], analysis->reg, &handle, insn, j, bits);
1712  }
1713  break;
1714  default:
1715  break;
1716  }
1717 }
1718 
1719 static void patch_capstone_bugs(cs_insn *insn, int bits, bool big_endian) {
1720  if (!insn->detail) {
1721  return;
1722  }
1723  if (bits == 32) {
1724  cs_arm *detail = &insn->detail->arm;
1725 
1726  // b40071e0 ldrht r0, [r1], -4
1727  // has operand 2 as immediate 4 (positive) and subtracted as false from capstone.
1728  // This is wrong and makes it impossible to distinguish from b400f1e0 ldrht r0, [r1], 4.
1729  // We just read the respective bit from the encoding.
1730  if (insn->id == ARM_INS_LDRHT && ISREG(0) && ISMEM(1) && ISIMM(2)) {
1731  ut32 op = rz_read_ble32(insn->bytes, big_endian);
1732  if (!(op & (1 << 23))) {
1733  detail->operands[2].subtracted = true;
1734  }
1735  }
1736  }
1737 }
1738 
1739 static int analysis_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, RzAnalysisOpMask mask) {
1740  ArmCSContext *ctx = (ArmCSContext *)a->plugin_data;
1741 
1742  cs_insn *insn = NULL;
1743  int mode = (a->bits == 16) ? CS_MODE_THUMB : CS_MODE_ARM;
1744  int n, ret;
1745  mode |= (a->big_endian) ? CS_MODE_BIG_ENDIAN : CS_MODE_LITTLE_ENDIAN;
1746  if (a->cpu && strstr(a->cpu, "cortex")) {
1747  mode |= CS_MODE_MCLASS;
1748  }
1749 
1750  if (mode != ctx->omode || a->bits != ctx->obits) {
1751  cs_close(&ctx->handle);
1752  ctx->handle = 0; // unnecessary
1753  ctx->omode = mode;
1754  ctx->obits = a->bits;
1755  }
1756  op->size = (a->bits == 16) ? 2 : 4;
1757  op->addr = addr;
1758  if (ctx->handle == 0) {
1759  ret = (a->bits == 64) ? cs_open(CS_ARCH_ARM64, mode, &ctx->handle) : cs_open(CS_ARCH_ARM, mode, &ctx->handle);
1760  cs_option(ctx->handle, CS_OPT_DETAIL, CS_OPT_ON);
1761  if (ret != CS_ERR_OK) {
1762  ctx->handle = 0;
1763  return -1;
1764  }
1765  }
1766  int haa = hackyArmAnal(a, op, buf, len); // TODO: disable this for capstone 5 after testing that everything works
1767  if (haa > 0) {
1768  return haa;
1769  }
1770 
1771  n = cs_disasm(ctx->handle, (ut8 *)buf, len, addr, 1, &insn);
1772  if (n < 1) {
1773  op->type = RZ_ANALYSIS_OP_TYPE_ILL;
1774  if (mask & RZ_ANALYSIS_OP_MASK_DISASM) {
1775  op->mnemonic = strdup("invalid");
1776  }
1777  } else {
1778  patch_capstone_bugs(insn, a->bits, a->big_endian);
1779  if (mask & RZ_ANALYSIS_OP_MASK_DISASM) {
1780  op->mnemonic = rz_str_newf("%s%s%s",
1781  insn->mnemonic,
1782  insn->op_str[0] ? " " : "",
1783  insn->op_str);
1784  }
1785  // bool thumb = cs_insn_group (handle, insn, ARM_GRP_THUMB);
1786  bool thumb = a->bits == 16;
1787  op->size = insn->size;
1788  op->id = insn->id;
1789  if (a->bits == 64) {
1790  anop64(ctx, op, insn);
1791  if (mask & RZ_ANALYSIS_OP_MASK_OPEX) {
1792  opex64(&op->opex, ctx->handle, insn);
1793  }
1794  if (mask & RZ_ANALYSIS_OP_MASK_ESIL) {
1795  rz_arm_cs_analysis_op_64_esil(a, op, addr, buf, len, &ctx->handle, insn);
1796  }
1797  if (mask & RZ_ANALYSIS_OP_MASK_IL) {
1798  op->il_op = rz_arm_cs_64_il(&ctx->handle, insn);
1799  }
1800  } else {
1801  anop32(a, ctx->handle, op, insn, thumb, (ut8 *)buf, len);
1802  if (mask & RZ_ANALYSIS_OP_MASK_OPEX) {
1803  opex(&op->opex, ctx->handle, insn);
1804  }
1805  if (mask & RZ_ANALYSIS_OP_MASK_ESIL) {
1806  rz_arm_cs_analysis_op_32_esil(a, op, addr, buf, len, &ctx->handle, insn, thumb);
1807  }
1808  if (mask & RZ_ANALYSIS_OP_MASK_IL) {
1809  op->il_op = rz_arm_cs_32_il(&ctx->handle, insn, thumb);
1810  }
1811  }
1812  set_opdir(op);
1813  if (mask & RZ_ANALYSIS_OP_MASK_VAL) {
1814  op_fillval(a, op, ctx->handle, insn, a->bits);
1815  }
1816  cs_free(insn, n);
1817  }
1818  // cs_close (&handle);
1819  return op->size;
1820 }
1821 
1822 static char *get_reg_profile(RzAnalysis *analysis) {
1823  const char *p;
1824  if (analysis->bits == 64) {
1825  const char *snReg = (!strcmp(analysis->os, "android") || !strcmp(analysis->os, "linux")) ? "x8" : "x16";
1826  p =
1827  "=PC pc\n"
1828  "=SP sp\n"
1829  "=BP x29\n"
1830  "=A0 x0\n"
1831  "=A1 x1\n"
1832  "=A2 x2\n"
1833  "=A3 x3\n"
1834  "=ZF zf\n"
1835  "=SF nf\n"
1836  "=OF vf\n"
1837  "=CF cf\n"
1838  "=SN %s\n" // x8 on linux or android, x16 for the rest
1839 
1840  /* 64bit */
1841  "gpr x0 .64 0 0\n"
1842  "gpr x1 .64 8 0\n"
1843  "gpr x2 .64 16 0\n"
1844  "gpr x3 .64 24 0\n"
1845  "gpr x4 .64 32 0\n"
1846  "gpr x5 .64 40 0\n"
1847  "gpr x6 .64 48 0\n"
1848  "gpr x7 .64 56 0\n"
1849  "gpr x8 .64 64 0\n"
1850  "gpr x9 .64 72 0\n"
1851  "gpr x10 .64 80 0\n"
1852  "gpr x11 .64 88 0\n"
1853  "gpr x12 .64 96 0\n"
1854  "gpr x13 .64 104 0\n"
1855  "gpr x14 .64 112 0\n"
1856  "gpr x15 .64 120 0\n"
1857  "gpr x16 .64 128 0\n"
1858  "gpr x17 .64 136 0\n"
1859  "gpr x18 .64 144 0\n"
1860  "gpr x19 .64 152 0\n"
1861  "gpr x20 .64 160 0\n"
1862  "gpr x21 .64 168 0\n"
1863  "gpr x22 .64 176 0\n"
1864  "gpr x23 .64 184 0\n"
1865  "gpr x24 .64 192 0\n"
1866  "gpr x25 .64 200 0\n"
1867  "gpr x26 .64 208 0\n"
1868  "gpr x27 .64 216 0\n"
1869  "gpr x28 .64 224 0\n"
1870  "gpr x29 .64 232 0\n"
1871  "gpr x30 .64 240 0\n"
1872  "gpr tmp .64 288 0\n"
1873  /* 32bit sub-registers */
1874  "gpr w0 .32 0 0\n"
1875  "gpr w1 .32 8 0\n"
1876  "gpr w2 .32 16 0\n"
1877  "gpr w3 .32 24 0\n"
1878  "gpr w4 .32 32 0\n"
1879  "gpr w5 .32 40 0\n"
1880  "gpr w6 .32 48 0\n"
1881  "gpr w7 .32 56 0\n"
1882  "gpr w8 .32 64 0\n"
1883  "gpr w9 .32 72 0\n"
1884  "gpr w10 .32 80 0\n"
1885  "gpr w11 .32 88 0\n"
1886  "gpr w12 .32 96 0\n"
1887  "gpr w13 .32 104 0\n"
1888  "gpr w14 .32 112 0\n"
1889  "gpr w15 .32 120 0\n"
1890  "gpr w16 .32 128 0\n"
1891  "gpr w17 .32 136 0\n"
1892  "gpr w18 .32 144 0\n"
1893  "gpr w19 .32 152 0\n"
1894  "gpr w20 .32 160 0\n"
1895  "gpr w21 .32 168 0\n"
1896  "gpr w22 .32 176 0\n"
1897  "gpr w23 .32 184 0\n"
1898  "gpr w24 .32 192 0\n"
1899  "gpr w25 .32 200 0\n"
1900  "gpr w26 .32 208 0\n"
1901  "gpr w27 .32 216 0\n"
1902  "gpr w28 .32 224 0\n"
1903  "gpr w29 .32 232 0\n"
1904  "gpr w30 .32 240 0\n"
1905  "gpr wsp .32 248 0\n"
1906  "gpr wzr .32 ? 0\n"
1907 
1908  /* aliases */
1909  "gpr fp .64 232 0\n" // fp = x29
1910  "gpr lr .64 240 0\n" // lr = x30
1911  "gpr sp .64 248 0\n"
1912  "gpr pc .64 256 0\n"
1913  "gpr zr .64 ? 0\n"
1914  "gpr xzr .64 ? 0\n"
1915  /* flags */
1916  "flg pstate .64 280 0 _____tfiae_____________j__qvczn\n" // x0
1917  //"flg cpsr .32 280 0\n" // _____tfiae_____________j__qvczn\n"
1918  "flg vf .1 280.28 0 overflow\n" // set if overflows
1919  "flg cf .1 280.29 0 carry\n" // set if last op carries
1920  "flg zf .1 280.30 0 zero\n" // set if last op is 0
1921  "flg nf .1 280.31 0 sign\n" // msb bit of last op
1922 
1923  /* 64bit double */
1924  "fpu d0 .64 0 0\n"
1925  "fpu d1 .64 8 0\n"
1926  "fpu d2 .64 16 0\n"
1927  "fpu d3 .64 24 0\n"
1928  "fpu d4 .64 32 0\n"
1929  "fpu d5 .64 40 0\n"
1930  "fpu d6 .64 48 0\n"
1931  "fpu d7 .64 56 0\n"
1932  "fpu d8 .64 64 0\n"
1933  "fpu d9 .64 72 0\n"
1934  "fpu d10 .64 80 0\n"
1935  "fpu d11 .64 88 0\n"
1936  "fpu d12 .64 96 0\n"
1937  "fpu d13 .64 104 0\n"
1938  "fpu d14 .64 112 0\n"
1939  "fpu d15 .64 120 0\n"
1940  "fpu d16 .64 128 0\n"
1941  "fpu d17 .64 136 0\n"
1942  "fpu d18 .64 144 0\n"
1943  "fpu d19 .64 152 0\n"
1944  "fpu d20 .64 160 0\n"
1945  "fpu d21 .64 168 0\n"
1946  "fpu d22 .64 176 0\n"
1947  "fpu d23 .64 184 0\n"
1948  "fpu d24 .64 192 0\n"
1949  "fpu d25 .64 200 0\n"
1950  "fpu d26 .64 208 0\n"
1951  "fpu d27 .64 216 0\n"
1952  "fpu d28 .64 224 0\n"
1953  "fpu d29 .64 232 0\n"
1954  "fpu d30 .64 240 0\n"
1955  "fpu dsp .64 248 0\n"
1956  /* 32bit float sub-registers */
1957  "fpu s0 .32 0 0\n"
1958  "fpu s1 .32 8 0\n"
1959  "fpu s2 .32 16 0\n"
1960  "fpu s3 .32 24 0\n"
1961  "fpu s4 .32 32 0\n"
1962  "fpu s5 .32 40 0\n"
1963  "fpu s6 .32 48 0\n"
1964  "fpu s7 .32 56 0\n"
1965  "fpu s8 .32 64 0\n"
1966  "fpu s9 .32 72 0\n"
1967  "fpu s10 .32 80 0\n"
1968  "fpu s11 .32 88 0\n"
1969  "fpu s12 .32 96 0\n"
1970  "fpu s13 .32 104 0\n"
1971  "fpu s14 .32 112 0\n"
1972  "fpu s15 .32 120 0\n"
1973  "fpu s16 .32 128 0\n"
1974  "fpu s17 .32 136 0\n"
1975  "fpu s18 .32 144 0\n"
1976  "fpu s19 .32 152 0\n"
1977  "fpu s20 .32 160 0\n"
1978  "fpu s21 .32 168 0\n"
1979  "fpu s22 .32 176 0\n"
1980  "fpu s23 .32 184 0\n"
1981  "fpu s24 .32 192 0\n"
1982  "fpu s25 .32 200 0\n"
1983  "fpu s26 .32 208 0\n"
1984  "fpu s27 .32 216 0\n"
1985  "fpu s28 .32 224 0\n"
1986  "fpu s29 .32 232 0\n"
1987  "fpu s30 .32 240 0\n"
1988  /* 16bit sub-registers */
1989  "fpu h0 .16 0 0\n"
1990  "fpu h1 .16 8 0\n"
1991  "fpu h2 .16 16 0\n"
1992  "fpu h3 .16 24 0\n"
1993  "fpu h4 .16 32 0\n"
1994  "fpu h5 .16 40 0\n"
1995  "fpu h6 .16 48 0\n"
1996  "fpu h7 .16 56 0\n"
1997  "fpu h8 .16 64 0\n"
1998  "fpu h9 .16 72 0\n"
1999  "fpu h10 .16 80 0\n"
2000  "fpu h11 .16 88 0\n"
2001  "fpu h12 .16 96 0\n"
2002  "fpu h13 .16 104 0\n"
2003  "fpu h14 .16 112 0\n"
2004  "fpu h15 .16 120 0\n"
2005  "fpu h16 .16 128 0\n"
2006  "fpu h17 .16 136 0\n"
2007  "fpu h18 .16 144 0\n"
2008  "fpu h19 .16 152 0\n"
2009  "fpu h20 .16 160 0\n"
2010  "fpu h21 .16 168 0\n"
2011  "fpu h22 .16 176 0\n"
2012  "fpu h23 .16 184 0\n"
2013  "fpu h24 .16 192 0\n"
2014  "fpu h25 .16 200 0\n"
2015  "fpu h26 .16 208 0\n"
2016  "fpu h27 .16 216 0\n"
2017  "fpu h28 .16 224 0\n"
2018  "fpu h29 .16 232 0\n"
2019  "fpu h30 .16 240 0\n"
2020  /* 8bit sub-registers */
2021  "fpu b0 .8 0 0\n"
2022  "fpu b1 .8 8 0\n"
2023  "fpu b2 .8 16 0\n"
2024  "fpu b3 .8 24 0\n"
2025  "fpu b4 .8 32 0\n"
2026  "fpu b5 .8 40 0\n"
2027  "fpu b6 .8 48 0\n"
2028  "fpu b7 .8 56 0\n"
2029  "fpu b8 .8 64 0\n"
2030  "fpu b9 .8 72 0\n"
2031  "fpu b10 .8 80 0\n"
2032  "fpu b11 .8 88 0\n"
2033  "fpu b12 .8 96 0\n"
2034  "fpu b13 .8 104 0\n"
2035  "fpu b14 .8 112 0\n"
2036  "fpu b15 .8 120 0\n"
2037  "fpu b16 .8 128 0\n"
2038  "fpu b17 .8 136 0\n"
2039  "fpu b18 .8 144 0\n"
2040  "fpu b19 .8 152 0\n"
2041  "fpu b20 .8 160 0\n"
2042  "fpu b21 .8 168 0\n"
2043  "fpu b22 .8 176 0\n"
2044  "fpu b23 .8 184 0\n"
2045  "fpu b24 .8 192 0\n"
2046  "fpu b25 .8 200 0\n"
2047  "fpu b26 .8 208 0\n"
2048  "fpu b27 .8 216 0\n"
2049  "fpu b28 .8 224 0\n"
2050  "fpu b29 .8 232 0\n"
2051  "fpu b30 .8 240 0\n"
2052  "fpu bsp .8 248 0\n";
2053  return rz_str_newf(p, snReg);
2054  } else {
2055  p =
2056  "=PC r15\n"
2057  "=LR r14\n"
2058  "=SP sp\n"
2059  "=BP fp\n"
2060  "=A0 r0\n"
2061  "=A1 r1\n"
2062  "=A2 r2\n"
2063  "=A3 r3\n"
2064  "=ZF zf\n"
2065  "=SF nf\n"
2066  "=OF vf\n"
2067  "=CF cf\n"
2068  "=SN r7\n"
2069  "gpr sb .32 36 0\n" // r9
2070  "gpr sl .32 40 0\n" // rl0
2071  "gpr fp .32 44 0\n" // r11
2072  "gpr ip .32 48 0\n" // r12
2073  "gpr sp .32 52 0\n" // r13
2074  "gpr lr .32 56 0\n" // r14
2075  "gpr pc .32 60 0\n" // r15
2076 
2077  "gpr r0 .32 0 0\n"
2078  "gpr r1 .32 4 0\n"
2079  "gpr r2 .32 8 0\n"
2080  "gpr r3 .32 12 0\n"
2081  "gpr r4 .32 16 0\n"
2082  "gpr r5 .32 20 0\n"
2083  "gpr r6 .32 24 0\n"
2084  "gpr r7 .32 28 0\n"
2085  "gpr r8 .32 32 0\n"
2086  "gpr r9 .32 36 0\n"
2087  "gpr r10 .32 40 0\n"
2088  "gpr r11 .32 44 0\n"
2089  "gpr r12 .32 48 0\n"
2090  "gpr r13 .32 52 0\n"
2091  "gpr r14 .32 56 0\n"
2092  "gpr r15 .32 60 0\n"
2093  "flg cpsr .32 64 0\n"
2094 
2095  // CPSR bit fields:
2096  // 576-580 Mode fields (and register sets associated to each field):
2097  // 10000 User R0-R14, CPSR, PC
2098  // 10001 FIQ R0-R7, R8_fiq-R14_fiq, CPSR, SPSR_fiq, PC
2099  // 10010 IRQ R0-R12, R13_irq, R14_irq, CPSR, SPSR_irq, PC
2100  // 10011 SVC (supervisor) R0-R12, R13_svc R14_svc CPSR, SPSR_irq, PC
2101  // 10111 Abort R0-R12, R13_abt R14_abt CPSR, SPSR_abt PC
2102  // 11011 Undefined R0-R12, R13_und R14_und, CPSR, SPSR_und PC
2103  // 11111 System (ARMv4+) R0-R14, CPSR, PC
2104  "flg tf .1 .517 0 thumb\n" // +5
2105  // 582 FIQ disable bit
2106  // 583 IRQ disable bit
2107  // 584 Disable imprecise aborts flag
2108  "flg ef .1 .521 0 endian\n" // +9
2109  "flg itc .4 .522 0 if_then_count\n" // +10
2110  // Reserved
2111  "flg gef .4 .528 0 great_or_equal\n" // +16
2112  "flg jf .1 .536 0 java\n" // +24
2113  // Reserved
2114  "flg qf .1 .539 0 sticky_overflow\n" // +27
2115  "flg vf .1 .540 0 overflow\n" // +28
2116  "flg cf .1 .541 0 carry\n" // +29
2117  "flg zf .1 .542 0 zero\n" // +30
2118  "flg nf .1 .543 0 negative\n" // +31
2119 
2120  /* NEON and VFP registers */
2121  /* 32bit float sub-registers */
2122  "fpu s0 .32 68 0\n"
2123  "fpu s1 .32 72 0\n"
2124  "fpu s2 .32 76 0\n"
2125  "fpu s3 .32 80 0\n"
2126  "fpu s4 .32 84 0\n"
2127  "fpu s5 .32 88 0\n"
2128  "fpu s6 .32 92 0\n"
2129  "fpu s7 .32 96 0\n"
2130  "fpu s8 .32 100 0\n"
2131  "fpu s9 .32 104 0\n"
2132  "fpu s10 .32 108 0\n"
2133  "fpu s11 .32 112 0\n"
2134  "fpu s12 .32 116 0\n"
2135  "fpu s13 .32 120 0\n"
2136  "fpu s14 .32 124 0\n"
2137  "fpu s15 .32 128 0\n"
2138  "fpu s16 .32 132 0\n"
2139  "fpu s17 .32 136 0\n"
2140  "fpu s18 .32 140 0\n"
2141  "fpu s19 .32 144 0\n"
2142  "fpu s20 .32 148 0\n"
2143  "fpu s21 .32 152 0\n"
2144  "fpu s22 .32 156 0\n"
2145  "fpu s23 .32 160 0\n"
2146  "fpu s24 .32 164 0\n"
2147  "fpu s25 .32 168 0\n"
2148  "fpu s26 .32 172 0\n"
2149  "fpu s27 .32 176 0\n"
2150  "fpu s28 .32 180 0\n"
2151  "fpu s29 .32 184 0\n"
2152  "fpu s30 .32 188 0\n"
2153  "fpu s31 .32 192 0\n"
2154 
2155  /* 64bit double */
2156  "fpu d0 .64 68 0\n"
2157  "fpu d1 .64 76 0\n"
2158  "fpu d2 .64 84 0\n"
2159  "fpu d3 .64 92 0\n"
2160  "fpu d4 .64 100 0\n"
2161  "fpu d5 .64 108 0\n"
2162  "fpu d6 .64 116 0\n"
2163  "fpu d7 .64 124 0\n"
2164  "fpu d8 .64 132 0\n"
2165  "fpu d9 .64 140 0\n"
2166  "fpu d10 .64 148 0\n"
2167  "fpu d11 .64 156 0\n"
2168  "fpu d12 .64 164 0\n"
2169  "fpu d13 .64 172 0\n"
2170  "fpu d14 .64 180 0\n"
2171  "fpu d15 .64 188 0\n"
2172  "fpu d16 .64 196 0\n"
2173  "fpu d17 .64 204 0\n"
2174  "fpu d18 .64 212 0\n"
2175  "fpu d19 .64 220 0\n"
2176  "fpu d20 .64 228 0\n"
2177  "fpu d21 .64 236 0\n"
2178  "fpu d22 .64 244 0\n"
2179  "fpu d23 .64 252 0\n"
2180  "fpu d24 .64 260 0\n"
2181  "fpu d25 .64 268 0\n"
2182  "fpu d26 .64 276 0\n"
2183  "fpu d27 .64 284 0\n"
2184  "fpu d28 .64 292 0\n"
2185  "fpu d29 .64 300 0\n"
2186  "fpu d30 .64 308 0\n"
2187  "fpu d31 .64 316 0\n"
2188 
2189  /* 128bit double */
2190  "fpu q0 .128 68 0\n"
2191  "fpu q1 .128 84 0\n"
2192  "fpu q2 .128 100 0\n"
2193  "fpu q3 .128 116 0\n"
2194  "fpu q4 .128 132 0\n"
2195  "fpu q5 .128 148 0\n"
2196  "fpu q6 .128 164 0\n"
2197  "fpu q7 .128 180 0\n"
2198  "fpu q8 .128 196 0\n"
2199  "fpu q9 .128 212 0\n"
2200  "fpu q10 .128 228 0\n"
2201  "fpu q11 .128 244 0\n"
2202  "fpu q12 .128 260 0\n"
2203  "fpu q13 .128 276 0\n"
2204  "fpu q14 .128 292 0\n"
2205  "fpu q15 .128 308 0\n";
2206  }
2207  return strdup(p);
2208 }
2209 
2210 static int archinfo(RzAnalysis *analysis, int q) {
2211  if (q == RZ_ANALYSIS_ARCHINFO_DATA_ALIGN) {
2212  return 4;
2213  }
2214  if (q == RZ_ANALYSIS_ARCHINFO_ALIGN) {
2215  if (analysis && analysis->bits == 16) {
2216  return 2;
2217  }
2218  return 4;
2219  }
2220  if (q == RZ_ANALYSIS_ARCHINFO_MAX_OP_SIZE) {
2221  return 4;
2222  }
2223  if (q == RZ_ANALYSIS_ARCHINFO_MIN_OP_SIZE) {
2224  if (analysis && analysis->bits == 16) {
2225  return 2;
2226  }
2227  return 4;
2228  }
2229  return 4; // XXX
2230 }
2231 
2232 static ut8 *analysis_mask(RzAnalysis *analysis, int size, const ut8 *data, ut64 at) {
2233  RzAnalysisOp *op = NULL;
2234  ut8 *ret = NULL;
2235  int oplen, idx = 0, obits = analysis->bits;
2236  RzAnalysisHint *hint = NULL;
2237 
2238  if (!data) {
2239  return NULL;
2240  }
2241 
2242  op = rz_analysis_op_new();
2243  ret = malloc(size);
2244  memset(ret, 0xff, size);
2245 
2246  while (idx < size) {
2247  hint = rz_analysis_hint_get(analysis, at + idx);
2248  if (hint) {
2249  if (hint->bits != 0) {
2250  analysis->bits = hint->bits;
2251  }
2252  free(hint);
2253  }
2254 
2255  if ((oplen = analysis_op(analysis, op, at + idx, data + idx, size - idx, RZ_ANALYSIS_OP_MASK_BASIC)) < 1) {
2256  break;
2257  }
2258  if (op->ptr != UT64_MAX || op->jump != UT64_MAX) {
2259  if ((oplen * 8) > size - idx) {
2260  break;
2261  }
2262  ut32 opcode = rz_read_ble(data + idx, analysis->big_endian, oplen * 8);
2263  switch (oplen) {
2264  case 2:
2265  memcpy(ret + idx, "\xf0\x00", 2);
2266  break;
2267  case 4:
2268  if (analysis->bits == 64) {
2269  switch (op->id) {
2270  case ARM64_INS_LDP:
2271  case ARM64_INS_LDXP:
2272  case ARM64_INS_LDXR:
2273  case ARM64_INS_LDXRB:
2274  case ARM64_INS_LDXRH:
2275  case ARM64_INS_LDPSW:
2276  case ARM64_INS_LDNP:
2277  case ARM64_INS_LDTR:
2278  case ARM64_INS_LDTRB:
2279  case ARM64_INS_LDTRH:
2280  case ARM64_INS_LDTRSB:
2281  case ARM64_INS_LDTRSH:
2282  case ARM64_INS_LDTRSW:
2283  case ARM64_INS_LDUR:
2284  case ARM64_INS_LDURB:
2285  case ARM64_INS_LDURH:
2286  case ARM64_INS_LDURSB:
2287  case ARM64_INS_LDURSH:
2288  case ARM64_INS_LDURSW:
2289  case ARM64_INS_STP:
2290  case ARM64_INS_STNP:
2291  case ARM64_INS_STXR:
2292  case ARM64_INS_STXRB:
2293  case ARM64_INS_STXRH:
2294  rz_write_ble(ret + idx, 0xffffffff, analysis->big_endian, 32);
2295  break;
2296  case ARM64_INS_STRB:
2297  case ARM64_INS_STURB:
2298  case ARM64_INS_STURH:
2299  case ARM64_INS_STUR:
2300  case ARM64_INS_STR:
2301  case ARM64_INS_STTR:
2302  case ARM64_INS_STTRB:
2303  case ARM64_INS_STRH:
2304  case ARM64_INS_STTRH:
2305  case ARM64_INS_LDR:
2306  case ARM64_INS_LDRB:
2307  case ARM64_INS_LDRH:
2308  case ARM64_INS_LDRSB:
2309  case ARM64_INS_LDRSW:
2310  case ARM64_INS_LDRSH: {
2311  bool is_literal = (opcode & 0x38000000) == 0x18000000;
2312  if (is_literal) {
2313  rz_write_ble(ret + idx, 0xff000000, analysis->big_endian, 32);
2314  } else {
2315  rz_write_ble(ret + idx, 0xffffffff, analysis->big_endian, 32);
2316  }
2317  break;
2318  }
2319  case ARM64_INS_B:
2320  case ARM64_INS_BL:
2321  case ARM64_INS_CBZ:
2322  case ARM64_INS_CBNZ:
2323  if (op->type == RZ_ANALYSIS_OP_TYPE_CJMP) {
2324  rz_write_ble(ret + idx, 0xff00001f, analysis->big_endian, 32);
2325  } else {
2326  rz_write_ble(ret + idx, 0xfc000000, analysis->big_endian, 32);
2327  }
2328  break;
2329  case ARM64_INS_TBZ:
2330  case ARM64_INS_TBNZ:
2331  rz_write_ble(ret + idx, 0xfff8001f, analysis->big_endian, 32);
2332  break;
2333  case ARM64_INS_ADR:
2334  case ARM64_INS_ADRP:
2335  rz_write_ble(ret + idx, 0xff00001f, analysis->big_endian, 32);
2336  break;
2337  default:
2338  rz_write_ble(ret + idx, 0xfff00000, analysis->big_endian, 32);
2339  }
2340  } else {
2341  rz_write_ble(ret + idx, 0xfff00000, analysis->big_endian, 32);
2342  }
2343  break;
2344  }
2345  }
2346  idx += oplen;
2347  }
2348 
2349  analysis->bits = obits;
2350  rz_analysis_op_free(op);
2351 
2352  return ret;
2353 }
2354 
2355 static RzList *analysis_preludes(RzAnalysis *analysis) {
2356 #define KW(d, ds, m, ms) rz_list_append(l, rz_search_keyword_new((const ut8 *)d, ds, (const ut8 *)m, ms, NULL))
2357  RzList *l = rz_list_newf((RzListFree)rz_search_keyword_free);
2358  switch (analysis->bits) {
2359  case 16:
2360  KW("\x00\xb5", 2, "\x0f\xff", 2);
2361  KW("\x08\xb5", 2, "\x0f\xff", 2);
2362  break;
2363  case 32:
2364  KW("\x00\x00\x2d\xe9", 4, "\x0f\x0f\xff\xff", 4);
2365  break;
2366  case 64:
2367  KW("\xf0\x0f\x00\xf8", 4, "\xf0\x0f\x00\xff", 4);
2368  KW("\xf0\x00\x00\xd1", 4, "\xf0\x00\x00\xff", 4);
2369  KW("\xf0\x00\x00\xa9", 4, "\xf0\x00\x00\xff", 4);
2370  KW("\x7f\x23\x03\xd5\xff", 5, NULL, 0);
2371  break;
2372  default:
2373  rz_list_free(l);
2374  l = NULL;
2375  }
2376  return l;
2377 }
2378 
2379 static int address_bits(RzAnalysis *analysis, int bits) {
2380  // thumb still has 32bit addrs, all other cases use the default behavior (-1)
2381  return bits == 16 ? 32 : -1;
2382 }
2383 
2384 static bool init(void **user) {
2385  ArmCSContext *ctx = RZ_NEW0(ArmCSContext);
2386  if (!ctx) {
2387  return false;
2388  }
2389  rz_arm_it_context_init(&ctx->it);
2390  ctx->handle = 0;
2391  ctx->omode = -1;
2392  ctx->obits = 32;
2393  *user = ctx;
2394  return true;
2395 }
2396 
2397 static bool fini(void *user) {
2398  rz_return_val_if_fail(user, false);
2399  ArmCSContext *ctx = (ArmCSContext *)user;
2400  cs_close(&ctx->handle);
2401  rz_arm_it_context_fini(&ctx->it);
2402  free(ctx);
2403  return true;
2404 }
2405 
2406 static RzAnalysisILConfig *il_config(RzAnalysis *analysis) {
2407  if (analysis->bits == 64) {
2408  return rz_arm_cs_64_il_config(analysis->big_endian);
2409  }
2410  return rz_arm_cs_32_il_config(analysis->big_endian);
2411 }
2412 
2413 RzAnalysisPlugin rz_analysis_plugin_arm_cs = {
2414  .name = "arm",
2415  .desc = "Capstone ARM analyzer",
2416  .license = "BSD",
2417  .esil = true,
2418  .arch = "arm",
2419  .archinfo = archinfo,
2420  .get_reg_profile = get_reg_profile,
2421  .analysis_mask = analysis_mask,
2422  .preludes = analysis_preludes,
2423  .bits = 16 | 32 | 64,
2424  .address_bits = address_bits,
2425  .op = &analysis_op,
2426  .il_config = il_config,
2427  .init = &init,
2428  .fini = &fini,
2429 };
2430 
2431 #ifndef RZ_PLUGIN_INCORE
2432 RZ_API RzLibStruct rizin_plugin = {
2433  .type = RZ_LIB_TYPE_ANALYSIS,
2434  .data = &rz_analysis_plugin_arm_cs,
2435  .version = RZ_VERSION
2436 };
2437 #endif
len
size_t len
Definition: 6502dis.c:15
rz_analysis_value_new
RZ_API RzAnalysisValue * rz_analysis_value_new(void)
Definition: value.c:6
analysis_mask
static ut8 * analysis_mask(RzAnalysis *analysis, int size, const ut8 *data, ut64 at)
Definition: analysis_arm_cs.c:2232
cond_cs2r2
static int cond_cs2r2(int cc)
Definition: analysis_arm_cs.c:552
op_fillval
static void op_fillval(RzAnalysis *analysis, RzAnalysisOp *op, csh handle, cs_insn *insn, int bits)
Definition: analysis_arm_cs.c:1648
is_valid64
static bool is_valid64(arm64_reg reg)
Definition: analysis_arm_cs.c:1534
get_reg_profile
static char * get_reg_profile(RzAnalysis *analysis)
Definition: analysis_arm_cs.c:1822
opex64
static void opex64(RzStrBuf *buf, csh handle, cs_insn *insn)
Definition: analysis_arm_cs.c:416
il_config
static RzAnalysisILConfig * il_config(RzAnalysis *analysis)
Definition: analysis_arm_cs.c:2406
create_src_dst
static void create_src_dst(RzAnalysisOp *op)
Definition: analysis_arm_cs.c:1641
cc_name
static const char * cc_name(arm_cc cc)
Definition: analysis_arm_cs.c:132
cc_name64
static const char * cc_name64(arm64_cc cc)
Definition: analysis_arm_cs.c:304
opex
static void opex(RzStrBuf *buf, csh handle, cs_insn *insn)
Definition: analysis_arm_cs.c:167
ArmCSContext
struct arm_cs_context_t ArmCSContext
KW
#define KW(d, ds, m, ms)
extender_name
static const char * extender_name(arm64_extender extender)
Definition: analysis_arm_cs.c:339
rizin_plugin
RZ_API RzLibStruct rizin_plugin
Definition: analysis_arm_cs.c:2432
parse_reg_name
static int parse_reg_name(RzReg *reg, RzRegItem **reg_base, RzRegItem **reg_delta, csh handle, cs_insn *insn, int reg_num)
Definition: analysis_arm_cs.c:1512
anop64
static void anop64(ArmCSContext *ctx, RzAnalysisOp *op, cs_insn *insn)
Definition: analysis_arm_cs.c:576
analysis_op
static int analysis_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, RzAnalysisOpMask mask)
Definition: analysis_arm_cs.c:1739
set_src_dst
static void set_src_dst(RzAnalysisValue *val, RzReg *reg, csh *handle, cs_insn *insn, int x, int bits)
Definition: analysis_arm_cs.c:1595
reg_list
static char * reg_list[]
Definition: analysis_arm_cs.c:1538
shift_type_name
static const char * shift_type_name(arm_shifter type)
Definition: analysis_arm_cs.c:24
rz_analysis_plugin_arm_cs
RzAnalysisPlugin rz_analysis_plugin_arm_cs
Definition: analysis_arm_cs.c:2413
address_bits
static int address_bits(RzAnalysis *analysis, int bits)
Definition: analysis_arm_cs.c:2379
anop32
static void anop32(RzAnalysis *a, csh handle, RzAnalysisOp *op, cs_insn *insn, bool thumb, const ut8 *buf, int len)
Definition: analysis_arm_cs.c:1025
set_opdir
static void set_opdir(RzAnalysisOp *op)
Definition: analysis_arm_cs.c:1573
vas_name
static const char * vas_name(arm64_vas vas)
Definition: analysis_arm_cs.c:362
vector_data_type_name
static const char * vector_data_type_name(arm_vectordata_type type)
Definition: analysis_arm_cs.c:51
init
static bool init(void **user)
Definition: analysis_arm_cs.c:2384
archinfo
static int archinfo(RzAnalysis *analysis, int q)
Definition: analysis_arm_cs.c:2210
is_valid
static bool is_valid(arm_reg reg)
Definition: analysis_arm_cs.c:1508
parse_reg64_name
static int parse_reg64_name(RzReg *reg, RzRegItem **reg_base, RzRegItem **reg_delta, csh handle, cs_insn *insn, int reg_num)
Definition: analysis_arm_cs.c:1548
analysis_preludes
static RzList * analysis_preludes(RzAnalysis *analysis)
Definition: analysis_arm_cs.c:2355
patch_capstone_bugs
static void patch_capstone_bugs(cs_insn *insn, int bits, bool big_endian)
Definition: analysis_arm_cs.c:1719
fini
static bool fini(void *user)
Definition: analysis_arm_cs.c:2397
analysis_arm_hacks.inc
mask
#define mask()
Definition: analysis_h8300.c:39
i
lzma_index ** i
Definition: index.h:629
ISREG
#define ISREG(x)
Definition: arm_accessors32.h:21
INSOP
#define INSOP(x)
Definition: arm_accessors32.h:14
MEMDISP
#define MEMDISP(x)
Definition: arm_accessors32.h:19
IMM
#define IMM(x)
Definition: arm_accessors32.h:13
REGBASE
#define REGBASE(x)
Definition: arm_accessors32.h:15
ISIMM
#define ISIMM(x)
Definition: arm_accessors32.h:20
ISMEM
#define ISMEM(x)
Definition: arm_accessors32.h:22
REGID
#define REGID(x)
Definition: arm_accessors32.h:12
LSHIFT
#define LSHIFT(x)
Definition: arm_accessors32.h:28
IMM64
#define IMM64(x)
Definition: arm_accessors64.h:12
REGID64
#define REGID64(x)
Definition: arm_accessors64.h:15
REGBASE64
#define REGBASE64(x)
Definition: arm_accessors64.h:16
ISREG64
#define ISREG64(x)
Definition: arm_accessors64.h:21
MEMDISP64
#define MEMDISP64(x)
Definition: arm_accessors64.h:19
ISPREINDEX64
#define ISPREINDEX64()
Definition: arm_accessors64.h:32
ISIMM64
#define ISIMM64(x)
Definition: arm_accessors64.h:20
ISPOSTINDEX64
#define ISPOSTINDEX64()
Definition: arm_accessors64.h:33
INSOP64
#define INSOP64(x)
Definition: arm_accessors64.h:13
rz_arm_cs_analysis_op_32_esil
RZ_IPI int rz_arm_cs_analysis_op_32_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, csh *handle, cs_insn *insn, bool thumb)
Definition: arm_esil32.c:239
rz_arm_cs_64_il_config
RZ_IPI RzAnalysisILConfig * rz_arm_cs_64_il_config(bool big_endian)
Definition: arm_il64.c:2762
rz_arm_cs_32_il_config
RZ_IPI RzAnalysisILConfig * rz_arm_cs_32_il_config(bool big_endian)
Definition: arm_il32.c:2667
rz_arm_cs_64_il
RZ_IPI RzILOpEffect * rz_arm_cs_64_il(csh *handle, cs_insn *insn)
Definition: arm_il64.c:2316
rz_arm_cs_32_il
RZ_IPI RzILOpEffect * rz_arm_cs_32_il(csh *handle, cs_insn *insn, bool thumb)
Definition: arm_il32.c:2647
rz_arm_cs_analysis_op_64_esil
RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, csh *handle, cs_insn *insn)
Definition: arm_esil64.c:202
PC
#define PC(addr, is_thumb)
Definition: arm_il32.c:108
rz_arm_it_context_fini
RZ_API void rz_arm_it_context_fini(RzArmITContext *ctx)
Definition: arm_it.c:25
rz_arm_it_context_init
RZ_API void rz_arm_it_context_init(RzArmITContext *ctx)
Definition: arm_it.c:20
rz_arm_it_update_nonblock
RZ_API void rz_arm_it_update_nonblock(RzArmITContext *ctx, cs_insn *insn)
Definition: arm_it.c:70
rz_arm_it_apply_cond
RZ_API bool rz_arm_it_apply_cond(RzArmITContext *ctx, cs_insn *insn)
Definition: arm_it.c:87
rz_arm_it_update_block
RZ_API void rz_arm_it_update_block(RzArmITContext *ctx, cs_insn *insn)
Definition: arm_it.c:34
val
ut16 val
Definition: armass64_const.h:6
handle
static mcore_handle handle
Definition: asm_mcore.c:8
instructions
static const AvrInstruction instructions[]
Definition: assembler.c:880
bits
int bits(struct state *s, int need)
Definition: blast.c:72
in
const lzma_allocator const uint8_t * in
Definition: block.h:527
arm64_vess
arm64_vess
Vector element size specifier.
Definition: arm64.h:207
ARM64_VESS_B
@ ARM64_VESS_B
Definition: arm64.h:209
ARM64_VESS_D
@ ARM64_VESS_D
Definition: arm64.h:212
ARM64_VESS_INVALID
@ ARM64_VESS_INVALID
Definition: arm64.h:208
ARM64_VESS_H
@ ARM64_VESS_H
Definition: arm64.h:210
ARM64_VESS_S
@ ARM64_VESS_S
Definition: arm64.h:211
ARM64_OP_FP
@ ARM64_OP_FP
= CS_OP_FP (Floating-Point operand).
Definition: arm64.h:238
ARM64_OP_PSTATE
@ ARM64_OP_PSTATE
PState operand.
Definition: arm64.h:242
ARM64_OP_BARRIER
@ ARM64_OP_BARRIER
Memory barrier operand (ISB/DMB/DSB instructions).
Definition: arm64.h:245
ARM64_OP_REG
@ ARM64_OP_REG
= CS_OP_REG (Register operand).
Definition: arm64.h:235
ARM64_OP_PREFETCH
@ ARM64_OP_PREFETCH
Prefetch operand (PRFM).
Definition: arm64.h:244
ARM64_OP_MEM
@ ARM64_OP_MEM
= CS_OP_MEM (Memory operand).
Definition: arm64.h:237
ARM64_OP_SYS
@ ARM64_OP_SYS
SYS operand for IC/DC/AT/TLBI instructions.
Definition: arm64.h:243
ARM64_OP_REG_MRS
@ ARM64_OP_REG_MRS
MRS register operand.
Definition: arm64.h:240
ARM64_OP_CIMM
@ ARM64_OP_CIMM
C-Immediate.
Definition: arm64.h:239
ARM64_OP_IMM
@ ARM64_OP_IMM
= CS_OP_IMM (Immediate operand).
Definition: arm64.h:236
ARM64_OP_REG_MSR
@ ARM64_OP_REG_MSR
MSR register operand.
Definition: arm64.h:241
arm64_vas
arm64_vas
Vector arrangement specifier (for FloatingPoint/Advanced SIMD insn)
Definition: arm64.h:193
ARM64_VAS_INVALID
@ ARM64_VAS_INVALID
Definition: arm64.h:194
ARM64_VAS_8B
@ ARM64_VAS_8B
Definition: arm64.h:195
ARM64_VAS_8H
@ ARM64_VAS_8H
Definition: arm64.h:198
ARM64_VAS_1Q
@ ARM64_VAS_1Q
Definition: arm64.h:203
ARM64_VAS_4H
@ ARM64_VAS_4H
Definition: arm64.h:197
ARM64_VAS_2D
@ ARM64_VAS_2D
Definition: arm64.h:202
ARM64_VAS_2S
@ ARM64_VAS_2S
Definition: arm64.h:199
ARM64_VAS_1D
@ ARM64_VAS_1D
Definition: arm64.h:201
ARM64_VAS_16B
@ ARM64_VAS_16B
Definition: arm64.h:196
ARM64_VAS_4S
@ ARM64_VAS_4S
Definition: arm64.h:200
ARM64_PSTATE_DAIFSET
@ ARM64_PSTATE_DAIFSET
Definition: arm64.h:188
ARM64_PSTATE_DAIFCLR
@ ARM64_PSTATE_DAIFCLR
Definition: arm64.h:189
ARM64_PSTATE_SPSEL
@ ARM64_PSTATE_SPSEL
Definition: arm64.h:187
ARM64_SFT_LSL
@ ARM64_SFT_LSL
Definition: arm64.h:20
ARM64_SFT_LSR
@ ARM64_SFT_LSR
Definition: arm64.h:22
ARM64_SFT_ASR
@ ARM64_SFT_ASR
Definition: arm64.h:23
ARM64_SFT_ROR
@ ARM64_SFT_ROR
Definition: arm64.h:24
ARM64_SFT_MSL
@ ARM64_SFT_MSL
Definition: arm64.h:21
ARM64_SFT_INVALID
@ ARM64_SFT_INVALID
Definition: arm64.h:19
ARM64_GRP_CRC
@ ARM64_GRP_CRC
Definition: arm64.h:1155
ARM64_GRP_PRIVILEGE
@ ARM64_GRP_PRIVILEGE
= CS_GRP_PRIVILEGE
Definition: arm64.h:1148
ARM64_GRP_CRYPTO
@ ARM64_GRP_CRYPTO
Definition: arm64.h:1152
ARM64_GRP_FPARMV8
@ ARM64_GRP_FPARMV8
Definition: arm64.h:1153
ARM64_GRP_NEON
@ ARM64_GRP_NEON
Definition: arm64.h:1154
arm64_reg
arm64_reg
ARM64 registers.
Definition: arm64.h:347
ARM64_REG_SP
@ ARM64_REG_SP
Definition: arm64.h:353
ARM64_REG_LR
@ ARM64_REG_LR
Definition: arm64.h:618
ARM64_REG_INVALID
@ ARM64_REG_INVALID
Definition: arm64.h:348
ARM64_REG_X29
@ ARM64_REG_X29
Definition: arm64.h:350
arm64_extender
arm64_extender
ARM64 extender type.
Definition: arm64.h:28
ARM64_EXT_SXTW
@ ARM64_EXT_SXTW
Definition: arm64.h:36
ARM64_EXT_UXTB
@ ARM64_EXT_UXTB
Definition: arm64.h:30
ARM64_EXT_INVALID
@ ARM64_EXT_INVALID
Definition: arm64.h:29
ARM64_EXT_UXTW
@ ARM64_EXT_UXTW
Definition: arm64.h:32
ARM64_EXT_SXTH
@ ARM64_EXT_SXTH
Definition: arm64.h:35
ARM64_EXT_SXTB
@ ARM64_EXT_SXTB
Definition: arm64.h:34
ARM64_EXT_UXTX
@ ARM64_EXT_UXTX
Definition: arm64.h:33
ARM64_EXT_UXTH
@ ARM64_EXT_UXTH
Definition: arm64.h:31
ARM64_EXT_SXTX
@ ARM64_EXT_SXTX
Definition: arm64.h:37
ARM64_INS_BFI
@ ARM64_INS_BFI
Definition: arm64.h:1110
ARM64_INS_STNP
@ ARM64_INS_STNP
Definition: arm64.h:1000
ARM64_INS_AND
@ ARM64_INS_AND
Definition: arm64.h:687
ARM64_INS_NOP
@ ARM64_INS_NOP
Definition: arm64.h:1099
ARM64_INS_LDTRH
@ ARM64_INS_LDTRH
Definition: arm64.h:843
ARM64_INS_UXTW
@ ARM64_INS_UXTW
Definition: arm64.h:1126
ARM64_INS_LDURH
@ ARM64_INS_LDURH
Definition: arm64.h:851
ARM64_INS_CCMN
@ ARM64_INS_CCMN
Definition: arm64.h:701
ARM64_INS_TBNZ
@ ARM64_INS_TBNZ
Definition: arm64.h:1023
ARM64_INS_ORN
@ ARM64_INS_ORN
Definition: arm64.h:875
ARM64_INS_LDPSW
@ ARM64_INS_LDPSW
Definition: arm64.h:835
ARM64_INS_DSB
@ ARM64_INS_DSB
Definition: arm64.h:733
ARM64_INS_STUR
@ ARM64_INS_STUR
Definition: arm64.h:1009
ARM64_INS_LDRH
@ ARM64_INS_LDRH
Definition: arm64.h:838
ARM64_INS_ADC
@ ARM64_INS_ADC
Definition: arm64.h:675
ARM64_INS_ERET
@ ARM64_INS_ERET
Definition: arm64.h:737
ARM64_INS_SXTH
@ ARM64_INS_SXTH
Definition: arm64.h:1121
ARM64_INS_SVC
@ ARM64_INS_SVC
Definition: arm64.h:1019
ARM64_INS_DUP
@ ARM64_INS_DUP
Definition: arm64.h:734
ARM64_INS_HLT
@ ARM64_INS_HLT
Definition: arm64.h:812
ARM64_INS_STLXR
@ ARM64_INS_STLXR
Definition: arm64.h:999
ARM64_INS_CMN
@ ARM64_INS_CMN
Definition: arm64.h:1112
ARM64_INS_LDXP
@ ARM64_INS_LDXP
Definition: arm64.h:855
ARM64_INS_EON
@ ARM64_INS_EON
Definition: arm64.h:735
ARM64_INS_CSEL
@ ARM64_INS_CSEL
Definition: arm64.h:724
ARM64_INS_MOVI
@ ARM64_INS_MOVI
Definition: arm64.h:864
ARM64_INS_CCMP
@ ARM64_INS_CCMP
Definition: arm64.h:702
ARM64_INS_UMADDL
@ ARM64_INS_UMADDL
Definition: arm64.h:1046
ARM64_INS_ISB
@ ARM64_INS_ISB
Definition: arm64.h:816
ARM64_INS_RET
@ ARM64_INS_RET
Definition: arm64.h:885
ARM64_INS_TBZ
@ ARM64_INS_TBZ
Definition: arm64.h:1025
ARM64_INS_LDXRH
@ ARM64_INS_LDXRH
Definition: arm64.h:857
ARM64_INS_LDTRSB
@ ARM64_INS_LDTRSB
Definition: arm64.h:844
ARM64_INS_FMADD
@ ARM64_INS_FMADD
Definition: arm64.h:774
ARM64_INS_LDTR
@ ARM64_INS_LDTR
Definition: arm64.h:848
ARM64_INS_BRK
@ ARM64_INS_BRK
Definition: arm64.h:697
ARM64_INS_LDNP
@ ARM64_INS_LDNP
Definition: arm64.h:833
ARM64_INS_LDRSW
@ ARM64_INS_LDRSW
Definition: arm64.h:841
ARM64_INS_STXR
@ ARM64_INS_STXR
Definition: arm64.h:1014
ARM64_INS_STXRB
@ ARM64_INS_STXRB
Definition: arm64.h:1012
ARM64_INS_CINC
@ ARM64_INS_CINC
Definition: arm64.h:1116
ARM64_INS_MOVK
@ ARM64_INS_MOVK
Definition: arm64.h:865
ARM64_INS_EXT
@ ARM64_INS_EXT
Definition: arm64.h:739
ARM64_INS_MRS
@ ARM64_INS_MRS
Definition: arm64.h:868
ARM64_INS_MOVN
@ ARM64_INS_MOVN
Definition: arm64.h:866
ARM64_INS_STURH
@ ARM64_INS_STURH
Definition: arm64.h:1010
ARM64_INS_INS
@ ARM64_INS_INS
Definition: arm64.h:814
ARM64_INS_UMULL
@ ARM64_INS_UMULL
Definition: arm64.h:1061
ARM64_INS_SXTW
@ ARM64_INS_SXTW
Definition: arm64.h:1122
ARM64_INS_ROR
@ ARM64_INS_ROR
Definition: arm64.h:890
ARM64_INS_CSET
@ ARM64_INS_CSET
Definition: arm64.h:1115
ARM64_INS_UXTH
@ ARM64_INS_UXTH
Definition: arm64.h:1125
ARM64_INS_LDTRSW
@ ARM64_INS_LDTRSW
Definition: arm64.h:847
ARM64_INS_LDURB
@ ARM64_INS_LDURB
Definition: arm64.h:849
ARM64_INS_FDIV
@ ARM64_INS_FDIV
Definition: arm64.h:773
ARM64_INS_BFXIL
@ ARM64_INS_BFXIL
Definition: arm64.h:1111
ARM64_INS_LDURSB
@ ARM64_INS_LDURSB
Definition: arm64.h:852
ARM64_INS_STLXRH
@ ARM64_INS_STLXRH
Definition: arm64.h:998
ARM64_INS_LDUR
@ ARM64_INS_LDUR
Definition: arm64.h:850
ARM64_INS_REV64
@ ARM64_INS_REV64
Definition: arm64.h:888
ARM64_INS_XTN
@ ARM64_INS_XTN
Definition: arm64.h:1091
ARM64_INS_LDXRB
@ ARM64_INS_LDXRB
Definition: arm64.h:856
ARM64_INS_UBFX
@ ARM64_INS_UBFX
Definition: arm64.h:1109
ARM64_INS_ADR
@ ARM64_INS_ADR
Definition: arm64.h:681
ARM64_INS_DMB
@ ARM64_INS_DMB
Definition: arm64.h:731
ARM64_INS_SMULL
@ ARM64_INS_SMULL
Definition: arm64.h:947
ARM64_INS_SMADDL
@ ARM64_INS_SMADDL
Definition: arm64.h:931
ARM64_INS_MSUB
@ ARM64_INS_MSUB
Definition: arm64.h:870
ARM64_INS_LDTRB
@ ARM64_INS_LDTRB
Definition: arm64.h:842
ARM64_INS_ADRP
@ ARM64_INS_ADRP
Definition: arm64.h:682
ARM64_INS_LDRSB
@ ARM64_INS_LDRSB
Definition: arm64.h:839
ARM64_INS_STRH
@ ARM64_INS_STRH
Definition: arm64.h:1004
ARM64_INS_MSR
@ ARM64_INS_MSR
Definition: arm64.h:869
ARM64_INS_CBNZ
@ ARM64_INS_CBNZ
Definition: arm64.h:699
ARM64_INS_UBFM
@ ARM64_INS_UBFM
Definition: arm64.h:1041
ARM64_INS_STTRH
@ ARM64_INS_STTRH
Definition: arm64.h:1006
ARM64_INS_LSL
@ ARM64_INS_LSL
Definition: arm64.h:859
ARM64_INS_LDR
@ ARM64_INS_LDR
Definition: arm64.h:837
ARM64_INS_FCSEL
@ ARM64_INS_FCSEL
Definition: arm64.h:755
ARM64_INS_STTR
@ ARM64_INS_STTR
Definition: arm64.h:1007
ARM64_INS_FMOV
@ ARM64_INS_FMOV
Definition: arm64.h:789
ARM64_INS_SDIV
@ ARM64_INS_SDIV
Definition: arm64.h:912
ARM64_INS_UXTB
@ ARM64_INS_UXTB
Definition: arm64.h:1124
ARM64_INS_MADD
@ ARM64_INS_MADD
Definition: arm64.h:861
ARM64_INS_LDRB
@ ARM64_INS_LDRB
Definition: arm64.h:836
ARM64_INS_B
@ ARM64_INS_B
Definition: arm64.h:689
ARM64_INS_STR
@ ARM64_INS_STR
Definition: arm64.h:1003
ARM64_INS_DC
@ ARM64_INS_DC
Definition: arm64.h:1128
ARM64_INS_MOVZ
@ ARM64_INS_MOVZ
Definition: arm64.h:867
ARM64_INS_NEG
@ ARM64_INS_NEG
Definition: arm64.h:873
ARM64_INS_SXTB
@ ARM64_INS_SXTB
Definition: arm64.h:1120
ARM64_INS_SBFIZ
@ ARM64_INS_SBFIZ
Definition: arm64.h:1106
ARM64_INS_LDURSW
@ ARM64_INS_LDURSW
Definition: arm64.h:854
ARM64_INS_UDIV
@ ARM64_INS_UDIV
Definition: arm64.h:1043
ARM64_INS_ADD
@ ARM64_INS_ADD
Definition: arm64.h:679
ARM64_INS_SBFX
@ ARM64_INS_SBFX
Definition: arm64.h:1108
ARM64_INS_USHLL
@ ARM64_INS_USHLL
Definition: arm64.h:1079
ARM64_INS_SMOV
@ ARM64_INS_SMOV
Definition: arm64.h:943
ARM64_INS_MOV
@ ARM64_INS_MOV
Definition: arm64.h:715
ARM64_INS_LDRSH
@ ARM64_INS_LDRSH
Definition: arm64.h:840
ARM64_INS_UMOV
@ ARM64_INS_UMOV
Definition: arm64.h:1057
ARM64_INS_BR
@ ARM64_INS_BR
Definition: arm64.h:696
ARM64_INS_LSR
@ ARM64_INS_LSR
Definition: arm64.h:860
ARM64_INS_LDP
@ ARM64_INS_LDP
Definition: arm64.h:834
ARM64_INS_BL
@ ARM64_INS_BL
Definition: arm64.h:694
ARM64_INS_BIC
@ ARM64_INS_BIC
Definition: arm64.h:691
ARM64_INS_EOR
@ ARM64_INS_EOR
Definition: arm64.h:736
ARM64_INS_XTN2
@ ARM64_INS_XTN2
Definition: arm64.h:1090
ARM64_INS_CMP
@ ARM64_INS_CMP
Definition: arm64.h:1123
ARM64_INS_STXRH
@ ARM64_INS_STXRH
Definition: arm64.h:1013
ARM64_INS_SHL
@ ARM64_INS_SHL
Definition: arm64.h:926
ARM64_INS_MUL
@ ARM64_INS_MUL
Definition: arm64.h:871
ARM64_INS_STURB
@ ARM64_INS_STURB
Definition: arm64.h:1008
ARM64_INS_STTRB
@ ARM64_INS_STTRB
Definition: arm64.h:1005
ARM64_INS_FCMP
@ ARM64_INS_FCMP
Definition: arm64.h:753
ARM64_INS_LDURSH
@ ARM64_INS_LDURSH
Definition: arm64.h:853
ARM64_INS_CBZ
@ ARM64_INS_CBZ
Definition: arm64.h:700
ARM64_INS_ORR
@ ARM64_INS_ORR
Definition: arm64.h:876
ARM64_INS_LDTRSH
@ ARM64_INS_LDTRSH
Definition: arm64.h:846
ARM64_INS_BLR
@ ARM64_INS_BLR
Definition: arm64.h:695
ARM64_INS_STRB
@ ARM64_INS_STRB
Definition: arm64.h:1002
ARM64_INS_SUB
@ ARM64_INS_SUB
Definition: arm64.h:1017
ARM64_INS_TST
@ ARM64_INS_TST
Definition: arm64.h:1114
ARM64_INS_FMUL
@ ARM64_INS_FMUL
Definition: arm64.h:791
ARM64_INS_LDXR
@ ARM64_INS_LDXR
Definition: arm64.h:858
ARM64_INS_ASR
@ ARM64_INS_ASR
Definition: arm64.h:688
ARM64_INS_UBFIZ
@ ARM64_INS_UBFIZ
Definition: arm64.h:1107
ARM64_INS_STP
@ ARM64_INS_STP
Definition: arm64.h:1001
ARM64_INS_NEGS
@ ARM64_INS_NEGS
Definition: arm64.h:1132
ARM64_INS_IC
@ ARM64_INS_IC
Definition: arm64.h:1127
arm64_cc
arm64_cc
ARM64 condition code.
Definition: arm64.h:41
ARM64_CC_HS
@ ARM64_CC_HS
Unsigned higher or same: >, ==, or unordered.
Definition: arm64.h:45
ARM64_CC_NV
@ ARM64_CC_NV
Always (unconditional): Always (unconditional)
Definition: arm64.h:58
ARM64_CC_PL
@ ARM64_CC_PL
Plus, positive or zero: >, ==, or unordered.
Definition: arm64.h:48
ARM64_CC_EQ
@ ARM64_CC_EQ
Equal.
Definition: arm64.h:43
ARM64_CC_LT
@ ARM64_CC_LT
Less than: Less than, or unordered.
Definition: arm64.h:54
ARM64_CC_VC
@ ARM64_CC_VC
No overflow: Ordered.
Definition: arm64.h:50
ARM64_CC_LS
@ ARM64_CC_LS
Unsigned lower or same: Less than or equal.
Definition: arm64.h:52
ARM64_CC_GE
@ ARM64_CC_GE
Greater than or equal: Greater than or equal.
Definition: arm64.h:53
ARM64_CC_GT
@ ARM64_CC_GT
Signed greater than: Greater than.
Definition: arm64.h:55
ARM64_CC_NE
@ ARM64_CC_NE
Not equal: Not equal, or unordered.
Definition: arm64.h:44
ARM64_CC_AL
@ ARM64_CC_AL
Always (unconditional): Always (unconditional)
Definition: arm64.h:57
ARM64_CC_LO
@ ARM64_CC_LO
Unsigned lower or same: Less than.
Definition: arm64.h:46
ARM64_CC_VS
@ ARM64_CC_VS
Overflow: Unordered.
Definition: arm64.h:49
ARM64_CC_HI
@ ARM64_CC_HI
Unsigned higher: Greater than, or unordered.
Definition: arm64.h:51
ARM64_CC_LE
@ ARM64_CC_LE
Signed less than or equal: <, ==, or unordered.
Definition: arm64.h:56
ARM64_CC_MI
@ ARM64_CC_MI
Minus, negative: Less than.
Definition: arm64.h:47
ARM64_CC_INVALID
@ ARM64_CC_INVALID
Definition: arm64.h:42
ARM_INS_TBH
@ ARM_INS_TBH
Definition: arm.h:865
ARM_INS_ADR
@ ARM_INS_ADR
Definition: arm.h:448
ARM_INS_FLDMIAX
@ ARM_INS_FLDMIAX
Definition: arm.h:483
ARM_INS_SADD16
@ ARM_INS_SADD16
Definition: arm.h:564
ARM_INS_LDRSH
@ ARM_INS_LDRSH
Definition: arm.h:517
ARM_INS_STR
@ ARM_INS_STR
Definition: arm.h:659
ARM_INS_VMOV
@ ARM_INS_VMOV
Definition: arm.h:481
ARM_INS_LDRT
@ ARM_INS_LDRT
Definition: arm.h:519
ARM_INS_TBB
@ ARM_INS_TBB
Definition: arm.h:864
ARM_INS_BXJ
@ ARM_INS_BXJ
Definition: arm.h:461
ARM_INS_STRH
@ ARM_INS_STRH
Definition: arm.h:656
ARM_INS_ADC
@ ARM_INS_ADC
Definition: arm.h:446
ARM_INS_ORN
@ ARM_INS_ORN
Definition: arm.h:860
ARM_INS_UXTB16
@ ARM_INS_UXTB16
Definition: arm.h:705
ARM_INS_BX
@ ARM_INS_BX
Definition: arm.h:460
ARM_INS_LDRB
@ ARM_INS_LDRB
Definition: arm.h:507
ARM_INS_SUB
@ ARM_INS_SUB
Definition: arm.h:660
ARM_INS_STREXH
@ ARM_INS_STREXH
Definition: arm.h:655
ARM_INS_IT
@ ARM_INS_IT
Definition: arm.h:857
ARM_INS_ASR
@ ARM_INS_ASR
Definition: arm.h:853
ARM_INS_LDRHT
@ ARM_INS_LDRHT
Definition: arm.h:514
ARM_INS_UXTB
@ ARM_INS_UXTB
Definition: arm.h:704
ARM_INS_AND
@ ARM_INS_AND
Definition: arm.h:453
ARM_INS_SMULL
@ ARM_INS_SMULL
Definition: arm.h:618
ARM_INS_STRB
@ ARM_INS_STRB
Definition: arm.h:650
ARM_INS_LDRSBT
@ ARM_INS_LDRSBT
Definition: arm.h:516
ARM_INS_SSUB16
@ ARM_INS_SSUB16
Definition: arm.h:632
ARM_INS_TST
@ ARM_INS_TST
Definition: arm.h:672
ARM_INS_SXTH
@ ARM_INS_SXTH
Definition: arm.h:669
ARM_INS_PUSH
@ ARM_INS_PUSH
Definition: arm.h:869
ARM_INS_BKPT
@ ARM_INS_BKPT
Definition: arm.h:457
ARM_INS_MOVT
@ ARM_INS_MOVT
Definition: arm.h:528
ARM_INS_MOV
@ ARM_INS_MOV
Definition: arm.h:527
ARM_INS_PLD
@ ARM_INS_PLD
Definition: arm.h:542
ARM_INS_SADD8
@ ARM_INS_SADD8
Definition: arm.h:565
ARM_INS_UXTAH
@ ARM_INS_UXTAH
Definition: arm.h:703
ARM_INS_FLDMDBX
@ ARM_INS_FLDMDBX
Definition: arm.h:482
ARM_INS_LDRSB
@ ARM_INS_LDRSB
Definition: arm.h:515
ARM_INS_STREXD
@ ARM_INS_STREXD
Definition: arm.h:654
ARM_INS_LDRBT
@ ARM_INS_LDRBT
Definition: arm.h:506
ARM_INS_LDM
@ ARM_INS_LDM
Definition: arm.h:504
ARM_INS_SBFX
@ ARM_INS_SBFX
Definition: arm.h:568
ARM_INS_VDIV
@ ARM_INS_VDIV
Definition: arm.h:740
ARM_INS_STMDB
@ ARM_INS_STMDB
Definition: arm.h:646
ARM_INS_BFI
@ ARM_INS_BFI
Definition: arm.h:455
ARM_INS_MRS
@ ARM_INS_MRS
Definition: arm.h:534
ARM_INS_TRAP
@ ARM_INS_TRAP
Definition: arm.h:671
ARM_INS_UBFX
@ ARM_INS_UBFX
Definition: arm.h:676
ARM_INS_LSL
@ ARM_INS_LSL
Definition: arm.h:858
ARM_INS_LSR
@ ARM_INS_LSR
Definition: arm.h:859
ARM_INS_STRBT
@ ARM_INS_STRBT
Definition: arm.h:649
ARM_INS_UMULL
@ ARM_INS_UMULL
Definition: arm.h:687
ARM_INS_BIC
@ ARM_INS_BIC
Definition: arm.h:456
ARM_INS_VMOVL
@ ARM_INS_VMOVL
Definition: arm.h:765
ARM_INS_VQMOVUN
@ ARM_INS_VQMOVUN
Definition: arm.h:788
ARM_INS_VCMP
@ ARM_INS_VCMP
Definition: arm.h:730
ARM_INS_UDF
@ ARM_INS_UDF
Definition: arm.h:677
ARM_INS_MUL
@ ARM_INS_MUL
Definition: arm.h:536
ARM_INS_ADDW
@ ARM_INS_ADDW
Definition: arm.h:852
ARM_INS_LDRH
@ ARM_INS_LDRH
Definition: arm.h:513
ARM_INS_CBZ
@ ARM_INS_CBZ
Definition: arm.h:867
ARM_INS_LDREXD
@ ARM_INS_LDREXD
Definition: arm.h:511
ARM_INS_EOR
@ ARM_INS_EOR
Definition: arm.h:479
ARM_INS_VMUL
@ ARM_INS_VMUL
Definition: arm.h:768
ARM_INS_NOP
@ ARM_INS_NOP
Definition: arm.h:872
ARM_INS_LDMDA
@ ARM_INS_LDMDA
Definition: arm.h:502
ARM_INS_UDIV
@ ARM_INS_UDIV
Definition: arm.h:678
ARM_INS_STMDA
@ ARM_INS_STMDA
Definition: arm.h:645
ARM_INS_LDREX
@ ARM_INS_LDREX
Definition: arm.h:509
ARM_INS_ADD
@ ARM_INS_ADD
Definition: arm.h:447
ARM_INS_LDRSHT
@ ARM_INS_LDRSHT
Definition: arm.h:518
ARM_INS_POP
@ ARM_INS_POP
Definition: arm.h:868
ARM_INS_BLX
@ ARM_INS_BLX
Definition: arm.h:459
ARM_INS_STM
@ ARM_INS_STM
Definition: arm.h:647
ARM_INS_VQMOVN
@ ARM_INS_VQMOVN
Definition: arm.h:789
ARM_INS_LDMIB
@ ARM_INS_LDMIB
Definition: arm.h:505
ARM_INS_CMN
@ ARM_INS_CMN
Definition: arm.h:467
ARM_INS_VMOVN
@ ARM_INS_VMOVN
Definition: arm.h:766
ARM_INS_ROR
@ ARM_INS_ROR
Definition: arm.h:861
ARM_INS_LDR
@ ARM_INS_LDR
Definition: arm.h:520
ARM_INS_STRT
@ ARM_INS_STRT
Definition: arm.h:658
ARM_INS_STREXB
@ ARM_INS_STREXB
Definition: arm.h:653
ARM_INS_STRD
@ ARM_INS_STRD
Definition: arm.h:651
ARM_INS_CBNZ
@ ARM_INS_CBNZ
Definition: arm.h:866
ARM_INS_LDREXH
@ ARM_INS_LDREXH
Definition: arm.h:512
ARM_INS_SDIV
@ ARM_INS_SDIV
Definition: arm.h:569
ARM_INS_UXTAB
@ ARM_INS_UXTAB
Definition: arm.h:701
ARM_INS_SVC
@ ARM_INS_SVC
Definition: arm.h:661
ARM_INS_B
@ ARM_INS_B
Definition: arm.h:462
ARM_INS_UXTAB16
@ ARM_INS_UXTAB16
Definition: arm.h:702
ARM_INS_SUBW
@ ARM_INS_SUBW
Definition: arm.h:863
ARM_INS_BL
@ ARM_INS_BL
Definition: arm.h:458
ARM_INS_LDMDB
@ ARM_INS_LDMDB
Definition: arm.h:503
ARM_INS_STREX
@ ARM_INS_STREX
Definition: arm.h:652
ARM_INS_CMP
@ ARM_INS_CMP
Definition: arm.h:468
ARM_INS_UXTH
@ ARM_INS_UXTH
Definition: arm.h:706
ARM_INS_LDRD
@ ARM_INS_LDRD
Definition: arm.h:508
ARM_INS_MOVW
@ ARM_INS_MOVW
Definition: arm.h:529
ARM_INS_LDREXB
@ ARM_INS_LDREXB
Definition: arm.h:510
ARM_INS_STRHT
@ ARM_INS_STRHT
Definition: arm.h:657
ARM_INS_SSUB8
@ ARM_INS_SSUB8
Definition: arm.h:633
ARM_INS_RRX
@ ARM_INS_RRX
Definition: arm.h:862
ARM_INS_ORR
@ ARM_INS_ORR
Definition: arm.h:538
ARM_INS_MSR
@ ARM_INS_MSR
Definition: arm.h:535
ARM_INS_SXTB
@ ARM_INS_SXTB
Definition: arm.h:667
arm_shifter
arm_shifter
ARM shift type.
Definition: arm.h:18
ARM_SFT_ROR_REG
@ ARM_SFT_ROR_REG
shift with register
Definition: arm.h:28
ARM_SFT_ASR
@ ARM_SFT_ASR
shift with immediate const
Definition: arm.h:20
ARM_SFT_LSR_REG
@ ARM_SFT_LSR_REG
shift with register
Definition: arm.h:27
ARM_SFT_LSL_REG
@ ARM_SFT_LSL_REG
shift with register
Definition: arm.h:26
ARM_SFT_ROR
@ ARM_SFT_ROR
shift with immediate const
Definition: arm.h:23
ARM_SFT_LSL
@ ARM_SFT_LSL
shift with immediate const
Definition: arm.h:21
ARM_SFT_RRX_REG
@ ARM_SFT_RRX_REG
shift with register
Definition: arm.h:29
ARM_SFT_LSR
@ ARM_SFT_LSR
shift with immediate const
Definition: arm.h:22
ARM_SFT_RRX
@ ARM_SFT_RRX
shift with immediate const
Definition: arm.h:24
ARM_SFT_INVALID
@ ARM_SFT_INVALID
Definition: arm.h:19
ARM_SFT_ASR_REG
@ ARM_SFT_ASR_REG
shift with register
Definition: arm.h:25
ARM_SETEND_LE
@ ARM_SETEND_LE
LE operand.
Definition: arm.h:177
ARM_SETEND_BE
@ ARM_SETEND_BE
BE operand.
Definition: arm.h:176
ARM_MB_INVALID
@ ARM_MB_INVALID
Definition: arm.h:141
ARM_GRP_THUMB2DSP
@ ARM_GRP_THUMB2DSP
Definition: arm.h:904
ARM_GRP_FPARMV8
@ ARM_GRP_FPARMV8
Definition: arm.h:900
ARM_GRP_PRIVILEGE
@ ARM_GRP_PRIVILEGE
= CS_GRP_PRIVILEGE
Definition: arm.h:893
ARM_GRP_CRYPTO
@ ARM_GRP_CRYPTO
Definition: arm.h:897
ARM_GRP_CRC
@ ARM_GRP_CRC
Definition: arm.h:925
ARM_GRP_NEON
@ ARM_GRP_NEON
Definition: arm.h:902
ARM_GRP_VIRTUALIZATION
@ ARM_GRP_VIRTUALIZATION
Definition: arm.h:928
ARM_OP_IMM
@ ARM_OP_IMM
= CS_OP_IMM (Immediate operand).
Definition: arm.h:164
ARM_OP_REG
@ ARM_OP_REG
= CS_OP_REG (Register operand).
Definition: arm.h:163
ARM_OP_CIMM
@ ARM_OP_CIMM
C-Immediate (coprocessor registers)
Definition: arm.h:167
ARM_OP_SETEND
@ ARM_OP_SETEND
operand for SETEND instruction
Definition: arm.h:169
ARM_OP_PIMM
@ ARM_OP_PIMM
P-Immediate (coprocessor registers)
Definition: arm.h:168
ARM_OP_MEM
@ ARM_OP_MEM
= CS_OP_MEM (Memory operand).
Definition: arm.h:165
ARM_OP_FP
@ ARM_OP_FP
= CS_OP_FP (Floating-Point operand).
Definition: arm.h:166
ARM_OP_SYSREG
@ ARM_OP_SYSREG
MSR/MRS special register operand.
Definition: arm.h:170
arm_cc
arm_cc
ARM condition code.
Definition: arm.h:33
ARM_CC_GT
@ ARM_CC_GT
Greater than Greater than.
Definition: arm.h:47
ARM_CC_LE
@ ARM_CC_LE
Less than or equal <, ==, or unordered.
Definition: arm.h:48
ARM_CC_AL
@ ARM_CC_AL
Always (unconditional) Always (unconditional)
Definition: arm.h:49
ARM_CC_HI
@ ARM_CC_HI
Unsigned higher Greater than, or unordered.
Definition: arm.h:43
ARM_CC_VC
@ ARM_CC_VC
No overflow Not unordered.
Definition: arm.h:42
ARM_CC_LS
@ ARM_CC_LS
Unsigned lower or same Less than or equal.
Definition: arm.h:44
ARM_CC_GE
@ ARM_CC_GE
Greater than or equal Greater than or equal.
Definition: arm.h:45
ARM_CC_VS
@ ARM_CC_VS
Overflow Unordered.
Definition: arm.h:41
ARM_CC_PL
@ ARM_CC_PL
Plus, positive or zero >, ==, or unordered.
Definition: arm.h:40
ARM_CC_INVALID
@ ARM_CC_INVALID
Definition: arm.h:34
ARM_CC_NE
@ ARM_CC_NE
Not equal Not equal, or unordered.
Definition: arm.h:36
ARM_CC_LO
@ ARM_CC_LO
Carry clear Less than.
Definition: arm.h:38
ARM_CC_EQ
@ ARM_CC_EQ
Equal Equal.
Definition: arm.h:35
ARM_CC_LT
@ ARM_CC_LT
Less than Less than, or unordered.
Definition: arm.h:46
ARM_CC_HS
@ ARM_CC_HS
Carry set >, ==, or unordered.
Definition: arm.h:37
ARM_CC_MI
@ ARM_CC_MI
Minus, negative Less than.
Definition: arm.h:39
ARM_CPSFLAG_INVALID
@ ARM_CPSFLAG_INVALID
Definition: arm.h:188
arm_vectordata_type
arm_vectordata_type
Data type for elements of vector instructions.
Definition: arm.h:196
ARM_VECTORDATA_F64
@ ARM_VECTORDATA_F64
Definition: arm.h:222
ARM_VECTORDATA_U64
@ ARM_VECTORDATA_U64
Definition: arm.h:215
ARM_VECTORDATA_I64
@ ARM_VECTORDATA_I64
Definition: arm.h:203
ARM_VECTORDATA_S16F64
@ ARM_VECTORDATA_S16F64
Definition: arm.h:240
ARM_VECTORDATA_I32
@ ARM_VECTORDATA_I32
Definition: arm.h:202
ARM_VECTORDATA_P8
@ ARM_VECTORDATA_P8
Definition: arm.h:218
ARM_VECTORDATA_F32
@ ARM_VECTORDATA_F32
Definition: arm.h:221
ARM_VECTORDATA_S32F32
@ ARM_VECTORDATA_S32F32
Definition: arm.h:233
ARM_VECTORDATA_F64F32
@ ARM_VECTORDATA_F64F32
Definition: arm.h:229
ARM_VECTORDATA_S16
@ ARM_VECTORDATA_S16
Definition: arm.h:207
ARM_VECTORDATA_F32F16
@ ARM_VECTORDATA_F32F16
Definition: arm.h:227
ARM_VECTORDATA_F16F32
@ ARM_VECTORDATA_F16F32
Definition: arm.h:228
ARM_VECTORDATA_F64F16
@ ARM_VECTORDATA_F64F16
Definition: arm.h:226
ARM_VECTORDATA_U32
@ ARM_VECTORDATA_U32
Definition: arm.h:214
ARM_VECTORDATA_F64S16
@ ARM_VECTORDATA_F64S16
Definition: arm.h:237
ARM_VECTORDATA_S32
@ ARM_VECTORDATA_S32
Definition: arm.h:208
ARM_VECTORDATA_F32U32
@ ARM_VECTORDATA_F32U32
Definition: arm.h:236
ARM_VECTORDATA_U16
@ ARM_VECTORDATA_U16
Definition: arm.h:213
ARM_VECTORDATA_S8
@ ARM_VECTORDATA_S8
Definition: arm.h:206
ARM_VECTORDATA_U16F32
@ ARM_VECTORDATA_U16F32
Definition: arm.h:244
ARM_VECTORDATA_U16F64
@ ARM_VECTORDATA_U16F64
Definition: arm.h:243
ARM_VECTORDATA_U32F64
@ ARM_VECTORDATA_U32F64
Definition: arm.h:245
ARM_VECTORDATA_I16
@ ARM_VECTORDATA_I16
Definition: arm.h:201
ARM_VECTORDATA_INVALID
@ ARM_VECTORDATA_INVALID
Definition: arm.h:197
ARM_VECTORDATA_U32F32
@ ARM_VECTORDATA_U32F32
Definition: arm.h:234
ARM_VECTORDATA_F32U16
@ ARM_VECTORDATA_F32U16
Definition: arm.h:247
ARM_VECTORDATA_I8
@ ARM_VECTORDATA_I8
Definition: arm.h:200
ARM_VECTORDATA_S64
@ ARM_VECTORDATA_S64
Definition: arm.h:209
ARM_VECTORDATA_F16F64
@ ARM_VECTORDATA_F16F64
Definition: arm.h:225
ARM_VECTORDATA_F32S16
@ ARM_VECTORDATA_F32S16
Definition: arm.h:238
ARM_VECTORDATA_S32F64
@ ARM_VECTORDATA_S32F64
Definition: arm.h:242
ARM_VECTORDATA_F32F64
@ ARM_VECTORDATA_F32F64
Definition: arm.h:230
ARM_VECTORDATA_F32S32
@ ARM_VECTORDATA_F32S32
Definition: arm.h:235
ARM_VECTORDATA_S16F32
@ ARM_VECTORDATA_S16F32
Definition: arm.h:241
ARM_VECTORDATA_F64S32
@ ARM_VECTORDATA_F64S32
Definition: arm.h:239
ARM_VECTORDATA_F64U16
@ ARM_VECTORDATA_F64U16
Definition: arm.h:246
ARM_VECTORDATA_F64U32
@ ARM_VECTORDATA_F64U32
Definition: arm.h:248
ARM_VECTORDATA_U8
@ ARM_VECTORDATA_U8
Definition: arm.h:212
arm_reg
arm_reg
ARM registers.
Definition: arm.h:252
ARM_REG_INVALID
@ ARM_REG_INVALID
Definition: arm.h:253
ARM_REG_FP
@ ARM_REG_FP
Definition: arm.h:374
ARM_REG_LR
@ ARM_REG_LR
Definition: arm.h:263
ARM_REG_SP
@ ARM_REG_SP
Definition: arm.h:265
ARM_REG_PC
@ ARM_REG_PC
Definition: arm.h:264
ARM_REG_IP
@ ARM_REG_IP
Definition: arm.h:375
ARM_CPSMODE_INVALID
@ ARM_CPSMODE_INVALID
Definition: arm.h:181
CS_ARCH_ARM64
@ CS_ARCH_ARM64
ARM-64, also called AArch64.
Definition: capstone.h:76
CS_ARCH_ARM
@ CS_ARCH_ARM
ARM architecture (including Thumb, Thumb-2)
Definition: capstone.h:75
CS_MODE_MCLASS
@ CS_MODE_MCLASS
ARM's Cortex-M series.
Definition: capstone.h:109
CS_MODE_ARM
@ CS_MODE_ARM
32-bit ARM
Definition: capstone.h:104
CS_MODE_BIG_ENDIAN
@ CS_MODE_BIG_ENDIAN
big-endian mode
Definition: capstone.h:123
CS_MODE_THUMB
@ CS_MODE_THUMB
ARM's Thumb mode, including Thumb-2.
Definition: capstone.h:108
CS_MODE_LITTLE_ENDIAN
@ CS_MODE_LITTLE_ENDIAN
little-endian mode (default mode)
Definition: capstone.h:103
CS_OPT_DETAIL
@ CS_OPT_DETAIL
Break down instruction structure into details.
Definition: capstone.h:171
csh
size_t csh
Definition: capstone.h:71
CS_OPT_ON
@ CS_OPT_ON
Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA).
Definition: capstone.h:183
CS_AC_WRITE
@ CS_AC_WRITE
Operand write to memory or register.
Definition: capstone.h:205
value
static int value
Definition: cmd_api.c:93
RZ_API
#define RZ_API
Definition: core_plugin_example.c:36
NULL
#define NULL
Definition: cris-opc.c:27
cs_disasm
CAPSTONE_EXPORT size_t CAPSTONE_API cs_disasm(csh ud, const uint8_t *buffer, size_t size, uint64_t offset, size_t count, cs_insn **insn)
Definition: cs.c:798
cs_open
CAPSTONE_EXPORT cs_err CAPSTONE_API cs_open(cs_arch arch, cs_mode mode, csh *handle)
Definition: cs.c:453
cs_insn_group
CAPSTONE_EXPORT bool CAPSTONE_API cs_insn_group(csh ud, const cs_insn *insn, unsigned int group_id)
Definition: cs.c:1190
cs_free
CAPSTONE_EXPORT void CAPSTONE_API cs_free(cs_insn *insn, size_t count)
Definition: cs.c:1017
cs_reg_name
CAPSTONE_EXPORT const char *CAPSTONE_API cs_reg_name(csh ud, unsigned int reg)
Definition: cs.c:1154
cs_close
CAPSTONE_EXPORT cs_err CAPSTONE_API cs_close(csh *handle)
Definition: cs.c:501
cs_option
CAPSTONE_EXPORT cs_err CAPSTONE_API cs_option(csh ud, cs_opt_type type, size_t value)
Definition: cs.c:646
count
static static sync static getppid static getegid const char static filename char static len const char char static bufsiz static mask static vfork const void static prot static getpgrp const char static swapflags static arg static fd static protocol static who struct sockaddr static addrlen static backlog struct timeval struct timezone static tz const struct iovec static count static mode const void const struct sockaddr static tolen const char static pathname void count
Definition: sflib.h:98
length
static static sync static getppid static getegid const char static filename char static len const char char static bufsiz static mask static vfork const void static prot static getpgrp const char static swapflags static arg static fd static protocol static who struct sockaddr static addrlen static backlog struct timeval struct timezone static tz const struct iovec static count static mode const void const struct sockaddr static tolen const char static pathname void static offset struct stat static buf void long static basep static whence static length const void static len static semflg const void static shmflg const struct timespec struct timespec static rem const char static group const void length
Definition: sflib.h:133
ut32
uint32_t ut32
Definition: demangler_util.h:31
rz_analysis_hint_get
RZ_API RzAnalysisHint * rz_analysis_hint_get(RzAnalysis *a, ut64 addr)
Definition: hint.c:506
free
RZ_API void Ht_() free(HtName_(Ht) *ht)
Definition: ht_inc.c:130
ht_uu.h
size
voidpf void uLong size
Definition: ioapi.h:138
mode
const char int mode
Definition: ioapi.h:137
buf
voidpf void * buf
Definition: ioapi.h:138
rz_search_keyword_free
RZ_API void rz_search_keyword_free(RzSearchKeyword *kw)
Definition: keyword.c:49
reg
#define reg(n)
ut8
uint8_t ut8
Definition: lh5801.h:11
memset
return memset(p, 0, total)
p
void * p
Definition: libc.cpp:67
mem
void * mem
Definition: libc.cpp:91
memcpy
memcpy(mem, inblock.get(), min(CONTAINING_RECORD(inblock.get(), MEMBLOCK, data) ->size, size))
rz_list_newf
RZ_API RZ_OWN RzList * rz_list_newf(RzListFree f)
Returns a new initialized RzList pointer and sets the free method.
Definition: list.c:248
rz_list_free
RZ_API void rz_list_free(RZ_NONNULL RzList *list)
Empties the list and frees the list pointer.
Definition: list.c:137
malloc
void * malloc(size_t size)
Definition: malloc.c:123
strdup
return strdup("=SP r13\n" "=LR r14\n" "=PC r15\n" "=A0 r0\n" "=A1 r1\n" "=A2 r2\n" "=A3 r3\n" "=ZF zf\n" "=SF nf\n" "=OF vf\n" "=CF cf\n" "=SN or0\n" "gpr lr .32 56 0\n" "gpr pc .32 60 0\n" "gpr cpsr .32 64 0 ____tfiae_________________qvczn\n" "gpr or0 .32 68 0\n" "gpr tf .1 64.5 0 thumb\n" "gpr ef .1 64.9 0 endian\n" "gpr jf .1 64.24 0 java\n" "gpr qf .1 64.27 0 sticky_overflow\n" "gpr vf .1 64.28 0 overflow\n" "gpr cf .1 64.29 0 carry\n" "gpr zf .1 64.30 0 zero\n" "gpr nf .1 64.31 0 negative\n" "gpr itc .4 64.10 0 if_then_count\n" "gpr gef .4 64.16 0 great_or_equal\n" "gpr r0 .32 0 0\n" "gpr r1 .32 4 0\n" "gpr r2 .32 8 0\n" "gpr r3 .32 12 0\n" "gpr r4 .32 16 0\n" "gpr r5 .32 20 0\n" "gpr r6 .32 24 0\n" "gpr r7 .32 28 0\n" "gpr r8 .32 32 0\n" "gpr r9 .32 36 0\n" "gpr r10 .32 40 0\n" "gpr r11 .32 44 0\n" "gpr r12 .32 48 0\n" "gpr r13 .32 52 0\n" "gpr r14 .32 56 0\n" "gpr r15 .32 60 0\n" "gpr r16 .32 64 0\n" "gpr r17 .32 68 0\n")
x
int x
Definition: mipsasm.c:20
n
int n
Definition: mipsasm.c:19
type
int type
Definition: mipsasm.c:17
capstone.CS_ERR_OK
int CS_ERR_OK
Definition: __init__.py:235
setup.provides
provides
Definition: setup.py:253
setup.idx
int idx
Definition: setup.py:197
rz_analysis_op_free
RZ_API void rz_analysis_op_free(void *op)
Definition: op.c:61
rz_analysis_optype_to_string
RZ_API const char * rz_analysis_optype_to_string(int type)
Definition: op.c:310
rz_analysis_op_new
RZ_API RzAnalysisOp * rz_analysis_op_new(void)
Definition: op.c:9
rz_reg_get
RZ_API RzRegItem * rz_reg_get(RzReg *reg, const char *name, int type)
Definition: reg.c:344
rz_analysis.h
RZ_ANALYSIS_ARCHINFO_DATA_ALIGN
#define RZ_ANALYSIS_ARCHINFO_DATA_ALIGN
Definition: rz_analysis.h:101
RZ_ANALYSIS_ARCHINFO_ALIGN
#define RZ_ANALYSIS_ARCHINFO_ALIGN
Definition: rz_analysis.h:100
RZ_ANALYSIS_STACK_RESET
@ RZ_ANALYSIS_STACK_RESET
Definition: rz_analysis.h:460
RZ_ANALYSIS_STACK_SET
@ RZ_ANALYSIS_STACK_SET
Definition: rz_analysis.h:459
RZ_ANALYSIS_STACK_GET
@ RZ_ANALYSIS_STACK_GET
Definition: rz_analysis.h:458
RZ_ANALYSIS_STACK_INC
@ RZ_ANALYSIS_STACK_INC
Definition: rz_analysis.h:457
RZ_ANALYSIS_VAL_IMM
@ RZ_ANALYSIS_VAL_IMM
Definition: rz_analysis.h:770
RZ_ANALYSIS_VAL_REG
@ RZ_ANALYSIS_VAL_REG
Definition: rz_analysis.h:768
RZ_ANALYSIS_VAL_MEM
@ RZ_ANALYSIS_VAL_MEM
Definition: rz_analysis.h:769
RZ_ANALYSIS_OP_FAMILY_FPU
@ RZ_ANALYSIS_OP_FAMILY_FPU
Definition: rz_analysis.h:313
RZ_ANALYSIS_OP_FAMILY_THREAD
@ RZ_ANALYSIS_OP_FAMILY_THREAD
Definition: rz_analysis.h:318
RZ_ANALYSIS_OP_FAMILY_CRYPTO
@ RZ_ANALYSIS_OP_FAMILY_CRYPTO
Definition: rz_analysis.h:317
RZ_ANALYSIS_OP_FAMILY_PRIV
@ RZ_ANALYSIS_OP_FAMILY_PRIV
Definition: rz_analysis.h:316
RZ_ANALYSIS_OP_FAMILY_CPU
@ RZ_ANALYSIS_OP_FAMILY_CPU
Definition: rz_analysis.h:312
RZ_ANALYSIS_OP_FAMILY_MMX
@ RZ_ANALYSIS_OP_FAMILY_MMX
Definition: rz_analysis.h:314
RZ_ANALYSIS_OP_FAMILY_VIRT
@ RZ_ANALYSIS_OP_FAMILY_VIRT
Definition: rz_analysis.h:319
RZ_ANALYSIS_OP_FAMILY_SECURITY
@ RZ_ANALYSIS_OP_FAMILY_SECURITY
Definition: rz_analysis.h:320
RZ_ANALYSIS_ARCHINFO_MAX_OP_SIZE
#define RZ_ANALYSIS_ARCHINFO_MAX_OP_SIZE
Definition: rz_analysis.h:99
RZ_ANALYSIS_OP_DIR_READ
@ RZ_ANALYSIS_OP_DIR_READ
Definition: rz_analysis.h:790
RZ_ANALYSIS_OP_DIR_EXEC
@ RZ_ANALYSIS_OP_DIR_EXEC
Definition: rz_analysis.h:792
RZ_ANALYSIS_OP_DIR_WRITE
@ RZ_ANALYSIS_OP_DIR_WRITE
Definition: rz_analysis.h:791
RZ_ANALYSIS_OP_DIR_REF
@ RZ_ANALYSIS_OP_DIR_REF
Definition: rz_analysis.h:793
RzAnalysisOpMask
RzAnalysisOpMask
Definition: rz_analysis.h:439
RZ_ANALYSIS_OP_MASK_DISASM
@ RZ_ANALYSIS_OP_MASK_DISASM
Definition: rz_analysis.h:445
RZ_ANALYSIS_OP_MASK_BASIC
@ RZ_ANALYSIS_OP_MASK_BASIC
Definition: rz_analysis.h:440
RZ_ANALYSIS_OP_MASK_VAL
@ RZ_ANALYSIS_OP_MASK_VAL
Definition: rz_analysis.h:442
RZ_ANALYSIS_OP_MASK_OPEX
@ RZ_ANALYSIS_OP_MASK_OPEX
Definition: rz_analysis.h:444
RZ_ANALYSIS_OP_MASK_ESIL
@ RZ_ANALYSIS_OP_MASK_ESIL
Definition: rz_analysis.h:441
RZ_ANALYSIS_OP_MASK_IL
@ RZ_ANALYSIS_OP_MASK_IL
Definition: rz_analysis.h:446
RZ_ANALYSIS_OP_TYPE_MASK
#define RZ_ANALYSIS_OP_TYPE_MASK
Definition: rz_analysis.h:358
RZ_ANALYSIS_ARCHINFO_MIN_OP_SIZE
#define RZ_ANALYSIS_ARCHINFO_MIN_OP_SIZE
Definition: rz_analysis.h:98
RZ_ANALYSIS_OP_TYPE_CMP
@ RZ_ANALYSIS_OP_TYPE_CMP
Definition: rz_analysis.h:399
RZ_ANALYSIS_OP_TYPE_SUB
@ RZ_ANALYSIS_OP_TYPE_SUB
Definition: rz_analysis.h:402
RZ_ANALYSIS_OP_TYPE_LOAD
@ RZ_ANALYSIS_OP_TYPE_LOAD
Definition: rz_analysis.h:416
RZ_ANALYSIS_OP_TYPE_MUL
@ RZ_ANALYSIS_OP_TYPE_MUL
Definition: rz_analysis.h:404
RZ_ANALYSIS_OP_TYPE_ROL
@ RZ_ANALYSIS_OP_TYPE_ROL
Definition: rz_analysis.h:420
RZ_ANALYSIS_OP_TYPE_JMP
@ RZ_ANALYSIS_OP_TYPE_JMP
Definition: rz_analysis.h:368
RZ_ANALYSIS_OP_TYPE_AND
@ RZ_ANALYSIS_OP_TYPE_AND
Definition: rz_analysis.h:411
RZ_ANALYSIS_OP_TYPE_SAL
@ RZ_ANALYSIS_OP_TYPE_SAL
Definition: rz_analysis.h:408
RZ_ANALYSIS_OP_TYPE_SYNC
@ RZ_ANALYSIS_OP_TYPE_SYNC
Definition: rz_analysis.h:431
RZ_ANALYSIS_OP_TYPE_UJMP
@ RZ_ANALYSIS_OP_TYPE_UJMP
Definition: rz_analysis.h:369
RZ_ANALYSIS_OP_TYPE_NOR
@ RZ_ANALYSIS_OP_TYPE_NOR
Definition: rz_analysis.h:413
RZ_ANALYSIS_OP_TYPE_ROR
@ RZ_ANALYSIS_OP_TYPE_ROR
Definition: rz_analysis.h:419
RZ_ANALYSIS_OP_TYPE_SWI
@ RZ_ANALYSIS_OP_TYPE_SWI
Definition: rz_analysis.h:393
RZ_ANALYSIS_OP_TYPE_SAR
@ RZ_ANALYSIS_OP_TYPE_SAR
Definition: rz_analysis.h:409
RZ_ANALYSIS_OP_TYPE_CMOV
@ RZ_ANALYSIS_OP_TYPE_CMOV
Definition: rz_analysis.h:391
RZ_ANALYSIS_OP_TYPE_TRAP
@ RZ_ANALYSIS_OP_TYPE_TRAP
Definition: rz_analysis.h:392
RZ_ANALYSIS_OP_TYPE_CALL
@ RZ_ANALYSIS_OP_TYPE_CALL
Definition: rz_analysis.h:378
RZ_ANALYSIS_OP_TYPE_ADD
@ RZ_ANALYSIS_OP_TYPE_ADD
Definition: rz_analysis.h:401
RZ_ANALYSIS_OP_TYPE_OR
@ RZ_ANALYSIS_OP_TYPE_OR
Definition: rz_analysis.h:410
RZ_ANALYSIS_OP_TYPE_STORE
@ RZ_ANALYSIS_OP_TYPE_STORE
Definition: rz_analysis.h:415
RZ_ANALYSIS_OP_TYPE_CRET
@ RZ_ANALYSIS_OP_TYPE_CRET
Definition: rz_analysis.h:386
RZ_ANALYSIS_OP_TYPE_PUSH
@ RZ_ANALYSIS_OP_TYPE_PUSH
Definition: rz_analysis.h:397
RZ_ANALYSIS_OP_TYPE_SHR
@ RZ_ANALYSIS_OP_TYPE_SHR
Definition: rz_analysis.h:406
RZ_ANALYSIS_OP_TYPE_POP
@ RZ_ANALYSIS_OP_TYPE_POP
Definition: rz_analysis.h:398
RZ_ANALYSIS_OP_TYPE_RJMP
@ RZ_ANALYSIS_OP_TYPE_RJMP
Definition: rz_analysis.h:370
RZ_ANALYSIS_OP_TYPE_CJMP
@ RZ_ANALYSIS_OP_TYPE_CJMP
Definition: rz_analysis.h:373
RZ_ANALYSIS_OP_TYPE_DIV
@ RZ_ANALYSIS_OP_TYPE_DIV
Definition: rz_analysis.h:405
RZ_ANALYSIS_OP_TYPE_CAST
@ RZ_ANALYSIS_OP_TYPE_CAST
Definition: rz_analysis.h:426
RZ_ANALYSIS_OP_TYPE_UCJMP
@ RZ_ANALYSIS_OP_TYPE_UCJMP
Definition: rz_analysis.h:377
RZ_ANALYSIS_OP_TYPE_MOV
@ RZ_ANALYSIS_OP_TYPE_MOV
Definition: rz_analysis.h:390
RZ_ANALYSIS_OP_TYPE_SHL
@ RZ_ANALYSIS_OP_TYPE_SHL
Definition: rz_analysis.h:407
RZ_ANALYSIS_OP_TYPE_ILL
@ RZ_ANALYSIS_OP_TYPE_ILL
Definition: rz_analysis.h:387
RZ_ANALYSIS_OP_TYPE_UCALL
@ RZ_ANALYSIS_OP_TYPE_UCALL
Definition: rz_analysis.h:379
RZ_ANALYSIS_OP_TYPE_NOT
@ RZ_ANALYSIS_OP_TYPE_NOT
Definition: rz_analysis.h:414
RZ_ANALYSIS_OP_TYPE_RET
@ RZ_ANALYSIS_OP_TYPE_RET
Definition: rz_analysis.h:385
RZ_ANALYSIS_OP_TYPE_NOP
@ RZ_ANALYSIS_OP_TYPE_NOP
Definition: rz_analysis.h:389
RZ_ANALYSIS_OP_TYPE_LEA
@ RZ_ANALYSIS_OP_TYPE_LEA
Definition: rz_analysis.h:417
RZ_ANALYSIS_OP_TYPE_RCALL
@ RZ_ANALYSIS_OP_TYPE_RCALL
Definition: rz_analysis.h:380
RZ_ANALYSIS_OP_TYPE_XOR
@ RZ_ANALYSIS_OP_TYPE_XOR
Definition: rz_analysis.h:412
rz_assert.h
rz_return_val_if_fail
#define rz_return_val_if_fail(expr, val)
Definition: rz_assert.h:108
rz_write_ble
static void rz_write_ble(void *dst, ut64 val, bool big_endian, int size)
Definition: rz_endian.h:548
rz_read_ble32
static ut32 rz_read_ble32(const void *src, bool big_endian)
Definition: rz_endian.h:497
rz_read_ble
static ut64 rz_read_ble(const void *src, bool big_endian, int size)
Definition: rz_endian.h:517
rz_lib.h
RZ_LIB_TYPE_ANALYSIS
@ RZ_LIB_TYPE_ANALYSIS
Definition: rz_lib.h:73
RzListFree
void(* RzListFree)(void *ptr)
Definition: rz_list.h:11
RZ_LOG_DEBUG
#define RZ_LOG_DEBUG(fmtstr,...)
Definition: rz_log.h:49
pj_ko
RZ_API PJ * pj_ko(PJ *j, const char *k)
Definition: pj.c:156
pj_ka
RZ_API PJ * pj_ka(PJ *j, const char *k)
Definition: pj.c:163
pj_new
RZ_API PJ * pj_new(void)
Definition: pj.c:25
pj_kb
RZ_API PJ * pj_kb(PJ *j, const char *k, bool v)
Definition: pj.c:177
pj_ki
RZ_API PJ * pj_ki(PJ *j, const char *k, int d)
Definition: pj.c:149
pj_end
RZ_API PJ * pj_end(PJ *j)
Definition: pj.c:87
pj_string
RZ_API const char * pj_string(PJ *pj)
Definition: pj.c:57
pj_free
RZ_API void pj_free(PJ *j)
Definition: pj.c:34
pj_o
RZ_API PJ * pj_o(PJ *j)
Definition: pj.c:75
pj_ks
RZ_API PJ * pj_ks(PJ *j, const char *k, const char *v)
Definition: pj.c:170
pj_kn
RZ_API PJ * pj_kn(PJ *j, const char *k, ut64 n)
Definition: pj.c:121
pj_kd
RZ_API PJ * pj_kd(PJ *j, const char *k, double d)
Definition: pj.c:136
pj_kN
RZ_API PJ * pj_kN(PJ *j, const char *k, st64 n)
Definition: pj.c:128
RZ_REG_TYPE_ANY
@ RZ_REG_TYPE_ANY
Definition: rz_reg.h:35
rz_str_newf
RZ_API char * rz_str_newf(const char *fmt,...) RZ_PRINTF_CHECK(1
rz_str_get_null
static const char * rz_str_get_null(const char *str)
Definition: rz_str.h:190
rz_strbuf_append
RZ_API bool rz_strbuf_append(RzStrBuf *sb, const char *s)
Definition: strbuf.c:222
rz_strbuf_init
RZ_API void rz_strbuf_init(RzStrBuf *sb)
Definition: strbuf.c:33
RzTypeCond
RzTypeCond
Type Conditions.
Definition: rz_type.h:182
RZ_TYPE_COND_LO
@ RZ_TYPE_COND_LO
Carry clear Less than.
Definition: rz_type.h:192
RZ_TYPE_COND_VS
@ RZ_TYPE_COND_VS
Overflow Unordered.
Definition: rz_type.h:195
RZ_TYPE_COND_LE
@ RZ_TYPE_COND_LE
Less or equal.
Definition: rz_type.h:188
RZ_TYPE_COND_GE
@ RZ_TYPE_COND_GE
Greater or equal.
Definition: rz_type.h:186
RZ_TYPE_COND_VC
@ RZ_TYPE_COND_VC
No overflow Not unordered.
Definition: rz_type.h:196
RZ_TYPE_COND_LS
@ RZ_TYPE_COND_LS
Unsigned lower or same Less than or equal.
Definition: rz_type.h:198
RZ_TYPE_COND_NV
@ RZ_TYPE_COND_NV
Never executed must be a nop? :D.
Definition: rz_type.h:190
RZ_TYPE_COND_EQ
@ RZ_TYPE_COND_EQ
Equal.
Definition: rz_type.h:184
RZ_TYPE_COND_HS
@ RZ_TYPE_COND_HS
Carry set >, ==, or unordered.
Definition: rz_type.h:191
RZ_TYPE_COND_NE
@ RZ_TYPE_COND_NE
Not equal.
Definition: rz_type.h:185
RZ_TYPE_COND_AL
@ RZ_TYPE_COND_AL
Always executed (no condition)
Definition: rz_type.h:183
RZ_TYPE_COND_MI
@ RZ_TYPE_COND_MI
Minus, negative Less than.
Definition: rz_type.h:193
RZ_TYPE_COND_HI
@ RZ_TYPE_COND_HI
Unsigned higher Greater than, or unordered.
Definition: rz_type.h:197
RZ_TYPE_COND_GT
@ RZ_TYPE_COND_GT
Greater than.
Definition: rz_type.h:187
RZ_TYPE_COND_PL
@ RZ_TYPE_COND_PL
Plus, positive or zero >, ==, or unordered.
Definition: rz_type.h:194
RZ_TYPE_COND_LT
@ RZ_TYPE_COND_LT
Less than.
Definition: rz_type.h:189
RZ_NEW0
#define RZ_NEW0(x)
Definition: rz_types.h:284
PFMT64x
#define PFMT64x
Definition: rz_types.h:393
UT32_MAX
#define UT32_MAX
Definition: rz_types_base.h:99
UT64_MAX
#define UT64_MAX
Definition: rz_types_base.h:86
RZ_VERSION
#define RZ_VERSION
Definition: rz_version.h:8
from
static struct sockaddr static addrlen static backlog const void static flags void struct sockaddr from
Definition: sfsocketcall.h:123
to
static struct sockaddr static addrlen static backlog const void static flags void struct sockaddr socklen_t static fromlen const void const struct sockaddr to
Definition: sfsocketcall.h:125
int
static int
Definition: sfsocketcall.h:114
d
#define d(i)
Definition: sha256.c:44
a
#define a(i)
Definition: sha256.c:41
arm64_op_mem::base
arm64_reg base
base register
Definition: arm64.h:624
arm64_op_mem::index
arm64_reg index
index register
Definition: arm64.h:625
arm64_op_mem::disp
int32_t disp
displacement/offset value
Definition: arm64.h:626
arm_cs_context_t
Definition: analysis_arm_cs.c:17
arm_cs_context_t::handle
csh handle
Definition: analysis_arm_cs.c:19
arm_cs_context_t::omode
int omode
Definition: analysis_arm_cs.c:20
arm_cs_context_t::it
RzArmITContext it
Definition: analysis_arm_cs.c:18
arm_cs_context_t::obits
int obits
Definition: analysis_arm_cs.c:21
arm_op_mem::scale
int scale
scale for index register (can be 1, or -1)
Definition: arm.h:383
arm_op_mem::base
arm_reg base
base register
Definition: arm.h:381
arm_op_mem::disp
int disp
Definition: arm.h:384
arm_op_mem::lshift
int lshift
Definition: arm.h:387
arm_op_mem::index
arm_reg index
index register
Definition: arm.h:382
cs_arm64_op
Instruction operand.
Definition: arm64.h:630
cs_arm64_op::reg
arm64_reg reg
register value for REG operand
Definition: arm64.h:641
cs_arm64_op::mem
arm64_op_mem mem
base/index/scale/disp value for MEM operand
Definition: arm64.h:644
cs_arm64_op::type
arm64_shifter type
shifter type of this operand
Definition: arm64.h:635
cs_arm64_op::access
uint8_t access
Definition: arm64.h:654
cs_arm64_op::imm
int64_t imm
immediate value, or index for C-IMM or IMM operand
Definition: arm64.h:642
cs_arm64
Instruction structure.
Definition: arm64.h:658
cs_arm_op
Instruction operand.
Definition: arm.h:391
cs_arm_op::type
arm_shifter type
Definition: arm.h:395
cs_arm_op::mem
arm_op_mem mem
base/index/scale/disp value for MEM operand
Definition: arm.h:405
cs_arm_op::imm
int32_t imm
immediate value for C-IMM, P-IMM or IMM operand
Definition: arm.h:403
cs_arm_op::access
uint8_t access
Definition: arm.h:417
cs_arm_op::reg
int reg
register value for REG/SYSREG operand
Definition: arm.h:402
cs_arm
Instruction structure.
Definition: arm.h:424
pj_t
Definition: rz_pj.h:12
rz_analysis_hint_t
Definition: rz_analysis.h:669
rz_analysis_hint_t::bits
int bits
Definition: rz_analysis.h:683
rz_analysis_il_config_t
Description of the global context of an RzAnalysisILVM.
Definition: rz_analysis.h:1134
rz_analysis_op_t
Definition: rz_analysis.h:811
rz_analysis_plugin_t
Definition: rz_analysis.h:1233
rz_analysis_plugin_t::version
const char * version
Definition: rz_analysis.h:1239
rz_analysis_plugin_t::name
const char * name
Definition: rz_analysis.h:1234
rz_analysis_t
Definition: rz_analysis.h:553
rz_analysis_t::big_endian
int big_endian
Definition: rz_analysis.h:558
rz_analysis_t::os
char * os
Definition: rz_analysis.h:555
rz_analysis_t::bits
int bits
Definition: rz_analysis.h:556
rz_analysis_t::reg
RzReg * reg
Definition: rz_analysis.h:568
rz_analysis_value_t
Definition: rz_analysis.h:774
rz_arm_it_context_t
Definition: arm_it.h:17
rz_lib_struct_t
Definition: rz_lib.h:57
rz_lib_struct_t::type
int type
Definition: rz_lib.h:58
rz_list_t
Definition: rz_list.h:18
rz_reg_item_t
Definition: rz_reg.h:117
rz_reg_item_t::name
char * name
Definition: rz_reg.h:118
rz_reg_t
Definition: rz_reg.h:144
state
Definition: dis.h:43
op
Definition: dis.c:32
delta
static st64 delta
Definition: vmenus.c:2425
ut64
ut64(WINAPI *w32_GetEnabledXStateFeatures)()
addr
static int addr
Definition: z80asm.c:58