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#define | RVC_JUMP_BITS 11 |
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#define | RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN) |
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#define | RVC_BRANCH_BITS 8 |
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#define | RVC_BRANCH_REACH ((1ULL << RVC_BRANCH_BITS) * RISCV_BRANCH_ALIGN) |
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#define | RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1)) |
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#define | RV_IMM_SIGN(x) (-(((x) >> 31) & 1)) |
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#define | EXTRACT_ITYPE_IMM(x) (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12)) |
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#define | EXTRACT_STYPE_IMM(x) (RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12)) |
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#define | EXTRACT_SBTYPE_IMM(x) ((RV_X(x, 8, 4) << 1) | (RV_X(x, 25, 6) << 5) | (RV_X(x, 7, 1) << 11) | (RV_IMM_SIGN(x) << 12)) |
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#define | EXTRACT_UTYPE_IMM(x) ((RV_X(x, 12, 20) << 12) | (RV_IMM_SIGN(x) << 32)) |
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#define | EXTRACT_UJTYPE_IMM(x) ((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20)) |
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#define | EXTRACT_RVC_IMM(x) (RV_X(x, 2, 5) | (-RV_X(x, 12, 1) << 5)) |
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#define | EXTRACT_RVC_LUI_IMM(x) (EXTRACT_RVC_IMM (x) << RISCV_IMM_BITS) |
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#define | EXTRACT_RVC_SIMM3(x) (RV_X(x, 10, 2) | (-RV_X(x, 12, 1) << 2)) |
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#define | EXTRACT_RVC_ADDI4SPN_IMM(x) ((RV_X(x, 6, 1) << 2) | (RV_X(x, 5, 1) << 3) | (RV_X(x, 11, 2) << 4) | (RV_X(x, 7, 4) << 6)) |
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#define | EXTRACT_RVC_ADDI16SP_IMM(x) ((RV_X(x, 6, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 1) << 6) | (RV_X(x, 3, 2) << 7) | (-RV_X(x, 12, 1) << 9)) |
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#define | EXTRACT_RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | (RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 1) << 6)) |
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#define | EXTRACT_RVC_LD_IMM(x) ((RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 2) << 6)) |
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#define | EXTRACT_RVC_LWSP_IMM(x) ((RV_X(x, 4, 3) << 2) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 2) << 6)) |
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#define | EXTRACT_RVC_LDSP_IMM(x) ((RV_X(x, 5, 2) << 3) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 3) << 6)) |
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#define | EXTRACT_RVC_SWSP_IMM(x) ((RV_X(x, 9, 4) << 2) | (RV_X(x, 7, 2) << 6)) |
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#define | EXTRACT_RVC_SDSP_IMM(x) ((RV_X(x, 10, 3) << 3) | (RV_X(x, 7, 3) << 6)) |
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#define | EXTRACT_RVC_B_IMM(x) ((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8)) |
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#define | EXTRACT_RVC_J_IMM(x) ((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11)) |
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#define | ENCODE_ITYPE_IMM(x) (RV_X(x, 0, 12) << 20) |
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#define | ENCODE_STYPE_IMM(x) ((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25)) |
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#define | ENCODE_SBTYPE_IMM(x) ((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31)) |
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#define | ENCODE_UTYPE_IMM(x) (RV_X(x, 12, 20) << 12) |
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#define | ENCODE_UJTYPE_IMM(x) ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31)) |
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#define | ENCODE_RVC_IMM(x) ((RV_X(x, 0, 5) << 2) | (RV_X(x, 5, 1) << 12)) |
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#define | ENCODE_RVC_LUI_IMM(x) ENCODE_RVC_IMM ((x) >> RISCV_IMM_BITS) |
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#define | ENCODE_RVC_SIMM3(x) (RV_X(x, 0, 3) << 10) |
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#define | ENCODE_RVC_ADDI4SPN_IMM(x) ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 1) << 5) | (RV_X(x, 4, 2) << 11) | (RV_X(x, 6, 4) << 7)) |
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#define | ENCODE_RVC_ADDI16SP_IMM(x) ((RV_X(x, 4, 1) << 6) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 5) | (RV_X(x, 7, 2) << 3) | (RV_X(x, 9, 1) << 12)) |
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#define | ENCODE_RVC_LW_IMM(x) ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 1) << 5)) |
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#define | ENCODE_RVC_LD_IMM(x) ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 2) << 5)) |
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#define | ENCODE_RVC_LWSP_IMM(x) ((RV_X(x, 2, 3) << 4) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 2) << 2)) |
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#define | ENCODE_RVC_LDSP_IMM(x) ((RV_X(x, 3, 2) << 5) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 3) << 2)) |
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#define | ENCODE_RVC_SWSP_IMM(x) ((RV_X(x, 2, 4) << 9) | (RV_X(x, 6, 2) << 7)) |
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#define | ENCODE_RVC_SDSP_IMM(x) ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 3) << 7)) |
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#define | ENCODE_RVC_B_IMM(x) ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12)) |
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#define | ENCODE_RVC_J_IMM(x) ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12)) |
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#define | VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x)) |
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#define | VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x)) |
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#define | VALID_SBTYPE_IMM(x) (EXTRACT_SBTYPE_IMM(ENCODE_SBTYPE_IMM(x)) == (x)) |
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#define | VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x)) |
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#define | VALID_UJTYPE_IMM(x) (EXTRACT_UJTYPE_IMM(ENCODE_UJTYPE_IMM(x)) == (x)) |
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#define | VALID_RVC_IMM(x) (EXTRACT_RVC_IMM(ENCODE_RVC_IMM(x)) == (x)) |
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#define | VALID_RVC_LUI_IMM(x) (EXTRACT_RVC_LUI_IMM(ENCODE_RVC_LUI_IMM(x)) == (x)) |
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#define | VALID_RVC_SIMM3(x) (EXTRACT_RVC_SIMM3(ENCODE_RVC_SIMM3(x)) == (x)) |
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#define | VALID_RVC_ADDI4SPN_IMM(x) (EXTRACT_RVC_ADDI4SPN_IMM(ENCODE_RVC_ADDI4SPN_IMM(x)) == (x)) |
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#define | VALID_RVC_ADDI16SP_IMM(x) (EXTRACT_RVC_ADDI16SP_IMM(ENCODE_RVC_ADDI16SP_IMM(x)) == (x)) |
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#define | VALID_RVC_LW_IMM(x) (EXTRACT_RVC_LW_IMM(ENCODE_RVC_LW_IMM(x)) == (x)) |
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#define | VALID_RVC_LD_IMM(x) (EXTRACT_RVC_LD_IMM(ENCODE_RVC_LD_IMM(x)) == (x)) |
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#define | VALID_RVC_LWSP_IMM(x) (EXTRACT_RVC_LWSP_IMM(ENCODE_RVC_LWSP_IMM(x)) == (x)) |
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#define | VALID_RVC_LDSP_IMM(x) (EXTRACT_RVC_LDSP_IMM(ENCODE_RVC_LDSP_IMM(x)) == (x)) |
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#define | VALID_RVC_SWSP_IMM(x) (EXTRACT_RVC_SWSP_IMM(ENCODE_RVC_SWSP_IMM(x)) == (x)) |
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#define | VALID_RVC_SDSP_IMM(x) (EXTRACT_RVC_SDSP_IMM(ENCODE_RVC_SDSP_IMM(x)) == (x)) |
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#define | VALID_RVC_B_IMM(x) (EXTRACT_RVC_B_IMM(ENCODE_RVC_B_IMM(x)) == (x)) |
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#define | VALID_RVC_J_IMM(x) (EXTRACT_RVC_J_IMM(ENCODE_RVC_J_IMM(x)) == (x)) |
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#define | RISCV_RTYPE(insn, rd, rs1, rs2) ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2)) |
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#define | RISCV_ITYPE(insn, rd, rs1, imm) ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ENCODE_ITYPE_IMM(imm)) |
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#define | RISCV_STYPE(insn, rs1, rs2, imm) ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_STYPE_IMM(imm)) |
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#define | RISCV_SBTYPE(insn, rs1, rs2, target) ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_SBTYPE_IMM(target)) |
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#define | RISCV_UTYPE(insn, rd, bigimm) ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UTYPE_IMM(bigimm)) |
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#define | RISCV_UJTYPE(insn, rd, target) ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UJTYPE_IMM(target)) |
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#define | RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0) |
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#define | RVC_NOP MATCH_C_ADDI |
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#define | RISCV_CONST_HIGH_PART(VALUE) (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1)) |
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#define | RISCV_CONST_LOW_PART(VALUE) ((VALUE) - RISCV_CONST_HIGH_PART (VALUE)) |
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#define | RISCV_PCREL_HIGH_PART(VALUE, PC) RISCV_CONST_HIGH_PART((VALUE) - (PC)) |
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#define | RISCV_PCREL_LOW_PART(VALUE, PC) RISCV_CONST_LOW_PART((VALUE) - (PC)) |
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#define | RISCV_JUMP_BITS RISCV_BIGIMM_BITS |
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#define | RISCV_JUMP_ALIGN_BITS 1 |
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#define | RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS) |
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#define | RISCV_JUMP_REACH ((1ULL << RISCV_JUMP_BITS) * RISCV_JUMP_ALIGN) |
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#define | RISCV_IMM_BITS 12 |
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#define | RISCV_BIGIMM_BITS (32 - RISCV_IMM_BITS) |
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#define | RISCV_IMM_REACH (1LL << RISCV_IMM_BITS) |
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#define | RISCV_BIGIMM_REACH (1LL << RISCV_BIGIMM_BITS) |
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#define | RISCV_RVC_IMM_REACH (1LL << 6) |
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#define | RISCV_BRANCH_BITS RISCV_IMM_BITS |
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#define | RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS |
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#define | RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS) |
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#define | RISCV_BRANCH_REACH (RISCV_IMM_REACH * RISCV_BRANCH_ALIGN) |
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#define | OP_MASK_OP 0x7f |
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#define | OP_SH_OP 0 |
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#define | OP_MASK_RS2 0x1f |
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#define | OP_SH_RS2 20 |
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#define | OP_MASK_RS1 0x1f |
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#define | OP_SH_RS1 15 |
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#define | OP_MASK_RS3 0x1f |
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#define | OP_SH_RS3 27 |
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#define | OP_MASK_RD 0x1f |
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#define | OP_SH_RD 7 |
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#define | OP_MASK_SHAMT 0x3f |
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#define | OP_SH_SHAMT 20 |
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#define | OP_MASK_SHAMTW 0x1f |
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#define | OP_SH_SHAMTW 20 |
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#define | OP_MASK_RM 0x7 |
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#define | OP_SH_RM 12 |
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#define | OP_MASK_PRED 0xf |
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#define | OP_SH_PRED 24 |
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#define | OP_MASK_SUCC 0xf |
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#define | OP_SH_SUCC 20 |
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#define | OP_MASK_AQ 0x1 |
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#define | OP_SH_AQ 26 |
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#define | OP_MASK_RL 0x1 |
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#define | OP_SH_RL 25 |
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#define | OP_MASK_CUSTOM_IMM 0x7f |
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#define | OP_SH_CUSTOM_IMM 25 |
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#define | OP_MASK_CSR 0xfff |
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#define | OP_SH_CSR 20 |
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#define | OP_MASK_CRS2 0x1f |
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#define | OP_SH_CRS2 2 |
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#define | OP_MASK_CRS1S 0x7 |
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#define | OP_SH_CRS1S 7 |
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#define | OP_MASK_CRS2S 0x7 |
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#define | OP_SH_CRS2S 2 |
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#define | X_RA 1 |
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#define | X_SP 2 |
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#define | X_GP 3 |
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#define | X_TP 4 |
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#define | X_T0 5 |
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#define | X_T1 6 |
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#define | X_T2 7 |
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#define | X_T3 28 |
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#define | NGPR 32 |
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#define | NFPR 32 |
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#define | INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) |
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#define | EXTRACT_BITS(STRUCT, MASK, SHIFT) (((STRUCT) >> (SHIFT)) & (MASK)) |
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#define | EXTRACT_OPERAND(FIELD, INSN) EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD) |
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#define | INSN_ALIAS 0x00000001 |
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#define | INSN_MACRO 0xffffffff |
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#define | NUMOPCODES bfd_riscv_num_opcodes |
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