Rizin
unix-like reverse engineering framework and cli tools
riscv-opc.h
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1 // SPDX-FileCopyrightText: 2011-2015 Free Software Foundation, Inc.
2 // SPDX-License-Identifier: GPL-3.0-or-later
3 
4 /* Automatically generated by parse-opcodes. */
5 #ifndef RISCV_ENCODING_H
6 #define RISCV_ENCODING_H
7 #define MATCH_SLLI_RV32 0x1013
8 #define MASK_SLLI_RV32 0xfe00707f
9 #define MATCH_SRLI_RV32 0x5013
10 #define MASK_SRLI_RV32 0xfe00707f
11 #define MATCH_SRAI_RV32 0x40005013
12 #define MASK_SRAI_RV32 0xfe00707f
13 #define MATCH_FRFLAGS 0x102073
14 #define MASK_FRFLAGS 0xfffff07f
15 #define MATCH_FSFLAGS 0x101073
16 #define MASK_FSFLAGS 0xfff0707f
17 #define MATCH_FSFLAGSI 0x105073
18 #define MASK_FSFLAGSI 0xfff0707f
19 #define MATCH_FRRM 0x202073
20 #define MASK_FRRM 0xfffff07f
21 #define MATCH_FSRM 0x201073
22 #define MASK_FSRM 0xfff0707f
23 #define MATCH_FSRMI 0x205073
24 #define MASK_FSRMI 0xfff0707f
25 #define MATCH_FSCSR 0x301073
26 #define MASK_FSCSR 0xfff0707f
27 #define MATCH_FRCSR 0x302073
28 #define MASK_FRCSR 0xfffff07f
29 #define MATCH_RDCYCLE 0xc0002073
30 #define MASK_RDCYCLE 0xfffff07f
31 #define MATCH_RDTIME 0xc0102073
32 #define MASK_RDTIME 0xfffff07f
33 #define MATCH_RDINSTRET 0xc0202073
34 #define MASK_RDINSTRET 0xfffff07f
35 #define MATCH_RDCYCLEH 0xc8002073
36 #define MASK_RDCYCLEH 0xfffff07f
37 #define MATCH_RDTIMEH 0xc8102073
38 #define MASK_RDTIMEH 0xfffff07f
39 #define MATCH_RDINSTRETH 0xc8202073
40 #define MASK_RDINSTRETH 0xfffff07f
41 #define MATCH_SCALL 0x73
42 #define MASK_SCALL 0xffffffff
43 #define MATCH_SBREAK 0x100073
44 #define MASK_SBREAK 0xffffffff
45 #define MATCH_BEQ 0x63
46 #define MASK_BEQ 0x707f
47 #define MATCH_BNE 0x1063
48 #define MASK_BNE 0x707f
49 #define MATCH_BLT 0x4063
50 #define MASK_BLT 0x707f
51 #define MATCH_BGE 0x5063
52 #define MASK_BGE 0x707f
53 #define MATCH_BLTU 0x6063
54 #define MASK_BLTU 0x707f
55 #define MATCH_BGEU 0x7063
56 #define MASK_BGEU 0x707f
57 #define MATCH_JALR 0x67
58 #define MASK_JALR 0x707f
59 #define MATCH_JAL 0x6f
60 #define MASK_JAL 0x7f
61 #define MATCH_LUI 0x37
62 #define MASK_LUI 0x7f
63 #define MATCH_AUIPC 0x17
64 #define MASK_AUIPC 0x7f
65 #define MATCH_ADDI 0x13
66 #define MASK_ADDI 0x707f
67 #define MATCH_SLLI 0x1013
68 #define MASK_SLLI 0xfc00707f
69 #define MATCH_SLTI 0x2013
70 #define MASK_SLTI 0x707f
71 #define MATCH_SLTIU 0x3013
72 #define MASK_SLTIU 0x707f
73 #define MATCH_XORI 0x4013
74 #define MASK_XORI 0x707f
75 #define MATCH_SRLI 0x5013
76 #define MASK_SRLI 0xfc00707f
77 #define MATCH_SRAI 0x40005013
78 #define MASK_SRAI 0xfc00707f
79 #define MATCH_ORI 0x6013
80 #define MASK_ORI 0x707f
81 #define MATCH_ANDI 0x7013
82 #define MASK_ANDI 0x707f
83 #define MATCH_ADD 0x33
84 #define MASK_ADD 0xfe00707f
85 #define MATCH_SUB 0x40000033
86 #define MASK_SUB 0xfe00707f
87 #define MATCH_SLL 0x1033
88 #define MASK_SLL 0xfe00707f
89 #define MATCH_SLT 0x2033
90 #define MASK_SLT 0xfe00707f
91 #define MATCH_SLTU 0x3033
92 #define MASK_SLTU 0xfe00707f
93 #define MATCH_XOR 0x4033
94 #define MASK_XOR 0xfe00707f
95 #define MATCH_SRL 0x5033
96 #define MASK_SRL 0xfe00707f
97 #define MATCH_SRA 0x40005033
98 #define MASK_SRA 0xfe00707f
99 #define MATCH_OR 0x6033
100 #define MASK_OR 0xfe00707f
101 #define MATCH_AND 0x7033
102 #define MASK_AND 0xfe00707f
103 #define MATCH_ADDIW 0x1b
104 #define MASK_ADDIW 0x707f
105 #define MATCH_SLLIW 0x101b
106 #define MASK_SLLIW 0xfe00707f
107 #define MATCH_SRLIW 0x501b
108 #define MASK_SRLIW 0xfe00707f
109 #define MATCH_SRAIW 0x4000501b
110 #define MASK_SRAIW 0xfe00707f
111 #define MATCH_ADDW 0x3b
112 #define MASK_ADDW 0xfe00707f
113 #define MATCH_SUBW 0x4000003b
114 #define MASK_SUBW 0xfe00707f
115 #define MATCH_SLLW 0x103b
116 #define MASK_SLLW 0xfe00707f
117 #define MATCH_SRLW 0x503b
118 #define MASK_SRLW 0xfe00707f
119 #define MATCH_SRAW 0x4000503b
120 #define MASK_SRAW 0xfe00707f
121 #define MATCH_LB 0x3
122 #define MASK_LB 0x707f
123 #define MATCH_LH 0x1003
124 #define MASK_LH 0x707f
125 #define MATCH_LW 0x2003
126 #define MASK_LW 0x707f
127 #define MATCH_LD 0x3003
128 #define MASK_LD 0x707f
129 #define MATCH_LBU 0x4003
130 #define MASK_LBU 0x707f
131 #define MATCH_LHU 0x5003
132 #define MASK_LHU 0x707f
133 #define MATCH_LWU 0x6003
134 #define MASK_LWU 0x707f
135 #define MATCH_SB 0x23
136 #define MASK_SB 0x707f
137 #define MATCH_SH 0x1023
138 #define MASK_SH 0x707f
139 #define MATCH_SW 0x2023
140 #define MASK_SW 0x707f
141 #define MATCH_SD 0x3023
142 #define MASK_SD 0x707f
143 #define MATCH_FENCE 0xf
144 #define MASK_FENCE 0x707f
145 #define MATCH_FENCE_I 0x100f
146 #define MASK_FENCE_I 0x707f
147 #define MATCH_MUL 0x2000033
148 #define MASK_MUL 0xfe00707f
149 #define MATCH_MULH 0x2001033
150 #define MASK_MULH 0xfe00707f
151 #define MATCH_MULHSU 0x2002033
152 #define MASK_MULHSU 0xfe00707f
153 #define MATCH_MULHU 0x2003033
154 #define MASK_MULHU 0xfe00707f
155 #define MATCH_DIV 0x2004033
156 #define MASK_DIV 0xfe00707f
157 #define MATCH_DIVU 0x2005033
158 #define MASK_DIVU 0xfe00707f
159 #define MATCH_REM 0x2006033
160 #define MASK_REM 0xfe00707f
161 #define MATCH_REMU 0x2007033
162 #define MASK_REMU 0xfe00707f
163 #define MATCH_MULW 0x200003b
164 #define MASK_MULW 0xfe00707f
165 #define MATCH_DIVW 0x200403b
166 #define MASK_DIVW 0xfe00707f
167 #define MATCH_DIVUW 0x200503b
168 #define MASK_DIVUW 0xfe00707f
169 #define MATCH_REMW 0x200603b
170 #define MASK_REMW 0xfe00707f
171 #define MATCH_REMUW 0x200703b
172 #define MASK_REMUW 0xfe00707f
173 #define MATCH_AMOADD_W 0x202f
174 #define MASK_AMOADD_W 0xf800707f
175 #define MATCH_AMOXOR_W 0x2000202f
176 #define MASK_AMOXOR_W 0xf800707f
177 #define MATCH_AMOOR_W 0x4000202f
178 #define MASK_AMOOR_W 0xf800707f
179 #define MATCH_AMOAND_W 0x6000202f
180 #define MASK_AMOAND_W 0xf800707f
181 #define MATCH_AMOMIN_W 0x8000202f
182 #define MASK_AMOMIN_W 0xf800707f
183 #define MATCH_AMOMAX_W 0xa000202f
184 #define MASK_AMOMAX_W 0xf800707f
185 #define MATCH_AMOMINU_W 0xc000202f
186 #define MASK_AMOMINU_W 0xf800707f
187 #define MATCH_AMOMAXU_W 0xe000202f
188 #define MASK_AMOMAXU_W 0xf800707f
189 #define MATCH_AMOSWAP_W 0x800202f
190 #define MASK_AMOSWAP_W 0xf800707f
191 #define MATCH_LR_W 0x1000202f
192 #define MASK_LR_W 0xf9f0707f
193 #define MATCH_SC_W 0x1800202f
194 #define MASK_SC_W 0xf800707f
195 #define MATCH_AMOADD_D 0x302f
196 #define MASK_AMOADD_D 0xf800707f
197 #define MATCH_AMOXOR_D 0x2000302f
198 #define MASK_AMOXOR_D 0xf800707f
199 #define MATCH_AMOOR_D 0x4000302f
200 #define MASK_AMOOR_D 0xf800707f
201 #define MATCH_AMOAND_D 0x6000302f
202 #define MASK_AMOAND_D 0xf800707f
203 #define MATCH_AMOMIN_D 0x8000302f
204 #define MASK_AMOMIN_D 0xf800707f
205 #define MATCH_AMOMAX_D 0xa000302f
206 #define MASK_AMOMAX_D 0xf800707f
207 #define MATCH_AMOMINU_D 0xc000302f
208 #define MASK_AMOMINU_D 0xf800707f
209 #define MATCH_AMOMAXU_D 0xe000302f
210 #define MASK_AMOMAXU_D 0xf800707f
211 #define MATCH_AMOSWAP_D 0x800302f
212 #define MASK_AMOSWAP_D 0xf800707f
213 #define MATCH_LR_D 0x1000302f
214 #define MASK_LR_D 0xf9f0707f
215 #define MATCH_SC_D 0x1800302f
216 #define MASK_SC_D 0xf800707f
217 #define MATCH_ECALL 0x73
218 #define MASK_ECALL 0xffffffff
219 #define MATCH_EBREAK 0x100073
220 #define MASK_EBREAK 0xffffffff
221 #define MATCH_URET 0x200073
222 #define MASK_URET 0xffffffff
223 #define MATCH_SRET 0x10200073
224 #define MASK_SRET 0xffffffff
225 #define MATCH_HRET 0x20200073
226 #define MASK_HRET 0xffffffff
227 #define MATCH_MRET 0x30200073
228 #define MASK_MRET 0xffffffff
229 #define MATCH_DRET 0x7b200073
230 #define MASK_DRET 0xffffffff
231 #define MATCH_SFENCE_VM 0x10400073
232 #define MASK_SFENCE_VM 0xfff07fff
233 #define MATCH_WFI 0x10500073
234 #define MASK_WFI 0xffffffff
235 #define MATCH_CSRRW 0x1073
236 #define MASK_CSRRW 0x707f
237 #define MATCH_CSRRS 0x2073
238 #define MASK_CSRRS 0x707f
239 #define MATCH_CSRRC 0x3073
240 #define MASK_CSRRC 0x707f
241 #define MATCH_CSRRWI 0x5073
242 #define MASK_CSRRWI 0x707f
243 #define MATCH_CSRRSI 0x6073
244 #define MASK_CSRRSI 0x707f
245 #define MATCH_CSRRCI 0x7073
246 #define MASK_CSRRCI 0x707f
247 #define MATCH_FADD_S 0x53
248 #define MASK_FADD_S 0xfe00007f
249 #define MATCH_FSUB_S 0x8000053
250 #define MASK_FSUB_S 0xfe00007f
251 #define MATCH_FMUL_S 0x10000053
252 #define MASK_FMUL_S 0xfe00007f
253 #define MATCH_FDIV_S 0x18000053
254 #define MASK_FDIV_S 0xfe00007f
255 #define MATCH_FSGNJ_S 0x20000053
256 #define MASK_FSGNJ_S 0xfe00707f
257 #define MATCH_FSGNJN_S 0x20001053
258 #define MASK_FSGNJN_S 0xfe00707f
259 #define MATCH_FSGNJX_S 0x20002053
260 #define MASK_FSGNJX_S 0xfe00707f
261 #define MATCH_FMIN_S 0x28000053
262 #define MASK_FMIN_S 0xfe00707f
263 #define MATCH_FMAX_S 0x28001053
264 #define MASK_FMAX_S 0xfe00707f
265 #define MATCH_FSQRT_S 0x58000053
266 #define MASK_FSQRT_S 0xfff0007f
267 #define MATCH_FADD_D 0x2000053
268 #define MASK_FADD_D 0xfe00007f
269 #define MATCH_FSUB_D 0xa000053
270 #define MASK_FSUB_D 0xfe00007f
271 #define MATCH_FMUL_D 0x12000053
272 #define MASK_FMUL_D 0xfe00007f
273 #define MATCH_FDIV_D 0x1a000053
274 #define MASK_FDIV_D 0xfe00007f
275 #define MATCH_FSGNJ_D 0x22000053
276 #define MASK_FSGNJ_D 0xfe00707f
277 #define MATCH_FSGNJN_D 0x22001053
278 #define MASK_FSGNJN_D 0xfe00707f
279 #define MATCH_FSGNJX_D 0x22002053
280 #define MASK_FSGNJX_D 0xfe00707f
281 #define MATCH_FMIN_D 0x2a000053
282 #define MASK_FMIN_D 0xfe00707f
283 #define MATCH_FMAX_D 0x2a001053
284 #define MASK_FMAX_D 0xfe00707f
285 #define MATCH_FCVT_S_D 0x40100053
286 #define MASK_FCVT_S_D 0xfff0007f
287 #define MATCH_FCVT_D_S 0x42000053
288 #define MASK_FCVT_D_S 0xfff0007f
289 #define MATCH_FSQRT_D 0x5a000053
290 #define MASK_FSQRT_D 0xfff0007f
291 #define MATCH_FADD_Q 0x6000053
292 #define MASK_FADD_Q 0xfe00007f
293 #define MATCH_FSUB_Q 0xe000053
294 #define MASK_FSUB_Q 0xfe00007f
295 #define MATCH_FMUL_Q 0x16000053
296 #define MASK_FMUL_Q 0xfe00007f
297 #define MATCH_FDIV_Q 0x1e000053
298 #define MASK_FDIV_Q 0xfe00007f
299 #define MATCH_FSGNJ_Q 0x26000053
300 #define MASK_FSGNJ_Q 0xfe00707f
301 #define MATCH_FSGNJN_Q 0x26001053
302 #define MASK_FSGNJN_Q 0xfe00707f
303 #define MATCH_FSGNJX_Q 0x26002053
304 #define MASK_FSGNJX_Q 0xfe00707f
305 #define MATCH_FMIN_Q 0x2e000053
306 #define MASK_FMIN_Q 0xfe00707f
307 #define MATCH_FMAX_Q 0x2e001053
308 #define MASK_FMAX_Q 0xfe00707f
309 #define MATCH_FCVT_S_Q 0x40300053
310 #define MASK_FCVT_S_Q 0xfff0007f
311 #define MATCH_FCVT_Q_S 0x46000053
312 #define MASK_FCVT_Q_S 0xfff0007f
313 #define MATCH_FCVT_D_Q 0x42300053
314 #define MASK_FCVT_D_Q 0xfff0007f
315 #define MATCH_FCVT_Q_D 0x46100053
316 #define MASK_FCVT_Q_D 0xfff0007f
317 #define MATCH_FSQRT_Q 0x5e000053
318 #define MASK_FSQRT_Q 0xfff0007f
319 #define MATCH_FLE_S 0xa0000053
320 #define MASK_FLE_S 0xfe00707f
321 #define MATCH_FLT_S 0xa0001053
322 #define MASK_FLT_S 0xfe00707f
323 #define MATCH_FEQ_S 0xa0002053
324 #define MASK_FEQ_S 0xfe00707f
325 #define MATCH_FLE_D 0xa2000053
326 #define MASK_FLE_D 0xfe00707f
327 #define MATCH_FLT_D 0xa2001053
328 #define MASK_FLT_D 0xfe00707f
329 #define MATCH_FEQ_D 0xa2002053
330 #define MASK_FEQ_D 0xfe00707f
331 #define MATCH_FLE_Q 0xa6000053
332 #define MASK_FLE_Q 0xfe00707f
333 #define MATCH_FLT_Q 0xa6001053
334 #define MASK_FLT_Q 0xfe00707f
335 #define MATCH_FEQ_Q 0xa6002053
336 #define MASK_FEQ_Q 0xfe00707f
337 #define MATCH_FCVT_W_S 0xc0000053
338 #define MASK_FCVT_W_S 0xfff0007f
339 #define MATCH_FCVT_WU_S 0xc0100053
340 #define MASK_FCVT_WU_S 0xfff0007f
341 #define MATCH_FCVT_L_S 0xc0200053
342 #define MASK_FCVT_L_S 0xfff0007f
343 #define MATCH_FCVT_LU_S 0xc0300053
344 #define MASK_FCVT_LU_S 0xfff0007f
345 #define MATCH_FMV_X_S 0xe0000053
346 #define MASK_FMV_X_S 0xfff0707f
347 #define MATCH_FCLASS_S 0xe0001053
348 #define MASK_FCLASS_S 0xfff0707f
349 #define MATCH_FCVT_W_D 0xc2000053
350 #define MASK_FCVT_W_D 0xfff0007f
351 #define MATCH_FCVT_WU_D 0xc2100053
352 #define MASK_FCVT_WU_D 0xfff0007f
353 #define MATCH_FCVT_L_D 0xc2200053
354 #define MASK_FCVT_L_D 0xfff0007f
355 #define MATCH_FCVT_LU_D 0xc2300053
356 #define MASK_FCVT_LU_D 0xfff0007f
357 #define MATCH_FMV_X_D 0xe2000053
358 #define MASK_FMV_X_D 0xfff0707f
359 #define MATCH_FCLASS_D 0xe2001053
360 #define MASK_FCLASS_D 0xfff0707f
361 #define MATCH_FCVT_W_Q 0xc6000053
362 #define MASK_FCVT_W_Q 0xfff0007f
363 #define MATCH_FCVT_WU_Q 0xc6100053
364 #define MASK_FCVT_WU_Q 0xfff0007f
365 #define MATCH_FCVT_L_Q 0xc6200053
366 #define MASK_FCVT_L_Q 0xfff0007f
367 #define MATCH_FCVT_LU_Q 0xc6300053
368 #define MASK_FCVT_LU_Q 0xfff0007f
369 #define MATCH_FMV_X_Q 0xe6000053
370 #define MASK_FMV_X_Q 0xfff0707f
371 #define MATCH_FCLASS_Q 0xe6001053
372 #define MASK_FCLASS_Q 0xfff0707f
373 #define MATCH_FCVT_S_W 0xd0000053
374 #define MASK_FCVT_S_W 0xfff0007f
375 #define MATCH_FCVT_S_WU 0xd0100053
376 #define MASK_FCVT_S_WU 0xfff0007f
377 #define MATCH_FCVT_S_L 0xd0200053
378 #define MASK_FCVT_S_L 0xfff0007f
379 #define MATCH_FCVT_S_LU 0xd0300053
380 #define MASK_FCVT_S_LU 0xfff0007f
381 #define MATCH_FMV_S_X 0xf0000053
382 #define MASK_FMV_S_X 0xfff0707f
383 #define MATCH_FCVT_D_W 0xd2000053
384 #define MASK_FCVT_D_W 0xfff0007f
385 #define MATCH_FCVT_D_WU 0xd2100053
386 #define MASK_FCVT_D_WU 0xfff0007f
387 #define MATCH_FCVT_D_L 0xd2200053
388 #define MASK_FCVT_D_L 0xfff0007f
389 #define MATCH_FCVT_D_LU 0xd2300053
390 #define MASK_FCVT_D_LU 0xfff0007f
391 #define MATCH_FMV_D_X 0xf2000053
392 #define MASK_FMV_D_X 0xfff0707f
393 #define MATCH_FCVT_Q_W 0xd6000053
394 #define MASK_FCVT_Q_W 0xfff0007f
395 #define MATCH_FCVT_Q_WU 0xd6100053
396 #define MASK_FCVT_Q_WU 0xfff0007f
397 #define MATCH_FCVT_Q_L 0xd6200053
398 #define MASK_FCVT_Q_L 0xfff0007f
399 #define MATCH_FCVT_Q_LU 0xd6300053
400 #define MASK_FCVT_Q_LU 0xfff0007f
401 #define MATCH_FMV_Q_X 0xf6000053
402 #define MASK_FMV_Q_X 0xfff0707f
403 #define MATCH_FLW 0x2007
404 #define MASK_FLW 0x707f
405 #define MATCH_FLD 0x3007
406 #define MASK_FLD 0x707f
407 #define MATCH_FLQ 0x4007
408 #define MASK_FLQ 0x707f
409 #define MATCH_FSW 0x2027
410 #define MASK_FSW 0x707f
411 #define MATCH_FSD 0x3027
412 #define MASK_FSD 0x707f
413 #define MATCH_FSQ 0x4027
414 #define MASK_FSQ 0x707f
415 #define MATCH_FMADD_S 0x43
416 #define MASK_FMADD_S 0x600007f
417 #define MATCH_FMSUB_S 0x47
418 #define MASK_FMSUB_S 0x600007f
419 #define MATCH_FNMSUB_S 0x4b
420 #define MASK_FNMSUB_S 0x600007f
421 #define MATCH_FNMADD_S 0x4f
422 #define MASK_FNMADD_S 0x600007f
423 #define MATCH_FMADD_D 0x2000043
424 #define MASK_FMADD_D 0x600007f
425 #define MATCH_FMSUB_D 0x2000047
426 #define MASK_FMSUB_D 0x600007f
427 #define MATCH_FNMSUB_D 0x200004b
428 #define MASK_FNMSUB_D 0x600007f
429 #define MATCH_FNMADD_D 0x200004f
430 #define MASK_FNMADD_D 0x600007f
431 #define MATCH_FMADD_Q 0x6000043
432 #define MASK_FMADD_Q 0x600007f
433 #define MATCH_FMSUB_Q 0x6000047
434 #define MASK_FMSUB_Q 0x600007f
435 #define MATCH_FNMSUB_Q 0x600004b
436 #define MASK_FNMSUB_Q 0x600007f
437 #define MATCH_FNMADD_Q 0x600004f
438 #define MASK_FNMADD_Q 0x600007f
439 #define MATCH_C_ADDI4SPN 0x0
440 #define MASK_C_ADDI4SPN 0xe003
441 #define MATCH_C_FLD 0x2000
442 #define MASK_C_FLD 0xe003
443 #define MATCH_C_LW 0x4000
444 #define MASK_C_LW 0xe003
445 #define MATCH_C_FLW 0x6000
446 #define MASK_C_FLW 0xe003
447 #define MATCH_C_FSD 0xa000
448 #define MASK_C_FSD 0xe003
449 #define MATCH_C_SW 0xc000
450 #define MASK_C_SW 0xe003
451 #define MATCH_C_FSW 0xe000
452 #define MASK_C_FSW 0xe003
453 #define MATCH_C_ADDI 0x1
454 #define MASK_C_ADDI 0xe003
455 #define MATCH_C_JAL 0x2001
456 #define MASK_C_JAL 0xe003
457 #define MATCH_C_LI 0x4001
458 #define MASK_C_LI 0xe003
459 #define MATCH_C_LUI 0x6001
460 #define MASK_C_LUI 0xe003
461 #define MATCH_C_SRLI 0x8001
462 #define MASK_C_SRLI 0xec03
463 #define MATCH_C_SRAI 0x8401
464 #define MASK_C_SRAI 0xec03
465 #define MATCH_C_ANDI 0x8801
466 #define MASK_C_ANDI 0xec03
467 #define MATCH_C_SUB 0x8c01
468 #define MASK_C_SUB 0xfc63
469 #define MATCH_C_XOR 0x8c21
470 #define MASK_C_XOR 0xfc63
471 #define MATCH_C_OR 0x8c41
472 #define MASK_C_OR 0xfc63
473 #define MATCH_C_AND 0x8c61
474 #define MASK_C_AND 0xfc63
475 #define MATCH_C_SUBW 0x9c01
476 #define MASK_C_SUBW 0xfc63
477 #define MATCH_C_ADDW 0x9c21
478 #define MASK_C_ADDW 0xfc63
479 #define MATCH_C_J 0xa001
480 #define MASK_C_J 0xe003
481 #define MATCH_C_BEQZ 0xc001
482 #define MASK_C_BEQZ 0xe003
483 #define MATCH_C_BNEZ 0xe001
484 #define MASK_C_BNEZ 0xe003
485 #define MATCH_C_SLLI 0x2
486 #define MASK_C_SLLI 0xe003
487 #define MATCH_C_FLDSP 0x2002
488 #define MASK_C_FLDSP 0xe003
489 #define MATCH_C_LWSP 0x4002
490 #define MASK_C_LWSP 0xe003
491 #define MATCH_C_FLWSP 0x6002
492 #define MASK_C_FLWSP 0xe003
493 #define MATCH_C_MV 0x8002
494 #define MASK_C_MV 0xf003
495 #define MATCH_C_ADD 0x9002
496 #define MASK_C_ADD 0xf003
497 #define MATCH_C_FSDSP 0xa002
498 #define MASK_C_FSDSP 0xe003
499 #define MATCH_C_SWSP 0xc002
500 #define MASK_C_SWSP 0xe003
501 #define MATCH_C_FSWSP 0xe002
502 #define MASK_C_FSWSP 0xe003
503 #define MATCH_C_NOP 0x1
504 #define MASK_C_NOP 0xffff
505 #define MATCH_C_ADDI16SP 0x6101
506 #define MASK_C_ADDI16SP 0xef83
507 #define MATCH_C_JR 0x8002
508 #define MASK_C_JR 0xf07f
509 #define MATCH_C_JALR 0x9002
510 #define MASK_C_JALR 0xf07f
511 #define MATCH_C_EBREAK 0x9002
512 #define MASK_C_EBREAK 0xffff
513 #define MATCH_C_LD 0x6000
514 #define MASK_C_LD 0xe003
515 #define MATCH_C_SD 0xe000
516 #define MASK_C_SD 0xe003
517 #define MATCH_C_ADDIW 0x2001
518 #define MASK_C_ADDIW 0xe003
519 #define MATCH_C_LDSP 0x6002
520 #define MASK_C_LDSP 0xe003
521 #define MATCH_C_SDSP 0xe002
522 #define MASK_C_SDSP 0xe003
523 #define MATCH_CUSTOM0 0xb
524 #define MASK_CUSTOM0 0x707f
525 #define MATCH_CUSTOM0_RS1 0x200b
526 #define MASK_CUSTOM0_RS1 0x707f
527 #define MATCH_CUSTOM0_RS1_RS2 0x300b
528 #define MASK_CUSTOM0_RS1_RS2 0x707f
529 #define MATCH_CUSTOM0_RD 0x400b
530 #define MASK_CUSTOM0_RD 0x707f
531 #define MATCH_CUSTOM0_RD_RS1 0x600b
532 #define MASK_CUSTOM0_RD_RS1 0x707f
533 #define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
534 #define MASK_CUSTOM0_RD_RS1_RS2 0x707f
535 #define MATCH_CUSTOM1 0x2b
536 #define MASK_CUSTOM1 0x707f
537 #define MATCH_CUSTOM1_RS1 0x202b
538 #define MASK_CUSTOM1_RS1 0x707f
539 #define MATCH_CUSTOM1_RS1_RS2 0x302b
540 #define MASK_CUSTOM1_RS1_RS2 0x707f
541 #define MATCH_CUSTOM1_RD 0x402b
542 #define MASK_CUSTOM1_RD 0x707f
543 #define MATCH_CUSTOM1_RD_RS1 0x602b
544 #define MASK_CUSTOM1_RD_RS1 0x707f
545 #define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
546 #define MASK_CUSTOM1_RD_RS1_RS2 0x707f
547 #define MATCH_CUSTOM2 0x5b
548 #define MASK_CUSTOM2 0x707f
549 #define MATCH_CUSTOM2_RS1 0x205b
550 #define MASK_CUSTOM2_RS1 0x707f
551 #define MATCH_CUSTOM2_RS1_RS2 0x305b
552 #define MASK_CUSTOM2_RS1_RS2 0x707f
553 #define MATCH_CUSTOM2_RD 0x405b
554 #define MASK_CUSTOM2_RD 0x707f
555 #define MATCH_CUSTOM2_RD_RS1 0x605b
556 #define MASK_CUSTOM2_RD_RS1 0x707f
557 #define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
558 #define MASK_CUSTOM2_RD_RS1_RS2 0x707f
559 #define MATCH_CUSTOM3 0x7b
560 #define MASK_CUSTOM3 0x707f
561 #define MATCH_CUSTOM3_RS1 0x207b
562 #define MASK_CUSTOM3_RS1 0x707f
563 #define MATCH_CUSTOM3_RS1_RS2 0x307b
564 #define MASK_CUSTOM3_RS1_RS2 0x707f
565 #define MATCH_CUSTOM3_RD 0x407b
566 #define MASK_CUSTOM3_RD 0x707f
567 #define MATCH_CUSTOM3_RD_RS1 0x607b
568 #define MASK_CUSTOM3_RD_RS1 0x707f
569 #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
570 #define MASK_CUSTOM3_RD_RS1_RS2 0x707f
571 #define CSR_FFLAGS 0x1
572 #define CSR_FRM 0x2
573 #define CSR_FCSR 0x3
574 #define CSR_CYCLE 0xc00
575 #define CSR_TIME 0xc01
576 #define CSR_INSTRET 0xc02
577 #define CSR_HPMCOUNTER3 0xc03
578 #define CSR_HPMCOUNTER4 0xc04
579 #define CSR_HPMCOUNTER5 0xc05
580 #define CSR_HPMCOUNTER6 0xc06
581 #define CSR_HPMCOUNTER7 0xc07
582 #define CSR_HPMCOUNTER8 0xc08
583 #define CSR_HPMCOUNTER9 0xc09
584 #define CSR_HPMCOUNTER10 0xc0a
585 #define CSR_HPMCOUNTER11 0xc0b
586 #define CSR_HPMCOUNTER12 0xc0c
587 #define CSR_HPMCOUNTER13 0xc0d
588 #define CSR_HPMCOUNTER14 0xc0e
589 #define CSR_HPMCOUNTER15 0xc0f
590 #define CSR_HPMCOUNTER16 0xc10
591 #define CSR_HPMCOUNTER17 0xc11
592 #define CSR_HPMCOUNTER18 0xc12
593 #define CSR_HPMCOUNTER19 0xc13
594 #define CSR_HPMCOUNTER20 0xc14
595 #define CSR_HPMCOUNTER21 0xc15
596 #define CSR_HPMCOUNTER22 0xc16
597 #define CSR_HPMCOUNTER23 0xc17
598 #define CSR_HPMCOUNTER24 0xc18
599 #define CSR_HPMCOUNTER25 0xc19
600 #define CSR_HPMCOUNTER26 0xc1a
601 #define CSR_HPMCOUNTER27 0xc1b
602 #define CSR_HPMCOUNTER28 0xc1c
603 #define CSR_HPMCOUNTER29 0xc1d
604 #define CSR_HPMCOUNTER30 0xc1e
605 #define CSR_HPMCOUNTER31 0xc1f
606 #define CSR_SSTATUS 0x100
607 #define CSR_SIE 0x104
608 #define CSR_STVEC 0x105
609 #define CSR_SSCRATCH 0x140
610 #define CSR_SEPC 0x141
611 #define CSR_SCAUSE 0x142
612 #define CSR_SBADADDR 0x143
613 #define CSR_SIP 0x144
614 #define CSR_SPTBR 0x180
615 #define CSR_MSTATUS 0x300
616 #define CSR_MISA 0x301
617 #define CSR_MEDELEG 0x302
618 #define CSR_MIDELEG 0x303
619 #define CSR_MIE 0x304
620 #define CSR_MTVEC 0x305
621 #define CSR_MSCRATCH 0x340
622 #define CSR_MEPC 0x341
623 #define CSR_MCAUSE 0x342
624 #define CSR_MBADADDR 0x343
625 #define CSR_MIP 0x344
626 #define CSR_TSELECT 0x7a0
627 #define CSR_TDATA1 0x7a1
628 #define CSR_TDATA2 0x7a2
629 #define CSR_TDATA3 0x7a3
630 #define CSR_DCSR 0x7b0
631 #define CSR_DPC 0x7b1
632 #define CSR_DSCRATCH 0x7b2
633 #define CSR_MCYCLE 0xb00
634 #define CSR_MINSTRET 0xb02
635 #define CSR_MHPMCOUNTER3 0xb03
636 #define CSR_MHPMCOUNTER4 0xb04
637 #define CSR_MHPMCOUNTER5 0xb05
638 #define CSR_MHPMCOUNTER6 0xb06
639 #define CSR_MHPMCOUNTER7 0xb07
640 #define CSR_MHPMCOUNTER8 0xb08
641 #define CSR_MHPMCOUNTER9 0xb09
642 #define CSR_MHPMCOUNTER10 0xb0a
643 #define CSR_MHPMCOUNTER11 0xb0b
644 #define CSR_MHPMCOUNTER12 0xb0c
645 #define CSR_MHPMCOUNTER13 0xb0d
646 #define CSR_MHPMCOUNTER14 0xb0e
647 #define CSR_MHPMCOUNTER15 0xb0f
648 #define CSR_MHPMCOUNTER16 0xb10
649 #define CSR_MHPMCOUNTER17 0xb11
650 #define CSR_MHPMCOUNTER18 0xb12
651 #define CSR_MHPMCOUNTER19 0xb13
652 #define CSR_MHPMCOUNTER20 0xb14
653 #define CSR_MHPMCOUNTER21 0xb15
654 #define CSR_MHPMCOUNTER22 0xb16
655 #define CSR_MHPMCOUNTER23 0xb17
656 #define CSR_MHPMCOUNTER24 0xb18
657 #define CSR_MHPMCOUNTER25 0xb19
658 #define CSR_MHPMCOUNTER26 0xb1a
659 #define CSR_MHPMCOUNTER27 0xb1b
660 #define CSR_MHPMCOUNTER28 0xb1c
661 #define CSR_MHPMCOUNTER29 0xb1d
662 #define CSR_MHPMCOUNTER30 0xb1e
663 #define CSR_MHPMCOUNTER31 0xb1f
664 #define CSR_MUCOUNTEREN 0x320
665 #define CSR_MSCOUNTEREN 0x321
666 #define CSR_MHPMEVENT3 0x323
667 #define CSR_MHPMEVENT4 0x324
668 #define CSR_MHPMEVENT5 0x325
669 #define CSR_MHPMEVENT6 0x326
670 #define CSR_MHPMEVENT7 0x327
671 #define CSR_MHPMEVENT8 0x328
672 #define CSR_MHPMEVENT9 0x329
673 #define CSR_MHPMEVENT10 0x32a
674 #define CSR_MHPMEVENT11 0x32b
675 #define CSR_MHPMEVENT12 0x32c
676 #define CSR_MHPMEVENT13 0x32d
677 #define CSR_MHPMEVENT14 0x32e
678 #define CSR_MHPMEVENT15 0x32f
679 #define CSR_MHPMEVENT16 0x330
680 #define CSR_MHPMEVENT17 0x331
681 #define CSR_MHPMEVENT18 0x332
682 #define CSR_MHPMEVENT19 0x333
683 #define CSR_MHPMEVENT20 0x334
684 #define CSR_MHPMEVENT21 0x335
685 #define CSR_MHPMEVENT22 0x336
686 #define CSR_MHPMEVENT23 0x337
687 #define CSR_MHPMEVENT24 0x338
688 #define CSR_MHPMEVENT25 0x339
689 #define CSR_MHPMEVENT26 0x33a
690 #define CSR_MHPMEVENT27 0x33b
691 #define CSR_MHPMEVENT28 0x33c
692 #define CSR_MHPMEVENT29 0x33d
693 #define CSR_MHPMEVENT30 0x33e
694 #define CSR_MHPMEVENT31 0x33f
695 #define CSR_MVENDORID 0xf11
696 #define CSR_MARCHID 0xf12
697 #define CSR_MIMPID 0xf13
698 #define CSR_MHARTID 0xf14
699 #define CSR_CYCLEH 0xc80
700 #define CSR_TIMEH 0xc81
701 #define CSR_INSTRETH 0xc82
702 #define CSR_HPMCOUNTER3H 0xc83
703 #define CSR_HPMCOUNTER4H 0xc84
704 #define CSR_HPMCOUNTER5H 0xc85
705 #define CSR_HPMCOUNTER6H 0xc86
706 #define CSR_HPMCOUNTER7H 0xc87
707 #define CSR_HPMCOUNTER8H 0xc88
708 #define CSR_HPMCOUNTER9H 0xc89
709 #define CSR_HPMCOUNTER10H 0xc8a
710 #define CSR_HPMCOUNTER11H 0xc8b
711 #define CSR_HPMCOUNTER12H 0xc8c
712 #define CSR_HPMCOUNTER13H 0xc8d
713 #define CSR_HPMCOUNTER14H 0xc8e
714 #define CSR_HPMCOUNTER15H 0xc8f
715 #define CSR_HPMCOUNTER16H 0xc90
716 #define CSR_HPMCOUNTER17H 0xc91
717 #define CSR_HPMCOUNTER18H 0xc92
718 #define CSR_HPMCOUNTER19H 0xc93
719 #define CSR_HPMCOUNTER20H 0xc94
720 #define CSR_HPMCOUNTER21H 0xc95
721 #define CSR_HPMCOUNTER22H 0xc96
722 #define CSR_HPMCOUNTER23H 0xc97
723 #define CSR_HPMCOUNTER24H 0xc98
724 #define CSR_HPMCOUNTER25H 0xc99
725 #define CSR_HPMCOUNTER26H 0xc9a
726 #define CSR_HPMCOUNTER27H 0xc9b
727 #define CSR_HPMCOUNTER28H 0xc9c
728 #define CSR_HPMCOUNTER29H 0xc9d
729 #define CSR_HPMCOUNTER30H 0xc9e
730 #define CSR_HPMCOUNTER31H 0xc9f
731 #define CSR_MCYCLEH 0xb80
732 #define CSR_MINSTRETH 0xb82
733 #define CSR_MHPMCOUNTER3H 0xb83
734 #define CSR_MHPMCOUNTER4H 0xb84
735 #define CSR_MHPMCOUNTER5H 0xb85
736 #define CSR_MHPMCOUNTER6H 0xb86
737 #define CSR_MHPMCOUNTER7H 0xb87
738 #define CSR_MHPMCOUNTER8H 0xb88
739 #define CSR_MHPMCOUNTER9H 0xb89
740 #define CSR_MHPMCOUNTER10H 0xb8a
741 #define CSR_MHPMCOUNTER11H 0xb8b
742 #define CSR_MHPMCOUNTER12H 0xb8c
743 #define CSR_MHPMCOUNTER13H 0xb8d
744 #define CSR_MHPMCOUNTER14H 0xb8e
745 #define CSR_MHPMCOUNTER15H 0xb8f
746 #define CSR_MHPMCOUNTER16H 0xb90
747 #define CSR_MHPMCOUNTER17H 0xb91
748 #define CSR_MHPMCOUNTER18H 0xb92
749 #define CSR_MHPMCOUNTER19H 0xb93
750 #define CSR_MHPMCOUNTER20H 0xb94
751 #define CSR_MHPMCOUNTER21H 0xb95
752 #define CSR_MHPMCOUNTER22H 0xb96
753 #define CSR_MHPMCOUNTER23H 0xb97
754 #define CSR_MHPMCOUNTER24H 0xb98
755 #define CSR_MHPMCOUNTER25H 0xb99
756 #define CSR_MHPMCOUNTER26H 0xb9a
757 #define CSR_MHPMCOUNTER27H 0xb9b
758 #define CSR_MHPMCOUNTER28H 0xb9c
759 #define CSR_MHPMCOUNTER29H 0xb9d
760 #define CSR_MHPMCOUNTER30H 0xb9e
761 #define CSR_MHPMCOUNTER31H 0xb9f
762 #define CAUSE_MISALIGNED_FETCH 0x0
763 #define CAUSE_FAULT_FETCH 0x1
764 #define CAUSE_ILLEGAL_INSTRUCTION 0x2
765 #define CAUSE_BREAKPOINT 0x3
766 #define CAUSE_MISALIGNED_LOAD 0x4
767 #define CAUSE_FAULT_LOAD 0x5
768 #define CAUSE_MISALIGNED_STORE 0x6
769 #define CAUSE_FAULT_STORE 0x7
770 #define CAUSE_USER_ECALL 0x8
771 #define CAUSE_SUPERVISOR_ECALL 0x9
772 #define CAUSE_HYPERVISOR_ECALL 0xa
773 #define CAUSE_MACHINE_ECALL 0xb
774 #endif
775 #ifdef DECLARE_INSN
776 DECLARE_INSN(slli_rv32, MATCH_SLLI_RV32, MASK_SLLI_RV32)
777 DECLARE_INSN(srli_rv32, MATCH_SRLI_RV32, MASK_SRLI_RV32)
778 DECLARE_INSN(srai_rv32, MATCH_SRAI_RV32, MASK_SRAI_RV32)
779 DECLARE_INSN(frflags, MATCH_FRFLAGS, MASK_FRFLAGS)
780 DECLARE_INSN(fsflags, MATCH_FSFLAGS, MASK_FSFLAGS)
781 DECLARE_INSN(fsflagsi, MATCH_FSFLAGSI, MASK_FSFLAGSI)
782 DECLARE_INSN(frrm, MATCH_FRRM, MASK_FRRM)
783 DECLARE_INSN(fsrm, MATCH_FSRM, MASK_FSRM)
784 DECLARE_INSN(fsrmi, MATCH_FSRMI, MASK_FSRMI)
785 DECLARE_INSN(fscsr, MATCH_FSCSR, MASK_FSCSR)
786 DECLARE_INSN(frcsr, MATCH_FRCSR, MASK_FRCSR)
787 DECLARE_INSN(rdcycle, MATCH_RDCYCLE, MASK_RDCYCLE)
788 DECLARE_INSN(rdtime, MATCH_RDTIME, MASK_RDTIME)
789 DECLARE_INSN(rdinstret, MATCH_RDINSTRET, MASK_RDINSTRET)
790 DECLARE_INSN(rdcycleh, MATCH_RDCYCLEH, MASK_RDCYCLEH)
791 DECLARE_INSN(rdtimeh, MATCH_RDTIMEH, MASK_RDTIMEH)
792 DECLARE_INSN(rdinstreth, MATCH_RDINSTRETH, MASK_RDINSTRETH)
793 DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL)
794 DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK)
795 DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
796 DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
797 DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
798 DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
799 DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
800 DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
801 DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
802 DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
803 DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
804 DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
805 DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
806 DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
807 DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
808 DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
809 DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
810 DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
811 DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
812 DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
813 DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
814 DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
815 DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
816 DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
817 DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
818 DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
819 DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
820 DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
821 DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
822 DECLARE_INSN(or, MATCH_OR, MASK_OR)
823 DECLARE_INSN(and, MATCH_AND, MASK_AND)
824 DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
825 DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
826 DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
827 DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
828 DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
829 DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
830 DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
831 DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
832 DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
833 DECLARE_INSN(lb, MATCH_LB, MASK_LB)
834 DECLARE_INSN(lh, MATCH_LH, MASK_LH)
835 DECLARE_INSN(lw, MATCH_LW, MASK_LW)
836 DECLARE_INSN(ld, MATCH_LD, MASK_LD)
837 DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
838 DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
839 DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
840 DECLARE_INSN(sb, MATCH_SB, MASK_SB)
841 DECLARE_INSN(sh, MATCH_SH, MASK_SH)
842 DECLARE_INSN(sw, MATCH_SW, MASK_SW)
843 DECLARE_INSN(sd, MATCH_SD, MASK_SD)
844 DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
845 DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
846 DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
847 DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
848 DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
849 DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
850 DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
851 DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
852 DECLARE_INSN(rem, MATCH_REM, MASK_REM)
853 DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
854 DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
855 DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
856 DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
857 DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
858 DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
859 DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
860 DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
861 DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
862 DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
863 DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
864 DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
865 DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
866 DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
867 DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
868 DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
869 DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
870 DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
871 DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
872 DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
873 DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
874 DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
875 DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
876 DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
877 DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
878 DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
879 DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
880 DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
881 DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
882 DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
883 DECLARE_INSN(uret, MATCH_URET, MASK_URET)
884 DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
885 DECLARE_INSN(hret, MATCH_HRET, MASK_HRET)
886 DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
887 DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
888 DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
889 DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
890 DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
891 DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
892 DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
893 DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
894 DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
895 DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
896 DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
897 DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
898 DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
899 DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
900 DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
901 DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
902 DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
903 DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
904 DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
905 DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
906 DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
907 DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
908 DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
909 DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
910 DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
911 DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
912 DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
913 DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
914 DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
915 DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
916 DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
917 DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
918 DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q)
919 DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q)
920 DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q)
921 DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q)
922 DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q)
923 DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q)
924 DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q)
925 DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q)
926 DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q)
927 DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q)
928 DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S)
929 DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q)
930 DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D)
931 DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q)
932 DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
933 DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
934 DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
935 DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
936 DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
937 DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
938 DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q)
939 DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q)
940 DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q)
941 DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
942 DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
943 DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
944 DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
945 DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
946 DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
947 DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
948 DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
949 DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
950 DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
951 DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
952 DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
953 DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q)
954 DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q)
955 DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q)
956 DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q)
957 DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q)
958 DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q)
959 DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
960 DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
961 DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
962 DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
963 DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
964 DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
965 DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
966 DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
967 DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
968 DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
969 DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W)
970 DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU)
971 DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L)
972 DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU)
973 DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X)
974 DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
975 DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
976 DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ)
977 DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
978 DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
979 DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ)
980 DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
981 DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
982 DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
983 DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
984 DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
985 DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
986 DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
987 DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
988 DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q)
989 DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q)
990 DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q)
991 DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q)
992 DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
993 DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
994 DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
995 DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW)
996 DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD)
997 DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
998 DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW)
999 DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
1000 DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL)
1001 DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
1002 DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
1003 DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
1004 DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
1005 DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI)
1006 DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
1007 DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)
1008 DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR)
1009 DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND)
1010 DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW)
1011 DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
1012 DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
1013 DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
1014 DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
1015 DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
1016 DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP)
1017 DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
1018 DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP)
1019 DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV)
1020 DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
1021 DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP)
1022 DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
1023 DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP)
1024 DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP)
1025 DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
1026 DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
1027 DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
1028 DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK)
1029 DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
1030 DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
1031 DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
1032 DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
1033 DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
1034 DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
1035 DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
1036 DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
1037 DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
1038 DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
1039 DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2)
1040 DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
1041 DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
1042 DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
1043 DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
1044 DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
1045 DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2)
1046 DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
1047 DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
1048 DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
1049 DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
1050 DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
1051 DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2)
1052 DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
1053 DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
1054 DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
1055 DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
1056 DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
1057 DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
1058 #endif
1059 #ifdef DECLARE_CSR
1060 DECLARE_CSR(fflags, CSR_FFLAGS)
1061 DECLARE_CSR(frm, CSR_FRM)
1062 DECLARE_CSR(fcsr, CSR_FCSR)
1063 DECLARE_CSR(cycle, CSR_CYCLE)
1065 DECLARE_CSR(instret, CSR_INSTRET)
1066 DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3)
1067 DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4)
1068 DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5)
1069 DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6)
1070 DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7)
1071 DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8)
1072 DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9)
1073 DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10)
1074 DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11)
1075 DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12)
1076 DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13)
1077 DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14)
1078 DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15)
1079 DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16)
1080 DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17)
1081 DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18)
1082 DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19)
1083 DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20)
1084 DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21)
1085 DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22)
1086 DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23)
1087 DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24)
1088 DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25)
1089 DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26)
1090 DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27)
1091 DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28)
1092 DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29)
1093 DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30)
1094 DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31)
1095 DECLARE_CSR(sstatus, CSR_SSTATUS)
1096 DECLARE_CSR(sie, CSR_SIE)
1097 DECLARE_CSR(stvec, CSR_STVEC)
1098 DECLARE_CSR(sscratch, CSR_SSCRATCH)
1099 DECLARE_CSR(sepc, CSR_SEPC)
1100 DECLARE_CSR(scause, CSR_SCAUSE)
1101 DECLARE_CSR(sbadaddr, CSR_SBADADDR)
1102 DECLARE_CSR(sip, CSR_SIP)
1103 DECLARE_CSR(sptbr, CSR_SPTBR)
1104 DECLARE_CSR(mstatus, CSR_MSTATUS)
1105 DECLARE_CSR(misa, CSR_MISA)
1106 DECLARE_CSR(medeleg, CSR_MEDELEG)
1107 DECLARE_CSR(mideleg, CSR_MIDELEG)
1108 DECLARE_CSR(mie, CSR_MIE)
1109 DECLARE_CSR(mtvec, CSR_MTVEC)
1110 DECLARE_CSR(mscratch, CSR_MSCRATCH)
1111 DECLARE_CSR(mepc, CSR_MEPC)
1112 DECLARE_CSR(mcause, CSR_MCAUSE)
1113 DECLARE_CSR(mbadaddr, CSR_MBADADDR)
1114 DECLARE_CSR(mip, CSR_MIP)
1115 DECLARE_CSR(tselect, CSR_TSELECT)
1116 DECLARE_CSR(tdata1, CSR_TDATA1)
1117 DECLARE_CSR(tdata2, CSR_TDATA2)
1118 DECLARE_CSR(tdata3, CSR_TDATA3)
1119 DECLARE_CSR(dcsr, CSR_DCSR)
1120 DECLARE_CSR(dpc, CSR_DPC)
1121 DECLARE_CSR(dscratch, CSR_DSCRATCH)
1122 DECLARE_CSR(mcycle, CSR_MCYCLE)
1123 DECLARE_CSR(minstret, CSR_MINSTRET)
1124 DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3)
1125 DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4)
1126 DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5)
1127 DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6)
1128 DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7)
1129 DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8)
1130 DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9)
1131 DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10)
1132 DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11)
1133 DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12)
1134 DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13)
1135 DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14)
1136 DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15)
1137 DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16)
1138 DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17)
1139 DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18)
1140 DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19)
1141 DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20)
1142 DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21)
1143 DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22)
1144 DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23)
1145 DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24)
1146 DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25)
1147 DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26)
1148 DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27)
1149 DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28)
1150 DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29)
1151 DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30)
1152 DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31)
1153 DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN)
1154 DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN)
1155 DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3)
1156 DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4)
1157 DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5)
1158 DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6)
1159 DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7)
1160 DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8)
1161 DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9)
1162 DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10)
1163 DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11)
1164 DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12)
1165 DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13)
1166 DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14)
1167 DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15)
1168 DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16)
1169 DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17)
1170 DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18)
1171 DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19)
1172 DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20)
1173 DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21)
1174 DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22)
1175 DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23)
1176 DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24)
1177 DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25)
1178 DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26)
1179 DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27)
1180 DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28)
1181 DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29)
1182 DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30)
1183 DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31)
1184 DECLARE_CSR(mvendorid, CSR_MVENDORID)
1185 DECLARE_CSR(marchid, CSR_MARCHID)
1186 DECLARE_CSR(mimpid, CSR_MIMPID)
1187 DECLARE_CSR(mhartid, CSR_MHARTID)
1188 DECLARE_CSR(cycleh, CSR_CYCLEH)
1189 DECLARE_CSR(timeh, CSR_TIMEH)
1190 DECLARE_CSR(instreth, CSR_INSTRETH)
1191 DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H)
1192 DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H)
1193 DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H)
1194 DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H)
1195 DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H)
1196 DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H)
1197 DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H)
1198 DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H)
1199 DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H)
1200 DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H)
1201 DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H)
1202 DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H)
1203 DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H)
1204 DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H)
1205 DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H)
1206 DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H)
1207 DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H)
1208 DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H)
1209 DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H)
1210 DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H)
1211 DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H)
1212 DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H)
1213 DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H)
1214 DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H)
1215 DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H)
1216 DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H)
1217 DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H)
1218 DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H)
1219 DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H)
1220 DECLARE_CSR(mcycleh, CSR_MCYCLEH)
1221 DECLARE_CSR(minstreth, CSR_MINSTRETH)
1222 DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H)
1223 DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H)
1224 DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H)
1225 DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H)
1226 DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H)
1227 DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H)
1228 DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H)
1229 DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H)
1230 DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H)
1231 DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H)
1232 DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H)
1233 DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H)
1234 DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H)
1235 DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H)
1236 DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H)
1237 DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H)
1238 DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H)
1239 DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H)
1240 DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H)
1241 DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H)
1242 DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H)
1243 DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H)
1244 DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H)
1245 DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H)
1246 DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H)
1247 DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H)
1248 DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H)
1249 DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H)
1250 DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H)
1251 #endif
1252 #ifdef DECLARE_CAUSE
1253 DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
1254 DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH)
1255 DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION)
1256 DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT)
1257 DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD)
1258 DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD)
1259 DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE)
1260 DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE)
1261 DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL)
1262 DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL)
1263 DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL)
1264 DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL)
1265 #endif
1266 
#define DECLARE_CSR(name, num)
static RzILOpEffect * mul(cs_insn *insn, bool is_thumb)
Definition: arm_il32.c:539
static SblHeader sb
Definition: bin_mbn.c:26
static static fork const void static count static fd const char const char static newpath char char char static envp time
Definition: sflib.h:42
#define MATCH_AMOSWAP_D
Definition: riscv-opc.h:211
#define MASK_FSGNJX_D
Definition: riscv-opc.h:280
#define MATCH_C_NOP
Definition: riscv-opc.h:503
#define MASK_FSFLAGS
Definition: riscv-opc.h:16
#define CSR_MHPMEVENT6
Definition: riscv-opc.h:669
#define MATCH_FADD_Q
Definition: riscv-opc.h:291
#define MATCH_JALR
Definition: riscv-opc.h:57
#define MASK_FSW
Definition: riscv-opc.h:410
#define MATCH_SC_W
Definition: riscv-opc.h:193
#define MASK_C_FSDSP
Definition: riscv-opc.h:498
#define MATCH_LR_D
Definition: riscv-opc.h:213
#define CSR_MHPMEVENT29
Definition: riscv-opc.h:692
#define MATCH_CUSTOM1_RS1_RS2
Definition: riscv-opc.h:539
#define CSR_MHPMEVENT18
Definition: riscv-opc.h:681
#define MASK_FSUB_D
Definition: riscv-opc.h:270
#define MASK_AMOMINU_W
Definition: riscv-opc.h:186
#define CSR_HPMCOUNTER4
Definition: riscv-opc.h:578
#define CSR_INSTRET
Definition: riscv-opc.h:576
#define MATCH_FMV_X_S
Definition: riscv-opc.h:345
#define MATCH_FRFLAGS
Definition: riscv-opc.h:13
#define CSR_MHPMCOUNTER17H
Definition: riscv-opc.h:747
#define CSR_MHPMEVENT31
Definition: riscv-opc.h:694
#define MASK_FSQRT_D
Definition: riscv-opc.h:290
#define CSR_HPMCOUNTER29
Definition: riscv-opc.h:603
#define MATCH_C_SDSP
Definition: riscv-opc.h:521
#define MATCH_CUSTOM0_RS1_RS2
Definition: riscv-opc.h:527
#define CSR_HPMCOUNTER24
Definition: riscv-opc.h:598
#define MATCH_LH
Definition: riscv-opc.h:123
#define MATCH_LHU
Definition: riscv-opc.h:131
#define MATCH_AMOMAX_W
Definition: riscv-opc.h:183
#define MATCH_FCVT_Q_LU
Definition: riscv-opc.h:399
#define MASK_RDCYCLEH
Definition: riscv-opc.h:36
#define CSR_MHPMEVENT17
Definition: riscv-opc.h:680
#define MATCH_C_ANDI
Definition: riscv-opc.h:465
#define MATCH_FADD_S
Definition: riscv-opc.h:247
#define CAUSE_ILLEGAL_INSTRUCTION
Definition: riscv-opc.h:764
#define CSR_MHPMCOUNTER16
Definition: riscv-opc.h:648
#define MASK_ORI
Definition: riscv-opc.h:80
#define MASK_LBU
Definition: riscv-opc.h:130
#define MATCH_LUI
Definition: riscv-opc.h:61
#define MATCH_RDTIMEH
Definition: riscv-opc.h:37
#define MASK_FMSUB_S
Definition: riscv-opc.h:418
#define CSR_HPMCOUNTER25H
Definition: riscv-opc.h:724
#define MATCH_SFENCE_VM
Definition: riscv-opc.h:231
#define MATCH_CSRRW
Definition: riscv-opc.h:235
#define MATCH_FMADD_Q
Definition: riscv-opc.h:431
#define MATCH_FMIN_Q
Definition: riscv-opc.h:305
#define CSR_MBADADDR
Definition: riscv-opc.h:624
#define MASK_FMUL_D
Definition: riscv-opc.h:272
#define MATCH_ADDW
Definition: riscv-opc.h:111
#define MASK_FSGNJN_Q
Definition: riscv-opc.h:302
#define MASK_FMV_X_S
Definition: riscv-opc.h:346
#define MATCH_BGE
Definition: riscv-opc.h:51
#define MASK_C_BEQZ
Definition: riscv-opc.h:482
#define MASK_FMUL_Q
Definition: riscv-opc.h:296
#define MATCH_REMUW
Definition: riscv-opc.h:171
#define MASK_FCVT_D_S
Definition: riscv-opc.h:288
#define MATCH_C_ADDI
Definition: riscv-opc.h:453
#define CAUSE_MISALIGNED_LOAD
Definition: riscv-opc.h:766
#define MATCH_SLT
Definition: riscv-opc.h:89
#define MATCH_FMADD_D
Definition: riscv-opc.h:423
#define CSR_MHPMCOUNTER7H
Definition: riscv-opc.h:737
#define MASK_RDINSTRET
Definition: riscv-opc.h:34
#define MASK_ANDI
Definition: riscv-opc.h:82
#define MASK_DIVU
Definition: riscv-opc.h:158
#define CSR_MHPMEVENT20
Definition: riscv-opc.h:683
#define CSR_MHPMCOUNTER27H
Definition: riscv-opc.h:757
#define MATCH_JAL
Definition: riscv-opc.h:59
#define CSR_MHPMEVENT5
Definition: riscv-opc.h:668
#define MATCH_CUSTOM1_RD_RS1_RS2
Definition: riscv-opc.h:545
#define MASK_MULHSU
Definition: riscv-opc.h:152
#define CSR_MHPMCOUNTER25
Definition: riscv-opc.h:657
#define CSR_MHPMCOUNTER20
Definition: riscv-opc.h:652
#define MASK_LR_W
Definition: riscv-opc.h:192
#define MASK_FCVT_D_WU
Definition: riscv-opc.h:386
#define MASK_RDCYCLE
Definition: riscv-opc.h:30
#define CSR_HPMCOUNTER30
Definition: riscv-opc.h:604
#define MATCH_SLLI_RV32
Definition: riscv-opc.h:7
#define CSR_MHPMEVENT9
Definition: riscv-opc.h:672
#define MASK_C_LI
Definition: riscv-opc.h:458
#define CSR_MHPMCOUNTER28
Definition: riscv-opc.h:660
#define MATCH_SRA
Definition: riscv-opc.h:97
#define MASK_FCVT_D_LU
Definition: riscv-opc.h:390
#define MASK_FDIV_Q
Definition: riscv-opc.h:298
#define CAUSE_MACHINE_ECALL
Definition: riscv-opc.h:773
#define MASK_FMADD_D
Definition: riscv-opc.h:424
#define MASK_OR
Definition: riscv-opc.h:100
#define CSR_MHPMCOUNTER31
Definition: riscv-opc.h:663
#define MATCH_C_SLLI
Definition: riscv-opc.h:485
#define CSR_HPMCOUNTER22H
Definition: riscv-opc.h:721
#define MATCH_WFI
Definition: riscv-opc.h:233
#define MATCH_RDTIME
Definition: riscv-opc.h:31
#define CSR_MHPMEVENT13
Definition: riscv-opc.h:676
#define MASK_C_ADD
Definition: riscv-opc.h:496
#define CSR_MHPMCOUNTER18H
Definition: riscv-opc.h:748
#define MASK_AMOMAXU_D
Definition: riscv-opc.h:210
#define MATCH_BGEU
Definition: riscv-opc.h:55
#define MASK_FDIV_S
Definition: riscv-opc.h:254
#define MASK_FCVT_S_L
Definition: riscv-opc.h:378
#define MASK_LB
Definition: riscv-opc.h:122
#define MASK_CUSTOM3_RD_RS1
Definition: riscv-opc.h:568
#define CSR_MHPMCOUNTER21H
Definition: riscv-opc.h:751
#define MASK_FSGNJ_D
Definition: riscv-opc.h:276
#define MASK_FCVT_WU_Q
Definition: riscv-opc.h:364
#define MATCH_FSQ
Definition: riscv-opc.h:413
#define CSR_HPMCOUNTER12
Definition: riscv-opc.h:586
#define MASK_FCLASS_S
Definition: riscv-opc.h:348
#define CAUSE_FAULT_LOAD
Definition: riscv-opc.h:767
#define MATCH_FCVT_D_W
Definition: riscv-opc.h:383
#define MASK_FRFLAGS
Definition: riscv-opc.h:14
#define MATCH_OR
Definition: riscv-opc.h:99
#define MASK_FCVT_S_LU
Definition: riscv-opc.h:380
#define CSR_MINSTRET
Definition: riscv-opc.h:634
#define MATCH_FCLASS_Q
Definition: riscv-opc.h:371
#define MATCH_AUIPC
Definition: riscv-opc.h:63
#define MATCH_FCVT_D_L
Definition: riscv-opc.h:387
#define MATCH_CUSTOM1_RD_RS1
Definition: riscv-opc.h:543
#define MATCH_SRAI
Definition: riscv-opc.h:77
#define MASK_REMUW
Definition: riscv-opc.h:172
#define CSR_MTVEC
Definition: riscv-opc.h:620
#define MASK_AMOMINU_D
Definition: riscv-opc.h:208
#define MATCH_FCVT_Q_D
Definition: riscv-opc.h:315
#define MATCH_FCVT_W_Q
Definition: riscv-opc.h:361
#define CSR_HPMCOUNTER15H
Definition: riscv-opc.h:714
#define CSR_MHPMEVENT16
Definition: riscv-opc.h:679
#define MASK_CUSTOM2_RD_RS1
Definition: riscv-opc.h:556
#define MATCH_CSRRC
Definition: riscv-opc.h:239
#define MATCH_C_LW
Definition: riscv-opc.h:443
#define MATCH_CUSTOM0
Definition: riscv-opc.h:523
#define CSR_MSCRATCH
Definition: riscv-opc.h:621
#define MATCH_C_ADDW
Definition: riscv-opc.h:477
#define MASK_REMW
Definition: riscv-opc.h:170
#define MASK_FMSUB_Q
Definition: riscv-opc.h:434
#define MATCH_C_JALR
Definition: riscv-opc.h:509
#define MASK_FCVT_D_L
Definition: riscv-opc.h:388
#define MATCH_LWU
Definition: riscv-opc.h:133
#define MATCH_FSCSR
Definition: riscv-opc.h:25
#define MATCH_FDIV_D
Definition: riscv-opc.h:273
#define CSR_MHPMEVENT24
Definition: riscv-opc.h:687
#define MATCH_FCVT_W_D
Definition: riscv-opc.h:349
#define MATCH_BNE
Definition: riscv-opc.h:47
#define MASK_FMV_D_X
Definition: riscv-opc.h:392
#define MASK_CUSTOM1_RD_RS1
Definition: riscv-opc.h:544
#define CSR_HPMCOUNTER15
Definition: riscv-opc.h:589
#define MASK_C_ANDI
Definition: riscv-opc.h:466
#define MASK_SFENCE_VM
Definition: riscv-opc.h:232
#define MASK_C_JAL
Definition: riscv-opc.h:456
#define CSR_HPMCOUNTER12H
Definition: riscv-opc.h:711
#define MATCH_FCLASS_S
Definition: riscv-opc.h:347
#define MATCH_REMU
Definition: riscv-opc.h:161
#define MASK_ADDI
Definition: riscv-opc.h:66
#define CSR_HPMCOUNTER19H
Definition: riscv-opc.h:718
#define MATCH_FCVT_D_LU
Definition: riscv-opc.h:389
#define CSR_TIMEH
Definition: riscv-opc.h:700
#define MASK_C_ADDI
Definition: riscv-opc.h:454
#define MASK_FCVT_LU_Q
Definition: riscv-opc.h:368
#define CSR_MCAUSE
Definition: riscv-opc.h:623
#define CSR_MHPMCOUNTER28H
Definition: riscv-opc.h:758
#define MASK_SRL
Definition: riscv-opc.h:96
#define CSR_DSCRATCH
Definition: riscv-opc.h:632
#define MASK_FMAX_Q
Definition: riscv-opc.h:308
#define CSR_HPMCOUNTER3H
Definition: riscv-opc.h:702
#define MASK_C_ADDW
Definition: riscv-opc.h:478
#define MASK_AMOMAXU_W
Definition: riscv-opc.h:188
#define CSR_MHPMCOUNTER21
Definition: riscv-opc.h:653
#define MATCH_SRAIW
Definition: riscv-opc.h:109
#define CSR_MHPMCOUNTER9H
Definition: riscv-opc.h:739
#define CSR_MHPMCOUNTER7
Definition: riscv-opc.h:639
#define MATCH_FCVT_Q_W
Definition: riscv-opc.h:393
#define MATCH_FCVT_S_L
Definition: riscv-opc.h:377
#define MATCH_REMW
Definition: riscv-opc.h:169
#define MATCH_DIVU
Definition: riscv-opc.h:157
#define MASK_FLD
Definition: riscv-opc.h:406
#define CSR_TDATA3
Definition: riscv-opc.h:629
#define MATCH_FCVT_Q_S
Definition: riscv-opc.h:311
#define MASK_SB
Definition: riscv-opc.h:136
#define MASK_FCVT_Q_W
Definition: riscv-opc.h:394
#define CSR_MIP
Definition: riscv-opc.h:625
#define CSR_SEPC
Definition: riscv-opc.h:610
#define MATCH_BLT
Definition: riscv-opc.h:49
#define MASK_CSRRC
Definition: riscv-opc.h:240
#define MASK_FCVT_Q_S
Definition: riscv-opc.h:312
#define MASK_EBREAK
Definition: riscv-opc.h:220
#define MASK_SRAI
Definition: riscv-opc.h:78
#define CSR_MHPMCOUNTER29H
Definition: riscv-opc.h:759
#define MATCH_CSRRCI
Definition: riscv-opc.h:245
#define MASK_LUI
Definition: riscv-opc.h:62
#define MASK_CUSTOM0
Definition: riscv-opc.h:524
#define MATCH_FSGNJX_D
Definition: riscv-opc.h:279
#define MATCH_FNMADD_S
Definition: riscv-opc.h:421
#define MATCH_FMUL_Q
Definition: riscv-opc.h:295
#define MATCH_FCVT_WU_D
Definition: riscv-opc.h:351
#define MASK_BGEU
Definition: riscv-opc.h:56
#define CSR_MHPMCOUNTER26
Definition: riscv-opc.h:658
#define CSR_MHPMCOUNTER14
Definition: riscv-opc.h:646
#define MATCH_C_SW
Definition: riscv-opc.h:449
#define MATCH_CUSTOM3_RD_RS1_RS2
Definition: riscv-opc.h:569
#define CSR_MHPMCOUNTER10H
Definition: riscv-opc.h:740
#define MASK_MRET
Definition: riscv-opc.h:228
#define MATCH_C_FSW
Definition: riscv-opc.h:451
#define MATCH_CUSTOM2_RS1_RS2
Definition: riscv-opc.h:551
#define MASK_C_SRAI
Definition: riscv-opc.h:464
#define MASK_FCVT_L_D
Definition: riscv-opc.h:354
#define MASK_ECALL
Definition: riscv-opc.h:218
#define CSR_HPMCOUNTER4H
Definition: riscv-opc.h:703
#define CSR_MSCOUNTEREN
Definition: riscv-opc.h:665
#define MASK_CUSTOM1_RS1_RS2
Definition: riscv-opc.h:540
#define MASK_AND
Definition: riscv-opc.h:102
#define MATCH_C_FSWSP
Definition: riscv-opc.h:501
#define CSR_MHPMCOUNTER6
Definition: riscv-opc.h:638
#define MASK_FCVT_W_S
Definition: riscv-opc.h:338
#define MASK_JALR
Definition: riscv-opc.h:58
#define CSR_HPMCOUNTER10
Definition: riscv-opc.h:584
#define CSR_HPMCOUNTER14
Definition: riscv-opc.h:588
#define MASK_FMADD_S
Definition: riscv-opc.h:416
#define MATCH_FMIN_S
Definition: riscv-opc.h:261
#define MASK_C_LWSP
Definition: riscv-opc.h:490
#define MASK_FCVT_W_Q
Definition: riscv-opc.h:362
#define MASK_CUSTOM2_RS1
Definition: riscv-opc.h:550
#define MATCH_FCVT_S_D
Definition: riscv-opc.h:285
#define MASK_C_SWSP
Definition: riscv-opc.h:500
#define MATCH_FSGNJ_Q
Definition: riscv-opc.h:299
#define MASK_FLT_S
Definition: riscv-opc.h:322
#define CSR_MHPMCOUNTER5
Definition: riscv-opc.h:637
#define CSR_MHPMCOUNTER11H
Definition: riscv-opc.h:741
#define CSR_MHPMEVENT26
Definition: riscv-opc.h:689
#define CSR_SCAUSE
Definition: riscv-opc.h:611
#define MASK_SD
Definition: riscv-opc.h:142
#define MATCH_FSD
Definition: riscv-opc.h:411
#define MATCH_FCVT_S_LU
Definition: riscv-opc.h:379
#define MATCH_SC_D
Definition: riscv-opc.h:215
#define MASK_C_AND
Definition: riscv-opc.h:474
#define MASK_FNMSUB_S
Definition: riscv-opc.h:420
#define MASK_SUB
Definition: riscv-opc.h:86
#define MASK_SLLI
Definition: riscv-opc.h:68
#define CSR_TIME
Definition: riscv-opc.h:575
#define CSR_HPMCOUNTER9H
Definition: riscv-opc.h:708
#define MASK_FMADD_Q
Definition: riscv-opc.h:432
#define MASK_SLTU
Definition: riscv-opc.h:92
#define CSR_MHPMCOUNTER12H
Definition: riscv-opc.h:742
#define MATCH_CUSTOM0_RS1
Definition: riscv-opc.h:525
#define MATCH_FLE_Q
Definition: riscv-opc.h:331
#define MATCH_CUSTOM1_RS1
Definition: riscv-opc.h:537
#define CSR_MHPMEVENT21
Definition: riscv-opc.h:684
#define MASK_FCVT_L_Q
Definition: riscv-opc.h:366
#define CSR_MIMPID
Definition: riscv-opc.h:697
#define CSR_MHARTID
Definition: riscv-opc.h:698
#define MATCH_FMV_D_X
Definition: riscv-opc.h:391
#define MASK_SLLI_RV32
Definition: riscv-opc.h:8
#define CSR_MARCHID
Definition: riscv-opc.h:696
#define MATCH_FCVT_LU_S
Definition: riscv-opc.h:343
#define CSR_HPMCOUNTER31H
Definition: riscv-opc.h:730
#define CSR_MEPC
Definition: riscv-opc.h:622
#define CSR_SSCRATCH
Definition: riscv-opc.h:609
#define MASK_ADDW
Definition: riscv-opc.h:112
#define MATCH_FLT_S
Definition: riscv-opc.h:321
#define CSR_HPMCOUNTER28
Definition: riscv-opc.h:602
#define CSR_MHPMCOUNTER25H
Definition: riscv-opc.h:755
#define MATCH_FEQ_Q
Definition: riscv-opc.h:335
#define MATCH_SRAI_RV32
Definition: riscv-opc.h:11
#define MASK_CUSTOM3
Definition: riscv-opc.h:560
#define MATCH_FSGNJN_S
Definition: riscv-opc.h:257
#define MATCH_FCVT_LU_Q
Definition: riscv-opc.h:367
#define MATCH_CUSTOM0_RD_RS1_RS2
Definition: riscv-opc.h:533
#define MATCH_FSUB_D
Definition: riscv-opc.h:269
#define MATCH_LR_W
Definition: riscv-opc.h:191
#define MATCH_FMIN_D
Definition: riscv-opc.h:281
#define MATCH_C_EBREAK
Definition: riscv-opc.h:511
#define MASK_AMOMIN_W
Definition: riscv-opc.h:182
#define MATCH_FMAX_Q
Definition: riscv-opc.h:307
#define MASK_URET
Definition: riscv-opc.h:222
#define MATCH_DIVW
Definition: riscv-opc.h:165
#define MASK_C_MV
Definition: riscv-opc.h:494
#define CSR_MCYCLE
Definition: riscv-opc.h:633
#define MASK_JAL
Definition: riscv-opc.h:60
#define MATCH_CUSTOM2
Definition: riscv-opc.h:547
#define MATCH_FEQ_S
Definition: riscv-opc.h:323
#define MASK_C_FLW
Definition: riscv-opc.h:446
#define CSR_MHPMEVENT3
Definition: riscv-opc.h:666
#define MATCH_FLW
Definition: riscv-opc.h:403
#define CSR_HPMCOUNTER6H
Definition: riscv-opc.h:705
#define MATCH_C_AND
Definition: riscv-opc.h:473
#define CSR_MHPMCOUNTER26H
Definition: riscv-opc.h:756
#define CSR_HPMCOUNTER27H
Definition: riscv-opc.h:726
#define MATCH_CSRRS
Definition: riscv-opc.h:237
#define MATCH_C_ADDI16SP
Definition: riscv-opc.h:505
#define MASK_CUSTOM3_RD_RS1_RS2
Definition: riscv-opc.h:570
#define MATCH_SRLI_RV32
Definition: riscv-opc.h:9
#define CSR_HPMCOUNTER17H
Definition: riscv-opc.h:716
#define CSR_MHPMCOUNTER5H
Definition: riscv-opc.h:735
#define CSR_HPMCOUNTER21H
Definition: riscv-opc.h:720
#define MATCH_LW
Definition: riscv-opc.h:125
#define MASK_C_ADDI16SP
Definition: riscv-opc.h:506
#define MATCH_AMOMINU_W
Definition: riscv-opc.h:185
#define CSR_HPMCOUNTER6
Definition: riscv-opc.h:580
#define MATCH_DIV
Definition: riscv-opc.h:155
#define MATCH_FMSUB_D
Definition: riscv-opc.h:425
#define MASK_FSD
Definition: riscv-opc.h:412
#define CSR_MHPMEVENT14
Definition: riscv-opc.h:677
#define MASK_LHU
Definition: riscv-opc.h:132
#define CSR_SSTATUS
Definition: riscv-opc.h:606
#define MATCH_FSGNJ_S
Definition: riscv-opc.h:255
#define CSR_TSELECT
Definition: riscv-opc.h:626
#define MATCH_FDIV_S
Definition: riscv-opc.h:253
#define MATCH_C_FSD
Definition: riscv-opc.h:447
#define MATCH_LBU
Definition: riscv-opc.h:129
#define MATCH_FCVT_WU_S
Definition: riscv-opc.h:339
#define MASK_SRLI
Definition: riscv-opc.h:76
#define CSR_MHPMEVENT27
Definition: riscv-opc.h:690
#define MASK_FSCSR
Definition: riscv-opc.h:26
#define MATCH_FNMSUB_Q
Definition: riscv-opc.h:435
#define MATCH_SH
Definition: riscv-opc.h:137
#define CSR_MHPMCOUNTER24H
Definition: riscv-opc.h:754
#define MASK_FCVT_Q_D
Definition: riscv-opc.h:316
#define MASK_SRET
Definition: riscv-opc.h:224
#define MATCH_CUSTOM3_RS1_RS2
Definition: riscv-opc.h:563
#define CSR_HPMCOUNTER18H
Definition: riscv-opc.h:717
#define MATCH_FCVT_Q_WU
Definition: riscv-opc.h:395
#define MASK_C_ADDIW
Definition: riscv-opc.h:518
#define MATCH_REM
Definition: riscv-opc.h:159
#define MASK_FNMSUB_D
Definition: riscv-opc.h:428
#define MATCH_FCVT_S_W
Definition: riscv-opc.h:373
#define MASK_CUSTOM2_RD_RS1_RS2
Definition: riscv-opc.h:558
#define MASK_C_SDSP
Definition: riscv-opc.h:522
#define MASK_SRLIW
Definition: riscv-opc.h:108
#define CSR_MUCOUNTEREN
Definition: riscv-opc.h:664
#define MATCH_LB
Definition: riscv-opc.h:121
#define MATCH_C_SD
Definition: riscv-opc.h:515
#define MATCH_AMOOR_W
Definition: riscv-opc.h:177
#define CSR_MSTATUS
Definition: riscv-opc.h:615
#define MASK_FEQ_Q
Definition: riscv-opc.h:336
#define CSR_MHPMCOUNTER8H
Definition: riscv-opc.h:738
#define MASK_FSRMI
Definition: riscv-opc.h:24
#define CSR_MHPMCOUNTER3H
Definition: riscv-opc.h:733
#define MATCH_ADD
Definition: riscv-opc.h:83
#define MASK_C_FLD
Definition: riscv-opc.h:442
#define MATCH_CUSTOM2_RD
Definition: riscv-opc.h:553
#define MASK_SLT
Definition: riscv-opc.h:90
#define MASK_FCVT_Q_WU
Definition: riscv-opc.h:396
#define MASK_C_SUBW
Definition: riscv-opc.h:476
#define MASK_FEQ_D
Definition: riscv-opc.h:330
#define CSR_HPMCOUNTER5
Definition: riscv-opc.h:579
#define MASK_FCLASS_Q
Definition: riscv-opc.h:372
#define MATCH_EBREAK
Definition: riscv-opc.h:219
#define MASK_SLL
Definition: riscv-opc.h:88
#define MATCH_RDINSTRET
Definition: riscv-opc.h:33
#define MASK_FSQRT_Q
Definition: riscv-opc.h:318
#define CSR_HPMCOUNTER14H
Definition: riscv-opc.h:713
#define CSR_MHPMCOUNTER12
Definition: riscv-opc.h:644
#define MASK_FMUL_S
Definition: riscv-opc.h:252
#define CSR_HPMCOUNTER21
Definition: riscv-opc.h:595
#define CSR_MHPMCOUNTER20H
Definition: riscv-opc.h:750
#define MATCH_CUSTOM3
Definition: riscv-opc.h:559
#define MASK_CUSTOM0_RD_RS1_RS2
Definition: riscv-opc.h:534
#define MASK_BEQ
Definition: riscv-opc.h:46
#define CAUSE_FAULT_STORE
Definition: riscv-opc.h:769
#define MASK_C_XOR
Definition: riscv-opc.h:470
#define MATCH_FMV_S_X
Definition: riscv-opc.h:381
#define MASK_AMOAND_W
Definition: riscv-opc.h:180
#define MATCH_FRCSR
Definition: riscv-opc.h:27
#define CSR_HPMCOUNTER20
Definition: riscv-opc.h:594
#define MASK_SRA
Definition: riscv-opc.h:98
#define MASK_AMOSWAP_D
Definition: riscv-opc.h:212
#define MATCH_FENCE_I
Definition: riscv-opc.h:145
#define MASK_ADDIW
Definition: riscv-opc.h:104
#define MASK_CSRRS
Definition: riscv-opc.h:238
#define MATCH_FENCE
Definition: riscv-opc.h:143
#define CSR_MHPMEVENT19
Definition: riscv-opc.h:682
#define MATCH_AMOSWAP_W
Definition: riscv-opc.h:189
#define MASK_LWU
Definition: riscv-opc.h:134
#define MATCH_MULH
Definition: riscv-opc.h:149
#define MATCH_URET
Definition: riscv-opc.h:221
#define MATCH_CUSTOM2_RS1
Definition: riscv-opc.h:549
#define MATCH_HRET
Definition: riscv-opc.h:225
#define MASK_LD
Definition: riscv-opc.h:128
#define CSR_DPC
Definition: riscv-opc.h:631
#define MASK_SLLW
Definition: riscv-opc.h:116
#define MASK_FCVT_D_W
Definition: riscv-opc.h:384
#define MATCH_FCVT_L_Q
Definition: riscv-opc.h:365
#define MATCH_FCVT_WU_Q
Definition: riscv-opc.h:363
#define MASK_FNMSUB_Q
Definition: riscv-opc.h:436
#define MATCH_C_J
Definition: riscv-opc.h:479
#define MATCH_SCALL
Definition: riscv-opc.h:41
#define MASK_BLTU
Definition: riscv-opc.h:54
#define MASK_FMIN_D
Definition: riscv-opc.h:282
#define MATCH_FSGNJX_S
Definition: riscv-opc.h:259
#define MASK_SCALL
Definition: riscv-opc.h:42
#define MATCH_FNMSUB_D
Definition: riscv-opc.h:427
#define MATCH_SLTIU
Definition: riscv-opc.h:71
#define MASK_FCVT_D_Q
Definition: riscv-opc.h:314
#define MATCH_FNMADD_Q
Definition: riscv-opc.h:437
#define MATCH_ECALL
Definition: riscv-opc.h:217
#define MATCH_RDCYCLE
Definition: riscv-opc.h:29
#define CSR_MHPMEVENT15
Definition: riscv-opc.h:678
#define MASK_FSGNJX_S
Definition: riscv-opc.h:260
#define MATCH_ANDI
Definition: riscv-opc.h:81
#define MATCH_RDCYCLEH
Definition: riscv-opc.h:35
#define MATCH_MULHU
Definition: riscv-opc.h:153
#define MASK_FSRM
Definition: riscv-opc.h:22
#define MATCH_FCLASS_D
Definition: riscv-opc.h:359
#define MASK_FLE_Q
Definition: riscv-opc.h:332
#define MASK_SRAIW
Definition: riscv-opc.h:110
#define MASK_XOR
Definition: riscv-opc.h:94
#define MATCH_CUSTOM0_RD_RS1
Definition: riscv-opc.h:531
#define MASK_WFI
Definition: riscv-opc.h:234
#define MATCH_MULHSU
Definition: riscv-opc.h:151
#define MATCH_CUSTOM3_RD_RS1
Definition: riscv-opc.h:567
#define MASK_CSRRW
Definition: riscv-opc.h:236
#define MASK_FENCE_I
Definition: riscv-opc.h:146
#define MASK_SLTI
Definition: riscv-opc.h:70
#define MATCH_CUSTOM3_RD
Definition: riscv-opc.h:565
#define MASK_FADD_S
Definition: riscv-opc.h:248
#define MATCH_AMOOR_D
Definition: riscv-opc.h:199
#define MATCH_FSRMI
Definition: riscv-opc.h:23
#define MATCH_FLE_S
Definition: riscv-opc.h:319
#define MASK_CUSTOM3_RS1
Definition: riscv-opc.h:562
#define CAUSE_HYPERVISOR_ECALL
Definition: riscv-opc.h:772
#define MATCH_C_LWSP
Definition: riscv-opc.h:489
#define CSR_HPMCOUNTER28H
Definition: riscv-opc.h:727
#define MATCH_FMSUB_S
Definition: riscv-opc.h:417
#define MATCH_AMOADD_W
Definition: riscv-opc.h:173
#define MATCH_AND
Definition: riscv-opc.h:101
#define MASK_CUSTOM2
Definition: riscv-opc.h:548
#define CSR_MHPMEVENT11
Definition: riscv-opc.h:674
#define MASK_AMOXOR_D
Definition: riscv-opc.h:198
#define MATCH_SLTI
Definition: riscv-opc.h:69
#define CSR_MHPMEVENT4
Definition: riscv-opc.h:667
#define MASK_AMOADD_D
Definition: riscv-opc.h:196
#define MASK_DIVUW
Definition: riscv-opc.h:168
#define MASK_SUBW
Definition: riscv-opc.h:114
#define CSR_MHPMCOUNTER31H
Definition: riscv-opc.h:761
#define CSR_MHPMCOUNTER8
Definition: riscv-opc.h:640
#define MASK_SRAW
Definition: riscv-opc.h:120
#define MATCH_C_ADDI4SPN
Definition: riscv-opc.h:439
#define MASK_SH
Definition: riscv-opc.h:138
#define MASK_C_SD
Definition: riscv-opc.h:516
#define CSR_MHPMCOUNTER9
Definition: riscv-opc.h:641
#define MATCH_AMOMAX_D
Definition: riscv-opc.h:205
#define MATCH_FCVT_Q_L
Definition: riscv-opc.h:397
#define MATCH_FCVT_L_S
Definition: riscv-opc.h:341
#define MATCH_C_LDSP
Definition: riscv-opc.h:519
#define MATCH_DIVUW
Definition: riscv-opc.h:167
#define MATCH_FSQRT_S
Definition: riscv-opc.h:265
#define MATCH_C_BEQZ
Definition: riscv-opc.h:481
#define MATCH_FADD_D
Definition: riscv-opc.h:267
#define MASK_FSUB_S
Definition: riscv-opc.h:250
#define MATCH_AMOMIN_D
Definition: riscv-opc.h:203
#define MASK_FMAX_D
Definition: riscv-opc.h:284
#define MASK_FCVT_WU_D
Definition: riscv-opc.h:352
#define MATCH_SRLW
Definition: riscv-opc.h:117
#define MASK_AUIPC
Definition: riscv-opc.h:64
#define CSR_HPMCOUNTER22
Definition: riscv-opc.h:596
#define MATCH_SB
Definition: riscv-opc.h:135
#define MATCH_FMUL_D
Definition: riscv-opc.h:271
#define MASK_CUSTOM1_RD
Definition: riscv-opc.h:542
#define MASK_C_OR
Definition: riscv-opc.h:472
#define MASK_FLE_D
Definition: riscv-opc.h:326
#define MATCH_RDINSTRETH
Definition: riscv-opc.h:39
#define MASK_FLQ
Definition: riscv-opc.h:408
#define CSR_MHPMCOUNTER6H
Definition: riscv-opc.h:736
#define CSR_CYCLE
Definition: riscv-opc.h:574
#define MASK_CUSTOM1_RD_RS1_RS2
Definition: riscv-opc.h:546
#define MASK_FCLASS_D
Definition: riscv-opc.h:360
#define CSR_HPMCOUNTER16H
Definition: riscv-opc.h:715
#define MATCH_C_FLWSP
Definition: riscv-opc.h:491
#define MASK_BLT
Definition: riscv-opc.h:50
#define CAUSE_MISALIGNED_FETCH
Definition: riscv-opc.h:762
#define MASK_FMIN_Q
Definition: riscv-opc.h:306
#define MATCH_C_FSDSP
Definition: riscv-opc.h:497
#define MASK_C_LUI
Definition: riscv-opc.h:460
#define CSR_TDATA1
Definition: riscv-opc.h:627
#define MATCH_ORI
Definition: riscv-opc.h:79
#define MATCH_CUSTOM0_RD
Definition: riscv-opc.h:529
#define MASK_C_FSWSP
Definition: riscv-opc.h:502
#define MASK_AMOOR_D
Definition: riscv-opc.h:200
#define CSR_MHPMCOUNTER23H
Definition: riscv-opc.h:753
#define MASK_CUSTOM2_RD
Definition: riscv-opc.h:554
#define MASK_ADD
Definition: riscv-opc.h:84
#define MASK_FCVT_W_D
Definition: riscv-opc.h:350
#define MATCH_DRET
Definition: riscv-opc.h:229
#define MASK_SW
Definition: riscv-opc.h:140
#define CSR_MINSTRETH
Definition: riscv-opc.h:732
#define MASK_C_SW
Definition: riscv-opc.h:450
#define MATCH_FSFLAGSI
Definition: riscv-opc.h:17
#define CSR_MHPMEVENT8
Definition: riscv-opc.h:671
#define CSR_HPMCOUNTER20H
Definition: riscv-opc.h:719
#define MASK_FADD_Q
Definition: riscv-opc.h:292
#define CSR_MHPMCOUNTER17
Definition: riscv-opc.h:649
#define CSR_MHPMCOUNTER11
Definition: riscv-opc.h:643
#define MATCH_SRLIW
Definition: riscv-opc.h:107
#define CSR_DCSR
Definition: riscv-opc.h:630
#define MATCH_FCVT_L_D
Definition: riscv-opc.h:353
#define MASK_FLE_S
Definition: riscv-opc.h:320
#define MASK_FMV_S_X
Definition: riscv-opc.h:382
#define MATCH_BEQ
Definition: riscv-opc.h:45
#define MASK_REMU
Definition: riscv-opc.h:162
#define MASK_CUSTOM0_RD
Definition: riscv-opc.h:530
#define CSR_MISA
Definition: riscv-opc.h:616
#define MASK_C_LDSP
Definition: riscv-opc.h:520
#define MASK_C_NOP
Definition: riscv-opc.h:504
#define MATCH_FLD
Definition: riscv-opc.h:405
#define MATCH_XOR
Definition: riscv-opc.h:93
#define CSR_FRM
Definition: riscv-opc.h:572
#define CAUSE_BREAKPOINT
Definition: riscv-opc.h:765
#define MASK_C_J
Definition: riscv-opc.h:480
#define CSR_HPMCOUNTER31
Definition: riscv-opc.h:605
#define MASK_FCVT_Q_LU
Definition: riscv-opc.h:400
#define CSR_MHPMEVENT7
Definition: riscv-opc.h:670
#define MATCH_CUSTOM2_RD_RS1_RS2
Definition: riscv-opc.h:557
#define CSR_SPTBR
Definition: riscv-opc.h:614
#define MASK_FSQRT_S
Definition: riscv-opc.h:266
#define MASK_SRAI_RV32
Definition: riscv-opc.h:12
#define MASK_CUSTOM1_RS1
Definition: riscv-opc.h:538
#define MASK_C_FSD
Definition: riscv-opc.h:448
#define CSR_HPMCOUNTER9
Definition: riscv-opc.h:583
#define MASK_CUSTOM0_RD_RS1
Definition: riscv-opc.h:532
#define CSR_MHPMCOUNTER15H
Definition: riscv-opc.h:745
#define MATCH_ADDIW
Definition: riscv-opc.h:103
#define CSR_STVEC
Definition: riscv-opc.h:608
#define MATCH_C_LI
Definition: riscv-opc.h:457
#define CSR_MEDELEG
Definition: riscv-opc.h:617
#define CSR_HPMCOUNTER23H
Definition: riscv-opc.h:722
#define MASK_AMOMAX_D
Definition: riscv-opc.h:206
#define MATCH_FSFLAGS
Definition: riscv-opc.h:15
#define MATCH_FSUB_Q
Definition: riscv-opc.h:293
#define CSR_MHPMCOUNTER3
Definition: riscv-opc.h:635
#define MASK_FRCSR
Definition: riscv-opc.h:28
#define CSR_HPMCOUNTER30H
Definition: riscv-opc.h:729
#define CSR_MHPMCOUNTER10
Definition: riscv-opc.h:642
#define MATCH_SLL
Definition: riscv-opc.h:87
#define MASK_AMOXOR_W
Definition: riscv-opc.h:176
#define MASK_FMV_Q_X
Definition: riscv-opc.h:402
#define CSR_MHPMCOUNTER14H
Definition: riscv-opc.h:744
#define MATCH_FSGNJX_Q
Definition: riscv-opc.h:303
#define MASK_FMSUB_D
Definition: riscv-opc.h:426
#define MATCH_C_LD
Definition: riscv-opc.h:513
#define MASK_FCVT_LU_D
Definition: riscv-opc.h:356
#define MASK_FMAX_S
Definition: riscv-opc.h:264
#define MASK_FMV_X_Q
Definition: riscv-opc.h:370
#define MASK_FSUB_Q
Definition: riscv-opc.h:294
#define MATCH_SRLI
Definition: riscv-opc.h:75
#define MASK_MULH
Definition: riscv-opc.h:150
#define MATCH_CUSTOM1
Definition: riscv-opc.h:535
#define MASK_FSGNJN_S
Definition: riscv-opc.h:258
#define CSR_HPMCOUNTER18
Definition: riscv-opc.h:592
#define MATCH_CUSTOM2_RD_RS1
Definition: riscv-opc.h:555
#define CSR_MHPMCOUNTER29
Definition: riscv-opc.h:661
#define MATCH_MULW
Definition: riscv-opc.h:163
#define MASK_RDTIME
Definition: riscv-opc.h:32
#define CSR_MHPMCOUNTER4
Definition: riscv-opc.h:636
#define CAUSE_FAULT_FETCH
Definition: riscv-opc.h:763
#define MASK_FSGNJX_Q
Definition: riscv-opc.h:304
#define MASK_DRET
Definition: riscv-opc.h:230
#define MATCH_FCVT_LU_D
Definition: riscv-opc.h:355
#define MASK_SC_W
Definition: riscv-opc.h:194
#define MASK_SC_D
Definition: riscv-opc.h:216
#define MASK_C_LW
Definition: riscv-opc.h:444
#define MATCH_C_ADDIW
Definition: riscv-opc.h:517
#define CSR_FCSR
Definition: riscv-opc.h:573
#define CSR_TDATA2
Definition: riscv-opc.h:628
#define CSR_HPMCOUNTER17
Definition: riscv-opc.h:591
#define MASK_FCVT_S_WU
Definition: riscv-opc.h:376
#define CSR_HPMCOUNTER3
Definition: riscv-opc.h:577
#define MATCH_FSQRT_Q
Definition: riscv-opc.h:317
#define MATCH_SLLIW
Definition: riscv-opc.h:105
#define MASK_RDTIMEH
Definition: riscv-opc.h:38
#define MATCH_SUBW
Definition: riscv-opc.h:113
#define MATCH_AMOMIN_W
Definition: riscv-opc.h:181
#define MASK_FMV_X_D
Definition: riscv-opc.h:358
#define MASK_C_FLWSP
Definition: riscv-opc.h:492
#define MATCH_C_JR
Definition: riscv-opc.h:507
#define CSR_HPMCOUNTER5H
Definition: riscv-opc.h:704
#define MASK_FSGNJ_S
Definition: riscv-opc.h:256
#define MATCH_C_FLW
Definition: riscv-opc.h:445
#define MASK_CUSTOM3_RD
Definition: riscv-opc.h:566
#define CSR_HPMCOUNTER13H
Definition: riscv-opc.h:712
#define CSR_MHPMEVENT12
Definition: riscv-opc.h:675
#define CAUSE_SUPERVISOR_ECALL
Definition: riscv-opc.h:771
#define CSR_MVENDORID
Definition: riscv-opc.h:695
#define MATCH_C_LUI
Definition: riscv-opc.h:459
#define MATCH_FSQRT_D
Definition: riscv-opc.h:289
#define CSR_SBADADDR
Definition: riscv-opc.h:612
#define MATCH_SW
Definition: riscv-opc.h:139
#define MASK_AMOADD_W
Definition: riscv-opc.h:174
#define MASK_HRET
Definition: riscv-opc.h:226
#define MASK_FCVT_Q_L
Definition: riscv-opc.h:398
#define MASK_FEQ_S
Definition: riscv-opc.h:324
#define MATCH_SD
Definition: riscv-opc.h:141
#define CSR_SIP
Definition: riscv-opc.h:613
#define MASK_CSRRWI
Definition: riscv-opc.h:242
#define MATCH_AMOMAXU_W
Definition: riscv-opc.h:187
#define MASK_MULW
Definition: riscv-opc.h:164
#define MATCH_FSRM
Definition: riscv-opc.h:21
#define MASK_AMOMIN_D
Definition: riscv-opc.h:204
#define MASK_FADD_D
Definition: riscv-opc.h:268
#define CSR_HPMCOUNTER11
Definition: riscv-opc.h:585
#define MASK_C_SRLI
Definition: riscv-opc.h:462
#define MATCH_FMUL_S
Definition: riscv-opc.h:251
#define CSR_MHPMCOUNTER27
Definition: riscv-opc.h:659
#define MATCH_AMOXOR_W
Definition: riscv-opc.h:175
#define MATCH_FMADD_S
Definition: riscv-opc.h:415
#define CSR_HPMCOUNTER7H
Definition: riscv-opc.h:706
#define CSR_MHPMCOUNTER18
Definition: riscv-opc.h:650
#define MASK_FLW
Definition: riscv-opc.h:404
#define MATCH_AMOAND_D
Definition: riscv-opc.h:201
#define MASK_SRLI_RV32
Definition: riscv-opc.h:10
#define MASK_SBREAK
Definition: riscv-opc.h:44
#define CSR_MHPMEVENT25
Definition: riscv-opc.h:688
#define CSR_MHPMCOUNTER13H
Definition: riscv-opc.h:743
#define CSR_HPMCOUNTER16
Definition: riscv-opc.h:590
#define MASK_C_FSW
Definition: riscv-opc.h:452
#define MATCH_AMOXOR_D
Definition: riscv-opc.h:197
#define CSR_HPMCOUNTER26H
Definition: riscv-opc.h:725
#define MATCH_C_XOR
Definition: riscv-opc.h:469
#define MATCH_FLT_D
Definition: riscv-opc.h:327
#define MATCH_SRET
Definition: riscv-opc.h:223
#define MASK_XORI
Definition: riscv-opc.h:74
#define MASK_FCVT_S_W
Definition: riscv-opc.h:374
#define MATCH_C_JAL
Definition: riscv-opc.h:455
#define CSR_HPMCOUNTER27
Definition: riscv-opc.h:601
#define MATCH_FSGNJN_D
Definition: riscv-opc.h:277
#define MATCH_FMAX_S
Definition: riscv-opc.h:263
#define MASK_CUSTOM2_RS1_RS2
Definition: riscv-opc.h:552
#define CAUSE_USER_ECALL
Definition: riscv-opc.h:770
#define CSR_HPMCOUNTER23
Definition: riscv-opc.h:597
#define CSR_MHPMCOUNTER4H
Definition: riscv-opc.h:734
#define MASK_AMOSWAP_W
Definition: riscv-opc.h:190
#define MATCH_FNMADD_D
Definition: riscv-opc.h:429
#define CSR_MHPMCOUNTER23
Definition: riscv-opc.h:655
#define MASK_FLT_D
Definition: riscv-opc.h:328
#define MATCH_C_MV
Definition: riscv-opc.h:493
#define CSR_HPMCOUNTER13
Definition: riscv-opc.h:587
#define MATCH_SRL
Definition: riscv-opc.h:95
#define MATCH_SLLI
Definition: riscv-opc.h:67
#define CSR_MHPMCOUNTER24
Definition: riscv-opc.h:656
#define MASK_AMOAND_D
Definition: riscv-opc.h:202
#define MASK_C_JALR
Definition: riscv-opc.h:510
#define MASK_BGE
Definition: riscv-opc.h:52
#define MASK_C_SLLI
Definition: riscv-opc.h:486
#define CSR_HPMCOUNTER7
Definition: riscv-opc.h:581
#define CAUSE_MISALIGNED_STORE
Definition: riscv-opc.h:768
#define MATCH_CSRRSI
Definition: riscv-opc.h:243
#define MATCH_C_SUB
Definition: riscv-opc.h:467
#define MASK_C_LD
Definition: riscv-opc.h:514
#define CSR_HPMCOUNTER26
Definition: riscv-opc.h:600
#define MASK_MUL
Definition: riscv-opc.h:148
#define MASK_LR_D
Definition: riscv-opc.h:214
#define MASK_DIV
Definition: riscv-opc.h:156
#define MASK_CUSTOM0_RS1
Definition: riscv-opc.h:526
#define MASK_FNMADD_Q
Definition: riscv-opc.h:438
#define MASK_FSGNJN_D
Definition: riscv-opc.h:278
#define MATCH_FMAX_D
Definition: riscv-opc.h:283
#define MATCH_AMOAND_W
Definition: riscv-opc.h:179
#define MASK_FCVT_S_D
Definition: riscv-opc.h:286
#define MATCH_FMV_X_Q
Definition: riscv-opc.h:369
#define MASK_SLLIW
Definition: riscv-opc.h:106
#define MASK_AMOOR_W
Definition: riscv-opc.h:178
#define CSR_MHPMCOUNTER15
Definition: riscv-opc.h:647
#define MATCH_FCVT_D_WU
Definition: riscv-opc.h:385
#define MASK_C_SUB
Definition: riscv-opc.h:468
#define MASK_FCVT_L_S
Definition: riscv-opc.h:342
#define MASK_CSRRCI
Definition: riscv-opc.h:246
#define CSR_MHPMCOUNTER22
Definition: riscv-opc.h:654
#define MASK_SRLW
Definition: riscv-opc.h:118
#define MASK_AMOMAX_W
Definition: riscv-opc.h:184
#define MATCH_BLTU
Definition: riscv-opc.h:53
#define CSR_HPMCOUNTER8H
Definition: riscv-opc.h:707
#define MASK_C_EBREAK
Definition: riscv-opc.h:512
#define MATCH_FSGNJ_D
Definition: riscv-opc.h:275
#define CSR_MCYCLEH
Definition: riscv-opc.h:731
#define MASK_C_FLDSP
Definition: riscv-opc.h:488
#define CSR_MHPMCOUNTER13
Definition: riscv-opc.h:645
#define MATCH_CUSTOM1_RD
Definition: riscv-opc.h:541
#define MASK_CUSTOM0_RS1_RS2
Definition: riscv-opc.h:528
#define CSR_MIDELEG
Definition: riscv-opc.h:618
#define MASK_FCVT_S_Q
Definition: riscv-opc.h:310
#define MASK_C_BNEZ
Definition: riscv-opc.h:484
#define MATCH_FCVT_D_Q
Definition: riscv-opc.h:313
#define MASK_C_ADDI4SPN
Definition: riscv-opc.h:440
#define MATCH_FMV_X_D
Definition: riscv-opc.h:357
#define MATCH_CUSTOM3_RS1
Definition: riscv-opc.h:561
#define MATCH_FLQ
Definition: riscv-opc.h:407
#define MATCH_FSGNJN_Q
Definition: riscv-opc.h:301
#define MASK_LH
Definition: riscv-opc.h:124
#define CSR_MIE
Definition: riscv-opc.h:619
#define MATCH_AMOMINU_D
Definition: riscv-opc.h:207
#define MASK_LW
Definition: riscv-opc.h:126
#define MATCH_AMOADD_D
Definition: riscv-opc.h:195
#define CSR_MHPMCOUNTER30
Definition: riscv-opc.h:662
#define MATCH_CSRRWI
Definition: riscv-opc.h:241
#define MATCH_C_SWSP
Definition: riscv-opc.h:499
#define CSR_HPMCOUNTER11H
Definition: riscv-opc.h:710
#define MASK_FCVT_LU_S
Definition: riscv-opc.h:344
#define MASK_FCVT_WU_S
Definition: riscv-opc.h:340
#define MATCH_FCVT_S_WU
Definition: riscv-opc.h:375
#define MASK_FNMADD_S
Definition: riscv-opc.h:422
#define MASK_REM
Definition: riscv-opc.h:160
#define MATCH_FCVT_S_Q
Definition: riscv-opc.h:309
#define MATCH_FRRM
Definition: riscv-opc.h:19
#define MASK_DIVW
Definition: riscv-opc.h:166
#define MASK_FSQ
Definition: riscv-opc.h:414
#define MATCH_C_ADD
Definition: riscv-opc.h:495
#define MASK_SLTIU
Definition: riscv-opc.h:72
#define CSR_HPMCOUNTER24H
Definition: riscv-opc.h:723
#define MATCH_SUB
Definition: riscv-opc.h:85
#define MASK_BNE
Definition: riscv-opc.h:48
#define CSR_HPMCOUNTER8
Definition: riscv-opc.h:582
#define CSR_HPMCOUNTER25
Definition: riscv-opc.h:599
#define MATCH_FSW
Definition: riscv-opc.h:409
#define CSR_MHPMEVENT22
Definition: riscv-opc.h:685
#define MATCH_XORI
Definition: riscv-opc.h:73
#define MASK_FSGNJ_Q
Definition: riscv-opc.h:300
#define MASK_CSRRSI
Definition: riscv-opc.h:244
#define MATCH_FLE_D
Definition: riscv-opc.h:325
#define CSR_INSTRETH
Definition: riscv-opc.h:701
#define MATCH_FDIV_Q
Definition: riscv-opc.h:297
#define CSR_FFLAGS
Definition: riscv-opc.h:571
#define MATCH_FSUB_S
Definition: riscv-opc.h:249
#define MASK_FMIN_S
Definition: riscv-opc.h:262
#define CSR_MHPMEVENT30
Definition: riscv-opc.h:693
#define MASK_FENCE
Definition: riscv-opc.h:144
#define MATCH_C_SRAI
Definition: riscv-opc.h:463
#define MATCH_MUL
Definition: riscv-opc.h:147
#define CSR_MHPMCOUNTER22H
Definition: riscv-opc.h:752
#define MATCH_FEQ_D
Definition: riscv-opc.h:329
#define CSR_MHPMEVENT10
Definition: riscv-opc.h:673
#define CSR_HPMCOUNTER29H
Definition: riscv-opc.h:728
#define MATCH_C_SRLI
Definition: riscv-opc.h:461
#define MATCH_AMOMAXU_D
Definition: riscv-opc.h:209
#define MATCH_FMSUB_Q
Definition: riscv-opc.h:433
#define MATCH_FNMSUB_S
Definition: riscv-opc.h:419
#define MATCH_C_SUBW
Definition: riscv-opc.h:475
#define MASK_FNMADD_D
Definition: riscv-opc.h:430
#define CSR_HPMCOUNTER10H
Definition: riscv-opc.h:709
#define MATCH_FCVT_D_S
Definition: riscv-opc.h:287
#define CSR_MHPMCOUNTER19H
Definition: riscv-opc.h:749
#define MATCH_SBREAK
Definition: riscv-opc.h:43
#define CSR_CYCLEH
Definition: riscv-opc.h:699
#define CSR_MHPMCOUNTER16H
Definition: riscv-opc.h:746
#define MATCH_FMV_Q_X
Definition: riscv-opc.h:401
#define MATCH_SLTU
Definition: riscv-opc.h:91
#define MASK_FLT_Q
Definition: riscv-opc.h:334
#define MASK_FRRM
Definition: riscv-opc.h:20
#define MASK_CUSTOM3_RS1_RS2
Definition: riscv-opc.h:564
#define MASK_CUSTOM1
Definition: riscv-opc.h:536
#define MATCH_ADDI
Definition: riscv-opc.h:65
#define CSR_MHPMCOUNTER30H
Definition: riscv-opc.h:760
#define MASK_C_JR
Definition: riscv-opc.h:508
#define MATCH_FLT_Q
Definition: riscv-opc.h:333
#define MATCH_C_OR
Definition: riscv-opc.h:471
#define MATCH_C_BNEZ
Definition: riscv-opc.h:483
#define MASK_FDIV_D
Definition: riscv-opc.h:274
#define MATCH_LD
Definition: riscv-opc.h:127
#define MATCH_MRET
Definition: riscv-opc.h:227
#define MATCH_SRAW
Definition: riscv-opc.h:119
#define MATCH_C_FLDSP
Definition: riscv-opc.h:487
#define CSR_MHPMCOUNTER19
Definition: riscv-opc.h:651
#define CSR_MHPMEVENT23
Definition: riscv-opc.h:686
#define MASK_MULHU
Definition: riscv-opc.h:154
#define MASK_RDINSTRETH
Definition: riscv-opc.h:40
#define CSR_SIE
Definition: riscv-opc.h:607
#define MATCH_SLLW
Definition: riscv-opc.h:115
#define CSR_HPMCOUNTER19
Definition: riscv-opc.h:593
#define MATCH_FCVT_W_S
Definition: riscv-opc.h:337
#define MASK_FSFLAGSI
Definition: riscv-opc.h:18
#define MATCH_C_FLD
Definition: riscv-opc.h:441
#define CSR_MHPMEVENT28
Definition: riscv-opc.h:691
static int add(char *argv[])
Definition: ziptool.c:84