Rizin
unix-like reverse engineering framework and cli tools
test_iter.c File Reference
#include <stdio.h>
#include <stdlib.h>
#include <capstone/platform.h>
#include <capstone/capstone.h>

Go to the source code of this file.

Classes

struct  platform
 

Functions

static void print_string_hex (unsigned char *str, size_t len)
 
static void test ()
 
int main ()
 

Function Documentation

◆ main()

int main ( void  )

Definition at line 289 of file test_iter.c.

290 {
291  test();
292 
293  return 0;
294 }
static void test()
Definition: test_iter.c:32

References test().

◆ print_string_hex()

static void print_string_hex ( unsigned char *  str,
size_t  len 
)
static

Definition at line 21 of file test_iter.c.

22 {
23  unsigned char *c;
24 
25  printf("Code: ");
26  for (c = str; c < str + len; c++) {
27  printf("0x%02x ", *c & 0xff);
28  }
29  printf("\n");
30 }
size_t len
Definition: 6502dis.c:15
_Use_decl_annotations_ int __cdecl printf(const char *const _Format,...)
Definition: cs_driver.c:93
#define c(i)
Definition: sha256.c:43

References c, len, printf(), and cmd_descs_generate::str.

Referenced by test().

◆ test()

static void test ( )
static

Definition at line 32 of file test_iter.c.

33 {
34 #ifdef CAPSTONE_HAS_X86
35 #define X86_CODE16 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
36 #define X86_CODE32 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
37 #define X86_CODE64 "\x55\x48\x8b\x05\xb8\x13\x00\x00"
38 #endif
39 #ifdef CAPSTONE_HAS_ARM
40 #define ARM_CODE "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3"
41 #define ARM_CODE2 "\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3"
42 #define THUMB_CODE "\x70\x47\xeb\x46\x83\xb0\xc9\x68"
43 #define THUMB_CODE2 "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0"
44 #endif
45 #ifdef CAPSTONE_HAS_MIPS
46 #define MIPS_CODE "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56\x00\x80\x04\x08"
47 #define MIPS_CODE2 "\x56\x34\x21\x34\xc2\x17\x01\x00"
48 #endif
49 #ifdef CAPSTONE_HAS_ARM64
50 #define ARM64_CODE "\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c"
51 #endif
52 #ifdef CAPSTONE_HAS_POWERPC
53 #define PPC_CODE "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21\x40\x82\x00\x14"
54 #endif
55 #ifdef CAPSTONE_HAS_SPARC
56 #define SPARC_CODE "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
57 #define SPARCV9_CODE "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
58 #endif
59 #ifdef CAPSTONE_HAS_SYSZ
60 #define SYSZ_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
61 #endif
62 #ifdef CAPSTONE_HAS_XCORE
63 #define XCORE_CODE "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10"
64 #endif
65 #ifdef CAPSTONE_HAS_M680X
66 #define M680X_CODE "\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39"
67 #endif
68 
69  struct platform platforms[] = {
70 #ifdef CAPSTONE_HAS_X86
71  {
73  CS_MODE_16,
74  (unsigned char *)X86_CODE16,
75  sizeof(X86_CODE32) - 1,
76  "X86 16bit (Intel syntax)"
77  },
78  {
80  CS_MODE_32,
81  (unsigned char *)X86_CODE32,
82  sizeof(X86_CODE32) - 1,
83  "X86 32bit (ATT syntax)",
86  },
87  {
89  CS_MODE_32,
90  (unsigned char *)X86_CODE32,
91  sizeof(X86_CODE32) - 1,
92  "X86 32 (Intel syntax)"
93  },
94  {
96  CS_MODE_64,
97  (unsigned char *)X86_CODE64,
98  sizeof(X86_CODE64) - 1,
99  "X86 64 (Intel syntax)"
100  },
101 #endif
102 #ifdef CAPSTONE_HAS_ARM
103  {
104  CS_ARCH_ARM,
105  CS_MODE_ARM,
106  (unsigned char *)ARM_CODE,
107  sizeof(ARM_CODE) - 1,
108  "ARM"
109  },
110  {
111  CS_ARCH_ARM,
113  (unsigned char *)THUMB_CODE2,
114  sizeof(THUMB_CODE2) - 1,
115  "THUMB-2"
116  },
117  {
118  CS_ARCH_ARM,
119  CS_MODE_ARM,
120  (unsigned char *)ARM_CODE2,
121  sizeof(ARM_CODE2) - 1,
122  "ARM: Cortex-A15 + NEON"
123  },
124  {
125  CS_ARCH_ARM,
127  (unsigned char *)THUMB_CODE,
128  sizeof(THUMB_CODE) - 1,
129  "THUMB"
130  },
131 #endif
132 #ifdef CAPSTONE_HAS_MIPS
133  {
134  CS_ARCH_MIPS,
136  (unsigned char *)MIPS_CODE,
137  sizeof(MIPS_CODE) - 1,
138  "MIPS-32 (Big-endian)"
139  },
140  {
141  CS_ARCH_MIPS,
143  (unsigned char *)MIPS_CODE2,
144  sizeof(MIPS_CODE2) - 1,
145  "MIPS-64-EL (Little-endian)"
146  },
147 #endif
148 #ifdef CAPSTONE_HAS_ARM64
149  {
151  CS_MODE_ARM,
152  (unsigned char *)ARM64_CODE,
153  sizeof(ARM64_CODE) - 1,
154  "ARM-64"
155  },
156 #endif
157 #ifdef CAPSTONE_HAS_POWERPC
158  {
159  CS_ARCH_PPC,
161  (unsigned char*)PPC_CODE,
162  sizeof(PPC_CODE) - 1,
163  "PPC-64"
164  },
165 #endif
166 #ifdef CAPSTONE_HAS_SPARC
167  {
170  (unsigned char*)SPARC_CODE,
171  sizeof(SPARC_CODE) - 1,
172  "Sparc"
173  },
174  {
177  (unsigned char*)SPARCV9_CODE,
178  sizeof(SPARCV9_CODE) - 1,
179  "SparcV9"
180  },
181 #endif
182 #ifdef CAPSTONE_HAS_SYSZ
183  {
184  CS_ARCH_SYSZ,
185  (cs_mode)0,
186  (unsigned char*)SYSZ_CODE,
187  sizeof(SYSZ_CODE) - 1,
188  "SystemZ"
189  },
190 #endif
191 #ifdef CAPSTONE_HAS_XCORE
192  {
194  (cs_mode)0,
195  (unsigned char*)XCORE_CODE,
196  sizeof(XCORE_CODE) - 1,
197  "XCore"
198  },
199 #endif
200 #ifdef CAPSTONE_HAS_M680X
201  {
204  (unsigned char*)M680X_CODE,
205  sizeof(M680X_CODE) - 1,
206  "M680X_6809"
207  },
208 #endif
209  };
210 
211  csh handle;
212  uint64_t address;
213  cs_insn *insn;
214  cs_detail *detail;
215  int i;
216  cs_err err;
217  const uint8_t *code;
218  size_t size;
219 
220  for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
221  printf("****************\n");
222  printf("Platform: %s\n", platforms[i].comment);
224  if (err) {
225  printf("Failed on cs_open() with error returned: %u\n", err);
226  abort();
227  }
228 
229  if (platforms[i].opt_type)
231 
233 
234  // allocate memory for the cache to be used by cs_disasm_iter()
235  insn = cs_malloc(handle);
236 
238  printf("Disasm:\n");
239 
240  address = 0x1000;
241  code = platforms[i].code;
242  size = platforms[i].size;
243  while(cs_disasm_iter(handle, &code, &size, &address, insn)) {
244  int n;
245 
246  printf("0x%" PRIx64 ":\t%s\t\t%s // insn-ID: %u, insn-mnem: %s\n",
247  insn->address, insn->mnemonic, insn->op_str,
248  insn->id, cs_insn_name(handle, insn->id));
249 
250  // print implicit registers used by this instruction
251  detail = insn->detail;
252 
253  if (detail->regs_read_count > 0) {
254  printf("\tImplicit registers read: ");
255  for (n = 0; n < detail->regs_read_count; n++) {
256  printf("%s ", cs_reg_name(handle, detail->regs_read[n]));
257  }
258  printf("\n");
259  }
260 
261  // print implicit registers modified by this instruction
262  if (detail->regs_write_count > 0) {
263  printf("\tImplicit registers modified: ");
264  for (n = 0; n < detail->regs_write_count; n++) {
265  printf("%s ", cs_reg_name(handle, detail->regs_write[n]));
266  }
267  printf("\n");
268  }
269 
270  // print the groups this instruction belong to
271  if (detail->groups_count > 0) {
272  printf("\tThis instruction belongs to groups: ");
273  for (n = 0; n < detail->groups_count; n++) {
274  printf("%s ", cs_group_name(handle, detail->groups[n]));
275  }
276  printf("\n");
277  }
278  }
279 
280  printf("\n");
281 
282  // free memory allocated by cs_malloc()
283  cs_free(insn, 1);
284 
285  cs_close(&handle);
286  }
287 }
lzma_index ** i
Definition: index.h:629
static bool err
Definition: armass.c:435
static mcore_handle handle
Definition: asm_mcore.c:8
@ CS_ARCH_ARM64
ARM-64, also called AArch64.
Definition: capstone.h:76
@ CS_ARCH_SPARC
Sparc architecture.
Definition: capstone.h:80
@ CS_ARCH_XCORE
XCore architecture.
Definition: capstone.h:82
@ CS_ARCH_X86
X86 architecture (including x86 & x86-64)
Definition: capstone.h:78
@ CS_ARCH_M680X
680X architecture
Definition: capstone.h:85
@ CS_ARCH_ARM
ARM architecture (including Thumb, Thumb-2)
Definition: capstone.h:75
@ CS_ARCH_MIPS
Mips architecture.
Definition: capstone.h:77
@ CS_ARCH_SYSZ
SystemZ architecture.
Definition: capstone.h:81
@ CS_ARCH_PPC
PowerPC architecture.
Definition: capstone.h:79
cs_mode
Mode type.
Definition: capstone.h:102
@ CS_MODE_64
64-bit mode (X86, PPC)
Definition: capstone.h:107
@ CS_MODE_MIPS64
Mips64 ISA (Mips)
Definition: capstone.h:125
@ CS_MODE_32
32-bit mode (X86)
Definition: capstone.h:106
@ CS_MODE_ARM
32-bit ARM
Definition: capstone.h:104
@ CS_MODE_MIPS32
Mips32 ISA (Mips)
Definition: capstone.h:124
@ CS_MODE_BIG_ENDIAN
big-endian mode
Definition: capstone.h:123
@ CS_MODE_16
16-bit mode (X86)
Definition: capstone.h:105
@ CS_MODE_V9
SparcV9 mode (Sparc)
Definition: capstone.h:115
@ CS_MODE_THUMB
ARM's Thumb mode, including Thumb-2.
Definition: capstone.h:108
@ CS_MODE_LITTLE_ENDIAN
little-endian mode (default mode)
Definition: capstone.h:103
@ CS_MODE_M680X_6809
M680X Motorola 6809 mode.
Definition: capstone.h:132
@ CS_OPT_DETAIL
Break down instruction structure into details.
Definition: capstone.h:171
@ CS_OPT_SYNTAX
Assembly output syntax.
Definition: capstone.h:170
size_t csh
Definition: capstone.h:71
@ CS_OPT_SYNTAX_ATT
X86 ATT asm syntax (CS_OPT_SYNTAX).
Definition: capstone.h:186
@ CS_OPT_ON
Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA).
Definition: capstone.h:183
CAPSTONE_EXPORT const char *CAPSTONE_API cs_group_name(csh ud, unsigned int group)
Definition: cs.c:1178
CAPSTONE_EXPORT cs_err CAPSTONE_API cs_open(cs_arch arch, cs_mode mode, csh *handle)
Definition: cs.c:453
CAPSTONE_EXPORT const char *CAPSTONE_API cs_insn_name(csh ud, unsigned int insn)
Definition: cs.c:1166
CAPSTONE_EXPORT void CAPSTONE_API cs_free(cs_insn *insn, size_t count)
Definition: cs.c:1017
CAPSTONE_EXPORT const char *CAPSTONE_API cs_reg_name(csh ud, unsigned int reg)
Definition: cs.c:1154
CAPSTONE_EXPORT cs_err CAPSTONE_API cs_close(csh *handle)
Definition: cs.c:501
CAPSTONE_EXPORT cs_insn *CAPSTONE_API cs_malloc(csh ud)
Definition: cs.c:1030
CAPSTONE_EXPORT bool CAPSTONE_API cs_disasm_iter(csh ud, const uint8_t **code, size_t *size, uint64_t *address, cs_insn *insn)
Definition: cs.c:1058
CAPSTONE_EXPORT cs_err CAPSTONE_API cs_option(csh ud, cs_opt_type type, size_t value)
Definition: cs.c:646
cs_arch arch
Definition: cstool.c:13
struct platform platforms[]
Definition: fuzz_diff.c:18
voidpf void uLong size
Definition: ioapi.h:138
const char int mode
Definition: ioapi.h:137
int n
Definition: mipsasm.c:19
string M680X_CODE
Definition: test_basic.py:36
const char * code
Definition: pal.c:98
unsigned long uint64_t
Definition: sftypes.h:28
unsigned char uint8_t
Definition: sftypes.h:31
Definition: inftree9.h:24
cs_opt_type opt_type
Definition: test_basic.c:16
cs_opt_value opt_value
Definition: test_basic.c:17
unsigned char * code
#define PRIx64
Definition: sysdefs.h:94
#define ARM64_CODE
#define THUMB_CODE
#define ARM_CODE2
#define ARM_CODE
#define THUMB_CODE2
static void print_string_hex(unsigned char *str, size_t len)
Definition: test_iter.c:21
#define X86_CODE32
#define MIPS_CODE2
#define MIPS_CODE
#define PPC_CODE
#define SPARCV9_CODE
#define SPARC_CODE
#define SYSZ_CODE
#define X86_CODE64
#define X86_CODE16
#define XCORE_CODE

References arch, ARM64_CODE, ARM_CODE, ARM_CODE2, code, platform::code, platform::comment, CS_ARCH_ARM, CS_ARCH_ARM64, CS_ARCH_M680X, CS_ARCH_MIPS, CS_ARCH_PPC, CS_ARCH_SPARC, CS_ARCH_SYSZ, CS_ARCH_X86, CS_ARCH_XCORE, cs_close(), cs_disasm_iter(), cs_free(), cs_group_name(), cs_insn_name(), cs_malloc(), CS_MODE_16, CS_MODE_32, CS_MODE_64, CS_MODE_ARM, CS_MODE_BIG_ENDIAN, CS_MODE_LITTLE_ENDIAN, CS_MODE_M680X_6809, CS_MODE_MIPS32, CS_MODE_MIPS64, CS_MODE_THUMB, CS_MODE_V9, cs_open(), CS_OPT_DETAIL, CS_OPT_ON, CS_OPT_SYNTAX, CS_OPT_SYNTAX_ATT, cs_option(), cs_reg_name(), test_evm::detail, err, handle, i, test_basic::M680X_CODE, MIPS_CODE, MIPS_CODE2, n, platform::opt_type, platform::opt_value, platforms, PPC_CODE, print_string_hex(), printf(), PRIx64, platform::size, SPARC_CODE, SPARCV9_CODE, SYSZ_CODE, THUMB_CODE, THUMB_CODE2, X86_CODE16, X86_CODE32, X86_CODE64, and XCORE_CODE.

Referenced by main().