Rizin
unix-like reverse engineering framework and cli tools
test_basic.c File Reference
#include <stdio.h>
#include <stdlib.h>
#include <capstone/platform.h>
#include <capstone/capstone.h>

Go to the source code of this file.

Classes

struct  platform
 

Functions

static void print_string_hex (unsigned char *str, size_t len)
 
static void test ()
 
int main ()
 

Function Documentation

◆ main()

int main ( void  )

Definition at line 363 of file test_basic.c.

364 {
365  test();
366 
367  return 0;
368 }
static void test()
Definition: test_basic.c:31

References test().

◆ print_string_hex()

static void print_string_hex ( unsigned char *  str,
size_t  len 
)
static

Definition at line 20 of file test_basic.c.

21 {
22  unsigned char *c;
23 
24  printf("Code: ");
25  for (c = str; c < str + len; c++) {
26  printf("0x%02x ", *c & 0xff);
27  }
28  printf("\n");
29 }
size_t len
Definition: 6502dis.c:15
_Use_decl_annotations_ int __cdecl printf(const char *const _Format,...)
Definition: cs_driver.c:93
#define c(i)
Definition: sha256.c:43

References c, len, printf(), and cmd_descs_generate::str.

Referenced by test().

◆ test()

static void test ( )
static

Definition at line 31 of file test_basic.c.

32 {
33 #ifdef CAPSTONE_HAS_X86
34 #define X86_CODE16 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
35 #define X86_CODE32 "\xba\xcd\xab\x00\x00\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
36 #define X86_CODE64 "\x55\x48\x8b\x05\xb8\x13\x00\x00"
37 #endif
38 #ifdef CAPSTONE_HAS_ARM
39 #define ARM_CODE "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3"
40 #define ARM_CODE2 "\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3"
41 #define ARMV8 "\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5"
42 #define THUMB_MCLASS "\xef\xf3\x02\x80"
43 #define THUMB_CODE "\x70\x47\xeb\x46\x83\xb0\xc9\x68"
44 #define THUMB_CODE2 "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0"
45 #endif
46 #ifdef CAPSTONE_HAS_MIPS
47 #define MIPS_CODE "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56"
48 #define MIPS_CODE2 "\x56\x34\x21\x34\xc2\x17\x01\x00"
49 #define MIPS_32R6M "\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0"
50 #define MIPS_32R6 "\xec\x80\x00\x19\x7c\x43\x22\xa0"
51 #endif
52 #ifdef CAPSTONE_HAS_ARM64
53 #define ARM64_CODE "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9"
54 #endif
55 #ifdef CAPSTONE_HAS_POWERPC
56 #define PPC_CODE "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21"
57 #define PPC_CODE2 "\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f"
58 #endif
59 #ifdef CAPSTONE_HAS_SPARC
60 #define SPARC_CODE "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
61 #define SPARCV9_CODE "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
62 #endif
63 #ifdef CAPSTONE_HAS_SYSZ
64 #define SYSZ_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
65 #endif
66 #ifdef CAPSTONE_HAS_XCORE
67 #define XCORE_CODE "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10"
68 #endif
69 #ifdef CAPSTONE_HAS_M68K
70 #define M68K_CODE "\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28"
71 #endif
72 #ifdef CAPSTONE_HAS_TMS320C64X
73 #define TMS320C64X_CODE "\x01\xac\x88\x40\x81\xac\x88\x43\x00\x00\x00\x00\x02\x90\x32\x96\x02\x80\x46\x9e\x05\x3c\x83\xe6\x0b\x0c\x8b\x24"
74 #endif
75 #ifdef CAPSTONE_HAS_M680X
76 #define M680X_CODE "\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39"
77 #endif
78 #ifdef CAPSTONE_HAS_EVM
79 #define EVM_CODE "\x60\x61"
80 #endif
81 
82  struct platform {
83  cs_arch arch;
84  cs_mode mode;
85  unsigned char *code;
86  size_t size;
87  const char *comment;
90  };
91  struct platform platforms[] = {
92 #ifdef CAPSTONE_HAS_X86
93  {
96  (unsigned char*)X86_CODE16,
97  sizeof(X86_CODE16) - 1,
98  "X86 16bit (Intel syntax)"
99  },
100  {
101  CS_ARCH_X86,
103  (unsigned char*)X86_CODE32,
104  sizeof(X86_CODE32) - 1,
105  "X86 32bit (ATT syntax)",
108  },
109  {
110  CS_ARCH_X86,
112  (unsigned char*)X86_CODE32,
113  sizeof(X86_CODE32) - 1,
114  "X86 32 (Intel syntax)"
115  },
116  {
117  CS_ARCH_X86,
119  (unsigned char*)X86_CODE32,
120  sizeof(X86_CODE32) - 1,
121  "X86 32 (MASM syntax)",
124  },
125  {
126  CS_ARCH_X86,
128  (unsigned char*)X86_CODE64,
129  sizeof(X86_CODE64) - 1,
130  "X86 64 (Intel syntax)"
131  },
132 #endif
133 #ifdef CAPSTONE_HAS_ARM
134  {
135  CS_ARCH_ARM,
137  (unsigned char*)ARM_CODE,
138  sizeof(ARM_CODE) - 1,
139  "ARM"
140  },
141  {
142  CS_ARCH_ARM,
144  (unsigned char*)THUMB_CODE2,
145  sizeof(THUMB_CODE2) - 1,
146  "THUMB-2"
147  },
148  {
149  CS_ARCH_ARM,
151  (unsigned char*)ARM_CODE2,
152  sizeof(ARM_CODE2) - 1,
153  "ARM: Cortex-A15 + NEON"
154  },
155  {
156  CS_ARCH_ARM,
158  (unsigned char*)THUMB_CODE,
159  sizeof(THUMB_CODE) - 1,
160  "THUMB"
161  },
162  {
163  CS_ARCH_ARM,
165  (unsigned char*)THUMB_MCLASS,
166  sizeof(THUMB_MCLASS) - 1,
167  "Thumb-MClass"
168  },
169  {
170  CS_ARCH_ARM,
172  (unsigned char*)ARMV8,
173  sizeof(ARMV8) - 1,
174  "Arm-V8"
175  },
176 #endif
177 #ifdef CAPSTONE_HAS_MIPS
178  {
179  CS_ARCH_MIPS,
181  (unsigned char*)MIPS_CODE,
182  sizeof(MIPS_CODE) - 1,
183  "MIPS-32 (Big-endian)"
184  },
185  {
186  CS_ARCH_MIPS,
188  (unsigned char*)MIPS_CODE2,
189  sizeof(MIPS_CODE2) - 1,
190  "MIPS-64-EL (Little-endian)"
191  },
192  {
193  CS_ARCH_MIPS,
195  (unsigned char*)MIPS_32R6M,
196  sizeof(MIPS_32R6M) - 1,
197  "MIPS-32R6 | Micro (Big-endian)"
198  },
199  {
200  CS_ARCH_MIPS,
202  (unsigned char*)MIPS_32R6,
203  sizeof(MIPS_32R6) - 1,
204  "MIPS-32R6 (Big-endian)"
205  },
206 #endif
207 #ifdef CAPSTONE_HAS_ARM64
208  {
211  (unsigned char*)ARM64_CODE,
212  sizeof(ARM64_CODE) - 1,
213  "ARM-64"
214  },
215 #endif
216 #ifdef CAPSTONE_HAS_POWERPC
217  {
218  CS_ARCH_PPC,
220  (unsigned char*)PPC_CODE,
221  sizeof(PPC_CODE) - 1,
222  "PPC-64"
223  },
224  {
225  CS_ARCH_PPC,
227  (unsigned char*)PPC_CODE,
228  sizeof(PPC_CODE) - 1,
229  "PPC-64, print register with number only",
232  },
233  {
234  CS_ARCH_PPC,
236  (unsigned char*)PPC_CODE2,
237  sizeof(PPC_CODE2) - 1,
238  "PPC-64 + QPX",
239  },
240 #endif
241 #ifdef CAPSTONE_HAS_SPARC
242  {
245  (unsigned char*)SPARC_CODE,
246  sizeof(SPARC_CODE) - 1,
247  "Sparc"
248  },
249  {
252  (unsigned char*)SPARCV9_CODE,
253  sizeof(SPARCV9_CODE) - 1,
254  "SparcV9"
255  },
256 #endif
257 #ifdef CAPSTONE_HAS_SYSZ
258  {
259  CS_ARCH_SYSZ,
260  (cs_mode)0,
261  (unsigned char*)SYSZ_CODE,
262  sizeof(SYSZ_CODE) - 1,
263  "SystemZ"
264  },
265 #endif
266 #ifdef CAPSTONE_HAS_XCORE
267  {
269  (cs_mode)0,
270  (unsigned char*)XCORE_CODE,
271  sizeof(XCORE_CODE) - 1,
272  "XCore"
273  },
274 #endif
275 #ifdef CAPSTONE_HAS_M68K
276  {
277  CS_ARCH_M68K,
279  (unsigned char*)M68K_CODE,
280  sizeof(M68K_CODE) - 1,
281  "M68K",
282  },
283 #endif
284 #ifdef CAPSTONE_HAS_TMS320C64X
285  {
287  (cs_mode)0,
288  (unsigned char*)TMS320C64X_CODE,
289  sizeof(TMS320C64X_CODE) - 1,
290  "TMS320C64x",
291  },
292 #endif
293 #ifdef CAPSTONE_HAS_M680X
294  {
297  (unsigned char*)M680X_CODE,
298  sizeof(M680X_CODE) - 1,
299  "M680X_M6809",
300  },
301 #endif
302 #ifdef CAPSTONE_HAS_EVM
303  {
304  CS_ARCH_EVM,
305  (cs_mode)0,
306  (unsigned char*)EVM_CODE,
307  sizeof(EVM_CODE) - 1,
308  "EVM",
309  },
310 #endif
311  };
312 
313  csh handle;
314  uint64_t address = 0x1000;
315  cs_insn *insn;
316  int i;
317  size_t count;
318  cs_err err;
319 
320  for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
321  printf("****************\n");
322  printf("Platform: %s\n", platforms[i].comment);
324  if (err) {
325  printf("Failed on cs_open() with error returned: %u\n", err);
326  abort();
327  }
328 
329  if (platforms[i].opt_type)
331 
332  count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
333  if (count) {
334  size_t j;
335 
337  printf("Disasm:\n");
338 
339  for (j = 0; j < count; j++) {
340  printf("0x%" PRIx64 ":\t%s\t\t%s\n",
341  insn[j].address, insn[j].mnemonic, insn[j].op_str);
342  }
343 
344  // print out the next offset, after the last insn
345  printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size);
346 
347  // free memory allocated by cs_disasm()
348  cs_free(insn, count);
349  } else {
350  printf("****************\n");
351  printf("Platform: %s\n", platforms[i].comment);
353  printf("ERROR: Failed to disasm given code!\n");
354  abort();
355  }
356 
357  printf("\n");
358 
359  cs_close(&handle);
360  }
361 }
lzma_index ** i
Definition: index.h:629
static bool err
Definition: armass.c:435
static mcore_handle handle
Definition: asm_mcore.c:8
cs_arch
Architecture type.
Definition: capstone.h:74
@ CS_ARCH_ARM64
ARM-64, also called AArch64.
Definition: capstone.h:76
@ CS_ARCH_SPARC
Sparc architecture.
Definition: capstone.h:80
@ CS_ARCH_XCORE
XCore architecture.
Definition: capstone.h:82
@ CS_ARCH_M68K
68K architecture
Definition: capstone.h:83
@ CS_ARCH_X86
X86 architecture (including x86 & x86-64)
Definition: capstone.h:78
@ CS_ARCH_M680X
680X architecture
Definition: capstone.h:85
@ CS_ARCH_ARM
ARM architecture (including Thumb, Thumb-2)
Definition: capstone.h:75
@ CS_ARCH_MIPS
Mips architecture.
Definition: capstone.h:77
@ CS_ARCH_SYSZ
SystemZ architecture.
Definition: capstone.h:81
@ CS_ARCH_TMS320C64X
TMS320C64x architecture.
Definition: capstone.h:84
@ CS_ARCH_EVM
Ethereum architecture.
Definition: capstone.h:86
@ CS_ARCH_PPC
PowerPC architecture.
Definition: capstone.h:79
cs_mode
Mode type.
Definition: capstone.h:102
@ CS_MODE_MCLASS
ARM's Cortex-M series.
Definition: capstone.h:109
@ CS_MODE_64
64-bit mode (X86, PPC)
Definition: capstone.h:107
@ CS_MODE_M68K_040
M68K 68040 mode.
Definition: capstone.h:121
@ CS_MODE_MIPS64
Mips64 ISA (Mips)
Definition: capstone.h:125
@ CS_MODE_32
32-bit mode (X86)
Definition: capstone.h:106
@ CS_MODE_ARM
32-bit ARM
Definition: capstone.h:104
@ CS_MODE_V8
ARMv8 A32 encodings for ARM.
Definition: capstone.h:110
@ CS_MODE_MICRO
MicroMips mode (MIPS)
Definition: capstone.h:111
@ CS_MODE_MIPS32
Mips32 ISA (Mips)
Definition: capstone.h:124
@ CS_MODE_MIPS32R6
Mips32r6 ISA.
Definition: capstone.h:113
@ CS_MODE_BIG_ENDIAN
big-endian mode
Definition: capstone.h:123
@ CS_MODE_16
16-bit mode (X86)
Definition: capstone.h:105
@ CS_MODE_V9
SparcV9 mode (Sparc)
Definition: capstone.h:115
@ CS_MODE_THUMB
ARM's Thumb mode, including Thumb-2.
Definition: capstone.h:108
@ CS_MODE_QPX
Quad Processing eXtensions mode (PPC)
Definition: capstone.h:116
@ CS_MODE_LITTLE_ENDIAN
little-endian mode (default mode)
Definition: capstone.h:103
@ CS_MODE_M680X_6809
M680X Motorola 6809 mode.
Definition: capstone.h:132
cs_opt_type
Runtime option for the disassembled engine.
Definition: capstone.h:168
@ CS_OPT_SYNTAX
Assembly output syntax.
Definition: capstone.h:170
size_t csh
Definition: capstone.h:71
cs_opt_value
Runtime option value (associated with option type above)
Definition: capstone.h:181
@ CS_OPT_SYNTAX_NOREGNAME
Prints register name with only number (CS_OPT_SYNTAX)
Definition: capstone.h:187
@ CS_OPT_SYNTAX_ATT
X86 ATT asm syntax (CS_OPT_SYNTAX).
Definition: capstone.h:186
@ CS_OPT_SYNTAX_MASM
X86 Intel Masm syntax (CS_OPT_SYNTAX).
Definition: capstone.h:188
CAPSTONE_EXPORT size_t CAPSTONE_API cs_disasm(csh ud, const uint8_t *buffer, size_t size, uint64_t offset, size_t count, cs_insn **insn)
Definition: cs.c:798
CAPSTONE_EXPORT cs_err CAPSTONE_API cs_open(cs_arch arch, cs_mode mode, csh *handle)
Definition: cs.c:453
CAPSTONE_EXPORT void CAPSTONE_API cs_free(cs_insn *insn, size_t count)
Definition: cs.c:1017
CAPSTONE_EXPORT cs_err CAPSTONE_API cs_close(csh *handle)
Definition: cs.c:501
CAPSTONE_EXPORT cs_err CAPSTONE_API cs_option(csh ud, cs_opt_type type, size_t value)
Definition: cs.c:646
cs_arch arch
Definition: cstool.c:13
static static sync static getppid static getegid const char static filename char static len const char char static bufsiz static mask static vfork const void static prot static getpgrp const char static swapflags static arg static fd static protocol static who struct sockaddr static addrlen static backlog struct timeval struct timezone static tz const struct iovec static count static mode const void const struct sockaddr static tolen const char static pathname void count
Definition: sflib.h:98
struct platform platforms[]
Definition: fuzz_diff.c:18
voidpf void uLong size
Definition: ioapi.h:138
const char int mode
Definition: ioapi.h:137
string M680X_CODE
Definition: test_basic.py:36
unsigned long uint64_t
Definition: sftypes.h:28
Definition: inftree9.h:24
cs_opt_type opt_type
Definition: test_basic.c:16
cs_opt_value opt_value
Definition: test_basic.c:17
unsigned char * code
#define PRIx64
Definition: sysdefs.h:94
#define ARM64_CODE
#define THUMB_CODE
#define THUMB_MCLASS
#define ARM_CODE2
#define ARMV8
#define ARM_CODE
#define THUMB_CODE2
static void print_string_hex(unsigned char *str, size_t len)
Definition: test_basic.c:20
#define EVM_CODE
#define X86_CODE32
#define M68K_CODE
#define MIPS_CODE2
#define MIPS_32R6
#define MIPS_CODE
#define MIPS_32R6M
#define PPC_CODE2
#define PPC_CODE
#define SPARCV9_CODE
#define SPARC_CODE
#define SYSZ_CODE
#define TMS320C64X_CODE
#define X86_CODE64
#define X86_CODE16
#define XCORE_CODE
mnemonic
Definition: z80asm.h:48

References arch, platform::arch, ARM64_CODE, ARM_CODE, ARM_CODE2, ARMV8, platform::code, platform::comment, count, CS_ARCH_ARM, CS_ARCH_ARM64, CS_ARCH_EVM, CS_ARCH_M680X, CS_ARCH_M68K, CS_ARCH_MIPS, CS_ARCH_PPC, CS_ARCH_SPARC, CS_ARCH_SYSZ, CS_ARCH_TMS320C64X, CS_ARCH_X86, CS_ARCH_XCORE, cs_close(), cs_disasm(), cs_free(), CS_MODE_16, CS_MODE_32, CS_MODE_64, CS_MODE_ARM, CS_MODE_BIG_ENDIAN, CS_MODE_LITTLE_ENDIAN, CS_MODE_M680X_6809, CS_MODE_M68K_040, CS_MODE_MCLASS, CS_MODE_MICRO, CS_MODE_MIPS32, CS_MODE_MIPS32R6, CS_MODE_MIPS64, CS_MODE_QPX, CS_MODE_THUMB, CS_MODE_V8, CS_MODE_V9, cs_open(), CS_OPT_SYNTAX, CS_OPT_SYNTAX_ATT, CS_OPT_SYNTAX_MASM, CS_OPT_SYNTAX_NOREGNAME, cs_option(), err, EVM_CODE, handle, i, test_basic::M680X_CODE, M68K_CODE, MIPS_32R6, MIPS_32R6M, MIPS_CODE, MIPS_CODE2, platform::mode, platform::opt_type, platform::opt_value, platforms, PPC_CODE, PPC_CODE2, print_string_hex(), printf(), PRIx64, platform::size, SPARC_CODE, SPARCV9_CODE, SYSZ_CODE, THUMB_CODE, THUMB_CODE2, THUMB_MCLASS, TMS320C64X_CODE, X86_CODE16, X86_CODE32, X86_CODE64, and XCORE_CODE.

Referenced by main().