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Rizin
unix-like reverse engineering framework and cli tools
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Rizin
unix-like reverse engineering framework and cli tools
|
Go to the source code of this file.
Classes | |
| struct | mips_opcode |
Macros | |
| #define | OP_MASK_OP 0x3f |
| #define | OP_SH_OP 26 |
| #define | OP_MASK_RS 0x1f |
| #define | OP_SH_RS 21 |
| #define | OP_MASK_FR 0x1f |
| #define | OP_SH_FR 21 |
| #define | OP_MASK_FMT 0x1f |
| #define | OP_SH_FMT 21 |
| #define | OP_MASK_BCC 0x7 |
| #define | OP_SH_BCC 18 |
| #define | OP_MASK_CODE 0x3ff |
| #define | OP_SH_CODE 16 |
| #define | OP_MASK_CODE2 0x3ff |
| #define | OP_SH_CODE2 6 |
| #define | OP_MASK_RT 0x1f |
| #define | OP_SH_RT 16 |
| #define | OP_MASK_FT 0x1f |
| #define | OP_SH_FT 16 |
| #define | OP_MASK_CACHE 0x1f |
| #define | OP_SH_CACHE 16 |
| #define | OP_MASK_RD 0x1f |
| #define | OP_SH_RD 11 |
| #define | OP_MASK_FS 0x1f |
| #define | OP_SH_FS 11 |
| #define | OP_MASK_PREFX 0x1f |
| #define | OP_SH_PREFX 11 |
| #define | OP_MASK_CCC 0x7 |
| #define | OP_SH_CCC 8 |
| #define | OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */ |
| #define | OP_SH_CODE20 6 |
| #define | OP_MASK_SHAMT 0x1f |
| #define | OP_SH_SHAMT 6 |
| #define | OP_MASK_FD 0x1f |
| #define | OP_SH_FD 6 |
| #define | OP_MASK_TARGET 0x3ffffff |
| #define | OP_SH_TARGET 0 |
| #define | OP_MASK_COPZ 0x1ffffff |
| #define | OP_SH_COPZ 0 |
| #define | OP_MASK_IMMEDIATE 0xffff |
| #define | OP_SH_IMMEDIATE 0 |
| #define | OP_MASK_DELTA 0xffff |
| #define | OP_SH_DELTA 0 |
| #define | OP_MASK_FUNCT 0x3f |
| #define | OP_SH_FUNCT 0 |
| #define | OP_MASK_SPEC 0x3f |
| #define | OP_SH_SPEC 0 |
| #define | OP_SH_LOCC 8 /* FP condition code. */ |
| #define | OP_SH_HICC 18 /* FP condition code. */ |
| #define | OP_MASK_CC 0x7 |
| #define | OP_SH_COP1NORM 25 /* Normal COP1 encoding. */ |
| #define | OP_MASK_COP1NORM 0x1 /* a single bit. */ |
| #define | OP_SH_COP1SPEC 21 /* COP1 encodings. */ |
| #define | OP_MASK_COP1SPEC 0xf |
| #define | OP_MASK_COP1SCLR 0x4 |
| #define | OP_MASK_COP1CMP 0x3 |
| #define | OP_SH_COP1CMP 4 |
| #define | OP_SH_FORMAT 21 /* FP short format field. */ |
| #define | OP_MASK_FORMAT 0x7 |
| #define | OP_SH_TRUE 16 |
| #define | OP_MASK_TRUE 0x1 |
| #define | OP_SH_GE 17 |
| #define | OP_MASK_GE 0x01 |
| #define | OP_SH_UNSIGNED 16 |
| #define | OP_MASK_UNSIGNED 0x1 |
| #define | OP_SH_HINT 16 |
| #define | OP_MASK_HINT 0x1f |
| #define | OP_SH_MMI 0 /* Multimedia (parallel) op. */ |
| #define | OP_MASK_MMI 0x3f |
| #define | OP_SH_MMISUB 6 |
| #define | OP_MASK_MMISUB 0x1f |
| #define | OP_MASK_PERFREG 0x1f /* Performance monitoring. */ |
| #define | OP_SH_PERFREG 1 |
| #define | OP_SH_SEL 0 /* Coprocessor select field. */ |
| #define | OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ |
| #define | OP_SH_CODE19 6 /* 19 bit wait code. */ |
| #define | OP_MASK_CODE19 0x7ffff |
| #define | OP_SH_ALN 21 |
| #define | OP_MASK_ALN 0x7 |
| #define | OP_SH_VSEL 21 |
| #define | OP_MASK_VSEL 0x1f |
| #define | OP_MASK_VECBYTE |
| #define | OP_SH_VECBYTE 22 |
| #define | OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ |
| #define | OP_SH_VECALIGN 21 |
| #define | OP_MASK_INSMSB 0x1f /* "ins" MSB. */ |
| #define | OP_SH_INSMSB 11 |
| #define | OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */ |
| #define | OP_SH_EXTMSBD 11 |
| #define | OP_SH_DSPACC 11 |
| #define | OP_MASK_DSPACC 0x3 |
| #define | OP_SH_DSPACC_S 21 |
| #define | OP_MASK_DSPACC_S 0x3 |
| #define | OP_SH_DSPSFT 20 |
| #define | OP_MASK_DSPSFT 0x3f |
| #define | OP_SH_DSPSFT_7 19 |
| #define | OP_MASK_DSPSFT_7 0x7f |
| #define | OP_SH_SA3 21 |
| #define | OP_MASK_SA3 0x7 |
| #define | OP_SH_SA4 21 |
| #define | OP_MASK_SA4 0xf |
| #define | OP_SH_IMM8 16 |
| #define | OP_MASK_IMM8 0xff |
| #define | OP_SH_IMM10 16 |
| #define | OP_MASK_IMM10 0x3ff |
| #define | OP_SH_WRDSP 11 |
| #define | OP_MASK_WRDSP 0x3f |
| #define | OP_SH_RDDSP 16 |
| #define | OP_MASK_RDDSP 0x3f |
| #define | OP_SH_BP 11 |
| #define | OP_MASK_BP 0x3 |
| #define | OP_SH_MT_U 5 |
| #define | OP_MASK_MT_U 0x1 |
| #define | OP_SH_MT_H 4 |
| #define | OP_MASK_MT_H 0x1 |
| #define | OP_SH_MTACC_T 18 |
| #define | OP_MASK_MTACC_T 0x3 |
| #define | OP_SH_MTACC_D 13 |
| #define | OP_MASK_MTACC_D 0x3 |
| #define | OP_OP_COP0 0x10 |
| #define | OP_OP_COP1 0x11 |
| #define | OP_OP_COP2 0x12 |
| #define | OP_OP_COP3 0x13 |
| #define | OP_OP_LWC1 0x31 |
| #define | OP_OP_LWC2 0x32 |
| #define | OP_OP_LWC3 0x33 /* a.k.a. pref */ |
| #define | OP_OP_LDC1 0x35 |
| #define | OP_OP_LDC2 0x36 |
| #define | OP_OP_LDC3 0x37 /* a.k.a. ld */ |
| #define | OP_OP_SWC1 0x39 |
| #define | OP_OP_SWC2 0x3a |
| #define | OP_OP_SWC3 0x3b |
| #define | OP_OP_SDC1 0x3d |
| #define | OP_OP_SDC2 0x3e |
| #define | OP_OP_SDC3 0x3f /* a.k.a. sd */ |
| #define | MDMX_FMTSEL_IMM_QH 0x1d |
| #define | MDMX_FMTSEL_IMM_OB 0x1e |
| #define | MDMX_FMTSEL_VEC_QH 0x15 |
| #define | MDMX_FMTSEL_VEC_OB 0x16 |
| #define | OP_SH_UDI1 6 |
| #define | OP_MASK_UDI1 0x1f |
| #define | OP_SH_UDI2 6 |
| #define | OP_MASK_UDI2 0x3ff |
| #define | OP_SH_UDI3 6 |
| #define | OP_MASK_UDI3 0x7fff |
| #define | OP_SH_UDI4 6 |
| #define | OP_MASK_UDI4 0xfffff |
| #define | INSN_WRITE_GPR_D 0x00000001 |
| #define | INSN_WRITE_GPR_T 0x00000002 |
| #define | INSN_WRITE_GPR_31 0x00000004 |
| #define | INSN_WRITE_FPR_D 0x00000008 |
| #define | INSN_WRITE_FPR_S 0x00000010 |
| #define | INSN_WRITE_FPR_T 0x00000020 |
| #define | INSN_READ_GPR_S 0x00000040 |
| #define | INSN_READ_GPR_T 0x00000080 |
| #define | INSN_READ_FPR_S 0x00000100 |
| #define | INSN_READ_FPR_T 0x00000200 |
| #define | INSN_READ_FPR_R 0x00000400 |
| #define | INSN_WRITE_COND_CODE 0x00000800 |
| #define | INSN_READ_COND_CODE 0x00001000 |
| #define | INSN_TLB 0x00002000 |
| #define | INSN_COP 0x00004000 |
| #define | INSN_LOAD_MEMORY_DELAY 0x00008000 |
| #define | INSN_LOAD_COPROC_DELAY 0x00010000 |
| #define | INSN_UNCOND_BRANCH_DELAY 0x00020000 |
| #define | INSN_COND_BRANCH_DELAY 0x00040000 |
| #define | INSN_COND_BRANCH_LIKELY 0x00080000 |
| #define | INSN_COPROC_MOVE_DELAY 0x00100000 |
| #define | INSN_COPROC_MEMORY_DELAY 0x00200000 |
| #define | INSN_READ_HI 0x00400000 |
| #define | INSN_READ_LO 0x00800000 |
| #define | INSN_WRITE_HI 0x01000000 |
| #define | INSN_WRITE_LO 0x02000000 |
| #define | INSN_TRAP 0x04000000 |
| #define | INSN_STORE_MEMORY 0x08000000 |
| #define | FP_S 0x10000000 |
| #define | FP_D 0x20000000 |
| #define | INSN_MULT 0x40000000 |
| #define | INSN_SYNC 0x80000000 |
| #define | INSN2_ALIAS 0x00000001 |
| #define | INSN2_READ_MDMX_ACC 0x00000002 |
| #define | INSN2_WRITE_MDMX_ACC 0x00000004 |
| #define | INSN_MACRO 0xffffffff |
| #define | INSN_ISA_MASK 0x0000000ful |
| #define | INSN_ISA1 1 |
| #define | INSN_ISA2 2 |
| #define | INSN_ISA3 3 |
| #define | INSN_ISA4 4 |
| #define | INSN_ISA5 5 |
| #define | INSN_ISA32 6 |
| #define | INSN_ISA32R2 7 |
| #define | INSN_ISA64 8 |
| #define | INSN_ISA64R2 9 |
| #define | INSN_ISA3_32 10 |
| #define | INSN_ISA3_32R2 11 |
| #define | INSN_ISA4_32 12 |
| #define | INSN_ISA4_32R2 13 |
| #define | INSN_ISA5_32R2 14 |
| #define | INSN_CHIP_MASK 0xc3ff0800 |
| #define | INSN_OCTEON 0x00000800 |
| #define | INSN_ASE_MASK 0x3c00f000 |
| #define | INSN_DSP 0x00001000 |
| #define | INSN_DSP64 0x00002000 |
| #define | INSN_MIPS16 0x00004000 |
| #define | INSN_MIPS3D 0x00008000 |
| #define | INSN_4650 0x00010000 |
| #define | INSN_4010 0x00020000 |
| #define | INSN_4100 0x00040000 |
| #define | INSN_3900 0x00080000 |
| #define | INSN_10000 0x00100000 |
| #define | INSN_SB1 0x00200000 |
| #define | INSN_4111 0x00400000 |
| #define | INSN_4120 0x00800000 |
| #define | INSN_5400 0x01000000 |
| #define | INSN_5500 0x02000000 |
| #define | INSN_MDMX 0x04000000 |
| #define | INSN_MT 0x08000000 |
| #define | INSN_SMARTMIPS 0x10000000 |
| #define | INSN_DSPR2 0x20000000 |
| #define | INSN_LOONGSON_2E 0x40000000 |
| #define | INSN_LOONGSON_2F 0x80000000 |
| #define | ISA_UNKNOWN 0 /* Gas internal use. */ |
| #define | ISA_MIPS1 INSN_ISA1 |
| #define | ISA_MIPS2 INSN_ISA2 |
| #define | ISA_MIPS3 INSN_ISA3 |
| #define | ISA_MIPS4 INSN_ISA4 |
| #define | ISA_MIPS5 INSN_ISA5 |
| #define | ISA_MIPS32 INSN_ISA32 |
| #define | ISA_MIPS64 INSN_ISA64 |
| #define | ISA_MIPS32R2 INSN_ISA32R2 |
| #define | ISA_MIPS64R2 INSN_ISA64R2 |
| #define | CPU_UNKNOWN 0 /* Gas internal use. */ |
| #define | CPU_R3000 3000 |
| #define | CPU_R3900 3900 |
| #define | CPU_R4000 4000 |
| #define | CPU_R4010 4010 |
| #define | CPU_VR4100 4100 |
| #define | CPU_R4111 4111 |
| #define | CPU_VR4120 4120 |
| #define | CPU_R4300 4300 |
| #define | CPU_R4400 4400 |
| #define | CPU_R4600 4600 |
| #define | CPU_R4650 4650 |
| #define | CPU_R5000 5000 |
| #define | CPU_VR5400 5400 |
| #define | CPU_VR5500 5500 |
| #define | CPU_R6000 6000 |
| #define | CPU_RM7000 7000 |
| #define | CPU_R8000 8000 |
| #define | CPU_RM9000 9000 |
| #define | CPU_R10000 10000 |
| #define | CPU_R12000 12000 |
| #define | CPU_MIPS16 16 |
| #define | CPU_MIPS32 32 |
| #define | CPU_MIPS32R2 33 |
| #define | CPU_MIPS5 5 |
| #define | CPU_MIPS64 64 |
| #define | CPU_MIPS64R2 65 |
| #define | CPU_SB1 12310201 /* octal 'SB', 01. */ |
| #define | CPU_LOONGSON_2E 3001 |
| #define | CPU_LOONGSON_2F 3002 |
| #define | CPU_OCTEON 6501 |
| #define | OPCODE_IS_MEMBER(insn, isa, cpu) (((isa & INSN_ISA_MASK) != 0 && ((insn)->membership & INSN_ISA_MASK) != 0 && ((mips_isa_table[(isa & INSN_ISA_MASK) - 1] >> (((insn)->membership & INSN_ISA_MASK) - 1)) & 1) != 0) || ((isa & ~INSN_ISA_MASK) & ((insn)->membership & ~INSN_ISA_MASK)) != 0 || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) || ((cpu == CPU_R10000 || cpu == CPU_R12000) && ((insn)->membership & INSN_10000) != 0) || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) || (cpu == CPU_LOONGSON_2E && ((insn)->membership & INSN_LOONGSON_2E) != 0) || (cpu == CPU_LOONGSON_2F && ((insn)->membership & INSN_LOONGSON_2F) != 0) || (cpu == CPU_OCTEON && ((insn)->membership & INSN_OCTEON) != 0) || 0) /* Please keep this term for easier source merging. */ |
| #define | NUMOPCODES bfd_mips_num_opcodes |
| #define | MIPS16OP_MASK_OP 0x1f |
| #define | MIPS16OP_SH_OP 11 |
| #define | MIPS16OP_MASK_IMM11 0x7ff |
| #define | MIPS16OP_SH_IMM11 0 |
| #define | MIPS16OP_MASK_RX 0x7 |
| #define | MIPS16OP_SH_RX 8 |
| #define | MIPS16OP_MASK_IMM8 0xff |
| #define | MIPS16OP_SH_IMM8 0 |
| #define | MIPS16OP_MASK_RY 0x7 |
| #define | MIPS16OP_SH_RY 5 |
| #define | MIPS16OP_MASK_IMM5 0x1f |
| #define | MIPS16OP_SH_IMM5 0 |
| #define | MIPS16OP_MASK_RZ 0x7 |
| #define | MIPS16OP_SH_RZ 2 |
| #define | MIPS16OP_MASK_IMM4 0xf |
| #define | MIPS16OP_SH_IMM4 0 |
| #define | MIPS16OP_MASK_REGR32 0x1f |
| #define | MIPS16OP_SH_REGR32 0 |
| #define | MIPS16OP_MASK_REG32R 0x1f |
| #define | MIPS16OP_SH_REG32R 3 |
| #define | MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i)&0x18)) |
| #define | MIPS16OP_MASK_MOVE32Z 0x7 |
| #define | MIPS16OP_SH_MOVE32Z 0 |
| #define | MIPS16OP_MASK_IMM6 0x3f |
| #define | MIPS16OP_SH_IMM6 5 |
| #define | MIPS16_ALL_ARGS 0xe |
| #define | MIPS16_ALL_STATICS 0xb |
| #define | MIPS16_INSN_WRITE_X 0x00000001 |
| #define | MIPS16_INSN_WRITE_Y 0x00000002 |
| #define | MIPS16_INSN_WRITE_Z 0x00000004 |
| #define | MIPS16_INSN_WRITE_T 0x00000008 |
| #define | MIPS16_INSN_WRITE_SP 0x00000010 |
| #define | MIPS16_INSN_WRITE_31 0x00000020 |
| #define | MIPS16_INSN_WRITE_GPR_Y 0x00000040 |
| #define | MIPS16_INSN_READ_X 0x00000080 |
| #define | MIPS16_INSN_READ_Y 0x00000100 |
| #define | MIPS16_INSN_READ_Z 0x00000200 |
| #define | MIPS16_INSN_READ_T 0x00000400 |
| #define | MIPS16_INSN_READ_SP 0x00000800 |
| #define | MIPS16_INSN_READ_31 0x00001000 |
| #define | MIPS16_INSN_READ_PC 0x00002000 |
| #define | MIPS16_INSN_READ_GPR_X 0x00004000 |
| #define | MIPS16_INSN_BRANCH 0x00010000 |
Variables | |
| static const unsigned int | mips_isa_table [] = { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff } |
| const struct mips_opcode | mips_builtin_opcodes [] |
| const int | bfd_mips_num_builtin_opcodes |
| struct mips_opcode * | mips_opcodes |
| int | bfd_mips_num_opcodes |
| const struct mips_opcode | mips16_opcodes [] |
| const int | bfd_mips16_num_opcodes |
| #define ISA_MIPS32 INSN_ISA32 |
| #define ISA_MIPS32R2 INSN_ISA32R2 |
| #define ISA_MIPS64 INSN_ISA64 |
| #define ISA_MIPS64R2 INSN_ISA64R2 |
| #define NUMOPCODES bfd_mips_num_opcodes |
| #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ |
| #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */ |
| #define OP_MASK_VECBYTE |
| #define OPCODE_IS_MEMBER | ( | insn, | |
| isa, | |||
| cpu | |||
| ) | (((isa & INSN_ISA_MASK) != 0 && ((insn)->membership & INSN_ISA_MASK) != 0 && ((mips_isa_table[(isa & INSN_ISA_MASK) - 1] >> (((insn)->membership & INSN_ISA_MASK) - 1)) & 1) != 0) || ((isa & ~INSN_ISA_MASK) & ((insn)->membership & ~INSN_ISA_MASK)) != 0 || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) || ((cpu == CPU_R10000 || cpu == CPU_R12000) && ((insn)->membership & INSN_10000) != 0) || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) || (cpu == CPU_LOONGSON_2E && ((insn)->membership & INSN_LOONGSON_2E) != 0) || (cpu == CPU_LOONGSON_2F && ((insn)->membership & INSN_LOONGSON_2F) != 0) || (cpu == CPU_OCTEON && ((insn)->membership & INSN_OCTEON) != 0) || 0) /* Please keep this term for easier source merging. */ |
| anonymous enum |
Definition at line 629 of file mips.h.
Definition at line 243 of file mips16-opc.c.
Referenced by print_insn_mips16().
Definition at line 2011 of file mips-opc.c.
|
extern |
Definition at line 2017 of file mips-opc.c.
|
extern |
Definition at line 1 of file mips16-opc.c.
Referenced by print_insn_mips16().
|
extern |
Definition at line 1 of file mips-opc.c.
|
extern |
Definition at line 2015 of file mips-opc.c.
Referenced by print_insn_mips().
1.9.1 
