asm_arm_cs.c File Reference

#include <rz_asm.h>
#include <rz_lib.h>
#include <ht_uu.h>
#include <capstone/capstone.h>
#include "../arch/arm/asm-arm.h"
#include "../arch/arm/arm_it.h"
#include "./asm_arm_hacks.inc"

Go to the source code of this file.

Classes
struct	arm_cs_context_t

Typedefs
typedef struct arm_cs_context_t	ArmCSContext

Functions
bool	arm64ass (const char *str, ut64 addr, ut32 *op)
static bool	check_features (RzAsm *a, cs_insn *insn)
static const char *	cc_name (arm_cc cc)
static int	disassemble (RzAsm *a, RzAsmOp *op, const ut8 *buf, int len)
static int	assemble (RzAsm *a, RzAsmOp *op, const char *buf)
static bool	arm_init (void **user)
static bool	arm_fini (void *user)
static char *	mnemonics (RzAsm *a, int id, bool json)

Variables
RzAsmPlugin	rz_asm_plugin_arm_cs
RZ_API RzLibStruct	rizin_plugin

Typedef Documentation

ArmCSContext

typedef struct arm_cs_context_t ArmCSContext

Function Documentation

arm64ass()

bool arm64ass	(	const char *	str,
		ut64	addr,
		ut32 *	op
	)

Definition at line 1348 of file armass64.c.

                                                    {
    *op = UT32_MAX;
    ArmOp ops = { 0 };
    if (!parseOpcode(str, &ops)) {
        free(ops.mnemonic);
        return false;
    }
    /* TODO: write tests for this and move out the regsize logic into the mov */
    if (!strncmp(str, "mov", 3)) {
        *op = mov(&ops);
    } else if (!strncmp(str, "cb", 2)) {
        *op = cb(&ops);
    } else if (!strncmp(str, "cmp", 3)) {
        *op = cmp(&ops);
    } else if (!strncmp(str, "ldrb", 4)) {
        *op = lsop(&ops, 0x00004038, -1);
    } else if (!strncmp(str, "ldrh", 4)) {
        *op = lsop(&ops, 0x00004078, -1);
    } else if (!strncmp(str, "ldrsh", 5)) {
        *op = lsop(&ops, 0x00008078, -1);
    } else if (!strncmp(str, "ldrsw", 5)) {
        *op = lsop(&ops, 0x00000098, addr);
    } else if (!strncmp(str, "ldrsb", 5)) {
        *op = lsop(&ops, 0x00008038, -1);
    } else if (!strncmp(str, "strb", 4)) {
        *op = lsop(&ops, 0x00000038, -1);
    } else if (!strncmp(str, "strh", 4)) {
        *op = lsop(&ops, 0x00000078, -1);
    } else if (!strncmp(str, "ldr", 3)) {
        *op = reglsop(&ops, 0x000040f8);
    } else if (!strncmp(str, "stur", 4)) {
        *op = regsluop(&ops, 0x000000f8);
    } else if (!strncmp(str, "ldur", 4)) {
        *op = regsluop(&ops, 0x000040f8);
    } else if (!strncmp(str, "str", 3)) {
        *op = reglsop(&ops, 0x000000f8);
    } else if (!strncmp(str, "stp", 3)) {
        *op = stp(&ops, 0x000000a9);
    } else if (!strncmp(str, "ldp", 3)) {
        *op = stp(&ops, 0x000040a9);
    } else if (!strncmp(str, "sub", 3)) { // w
        *op = arithmetic(&ops, 0xd1);
    } else if (!strncmp(str, "add x", 5)) {
        *op = arithmetic(&ops, 0x91);
    } else if (!strncmp(str, "add w", 5)) {
        *op = arithmetic(&ops, 0x11);
    } else if (!strncmp(str, "adr x", 5)) { // w
        *op = adr(&ops, addr);
    } else if (!strncmp(str, "adrp x", 6)) {
        *op = adrp(&ops, addr, 0x00000090);
    } else if (!strncmp(str, "neg", 3)) {
        *op = neg(&ops);
    } else if (!strcmp(str, "isb")) {
        *op = 0xdf3f03d5;
    } else if (handlePAC(op, str)) { // PAC
        free(ops.mnemonic);
        return true;
    } else if (!strcmp(str, "nop")) {
        *op = 0x1f2003d5;
    } else if (!strcmp(str, "ret")) {
        *op = 0xc0035fd6;
    } else if (!strncmp(str, "msr ", 4)) {
        *op = msr(&ops, 0);
    } else if (!strncmp(str, "mrs ", 4)) {
        *op = msr(&ops, 1);
    } else if (!strncmp(str, "ands ", 5)) {
        *op = logical(&ops, false, ARM_ANDS);
    } else if (!strncmp(str, "and ", 4)) {
        *op = logical(&ops, false, ARM_AND);
    } else if (!strncmp(str, "bics ", 5)) {
        *op = logical(&ops, true, ARM_ANDS);
    } else if (!strncmp(str, "bic ", 4)) {
        *op = logical(&ops, true, ARM_AND);
    } else if (!strncmp(str, "eon ", 4)) {
        *op = logical(&ops, true, ARM_EOR);
    } else if (!strncmp(str, "eor ", 4)) {
        *op = logical(&ops, false, ARM_EOR);
    } else if (!strncmp(str, "orn ", 4)) {
        *op = logical(&ops, true, ARM_ORR);
    } else if (!strncmp(str, "orr ", 4)) {
        *op = logical(&ops, false, ARM_ORR);
    } else if (!strncmp(str, "svc ", 4)) { // system level exception
        *op = exception(&ops, 0x010000d4);
    } else if (!strncmp(str, "hvc ", 4)) { // hypervisor level exception
        *op = exception(&ops, 0x020000d4);
    } else if (!strncmp(str, "smc ", 4)) { // secure monitor exception
        *op = exception(&ops, 0x030000d4);
    } else if (!strncmp(str, "brk ", 4)) { // breakpoint
        *op = exception(&ops, 0x000020d4);
    } else if (!strncmp(str, "hlt ", 4)) { // halt
        *op = exception(&ops, 0x000040d4);
    } else if (!strncmp(str, "b ", 2)) {
        *op = branch(&ops, addr, 0x14);
    } else if (!strncmp(str, "b.", 2)) {
        *op = parse_bdot(str + 2, &ops, addr);
    } else if (!strncmp(str, "bl ", 3)) {
        *op = branch(&ops, addr, 0x94);
    } else if (!strncmp(str, "br x", 4)) {
        *op = branch(&ops, addr, 0x1fd6);
    } else if (!strncmp(str, "blr x", 5)) {
        *op = branch(&ops, addr, 0x3fd6);
    } else if (!strncmp(str, "dmb ", 4)) {
        *op = mem_barrier(&ops, addr, 0xbf3003d5);
    } else if (!strncmp(str, "dsb ", 4)) {
        *op = mem_barrier(&ops, addr, 0x9f3003d5);
    } else if (!strncmp(str, "isb", 3)) {
        *op = mem_barrier(&ops, addr, 0xdf3f03d5);
    } else if (!strncmp(str, "sbfiz ", 6) || !strncmp(str, "sbfm ", 5) || !strncmp(str, "sbfx ", 5)) {
        *op = bitfield(&ops, 0x00000013);
    } else if (!strncmp(str, "ubfiz ", 6) || !strncmp(str, "ubfm ", 5) || !strncmp(str, "ubfx ", 5)) {
        *op = bitfield(&ops, 0x00000053);
    }
    free(ops.mnemonic);
    return *op != UT32_MAX;
}

References addr, adr(), adrp(), arithmetic(), ARM_AND, ARM_ANDS, ARM_EOR, ARM_ORR, bitfield(), branch(), cb(), cmp(), exception(), free(), handlePAC(), logical(), lsop(), mem_barrier(), mov(), msr(), neg(), ops, parse_bdot(), parseOpcode(), reglsop(), regsluop(), stp(), cmd_descs_generate::str, and UT32_MAX.

Referenced by assemble().

arm_fini()

static bool arm_fini ( void *  user )

static

Definition at line 252 of file asm_arm_cs.c.

                                 {
    rz_return_val_if_fail(user, false);
    ArmCSContext *ctx = (ArmCSContext *)user;
    cs_close(&ctx->cd);
    rz_arm_it_context_fini(&ctx->it);
    free(ctx);
    return true;
}

References cs_close(), free(), rz_arm_it_context_fini(), and rz_return_val_if_fail.

arm_init()

static bool arm_init ( void **  user )

static

Definition at line 239 of file asm_arm_cs.c.

                                  {
    ArmCSContext *ctx = RZ_NEW0(ArmCSContext);
    if (!ctx) {
        return false;
    }
    rz_arm_it_context_init(&ctx->it);
    ctx->cd = 0;
    ctx->omode = -1;
    ctx->obits = 32;
    *user = ctx;
    return true;
}

References rz_arm_it_context_init(), and RZ_NEW0.

assemble()

static int assemble ( RzAsm *  a, RzAsmOp *  op, const char *  buf  )

static

Definition at line 190 of file asm_arm_cs.c.

                                                            {
    const bool is_thumb = (a->bits == 16);
    int opsize;
    ut32 opcode;
    if (a->bits == 64) {
        if (!arm64ass(buf, a->pc, &opcode)) {
            return -1;
        }
    } else {
        opcode = armass_assemble(buf, a->pc, is_thumb);
        if (a->bits != 32 && a->bits != 16) {
            RZ_LOG_ERROR("assembler: arm: cannot assemble instruction due invalid 'asm.bits' value (accepted only 16 or 32 bits).\n");
            return -1;
        }
    }
    if (opcode == UT32_MAX) {
        return -1;
    }
    ut8 opbuf[4];
    if (is_thumb) {
        const int o = opcode >> 16;
        opsize = o > 0 ? 4 : 2;
        if (opsize == 4) {
            if (a->big_endian) {
                rz_write_le16(opbuf, opcode >> 16);
                rz_write_le16(opbuf + 2, opcode & UT16_MAX);
            } else {
                rz_write_be32(opbuf, opcode);
            }
        } else if (opsize == 2) {
            if (a->big_endian) {
                rz_write_le16(opbuf, opcode & UT16_MAX);
            } else {
                rz_write_be16(opbuf, opcode & UT16_MAX);
            }
        }
    } else {
        opsize = 4;
        if (a->big_endian) {
            rz_write_le32(opbuf, opcode);
        } else {
            rz_write_be32(opbuf, opcode);
        }
    }
    rz_strbuf_setbin(&op->buf, opbuf, opsize);
    // XXX. thumb endian assembler needs no swap
    return opsize;
}

References a, arm64ass(), armass_assemble(), is_thumb(), RZ_LOG_ERROR, rz_strbuf_setbin(), rz_write_be16(), rz_write_be32(), rz_write_le16(), rz_write_le32(), UT16_MAX, and UT32_MAX.

cc_name()

static const char* cc_name ( arm_cc  cc )

static

Definition at line 51 of file asm_arm_cs.c.

                                      {
    switch (cc) {
    case ARM_CC_EQ: // Equal                      Equal
        return "eq";
    case ARM_CC_NE: // Not equal                  Not equal, or unordered
        return "ne";
    case ARM_CC_HS: // Carry set                  >, ==, or unordered
        return "hs";
    case ARM_CC_LO: // Carry clear                Less than
        return "lo";
    case ARM_CC_MI: // Minus, negative            Less than
        return "mi";
    case ARM_CC_PL: // Plus, positive or zero     >, ==, or unordered
        return "pl";
    case ARM_CC_VS: // Overflow                   Unordered
        return "vs";
    case ARM_CC_VC: // No overflow                Not unordered
        return "vc";
    case ARM_CC_HI: // Unsigned higher            Greater than, or unordered
        return "hi";
    case ARM_CC_LS: // Unsigned lower or same     Less than or equal
        return "ls";
    case ARM_CC_GE: // Greater than or equal      Greater than or equal
        return "ge";
    case ARM_CC_LT: // Less than                  Less than, or unordered
        return "lt";
    case ARM_CC_GT: // Greater than               Greater than
        return "gt";
    case ARM_CC_LE: // Less than or equal         <, ==, or unordered
        return "le";
    default:
        return "";
    }
}

References ARM_CC_EQ, ARM_CC_GE, ARM_CC_GT, ARM_CC_HI, ARM_CC_HS, ARM_CC_LE, ARM_CC_LO, ARM_CC_LS, ARM_CC_LT, ARM_CC_MI, ARM_CC_NE, ARM_CC_PL, ARM_CC_VC, and ARM_CC_VS.

Referenced by disassemble().

check_features()

static bool check_features ( RzAsm *  a, cs_insn *  insn  )

static

Definition at line 21 of file asm_arm_cs.c.

                                                    {
    ArmCSContext *ctx = (ArmCSContext *)a->plugin_data;
    int i;
    if (!insn || !insn->detail) {
        return true;
    }
    for (i = 0; i < insn->detail->groups_count; i++) {
        int id = insn->detail->groups[i];
        switch (id) {
        case ARM_GRP_ARM:
        case ARM_GRP_THUMB:
        case ARM_GRP_THUMB1ONLY:
        case ARM_GRP_THUMB2:
            continue;
        default:
            if (id < 128) {
                continue;
            }
        }
        const char *name = cs_group_name(ctx->cd, id);
        if (!name) {
            return true;
        }
        if (!strstr(a->features, name)) {
            return false;
        }
    }
    return true;
}

References a, ARM_GRP_ARM, ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, ARM_GRP_THUMB2, cs_group_name(), i, and if().

Referenced by disassemble().

disassemble()

static int disassemble ( RzAsm *  a, RzAsmOp *  op, const ut8 *  buf, int  len  )

static

Definition at line 86 of file asm_arm_cs.c.

                                                                       {
    ArmCSContext *ctx = (ArmCSContext *)a->plugin_data;
 
    bool disp_hash = a->immdisp;
    cs_insn *insn = NULL;
    cs_mode mode = 0;
    int ret, n = 0;
 
    bool thumb = a->bits == 16;
    mode |= thumb ? CS_MODE_THUMB : CS_MODE_ARM;
    mode |= (a->big_endian) ? CS_MODE_BIG_ENDIAN : CS_MODE_LITTLE_ENDIAN;
    if (mode != ctx->omode || a->bits != ctx->obits) {
        cs_close(&ctx->cd);
        ctx->cd = 0; // unnecessary
        ctx->omode = mode;
        ctx->obits = a->bits;
    }
 
    if (a->cpu) {
        if (strstr(a->cpu, "cortex")) {
            mode |= CS_MODE_MCLASS;
        }
        if (a->bits != 64) {
            if (strstr(a->cpu, "v8")) {
                mode |= CS_MODE_V8;
            }
        }
    }
    if (a->features && a->bits != 64) {
        if (strstr(a->features, "v8")) {
            mode |= CS_MODE_V8;
        }
    }
    if (op) {
        op->size = 4;
        rz_strbuf_set(&op->buf_asm, "");
    }
    if (!ctx->cd || mode != ctx->omode) {
        ret = (a->bits == 64) ? cs_open(CS_ARCH_ARM64, mode, &ctx->cd) : cs_open(CS_ARCH_ARM, mode, &ctx->cd);
        if (ret) {
            ret = -1;
            goto beach;
        }
    }
    cs_option(ctx->cd, CS_OPT_SYNTAX, (a->syntax == RZ_ASM_SYNTAX_REGNUM) ? CS_OPT_SYNTAX_NOREGNAME : CS_OPT_SYNTAX_DEFAULT);
    cs_option(ctx->cd, CS_OPT_DETAIL, (a->features && *a->features) ? CS_OPT_ON : CS_OPT_OFF);
    cs_option(ctx->cd, CS_OPT_DETAIL, CS_OPT_ON);
    if (!buf) {
        goto beach;
    }
    int haa = hackyArmAsm(a, op, buf, len);
    if (haa > 0) {
        return haa;
    }
 
    n = cs_disasm(ctx->cd, buf, RZ_MIN(4, len), a->pc, 1, &insn);
    if (n < 1 || insn->size < 1) {
        ret = -1;
        goto beach;
    }
    if (op) {
        op->size = 0;
    }
    if (a->features && *a->features) {
        if (!check_features(a, insn) && op) {
            op->size = insn->size;
            rz_strbuf_set(&op->buf_asm, "illegal");
        }
    }
    if (op && !op->size) {
        op->size = insn->size;
        if (insn->id == ARM_INS_IT) {
            rz_arm_it_update_block(&ctx->it, insn);
        } else {
            rz_arm_it_update_nonblock(&ctx->it, insn);
        }
        if (thumb && rz_arm_it_apply_cond(&ctx->it, insn)) {
            char *tmpstr = rz_str_newf("%s%s",
                cs_insn_name(ctx->cd, insn->id),
                cc_name(insn->detail->arm.cc));
            rz_str_cpy(insn->mnemonic, tmpstr);
            free(tmpstr);
        }
        char *buf_asm = sdb_fmt("%s%s%s",
            insn->mnemonic,
            insn->op_str[0] ? " " : "",
            insn->op_str);
        if (!disp_hash) {
            rz_str_replace_char(buf_asm, '#', 0);
        }
        rz_strbuf_set(&op->buf_asm, buf_asm);
    }
    cs_free(insn, n);
beach:
    cs_close(&ctx->cd);
    if (op) {
        if (!*rz_strbuf_get(&op->buf_asm)) {
            rz_strbuf_set(&op->buf_asm, "invalid");
        }
        return op->size;
    }
    return ret;
}

References a, ARM_INS_IT, cc_name(), check_features(), CS_ARCH_ARM, CS_ARCH_ARM64, cs_close(), cs_disasm(), cs_free(), cs_insn_name(), CS_MODE_ARM, CS_MODE_BIG_ENDIAN, CS_MODE_LITTLE_ENDIAN, CS_MODE_MCLASS, CS_MODE_THUMB, CS_MODE_V8, cs_open(), CS_OPT_DETAIL, CS_OPT_OFF, CS_OPT_ON, CS_OPT_SYNTAX, CS_OPT_SYNTAX_DEFAULT, CS_OPT_SYNTAX_NOREGNAME, cs_option(), free(), len, n, NULL, rz_arm_it_apply_cond(), rz_arm_it_update_block(), rz_arm_it_update_nonblock(), RZ_ASM_SYNTAX_REGNUM, RZ_MIN, rz_str_cpy, rz_str_newf(), rz_str_replace_char(), rz_strbuf_get(), rz_strbuf_set(), and sdb_fmt().

mnemonics()

static char* mnemonics ( RzAsm *  a, int  id, bool  json  )

static

Definition at line 261 of file asm_arm_cs.c.

                                                    {
    ArmCSContext *ctx = (ArmCSContext *)a->plugin_data;
    int i;
    a->cur->disassemble(a, NULL, NULL, -1);
    if (id != -1) {
        const char *name = cs_insn_name(ctx->cd, id);
        if (json) {
            return name ? rz_str_newf("[\"%s\"]\n", name) : NULL;
        }
        return name ? strdup(name) : NULL;
    }
    RzStrBuf *buf = rz_strbuf_new("");
    if (json) {
        rz_strbuf_append(buf, "[");
    }
    for (i = 1;; i++) {
        const char *op = cs_insn_name(ctx->cd, i);
        if (!op) {
            break;
        }
        if (json) {
            rz_strbuf_append(buf, "\"");
        }
        rz_strbuf_append(buf, op);
        if (json) {
            if (cs_insn_name(ctx->cd, i + 1)) {
                rz_strbuf_append(buf, "\",");
            } else {
                rz_strbuf_append(buf, "\"]\n");
            }
        } else {
            rz_strbuf_append(buf, "\n");
        }
    }
    return rz_strbuf_drain(buf);
}

References a, cs_insn_name(), i, NULL, rz_str_newf(), rz_strbuf_append(), rz_strbuf_drain(), rz_strbuf_new(), and strdup().

Variable Documentation

rizin_plugin

RZ_API RzLibStruct rizin_plugin

Initial value:

= {
    .type = RZ_LIB_TYPE_ASM,
    .data = &rz_asm_plugin_arm_cs,
    .version = RZ_VERSION
}

Definition at line 323 of file asm_arm_cs.c.

rz_asm_plugin_arm_cs

RzAsmPlugin rz_asm_plugin_arm_cs

Initial value:

= {
    .name = "arm",
    .desc = "Capstone ARM disassembler",
    .cpus = "v8,cortex,arm1176,cortexA72,cortexA8",
    .platforms = "bcm2835,omap3430",
    .features = "v8",
    .license = "BSD",
    .arch = "arm",
    .bits = 16 | 32 | 64,
    .endian = RZ_SYS_ENDIAN_LITTLE | RZ_SYS_ENDIAN_BIG,
    .disassemble = &disassemble,
    .mnemonics = mnemonics,
    .assemble = &assemble,
    .init = &arm_init,
    .fini = &arm_fini,
 
 
 
 
 
 
 
}

Definition at line 298 of file asm_arm_cs.c.