v810_disas.h File Reference

Go to the source code of this file.

Classes
struct	v810_cmd

Macros
#define	V810_INSTR_MAXLEN   24
#define	OPCODE(instr)   (((instr) >> 10) & 0x3F)
#define	REG1(instr)   ((instr)&0x1F)
#define	REG2(instr)   (((instr) >> 5) & 0x1F)
#define	IMM5(instr)   REG1((instr))
#define	COND(instr)   (((instr) >> 9) & 0xF)
#define	SIGN_EXT_T5(imm)   (((imm)&0x10) ? (imm) | 0xE0 : (imm))
#define	SIGN_EXT_T9(imm)   (((imm)&0x100) ? (imm) | 0xFFFFFE00 : (imm))
#define	SIGN_EXT_T26(imm)   (((imm)&0x2000000) ? (imm) | 0xFC000000 : (imm))
#define	DISP9(word1)   SIGN_EXT_T9((word1)&0x1FE)
#define	DISP26(word1, word2)   SIGN_EXT_T26((((word1)&0x3FF) << 16) | (word2))

Enumerations
enum	v810_cmd_opcodes {   V810_MOV = 0x0 , V810_ADD = 0x1 , V810_SUB = 0x2 , V810_CMP = 0x3 ,   V810_SHL = 0x4 , V810_SHR = 0x5 , V810_JMP = 0x6 , V810_SAR = 0x7 ,   V810_MUL = 0x8 , V810_DIV = 0x9 , V810_MULU = 0xA , V810_DIVU = 0xB ,   V810_OR = 0xC , V810_AND = 0xD , V810_XOR = 0xE , V810_NOT = 0xF ,   V810_MOV_IMM5 = 0x10 , V810_ADD_IMM5 = 0x11 , V810_SETF = 0x12 , V810_CMP_IMM5 = 0x13 ,   V810_SHL_IMM5 = 0x14 , V810_SHR_IMM5 = 0x15 , V810_CLI = 0x16 , V810_SAR_IMM5 = 0x17 ,   V810_TRAP = 0x18 , V810_RETI = 0x19 , V810_HALT = 0x1A , V810_LDSR = 0x1C ,   V810_STSR = 0x1D , V810_SEI = 0x1E , V810_BSTR = 0x1F , V810_BCOND = 0x20 ,   V810_MOVEA = 0x28 , V810_ADDI = 0x29 , V810_JR = 0x2A , V810_JAL = 0x2B ,   V810_ORI = 0x2C , V810_ANDI = 0x2D , V810_XORI = 0x2E , V810_MOVHI = 0x2F ,   V810_LDB = 0x30 , V810_LDH = 0x31 , V810_LDW = 0x33 , V810_STB = 0x34 ,   V810_STH = 0x35 , V810_STW = 0x37 , V810_INB = 0x38 , V810_INH = 0x39 ,   V810_CAXI = 0x3A , V810_INW = 0x3B , V810_OUTB = 0x3C , V810_OUTH = 0x3D ,   V810_EXT = 0x3E , V810_OUTW = 0x3F }
enum	v810_bit_ops {   V810_BIT_SCH0U = 0x0 , V810_BIT_SCH0D = 0x1 , V810_BIT_SCH1U = 0x2 , V810_BIT_SCH1D = 0x3 ,   V810_BIT_ORU = 0x8 , V810_BIT_ANDU = 0x9 , V810_BIT_XORU = 0xA , V810_BIT_MOVU = 0xB ,   V810_BIT_ORNU = 0xC , V810_BIT_ANDNU = 0xD , V810_BIT_XORNU = 0xE , V810_BIT_NOTU = 0xF }
enum	v810_ext_ops {   V810_EXT_CMPF_S = 0x0 , V810_EXT_CVT_WS = 0x2 , V810_EXT_CVT_SW = 0x3 , V810_EXT_ADDF_S = 0x4 ,   V810_EXT_SUBF_S = 0x5 , V810_EXT_MULF_S = 0x6 , V810_EXT_DIVF_S = 0x7 , V810_EXT_XB = 0x8 ,   V810_EXT_XH = 0x9 , V810_EXT_REV = 0xA , V810_EXT_TRNC_SW = 0xB , V810_EXT_MPYHW = 0xC }
enum	v810_conds {   V810_COND_V = 0x0 , V810_COND_L = 0x1 , V810_COND_E = 0x2 , V810_COND_NH = 0x3 ,   V810_COND_N = 0x4 , V810_COND_NONE = 0x5 , V810_COND_LT = 0x6 , V810_COND_LE = 0x7 ,   V810_COND_NV = 0x8 , V810_COND_NL = 0x9 , V810_COND_NE = 0xA , V810_COND_H = 0xB ,   V810_COND_P = 0xC , V810_COND_NOP = 0xD , V810_COND_GE = 0xE , V810_COND_GT = 0xF }
enum	v810_sysregs {   V810_SREG_EIPC = 0x0 , V810_SREG_EIPSW = 0x1 , V810_SREG_FEPC = 0x2 , V810_SREG_FEPSW = 0x3 ,   V810_SREG_ECR = 0x4 , V810_SREG_PSW = 0x5 , V810_SREG_PIR = 0x6 , V810_SREG_TKCW = 0x7 ,   V810_SREG_CHCW = 0x18 , V810_SREG_ADTRE = 0x19 }

Functions
int	v810_decode_command (const ut8 *instr, int len, struct v810_cmd *cmd)

Macro Definition Documentation

COND

#define COND

(

instr

)

(((instr) >> 9) & 0xF)

Definition at line 13 of file v810_disas.h.

DISP26

#define DISP26	(		word1,
			word2
	)		SIGN_EXT_T26((((word1)&0x3FF) << 16) | (word2))

Definition at line 20 of file v810_disas.h.

DISP9

#define DISP9

(

word1

)

SIGN_EXT_T9((word1)&0x1FE)

Definition at line 19 of file v810_disas.h.

IMM5

#define IMM5

(

instr

)

REG1((instr))

Definition at line 12 of file v810_disas.h.

OPCODE

#define OPCODE

(

instr

)

(((instr) >> 10) & 0x3F)

Definition at line 9 of file v810_disas.h.

REG1

#define REG1

(

instr

)

((instr)&0x1F)

Definition at line 10 of file v810_disas.h.

REG2

#define REG2

(

instr

)

(((instr) >> 5) & 0x1F)

Definition at line 11 of file v810_disas.h.

SIGN_EXT_T26

#define SIGN_EXT_T26

(

imm

)

(((imm)&0x2000000) ? (imm) | 0xFC000000 : (imm))

Definition at line 17 of file v810_disas.h.

SIGN_EXT_T5

#define SIGN_EXT_T5

(

imm

)

(((imm)&0x10) ? (imm) | 0xE0 : (imm))

Definition at line 15 of file v810_disas.h.

SIGN_EXT_T9

#define SIGN_EXT_T9

(

imm

)

(((imm)&0x100) ? (imm) | 0xFFFFFE00 : (imm))

Definition at line 16 of file v810_disas.h.

V810_INSTR_MAXLEN

#define V810_INSTR_MAXLEN   24

Definition at line 7 of file v810_disas.h.

Enumeration Type Documentation

v810_bit_ops

enum v810_bit_ops

Enumerator
V810_BIT_SCH0U
V810_BIT_SCH0D
V810_BIT_SCH1U
V810_BIT_SCH1D
V810_BIT_ORU
V810_BIT_ANDU
V810_BIT_XORU
V810_BIT_MOVU
V810_BIT_ORNU
V810_BIT_ANDNU
V810_BIT_XORNU
V810_BIT_NOTU

Definition at line 79 of file v810_disas.h.

                  {
    V810_BIT_SCH0U = 0x0,
    V810_BIT_SCH0D = 0x1,
    V810_BIT_SCH1U = 0x2,
    V810_BIT_SCH1D = 0x3,
    V810_BIT_ORU = 0x8,
    V810_BIT_ANDU = 0x9,
    V810_BIT_XORU = 0xA,
    V810_BIT_MOVU = 0xB,
    V810_BIT_ORNU = 0xC,
    V810_BIT_ANDNU = 0xD,
    V810_BIT_XORNU = 0xE,
    V810_BIT_NOTU = 0xF,
};

v810_cmd_opcodes

enum v810_cmd_opcodes

Enumerator
V810_MOV
V810_ADD
V810_SUB
V810_CMP
V810_SHL
V810_SHR
V810_JMP
V810_SAR
V810_MUL
V810_DIV
V810_MULU
V810_DIVU
V810_OR
V810_AND
V810_XOR
V810_NOT
V810_MOV_IMM5
V810_ADD_IMM5
V810_SETF
V810_CMP_IMM5
V810_SHL_IMM5
V810_SHR_IMM5
V810_CLI
V810_SAR_IMM5
V810_TRAP
V810_RETI
V810_HALT
V810_LDSR
V810_STSR
V810_SEI
V810_BSTR
V810_BCOND
V810_MOVEA
V810_ADDI
V810_JR
V810_JAL
V810_ORI
V810_ANDI
V810_XORI
V810_MOVHI
V810_LDB
V810_LDH
V810_LDW
V810_STB
V810_STH
V810_STW
V810_INB
V810_INH
V810_CAXI
V810_INW
V810_OUTB
V810_OUTH
V810_EXT
V810_OUTW

Definition at line 22 of file v810_disas.h.

                      {
    V810_MOV = 0x0,
    V810_ADD = 0x1,
    V810_SUB = 0x2,
    V810_CMP = 0x3,
    V810_SHL = 0x4,
    V810_SHR = 0x5,
    V810_JMP = 0x6,
    V810_SAR = 0x7,
    V810_MUL = 0x8,
    V810_DIV = 0x9,
    V810_MULU = 0xA,
    V810_DIVU = 0xB,
    V810_OR = 0xC,
    V810_AND = 0xD,
    V810_XOR = 0xE,
    V810_NOT = 0xF,
    V810_MOV_IMM5 = 0x10,
    V810_ADD_IMM5 = 0x11,
    V810_SETF = 0x12,
    V810_CMP_IMM5 = 0x13,
    V810_SHL_IMM5 = 0x14,
    V810_SHR_IMM5 = 0x15,
    V810_CLI = 0x16,
    V810_SAR_IMM5 = 0x17,
    V810_TRAP = 0x18,
    V810_RETI = 0x19,
    V810_HALT = 0x1A,
    V810_LDSR = 0x1C,
    V810_STSR = 0x1D,
    V810_SEI = 0x1E,
    V810_BSTR = 0x1F,
    V810_BCOND = 0x20,
    V810_MOVEA = 0x28,
    V810_ADDI = 0x29,
    V810_JR = 0x2A,
    V810_JAL = 0x2B,
    V810_ORI = 0x2C,
    V810_ANDI = 0x2D,
    V810_XORI = 0x2E,
    V810_MOVHI = 0x2F,
    V810_LDB = 0x30,
    V810_LDH = 0x31,
    V810_LDW = 0x33,
    V810_STB = 0x34,
    V810_STH = 0x35,
    V810_STW = 0x37,
    V810_INB = 0x38,
    V810_INH = 0x39,
    V810_CAXI = 0x3A,
    V810_INW = 0x3B,
    V810_OUTB = 0x3C,
    V810_OUTH = 0x3D,
    V810_EXT = 0x3E,
    V810_OUTW = 0x3F,
};

v810_conds

enum v810_conds

Enumerator
V810_COND_V
V810_COND_L
V810_COND_E
V810_COND_NH
V810_COND_N
V810_COND_NONE
V810_COND_LT
V810_COND_LE
V810_COND_NV
V810_COND_NL
V810_COND_NE
V810_COND_H
V810_COND_P
V810_COND_NOP
V810_COND_GE
V810_COND_GT

Definition at line 109 of file v810_disas.h.

                {
    V810_COND_V = 0x0,
    V810_COND_L = 0x1,
    V810_COND_E = 0x2,
    V810_COND_NH = 0x3,
    V810_COND_N = 0x4,
    V810_COND_NONE = 0x5,
    V810_COND_LT = 0x6,
    V810_COND_LE = 0x7,
    V810_COND_NV = 0x8,
    V810_COND_NL = 0x9,
    V810_COND_NE = 0xA,
    V810_COND_H = 0xB,
    V810_COND_P = 0xC,
    V810_COND_NOP = 0xD,
    V810_COND_GE = 0xE,
    V810_COND_GT = 0xF,
};

v810_ext_ops

enum v810_ext_ops

Enumerator
V810_EXT_CMPF_S
V810_EXT_CVT_WS
V810_EXT_CVT_SW
V810_EXT_ADDF_S
V810_EXT_SUBF_S
V810_EXT_MULF_S
V810_EXT_DIVF_S
V810_EXT_XB
V810_EXT_XH
V810_EXT_REV
V810_EXT_TRNC_SW
V810_EXT_MPYHW

Definition at line 94 of file v810_disas.h.

                  {
    V810_EXT_CMPF_S = 0x0,
    V810_EXT_CVT_WS = 0x2,
    V810_EXT_CVT_SW = 0x3,
    V810_EXT_ADDF_S = 0x4,
    V810_EXT_SUBF_S = 0x5,
    V810_EXT_MULF_S = 0x6,
    V810_EXT_DIVF_S = 0x7,
    V810_EXT_XB = 0x8,
    V810_EXT_XH = 0x9,
    V810_EXT_REV = 0xA,
    V810_EXT_TRNC_SW = 0xB,
    V810_EXT_MPYHW = 0xC,
};

v810_sysregs

enum v810_sysregs

Enumerator
V810_SREG_EIPC
V810_SREG_EIPSW
V810_SREG_FEPC
V810_SREG_FEPSW
V810_SREG_ECR
V810_SREG_PSW
V810_SREG_PIR
V810_SREG_TKCW
V810_SREG_CHCW
V810_SREG_ADTRE

Definition at line 128 of file v810_disas.h.

                  {
    V810_SREG_EIPC = 0x0,
    V810_SREG_EIPSW = 0x1,
    V810_SREG_FEPC = 0x2,
    V810_SREG_FEPSW = 0x3,
    V810_SREG_ECR = 0x4,
    V810_SREG_PSW = 0x5,
    V810_SREG_PIR = 0x6,
    V810_SREG_TKCW = 0x7,
    V810_SREG_CHCW = 0x18,
    V810_SREG_ADTRE = 0x19,
};

Function Documentation

v810_decode_command()

int v810_decode_command	(	const ut8 *	instr,
		int	len,
		struct v810_cmd *	cmd
	)

Definition at line 309 of file v810_disas.c.

                                                                         {
    int ret;
    ut16 word1 = 0;
    ut16 word2 = 0;
 
    word1 = rz_read_le16(instr);
    if (len >= 4) {
        word2 = rz_read_le16(instr + 2);
    }
 
    switch (OPCODE(word1)) {
    case V810_MOV:
    case V810_ADD:
    case V810_SUB:
    case V810_CMP:
    case V810_SHL:
    case V810_SHR:
    case V810_JMP:
    case V810_SAR:
    case V810_MUL:
    case V810_DIV:
    case V810_MULU:
    case V810_DIVU:
    case V810_OR:
    case V810_AND:
    case V810_NOT:
    case V810_XOR:
        ret = decode_reg_reg(word1, cmd);
        break;
    case V810_MOV_IMM5:
    case V810_ADD_IMM5:
    case V810_SETF:
    case V810_CMP_IMM5:
    case V810_SHL_IMM5:
    case V810_SHR_IMM5:
    case V810_CLI:
    case V810_SAR_IMM5:
    case V810_TRAP:
    case V810_RETI:
    case V810_HALT:
    case V810_LDSR:
    case V810_STSR:
    case V810_SEI:
        ret = decode_imm_reg(word1, cmd);
        break;
    case V810_MOVEA:
    case V810_ADDI:
    case V810_ORI:
    case V810_ANDI:
    case V810_XORI:
    case V810_MOVHI:
        ret = decode_3operands(word1, word2, cmd);
        break;
    case V810_JR:
    case V810_JAL:
        ret = decode_jump(word1, word2, cmd);
        break;
    case V810_LDB:
    case V810_LDH:
    case V810_LDW:
    case V810_STB:
    case V810_STH:
    case V810_STW:
    case V810_INB:
    case V810_INH:
    case V810_CAXI:
    case V810_INW:
    case V810_OUTB:
    case V810_OUTH:
    case V810_OUTW:
        ret = decode_load_store(word1, word2, cmd);
        break;
    case V810_BSTR:
        ret = decode_bit_op(word1, cmd);
        break;
    case V810_EXT:
        ret = decode_extended(word1, word2, cmd);
        break;
    default:
        if ((OPCODE(word1) >> 3) == 0x4) {
            ret = decode_bcond(word1, cmd);
        } else {
            ret = -1;
        }
    }
 
    if ((ret > 0) && (len < ret)) {
        ret = -1;
    }
 
    return ret;
}

References cmd, decode_3operands(), decode_bcond(), decode_bit_op(), decode_extended(), decode_imm_reg(), decode_jump(), decode_load_store(), decode_reg_reg(), len, OPCODE, rz_read_le16(), V810_ADD, V810_ADD_IMM5, V810_ADDI, V810_AND, V810_ANDI, V810_BSTR, V810_CAXI, V810_CLI, V810_CMP, V810_CMP_IMM5, V810_DIV, V810_DIVU, V810_EXT, V810_HALT, V810_INB, V810_INH, V810_INW, V810_JAL, V810_JMP, V810_JR, V810_LDB, V810_LDH, V810_LDSR, V810_LDW, V810_MOV, V810_MOV_IMM5, V810_MOVEA, V810_MOVHI, V810_MUL, V810_MULU, V810_NOT, V810_OR, V810_ORI, V810_OUTB, V810_OUTH, V810_OUTW, V810_RETI, V810_SAR, V810_SAR_IMM5, V810_SEI, V810_SETF, V810_SHL, V810_SHL_IMM5, V810_SHR, V810_SHR_IMM5, V810_STB, V810_STH, V810_STSR, V810_STW, V810_SUB, V810_TRAP, V810_XOR, and V810_XORI.

Referenced by disassemble(), and v810_op().