Rizin
unix-like reverse engineering framework and cli tools
amd29k.c
Go to the documentation of this file.
1 // SPDX-FileCopyrightText: 2019 deroad <wargio@libero.it>
2 // SPDX-License-Identifier: LGPL-3.0-only
3 #include "amd29k.h"
4 #include "amd29k_internal.h"
5 #include <stdio.h>
6 #include <string.h>
7 #include <rz_analysis.h>
8 
9 #define CPU_ANY "*"
10 
11 #define N_AMD29K_INSTRUCTIONS 207
12 
13 #define AMD29K_GET_TYPE(x, i) ((x)->type[(i)])
14 #define AMD29K_GET_VALUE(x, i) ((x)->operands[(i)])
15 #define AMD29K_SET_VALUE(x, i, v, t) \
16  ((x)->operands[(i)] = (v)); \
17  ((x)->type[(i)] = (t))
18 #define AMD29K_SET_INVALID(x, i) ((x)->type[(i)] = AMD29K_TYPE_UNK)
19 #define AMD29K_HAS_BIT(x) (((x)[0] & 1))
20 // Global registers
21 #define AMD29K_IS_REG_GR(x) ((x) >= 0 && (x) < 128)
22 // Local registers
23 #define AMD29K_IS_REG_LR(x) ((x) >= 128 && (x) < 256)
24 #define AMD29K_REGNAME(x) (AMD29K_IS_REG_GR(x) ? "gr" : "lr")
25 #define AMD29K_LR(x) (AMD29K_IS_REG_GR(x) ? (x) : (x)-127)
26 
27 static void decode_ra_rb_rci(amd29k_instr_t *instruction, const ut8 *buffer) {
28  AMD29K_SET_VALUE(instruction, 0, buffer[1], AMD29K_TYPE_REG);
29  AMD29K_SET_VALUE(instruction, 1, buffer[2], AMD29K_TYPE_REG);
30  if (AMD29K_HAS_BIT(buffer)) {
31  AMD29K_SET_VALUE(instruction, 2, buffer[3], AMD29K_TYPE_IMM);
32  } else {
33  AMD29K_SET_VALUE(instruction, 2, buffer[3], AMD29K_TYPE_REG);
34  }
35  AMD29K_SET_INVALID(instruction, 3);
36  AMD29K_SET_INVALID(instruction, 4);
37  AMD29K_SET_INVALID(instruction, 5);
38 }
39 
40 static void decode_ra_rb_rc(amd29k_instr_t *instruction, const ut8 *buffer) {
41  AMD29K_SET_VALUE(instruction, 0, buffer[1], AMD29K_TYPE_REG);
42  AMD29K_SET_VALUE(instruction, 1, buffer[2], AMD29K_TYPE_REG);
43  AMD29K_SET_VALUE(instruction, 2, buffer[3], AMD29K_TYPE_REG);
44  AMD29K_SET_INVALID(instruction, 3);
45  AMD29K_SET_INVALID(instruction, 4);
46  AMD29K_SET_INVALID(instruction, 5);
47 }
48 
49 static void decode_ra_imm16(amd29k_instr_t *instruction, const ut8 *buffer) {
50  int word = (buffer[1] << 8) + buffer[3];
51  AMD29K_SET_VALUE(instruction, 0, buffer[2], AMD29K_TYPE_REG);
52  AMD29K_SET_VALUE(instruction, 1, word, AMD29K_TYPE_IMM);
53  AMD29K_SET_INVALID(instruction, 2);
54  AMD29K_SET_INVALID(instruction, 3);
55  AMD29K_SET_INVALID(instruction, 4);
56  AMD29K_SET_INVALID(instruction, 5);
57 }
58 
59 static void decode_ra_i16_sh2(amd29k_instr_t *instruction, const ut8 *buffer) {
60  int word = (buffer[1] << 10) + (buffer[3] << 2);
61  if (word & 0x20000) {
62  word = (int)(0xfffc0000 | word);
63  }
64  AMD29K_SET_VALUE(instruction, 0, buffer[2], AMD29K_TYPE_REG);
65  if (AMD29K_HAS_BIT(buffer)) {
66  AMD29K_SET_VALUE(instruction, 1, word, AMD29K_TYPE_IMM);
67  } else {
68  AMD29K_SET_VALUE(instruction, 1, (ut32)word, AMD29K_TYPE_JMP);
69  }
70  AMD29K_SET_INVALID(instruction, 2);
71  AMD29K_SET_INVALID(instruction, 3);
72  AMD29K_SET_INVALID(instruction, 4);
73  AMD29K_SET_INVALID(instruction, 5);
74 }
75 
76 static void decode_imm16_sh2(amd29k_instr_t *instruction, const ut8 *buffer) {
77  int word = (buffer[1] << 10) + (buffer[3] << 2);
78  if (word & 0x20000) {
79  word = (int)(0xfffc0000 | word);
80  }
81  AMD29K_SET_VALUE(instruction, 0, word, AMD29K_HAS_BIT(buffer) ? AMD29K_TYPE_JMP : AMD29K_TYPE_IMM);
82  AMD29K_SET_INVALID(instruction, 1);
83  AMD29K_SET_INVALID(instruction, 2);
84  AMD29K_SET_INVALID(instruction, 3);
85  AMD29K_SET_INVALID(instruction, 4);
86  AMD29K_SET_INVALID(instruction, 5);
87 }
88 
89 static void decode_load_store(amd29k_instr_t *instruction, const ut8 *buffer) {
90  AMD29K_SET_VALUE(instruction, 0, ((buffer[1] & 0x80) >> 7), AMD29K_TYPE_IMM);
91  AMD29K_SET_VALUE(instruction, 1, (buffer[1] & 0x7F), AMD29K_TYPE_IMM);
92  AMD29K_SET_VALUE(instruction, 2, buffer[2], AMD29K_TYPE_REG);
93  AMD29K_SET_VALUE(instruction, 3, buffer[3], AMD29K_HAS_BIT(buffer) ? AMD29K_TYPE_IMM : AMD29K_TYPE_REG);
94  AMD29K_SET_INVALID(instruction, 4);
95  AMD29K_SET_INVALID(instruction, 5);
96 }
97 
98 static void decode_calli(amd29k_instr_t *instruction, const ut8 *buffer) {
99  AMD29K_SET_VALUE(instruction, 0, buffer[2], AMD29K_TYPE_REG);
100  AMD29K_SET_VALUE(instruction, 1, buffer[3], AMD29K_TYPE_REG);
101  AMD29K_SET_INVALID(instruction, 2);
102  AMD29K_SET_INVALID(instruction, 3);
103  AMD29K_SET_INVALID(instruction, 4);
104  AMD29K_SET_INVALID(instruction, 5);
105 }
106 
107 static void decode_rc_ra_imm(amd29k_instr_t *instruction, const ut8 *buffer) {
108  AMD29K_SET_VALUE(instruction, 0, buffer[1], AMD29K_TYPE_REG);
109  AMD29K_SET_VALUE(instruction, 1, buffer[2], AMD29K_TYPE_REG);
110  AMD29K_SET_VALUE(instruction, 2, (buffer[3] & 3), AMD29K_TYPE_IMM);
111  AMD29K_SET_INVALID(instruction, 3);
112  AMD29K_SET_INVALID(instruction, 4);
113  AMD29K_SET_INVALID(instruction, 5);
114 }
115 
116 static void decode_clz(amd29k_instr_t *instruction, const ut8 *buffer) {
117  AMD29K_SET_VALUE(instruction, 0, buffer[1], AMD29K_TYPE_REG);
118  AMD29K_SET_VALUE(instruction, 1, buffer[3], AMD29K_HAS_BIT(buffer) ? AMD29K_TYPE_IMM : AMD29K_TYPE_REG);
119  AMD29K_SET_INVALID(instruction, 2);
120  AMD29K_SET_INVALID(instruction, 3);
121  AMD29K_SET_INVALID(instruction, 4);
122  AMD29K_SET_INVALID(instruction, 5);
123 }
124 
125 static void decode_convert(amd29k_instr_t *instruction, const ut8 *buffer) {
126  // lambda w,ea: (w >> 24,[decode_byte1(w), decode_byte2(w), ('imm',False,(w&0x80)>>7), ('imm',False,(w&0x70)>>4), ('imm',False,(w&0xC)>>2), ('imm',False, w&3)])
127  AMD29K_SET_VALUE(instruction, 0, buffer[1], AMD29K_TYPE_REG);
128  AMD29K_SET_VALUE(instruction, 1, buffer[2], AMD29K_TYPE_REG);
129  AMD29K_SET_VALUE(instruction, 2, ((buffer[3] & 0x80) >> 7), AMD29K_TYPE_IMM);
130  AMD29K_SET_VALUE(instruction, 3, ((buffer[3] & 0x70) >> 4), AMD29K_TYPE_IMM);
131  AMD29K_SET_VALUE(instruction, 4, ((buffer[3] & 0x0c) >> 2), AMD29K_TYPE_IMM);
132  AMD29K_SET_VALUE(instruction, 5, (buffer[3] & 0x03), AMD29K_TYPE_IMM);
133 }
134 
135 static void decode_rc_ra(amd29k_instr_t *instruction, const ut8 *buffer) {
136  AMD29K_SET_VALUE(instruction, 0, buffer[1], AMD29K_TYPE_REG);
137  AMD29K_SET_VALUE(instruction, 1, buffer[2], AMD29K_TYPE_REG);
138  AMD29K_SET_INVALID(instruction, 2);
139  AMD29K_SET_INVALID(instruction, 3);
140  AMD29K_SET_INVALID(instruction, 4);
141  AMD29K_SET_INVALID(instruction, 5);
142 }
143 
144 static void decode_dmac_fmac(amd29k_instr_t *instruction, const ut8 *buffer) {
145  AMD29K_SET_VALUE(instruction, 0, ((buffer[1] & 0x3c) >> 2), AMD29K_TYPE_IMM);
146  AMD29K_SET_VALUE(instruction, 1, (buffer[1] & 0x03), AMD29K_TYPE_IMM);
147  AMD29K_SET_VALUE(instruction, 2, buffer[1], AMD29K_TYPE_REG);
148  AMD29K_SET_VALUE(instruction, 3, buffer[2], AMD29K_TYPE_REG);
149  AMD29K_SET_INVALID(instruction, 4);
150  AMD29K_SET_INVALID(instruction, 5);
151 }
152 
153 static void decode_ra_rb(amd29k_instr_t *instruction, const ut8 *buffer) {
154  AMD29K_SET_VALUE(instruction, 0, buffer[1], AMD29K_TYPE_REG);
155  AMD29K_SET_VALUE(instruction, 1, buffer[3], AMD29K_TYPE_REG);
156  AMD29K_SET_INVALID(instruction, 2);
157  AMD29K_SET_INVALID(instruction, 3);
158  AMD29K_SET_INVALID(instruction, 4);
159  AMD29K_SET_INVALID(instruction, 5);
160 }
161 
162 static void decode_rb(amd29k_instr_t *instruction, const ut8 *buffer) {
163  AMD29K_SET_VALUE(instruction, 0, buffer[3], AMD29K_TYPE_REG);
164  AMD29K_SET_INVALID(instruction, 1);
165  AMD29K_SET_INVALID(instruction, 2);
166  AMD29K_SET_INVALID(instruction, 3);
167  AMD29K_SET_INVALID(instruction, 4);
168  AMD29K_SET_INVALID(instruction, 5);
169 }
170 
171 static void decode_rc_imm(amd29k_instr_t *instruction, const ut8 *buffer) {
172  AMD29K_SET_VALUE(instruction, 0, buffer[1], AMD29K_TYPE_REG);
173  AMD29K_SET_VALUE(instruction, 1, ((buffer[3] & 0x0c) >> 2), AMD29K_TYPE_IMM);
174  AMD29K_SET_VALUE(instruction, 2, (buffer[3] & 0x03), AMD29K_TYPE_IMM);
175  AMD29K_SET_INVALID(instruction, 3);
176  AMD29K_SET_INVALID(instruction, 4);
177  AMD29K_SET_INVALID(instruction, 5);
178 }
179 
180 static void decode_ra_imm(amd29k_instr_t *instruction, const ut8 *buffer) {
181  AMD29K_SET_VALUE(instruction, 0, buffer[2], AMD29K_TYPE_REG);
182  AMD29K_SET_VALUE(instruction, 1, ((buffer[3] & 0x0c) >> 2), AMD29K_TYPE_IMM);
183  AMD29K_SET_VALUE(instruction, 2, (buffer[3] & 0x03), AMD29K_TYPE_IMM);
184  AMD29K_SET_INVALID(instruction, 3);
185  AMD29K_SET_INVALID(instruction, 4);
186  AMD29K_SET_INVALID(instruction, 5);
187 }
188 
189 static void decode_mfsr(amd29k_instr_t *instruction, const ut8 *buffer) {
190  AMD29K_SET_VALUE(instruction, 0, buffer[1], AMD29K_TYPE_REG);
191  AMD29K_SET_VALUE(instruction, 1, buffer[2], AMD29K_TYPE_REG);
192  AMD29K_SET_INVALID(instruction, 2);
193  AMD29K_SET_INVALID(instruction, 3);
194  AMD29K_SET_INVALID(instruction, 4);
195  AMD29K_SET_INVALID(instruction, 5);
196 }
197 
198 static void decode_mtsr(amd29k_instr_t *instruction, const ut8 *buffer) {
199  AMD29K_SET_VALUE(instruction, 0, buffer[2], AMD29K_TYPE_REG);
200  AMD29K_SET_VALUE(instruction, 1, buffer[3], AMD29K_TYPE_REG);
201  AMD29K_SET_INVALID(instruction, 2);
202  AMD29K_SET_INVALID(instruction, 3);
203  AMD29K_SET_INVALID(instruction, 4);
204  AMD29K_SET_INVALID(instruction, 5);
205 }
206 
207 static void decode_none(amd29k_instr_t *instruction, const ut8 *buffer) {
208  // lambda w,ea: (w >> 24, None)
209  AMD29K_SET_INVALID(instruction, 0);
210  AMD29K_SET_INVALID(instruction, 1);
211  AMD29K_SET_INVALID(instruction, 2);
212  AMD29K_SET_INVALID(instruction, 3);
213  AMD29K_SET_INVALID(instruction, 4);
214  AMD29K_SET_INVALID(instruction, 5);
215 }
216 
217 const amd29k_instruction_t amd29k_instructions[N_AMD29K_INSTRUCTIONS] = {
218  { CPU_ANY, "illegal", RZ_ANALYSIS_OP_TYPE_NULL, 0x00, decode_none, NULL },
219  { CPU_ANY, "add", RZ_ANALYSIS_OP_TYPE_ADD, 0x14, decode_ra_rb_rci, NULL },
220  { CPU_ANY, "add", RZ_ANALYSIS_OP_TYPE_ADD, 0x15, decode_ra_rb_rci, NULL },
221  { CPU_ANY, "addc", RZ_ANALYSIS_OP_TYPE_ADD, 0x1C, decode_ra_rb_rci, NULL },
222  { CPU_ANY, "addc", RZ_ANALYSIS_OP_TYPE_ADD, 0x1D, decode_ra_rb_rci, NULL },
223  { CPU_ANY, "addcs", RZ_ANALYSIS_OP_TYPE_ADD, 0x18, decode_ra_rb_rci, NULL },
224  { CPU_ANY, "addcs", RZ_ANALYSIS_OP_TYPE_ADD, 0x19, decode_ra_rb_rci, NULL },
225  { CPU_ANY, "addcu", RZ_ANALYSIS_OP_TYPE_ADD, 0x1A, decode_ra_rb_rci, NULL },
226  { CPU_ANY, "addcu", RZ_ANALYSIS_OP_TYPE_ADD, 0x1B, decode_ra_rb_rci, NULL },
227  { CPU_ANY, "adds", RZ_ANALYSIS_OP_TYPE_ADD, 0x10, decode_ra_rb_rci, NULL },
228  { CPU_ANY, "adds", RZ_ANALYSIS_OP_TYPE_ADD, 0x11, decode_ra_rb_rci, NULL },
229  { CPU_ANY, "addu", RZ_ANALYSIS_OP_TYPE_ADD, 0x12, decode_ra_rb_rci, NULL },
230  { CPU_ANY, "addu", RZ_ANALYSIS_OP_TYPE_ADD, 0x13, decode_ra_rb_rci, NULL },
231  { CPU_ANY, "and", RZ_ANALYSIS_OP_TYPE_AND, 0x90, decode_ra_rb_rci, NULL },
232  { CPU_ANY, "and", RZ_ANALYSIS_OP_TYPE_AND, 0x91, decode_ra_rb_rci, NULL },
233  { CPU_ANY, "andn", RZ_ANALYSIS_OP_TYPE_AND, 0x9C, decode_ra_rb_rci, NULL },
234  { CPU_ANY, "andn", RZ_ANALYSIS_OP_TYPE_AND, 0x9D, decode_ra_rb_rci, NULL },
235  { CPU_ANY, "aseq", RZ_ANALYSIS_OP_TYPE_CMP, 0x70, decode_ra_rb_rci, NULL },
236  { CPU_ANY, "asge", RZ_ANALYSIS_OP_TYPE_CMP, 0x5C, decode_ra_rb_rci, NULL },
237  { CPU_ANY, "asge", RZ_ANALYSIS_OP_TYPE_CMP, 0x5D, decode_ra_rb_rci, NULL },
238  { CPU_ANY, "asgeu", RZ_ANALYSIS_OP_TYPE_CMP, 0x5E, decode_ra_rb_rci, NULL },
239  { CPU_ANY, "asgeu", RZ_ANALYSIS_OP_TYPE_CMP, 0x5F, decode_ra_rb_rci, NULL },
240  { CPU_ANY, "asgt", RZ_ANALYSIS_OP_TYPE_CMP, 0x58, decode_ra_rb_rci, NULL },
241  { CPU_ANY, "asgt", RZ_ANALYSIS_OP_TYPE_CMP, 0x59, decode_ra_rb_rci, NULL },
242  { CPU_ANY, "asgtu", RZ_ANALYSIS_OP_TYPE_CMP, 0x5A, decode_ra_rb_rci, NULL },
243  { CPU_ANY, "asgtu", RZ_ANALYSIS_OP_TYPE_CMP, 0x5B, decode_ra_rb_rci, NULL },
244  { CPU_ANY, "asle", RZ_ANALYSIS_OP_TYPE_CMP, 0x54, decode_ra_rb_rci, NULL },
245  { CPU_ANY, "asle", RZ_ANALYSIS_OP_TYPE_CMP, 0x55, decode_ra_rb_rci, NULL },
246  { CPU_ANY, "asleu", RZ_ANALYSIS_OP_TYPE_CMP, 0x56, decode_ra_rb_rci, NULL },
247  { CPU_ANY, "asleu", RZ_ANALYSIS_OP_TYPE_CMP, 0x57, decode_ra_rb_rci, NULL },
248  { CPU_ANY, "aslt", RZ_ANALYSIS_OP_TYPE_CMP, 0x50, decode_ra_rb_rci, NULL },
249  { CPU_ANY, "aslt", RZ_ANALYSIS_OP_TYPE_CMP, 0x51, decode_ra_rb_rci, NULL },
250  { CPU_ANY, "asltu", RZ_ANALYSIS_OP_TYPE_CMP, 0x52, decode_ra_rb_rci, NULL },
251  { CPU_ANY, "asltu", RZ_ANALYSIS_OP_TYPE_CMP, 0x53, decode_ra_rb_rci, NULL },
252  { CPU_ANY, "asneq", RZ_ANALYSIS_OP_TYPE_CMP, 0x72, decode_ra_rb_rci, NULL },
253  { CPU_ANY, "asneq", RZ_ANALYSIS_OP_TYPE_CMP, 0x73, decode_ra_rb_rci, NULL },
254  { CPU_ANY, "call", RZ_ANALYSIS_OP_TYPE_CALL, 0xA8, decode_ra_i16_sh2, NULL },
255  { CPU_ANY, "call", RZ_ANALYSIS_OP_TYPE_CALL, 0xA9, decode_ra_i16_sh2, NULL },
256  { CPU_ANY, "calli", RZ_ANALYSIS_OP_TYPE_ICALL, 0xC8, decode_calli, NULL },
257  { CPU_29050, "class", RZ_ANALYSIS_OP_TYPE_NULL, 0xE6, decode_rc_ra_imm, NULL },
258  { CPU_ANY, "clz", RZ_ANALYSIS_OP_TYPE_NULL, 0x08, decode_clz, NULL },
259  { CPU_ANY, "clz", RZ_ANALYSIS_OP_TYPE_NULL, 0x09, decode_clz, NULL },
260  { CPU_ANY, "const", RZ_ANALYSIS_OP_TYPE_MOV, 0x03, decode_ra_imm16, NULL },
261  { CPU_ANY, "consth", RZ_ANALYSIS_OP_TYPE_MOV, 0x02, decode_ra_imm16, NULL },
262  { CPU_ANY, "consthz", RZ_ANALYSIS_OP_TYPE_MOV, 0x05, decode_ra_imm16, NULL },
263  { CPU_ANY, "constn", RZ_ANALYSIS_OP_TYPE_MOV, 0x01, decode_ra_imm16, NULL },
264  { CPU_29050, "convert", RZ_ANALYSIS_OP_TYPE_NULL, 0xE4, decode_convert, NULL },
265  { CPU_ANY, "cpbyte", RZ_ANALYSIS_OP_TYPE_CMP, 0x2E, decode_ra_rb_rci, NULL },
266  { CPU_ANY, "cpbyte", RZ_ANALYSIS_OP_TYPE_CMP, 0x2F, decode_ra_rb_rci, NULL },
267  { CPU_ANY, "cpeq", RZ_ANALYSIS_OP_TYPE_CMP, 0x60, decode_ra_rb_rci, NULL },
268  { CPU_ANY, "cpeq", RZ_ANALYSIS_OP_TYPE_CMP, 0x61, decode_ra_rb_rci, NULL },
269  { CPU_ANY, "cpge", RZ_ANALYSIS_OP_TYPE_CMP, 0x4C, decode_ra_rb_rci, NULL },
270  { CPU_ANY, "cpge", RZ_ANALYSIS_OP_TYPE_CMP, 0x4D, decode_ra_rb_rci, NULL },
271  { CPU_ANY, "cpgeu", RZ_ANALYSIS_OP_TYPE_CMP, 0x4E, decode_ra_rb_rci, NULL },
272  { CPU_ANY, "cpgeu", RZ_ANALYSIS_OP_TYPE_CMP, 0x4F, decode_ra_rb_rci, NULL },
273  { CPU_ANY, "cpgt", RZ_ANALYSIS_OP_TYPE_CMP, 0x48, decode_ra_rb_rci, NULL },
274  { CPU_ANY, "cpgt", RZ_ANALYSIS_OP_TYPE_CMP, 0x49, decode_ra_rb_rci, NULL },
275  { CPU_ANY, "cpgtu", RZ_ANALYSIS_OP_TYPE_CMP, 0x4A, decode_ra_rb_rci, NULL },
276  { CPU_ANY, "cpgtu", RZ_ANALYSIS_OP_TYPE_CMP, 0x4B, decode_ra_rb_rci, NULL },
277  { CPU_ANY, "cple", RZ_ANALYSIS_OP_TYPE_CMP, 0x44, decode_ra_rb_rci, NULL },
278  { CPU_ANY, "cple", RZ_ANALYSIS_OP_TYPE_CMP, 0x45, decode_ra_rb_rci, NULL },
279  { CPU_ANY, "cpleu", RZ_ANALYSIS_OP_TYPE_CMP, 0x46, decode_ra_rb_rci, NULL },
280  { CPU_ANY, "cpleu", RZ_ANALYSIS_OP_TYPE_CMP, 0x47, decode_ra_rb_rci, NULL },
281  { CPU_ANY, "cplt", RZ_ANALYSIS_OP_TYPE_CMP, 0x40, decode_ra_rb_rci, NULL },
282  { CPU_ANY, "cplt", RZ_ANALYSIS_OP_TYPE_CMP, 0x41, decode_ra_rb_rci, NULL },
283  { CPU_ANY, "cpltu", RZ_ANALYSIS_OP_TYPE_CMP, 0x42, decode_ra_rb_rci, NULL },
284  { CPU_ANY, "cpltu", RZ_ANALYSIS_OP_TYPE_CMP, 0x43, decode_ra_rb_rci, NULL },
285  { CPU_ANY, "cpneq", RZ_ANALYSIS_OP_TYPE_CMP, 0x62, decode_ra_rb_rci, NULL },
286  { CPU_ANY, "cpneq", RZ_ANALYSIS_OP_TYPE_CMP, 0x63, decode_ra_rb_rci, NULL },
287  { CPU_29000, "cvdf", RZ_ANALYSIS_OP_TYPE_NULL, 0xE9, decode_rc_ra, NULL },
288  { CPU_29000, "cvdint", RZ_ANALYSIS_OP_TYPE_NULL, 0xE7, decode_rc_ra, NULL },
289  { CPU_29000, "cvfd", RZ_ANALYSIS_OP_TYPE_NULL, 0xE8, decode_rc_ra, NULL },
290  { CPU_29000, "cvfint", RZ_ANALYSIS_OP_TYPE_NULL, 0xE6, decode_rc_ra, NULL },
291  { CPU_29000, "cvintd", RZ_ANALYSIS_OP_TYPE_NULL, 0xE5, decode_rc_ra, NULL },
292  { CPU_29000, "cvintf", RZ_ANALYSIS_OP_TYPE_NULL, 0xE4, decode_rc_ra, NULL },
293  { CPU_ANY, "dadd", RZ_ANALYSIS_OP_TYPE_NULL, 0xF1, decode_ra_rb_rc, NULL },
294  { CPU_ANY, "ddiv", RZ_ANALYSIS_OP_TYPE_DIV, 0xF7, decode_ra_rb_rc, NULL },
295  { CPU_ANY, "deq", RZ_ANALYSIS_OP_TYPE_CMP, 0xEB, decode_ra_rb_rc, NULL },
296  { CPU_29050, "dge", RZ_ANALYSIS_OP_TYPE_CMP, 0xEF, decode_ra_rb_rc, NULL },
297  { CPU_ANY, "dgt", RZ_ANALYSIS_OP_TYPE_CMP, 0xED, decode_ra_rb_rc, NULL },
298  { CPU_ANY, "div", RZ_ANALYSIS_OP_TYPE_DIV, 0x6A, decode_ra_rb_rci, NULL },
299  { CPU_ANY, "div", RZ_ANALYSIS_OP_TYPE_DIV, 0x6B, decode_ra_rb_rci, NULL },
300  { CPU_ANY, "div0", RZ_ANALYSIS_OP_TYPE_DIV, 0x68, decode_ra_rb_rci, NULL },
301  { CPU_ANY, "div0", RZ_ANALYSIS_OP_TYPE_DIV, 0x69, decode_ra_rb_rci, NULL },
302  { CPU_ANY, "divide", RZ_ANALYSIS_OP_TYPE_DIV, 0xE1, decode_ra_rb_rc, NULL },
303  { CPU_29050, "dividu", RZ_ANALYSIS_OP_TYPE_DIV, 0xE3, decode_ra_rb_rc, NULL },
304  { CPU_ANY, "divl", RZ_ANALYSIS_OP_TYPE_DIV, 0x6C, decode_ra_rb_rci, NULL },
305  { CPU_ANY, "divl", RZ_ANALYSIS_OP_TYPE_DIV, 0x6D, decode_ra_rb_rci, NULL },
306  { CPU_ANY, "divrem", RZ_ANALYSIS_OP_TYPE_DIV, 0x6E, decode_ra_rb_rci, NULL },
307  { CPU_ANY, "divrem", RZ_ANALYSIS_OP_TYPE_DIV, 0x6F, decode_ra_rb_rci, NULL },
308  { CPU_29000, "dlt", RZ_ANALYSIS_OP_TYPE_CMP, 0xEF, decode_ra_rb_rc, NULL },
309  { CPU_29050, "dmac", RZ_ANALYSIS_OP_TYPE_NULL, 0xD9, decode_dmac_fmac, NULL },
310  { CPU_29050, "dmsm", RZ_ANALYSIS_OP_TYPE_NULL, 0xDB, decode_ra_rb_rc, NULL },
311  { CPU_ANY, "dmul", RZ_ANALYSIS_OP_TYPE_MUL, 0xF5, decode_ra_rb_rc, NULL },
312  { CPU_ANY, "dsub", RZ_ANALYSIS_OP_TYPE_SUB, 0xF3, decode_ra_rb_rc, NULL },
313  { CPU_ANY, "emulate", RZ_ANALYSIS_OP_TYPE_NULL, 0xF8, decode_ra_rb_rci, NULL },
314  { CPU_ANY, "exbyte", RZ_ANALYSIS_OP_TYPE_NULL, 0x0A, decode_ra_rb_rci, NULL },
315  { CPU_ANY, "exbyte", RZ_ANALYSIS_OP_TYPE_NULL, 0x0B, decode_ra_rb_rci, NULL },
316  { CPU_ANY, "exhw", RZ_ANALYSIS_OP_TYPE_NULL, 0x7C, decode_ra_rb_rci, NULL },
317  { CPU_ANY, "exhw", RZ_ANALYSIS_OP_TYPE_NULL, 0x7D, decode_ra_rb_rci, NULL },
318  { CPU_ANY, "exhws", RZ_ANALYSIS_OP_TYPE_NULL, 0x7E, decode_rc_ra, NULL },
319  { CPU_ANY, "extract", RZ_ANALYSIS_OP_TYPE_NULL, 0x7A, decode_ra_rb_rci, NULL },
320  { CPU_ANY, "extract", RZ_ANALYSIS_OP_TYPE_NULL, 0x7B, decode_ra_rb_rci, NULL },
321  { CPU_ANY, "fadd", RZ_ANALYSIS_OP_TYPE_ADD, 0xF0, decode_ra_rb_rc, NULL },
322  { CPU_ANY, "fdiv", RZ_ANALYSIS_OP_TYPE_DIV, 0xF6, decode_ra_rb_rc, NULL },
323  { CPU_29050, "fdmul", RZ_ANALYSIS_OP_TYPE_MUL, 0xF9, decode_ra_rb_rc, NULL },
324  { CPU_ANY, "feq", RZ_ANALYSIS_OP_TYPE_CMP, 0xEA, decode_ra_rb_rc, NULL },
325  { CPU_29050, "fge", RZ_ANALYSIS_OP_TYPE_CMP, 0xEE, decode_ra_rb_rc, NULL },
326  { CPU_ANY, "fgt", RZ_ANALYSIS_OP_TYPE_CMP, 0xEC, decode_ra_rb_rc, NULL },
327  { CPU_29000, "flt", RZ_ANALYSIS_OP_TYPE_CMP, 0xEE, decode_ra_rb_rc, NULL },
328  { CPU_29050, "fmac", RZ_ANALYSIS_OP_TYPE_NULL, 0xD8, decode_dmac_fmac, NULL },
329  { CPU_29050, "fmsm", RZ_ANALYSIS_OP_TYPE_NULL, 0xDA, decode_ra_rb_rc, NULL },
330  { CPU_ANY, "fmul", RZ_ANALYSIS_OP_TYPE_MUL, 0xF4, decode_ra_rb_rc, NULL },
331  { CPU_ANY, "fsub", RZ_ANALYSIS_OP_TYPE_SUB, 0xF2, decode_ra_rb_rc, NULL },
332  { CPU_ANY, "halt", RZ_ANALYSIS_OP_TYPE_RET, 0x89, decode_none, NULL },
333  { CPU_ANY, "inbyte", RZ_ANALYSIS_OP_TYPE_NULL, 0x0C, decode_ra_rb_rci, NULL },
334  { CPU_ANY, "inbyte", RZ_ANALYSIS_OP_TYPE_NULL, 0x0D, decode_ra_rb_rci, NULL },
335  { CPU_ANY, "inhw", RZ_ANALYSIS_OP_TYPE_NULL, 0x78, decode_ra_rb_rci, NULL },
336  { CPU_ANY, "inhw", RZ_ANALYSIS_OP_TYPE_NULL, 0x79, decode_ra_rb_rci, NULL },
337  { CPU_ANY, "inv", RZ_ANALYSIS_OP_TYPE_NULL, 0x9F, decode_none, NULL },
338  { CPU_ANY, "iret", RZ_ANALYSIS_OP_TYPE_RET, 0x88, decode_none, NULL },
339  { CPU_ANY, "iretinv", RZ_ANALYSIS_OP_TYPE_RET, 0x8C, decode_none, NULL },
340  { CPU_ANY, "jmp", RZ_ANALYSIS_OP_TYPE_JMP, 0xA0, decode_imm16_sh2, NULL },
341  { CPU_ANY, "jmp", RZ_ANALYSIS_OP_TYPE_JMP, 0xA1, decode_imm16_sh2, NULL },
342  { CPU_ANY, "jmpf", RZ_ANALYSIS_OP_TYPE_CJMP, 0xA4, decode_ra_i16_sh2, NULL },
343  { CPU_ANY, "jmpf", RZ_ANALYSIS_OP_TYPE_CJMP, 0xA5, decode_ra_i16_sh2, NULL },
344  { CPU_ANY, "jmpfdec", RZ_ANALYSIS_OP_TYPE_CJMP, 0xB4, decode_ra_i16_sh2, NULL },
345  { CPU_ANY, "jmpfdec", RZ_ANALYSIS_OP_TYPE_CJMP, 0xB5, decode_ra_i16_sh2, NULL },
346  { CPU_ANY, "jmpfi", RZ_ANALYSIS_OP_TYPE_RCJMP, 0xC4, decode_ra_rb, NULL },
347  { CPU_ANY, "jmpi", RZ_ANALYSIS_OP_TYPE_RJMP, 0xC0, decode_rb, NULL },
348  { CPU_ANY, "jmpt", RZ_ANALYSIS_OP_TYPE_CJMP, 0xAC, decode_ra_i16_sh2, NULL },
349  { CPU_ANY, "jmpti", RZ_ANALYSIS_OP_TYPE_RCJMP, 0xCC, decode_ra_rb, NULL },
350  { CPU_29050, "mfacc", RZ_ANALYSIS_OP_TYPE_NULL, 0xE9, decode_rc_imm, NULL },
351  { CPU_29050, "mtacc", RZ_ANALYSIS_OP_TYPE_NULL, 0xE8, decode_ra_imm, NULL },
352  { CPU_ANY, "mfsr", RZ_ANALYSIS_OP_TYPE_NULL, 0xC6, decode_mfsr, NULL },
353  { CPU_ANY, "mftlb", RZ_ANALYSIS_OP_TYPE_NULL, 0xB6, decode_rc_ra, NULL },
354  { CPU_ANY, "mtsr", RZ_ANALYSIS_OP_TYPE_NULL, 0xCE, decode_mtsr, NULL },
355  { CPU_ANY, "mtsrim", RZ_ANALYSIS_OP_TYPE_NULL, 0x04, decode_ra_imm16, NULL },
356  { CPU_ANY, "mttlb", RZ_ANALYSIS_OP_TYPE_NULL, 0xBE, decode_ra_rb, NULL },
357  { CPU_ANY, "mul", RZ_ANALYSIS_OP_TYPE_MUL, 0x64, decode_ra_rb_rci, NULL },
358  { CPU_ANY, "mul", RZ_ANALYSIS_OP_TYPE_MUL, 0x65, decode_ra_rb_rci, NULL },
359  { CPU_ANY, "mull", RZ_ANALYSIS_OP_TYPE_MUL, 0x66, decode_ra_rb_rci, NULL },
360  { CPU_ANY, "mull", RZ_ANALYSIS_OP_TYPE_MUL, 0x67, decode_ra_rb_rci, NULL },
361  { CPU_29050, "multiplu", RZ_ANALYSIS_OP_TYPE_MUL, 0xE2, decode_ra_rb_rc, NULL },
362  { CPU_ANY, "multiply", RZ_ANALYSIS_OP_TYPE_MUL, 0xE0, decode_ra_rb_rc, NULL },
363  { CPU_29050, "multm", RZ_ANALYSIS_OP_TYPE_MUL, 0xDE, decode_ra_rb_rc, NULL },
364  { CPU_29050, "multmu", RZ_ANALYSIS_OP_TYPE_MUL, 0xDF, decode_ra_rb_rc, NULL },
365  { CPU_ANY, "mulu", RZ_ANALYSIS_OP_TYPE_MUL, 0x74, decode_ra_rb_rci, NULL },
366  { CPU_ANY, "mulu", RZ_ANALYSIS_OP_TYPE_MUL, 0x75, decode_ra_rb_rci, NULL },
367  { CPU_ANY, "nand", RZ_ANALYSIS_OP_TYPE_AND, 0x9A, decode_ra_rb_rci, NULL },
368  { CPU_ANY, "nand", RZ_ANALYSIS_OP_TYPE_AND, 0x9B, decode_ra_rb_rci, NULL },
369  { CPU_ANY, "nor", RZ_ANALYSIS_OP_TYPE_NOR, 0x98, decode_ra_rb_rci, NULL },
370  { CPU_ANY, "nor", RZ_ANALYSIS_OP_TYPE_NOR, 0x99, decode_ra_rb_rci, NULL },
371  { CPU_ANY, "or", RZ_ANALYSIS_OP_TYPE_OR, 0x92, decode_ra_rb_rci, NULL },
372  { CPU_ANY, "or", RZ_ANALYSIS_OP_TYPE_OR, 0x93, decode_ra_rb_rci, NULL },
373  { CPU_29050, "orn", RZ_ANALYSIS_OP_TYPE_OR, 0xAA, decode_ra_rb_rci, NULL },
374  { CPU_29050, "orn", RZ_ANALYSIS_OP_TYPE_OR, 0xAB, decode_ra_rb_rci, NULL },
375  { CPU_ANY, "setip", RZ_ANALYSIS_OP_TYPE_NULL, 0x9E, decode_ra_rb_rc, NULL },
376  { CPU_ANY, "sll", RZ_ANALYSIS_OP_TYPE_SHL, 0x80, decode_ra_rb_rci, NULL },
377  { CPU_ANY, "sll", RZ_ANALYSIS_OP_TYPE_SHL, 0x81, decode_ra_rb_rci, NULL },
378  { CPU_29050, "sqrt", RZ_ANALYSIS_OP_TYPE_NULL, 0xE5, decode_rc_ra_imm, NULL },
379  { CPU_ANY, "sra", RZ_ANALYSIS_OP_TYPE_SHR, 0x86, decode_ra_rb_rci, NULL },
380  { CPU_ANY, "sra", RZ_ANALYSIS_OP_TYPE_SHR, 0x87, decode_ra_rb_rci, NULL },
381  { CPU_ANY, "srl", RZ_ANALYSIS_OP_TYPE_SAL, 0x82, decode_ra_rb_rci, NULL },
382  { CPU_ANY, "srl", RZ_ANALYSIS_OP_TYPE_SAL, 0x83, decode_ra_rb_rci, NULL },
383  { CPU_ANY, "load", RZ_ANALYSIS_OP_TYPE_LOAD, 0x16, decode_load_store, NULL },
384  { CPU_ANY, "load", RZ_ANALYSIS_OP_TYPE_LOAD, 0x17, decode_load_store, NULL },
385  { CPU_ANY, "loadl", RZ_ANALYSIS_OP_TYPE_LOAD, 0x06, decode_load_store, NULL },
386  { CPU_ANY, "loadl", RZ_ANALYSIS_OP_TYPE_LOAD, 0x07, decode_load_store, NULL },
387  { CPU_ANY, "loadm", RZ_ANALYSIS_OP_TYPE_LOAD, 0x36, decode_load_store, NULL },
388  { CPU_ANY, "loadm", RZ_ANALYSIS_OP_TYPE_LOAD, 0x37, decode_load_store, NULL },
389  { CPU_ANY, "loadset", RZ_ANALYSIS_OP_TYPE_LOAD, 0x26, decode_load_store, NULL },
390  { CPU_ANY, "loadset", RZ_ANALYSIS_OP_TYPE_LOAD, 0x27, decode_load_store, NULL },
391  { CPU_ANY, "store", RZ_ANALYSIS_OP_TYPE_STORE, 0x1E, decode_load_store, NULL },
392  { CPU_ANY, "store", RZ_ANALYSIS_OP_TYPE_STORE, 0x1F, decode_load_store, NULL },
393  { CPU_ANY, "storel", RZ_ANALYSIS_OP_TYPE_STORE, 0x0E, decode_load_store, NULL },
394  { CPU_ANY, "storel", RZ_ANALYSIS_OP_TYPE_STORE, 0x0F, decode_load_store, NULL },
395  { CPU_ANY, "storem", RZ_ANALYSIS_OP_TYPE_STORE, 0x3E, decode_load_store, NULL },
396  { CPU_ANY, "storem", RZ_ANALYSIS_OP_TYPE_STORE, 0x3F, decode_load_store, NULL },
397  { CPU_ANY, "sub", RZ_ANALYSIS_OP_TYPE_SUB, 0x24, decode_ra_rb_rci, NULL },
398  { CPU_ANY, "sub", RZ_ANALYSIS_OP_TYPE_SUB, 0x25, decode_ra_rb_rci, NULL },
399  { CPU_ANY, "subc", RZ_ANALYSIS_OP_TYPE_SUB, 0x2C, decode_ra_rb_rci, NULL },
400  { CPU_ANY, "subc", RZ_ANALYSIS_OP_TYPE_SUB, 0x2D, decode_ra_rb_rci, NULL },
401  { CPU_ANY, "subcs", RZ_ANALYSIS_OP_TYPE_SUB, 0x28, decode_ra_rb_rci, NULL },
402  { CPU_ANY, "subcs", RZ_ANALYSIS_OP_TYPE_SUB, 0x29, decode_ra_rb_rci, NULL },
403  { CPU_ANY, "subcu", RZ_ANALYSIS_OP_TYPE_SUB, 0x2A, decode_ra_rb_rci, NULL },
404  { CPU_ANY, "subcu", RZ_ANALYSIS_OP_TYPE_SUB, 0x2B, decode_ra_rb_rci, NULL },
405  { CPU_ANY, "subr", RZ_ANALYSIS_OP_TYPE_SUB, 0x34, decode_ra_rb_rci, NULL },
406  { CPU_ANY, "subr", RZ_ANALYSIS_OP_TYPE_SUB, 0x35, decode_ra_rb_rci, NULL },
407  { CPU_ANY, "subrc", RZ_ANALYSIS_OP_TYPE_SUB, 0x3C, decode_ra_rb_rci, NULL },
408  { CPU_ANY, "subrc", RZ_ANALYSIS_OP_TYPE_SUB, 0x3D, decode_ra_rb_rci, NULL },
409  { CPU_ANY, "subrcs", RZ_ANALYSIS_OP_TYPE_SUB, 0x38, decode_ra_rb_rci, NULL },
410  { CPU_ANY, "subrcs", RZ_ANALYSIS_OP_TYPE_SUB, 0x39, decode_ra_rb_rci, NULL },
411  { CPU_ANY, "subrcu", RZ_ANALYSIS_OP_TYPE_SUB, 0x3A, decode_ra_rb_rci, NULL },
412  { CPU_ANY, "subrcu", RZ_ANALYSIS_OP_TYPE_SUB, 0x3B, decode_ra_rb_rci, NULL },
413  { CPU_ANY, "subrs", RZ_ANALYSIS_OP_TYPE_SUB, 0x30, decode_ra_rb_rci, NULL },
414  { CPU_ANY, "subrs", RZ_ANALYSIS_OP_TYPE_SUB, 0x31, decode_ra_rb_rci, NULL },
415  { CPU_ANY, "subru", RZ_ANALYSIS_OP_TYPE_SUB, 0x32, decode_ra_rb_rci, NULL },
416  { CPU_ANY, "subru", RZ_ANALYSIS_OP_TYPE_SUB, 0x33, decode_ra_rb_rci, NULL },
417  { CPU_ANY, "subs", RZ_ANALYSIS_OP_TYPE_SUB, 0x20, decode_ra_rb_rci, NULL },
418  { CPU_ANY, "subs", RZ_ANALYSIS_OP_TYPE_SUB, 0x21, decode_ra_rb_rci, NULL },
419  { CPU_ANY, "subu", RZ_ANALYSIS_OP_TYPE_SUB, 0x22, decode_ra_rb_rci, NULL },
420  { CPU_ANY, "subu", RZ_ANALYSIS_OP_TYPE_SUB, 0x23, decode_ra_rb_rci, NULL },
421  { CPU_ANY, "xnor", RZ_ANALYSIS_OP_TYPE_XOR, 0x96, decode_ra_rb_rci, NULL },
422  { CPU_ANY, "xnor", RZ_ANALYSIS_OP_TYPE_XOR, 0x97, decode_ra_rb_rci, NULL },
423  { CPU_ANY, "xor", RZ_ANALYSIS_OP_TYPE_XOR, 0x94, decode_ra_rb_rci, NULL },
424  { CPU_ANY, "xor", RZ_ANALYSIS_OP_TYPE_XOR, 0x95, decode_ra_rb_rci, NULL },
425 };
426 
427 static bool is_cpu(const char *cpu, const amd29k_instruction_t *in) {
428  return cpu[0] == in->cpu[0] &&
429  cpu[1] == in->cpu[1] &&
430  cpu[2] == in->cpu[2] &&
431  cpu[3] == in->cpu[3] &&
432  cpu[4] == in->cpu[4];
433 }
434 
435 bool amd29k_instr_decode(const ut8 *buffer, const ut32 buffer_size, amd29k_instr_t *instruction, const char *cpu) {
436  if (!buffer || buffer_size < 4 || !instruction || (cpu && strlen(cpu) < 5)) {
437  return false;
438  }
439  if (!cpu) {
440  cpu = CPU_29000;
441  }
442  if (buffer[0] == 0x70 && buffer[1] == 0x40 && buffer[2] == 0x01 && buffer[3] == 0x01) {
443  decode_none(instruction, buffer);
444  instruction->mnemonic = "nop";
445  instruction->op_type = RZ_ANALYSIS_OP_TYPE_NOP;
446  return true;
447  }
448  int i;
449  for (i = 0; i < N_AMD29K_INSTRUCTIONS; i++) {
450  const amd29k_instruction_t *in = &amd29k_instructions[i];
451  if (in->cpu[0] == '*' && in->mask == buffer[0]) {
452  in->decode(instruction, buffer);
453  instruction->mnemonic = in->mnemonic;
454  instruction->op_type = in->op_type;
455  return true;
456  } else if (in->cpu[0] != '*' && in->mask == buffer[0] && is_cpu(cpu, in)) {
457  in->decode(instruction, buffer);
458  instruction->mnemonic = in->mnemonic;
459  instruction->op_type = in->op_type;
460  return true;
461  }
462  }
463  return false;
464 }
465 
466 #define AMD29K_IS_6(a, b, c, d, e, f) (t0 == (a) && t1 == (b) && t2 == (c) && t3 == (d) && t4 == (e) && t5 == (f))
467 #define AMD29K_IS_1(a) AMD29K_IS_6(a, (AMD29K_TYPE_UNK), (AMD29K_TYPE_UNK), (AMD29K_TYPE_UNK), (AMD29K_TYPE_UNK), (AMD29K_TYPE_UNK))
468 #define AMD29K_IS_2(a, b) AMD29K_IS_6(a, b, (AMD29K_TYPE_UNK), (AMD29K_TYPE_UNK), (AMD29K_TYPE_UNK), (AMD29K_TYPE_UNK))
469 #define AMD29K_IS_3(a, b, c) AMD29K_IS_6(a, b, c, (AMD29K_TYPE_UNK), (AMD29K_TYPE_UNK), (AMD29K_TYPE_UNK))
470 #define AMD29K_IS_4(a, b, c, d) AMD29K_IS_6(a, b, c, d, (AMD29K_TYPE_UNK), (AMD29K_TYPE_UNK))
471 #define AMD29K_IS_5(a, b, c, d, e) AMD29K_IS_6(a, b, c, d, e, (AMD29K_TYPE_UNK))
472 
473 bool amd29k_instr_is_ret(amd29k_instr_t *instruction) {
474  if (instruction && !strcmp(instruction->mnemonic, "calli") && instruction->operands[0] == 128 && instruction->operands[1] == 128) {
475  return true;
476  }
477  return false;
478 }
479 
480 ut64 amd29k_instr_jump(ut64 address, amd29k_instr_t *instruction) {
481  if (!instruction) {
482  return UT64_MAX;
483  }
484  int t0 = AMD29K_GET_TYPE(instruction, 0);
485  int t1 = AMD29K_GET_TYPE(instruction, 1);
486  int t2 = AMD29K_GET_TYPE(instruction, 2);
487  int t3 = AMD29K_GET_TYPE(instruction, 3);
488  int t4 = AMD29K_GET_TYPE(instruction, 4);
489  int t5 = AMD29K_GET_TYPE(instruction, 5);
490 
491  int v0 = AMD29K_GET_VALUE(instruction, 0);
492  int v1 = AMD29K_GET_VALUE(instruction, 1);
493  if (AMD29K_IS_1(AMD29K_TYPE_JMP)) {
494  return address + ((int)v0);
495  } else if (AMD29K_IS_2(AMD29K_TYPE_REG, AMD29K_TYPE_JMP)) {
496  return address + ((int)v1);
497  }
498  return UT64_MAX;
499 }
500 
501 void amd29k_instr_print(char *string, int string_size, ut64 address, amd29k_instr_t *instruction) {
502  if (!string || string_size < 0 || !instruction) {
503  return;
504  }
505  int t0 = AMD29K_GET_TYPE(instruction, 0);
506  int t1 = AMD29K_GET_TYPE(instruction, 1);
507  int t2 = AMD29K_GET_TYPE(instruction, 2);
508  int t3 = AMD29K_GET_TYPE(instruction, 3);
509  int t4 = AMD29K_GET_TYPE(instruction, 4);
510  int t5 = AMD29K_GET_TYPE(instruction, 5);
511 
512  int v0 = AMD29K_GET_VALUE(instruction, 0);
513  int v1 = AMD29K_GET_VALUE(instruction, 1);
514  int v2 = AMD29K_GET_VALUE(instruction, 2);
515  int v3 = AMD29K_GET_VALUE(instruction, 3);
516  int v4 = AMD29K_GET_VALUE(instruction, 4);
517  int v5 = AMD29K_GET_VALUE(instruction, 5);
518 
519  if (AMD29K_IS_1(AMD29K_TYPE_REG)) {
520  const char *p0 = AMD29K_REGNAME(v0);
521  snprintf(string, string_size, "%s %s%d", instruction->mnemonic, p0, AMD29K_LR(v0));
522 
523  } else if (AMD29K_IS_1(AMD29K_TYPE_IMM)) {
524  if (v0 >= 0) {
525  snprintf(string, string_size, "%s 0x%x", instruction->mnemonic, v0);
526  } else {
527  v0 = 0 - v0;
528  snprintf(string, string_size, "%s -0x%x", instruction->mnemonic, v0);
529  }
530 
531  } else if (AMD29K_IS_1(AMD29K_TYPE_JMP)) {
532  ut64 ptr = address + ((int)v0);
533  snprintf(string, string_size, "%s 0x%" PFMT64x, instruction->mnemonic, ptr);
534 
535  } else if (AMD29K_IS_2(AMD29K_TYPE_REG, AMD29K_TYPE_REG)) {
536  const char *p0 = AMD29K_REGNAME(v0);
537  const char *p1 = AMD29K_REGNAME(v1);
538  snprintf(string, string_size, "%s %s%d %s%d", instruction->mnemonic, p0, AMD29K_LR(v0), p1, AMD29K_LR(v1));
539 
540  } else if (AMD29K_IS_2(AMD29K_TYPE_REG, AMD29K_TYPE_IMM)) {
541  const char *p0 = AMD29K_REGNAME(v0);
542  if (v1 >= 0) {
543  snprintf(string, string_size, "%s %s%d 0x%x", instruction->mnemonic, p0, AMD29K_LR(v0), v1);
544  } else {
545  v1 = 0 - v1;
546  snprintf(string, string_size, "%s %s%d -0x%x", instruction->mnemonic, p0, AMD29K_LR(v0), v1);
547  }
548 
549  } else if (AMD29K_IS_2(AMD29K_TYPE_REG, AMD29K_TYPE_JMP)) {
550  const char *p0 = AMD29K_REGNAME(v0);
551  ut64 ptr = address + ((int)v1);
552  snprintf(string, string_size, "%s %s%d 0x%" PFMT64x, instruction->mnemonic, p0, AMD29K_LR(v0), ptr);
553 
554  } else if (AMD29K_IS_3(AMD29K_TYPE_REG, AMD29K_TYPE_REG, AMD29K_TYPE_REG)) {
555  const char *p0 = AMD29K_REGNAME(v0);
556  const char *p1 = AMD29K_REGNAME(v1);
557  const char *p2 = AMD29K_REGNAME(v2);
558  snprintf(string, string_size, "%s %s%d %s%d %s%d", instruction->mnemonic, p0, AMD29K_LR(v0), p1, AMD29K_LR(v1), p2, AMD29K_LR(v2));
559 
560  } else if (AMD29K_IS_3(AMD29K_TYPE_REG, AMD29K_TYPE_REG, AMD29K_TYPE_IMM)) {
561  const char *p0 = AMD29K_REGNAME(v0);
562  const char *p1 = AMD29K_REGNAME(v1);
563  if (v2 >= 0) {
564  snprintf(string, string_size, "%s %s%d %s%d 0x%x", instruction->mnemonic, p0, AMD29K_LR(v0), p1, AMD29K_LR(v1), v2);
565  } else {
566  v2 = 0 - v2;
567  snprintf(string, string_size, "%s %s%d %s%d -0x%x", instruction->mnemonic, p0, AMD29K_LR(v0), p1, AMD29K_LR(v1), v2);
568  }
569 
570  } else if (AMD29K_IS_4(AMD29K_TYPE_IMM, AMD29K_TYPE_IMM, AMD29K_TYPE_REG, AMD29K_TYPE_REG)) {
571  const char *p2 = AMD29K_REGNAME(v2);
572  const char *p3 = AMD29K_REGNAME(v3);
573  snprintf(string, string_size, "%s %d %d %s%d %s%d", instruction->mnemonic, v0, v1, p2, AMD29K_LR(v2), p3, AMD29K_LR(v3));
574 
575  } else if (AMD29K_IS_6(AMD29K_TYPE_REG, AMD29K_TYPE_REG, AMD29K_TYPE_IMM, AMD29K_TYPE_IMM, AMD29K_TYPE_IMM, AMD29K_TYPE_IMM)) {
576  const char *p0 = AMD29K_REGNAME(v0);
577  const char *p1 = AMD29K_REGNAME(v1);
578  snprintf(string, string_size, "%s %s%d %s%d %d %d %d %d", instruction->mnemonic, p0, AMD29K_LR(v0), p1, AMD29K_LR(v1), v2, v3, v4, v5);
579 
580  } else {
581  snprintf(string, string_size, "%s", instruction->mnemonic);
582  }
583  return;
584 }
585 
586 #undef AMD29K_IS_6
587 #undef AMD29K_IS_1
588 #undef AMD29K_IS_2
589 #undef AMD29K_IS_3
590 #undef AMD29K_IS_4
591 #undef AMD29K_IS_5
AMD29K_SET_VALUE
#define AMD29K_SET_VALUE(x, i, v, t)
Definition: amd29k.c:15
AMD29K_IS_2
#define AMD29K_IS_2(a, b)
Definition: amd29k.c:468
AMD29K_HAS_BIT
#define AMD29K_HAS_BIT(x)
Definition: amd29k.c:19
AMD29K_IS_4
#define AMD29K_IS_4(a, b, c, d)
Definition: amd29k.c:470
decode_rc_ra
static void decode_rc_ra(amd29k_instr_t *instruction, const ut8 *buffer)
Definition: amd29k.c:135
decode_load_store
static void decode_load_store(amd29k_instr_t *instruction, const ut8 *buffer)
Definition: amd29k.c:89
AMD29K_LR
#define AMD29K_LR(x)
Definition: amd29k.c:25
decode_ra_i16_sh2
static void decode_ra_i16_sh2(amd29k_instr_t *instruction, const ut8 *buffer)
Definition: amd29k.c:59
AMD29K_GET_VALUE
#define AMD29K_GET_VALUE(x, i)
Definition: amd29k.c:14
decode_none
static void decode_none(amd29k_instr_t *instruction, const ut8 *buffer)
Definition: amd29k.c:207
decode_mfsr
static void decode_mfsr(amd29k_instr_t *instruction, const ut8 *buffer)
Definition: amd29k.c:189
decode_mtsr
static void decode_mtsr(amd29k_instr_t *instruction, const ut8 *buffer)
Definition: amd29k.c:198
decode_ra_rb
static void decode_ra_rb(amd29k_instr_t *instruction, const ut8 *buffer)
Definition: amd29k.c:153
decode_imm16_sh2
static void decode_imm16_sh2(amd29k_instr_t *instruction, const ut8 *buffer)
Definition: amd29k.c:76
decode_calli
static void decode_calli(amd29k_instr_t *instruction, const ut8 *buffer)
Definition: amd29k.c:98
AMD29K_SET_INVALID
#define AMD29K_SET_INVALID(x, i)
Definition: amd29k.c:18
decode_clz
static void decode_clz(amd29k_instr_t *instruction, const ut8 *buffer)
Definition: amd29k.c:116
amd29k_instructions
const amd29k_instruction_t amd29k_instructions[N_AMD29K_INSTRUCTIONS]
Definition: amd29k.c:217
AMD29K_IS_3
#define AMD29K_IS_3(a, b, c)
Definition: amd29k.c:469
AMD29K_IS_1
#define AMD29K_IS_1(a)
Definition: amd29k.c:467
decode_rc_ra_imm
static void decode_rc_ra_imm(amd29k_instr_t *instruction, const ut8 *buffer)
Definition: amd29k.c:107
decode_rc_imm
static void decode_rc_imm(amd29k_instr_t *instruction, const ut8 *buffer)
Definition: amd29k.c:171
CPU_ANY
#define CPU_ANY
Definition: amd29k.c:9
N_AMD29K_INSTRUCTIONS
#define N_AMD29K_INSTRUCTIONS
Definition: amd29k.c:11
decode_ra_rb_rc
static void decode_ra_rb_rc(amd29k_instr_t *instruction, const ut8 *buffer)
Definition: amd29k.c:40
amd29k_instr_decode
bool amd29k_instr_decode(const ut8 *buffer, const ut32 buffer_size, amd29k_instr_t *instruction, const char *cpu)
Definition: amd29k.c:435
decode_ra_imm
static void decode_ra_imm(amd29k_instr_t *instruction, const ut8 *buffer)
Definition: amd29k.c:180
amd29k_instr_is_ret
bool amd29k_instr_is_ret(amd29k_instr_t *instruction)
Definition: amd29k.c:473
amd29k_instr_jump
ut64 amd29k_instr_jump(ut64 address, amd29k_instr_t *instruction)
Definition: amd29k.c:480
is_cpu
static bool is_cpu(const char *cpu, const amd29k_instruction_t *in)
Definition: amd29k.c:427
AMD29K_GET_TYPE
#define AMD29K_GET_TYPE(x, i)
Definition: amd29k.c:13
decode_ra_imm16
static void decode_ra_imm16(amd29k_instr_t *instruction, const ut8 *buffer)
Definition: amd29k.c:49
decode_convert
static void decode_convert(amd29k_instr_t *instruction, const ut8 *buffer)
Definition: amd29k.c:125
decode_rb
static void decode_rb(amd29k_instr_t *instruction, const ut8 *buffer)
Definition: amd29k.c:162
decode_ra_rb_rci
static void decode_ra_rb_rci(amd29k_instr_t *instruction, const ut8 *buffer)
Definition: amd29k.c:27
decode_dmac_fmac
static void decode_dmac_fmac(amd29k_instr_t *instruction, const ut8 *buffer)
Definition: amd29k.c:144
AMD29K_REGNAME
#define AMD29K_REGNAME(x)
Definition: amd29k.c:24
amd29k_instr_print
void amd29k_instr_print(char *string, int string_size, ut64 address, amd29k_instr_t *instruction)
Definition: amd29k.c:501
AMD29K_IS_6
#define AMD29K_IS_6(a, b, c, d, e, f)
Definition: amd29k.c:466
CPU_29050
#define CPU_29050
Definition: amd29k.h:14
CPU_29000
#define CPU_29000
Definition: amd29k.h:13
amd29k_internal.h
AMD29K_TYPE_IMM
@ AMD29K_TYPE_IMM
Definition: amd29k_internal.h:21
AMD29K_TYPE_JMP
@ AMD29K_TYPE_JMP
Definition: amd29k_internal.h:22
AMD29K_TYPE_REG
@ AMD29K_TYPE_REG
Definition: amd29k_internal.h:20
cpu
static ut32 cpu[32]
Definition: analysis_or1k.c:21
i
lzma_index ** i
Definition: index.h:629
in
const lzma_allocator const uint8_t * in
Definition: block.h:527
NULL
#define NULL
Definition: cris-opc.c:27
ut32
uint32_t ut32
Definition: demangler_util.h:31
snprintf
snprintf
Definition: kernel.h:364
v0
@ v0
Definition: lanai.h:84
v1
@ v1
Definition: lanai.h:85
ut8
uint8_t ut8
Definition: lh5801.h:11
rz_analysis.h
RZ_ANALYSIS_OP_TYPE_CMP
@ RZ_ANALYSIS_OP_TYPE_CMP
Definition: rz_analysis.h:399
RZ_ANALYSIS_OP_TYPE_SUB
@ RZ_ANALYSIS_OP_TYPE_SUB
Definition: rz_analysis.h:402
RZ_ANALYSIS_OP_TYPE_ICALL
@ RZ_ANALYSIS_OP_TYPE_ICALL
Definition: rz_analysis.h:381
RZ_ANALYSIS_OP_TYPE_LOAD
@ RZ_ANALYSIS_OP_TYPE_LOAD
Definition: rz_analysis.h:416
RZ_ANALYSIS_OP_TYPE_MUL
@ RZ_ANALYSIS_OP_TYPE_MUL
Definition: rz_analysis.h:404
RZ_ANALYSIS_OP_TYPE_JMP
@ RZ_ANALYSIS_OP_TYPE_JMP
Definition: rz_analysis.h:368
RZ_ANALYSIS_OP_TYPE_AND
@ RZ_ANALYSIS_OP_TYPE_AND
Definition: rz_analysis.h:411
RZ_ANALYSIS_OP_TYPE_SAL
@ RZ_ANALYSIS_OP_TYPE_SAL
Definition: rz_analysis.h:408
RZ_ANALYSIS_OP_TYPE_NOR
@ RZ_ANALYSIS_OP_TYPE_NOR
Definition: rz_analysis.h:413
RZ_ANALYSIS_OP_TYPE_NULL
@ RZ_ANALYSIS_OP_TYPE_NULL
Definition: rz_analysis.h:367
RZ_ANALYSIS_OP_TYPE_CALL
@ RZ_ANALYSIS_OP_TYPE_CALL
Definition: rz_analysis.h:378
RZ_ANALYSIS_OP_TYPE_ADD
@ RZ_ANALYSIS_OP_TYPE_ADD
Definition: rz_analysis.h:401
RZ_ANALYSIS_OP_TYPE_OR
@ RZ_ANALYSIS_OP_TYPE_OR
Definition: rz_analysis.h:410
RZ_ANALYSIS_OP_TYPE_STORE
@ RZ_ANALYSIS_OP_TYPE_STORE
Definition: rz_analysis.h:415
RZ_ANALYSIS_OP_TYPE_RCJMP
@ RZ_ANALYSIS_OP_TYPE_RCJMP
Definition: rz_analysis.h:374
RZ_ANALYSIS_OP_TYPE_SHR
@ RZ_ANALYSIS_OP_TYPE_SHR
Definition: rz_analysis.h:406
RZ_ANALYSIS_OP_TYPE_RJMP
@ RZ_ANALYSIS_OP_TYPE_RJMP
Definition: rz_analysis.h:370
RZ_ANALYSIS_OP_TYPE_CJMP
@ RZ_ANALYSIS_OP_TYPE_CJMP
Definition: rz_analysis.h:373
RZ_ANALYSIS_OP_TYPE_DIV
@ RZ_ANALYSIS_OP_TYPE_DIV
Definition: rz_analysis.h:405
RZ_ANALYSIS_OP_TYPE_MOV
@ RZ_ANALYSIS_OP_TYPE_MOV
Definition: rz_analysis.h:390
RZ_ANALYSIS_OP_TYPE_SHL
@ RZ_ANALYSIS_OP_TYPE_SHL
Definition: rz_analysis.h:407
RZ_ANALYSIS_OP_TYPE_RET
@ RZ_ANALYSIS_OP_TYPE_RET
Definition: rz_analysis.h:385
RZ_ANALYSIS_OP_TYPE_NOP
@ RZ_ANALYSIS_OP_TYPE_NOP
Definition: rz_analysis.h:389
RZ_ANALYSIS_OP_TYPE_XOR
@ RZ_ANALYSIS_OP_TYPE_XOR
Definition: rz_analysis.h:412
PFMT64x
#define PFMT64x
Definition: rz_types.h:393
UT64_MAX
#define UT64_MAX
Definition: rz_types_base.h:86
int
static int
Definition: sfsocketcall.h:114
amd29k_instr_s
Definition: amd29k.h:16
amd29k_instruction_s
Definition: amd29k_internal.h:9
buffer
Definition: buffer.h:15
ut64
ut64(WINAPI *w32_GetEnabledXStateFeatures)()
buffer_size
#define buffer_size(buffer)
Definition: zip_source_buffer.c:70