Rizin
unix-like reverse engineering framework and cli tools
TMS320C64xInstPrinter.c
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1 /* Capstone Disassembly Engine */
2 /* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
3 
4 #ifdef CAPSTONE_HAS_TMS320C64X
5 
6 #ifdef _MSC_VER
7 // Disable security warnings for strcpy
8 #ifndef _CRT_SECURE_NO_WARNINGS
9 #define _CRT_SECURE_NO_WARNINGS
10 #endif
11 
12 // Banned API Usage : strcpy is a Banned API as listed in dontuse.h for
13 // security purposes.
14 #pragma warning(disable:28719)
15 #endif
16 
17 #include <ctype.h>
18 #include <string.h>
19 
20 #include "TMS320C64xInstPrinter.h"
21 #include "../../MCInst.h"
22 #include "../../utils.h"
23 #include "../../SStream.h"
24 #include "../../MCRegisterInfo.h"
25 #include "../../MathExtras.h"
26 #include "TMS320C64xMapping.h"
27 
28 #include "capstone/tms320c64x.h"
29 
30 static char *getRegisterName(unsigned RegNo);
31 static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
32 static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O);
33 static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O);
34 static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O);
35 
36 void TMS320C64x_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
37 {
38  SStream ss;
39  char *p, *p2, tmp[8];
40  unsigned int unit = 0;
41  int i;
42  cs_tms320c64x *tms320c64x;
43 
44  if (mci->csh->detail) {
45  tms320c64x = &mci->flat_insn->detail->tms320c64x;
46 
47  for (i = 0; i < insn->detail->groups_count; i++) {
48  switch(insn->detail->groups[i]) {
49  case TMS320C64X_GRP_FUNIT_D:
50  unit = TMS320C64X_FUNIT_D;
51  break;
52  case TMS320C64X_GRP_FUNIT_L:
53  unit = TMS320C64X_FUNIT_L;
54  break;
55  case TMS320C64X_GRP_FUNIT_M:
56  unit = TMS320C64X_FUNIT_M;
57  break;
58  case TMS320C64X_GRP_FUNIT_S:
59  unit = TMS320C64X_FUNIT_S;
60  break;
61  case TMS320C64X_GRP_FUNIT_NO:
62  unit = TMS320C64X_FUNIT_NO;
63  break;
64  }
65  if (unit != 0)
66  break;
67  }
68  tms320c64x->funit.unit = unit;
69 
70  SStream_Init(&ss);
71  if (tms320c64x->condition.reg != TMS320C64X_REG_INVALID)
72  SStream_concat(&ss, "[%c%s]|", (tms320c64x->condition.zero == 1) ? '!' : '|', cs_reg_name(ud, tms320c64x->condition.reg));
73 
74  p = strchr(insn_asm, '\t');
75  if (p != NULL)
76  *p++ = '\0';
77 
78  SStream_concat0(&ss, insn_asm);
79  if ((p != NULL) && (((p2 = strchr(p, '[')) != NULL) || ((p2 = strchr(p, '(')) != NULL))) {
80  while ((p2 > p) && ((*p2 != 'a') && (*p2 != 'b')))
81  p2--;
82  if (p2 == p) {
83  strcpy(insn_asm, "Invalid!");
84  return;
85  }
86  if (*p2 == 'a')
87  strcpy(tmp, "1T");
88  else
89  strcpy(tmp, "2T");
90  } else {
91  tmp[0] = '\0';
92  }
93  switch(tms320c64x->funit.unit) {
94  case TMS320C64X_FUNIT_D:
95  SStream_concat(&ss, ".D%s%u", tmp, tms320c64x->funit.side);
96  break;
97  case TMS320C64X_FUNIT_L:
98  SStream_concat(&ss, ".L%s%u", tmp, tms320c64x->funit.side);
99  break;
100  case TMS320C64X_FUNIT_M:
101  SStream_concat(&ss, ".M%s%u", tmp, tms320c64x->funit.side);
102  break;
103  case TMS320C64X_FUNIT_S:
104  SStream_concat(&ss, ".S%s%u", tmp, tms320c64x->funit.side);
105  break;
106  }
107  if (tms320c64x->funit.crosspath > 0)
108  SStream_concat0(&ss, "X");
109 
110  if (p != NULL)
111  SStream_concat(&ss, "\t%s", p);
112 
113  if (tms320c64x->parallel != 0)
114  SStream_concat(&ss, "\t||");
115 
116  /* insn_asm is a buffer from an SStream, so there should be enough space */
117  strcpy(insn_asm, ss.buffer);
118  }
119 }
120 
121 #define PRINT_ALIAS_INSTR
122 #include "TMS320C64xGenAsmWriter.inc"
123 
124 #define GET_INSTRINFO_ENUM
125 #include "TMS320C64xGenInstrInfo.inc"
126 
127 static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
128 {
129  MCOperand *Op = MCInst_getOperand(MI, OpNo);
130  unsigned reg;
131 
132  if (MCOperand_isReg(Op)) {
133  reg = MCOperand_getReg(Op);
134  if ((MCInst_getOpcode(MI) == TMS320C64x_MVC_s1_rr) && (OpNo == 1)) {
135  switch(reg) {
136  case TMS320C64X_REG_EFR:
137  SStream_concat0(O, "EFR");
138  break;
139  case TMS320C64X_REG_IFR:
140  SStream_concat0(O, "IFR");
141  break;
142  default:
143  SStream_concat0(O, getRegisterName(reg));
144  break;
145  }
146  } else {
147  SStream_concat0(O, getRegisterName(reg));
148  }
149 
150  if (MI->csh->detail) {
151  MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].type = TMS320C64X_OP_REG;
152  MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].reg = reg;
153  MI->flat_insn->detail->tms320c64x.op_count++;
154  }
155  } else if (MCOperand_isImm(Op)) {
156  int64_t Imm = MCOperand_getImm(Op);
157 
158  if (Imm >= 0) {
159  if (Imm > HEX_THRESHOLD)
160  SStream_concat(O, "0x%"PRIx64, Imm);
161  else
162  SStream_concat(O, "%"PRIu64, Imm);
163  } else {
164  if (Imm < -HEX_THRESHOLD)
165  SStream_concat(O, "-0x%"PRIx64, -Imm);
166  else
167  SStream_concat(O, "-%"PRIu64, -Imm);
168  }
169 
170  if (MI->csh->detail) {
171  MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].type = TMS320C64X_OP_IMM;
172  MI->flat_insn->detail->tms320c64x.operands[MI->flat_insn->detail->tms320c64x.op_count].imm = Imm;
173  MI->flat_insn->detail->tms320c64x.op_count++;
174  }
175  }
176 }
177 
178 static void printMemOperand(MCInst *MI, unsigned OpNo, SStream *O)
179 {
180  MCOperand *Op = MCInst_getOperand(MI, OpNo);
181  int64_t Val = MCOperand_getImm(Op);
182  unsigned scaled, base, offset, mode, unit;
183  cs_tms320c64x *tms320c64x;
184  char st, nd;
185 
186  scaled = (Val >> 19) & 1;
187  base = (Val >> 12) & 0x7f;
188  offset = (Val >> 5) & 0x7f;
189  mode = (Val >> 1) & 0xf;
190  unit = Val & 1;
191 
192  if (scaled) {
193  st = '[';
194  nd = ']';
195  } else {
196  st = '(';
197  nd = ')';
198  }
199 
200  switch(mode) {
201  case 0:
202  SStream_concat(O, "*-%s%c%u%c", getRegisterName(base), st, offset, nd);
203  break;
204  case 1:
205  SStream_concat(O, "*+%s%c%u%c", getRegisterName(base), st, offset, nd);
206  break;
207  case 4:
208  SStream_concat(O, "*-%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
209  break;
210  case 5:
211  SStream_concat(O, "*+%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
212  break;
213  case 8:
214  SStream_concat(O, "*--%s%c%u%c", getRegisterName(base), st, offset, nd);
215  break;
216  case 9:
217  SStream_concat(O, "*++%s%c%u%c", getRegisterName(base), st, offset, nd);
218  break;
219  case 10:
220  SStream_concat(O, "*%s--%c%u%c", getRegisterName(base), st, offset, nd);
221  break;
222  case 11:
223  SStream_concat(O, "*%s++%c%u%c", getRegisterName(base), st, offset, nd);
224  break;
225  case 12:
226  SStream_concat(O, "*--%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
227  break;
228  case 13:
229  SStream_concat(O, "*++%s%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
230  break;
231  case 14:
232  SStream_concat(O, "*%s--%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
233  break;
234  case 15:
235  SStream_concat(O, "*%s++%c%s%c", getRegisterName(base), st, getRegisterName(offset), nd);
236  break;
237  }
238 
239  if (MI->csh->detail) {
240  tms320c64x = &MI->flat_insn->detail->tms320c64x;
241 
242  tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_MEM;
243  tms320c64x->operands[tms320c64x->op_count].mem.base = base;
244  tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
245  tms320c64x->operands[tms320c64x->op_count].mem.unit = unit + 1;
246  tms320c64x->operands[tms320c64x->op_count].mem.scaled = scaled;
247  switch(mode) {
248  case 0:
249  tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
250  tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
251  tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
252  break;
253  case 1:
254  tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
255  tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
256  tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
257  break;
258  case 4:
259  tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
260  tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
261  tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
262  break;
263  case 5:
264  tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
265  tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
266  tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
267  break;
268  case 8:
269  tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
270  tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
271  tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
272  break;
273  case 9:
274  tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
275  tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
276  tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
277  break;
278  case 10:
279  tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
280  tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
281  tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
282  break;
283  case 11:
284  tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
285  tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
286  tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
287  break;
288  case 12:
289  tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
290  tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
291  tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
292  break;
293  case 13:
294  tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
295  tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
296  tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_PRE;
297  break;
298  case 14:
299  tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
300  tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_BW;
301  tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
302  break;
303  case 15:
304  tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_REGISTER;
305  tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
306  tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_POST;
307  break;
308  }
309  tms320c64x->op_count++;
310  }
311 }
312 
313 static void printMemOperand2(MCInst *MI, unsigned OpNo, SStream *O)
314 {
315  MCOperand *Op = MCInst_getOperand(MI, OpNo);
316  int64_t Val = MCOperand_getImm(Op);
317  uint16_t offset;
318  unsigned basereg;
319  cs_tms320c64x *tms320c64x;
320 
321  basereg = Val & 0x7f;
322  offset = (Val >> 7) & 0x7fff;
323  SStream_concat(O, "*+%s[0x%x]", getRegisterName(basereg), offset);
324 
325  if (MI->csh->detail) {
326  tms320c64x = &MI->flat_insn->detail->tms320c64x;
327 
328  tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_MEM;
329  tms320c64x->operands[tms320c64x->op_count].mem.base = basereg;
330  tms320c64x->operands[tms320c64x->op_count].mem.unit = 2;
331  tms320c64x->operands[tms320c64x->op_count].mem.disp = offset;
332  tms320c64x->operands[tms320c64x->op_count].mem.disptype = TMS320C64X_MEM_DISP_CONSTANT;
333  tms320c64x->operands[tms320c64x->op_count].mem.direction = TMS320C64X_MEM_DIR_FW;
334  tms320c64x->operands[tms320c64x->op_count].mem.modify = TMS320C64X_MEM_MOD_NO;
335  tms320c64x->op_count++;
336  }
337 }
338 
339 static void printRegPair(MCInst *MI, unsigned OpNo, SStream *O)
340 {
341  MCOperand *Op = MCInst_getOperand(MI, OpNo);
342  unsigned reg = MCOperand_getReg(Op);
343  cs_tms320c64x *tms320c64x;
344 
345  SStream_concat(O, "%s:%s", getRegisterName(reg + 1), getRegisterName(reg));
346 
347  if (MI->csh->detail) {
348  tms320c64x = &MI->flat_insn->detail->tms320c64x;
349 
350  tms320c64x->operands[tms320c64x->op_count].type = TMS320C64X_OP_REGPAIR;
351  tms320c64x->operands[tms320c64x->op_count].reg = reg;
352  tms320c64x->op_count++;
353  }
354 }
355 
356 static bool printAliasInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
357 {
358  unsigned opcode = MCInst_getOpcode(MI);
359  MCOperand *op;
360 
361  switch(opcode) {
362  /* ADD.Dx -i, x, y -> SUB.Dx x, i, y */
363  case TMS320C64x_ADD_d2_rir:
364  /* ADD.L -i, x, y -> SUB.L x, i, y */
365  case TMS320C64x_ADD_l1_irr:
366  case TMS320C64x_ADD_l1_ipp:
367  /* ADD.S -i, x, y -> SUB.S x, i, y */
368  case TMS320C64x_ADD_s1_irr:
369  if ((MCInst_getNumOperands(MI) == 3) &&
370  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
371  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
372  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
373  (MCOperand_getImm(MCInst_getOperand(MI, 2)) < 0)) {
374 
375  MCInst_setOpcodePub(MI, TMS320C64X_INS_SUB);
376  op = MCInst_getOperand(MI, 2);
377  MCOperand_setImm(op, -MCOperand_getImm(op));
378 
379  SStream_concat0(O, "SUB\t");
380  printOperand(MI, 1, O);
381  SStream_concat0(O, ", ");
382  printOperand(MI, 2, O);
383  SStream_concat0(O, ", ");
384  printOperand(MI, 0, O);
385 
386  return true;
387  }
388  break;
389  }
390  switch(opcode) {
391  /* ADD.D 0, x, y -> MV.D x, y */
392  case TMS320C64x_ADD_d1_rir:
393  /* OR.D x, 0, y -> MV.D x, y */
394  case TMS320C64x_OR_d2_rir:
395  /* ADD.L 0, x, y -> MV.L x, y */
396  case TMS320C64x_ADD_l1_irr:
397  case TMS320C64x_ADD_l1_ipp:
398  /* OR.L 0, x, y -> MV.L x, y */
399  case TMS320C64x_OR_l1_irr:
400  /* ADD.S 0, x, y -> MV.S x, y */
401  case TMS320C64x_ADD_s1_irr:
402  /* OR.S 0, x, y -> MV.S x, y */
403  case TMS320C64x_OR_s1_irr:
404  if ((MCInst_getNumOperands(MI) == 3) &&
405  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
406  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
407  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
408  (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
409 
410  MCInst_setOpcodePub(MI, TMS320C64X_INS_MV);
411  MI->size--;
412 
413  SStream_concat0(O, "MV\t");
414  printOperand(MI, 1, O);
415  SStream_concat0(O, ", ");
416  printOperand(MI, 0, O);
417 
418  return true;
419  }
420  break;
421  }
422  switch(opcode) {
423  /* XOR.D -1, x, y -> NOT.D x, y */
424  case TMS320C64x_XOR_d2_rir:
425  /* XOR.L -1, x, y -> NOT.L x, y */
426  case TMS320C64x_XOR_l1_irr:
427  /* XOR.S -1, x, y -> NOT.S x, y */
428  case TMS320C64x_XOR_s1_irr:
429  if ((MCInst_getNumOperands(MI) == 3) &&
430  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
431  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
432  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
433  (MCOperand_getImm(MCInst_getOperand(MI, 2)) == -1)) {
434 
435  MCInst_setOpcodePub(MI, TMS320C64X_INS_NOT);
436  MI->size--;
437 
438  SStream_concat0(O, "NOT\t");
439  printOperand(MI, 1, O);
440  SStream_concat0(O, ", ");
441  printOperand(MI, 0, O);
442 
443  return true;
444  }
445  break;
446  }
447  switch(opcode) {
448  /* MVK.D 0, x -> ZERO.D x */
449  case TMS320C64x_MVK_d1_rr:
450  /* MVK.L 0, x -> ZERO.L x */
451  case TMS320C64x_MVK_l2_ir:
452  if ((MCInst_getNumOperands(MI) == 2) &&
453  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
454  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
455  (MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0)) {
456 
457  MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
458  MI->size--;
459 
460  SStream_concat0(O, "ZERO\t");
461  printOperand(MI, 0, O);
462 
463  return true;
464  }
465  break;
466  }
467  switch(opcode) {
468  /* SUB.L x, x, y -> ZERO.L y */
469  case TMS320C64x_SUB_l1_rrp_x1:
470  /* SUB.S x, x, y -> ZERO.S y */
471  case TMS320C64x_SUB_s1_rrr:
472  if ((MCInst_getNumOperands(MI) == 3) &&
473  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
474  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
475  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
476  (MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
477 
478  MCInst_setOpcodePub(MI, TMS320C64X_INS_ZERO);
479  MI->size -= 2;
480 
481  SStream_concat0(O, "ZERO\t");
482  printOperand(MI, 0, O);
483 
484  return true;
485  }
486  break;
487  }
488  switch(opcode) {
489  /* SUB.L 0, x, y -> NEG.L x, y */
490  case TMS320C64x_SUB_l1_irr:
491  case TMS320C64x_SUB_l1_ipp:
492  /* SUB.S 0, x, y -> NEG.S x, y */
493  case TMS320C64x_SUB_s1_irr:
494  if ((MCInst_getNumOperands(MI) == 3) &&
495  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
496  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
497  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
498  (MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0)) {
499 
500  MCInst_setOpcodePub(MI, TMS320C64X_INS_NEG);
501  MI->size--;
502 
503  SStream_concat0(O, "NEG\t");
504  printOperand(MI, 1, O);
505  SStream_concat0(O, ", ");
506  printOperand(MI, 0, O);
507 
508  return true;
509  }
510  break;
511  }
512  switch(opcode) {
513  /* PACKLH2.L x, x, y -> SWAP2.L x, y */
514  case TMS320C64x_PACKLH2_l1_rrr_x2:
515  /* PACKLH2.S x, x, y -> SWAP2.S x, y */
516  case TMS320C64x_PACKLH2_s1_rrr:
517  if ((MCInst_getNumOperands(MI) == 3) &&
518  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
519  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
520  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
521  (MCOperand_getReg(MCInst_getOperand(MI, 1)) == MCOperand_getReg(MCInst_getOperand(MI, 2)))) {
522 
523  MCInst_setOpcodePub(MI, TMS320C64X_INS_SWAP2);
524  MI->size--;
525 
526  SStream_concat0(O, "SWAP2\t");
527  printOperand(MI, 1, O);
528  SStream_concat0(O, ", ");
529  printOperand(MI, 0, O);
530 
531  return true;
532  }
533  break;
534  }
535  switch(opcode) {
536  /* NOP 16 -> IDLE */
537  /* NOP 1 -> NOP */
538  case TMS320C64x_NOP_n:
539  if ((MCInst_getNumOperands(MI) == 1) &&
540  MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
541  (MCOperand_getReg(MCInst_getOperand(MI, 0)) == 16)) {
542 
543  MCInst_setOpcodePub(MI, TMS320C64X_INS_IDLE);
544  MI->size--;
545 
546  SStream_concat0(O, "IDLE");
547 
548  return true;
549  }
550  if ((MCInst_getNumOperands(MI) == 1) &&
551  MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
552  (MCOperand_getReg(MCInst_getOperand(MI, 0)) == 1)) {
553 
554  MI->size--;
555 
556  SStream_concat0(O, "NOP");
557 
558  return true;
559  }
560  break;
561  }
562 
563  return false;
564 }
565 
566 void TMS320C64x_printInst(MCInst *MI, SStream *O, void *Info)
567 {
568  if (!printAliasInstruction(MI, O, Info))
569  printInstruction(MI, O, Info);
570 }
571 
572 #endif
op
ut8 op
Definition: 6502dis.c:13
MCInst_getOpcode
unsigned MCInst_getOpcode(const MCInst *inst)
Definition: MCInst.c:68
MCInst_getNumOperands
unsigned MCInst_getNumOperands(const MCInst *inst)
Definition: MCInst.c:83
MCInst_getOperand
MCOperand * MCInst_getOperand(MCInst *inst, unsigned i)
Definition: MCInst.c:78
MCOperand_setImm
void MCOperand_setImm(MCOperand *op, int64_t Val)
Definition: MCInst.c:133
MCOperand_isReg
bool MCOperand_isReg(const MCOperand *op)
Definition: MCInst.c:101
MCInst_setOpcodePub
void MCInst_setOpcodePub(MCInst *inst, unsigned Op)
Definition: MCInst.c:63
MCOperand_getImm
int64_t MCOperand_getImm(MCOperand *op)
Definition: MCInst.c:128
MCOperand_getReg
unsigned MCOperand_getReg(const MCOperand *op)
getReg - Returns the register number.
Definition: MCInst.c:117
MCOperand_isImm
bool MCOperand_isImm(const MCOperand *op)
Definition: MCInst.c:106
SStream_Init
void SStream_Init(SStream *ss)
Definition: SStream.c:25
SStream_concat
void SStream_concat(SStream *ss, const char *fmt,...)
Definition: SStream.c:45
SStream_concat0
void SStream_concat0(SStream *ss, const char *s)
Definition: SStream.c:31
TMS320C64x_post_printer
void TMS320C64x_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
TMS320C64x_printInst
void TMS320C64x_printInst(MCInst *MI, SStream *O, void *Info)
i
lzma_index ** i
Definition: index.h:629
csh
size_t csh
Definition: capstone.h:71
NULL
#define NULL
Definition: cris-opc.c:27
cs_reg_name
CAPSTONE_EXPORT const char *CAPSTONE_API cs_reg_name(csh ud, unsigned int reg)
Definition: cs.c:1154
offset
voidpf uLong offset
Definition: ioapi.h:144
mode
const char int mode
Definition: ioapi.h:137
reg
#define reg(n)
p
void * p
Definition: libc.cpp:67
PRIu64
#define PRIu64
Definition: macros.h:18
autogen_x86imm.tmp
tmp
Definition: autogen_x86imm.py:12
O
#define O
Definition: rcond.c:14
uint16_t
unsigned short uint16_t
Definition: sftypes.h:30
int64_t
long int64_t
Definition: sftypes.h:32
MCInst
Definition: MCInst.h:88
MCInst::flat_insn
cs_insn * flat_insn
Definition: MCInst.h:95
MCInst::size
uint8_t size
Definition: MCInst.h:90
MCInst::csh
cs_struct * csh
Definition: MCInst.h:97
SStream
Definition: SStream.h:9
SStream::buffer
char buffer[512]
Definition: SStream.h:10
cs_struct::detail
cs_opt_value detail
Definition: cs_priv.h:68
cs_tms320c64x_op::mem
tms320c64x_op_mem mem
base/disp value for MEM operand
Definition: tms320c64x.h:60
cs_tms320c64x_op::type
tms320c64x_op_type type
operand type
Definition: tms320c64x.h:56
cs_tms320c64x_op::reg
unsigned int reg
register value for REG operand or first register for REGPAIR operand
Definition: tms320c64x.h:58
cs_tms320c64x
Definition: tms320c64x.h:64
cs_tms320c64x::operands
cs_tms320c64x_op operands[8]
operands for this instruction.
Definition: tms320c64x.h:66
cs_tms320c64x::funit
struct cs_tms320c64x::@364 funit
cs_tms320c64x::unit
unsigned int unit
Definition: tms320c64x.h:72
cs_tms320c64x::parallel
unsigned int parallel
Definition: tms320c64x.h:76
cs_tms320c64x::crosspath
unsigned int crosspath
Definition: tms320c64x.h:74
cs_tms320c64x::reg
unsigned int reg
Definition: tms320c64x.h:68
cs_tms320c64x::op_count
uint8_t op_count
Definition: tms320c64x.h:65
cs_tms320c64x::condition
struct cs_tms320c64x::@363 condition
cs_tms320c64x::zero
unsigned int zero
Definition: tms320c64x.h:69
cs_tms320c64x::side
unsigned int side
Definition: tms320c64x.h:73
tms320c64x_op_mem::disp
unsigned int disp
displacement/offset value
Definition: tms320c64x.h:47
tms320c64x_op_mem::base
unsigned int base
base register
Definition: tms320c64x.h:46
tms320c64x_op_mem::scaled
unsigned int scaled
offset scaled
Definition: tms320c64x.h:49
tms320c64x_op_mem::modify
unsigned int modify
modification
Definition: tms320c64x.h:52
tms320c64x_op_mem::direction
unsigned int direction
direction
Definition: tms320c64x.h:51
tms320c64x_op_mem::disptype
unsigned int disptype
displacement type
Definition: tms320c64x.h:50
tms320c64x_op_mem::unit
unsigned int unit
unit of base and offset register
Definition: tms320c64x.h:48
HEX_THRESHOLD
#define HEX_THRESHOLD
Definition: utils.h:16
PRIx64
#define PRIx64
Definition: sysdefs.h:94
TMS320C64X_GRP_FUNIT_NO
@ TMS320C64X_GRP_FUNIT_NO
Definition: tms320c64x.h:340
TMS320C64X_GRP_FUNIT_L
@ TMS320C64X_GRP_FUNIT_L
Definition: tms320c64x.h:337
TMS320C64X_GRP_FUNIT_S
@ TMS320C64X_GRP_FUNIT_S
Definition: tms320c64x.h:339
TMS320C64X_GRP_FUNIT_D
@ TMS320C64X_GRP_FUNIT_D
Definition: tms320c64x.h:336
TMS320C64X_GRP_FUNIT_M
@ TMS320C64X_GRP_FUNIT_M
Definition: tms320c64x.h:338
TMS320C64X_FUNIT_NO
@ TMS320C64X_FUNIT_NO
Definition: tms320c64x.h:351
TMS320C64X_FUNIT_L
@ TMS320C64X_FUNIT_L
Definition: tms320c64x.h:348
TMS320C64X_FUNIT_D
@ TMS320C64X_FUNIT_D
Definition: tms320c64x.h:347
TMS320C64X_FUNIT_S
@ TMS320C64X_FUNIT_S
Definition: tms320c64x.h:350
TMS320C64X_FUNIT_M
@ TMS320C64X_FUNIT_M
Definition: tms320c64x.h:349
TMS320C64X_MEM_DISP_CONSTANT
@ TMS320C64X_MEM_DISP_CONSTANT
Definition: tms320c64x.h:28
TMS320C64X_MEM_DISP_REGISTER
@ TMS320C64X_MEM_DISP_REGISTER
Definition: tms320c64x.h:29
TMS320C64X_INS_IDLE
@ TMS320C64X_INS_IDLE
Definition: tms320c64x.h:321
TMS320C64X_INS_NEG
@ TMS320C64X_INS_NEG
Definition: tms320c64x.h:323
TMS320C64X_INS_SUB
@ TMS320C64X_INS_SUB
Definition: tms320c64x.h:305
TMS320C64X_INS_SWAP2
@ TMS320C64X_INS_SWAP2
Definition: tms320c64x.h:325
TMS320C64X_INS_MV
@ TMS320C64X_INS_MV
Definition: tms320c64x.h:322
TMS320C64X_INS_ZERO
@ TMS320C64X_INS_ZERO
Definition: tms320c64x.h:326
TMS320C64X_INS_NOT
@ TMS320C64X_INS_NOT
Definition: tms320c64x.h:324
TMS320C64X_REG_IFR
@ TMS320C64X_REG_IFR
Definition: tms320c64x.h:176
TMS320C64X_REG_INVALID
@ TMS320C64X_REG_INVALID
Definition: tms320c64x.h:80
TMS320C64X_REG_EFR
@ TMS320C64X_REG_EFR
Definition: tms320c64x.h:175
TMS320C64X_MEM_DIR_FW
@ TMS320C64X_MEM_DIR_FW
Definition: tms320c64x.h:34
TMS320C64X_MEM_DIR_BW
@ TMS320C64X_MEM_DIR_BW
Definition: tms320c64x.h:35
TMS320C64X_MEM_MOD_POST
@ TMS320C64X_MEM_MOD_POST
Definition: tms320c64x.h:42
TMS320C64X_MEM_MOD_NO
@ TMS320C64X_MEM_MOD_NO
Definition: tms320c64x.h:40
TMS320C64X_MEM_MOD_PRE
@ TMS320C64X_MEM_MOD_PRE
Definition: tms320c64x.h:41
TMS320C64X_OP_REG
@ TMS320C64X_OP_REG
= CS_OP_REG (Register operand).
Definition: tms320c64x.h:20
TMS320C64X_OP_REGPAIR
@ TMS320C64X_OP_REGPAIR
Register pair for double word ops.
Definition: tms320c64x.h:23
TMS320C64X_OP_IMM
@ TMS320C64X_OP_IMM
= CS_OP_IMM (Immediate operand).
Definition: tms320c64x.h:21
TMS320C64X_OP_MEM
@ TMS320C64X_OP_MEM
= CS_OP_MEM (Memory operand).
Definition: tms320c64x.h:22
op
Definition: dis.c:32