Rizin
unix-like reverse engineering framework and cli tools
SystemZGenRegisterInfo.inc
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1 /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2 |* *|
3 |*Target Register Enum Values *|
4 |* *|
5 |* Automatically generated file, do not edit! *|
6 |* *|
7 \*===----------------------------------------------------------------------===*/
8 
9 /* Capstone Disassembly Engine */
10 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
11 
12 
13 #ifdef GET_REGINFO_ENUM
14 #undef GET_REGINFO_ENUM
15 
16 enum {
17  SystemZ_NoRegister,
18  SystemZ_CC = 1,
19  SystemZ_F0D = 2,
20  SystemZ_F1D = 3,
21  SystemZ_F2D = 4,
22  SystemZ_F3D = 5,
23  SystemZ_F4D = 6,
24  SystemZ_F5D = 7,
25  SystemZ_F6D = 8,
26  SystemZ_F7D = 9,
27  SystemZ_F8D = 10,
28  SystemZ_F9D = 11,
29  SystemZ_F10D = 12,
30  SystemZ_F11D = 13,
31  SystemZ_F12D = 14,
32  SystemZ_F13D = 15,
33  SystemZ_F14D = 16,
34  SystemZ_F15D = 17,
35  SystemZ_F0Q = 18,
36  SystemZ_F1Q = 19,
37  SystemZ_F4Q = 20,
38  SystemZ_F5Q = 21,
39  SystemZ_F8Q = 22,
40  SystemZ_F9Q = 23,
41  SystemZ_F12Q = 24,
42  SystemZ_F13Q = 25,
43  SystemZ_F0S = 26,
44  SystemZ_F1S = 27,
45  SystemZ_F2S = 28,
46  SystemZ_F3S = 29,
47  SystemZ_F4S = 30,
48  SystemZ_F5S = 31,
49  SystemZ_F6S = 32,
50  SystemZ_F7S = 33,
51  SystemZ_F8S = 34,
52  SystemZ_F9S = 35,
53  SystemZ_F10S = 36,
54  SystemZ_F11S = 37,
55  SystemZ_F12S = 38,
56  SystemZ_F13S = 39,
57  SystemZ_F14S = 40,
58  SystemZ_F15S = 41,
59  SystemZ_R0D = 42,
60  SystemZ_R1D = 43,
61  SystemZ_R2D = 44,
62  SystemZ_R3D = 45,
63  SystemZ_R4D = 46,
64  SystemZ_R5D = 47,
65  SystemZ_R6D = 48,
66  SystemZ_R7D = 49,
67  SystemZ_R8D = 50,
68  SystemZ_R9D = 51,
69  SystemZ_R10D = 52,
70  SystemZ_R11D = 53,
71  SystemZ_R12D = 54,
72  SystemZ_R13D = 55,
73  SystemZ_R14D = 56,
74  SystemZ_R15D = 57,
75  SystemZ_R0H = 58,
76  SystemZ_R1H = 59,
77  SystemZ_R2H = 60,
78  SystemZ_R3H = 61,
79  SystemZ_R4H = 62,
80  SystemZ_R5H = 63,
81  SystemZ_R6H = 64,
82  SystemZ_R7H = 65,
83  SystemZ_R8H = 66,
84  SystemZ_R9H = 67,
85  SystemZ_R10H = 68,
86  SystemZ_R11H = 69,
87  SystemZ_R12H = 70,
88  SystemZ_R13H = 71,
89  SystemZ_R14H = 72,
90  SystemZ_R15H = 73,
91  SystemZ_R0L = 74,
92  SystemZ_R1L = 75,
93  SystemZ_R2L = 76,
94  SystemZ_R3L = 77,
95  SystemZ_R4L = 78,
96  SystemZ_R5L = 79,
97  SystemZ_R6L = 80,
98  SystemZ_R7L = 81,
99  SystemZ_R8L = 82,
100  SystemZ_R9L = 83,
101  SystemZ_R10L = 84,
102  SystemZ_R11L = 85,
103  SystemZ_R12L = 86,
104  SystemZ_R13L = 87,
105  SystemZ_R14L = 88,
106  SystemZ_R15L = 89,
107  SystemZ_R0Q = 90,
108  SystemZ_R2Q = 91,
109  SystemZ_R4Q = 92,
110  SystemZ_R6Q = 93,
111  SystemZ_R8Q = 94,
112  SystemZ_R10Q = 95,
113  SystemZ_R12Q = 96,
114  SystemZ_R14Q = 97,
115  SystemZ_NUM_TARGET_REGS // 98
116 };
117 
118 // Register classes
119 enum {
120  SystemZ_GRX32BitRegClassID = 0,
121  SystemZ_FP32BitRegClassID = 1,
122  SystemZ_GR32BitRegClassID = 2,
123  SystemZ_GRH32BitRegClassID = 3,
124  SystemZ_ADDR32BitRegClassID = 4,
125  SystemZ_CCRegsRegClassID = 5,
126  SystemZ_FP64BitRegClassID = 6,
127  SystemZ_GR64BitRegClassID = 7,
128  SystemZ_ADDR64BitRegClassID = 8,
129  SystemZ_FP128BitRegClassID = 9,
130  SystemZ_GR128BitRegClassID = 10,
131  SystemZ_ADDR128BitRegClassID = 11
132 };
133 
134 #endif // GET_REGINFO_ENUM
135 
136 /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
137 |* *|
138 |*MC Register Information *|
139 |* *|
140 |* Automatically generated file, do not edit! *|
141 |* *|
142 \*===----------------------------------------------------------------------===*/
143 
144 
145 #ifdef GET_REGINFO_MC_DESC
146 #undef GET_REGINFO_MC_DESC
147 
148 static const MCPhysReg SystemZRegDiffLists[] = {
149  /* 0 */ 65193, 1, 1, 1, 0,
150  /* 5 */ 65469, 1, 0,
151  /* 8 */ 65519, 2, 0,
152  /* 11 */ 65521, 2, 0,
153  /* 14 */ 65523, 2, 0,
154  /* 17 */ 65525, 2, 0,
155  /* 20 */ 65512, 8, 0,
156  /* 23 */ 65512, 10, 0,
157  /* 26 */ 65512, 12, 0,
158  /* 29 */ 65512, 14, 0,
159  /* 32 */ 65512, 16, 0,
160  /* 35 */ 65522, 24, 65510, 24, 0,
161  /* 40 */ 65524, 24, 65510, 24, 0,
162  /* 45 */ 65526, 24, 65510, 24, 0,
163  /* 50 */ 65528, 24, 65510, 24, 0,
164  /* 55 */ 65504, 40, 0,
165  /* 58 */ 65520, 40, 0,
166  /* 61 */ 65504, 41, 0,
167  /* 64 */ 65520, 41, 0,
168  /* 67 */ 65504, 42, 0,
169  /* 70 */ 65520, 42, 0,
170  /* 73 */ 65504, 43, 0,
171  /* 76 */ 65520, 43, 0,
172  /* 79 */ 65504, 44, 0,
173  /* 82 */ 65520, 44, 0,
174  /* 85 */ 65504, 45, 0,
175  /* 88 */ 65520, 45, 0,
176  /* 91 */ 65504, 46, 0,
177  /* 94 */ 65520, 46, 0,
178  /* 97 */ 65504, 47, 0,
179  /* 100 */ 65520, 47, 0,
180  /* 103 */ 65504, 48, 0,
181  /* 106 */ 65520, 48, 0,
182  /* 109 */ 65405, 0,
183  /* 111 */ 65438, 0,
184  /* 113 */ 65511, 0,
185  /* 115 */ 65489, 32, 65520, 65519, 32, 65520, 0,
186  /* 122 */ 65490, 32, 65520, 65519, 32, 65520, 0,
187  /* 129 */ 65491, 32, 65520, 65519, 32, 65520, 0,
188  /* 136 */ 65492, 32, 65520, 65519, 32, 65520, 0,
189  /* 143 */ 65493, 32, 65520, 65519, 32, 65520, 0,
190  /* 150 */ 65494, 32, 65520, 65519, 32, 65520, 0,
191  /* 157 */ 65495, 32, 65520, 65519, 32, 65520, 0,
192  /* 164 */ 65496, 32, 65520, 65519, 32, 65520, 0,
193  /* 171 */ 65535, 0,
194 };
195 
196 static const uint16_t SystemZSubRegIdxLists[] = {
197  /* 0 */ 5, 1, 0,
198  /* 3 */ 6, 1, 2, 3, 0,
199  /* 8 */ 6, 5, 1, 2, 4, 3, 0,
200 };
201 
202 static MCRegisterDesc SystemZRegDesc[] = { // Descriptors
203  { 2, 0, 0, 0, 0, 0 },
204  { 0, 4, 4, 2, 2737, 0 },
205  { 13, 38, 33, 1, 2737, 3 },
206  { 31, 38, 33, 1, 2737, 3 },
207  { 49, 38, 30, 1, 2737, 3 },
208  { 67, 38, 30, 1, 2737, 3 },
209  { 85, 38, 30, 1, 2737, 3 },
210  { 103, 38, 30, 1, 2737, 3 },
211  { 111, 38, 27, 1, 2737, 3 },
212  { 119, 38, 27, 1, 2737, 3 },
213  { 127, 38, 27, 1, 2737, 3 },
214  { 135, 38, 27, 1, 2737, 3 },
215  { 3, 38, 24, 1, 2737, 3 },
216  { 21, 38, 24, 1, 2737, 3 },
217  { 39, 38, 24, 1, 2737, 3 },
218  { 57, 38, 24, 1, 2737, 3 },
219  { 75, 38, 21, 1, 2737, 3 },
220  { 93, 38, 21, 1, 2737, 3 },
221  { 288, 35, 4, 3, 129, 2 },
222  { 296, 35, 4, 3, 129, 2 },
223  { 324, 40, 4, 3, 177, 2 },
224  { 332, 40, 4, 3, 177, 2 },
225  { 340, 45, 4, 3, 225, 2 },
226  { 348, 45, 4, 3, 225, 2 },
227  { 300, 50, 4, 3, 273, 2 },
228  { 314, 50, 4, 3, 273, 2 },
229  { 357, 4, 32, 2, 1809, 0 },
230  { 366, 4, 32, 2, 1809, 0 },
231  { 375, 4, 29, 2, 1809, 0 },
232  { 384, 4, 29, 2, 1809, 0 },
233  { 393, 4, 29, 2, 1809, 0 },
234  { 402, 4, 29, 2, 1809, 0 },
235  { 406, 4, 26, 2, 1809, 0 },
236  { 410, 4, 26, 2, 1809, 0 },
237  { 414, 4, 26, 2, 1809, 0 },
238  { 418, 4, 26, 2, 1809, 0 },
239  { 352, 4, 23, 2, 1809, 0 },
240  { 361, 4, 23, 2, 1809, 0 },
241  { 370, 4, 23, 2, 1809, 0 },
242  { 379, 4, 23, 2, 1809, 0 },
243  { 388, 4, 20, 2, 1809, 0 },
244  { 397, 4, 20, 2, 1809, 0 },
245  { 17, 119, 104, 0, 82, 7 },
246  { 35, 119, 98, 0, 82, 7 },
247  { 53, 119, 98, 0, 82, 7 },
248  { 71, 119, 92, 0, 82, 7 },
249  { 89, 119, 92, 0, 82, 7 },
250  { 107, 119, 86, 0, 82, 7 },
251  { 115, 119, 86, 0, 82, 7 },
252  { 123, 119, 80, 0, 82, 7 },
253  { 131, 119, 80, 0, 82, 7 },
254  { 139, 119, 74, 0, 82, 7 },
255  { 8, 119, 74, 0, 82, 7 },
256  { 26, 119, 68, 0, 82, 7 },
257  { 44, 119, 68, 0, 82, 7 },
258  { 62, 119, 62, 0, 82, 7 },
259  { 80, 119, 62, 0, 82, 7 },
260  { 98, 119, 56, 0, 82, 7 },
261  { 148, 4, 106, 2, 1778, 0 },
262  { 157, 4, 100, 2, 1778, 0 },
263  { 166, 4, 100, 2, 1778, 0 },
264  { 175, 4, 94, 2, 1778, 0 },
265  { 184, 4, 94, 2, 1778, 0 },
266  { 193, 4, 88, 2, 1778, 0 },
267  { 197, 4, 88, 2, 1778, 0 },
268  { 201, 4, 82, 2, 1778, 0 },
269  { 205, 4, 82, 2, 1778, 0 },
270  { 209, 4, 76, 2, 1778, 0 },
271  { 143, 4, 76, 2, 1778, 0 },
272  { 152, 4, 70, 2, 1778, 0 },
273  { 161, 4, 70, 2, 1778, 0 },
274  { 170, 4, 64, 2, 1778, 0 },
275  { 179, 4, 64, 2, 1778, 0 },
276  { 188, 4, 58, 2, 1778, 0 },
277  { 218, 4, 103, 2, 1746, 0 },
278  { 227, 4, 97, 2, 1746, 0 },
279  { 236, 4, 97, 2, 1746, 0 },
280  { 245, 4, 91, 2, 1746, 0 },
281  { 254, 4, 91, 2, 1746, 0 },
282  { 263, 4, 85, 2, 1746, 0 },
283  { 267, 4, 85, 2, 1746, 0 },
284  { 271, 4, 79, 2, 1746, 0 },
285  { 275, 4, 79, 2, 1746, 0 },
286  { 279, 4, 73, 2, 1746, 0 },
287  { 213, 4, 73, 2, 1746, 0 },
288  { 222, 4, 67, 2, 1746, 0 },
289  { 231, 4, 67, 2, 1746, 0 },
290  { 240, 4, 61, 2, 1746, 0 },
291  { 249, 4, 61, 2, 1746, 0 },
292  { 258, 4, 55, 2, 1746, 0 },
293  { 292, 115, 4, 8, 4, 5 },
294  { 310, 122, 4, 8, 4, 5 },
295  { 328, 129, 4, 8, 4, 5 },
296  { 336, 136, 4, 8, 4, 5 },
297  { 344, 143, 4, 8, 4, 5 },
298  { 283, 150, 4, 8, 4, 5 },
299  { 305, 157, 4, 8, 4, 5 },
300  { 319, 164, 4, 8, 4, 5 },
301 };
302 
303  // GRX32Bit Register Class...
304  static const MCPhysReg GRX32Bit[] = {
305  SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H, SystemZ_R4H, SystemZ_R5H, SystemZ_R15L, SystemZ_R15H, SystemZ_R14L, SystemZ_R14H, SystemZ_R13L, SystemZ_R13H, SystemZ_R12L, SystemZ_R12H, SystemZ_R11L, SystemZ_R11H, SystemZ_R10L, SystemZ_R10H, SystemZ_R9L, SystemZ_R9H, SystemZ_R8L, SystemZ_R8H, SystemZ_R7L, SystemZ_R7H, SystemZ_R6L, SystemZ_R6H,
306  };
307 
308  // GRX32Bit Bit set.
309  static const uint8_t GRX32BitBits[] = {
310  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
311  };
312 
313  // FP32Bit Register Class...
314  static const MCPhysReg FP32Bit[] = {
315  SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S, SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S,
316  };
317 
318  // FP32Bit Bit set.
319  static const uint8_t FP32BitBits[] = {
320  0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
321  };
322 
323  // GR32Bit Register Class...
324  static const MCPhysReg GR32Bit[] = {
325  SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R15L, SystemZ_R14L, SystemZ_R13L, SystemZ_R12L, SystemZ_R11L, SystemZ_R10L, SystemZ_R9L, SystemZ_R8L, SystemZ_R7L, SystemZ_R6L,
326  };
327 
328  // GR32Bit Bit set.
329  static const uint8_t GR32BitBits[] = {
330  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
331  };
332 
333  // GRH32Bit Register Class...
334  static const MCPhysReg GRH32Bit[] = {
335  SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H, SystemZ_R4H, SystemZ_R5H, SystemZ_R15H, SystemZ_R14H, SystemZ_R13H, SystemZ_R12H, SystemZ_R11H, SystemZ_R10H, SystemZ_R9H, SystemZ_R8H, SystemZ_R7H, SystemZ_R6H,
336  };
337 
338  // GRH32Bit Bit set.
339  static const uint8_t GRH32BitBits[] = {
340  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
341  };
342 
343  // ADDR32Bit Register Class...
344  static const MCPhysReg ADDR32Bit[] = {
345  SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R15L, SystemZ_R14L, SystemZ_R13L, SystemZ_R12L, SystemZ_R11L, SystemZ_R10L, SystemZ_R9L, SystemZ_R8L, SystemZ_R7L, SystemZ_R6L,
346  };
347 
348  // ADDR32Bit Bit set.
349  static const uint8_t ADDR32BitBits[] = {
350  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03,
351  };
352 
353  // CCRegs Register Class...
354  static const MCPhysReg CCRegs[] = {
355  SystemZ_CC,
356  };
357 
358  // CCRegs Bit set.
359  static const uint8_t CCRegsBits[] = {
360  0x02,
361  };
362 
363  // FP64Bit Register Class...
364  static const MCPhysReg FP64Bit[] = {
365  SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D,
366  };
367 
368  // FP64Bit Bit set.
369  static const uint8_t FP64BitBits[] = {
370  0xfc, 0xff, 0x03,
371  };
372 
373  // GR64Bit Register Class...
374  static const MCPhysReg GR64Bit[] = {
375  SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, SystemZ_R5D, SystemZ_R15D, SystemZ_R14D, SystemZ_R13D, SystemZ_R12D, SystemZ_R11D, SystemZ_R10D, SystemZ_R9D, SystemZ_R8D, SystemZ_R7D, SystemZ_R6D,
376  };
377 
378  // GR64Bit Bit set.
379  static const uint8_t GR64BitBits[] = {
380  0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
381  };
382 
383  // ADDR64Bit Register Class...
384  static const MCPhysReg ADDR64Bit[] = {
385  SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, SystemZ_R5D, SystemZ_R15D, SystemZ_R14D, SystemZ_R13D, SystemZ_R12D, SystemZ_R11D, SystemZ_R10D, SystemZ_R9D, SystemZ_R8D, SystemZ_R7D, SystemZ_R6D,
386  };
387 
388  // ADDR64Bit Bit set.
389  static const uint8_t ADDR64BitBits[] = {
390  0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03,
391  };
392 
393  // FP128Bit Register Class...
394  static const MCPhysReg FP128Bit[] = {
395  SystemZ_F0Q, SystemZ_F1Q, SystemZ_F4Q, SystemZ_F5Q, SystemZ_F8Q, SystemZ_F9Q, SystemZ_F12Q, SystemZ_F13Q,
396  };
397 
398  // FP128Bit Bit set.
399  static const uint8_t FP128BitBits[] = {
400  0x00, 0x00, 0xfc, 0x03,
401  };
402 
403  // GR128Bit Register Class...
404  static const MCPhysReg GR128Bit[] = {
405  SystemZ_R0Q, SystemZ_R2Q, SystemZ_R4Q, SystemZ_R12Q, SystemZ_R10Q, SystemZ_R8Q, SystemZ_R6Q, SystemZ_R14Q,
406  };
407 
408  // GR128Bit Bit set.
409  static const uint8_t GR128BitBits[] = {
410  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
411  };
412 
413  // ADDR128Bit Register Class...
414  static const MCPhysReg ADDR128Bit[] = {
415  SystemZ_R2Q, SystemZ_R4Q, SystemZ_R12Q, SystemZ_R10Q, SystemZ_R8Q, SystemZ_R6Q, SystemZ_R14Q,
416  };
417 
418  // ADDR128Bit Bit set.
419  static const uint8_t ADDR128BitBits[] = {
420  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
421  };
422 
423 static MCRegisterClass SystemZMCRegisterClasses[] = {
424  { GRX32Bit, GRX32BitBits, 42, 32, sizeof(GRX32BitBits), SystemZ_GRX32BitRegClassID, 4, 4, 1, 1 },
425  { FP32Bit, FP32BitBits, 16, 16, sizeof(FP32BitBits), SystemZ_FP32BitRegClassID, 4, 4, 1, 1 },
426  { GR32Bit, GR32BitBits, 34, 16, sizeof(GR32BitBits), SystemZ_GR32BitRegClassID, 4, 4, 1, 1 },
427  { GRH32Bit, GRH32BitBits, 7, 16, sizeof(GRH32BitBits), SystemZ_GRH32BitRegClassID, 4, 4, 1, 1 },
428  { ADDR32Bit, ADDR32BitBits, 24, 15, sizeof(ADDR32BitBits), SystemZ_ADDR32BitRegClassID, 4, 4, 1, 1 },
429  { CCRegs, CCRegsBits, 0, 1, sizeof(CCRegsBits), SystemZ_CCRegsRegClassID, 4, 4, 1, 1 },
430  { FP64Bit, FP64BitBits, 51, 16, sizeof(FP64BitBits), SystemZ_FP64BitRegClassID, 8, 8, 1, 1 },
431  { GR64Bit, GR64BitBits, 69, 16, sizeof(GR64BitBits), SystemZ_GR64BitRegClassID, 8, 8, 1, 1 },
432  { ADDR64Bit, ADDR64BitBits, 59, 15, sizeof(ADDR64BitBits), SystemZ_ADDR64BitRegClassID, 8, 8, 1, 1 },
433  { FP128Bit, FP128BitBits, 77, 8, sizeof(FP128BitBits), SystemZ_FP128BitRegClassID, 16, 16, 1, 1 },
434  { GR128Bit, GR128BitBits, 97, 8, sizeof(GR128BitBits), SystemZ_GR128BitRegClassID, 16, 16, 1, 1 },
435  { ADDR128Bit, ADDR128BitBits, 86, 7, sizeof(ADDR128BitBits), SystemZ_ADDR128BitRegClassID, 16, 16, 1, 1 },
436 };
437 
438 #endif // GET_REGINFO_MC_DESC
MCPhysReg
uint16_t MCPhysReg
Definition: MCRegisterInfo.h:26
uint16_t
unsigned short uint16_t
Definition: sftypes.h:30
uint8_t
unsigned char uint8_t
Definition: sftypes.h:31