20 print(
"0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
26 if len(insn.operands) > 0:
27 print(
"\top_count: %u" %
len(insn.operands))
29 for i
in insn.operands:
31 if i.type == ARM64_OP_REG:
32 print(
"\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
33 if i.type == ARM64_OP_IMM:
34 print(
"\t\toperands[%u].type: IMM = 0x%s" % (c,
to_x(i.imm)))
35 if i.type == ARM64_OP_CIMM:
36 print(
"\t\toperands[%u].type: C-IMM = %u" % (c, i.imm))
37 if i.type == ARM64_OP_FP:
38 print(
"\t\toperands[%u].type: FP = %f" % (c, i.fp))
39 if i.type == ARM64_OP_MEM:
40 print(
"\t\toperands[%u].type: MEM" % c)
42 print(
"\t\t\toperands[%u].mem.base: REG = %s" \
43 % (c, insn.reg_name(i.mem.base)))
45 print(
"\t\t\toperands[%u].mem.index: REG = %s" \
46 % (c, insn.reg_name(i.mem.index)))
48 print(
"\t\t\toperands[%u].mem.disp: 0x%s" \
49 % (c,
to_x(i.mem.disp)))
50 if i.type == ARM64_OP_REG_MRS:
51 print(
"\t\toperands[%u].type: REG_MRS = 0x%x" % (c, i.reg))
52 if i.type == ARM64_OP_REG_MSR:
53 print(
"\t\toperands[%u].type: REG_MSR = 0x%x" % (c, i.reg))
54 if i.type == ARM64_OP_PSTATE:
55 print(
"\t\toperands[%u].type: PSTATE = 0x%x" % (c, i.pstate))
56 if i.type == ARM64_OP_SYS:
57 print(
"\t\toperands[%u].type: SYS = 0x%x" % (c, i.sys))
58 if i.type == ARM64_OP_PREFETCH:
59 print(
"\t\toperands[%u].type: PREFETCH = 0x%x" % (c, i.prefetch))
60 if i.type == ARM64_OP_BARRIER:
61 print(
"\t\toperands[%u].type: BARRIER = 0x%x" % (c, i.barrier))
63 if i.shift.type != ARM64_SFT_INVALID
and i.shift.value:
64 print(
"\t\t\tShift: type = %u, value = %u" % (i.shift.type, i.shift.value))
66 if i.ext != ARM64_EXT_INVALID:
67 print(
"\t\t\tExt: %u" % i.ext)
69 if i.vas != ARM64_VAS_INVALID:
70 print(
"\t\t\tVector Arrangement Specifier: 0x%x" % i.vas)
72 if i.vess != ARM64_VESS_INVALID:
73 print(
"\t\t\tVector Element Size Specifier: %u" % i.vess)
75 if i.vector_index != -1:
76 print(
"\t\t\tVector Index: %u" % i.vector_index)
78 if i.access == CS_AC_READ:
79 print(
"\t\toperands[%u].access: READ\n" % (c))
80 elif i.access == CS_AC_WRITE:
81 print(
"\t\toperands[%u].access: WRITE\n" % (c))
82 elif i.access == CS_AC_READ | CS_AC_WRITE:
83 print(
"\t\toperands[%u].access: READ | WRITE\n" % (c))
87 print(
"\tWrite-back: True")
88 if not insn.cc
in [ARM64_CC_AL, ARM64_CC_INVALID]:
89 print(
"\tCode-condition: %u" % insn.cc)
91 print(
"\tUpdate-flags: True")
93 (regs_read, regs_write) = insn.regs_access()
95 if len(regs_read) > 0:
96 print(
"\tRegisters read:", end=
"")
98 print(
" %s" %(insn.reg_name(r)), end=
"")
101 if len(regs_write) > 0:
102 print(
"\tRegisters modified:", end=
"")
104 print(
" %s" %(insn.reg_name(r)), end=
"")
def print_insn_detail(insn)