Rizin
unix-like reverse engineering framework and cli tools
mcore.c
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1 // SPDX-FileCopyrightText: 2018-2020 deroad <wargio@libero.it>
2 // SPDX-FileCopyrightText: 2018-2020 pancake <pancake@nopcode.org>
3 // SPDX-FileCopyrightText: 2020 Anton Kochkov <anton.kochkov@gmail.com>
4 // SPDX-License-Identifier: LGPL-3.0-only
5 
6 #include "mcore.h"
7 
8 #include <rz_analysis.h>
9 #include <string.h>
10 #include <stdlib.h>
11 #include <stdio.h>
12 
13 // Instructions are aligned by 2 bytes (16 bits)
14 #define MCORE_INSTR_ALIGN (2)
15 
16 // MCORE control registers
17 static const char *mcore_ctrl_registers[] = {
18  "psr", // Processor Status Register
19  "vbr", // Vector Base Register
20  "epsr", // Shadow Exception PSR
21  "fpsr", // Shadow Fast Interrupt PSR
22  "epc", // Shadow Exception Program Counter
23  "fpc", // Shadow Fast Interrupt PC
24  "ss0", // Supervisor Scratch Register 0-4
25  "ss1",
26  "ss2",
27  "ss3",
28  "ss4",
29  "gcr", // Global Control Register
30  "gsr", // Global Status Register
31  "cpidr",
32  "dcsr",
33  "cwr",
34  "cr16",
35  "cfr",
36  "ccr",
37  "capr",
38  "pacr",
39  "prsr",
40  "cr22",
41  "cr23",
42  "cr24",
43  "cr25",
44  "cr26",
45  "cr27",
46  "cr28",
47  "cr29",
48  "cr30",
49  "cr31",
50  "unknown"
51 };
52 
53 /*
54  * MCORE Register usage
55  * r0 | Stack Pointer | Preserved
56  * r1 | Scratch | Destroyed
57  * r2 | Argument Word 1/Return Buffer Address | Destroyed/Preserved
58  * r3 | Argument Word 2 | Destroyed
59  * r4 | Argument Word 3 | Destroyed
60  * r5 | Argument Word 4 | Destroyed
61  * r6 | Argument Word 5 | Destroyed
62  * r7 | Argument Word 6 | Destroyed
63  * r8 | Local | Preserved
64  * r9 | Local | Preserved
65  * r10 | Local | Preserved
66  * r11 | Local | Preserved
67  * r12 | Local | Preserved
68  * r13 | Local | Preserved
69  * r14 | Local | Preserved
70  * r15 | Link/Scratch | (Return Address)
71  */
72 
73 // MCORE instruction set
74 // http://www.ece.ualberta.ca/~cmpe490/documents/motorola/MCORERM.pdf
75 
76 #define INVALID_FIELD (0)
77 
78 typedef struct mcore_mask {
79  ut16 mask;
80  ut16 shift;
81  ut16 type;
82 } mcore_mask_t;
83 
84 typedef struct mcore_ops {
85  const char *name;
86  ut16 cpu;
87  ut16 mask;
88  ut64 type;
89  ut16 n_args;
90  mcore_mask_t args[ARGS_SIZE];
91 } mcore_ops_t;
92 
93 ut16 load_shift[4] = { 2, 0, 1, 0 };
94 
95 #define MCORE_INSTRS 265
96 mcore_ops_t mcore_instructions[MCORE_INSTRS] = {
97  { "bkpt", MCORE_CPU_DFLT, 0x0, RZ_ANALYSIS_OP_TYPE_ILL, 0, { { 0 }, { 0 }, { 0 }, { 0 }, { 0 } } },
98  { "sync", MCORE_CPU_DFLT, 0x1, RZ_ANALYSIS_OP_TYPE_SYNC, 0, { { 0 }, { 0 }, { 0 }, { 0 }, { 0 } } },
99  { "rte", MCORE_CPU_DFLT, 0x2, RZ_ANALYSIS_OP_TYPE_RET, 0, { { 0 }, { 0 }, { 0 }, { 0 }, { 0 } } },
100  { "rfi", MCORE_CPU_DFLT, 0x3, RZ_ANALYSIS_OP_TYPE_RET, 0, { { 0 }, { 0 }, { 0 }, { 0 }, { 0 } } },
101  { "stop", MCORE_CPU_DFLT, 0x4, RZ_ANALYSIS_OP_TYPE_NULL, 0, { { 0 }, { 0 }, { 0 }, { 0 }, { 0 } } },
102  { "wait", MCORE_CPU_DFLT, 0x5, RZ_ANALYSIS_OP_TYPE_NULL, 0, { { 0 }, { 0 }, { 0 }, { 0 }, { 0 } } },
103  { "doze", MCORE_CPU_DFLT, 0x6, RZ_ANALYSIS_OP_TYPE_NULL, 0, { { 0 }, { 0 }, { 0 }, { 0 }, { 0 } } },
104  { "idly4", MCORE_CPU_DFLT, 0x7, RZ_ANALYSIS_OP_TYPE_NULL, 0, { { 0 }, { 0 }, { 0 }, { 0 }, { 0 } } },
105  // 0b00000000000010ii, trap #ii
106  { "trap", MCORE_CPU_DFLT, 0xb, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0x3, 0, TYPE_IMM }, { 0 }, { 0 }, { 0 }, { 0 } } },
107  // 0b0000000000001100, mvtc 510E
108  { "mvtc", MCORE_CPU_510E, 0xc, RZ_ANALYSIS_OP_TYPE_NULL, 0, { { 0 }, { 0 }, { 0 }, { 0 }, { 0 } } },
109  // 0b0000000000001101, cprc cp
110  { "cprc", MCORE_CPU_DFLT, 0xd, RZ_ANALYSIS_OP_TYPE_NULL, 0, { { 0 }, { 0 }, { 0 }, { 0 }, { 0 } } },
111  // 0b000000000000111x, --
112  // 0b000000000001iiii, cpseti cp
113  { "cpseti", MCORE_CPU_DFLT, 0x1f, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_IMM }, { 0 }, { 0 }, { 0 }, { 0 } } },
114  // 0b000000000010rrrr, mvc
115  { "mvc", MCORE_CPU_DFLT, 0x2f, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
116  // 0b000000000011rrrr, mvcv
117  { "mvcv", MCORE_CPU_DFLT, 0x3f, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
118  // 0b000000000100rrrr, ldq
119  { "ldq", MCORE_CPU_DFLT, 0x4f, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
120  // 0b000000000101rrrr, stq
121  { "stq", MCORE_CPU_DFLT, 0x5f, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
122  // 0b000000000110rrrr, ldm
123  { "ldm", MCORE_CPU_DFLT, 0x6f, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
124  // 0b000000000111rrrr, stm
125  { "stm", MCORE_CPU_DFLT, 0x7f, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
126  // 0b000000001000rrrr, dect
127  { "dect", MCORE_CPU_DFLT, 0x8f, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
128  // 0b000000001001rrrr, decf
129  { "decf", MCORE_CPU_DFLT, 0x9f, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
130  // 0b000000001010rrrr, inct
131  { "inct", MCORE_CPU_DFLT, 0xaf, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
132  // 0b000000001011rrrr, incf
133  { "incf", MCORE_CPU_DFLT, 0xbf, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
134  // 0b000000001100rrrr, jmp
135  { "jmp", MCORE_CPU_DFLT, 0xcf, RZ_ANALYSIS_OP_TYPE_CALL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
136  // 0b000000001101rrrr, jsr
137  { "jsr", MCORE_CPU_DFLT, 0xdf, RZ_ANALYSIS_OP_TYPE_RET, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
138  // 0b000000001110rrrr, ff1
139  { "ff1", MCORE_CPU_DFLT, 0xef, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
140  // 0b000000001111rrrr, brev
141  { "brev", MCORE_CPU_DFLT, 0xff, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
142  // 0b000000010000rrrr, xtrb3
143  { "xtrb3", MCORE_CPU_DFLT, 0x10f, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
144  // 0b000000010001rrrr, xtrb2
145  { "xtrb2", MCORE_CPU_DFLT, 0x11f, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
146  // 0b000000010010rrrr, xtrb1
147  { "xtrb1", MCORE_CPU_DFLT, 0x12f, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
148  // 0b000000010011rrrr, xtrb0
149  { "xtrb0", MCORE_CPU_DFLT, 0x13f, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
150  // 0b000000010100rrrr, zextb
151  { "zextb", MCORE_CPU_DFLT, 0x14f, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 } } },
152  // 0b000000010101rrrr, sextb
153  { "sextb", MCORE_CPU_DFLT, 0x15f, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 } } },
154  // 0b000000010110rrrr, zexth
155  { "zexth", MCORE_CPU_DFLT, 0x16f, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 } } },
156  // 0b000000010111rrrr, sexth
157  { "sexth", MCORE_CPU_DFLT, 0x17f, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 } } },
158  // 0b000000011000rrrr, declt
159  { "declt", MCORE_CPU_DFLT, 0x18f, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
160  // 0b000000011001rrrr, tstnbz
161  { "declt", MCORE_CPU_DFLT, 0x19f, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
162  // 0b000000011010rrrr, decgt
163  { "decgt", MCORE_CPU_DFLT, 0x1af, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
164  // 0b000000011011rrrr, decne
165  { "decne", MCORE_CPU_DFLT, 0x1bf, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
166  // 0b000000011100rrrr, clrt
167  { "clrt", MCORE_CPU_DFLT, 0x1cf, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
168  // 0b000000011101rrrr, clrf
169  { "clrf", MCORE_CPU_DFLT, 0x1df, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
170  // 0b000000011110rrrr, abs
171  { "abs", MCORE_CPU_DFLT, 0x1ef, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
172  // 0b000000011111rrrr, not
173  { "not", MCORE_CPU_DFLT, 0x1ff, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
174  // 0b00000010ssssrrrr, movt
175  { "movt", MCORE_CPU_DFLT, 0x2ff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0xf0, 4, TYPE_REG }, { 0 }, { 0 }, { 0 } } },
176  // 0b00000011ssssrrrr, mult
177  { "mult", MCORE_CPU_DFLT, 0x3ff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0xf0, 4, TYPE_REG }, { 0 }, { 0 }, { 0 } } },
178  // 0b00000101ssssrrrr, subu
179  { "subu", MCORE_CPU_DFLT, 0x5ff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0xf0, 4, TYPE_REG }, { 0 }, { 0 }, { 0 } } },
180  // 0b00000110ssssrrrr, addc
181  { "addc", MCORE_CPU_DFLT, 0x6ff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0xf0, 4, TYPE_REG }, { 0 }, { 0 }, { 0 } } },
182  // 0b00000111ssssrrrr, subc
183  { "subc", MCORE_CPU_DFLT, 0x7ff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0xf0, 4, TYPE_REG }, { 0 }, { 0 }, { 0 } } },
184  // 0b0000100sssssrrrr, cprgr cp
185  { "cprgr", MCORE_CPU_DFLT, 0x9ff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0x1f0, 4, TYPE_REG }, { 0 }, { 0 }, { 0 } } },
186  // 0b00001010ssssrrrr, movf
187  { "movf", MCORE_CPU_DFLT, 0xaff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0xf0, 4, TYPE_REG }, { 0 }, { 0 }, { 0 } } },
188  // 0b00001011ssssrrrr, lsr
189  { "lsr", MCORE_CPU_DFLT, 0xbff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0xf0, 4, TYPE_REG }, { 0 }, { 0 }, { 0 } } },
190  // 0b00001100ssssrrrr, cmphs
191  { "cmphs", MCORE_CPU_DFLT, 0xbff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0xf0, 4, TYPE_REG }, { 0 }, { 0 }, { 0 } } },
192  // 0b00001101ssssrrrr, cmplt
193  { "cmplt", MCORE_CPU_DFLT, 0xdff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0xf0, 4, TYPE_REG }, { 0 }, { 0 }, { 0 } } },
194  // 0b00001110ssssrrrr, tst
195  { "tst", MCORE_CPU_DFLT, 0xeff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0xf0, 4, TYPE_REG }, { 0 }, { 0 }, { 0 } } },
196  // 0b00001111ssssrrrr, cmpne
197  { "cmpne", MCORE_CPU_DFLT, 0xfff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0xf0, 4, TYPE_REG }, { 0 }, { 0 }, { 0 } } },
198  // 0b0001000cccccrrrr, mfcr
199  { "mfcr", MCORE_CPU_DFLT, 0x11ff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0x1f0, 4, TYPE_CTRL }, { 0 }, { 0 }, { 0 } } },
200  // 0b0001000111110bbb, psrclr
201  { "psrclr", MCORE_CPU_DFLT, 0x11f7, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0x7, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
202  // 0b0001000111111bbb, psrset
203  { "psrset", MCORE_CPU_DFLT, 0x11ff, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0x7, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
204  // 0b00010010ssssrrrr, mov
205  { "mov", MCORE_CPU_DFLT, 0x12ff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0xf0, 4, TYPE_REG }, { 0 }, { 0 }, { 0 } } },
206  // 0b00010011ssssrrrr, bgenr
207  { "bgenr", MCORE_CPU_DFLT, 0x13ff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0xf0, 4, TYPE_REG }, { 0 }, { 0 }, { 0 } } },
208  // 0b00010100ssssrrrr, rsub
209  { "rsub", MCORE_CPU_DFLT, 0x14ff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0xf0, 4, TYPE_REG }, { 0 }, { 0 }, { 0 } } },
210  // 0b00010101ssssrrrr, lxw
211  { "lxw", MCORE_CPU_DFLT, 0x15ff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0xf0, 4, TYPE_REG }, { 0 }, { 0 }, { 0 } } },
212  // 0b00010110ssssrrrr, and
213  { "and", MCORE_CPU_DFLT, 0x16ff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0xf0, 4, TYPE_REG }, { 0 }, { 0 }, { 0 } } },
214  // 0b00010111ssssrrrr, xor
215  { "xor", MCORE_CPU_DFLT, 0x17ff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0xf0, 4, TYPE_REG }, { 0 }, { 0 }, { 0 } } },
216  // 0b0001100cccccrrrr, mtcr
217  { "mtcr", MCORE_CPU_DFLT, 0x11ff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0x1f0, 4, TYPE_CTRL }, { 0 }, { 0 }, { 0 } } },
218  // 0b00011010ssssrrrr, asr
219  { "asr", MCORE_CPU_DFLT, 0x1aff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0xf0, 4, TYPE_REG }, { 0 }, { 0 }, { 0 } } },
220  // 0b00011011ssssrrrr, lsl
221  { "lsl", MCORE_CPU_DFLT, 0x1bff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0xf0, 4, TYPE_REG }, { 0 }, { 0 }, { 0 } } },
222  // 0b00011100ssssrrrr, addu
223  { "addu", MCORE_CPU_DFLT, 0x1cff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0xf0, 4, TYPE_REG }, { 0 }, { 0 }, { 0 } } },
224  // 0b00011101ssssrrrr, lxh
225  { "lxh", MCORE_CPU_DFLT, 0x1dff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0xf0, 4, TYPE_REG }, { 0 }, { 0 }, { 0 } } },
226  // 0b00011110ssssrrrr, or
227  { "or", MCORE_CPU_DFLT, 0x1eff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0xf0, 4, TYPE_REG }, { 0 }, { 0 }, { 0 } } },
228  // 0b00011111ssssrrrr, andn
229  { "andn", MCORE_CPU_DFLT, 0x1fff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0xf0, 4, TYPE_REG }, { 0 }, { 0 }, { 0 } } },
230  // 0b0010000iiiiirrrr, addi
231  { "addi", MCORE_CPU_DFLT, 0x21ff, RZ_ANALYSIS_OP_TYPE_NULL, 3, { { 0xf, 0, TYPE_REG }, { 0xf, 0, TYPE_REG }, { 0x1f0, 4, TYPE_IMM }, { 0 }, { 0 } } },
232  // 0b0010001iiiiirrrr, cmplti
233  { "cmplti", MCORE_CPU_DFLT, 0x23ff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0x1f0, 4, TYPE_IMM }, { 0 }, { 0 }, { 0 } } },
234  // 0b0010010iiiiirrrr, subi
235  { "subi", MCORE_CPU_DFLT, 0x25ff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0x1f0, 4, TYPE_IMM }, { 0 }, { 0 }, { 0 } } },
236  // 0b0010011sssssrrrr, cpwgr cp
237  { "cpwgr", MCORE_CPU_DFLT, 0x27ff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0x1f0, 4, TYPE_CTRL }, { 0 }, { 0 }, { 0 } } },
238  // 0b0010100iiiiirrrr, rsubi
239  { "rsubi", MCORE_CPU_DFLT, 0x29ff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0x1f0, 4, TYPE_IMM }, { 0 }, { 0 }, { 0 } } },
240  // 0b0010101iiiiirrrr, cmpnei
241  { "cmpnei", MCORE_CPU_DFLT, 0x2bff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0x1f0, 4, TYPE_IMM }, { 0 }, { 0 }, { 0 } } },
242  // 0b001011000000rrrr, bmaski #32(set)
243  { "bmaski", MCORE_CPU_DFLT, 0x2c0f, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
244  // 0b001011000001rrrr, divu
245  { "divu", MCORE_CPU_DFLT, 0x2c1f, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
246  // 0b001011000010rrrr, mflos 610E
247  { "mflos", MCORE_CPU_610E, 0x2c2f, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
248  // 0b001011000011rrrr, mfhis 610E
249  { "mfhis", MCORE_CPU_610E, 0x2c2f, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
250  // 0b001011000100rrrr, mtlo 620
251  { "mtlo", MCORE_CPU_620, 0x2c4f, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
252  // 0b001011000101rrrr, mthi 620
253  { "mthi", MCORE_CPU_620, 0x2c5f, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
254  // 0b001011000110rrrr, mflo 620
255  { "mtlo", MCORE_CPU_620, 0x2c6f, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
256  // 0b001011000111rrrr, mfhi 620
257  { "mthi", MCORE_CPU_620, 0x2c7f, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
258  // 0b001011001iiirrrr, bmaski
259  { "bmaski", MCORE_CPU_DFLT, 0x2cff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0x70, 4, TYPE_IMM }, { 0 }, { 0 }, { 0 } } },
260  // 0b00101101iiiirrrr, bmaski
261  { "bmaski", MCORE_CPU_DFLT, 0x2dff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0xf0, 4, TYPE_IMM }, { 0 }, { 0 }, { 0 } } },
262  // 0b0010111iiiiirrrr, andi
263  { "andi", MCORE_CPU_DFLT, 0x2fff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0x1f0, 4, TYPE_IMM }, { 0 }, { 0 }, { 0 } } },
264  // 0b0011000iiiiirrrr, bclri
265  { "bclri", MCORE_CPU_DFLT, 0x31ff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0x1f0, 4, TYPE_IMM }, { 0 }, { 0 }, { 0 } } },
266  // 0b001100100000rrrr, cpwir cp
267  { "cpwir", MCORE_CPU_DFLT, 0x320f, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
268  // 0b001100100001rrrr, divs
269  { "divs", MCORE_CPU_DFLT, 0x321f, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
270  // 0b001100100010rrrr, cprsr cp
271  { "cprsr", MCORE_CPU_DFLT, 0x322f, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
272  // 0b001100100011rrrr, cpwsr cp
273  { "cpwsr", MCORE_CPU_DFLT, 0x323f, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
274  // 0b001100100100rrrr, --
275  // 0b001100100101rrrr, --
276  // 0b001100100110rrrr, --
277  // 0b001100100111rrrr, bgeni
278  { "bgeni", MCORE_CPU_DFLT, 0x327f, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
279  // 0b001100101iiirrrr, bgeni
280  { "bgeni", MCORE_CPU_DFLT, 0x32ff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0x70, 4, TYPE_IMM }, { 0 }, { 0 }, { 0 } } },
281  // 0b00110011iiiirrrr, bgeni
282  { "bgeni", MCORE_CPU_DFLT, 0x33ff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0xf0, 4, TYPE_IMM }, { 0 }, { 0 }, { 0 } } },
283  // 0b0011010iiiiirrrr, bseti
284  { "bgeni", MCORE_CPU_DFLT, 0x35ff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0x1f0, 4, TYPE_IMM }, { 0 }, { 0 }, { 0 } } },
285  // 0b0011011iiiiirrrr, btsti
286  { "btsti", MCORE_CPU_DFLT, 0x37ff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0x1f0, 4, TYPE_IMM }, { 0 }, { 0 }, { 0 } } },
287  // 0b001110000000rrrr, xsr
288  { "xsr", MCORE_CPU_DFLT, 0x380f, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
289  // 0b0011100iiiiirrrr, rotli
290  { "rotli", MCORE_CPU_DFLT, 0x39ff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0x1f0, 4, TYPE_IMM }, { 0 }, { 0 }, { 0 } } },
291  // 0b001110100000rrrr, asrc
292  { "asrc", MCORE_CPU_DFLT, 0x3a0f, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
293  // 0b0011101iiiiirrrr, asri
294  { "asri", MCORE_CPU_DFLT, 0x3bff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0x1f0, 4, TYPE_IMM }, { 0 }, { 0 }, { 0 } } },
295  // 0b001111000000rrrr, lslc
296  { "lslc", MCORE_CPU_DFLT, 0x3c0f, RZ_ANALYSIS_OP_TYPE_NULL, 1, { { 0xf, 0, TYPE_REG }, { 0 }, { 0 }, { 0 }, { 0 } } },
297  // 0b0011110iiiiirrrr, lsli
298  { "lsli", MCORE_CPU_DFLT, 0x3dff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0x1f0, 4, TYPE_IMM }, { 0 }, { 0 }, { 0 } } },
299  // 0b001111100000rrrr, lsrc
300  // 0b0011111iiiiirrrr, lsri
301  // 0b01000000ssssrrrr, omflip0 620
302  // 0b01000001ssssrrrr, omflip1 620
303  // 0b01000010ssssrrrr, omflip2 620
304  // 0b01000011ssssrrrr, omflip3 620
305  // 0b010001xxssssrrrr, --
306  // 0b01001xxxssssrrrr, --
307  // 0b01010000ssssrrrr, muls 610E
308  // 0b01010001ssssrrrr, mulsa 610E
309  // 0b
310  // 0b01010010ssssrrrr, mulss 610E
311  // 0b01010011ssssrrrr, --
312  // 0b01010100ssssrrrr, mulu 610E
313  // 0b01010101ssssrrrr, mulua 610E
314  // 0b01010110ssssrrrr, mulus 610E
315  // 0b01010111ssssrrrr, --
316  // 0b01011000ssssrrrr, vmulsh 610E
317  // 0b01011001ssssrrrr, vmulsha 610E
318  // 0b01011010ssssrrrr, vmulshs 610E
319  // 0b01011011ssssrrrr, --
320  // 0b01011100ssssrrrr, vmulsw 610E
321  // 0b01011101ssssrrrr, vmulswa 610E
322  // 0b01011110ssssrrrr, vmulsws 610E
323  // 0b01011111ssssrrrr, --
324  // 0b01100iiiiiiirrrr, movi
325  { "movi", MCORE_CPU_DFLT, 0x67ff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0xf, 0, TYPE_REG }, { 0x7f0, 4, TYPE_IMM }, { 0 }, { 0 }, { 0 } } },
326  // 0b01101000ssssrrrr, mulsh
327  // 0b01101001ssssrrrr, mulsha 610E
328  // 0b01101010ssssrrrr, mulshs 610E
329  // 0b01101011sssssrrr, cprcr cp
330  // 0b01101100ssssrrrr, mulsw 610E
331  // 0b01101101ssssrrrr, mulswa 610E
332  // 0b01101110ssssrrrr, mulsws 610E
333  // 0b01101111sssssrrr, cpwcr cp
334  { "cpwcr", MCORE_CPU_DFLT, 0x6fff, RZ_ANALYSIS_OP_TYPE_NULL, 2, { { 0x7, 0, TYPE_REG }, { 0xf8, 4, TYPE_IMM }, { 0 }, { 0 }, { 0 } } },
335  // 0b01110000dddddddd, jmpi
336  { "jmpi", MCORE_CPU_DFLT, 0x70ff, RZ_ANALYSIS_OP_TYPE_JMP, 2, { { 0xff, 0, TYPE_JMP }, { 0 }, { 0 }, { 0 }, { 0 } } },
337  // 0b0111zzzzdddddddd, lrw
338  { "lrw", MCORE_CPU_DFLT, 0x7fff, RZ_ANALYSIS_OP_TYPE_LOAD, 2, { { 0xff, 0, TYPE_MEM }, { 0xf00, 8, TYPE_REG }, { 0 }, { 0 }, { 0 } } },
339  // 0b01111111dddddddd, jsri
340  { "jsri", MCORE_CPU_DFLT, 0x7fff, RZ_ANALYSIS_OP_TYPE_CALL, 1, { { 0xff, 0, TYPE_JMPI }, { 0 }, { 0 }, { 0 }, { 0 } } },
341  // 0b1000zzzziiiirrrr, ld.w
342  { "ld.w", MCORE_CPU_DFLT, 0x8fff, RZ_ANALYSIS_OP_TYPE_LOAD, 4, { { 0xf, 0, TYPE_NONE }, { 0xf0, 4, TYPE_NONE }, { 0xf00, 8, TYPE_NONE }, { 0x6000, 13, TYPE_NONE }, { 0 } } },
343  // 0b1001zzzziiiirrrr, st.w
344  { "st.w", MCORE_CPU_DFLT, 0x9fff, RZ_ANALYSIS_OP_TYPE_STORE, 4, { { 0xf, 0, TYPE_NONE }, { 0xf0, 4, TYPE_NONE }, { 0xf00, 8, TYPE_NONE }, { 0x6000, 13, TYPE_NONE }, { 0 } } },
345  // 0b1010zzzziiiirrrr, ld.b
346  { "ld.b", MCORE_CPU_DFLT, 0xafff, RZ_ANALYSIS_OP_TYPE_LOAD, 4, { { 0xf, 0, TYPE_NONE }, { 0xf0, 4, TYPE_NONE }, { 0xf00, 8, TYPE_NONE }, { 0x6000, 13, TYPE_NONE }, { 0 } } },
347  // 0b1011zzzziiiirrrr, st.b
348  { "st.b", MCORE_CPU_DFLT, 0xbfff, RZ_ANALYSIS_OP_TYPE_STORE, 4, { { 0xf, 0, TYPE_NONE }, { 0xf0, 4, TYPE_NONE }, { 0xf00, 8, TYPE_NONE }, { 0x6000, 13, TYPE_NONE }, { 0 } } },
349  // 0b1100zzzziiiirrrr, ld.h
350  { "ld.h", MCORE_CPU_DFLT, 0xcfff, RZ_ANALYSIS_OP_TYPE_LOAD, 4, { { 0xf, 0, TYPE_NONE }, { 0xf0, 4, TYPE_NONE }, { 0xf00, 8, TYPE_NONE }, { 0x6000, 13, TYPE_NONE }, { 0 } } },
351  // 0b1101zzzziiiirrrr, st.h
352  { "st.h", MCORE_CPU_DFLT, 0xdfff, RZ_ANALYSIS_OP_TYPE_STORE, 4, { { 0xf, 0, TYPE_NONE }, { 0xf0, 4, TYPE_NONE }, { 0xf00, 8, TYPE_NONE }, { 0x6000, 13, TYPE_NONE }, { 0 } } },
353  // 0b11100ddddddddddd, bt
354  { "bt", MCORE_CPU_DFLT, 0xe7ff, RZ_ANALYSIS_OP_TYPE_CJMP, 1, { { 0x7ff, 0, TYPE_JMP }, { 0 }, { 0 }, { 0 }, { 0 } } },
355  // 0b11101ddddddddddd, bf
356  { "bf", MCORE_CPU_DFLT, 0xefff, RZ_ANALYSIS_OP_TYPE_CJMP, 1, { { 0x7ff, 0, TYPE_JMP }, { 0 }, { 0 }, { 0 }, { 0 } } },
357  // 0b11110ddddddddddd, br
358  { "br", MCORE_CPU_DFLT, 0xf7ff, RZ_ANALYSIS_OP_TYPE_CJMP, 1, { { 0x7ff, 0, TYPE_JMP }, { 0 }, { 0 }, { 0 }, { 0 } } },
359  // 0b11111ddddddddddd, bsr
360  { "bsr", MCORE_CPU_DFLT, 0xffff, RZ_ANALYSIS_OP_TYPE_CALL, 1, { { 0x7ff, 0, TYPE_JMP }, { 0 }, { 0 }, { 0 }, { 0 } } },
361 };
362 
363 static mcore_t *find_instruction(const ut8 *buffer) {
364  ut32 i = 0;
365  mcore_ops_t *op_ptr = NULL;
366  mcore_t *op = NULL;
367  if (!buffer || !(op = malloc(sizeof(mcore_t)))) {
368  return NULL;
369  }
370  memset(op, 0, sizeof(mcore_t));
371  ut32 count = sizeof(mcore_instructions) / sizeof(mcore_ops_t);
372  ut16 data = buffer[1] << 8;
373  data |= buffer[0];
374  op->bytes = data;
375  op->size = MCORE_INSTR_ALIGN;
376  if (data == 0) {
377  op_ptr = &mcore_instructions[0];
378  } else {
379  for (i = 1; i < count; i++) {
380  op_ptr = &mcore_instructions[i];
381  ut16 masked = data & op_ptr->mask;
382  // always masking with zero returns 0
383  if (masked == data) {
384  break;
385  }
386  }
387  if (i >= count) {
388  op->name = "illegal";
389  return op;
390  }
391  }
392 
393  if (!strncmp(op_ptr->name, "lrw", 3) && (data & 0xf00) == 0xf00) {
394  // is jump
395  if (i > 0 && i < MCORE_INSTRS) {
396  op_ptr = &mcore_instructions[i + 1];
397  }
398  }
399  op->type = op_ptr->type;
400  op->name = op_ptr->name;
401  op->n_args = op_ptr->n_args;
402  for (i = 0; i < op_ptr->n_args; i++) {
403  op->args[i].value = (data & op_ptr->args[i].mask) >> op_ptr->args[i].shift;
404  op->args[i].type = op_ptr->args[i].type;
405  }
406  return op;
407 }
408 
409 int mcore_init(mcore_handle *handle, const ut8 *buffer, const ut32 size) {
410  if (!handle || !buffer || size < 2) {
411  return 1;
412  }
413  handle->pos = buffer;
414  handle->end = buffer + size;
415  return 0;
416 }
417 
418 mcore_t *mcore_next(mcore_handle *handle) {
419  mcore_t *op = NULL;
420  if (!handle || handle->pos + MCORE_INSTR_ALIGN > handle->end) {
421  return NULL;
422  }
423 
424  if (!op && handle->pos + 2 <= handle->end) {
425  op = find_instruction(handle->pos);
426  }
427  handle->pos += MCORE_INSTR_ALIGN;
428 
429  return op;
430 }
431 
432 void mcore_free(mcore_t *instr) {
433  free(instr);
434 }
435 
436 void print_loop(char *str, int size, ut64 addr, mcore_t *instr) {
437  ut32 i;
438  int bufsize = size;
439  int add = snprintf(str, bufsize, "%s", instr->name);
440  for (i = 0; add > 0 && i < instr->n_args && add < bufsize; i++) {
441  if (instr->args[i].type == TYPE_REG) {
442  add += snprintf(str + add, bufsize - add, " r%u,", instr->args[i].value);
443  } else if (instr->args[i].type == TYPE_IMM) {
444  add += snprintf(str + add, bufsize - add, " 0x%x,", instr->args[i].value);
445  } else if (instr->args[i].type == TYPE_MEM) {
446  add += snprintf(str + add, bufsize - add, " 0x%x(r%d),",
447  instr->args[i + 1].value, instr->args[i].value);
448  i++;
449  } else if (instr->args[i].type == TYPE_JMPI) {
450  ut64 jump = addr + ((instr->args[i].value << 2) & 0xfffffffc);
451  add += snprintf(str + add, bufsize - add, " [0x%" PFMT64x "],", jump);
452  } else if (instr->args[i].type == TYPE_JMP) {
453  ut64 jump = addr + instr->args[i].value + 1;
454  add += snprintf(str + add, bufsize - add, " 0x%" PFMT64x ",", jump);
455  } else if (instr->args[i].type == TYPE_CTRL) {
456  ut32 pos = instr->args[i].value;
457  if (pos >= 32) {
458  pos = 32;
459  }
460  add += snprintf(str + add, bufsize - add, " %s,", mcore_ctrl_registers[pos]);
461  }
462  }
463  if (instr->n_args) {
464  // removing a comma
465  *(str + add - 1) = 0;
466  }
467 }
468 
469 void mcore_snprint(char *str, int size, ut64 addr, mcore_t *instr) {
470  ut32 imm;
471  if (!instr || !str) {
472  return;
473  }
474  switch (instr->type) {
475  case RZ_ANALYSIS_OP_TYPE_LOAD:
476  case RZ_ANALYSIS_OP_TYPE_STORE:
477  imm = instr->args[1].value << load_shift[instr->args[3].value];
478  snprintf(str, size, "%s r%u, (r%u, 0x%x)",
479  instr->name, instr->args[2].value, instr->args[0].value, imm);
480  break;
481  default:
482  print_loop(str, size, addr, instr);
483  break;
484  }
485 }
op
ut8 op
Definition: 6502dis.c:13
imm
#define imm
Definition: analysis_h8300.c:43
i
lzma_index ** i
Definition: index.h:629
TYPE_IMM
@ TYPE_IMM
Definition: armass.c:35
TYPE_MEM
@ TYPE_MEM
Definition: armass.c:36
handle
static mcore_handle handle
Definition: asm_mcore.c:8
jump
int jump(int a, int b)
Definition: bcj_test.c:35
buffer
struct buffer buffer
NULL
#define NULL
Definition: cris-opc.c:27
count
static static sync static getppid static getegid const char static filename char static len const char char static bufsiz static mask static vfork const void static prot static getpgrp const char static swapflags static arg static fd static protocol static who struct sockaddr static addrlen static backlog struct timeval struct timezone static tz const struct iovec static count static mode const void const struct sockaddr static tolen const char static pathname void count
Definition: sflib.h:98
ut16
uint16_t ut16
Definition: demangler_util.h:30
ut32
uint32_t ut32
Definition: demangler_util.h:31
free
RZ_API void Ht_() free(HtName_(Ht) *ht)
Definition: ht_inc.c:130
size
voidpf void uLong size
Definition: ioapi.h:138
snprintf
snprintf
Definition: kernel.h:364
ut8
uint8_t ut8
Definition: lh5801.h:11
memset
return memset(p, 0, total)
malloc
void * malloc(size_t size)
Definition: malloc.c:123
TYPE_NONE
@ TYPE_NONE
Definition: marshal.h:30
MCORE_INSTR_ALIGN
#define MCORE_INSTR_ALIGN
Definition: mcore.c:14
mcore_ops_t
struct mcore_ops mcore_ops_t
find_instruction
static mcore_t * find_instruction(const ut8 *buffer)
Definition: mcore.c:363
mcore_ctrl_registers
static const char * mcore_ctrl_registers[]
Definition: mcore.c:17
mcore_init
int mcore_init(mcore_handle *handle, const ut8 *buffer, const ut32 size)
Definition: mcore.c:409
mcore_snprint
void mcore_snprint(char *str, int size, ut64 addr, mcore_t *instr)
Definition: mcore.c:469
mcore_mask_t
struct mcore_mask mcore_mask_t
MCORE_INSTRS
#define MCORE_INSTRS
Definition: mcore.c:95
mcore_instructions
mcore_ops_t mcore_instructions[MCORE_INSTRS]
Definition: mcore.c:96
mcore_next
mcore_t * mcore_next(mcore_handle *handle)
Definition: mcore.c:418
print_loop
void print_loop(char *str, int size, ut64 addr, mcore_t *instr)
Definition: mcore.c:436
mcore_free
void mcore_free(mcore_t *instr)
Definition: mcore.c:432
load_shift
ut16 load_shift[4]
Definition: mcore.c:93
TYPE_JMPI
#define TYPE_JMPI
Definition: mcore.h:26
MCORE_CPU_610E
#define MCORE_CPU_610E
Definition: mcore.h:18
TYPE_CTRL
#define TYPE_CTRL
Definition: mcore.h:27
MCORE_CPU_DFLT
#define MCORE_CPU_DFLT
Definition: mcore.h:16
TYPE_REG
#define TYPE_REG
Definition: mcore.h:22
MCORE_CPU_620
#define MCORE_CPU_620
Definition: mcore.h:19
TYPE_JMP
#define TYPE_JMP
Definition: mcore.h:25
ARGS_SIZE
#define ARGS_SIZE
Definition: mcore.h:14
MCORE_CPU_510E
#define MCORE_CPU_510E
Definition: mcore.h:17
cmd_descs_generate.str
str
Definition: cmd_descs_generate.py:785
rz_analysis.h
RZ_ANALYSIS_OP_TYPE_LOAD
@ RZ_ANALYSIS_OP_TYPE_LOAD
Definition: rz_analysis.h:416
RZ_ANALYSIS_OP_TYPE_JMP
@ RZ_ANALYSIS_OP_TYPE_JMP
Definition: rz_analysis.h:368
RZ_ANALYSIS_OP_TYPE_SYNC
@ RZ_ANALYSIS_OP_TYPE_SYNC
Definition: rz_analysis.h:431
RZ_ANALYSIS_OP_TYPE_NULL
@ RZ_ANALYSIS_OP_TYPE_NULL
Definition: rz_analysis.h:367
RZ_ANALYSIS_OP_TYPE_CALL
@ RZ_ANALYSIS_OP_TYPE_CALL
Definition: rz_analysis.h:378
RZ_ANALYSIS_OP_TYPE_STORE
@ RZ_ANALYSIS_OP_TYPE_STORE
Definition: rz_analysis.h:415
RZ_ANALYSIS_OP_TYPE_CJMP
@ RZ_ANALYSIS_OP_TYPE_CJMP
Definition: rz_analysis.h:373
RZ_ANALYSIS_OP_TYPE_ILL
@ RZ_ANALYSIS_OP_TYPE_ILL
Definition: rz_analysis.h:387
RZ_ANALYSIS_OP_TYPE_RET
@ RZ_ANALYSIS_OP_TYPE_RET
Definition: rz_analysis.h:385
PFMT64x
#define PFMT64x
Definition: rz_types.h:393
buffer
Definition: buffer.h:15
mcore_field_t::type
ut16 type
Definition: mcore.h:37
mcore_field_t::value
ut32 value
Definition: mcore.h:36
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mcore_handle::pos
const ut8 * pos
Definition: mcore.h:31
mcore_handle::end
const ut8 * end
Definition: mcore.h:30
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Definition: mcore.c:78
mcore_mask::type
ut16 type
Definition: mcore.c:81
mcore_mask::shift
ut16 shift
Definition: mcore.c:80
mcore_mask::mask
ut16 mask
Definition: mcore.c:79
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Definition: mcore.c:84
mcore_ops::name
const char * name
Definition: mcore.c:85
mcore_ops::args
mcore_mask_t args[ARGS_SIZE]
Definition: mcore.c:90
mcore_ops::mask
ut16 mask
Definition: mcore.c:87
mcore_ops::type
ut64 type
Definition: mcore.c:88
mcore_ops::cpu
ut16 cpu
Definition: mcore.c:86
mcore_ops::n_args
ut16 n_args
Definition: mcore.c:89
mcore_t
Definition: mcore.h:40
mcore_t::type
ut64 type
Definition: mcore.h:43
mcore_t::n_args
ut16 n_args
Definition: mcore.h:44
mcore_t::name
const char * name
Definition: mcore.h:41
mcore_t::args
mcore_field_t args[ARGS_SIZE]
Definition: mcore.h:42
pos
int pos
Definition: main.c:11
op
Definition: dis.c:32
ut64
ut64(WINAPI *w32_GetEnabledXStateFeatures)()
addr
static int addr
Definition: z80asm.c:58
add
static int add(char *argv[])
Definition: ziptool.c:84