Rizin
unix-like reverse engineering framework and cli tools
ppc.h
Go to the documentation of this file.
1 // SPDX-FileCopyrightText: 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
2 // SPDX-License-Identifier: GPL-1.0-or-later
3 
4 /* ppc.h -- Header file for PowerPC opcode table
5  Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
6  2007 Free Software Foundation, Inc.
7  Written by Ian Lance Taylor, Cygnus Support
8 
9 This file is part of GDB, GAS, and the GNU binutils.
10 
11 GDB, GAS, and the GNU binutils are free software; you can redistribute
12 them and/or modify them under the terms of the GNU General Public
13 License as published by the Free Software Foundation; either version
14 1, or (at your option) any later version.
15 
16 GDB, GAS, and the GNU binutils are distributed in the hope that they
17 will be useful, but WITHOUT ANY WARRANTY; without even the implied
18 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
19 the GNU General Public License for more details.
20 
21 You should have received a copy of the GNU General Public License
22 along with this file; see the file COPYING. If not, write to the Free
23 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
24 
25 #ifndef PPC_H
26 #define PPC_H
27 
28 typedef unsigned long ppc_cpu_t;
29 
30 /* The opcode table is an array of struct powerpc_opcode. */
31 
33  /* The opcode name. */
34  const char *name;
35 
36  /* The opcode itself. Those bits which will be filled in with
37  operands are zeroes. */
38  unsigned long opcode;
39 
40  /* The opcode mask. This is used by the disassembler. This is a
41  mask containing ones indicating those bits which must match the
42  opcode field, and zeroes indicating those bits which need not
43  match (and are presumably filled in by operands). */
44  unsigned long mask;
45 
46  /* One bit flags for the opcode. These are used to indicate which
47  specific processors support the instructions. The defined values
48  are listed below. */
50 
51  /* An array of operand codes. Each code is an index into the
52  operand table. They appear in the order which the operands must
53  appear in assembly code, and are terminated by a zero. */
54  unsigned char operands[8];
55 };
56 
57 /* The table itself is sorted by major opcode number, and is otherwise
58  in the order in which the disassembler should consider
59  instructions. */
60 extern const struct powerpc_opcode powerpc_opcodes[];
61 extern const int powerpc_num_opcodes;
62 
63 /* Values defined for the flags field of a struct powerpc_opcode. */
64 
65 /* Opcode is defined for the PowerPC architecture. */
66 #define PPC_OPCODE_PPC 1
67 
68 /* Opcode is defined for the POWER (RS/6000) architecture. */
69 #define PPC_OPCODE_POWER 2
70 
71 /* Opcode is defined for the POWER2 (Rios 2) architecture. */
72 #define PPC_OPCODE_POWER2 4
73 
74 /* Opcode is only defined on 32 bit architectures. */
75 #define PPC_OPCODE_32 8
76 
77 /* Opcode is only defined on 64 bit architectures. */
78 #define PPC_OPCODE_64 0x10
79 
80 /* Opcode is supported by the Motorola PowerPC 601 processor. The 601
81  is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
82  but it also supports many additional POWER instructions. */
83 #define PPC_OPCODE_601 0x20
84 
85 /* Opcode is supported in both the Power and PowerPC architectures
86  (ie, compiler's -mcpu=common or assembler's -mcom). */
87 #define PPC_OPCODE_COMMON 0x40
88 
89 /* Opcode is supported for any Power or PowerPC platform (this is
90  for the assembler's -many option, and it eliminates duplicates). */
91 #define PPC_OPCODE_ANY 0x80
92 
93 /* Opcode is supported as part of the 64-bit bridge. */
94 #define PPC_OPCODE_64_BRIDGE 0x100
95 
96 /* Opcode is supported by Altivec Vector Unit */
97 #define PPC_OPCODE_ALTIVEC 0x200
98 
99 /* Opcode is supported by PowerPC 403 processor. */
100 #define PPC_OPCODE_403 0x400
101 
102 /* Opcode is supported by PowerPC BookE processor. */
103 #define PPC_OPCODE_BOOKE 0x800
104 
105 /* Opcode is only supported by 64-bit PowerPC BookE processor. */
106 #define PPC_OPCODE_BOOKE64 0x1000
107 
108 /* Opcode is supported by PowerPC 440 processor. */
109 #define PPC_OPCODE_440 0x2000
110 
111 /* Opcode is only supported by Power4 architecture. */
112 #define PPC_OPCODE_POWER4 0x4000
113 
114 /* Opcode isn't supported by Power4 architecture. */
115 #define PPC_OPCODE_NOPOWER4 0x8000
116 
117 /* Opcode is only supported by POWERPC Classic architecture. */
118 #define PPC_OPCODE_CLASSIC 0x10000
119 
120 /* Opcode is only supported by e500x2 Core. */
121 #define PPC_OPCODE_SPE 0x20000
122 
123 /* Opcode is supported by e500x2 Integer select APU. */
124 #define PPC_OPCODE_ISEL 0x40000
125 
126 /* Opcode is an e500 SPE floating point instruction. */
127 #define PPC_OPCODE_EFS 0x80000
128 
129 /* Opcode is supported by branch locking APU. */
130 #define PPC_OPCODE_BRLOCK 0x100000
131 
132 /* Opcode is supported by performance monitor APU. */
133 #define PPC_OPCODE_PMR 0x200000
134 
135 /* Opcode is supported by cache locking APU. */
136 #define PPC_OPCODE_CACHELCK 0x400000
137 
138 /* Opcode is supported by machine check APU. */
139 #define PPC_OPCODE_RFMCI 0x800000
140 
141 /* Opcode is only supported by Power5 architecture. */
142 #define PPC_OPCODE_POWER5 0x1000000
143 
144 /* Opcode is supported by PowerPC e300 family. */
145 #define PPC_OPCODE_E300 0x2000000
146 
147 /* Opcode is only supported by Power6 architecture. */
148 #define PPC_OPCODE_POWER6 0x4000000
149 
150 /* Opcode is only supported by PowerPC Cell family. */
151 #define PPC_OPCODE_CELL 0x8000000
152 
153 /* Opcode is supported by CPUs with paired singles support. */
154 #define PPC_OPCODE_PPCPS 0x10000000
155 
156 /* Opcode is supported by Power E500MC */
157 #define PPC_OPCODE_E500MC 0x20000000
158 
159 /* Opcode is supported by PowerPC 405 processor. */
160 #define PPC_OPCODE_405 0x40000000
161 
162 /* Opcode is supported by Vector-Scalar (VSX) Unit */
163 #define PPC_OPCODE_VSX 0x80000000
164 
165 /* A macro to extract the major opcode from an instruction. */
166 #define PPC_OP(i) (((i) >> 26) & 0x3f)
167 
168 /* The operands table is an array of struct powerpc_operand. */
169 
171  /* A bitmask of bits in the operand. */
172  unsigned int bitm;
173 
174  /* How far the operand is left shifted in the instruction.
175  -1 to indicate that BITM and SHIFT cannot be used to determine
176  where the operand goes in the insn. */
177  int shift;
178 
179  /* Insertion function. This is used by the assembler. To insert an
180  operand value into an instruction, check this field.
181 
182  If it is NULL, execute
183  i |= (op & o->bitm) << o->shift;
184  (i is the instruction which we are filling in, o is a pointer to
185  this structure, and op is the operand value).
186 
187  If this field is not NULL, then simply call it with the
188  instruction and the operand value. It will return the new value
189  of the instruction. If the ERRMSG argument is not NULL, then if
190  the operand value is illegal, *ERRMSG will be set to a warning
191  string (the operand will be inserted in any case). If the
192  operand value is legal, *ERRMSG will be unchanged (most operands
193  can accept any value). */
194  unsigned long (*insert)(unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg);
195 
196  /* Extraction function. This is used by the disassembler. To
197  extract this operand type from an instruction, check this field.
198 
199  If it is NULL, compute
200  op = (i >> o->shift) & o->bitm;
201  if ((o->flags & PPC_OPERAND_SIGNED) != 0)
202  sign_extend (op);
203  (i is the instruction, o is a pointer to this structure, and op
204  is the result).
205 
206  If this field is not NULL, then simply call it with the
207  instruction value. It will return the value of the operand. If
208  the INVALID argument is not NULL, *INVALID will be set to
209  non-zero if this operand type can not actually be extracted from
210  this operand (i.e., the instruction does not match). If the
211  operand is valid, *INVALID will not be changed. */
212  long (*extract)(unsigned long instruction, ppc_cpu_t dialect, int *invalid);
213 
214  /* One bit syntax flags. */
215  unsigned long flags;
216 };
217 
218 /* Elements in the table are retrieved by indexing with values from
219  the operands field of the powerpc_opcodes table. */
220 
221 extern const struct powerpc_operand powerpc_operands[];
222 extern const unsigned int num_powerpc_operands;
223 
224 /* Values defined for the flags field of a struct powerpc_operand. */
225 
226 /* This operand takes signed values. */
227 #define PPC_OPERAND_SIGNED (0x1)
228 
229 /* This operand takes signed values, but also accepts a full positive
230  range of values when running in 32 bit mode. That is, if bits is
231  16, it takes any value from -0x8000 to 0xffff. In 64 bit mode,
232  this flag is ignored. */
233 #define PPC_OPERAND_SIGNOPT (0x2)
234 
235 /* This operand does not actually exist in the assembler input. This
236  is used to support extended mnemonics such as mr, for which two
237  operands fields are identical. The assembler should call the
238  insert function with any op value. The disassembler should call
239  the extract function, ignore the return value, and check the value
240  placed in the valid argument. */
241 #define PPC_OPERAND_FAKE (0x4)
242 
243 /* The next operand should be wrapped in parentheses rather than
244  separated from this one by a comma. This is used for the load and
245  store instructions which want their operands to look like
246  reg,displacement(reg)
247  */
248 #define PPC_OPERAND_PARENS (0x8)
249 
250 /* This operand may use the symbolic names for the CR fields, which
251  are
252  lt 0 gt 1 eq 2 so 3 un 3
253  cr0 0 cr1 1 cr2 2 cr3 3
254  cr4 4 cr5 5 cr6 6 cr7 7
255  These may be combined arithmetically, as in cr2*4+gt. These are
256  only supported on the PowerPC, not the POWER. */
257 #define PPC_OPERAND_CR (0x10)
258 
259 /* This operand names a register. The disassembler uses this to print
260  register names with a leading 'r'. */
261 #define PPC_OPERAND_GPR (0x20)
262 
263 /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */
264 #define PPC_OPERAND_GPR_0 (0x40)
265 
266 /* This operand names a floating point register. The disassembler
267  prints these with a leading 'f'. */
268 #define PPC_OPERAND_FPR (0x80)
269 
270 /* This operand is a relative branch displacement. The disassembler
271  prints these symbolically if possible. */
272 #define PPC_OPERAND_RELATIVE (0x100)
273 
274 /* This operand is an absolute branch address. The disassembler
275  prints these symbolically if possible. */
276 #define PPC_OPERAND_ABSOLUTE (0x200)
277 
278 /* This operand is optional, and is zero if omitted. This is used for
279  example, in the optional BF field in the comparison instructions. The
280  assembler must count the number of operands remaining on the line,
281  and the number of operands remaining for the opcode, and decide
282  whether this operand is present or not. The disassembler should
283  print this operand out only if it is not zero. */
284 #define PPC_OPERAND_OPTIONAL (0x400)
285 
286 /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
287  is omitted, then for the next operand use this operand value plus
288  1, ignoring the next operand field for the opcode. This wretched
289  hack is needed because the Power rotate instructions can take
290  either 4 or 5 operands. The disassembler should print this operand
291  out regardless of the PPC_OPERAND_OPTIONAL field. */
292 #define PPC_OPERAND_NEXT (0x800)
293 
294 /* This operand should be regarded as a negative number for the
295  purposes of overflow checking (i.e., the normal most negative
296  number is disallowed and one more than the normal most positive
297  number is allowed). This flag will only be set for a signed
298  operand. */
299 #define PPC_OPERAND_NEGATIVE (0x1000)
300 
301 /* This operand names a vector unit register. The disassembler
302  prints these with a leading 'v'. */
303 #define PPC_OPERAND_VR (0x2000)
304 
305 /* This operand is for the DS field in a DS form instruction. */
306 #define PPC_OPERAND_DS (0x4000)
307 
308 /* This operand is for the DQ field in a DQ form instruction. */
309 #define PPC_OPERAND_DQ (0x8000)
310 
311 /* Valid range of operand is 0..n rather than 0..n-1. */
312 #define PPC_OPERAND_PLUS1 (0x10000)
313 
314 /* Xilinx APU and FSL related operands */
315 #define PPC_OPERAND_FSL (0x20000)
316 #define PPC_OPERAND_FCR (0x40000)
317 #define PPC_OPERAND_UDI (0x80000)
318 
319 /* This operand names a vector-scalar unit register. The disassembler
320  prints these with a leading 'vs'. */
321 #define PPC_OPERAND_VSR (0x100000)
322 
323 /* The POWER and PowerPC assemblers use a few macros. We keep them
324  with the operands table for simplicity. The macro table is an
325  array of struct powerpc_macro. */
326 
328  /* The macro name. */
329  const char *name;
330 
331  /* The number of operands the macro takes. */
332  unsigned int operands;
333 
334  /* One bit flags for the opcode. These are used to indicate which
335  specific processors support the instructions. The values are the
336  same as those for the struct powerpc_opcode flags field. */
338 
339  /* A format string to turn the macro into a normal instruction.
340  Each %N in the string is replaced with operand number N (zero
341  based). */
342  const char *format;
343 };
344 
345 extern const struct powerpc_macro powerpc_macros[];
346 extern const int powerpc_num_macros;
347 
348 #endif /* PPC_H */
ut8 op
Definition: 6502dis.c:13
static static sync static getppid static getegid const char static filename char static len const char char static bufsiz static mask static vfork const void static prot static getpgrp const char static swapflags long
Definition: sflib.h:79
const struct powerpc_macro powerpc_macros[]
const struct powerpc_opcode powerpc_opcodes[]
unsigned long ppc_cpu_t
Definition: ppc.h:28
const int powerpc_num_macros
const int powerpc_num_opcodes
const struct powerpc_operand powerpc_operands[]
const unsigned int num_powerpc_operands
ppc_cpu_t flags
Definition: ppc.h:337
const char * format
Definition: ppc.h:342
const char * name
Definition: ppc.h:329
unsigned int operands
Definition: ppc.h:332
unsigned long mask
Definition: ppc.h:44
unsigned long opcode
Definition: ppc.h:38
const char * name
Definition: ppc.h:34
ppc_cpu_t flags
Definition: ppc.h:49
unsigned int bitm
Definition: ppc.h:172
unsigned long(* insert)(unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg)
Definition: ppc.h:194
long(* extract)(unsigned long instruction, ppc_cpu_t dialect, int *invalid)
Definition: ppc.h:212
int shift
Definition: ppc.h:177
unsigned long flags
Definition: ppc.h:215