hexagon.h File Reference

#include <rz_asm.h>
#include <rz_config.h>
#include <rz_list.h>
#include <rz_types.h>
#include <rz_util/rz_print.h>

Go to the source code of this file.

Classes
struct	HexPktInfo
struct	HexOp
struct	HexInsn
struct	HexPkt
struct	HexConstExt
struct	HexState
	Buffer packets for reversed instructions. More...

Macros
#define	HEX_MAX_OPERANDS   6
#define	HEX_PARSE_BITS_MASK   0xc000
#define	MAX_CONST_EXT   512
#define	HEXAGON_STATE_PKTS   8
#define	BIT_MASK(len)   (BIT(len) - 1)
#define	BF_MASK(start, len)   (BIT_MASK(len) << (start))
#define	BF_PREP(x, start, len)   (((x)&BIT_MASK(len)) << (start))
#define	BF_GET(y, start, len)   (((y) >> (start)) & BIT_MASK(len))
#define	BF_GETB(y, start, end)   (BF_GET((y), (start), (end) - (start) + 1)

Enumerations
enum	HexPred { HEX_NOPRED , HEX_PRED_TRUE , HEX_PRED_FALSE , HEX_PRED_NEW }
enum	HexPf {   HEX_PF_RND = 1 , HEX_PF_CRND = 1 << 1 , HEX_PF_RAW = 1 << 2 , HEX_PF_CHOP = 1 << 3 ,   HEX_PF_SAT = 1 << 4 , HEX_PF_HI = 1 << 5 , HEX_PF_LO = 1 << 6 , HEX_PF_LSH1 = 1 << 7 ,   HEX_PF_LSH16 = 1 << 8 , HEX_PF_RSH1 = 1 << 9 , HEX_PF_NEG = 1 << 10 , HEX_PF_POS = 1 << 11 ,   HEX_PF_SCALE = 1 << 12 , HEX_PF_DEPRECATED = 1 << 15 }
enum	HexOpType { HEX_OP_TYPE_IMM , HEX_OP_TYPE_REG }
enum	HexOpAttr {   HEX_OP_CONST_EXT = 1 << 0 , HEX_OP_REG_HI = 1 << 1 , HEX_OP_REG_LO = 1 << 2 , HEX_OP_REG_PAIR = 1 << 3 ,   HEX_OP_REG_QUADRUPLE = 1 << 4 , HEX_OP_REG_OUT = 1 << 5 , HEX_OP_IMM_SCALED = 1 << 6 }
enum	HexLoopAttr { HEX_NO_LOOP = 0 , HEX_LOOP_0 = 1 , HEX_LOOP_1 = 1 << 1 , HEX_LOOP_01 = 1 << 2 }
enum	HexRegClass {   HEX_REG_CLASS_CTR_REGS , HEX_REG_CLASS_CTR_REGS64 , HEX_REG_CLASS_DOUBLE_REGS , HEX_REG_CLASS_GENERAL_DOUBLE_LOW8_REGS ,   HEX_REG_CLASS_GENERAL_SUB_REGS , HEX_REG_CLASS_GUEST_REGS , HEX_REG_CLASS_GUEST_REGS64 , HEX_REG_CLASS_HVX_QR ,   HEX_REG_CLASS_HVX_VQR , HEX_REG_CLASS_HVX_VR , HEX_REG_CLASS_HVX_WR , HEX_REG_CLASS_INT_REGS ,   HEX_REG_CLASS_INT_REGS_LOW8 , HEX_REG_CLASS_MOD_REGS , HEX_REG_CLASS_PRED_REGS , HEX_REG_CLASS_SYS_REGS ,   HEX_REG_CLASS_SYS_REGS64 }
enum	HEX_CTR_REGS {   HEX_REG_CTR_REGS_C0 = 0 , HEX_REG_CTR_REGS_C1 = 1 , HEX_REG_CTR_REGS_C2 = 2 , HEX_REG_CTR_REGS_C3 = 3 ,   HEX_REG_CTR_REGS_C4 = 4 , HEX_REG_CTR_REGS_C5 = 5 , HEX_REG_CTR_REGS_C6 = 6 , HEX_REG_CTR_REGS_C7 = 7 ,   HEX_REG_CTR_REGS_C8 = 8 , HEX_REG_CTR_REGS_C9 = 9 , HEX_REG_CTR_REGS_C10 = 10 , HEX_REG_CTR_REGS_C11 = 11 ,   HEX_REG_CTR_REGS_C12 = 12 , HEX_REG_CTR_REGS_C13 = 13 , HEX_REG_CTR_REGS_C14 = 14 , HEX_REG_CTR_REGS_C15 = 15 ,   HEX_REG_CTR_REGS_C16 = 16 , HEX_REG_CTR_REGS_C17 = 17 , HEX_REG_CTR_REGS_C18 = 18 , HEX_REG_CTR_REGS_C19 = 19 ,   HEX_REG_CTR_REGS_C30 = 30 , HEX_REG_CTR_REGS_C31 = 31 }
enum	HEX_CTR_REGS64 {   HEX_REG_CTR_REGS64_C1_0 = 0 , HEX_REG_CTR_REGS64_C3_2 = 2 , HEX_REG_CTR_REGS64_C5_4 = 4 , HEX_REG_CTR_REGS64_C7_6 = 6 ,   HEX_REG_CTR_REGS64_C9_8 = 8 , HEX_REG_CTR_REGS64_C11_10 = 10 , HEX_REG_CTR_REGS64_C13_12 = 12 , HEX_REG_CTR_REGS64_C15_14 = 14 ,   HEX_REG_CTR_REGS64_C17_16 = 16 , HEX_REG_CTR_REGS64_C19_18 = 18 , HEX_REG_CTR_REGS64_C31_30 = 30 }
enum	HEX_DOUBLE_REGS {   HEX_REG_DOUBLE_REGS_R1_0 = 0 , HEX_REG_DOUBLE_REGS_R3_2 = 2 , HEX_REG_DOUBLE_REGS_R5_4 = 4 , HEX_REG_DOUBLE_REGS_R7_6 = 6 ,   HEX_REG_DOUBLE_REGS_R9_8 = 8 , HEX_REG_DOUBLE_REGS_R11_10 = 10 , HEX_REG_DOUBLE_REGS_R13_12 = 12 , HEX_REG_DOUBLE_REGS_R15_14 = 14 ,   HEX_REG_DOUBLE_REGS_R17_16 = 16 , HEX_REG_DOUBLE_REGS_R19_18 = 18 , HEX_REG_DOUBLE_REGS_R21_20 = 20 , HEX_REG_DOUBLE_REGS_R23_22 = 22 ,   HEX_REG_DOUBLE_REGS_R25_24 = 24 , HEX_REG_DOUBLE_REGS_R27_26 = 26 , HEX_REG_DOUBLE_REGS_R29_28 = 28 , HEX_REG_DOUBLE_REGS_R31_30 = 30 }
enum	HEX_GENERAL_DOUBLE_LOW8_REGS {   HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R1_0 = 0 , HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R3_2 = 2 , HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R5_4 = 4 , HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R7_6 = 6 ,   HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R17_16 = 16 , HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R19_18 = 18 , HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R21_20 = 20 , HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R23_22 = 22 }
enum	HEX_GENERAL_SUB_REGS {   HEX_REG_GENERAL_SUB_REGS_R0 = 0 , HEX_REG_GENERAL_SUB_REGS_R1 = 1 , HEX_REG_GENERAL_SUB_REGS_R2 = 2 , HEX_REG_GENERAL_SUB_REGS_R3 = 3 ,   HEX_REG_GENERAL_SUB_REGS_R4 = 4 , HEX_REG_GENERAL_SUB_REGS_R5 = 5 , HEX_REG_GENERAL_SUB_REGS_R6 = 6 , HEX_REG_GENERAL_SUB_REGS_R7 = 7 ,   HEX_REG_GENERAL_SUB_REGS_R16 = 16 , HEX_REG_GENERAL_SUB_REGS_R17 = 17 , HEX_REG_GENERAL_SUB_REGS_R18 = 18 , HEX_REG_GENERAL_SUB_REGS_R19 = 19 ,   HEX_REG_GENERAL_SUB_REGS_R20 = 20 , HEX_REG_GENERAL_SUB_REGS_R21 = 21 , HEX_REG_GENERAL_SUB_REGS_R22 = 22 , HEX_REG_GENERAL_SUB_REGS_R23 = 23 }
enum	HEX_GUEST_REGS {   HEX_REG_GUEST_REGS_G0 = 0 , HEX_REG_GUEST_REGS_G1 = 1 , HEX_REG_GUEST_REGS_G2 = 2 , HEX_REG_GUEST_REGS_G3 = 3 ,   HEX_REG_GUEST_REGS_G4 = 4 , HEX_REG_GUEST_REGS_G5 = 5 , HEX_REG_GUEST_REGS_G6 = 6 , HEX_REG_GUEST_REGS_G7 = 7 ,   HEX_REG_GUEST_REGS_G8 = 8 , HEX_REG_GUEST_REGS_G9 = 9 , HEX_REG_GUEST_REGS_G10 = 10 , HEX_REG_GUEST_REGS_G11 = 11 ,   HEX_REG_GUEST_REGS_G12 = 12 , HEX_REG_GUEST_REGS_G13 = 13 , HEX_REG_GUEST_REGS_G14 = 14 , HEX_REG_GUEST_REGS_G15 = 15 ,   HEX_REG_GUEST_REGS_G16 = 16 , HEX_REG_GUEST_REGS_G17 = 17 , HEX_REG_GUEST_REGS_G18 = 18 , HEX_REG_GUEST_REGS_G19 = 19 ,   HEX_REG_GUEST_REGS_G20 = 20 , HEX_REG_GUEST_REGS_G21 = 21 , HEX_REG_GUEST_REGS_G22 = 22 , HEX_REG_GUEST_REGS_G23 = 23 ,   HEX_REG_GUEST_REGS_G24 = 24 , HEX_REG_GUEST_REGS_G25 = 25 , HEX_REG_GUEST_REGS_G26 = 26 , HEX_REG_GUEST_REGS_G27 = 27 ,   HEX_REG_GUEST_REGS_G28 = 28 , HEX_REG_GUEST_REGS_G29 = 29 , HEX_REG_GUEST_REGS_G30 = 30 , HEX_REG_GUEST_REGS_G31 = 31 }
enum	HEX_GUEST_REGS64 {   HEX_REG_GUEST_REGS64_G1_0 = 0 , HEX_REG_GUEST_REGS64_G3_2 = 2 , HEX_REG_GUEST_REGS64_G5_4 = 4 , HEX_REG_GUEST_REGS64_G7_6 = 6 ,   HEX_REG_GUEST_REGS64_G9_8 = 8 , HEX_REG_GUEST_REGS64_G11_10 = 10 , HEX_REG_GUEST_REGS64_G13_12 = 12 , HEX_REG_GUEST_REGS64_G15_14 = 14 ,   HEX_REG_GUEST_REGS64_G17_16 = 16 , HEX_REG_GUEST_REGS64_G19_18 = 18 , HEX_REG_GUEST_REGS64_G21_20 = 20 , HEX_REG_GUEST_REGS64_G23_22 = 22 ,   HEX_REG_GUEST_REGS64_G25_24 = 24 , HEX_REG_GUEST_REGS64_G27_26 = 26 , HEX_REG_GUEST_REGS64_G29_28 = 28 , HEX_REG_GUEST_REGS64_G31_30 = 30 }
enum	HEX_HVX_QR { HEX_REG_HVX_QR_Q0 = 0 , HEX_REG_HVX_QR_Q1 = 1 , HEX_REG_HVX_QR_Q2 = 2 , HEX_REG_HVX_QR_Q3 = 3 }
enum	HEX_HVX_VQR {   HEX_REG_HVX_VQR_V3_0 = 0 , HEX_REG_HVX_VQR_V7_4 = 4 , HEX_REG_HVX_VQR_V11_8 = 8 , HEX_REG_HVX_VQR_V15_12 = 12 ,   HEX_REG_HVX_VQR_V19_16 = 16 , HEX_REG_HVX_VQR_V23_20 = 20 , HEX_REG_HVX_VQR_V27_24 = 24 , HEX_REG_HVX_VQR_V31_28 = 28 }
enum	HEX_HVX_VR {   HEX_REG_HVX_VR_V0 = 0 , HEX_REG_HVX_VR_V1 = 1 , HEX_REG_HVX_VR_V2 = 2 , HEX_REG_HVX_VR_V3 = 3 ,   HEX_REG_HVX_VR_V4 = 4 , HEX_REG_HVX_VR_V5 = 5 , HEX_REG_HVX_VR_V6 = 6 , HEX_REG_HVX_VR_V7 = 7 ,   HEX_REG_HVX_VR_V8 = 8 , HEX_REG_HVX_VR_V9 = 9 , HEX_REG_HVX_VR_V10 = 10 , HEX_REG_HVX_VR_V11 = 11 ,   HEX_REG_HVX_VR_V12 = 12 , HEX_REG_HVX_VR_V13 = 13 , HEX_REG_HVX_VR_V14 = 14 , HEX_REG_HVX_VR_V15 = 15 ,   HEX_REG_HVX_VR_V16 = 16 , HEX_REG_HVX_VR_V17 = 17 , HEX_REG_HVX_VR_V18 = 18 , HEX_REG_HVX_VR_V19 = 19 ,   HEX_REG_HVX_VR_V20 = 20 , HEX_REG_HVX_VR_V21 = 21 , HEX_REG_HVX_VR_V22 = 22 , HEX_REG_HVX_VR_V23 = 23 ,   HEX_REG_HVX_VR_V24 = 24 , HEX_REG_HVX_VR_V25 = 25 , HEX_REG_HVX_VR_V26 = 26 , HEX_REG_HVX_VR_V27 = 27 ,   HEX_REG_HVX_VR_V28 = 28 , HEX_REG_HVX_VR_V29 = 29 , HEX_REG_HVX_VR_V30 = 30 , HEX_REG_HVX_VR_V31 = 31 }
enum	HEX_HVX_WR {   HEX_REG_HVX_WR_V1_0 = 0 , HEX_REG_HVX_WR_V3_2 = 2 , HEX_REG_HVX_WR_V5_4 = 4 , HEX_REG_HVX_WR_V7_6 = 6 ,   HEX_REG_HVX_WR_V9_8 = 8 , HEX_REG_HVX_WR_V11_10 = 10 , HEX_REG_HVX_WR_V13_12 = 12 , HEX_REG_HVX_WR_V15_14 = 14 ,   HEX_REG_HVX_WR_V17_16 = 16 , HEX_REG_HVX_WR_V19_18 = 18 , HEX_REG_HVX_WR_V21_20 = 20 , HEX_REG_HVX_WR_V23_22 = 22 ,   HEX_REG_HVX_WR_V25_24 = 24 , HEX_REG_HVX_WR_V27_26 = 26 , HEX_REG_HVX_WR_V29_28 = 28 , HEX_REG_HVX_WR_V31_30 = 30 }
enum	HEX_INT_REGS {   HEX_REG_INT_REGS_R0 = 0 , HEX_REG_INT_REGS_R1 = 1 , HEX_REG_INT_REGS_R2 = 2 , HEX_REG_INT_REGS_R3 = 3 ,   HEX_REG_INT_REGS_R4 = 4 , HEX_REG_INT_REGS_R5 = 5 , HEX_REG_INT_REGS_R6 = 6 , HEX_REG_INT_REGS_R7 = 7 ,   HEX_REG_INT_REGS_R8 = 8 , HEX_REG_INT_REGS_R9 = 9 , HEX_REG_INT_REGS_R10 = 10 , HEX_REG_INT_REGS_R11 = 11 ,   HEX_REG_INT_REGS_R12 = 12 , HEX_REG_INT_REGS_R13 = 13 , HEX_REG_INT_REGS_R14 = 14 , HEX_REG_INT_REGS_R15 = 15 ,   HEX_REG_INT_REGS_R16 = 16 , HEX_REG_INT_REGS_R17 = 17 , HEX_REG_INT_REGS_R18 = 18 , HEX_REG_INT_REGS_R19 = 19 ,   HEX_REG_INT_REGS_R20 = 20 , HEX_REG_INT_REGS_R21 = 21 , HEX_REG_INT_REGS_R22 = 22 , HEX_REG_INT_REGS_R23 = 23 ,   HEX_REG_INT_REGS_R24 = 24 , HEX_REG_INT_REGS_R25 = 25 , HEX_REG_INT_REGS_R26 = 26 , HEX_REG_INT_REGS_R27 = 27 ,   HEX_REG_INT_REGS_R28 = 28 , HEX_REG_INT_REGS_R29 = 29 , HEX_REG_INT_REGS_R30 = 30 , HEX_REG_INT_REGS_R31 = 31 }
enum	HEX_INT_REGS_LOW8 {   HEX_REG_INT_REGS_LOW8_R0 = 0 , HEX_REG_INT_REGS_LOW8_R1 = 1 , HEX_REG_INT_REGS_LOW8_R2 = 2 , HEX_REG_INT_REGS_LOW8_R3 = 3 ,   HEX_REG_INT_REGS_LOW8_R4 = 4 , HEX_REG_INT_REGS_LOW8_R5 = 5 , HEX_REG_INT_REGS_LOW8_R6 = 6 , HEX_REG_INT_REGS_LOW8_R7 = 7 }
enum	HEX_MOD_REGS { HEX_REG_MOD_REGS_C6 = 6 , HEX_REG_MOD_REGS_C7 = 7 }
enum	HEX_PRED_REGS { HEX_REG_PRED_REGS_P0 = 0 , HEX_REG_PRED_REGS_P1 = 1 , HEX_REG_PRED_REGS_P2 = 2 , HEX_REG_PRED_REGS_P3 = 3 }
enum	HEX_SYS_REGS {   HEX_REG_SYS_REGS_S0 = 0 , HEX_REG_SYS_REGS_S1 = 1 , HEX_REG_SYS_REGS_S2 = 2 , HEX_REG_SYS_REGS_S3 = 3 ,   HEX_REG_SYS_REGS_S4 = 4 , HEX_REG_SYS_REGS_S5 = 5 , HEX_REG_SYS_REGS_S6 = 6 , HEX_REG_SYS_REGS_S7 = 7 ,   HEX_REG_SYS_REGS_S8 = 8 , HEX_REG_SYS_REGS_S9 = 9 , HEX_REG_SYS_REGS_S10 = 10 , HEX_REG_SYS_REGS_S11 = 11 ,   HEX_REG_SYS_REGS_S12 = 12 , HEX_REG_SYS_REGS_S13 = 13 , HEX_REG_SYS_REGS_S14 = 14 , HEX_REG_SYS_REGS_S15 = 15 ,   HEX_REG_SYS_REGS_S16 = 16 , HEX_REG_SYS_REGS_S17 = 17 , HEX_REG_SYS_REGS_S18 = 18 , HEX_REG_SYS_REGS_S19 = 19 ,   HEX_REG_SYS_REGS_S20 = 20 , HEX_REG_SYS_REGS_S21 = 21 , HEX_REG_SYS_REGS_S22 = 22 , HEX_REG_SYS_REGS_S23 = 23 ,   HEX_REG_SYS_REGS_S24 = 24 , HEX_REG_SYS_REGS_S25 = 25 , HEX_REG_SYS_REGS_S26 = 26 , HEX_REG_SYS_REGS_S27 = 27 ,   HEX_REG_SYS_REGS_S28 = 28 , HEX_REG_SYS_REGS_S29 = 29 , HEX_REG_SYS_REGS_S30 = 30 , HEX_REG_SYS_REGS_S31 = 31 ,   HEX_REG_SYS_REGS_S32 = 32 , HEX_REG_SYS_REGS_S33 = 33 , HEX_REG_SYS_REGS_S34 = 34 , HEX_REG_SYS_REGS_S35 = 35 ,   HEX_REG_SYS_REGS_S36 = 36 , HEX_REG_SYS_REGS_S37 = 37 , HEX_REG_SYS_REGS_S38 = 38 , HEX_REG_SYS_REGS_S39 = 39 ,   HEX_REG_SYS_REGS_S40 = 40 , HEX_REG_SYS_REGS_S41 = 41 , HEX_REG_SYS_REGS_S42 = 42 , HEX_REG_SYS_REGS_S43 = 43 ,   HEX_REG_SYS_REGS_S44 = 44 , HEX_REG_SYS_REGS_S45 = 45 , HEX_REG_SYS_REGS_S46 = 46 , HEX_REG_SYS_REGS_S47 = 47 ,   HEX_REG_SYS_REGS_S48 = 48 , HEX_REG_SYS_REGS_S49 = 49 , HEX_REG_SYS_REGS_S50 = 50 , HEX_REG_SYS_REGS_S51 = 51 ,   HEX_REG_SYS_REGS_S52 = 52 , HEX_REG_SYS_REGS_S53 = 53 , HEX_REG_SYS_REGS_S54 = 54 , HEX_REG_SYS_REGS_S55 = 55 ,   HEX_REG_SYS_REGS_S56 = 56 , HEX_REG_SYS_REGS_S57 = 57 , HEX_REG_SYS_REGS_S58 = 58 , HEX_REG_SYS_REGS_S59 = 59 ,   HEX_REG_SYS_REGS_S60 = 60 , HEX_REG_SYS_REGS_S61 = 61 , HEX_REG_SYS_REGS_S62 = 62 , HEX_REG_SYS_REGS_S63 = 63 ,   HEX_REG_SYS_REGS_S64 = 64 , HEX_REG_SYS_REGS_S65 = 65 , HEX_REG_SYS_REGS_S66 = 66 , HEX_REG_SYS_REGS_S67 = 67 ,   HEX_REG_SYS_REGS_S68 = 68 , HEX_REG_SYS_REGS_S69 = 69 , HEX_REG_SYS_REGS_S70 = 70 , HEX_REG_SYS_REGS_S71 = 71 ,   HEX_REG_SYS_REGS_S72 = 72 , HEX_REG_SYS_REGS_S73 = 73 , HEX_REG_SYS_REGS_S74 = 74 , HEX_REG_SYS_REGS_S75 = 75 ,   HEX_REG_SYS_REGS_S76 = 76 , HEX_REG_SYS_REGS_S77 = 77 , HEX_REG_SYS_REGS_S78 = 78 , HEX_REG_SYS_REGS_S79 = 79 ,   HEX_REG_SYS_REGS_S80 = 80 }
enum	HEX_SYS_REGS64 {   HEX_REG_SYS_REGS64_S1_0 = 0 , HEX_REG_SYS_REGS64_S3_2 = 2 , HEX_REG_SYS_REGS64_S5_4 = 4 , HEX_REG_SYS_REGS64_S7_6 = 6 ,   HEX_REG_SYS_REGS64_S9_8 = 8 , HEX_REG_SYS_REGS64_S11_10 = 10 , HEX_REG_SYS_REGS64_S13_12 = 12 , HEX_REG_SYS_REGS64_S15_14 = 14 ,   HEX_REG_SYS_REGS64_S17_16 = 16 , HEX_REG_SYS_REGS64_S19_18 = 18 , HEX_REG_SYS_REGS64_S21_20 = 20 , HEX_REG_SYS_REGS64_S23_22 = 22 ,   HEX_REG_SYS_REGS64_S25_24 = 24 , HEX_REG_SYS_REGS64_S27_26 = 26 , HEX_REG_SYS_REGS64_S29_28 = 28 , HEX_REG_SYS_REGS64_S31_30 = 30 ,   HEX_REG_SYS_REGS64_S33_32 = 32 , HEX_REG_SYS_REGS64_S35_34 = 34 , HEX_REG_SYS_REGS64_S37_36 = 36 , HEX_REG_SYS_REGS64_S39_38 = 38 ,   HEX_REG_SYS_REGS64_S41_40 = 40 , HEX_REG_SYS_REGS64_S43_42 = 42 , HEX_REG_SYS_REGS64_S45_44 = 44 , HEX_REG_SYS_REGS64_S47_46 = 46 ,   HEX_REG_SYS_REGS64_S49_48 = 48 , HEX_REG_SYS_REGS64_S51_50 = 50 , HEX_REG_SYS_REGS64_S53_52 = 52 , HEX_REG_SYS_REGS64_S55_54 = 54 ,   HEX_REG_SYS_REGS64_S57_56 = 56 , HEX_REG_SYS_REGS64_S59_58 = 58 , HEX_REG_SYS_REGS64_S61_60 = 60 , HEX_REG_SYS_REGS64_S63_62 = 62 ,   HEX_REG_SYS_REGS64_S65_64 = 64 , HEX_REG_SYS_REGS64_S67_66 = 66 , HEX_REG_SYS_REGS64_S69_68 = 68 , HEX_REG_SYS_REGS64_S71_70 = 70 ,   HEX_REG_SYS_REGS64_S73_72 = 72 , HEX_REG_SYS_REGS64_S75_74 = 74 , HEX_REG_SYS_REGS64_S77_76 = 76 , HEX_REG_SYS_REGS64_S79_78 = 78 }

Functions
char *	hex_get_ctr_regs (int opcode_reg, bool get_alias)
char *	hex_get_ctr_regs64 (int opcode_reg, bool get_alias)
char *	hex_get_double_regs (int opcode_reg, bool get_alias)
char *	hex_get_general_double_low8_regs (int opcode_reg, bool get_alias)
char *	hex_get_general_sub_regs (int opcode_reg, bool get_alias)
char *	hex_get_guest_regs (int opcode_reg, bool get_alias)
char *	hex_get_guest_regs64 (int opcode_reg, bool get_alias)
char *	hex_get_hvx_qr (int opcode_reg, bool get_alias)
char *	hex_get_hvx_vqr (int opcode_reg, bool get_alias)
char *	hex_get_hvx_vr (int opcode_reg, bool get_alias)
char *	hex_get_hvx_wr (int opcode_reg, bool get_alias)
char *	hex_get_int_regs (int opcode_reg, bool get_alias)
char *	hex_get_int_regs_low8 (int opcode_reg, bool get_alias)
char *	hex_get_mod_regs (int opcode_reg, bool get_alias)
char *	hex_get_pred_regs (int opcode_reg, bool get_alias)
char *	hex_get_sys_regs (int opcode_reg, bool get_alias)
char *	hex_get_sys_regs64 (int opcode_reg, bool get_alias)
char *	hex_get_reg_in_class (HexRegClass cls, int opcode_reg, bool get_alias)
RZ_API RZ_BORROW RzConfig *	hexagon_get_config ()
RZ_API void	hex_extend_op (HexState *state, RZ_INOUT HexOp *op, const bool set_new_extender, const ut32 addr)
	Applies the constant extender to the immediate value in op. More...
int	resolve_n_register (const int reg_num, const ut32 addr, const HexPkt *p)
	Resolves the 3 bit value of an Nt.new reg to the general register of the producer. More...
int	hexagon_disasm_instruction (HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, HexPkt *pkt)
void	hexagon_disasm_0x0 (HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt)
void	hexagon_disasm_0x1 (HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt)
void	hexagon_disasm_0x2 (HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt)
void	hexagon_disasm_0x3 (HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt)
void	hexagon_disasm_0x4 (HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt)
void	hexagon_disasm_0x5 (HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt)
void	hexagon_disasm_0x6 (HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt)
void	hexagon_disasm_0x7 (HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt)
void	hexagon_disasm_0x8 (HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt)
void	hexagon_disasm_0x9 (HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt)
void	hexagon_disasm_0xa (HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt)
void	hexagon_disasm_0xb (HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt)
void	hexagon_disasm_0xc (HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt)
void	hexagon_disasm_0xd (HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt)
void	hexagon_disasm_0xe (HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt)
void	hexagon_disasm_duplex_0x0 (HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt)
void	hexagon_disasm_duplex_0x1 (HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt)
void	hexagon_disasm_duplex_0x2 (HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt)
void	hexagon_disasm_duplex_0x3 (HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt)
void	hexagon_disasm_duplex_0x4 (HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt)
void	hexagon_disasm_duplex_0x5 (HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt)
void	hexagon_disasm_duplex_0x6 (HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt)
void	hexagon_disasm_duplex_0x7 (HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt)
void	hexagon_disasm_duplex_0x8 (HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt)
void	hexagon_disasm_duplex_0x9 (HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt)
void	hexagon_disasm_duplex_0xa (HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt)
void	hexagon_disasm_duplex_0xb (HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt)
void	hexagon_disasm_duplex_0xc (HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt)
void	hexagon_disasm_duplex_0xd (HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt)
void	hexagon_disasm_duplex_0xe (HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt)

Macro Definition Documentation

BF_GET

#define BF_GET	(		y,
			start,
			len
	)		(((y) >> (start)) & BIT_MASK(len))

Definition at line 564 of file hexagon.h.

BF_GETB

#define BF_GETB	(		y,
			start,
			end
	)		(BF_GET((y), (start), (end) - (start) + 1)

Definition at line 565 of file hexagon.h.

BF_MASK

#define BF_MASK	(		start,
			len
	)		(BIT_MASK(len) << (start))

Definition at line 562 of file hexagon.h.

BF_PREP

#define BF_PREP	(		x,
			start,
			len
	)		(((x)&BIT_MASK(len)) << (start))

Definition at line 563 of file hexagon.h.

BIT_MASK

#define BIT_MASK

(

len

)

(BIT(len) - 1)

Definition at line 561 of file hexagon.h.

HEX_MAX_OPERANDS

#define HEX_MAX_OPERANDS   6

Definition at line 21 of file hexagon.h.

HEX_PARSE_BITS_MASK

#define HEX_PARSE_BITS_MASK   0xc000

Definition at line 22 of file hexagon.h.

HEXAGON_STATE_PKTS

#define HEXAGON_STATE_PKTS   8

Definition at line 25 of file hexagon.h.

MAX_CONST_EXT

#define MAX_CONST_EXT   512

Definition at line 24 of file hexagon.h.

Enumeration Type Documentation

HEX_CTR_REGS

enum HEX_CTR_REGS

Enumerator
HEX_REG_CTR_REGS_C0
HEX_REG_CTR_REGS_C1
HEX_REG_CTR_REGS_C2
HEX_REG_CTR_REGS_C3
HEX_REG_CTR_REGS_C4
HEX_REG_CTR_REGS_C5
HEX_REG_CTR_REGS_C6
HEX_REG_CTR_REGS_C7
HEX_REG_CTR_REGS_C8
HEX_REG_CTR_REGS_C9
HEX_REG_CTR_REGS_C10
HEX_REG_CTR_REGS_C11
HEX_REG_CTR_REGS_C12
HEX_REG_CTR_REGS_C13
HEX_REG_CTR_REGS_C14
HEX_REG_CTR_REGS_C15
HEX_REG_CTR_REGS_C16
HEX_REG_CTR_REGS_C17
HEX_REG_CTR_REGS_C18
HEX_REG_CTR_REGS_C19
HEX_REG_CTR_REGS_C30
HEX_REG_CTR_REGS_C31

Definition at line 162 of file hexagon.h.

             {
    HEX_REG_CTR_REGS_C0 = 0, // sa0
    HEX_REG_CTR_REGS_C1 = 1, // lc0
    HEX_REG_CTR_REGS_C2 = 2, // sa1
    HEX_REG_CTR_REGS_C3 = 3, // lc1
    HEX_REG_CTR_REGS_C4 = 4, // p3:0
    HEX_REG_CTR_REGS_C5 = 5, // c5
    HEX_REG_CTR_REGS_C6 = 6, // m0
    HEX_REG_CTR_REGS_C7 = 7, // m1
    HEX_REG_CTR_REGS_C8 = 8, // usr
    HEX_REG_CTR_REGS_C9 = 9, // pc
    HEX_REG_CTR_REGS_C10 = 10, // ugp
    HEX_REG_CTR_REGS_C11 = 11, // gp
    HEX_REG_CTR_REGS_C12 = 12, // cs0
    HEX_REG_CTR_REGS_C13 = 13, // cs1
    HEX_REG_CTR_REGS_C14 = 14, // upcyclelo
    HEX_REG_CTR_REGS_C15 = 15, // upcyclehi
    HEX_REG_CTR_REGS_C16 = 16, // framelimit
    HEX_REG_CTR_REGS_C17 = 17, // framekey
    HEX_REG_CTR_REGS_C18 = 18, // pktcountlo
    HEX_REG_CTR_REGS_C19 = 19, // pktcounthi
    HEX_REG_CTR_REGS_C30 = 30, // utimerlo
    HEX_REG_CTR_REGS_C31 = 31, // utimerhi
} HEX_CTR_REGS; // CtrRegs

HEX_CTR_REGS64

enum HEX_CTR_REGS64

Enumerator
HEX_REG_CTR_REGS64_C1_0
HEX_REG_CTR_REGS64_C3_2
HEX_REG_CTR_REGS64_C5_4
HEX_REG_CTR_REGS64_C7_6
HEX_REG_CTR_REGS64_C9_8
HEX_REG_CTR_REGS64_C11_10
HEX_REG_CTR_REGS64_C13_12
HEX_REG_CTR_REGS64_C15_14
HEX_REG_CTR_REGS64_C17_16
HEX_REG_CTR_REGS64_C19_18
HEX_REG_CTR_REGS64_C31_30

Definition at line 187 of file hexagon.h.

             {
    HEX_REG_CTR_REGS64_C1_0 = 0, // lc0:sa0
    HEX_REG_CTR_REGS64_C3_2 = 2, // lc1:sa1
    HEX_REG_CTR_REGS64_C5_4 = 4,
    HEX_REG_CTR_REGS64_C7_6 = 6, // m1:0
    HEX_REG_CTR_REGS64_C9_8 = 8,
    HEX_REG_CTR_REGS64_C11_10 = 10,
    HEX_REG_CTR_REGS64_C13_12 = 12, // cs1:0
    HEX_REG_CTR_REGS64_C15_14 = 14, // upcycle
    HEX_REG_CTR_REGS64_C17_16 = 16,
    HEX_REG_CTR_REGS64_C19_18 = 18, // pktcount
    HEX_REG_CTR_REGS64_C31_30 = 30, // utimer
} HEX_CTR_REGS64; // CtrRegs64

HEX_DOUBLE_REGS

enum HEX_DOUBLE_REGS

Enumerator
HEX_REG_DOUBLE_REGS_R1_0
HEX_REG_DOUBLE_REGS_R3_2
HEX_REG_DOUBLE_REGS_R5_4
HEX_REG_DOUBLE_REGS_R7_6
HEX_REG_DOUBLE_REGS_R9_8
HEX_REG_DOUBLE_REGS_R11_10
HEX_REG_DOUBLE_REGS_R13_12
HEX_REG_DOUBLE_REGS_R15_14
HEX_REG_DOUBLE_REGS_R17_16
HEX_REG_DOUBLE_REGS_R19_18
HEX_REG_DOUBLE_REGS_R21_20
HEX_REG_DOUBLE_REGS_R23_22
HEX_REG_DOUBLE_REGS_R25_24
HEX_REG_DOUBLE_REGS_R27_26
HEX_REG_DOUBLE_REGS_R29_28
HEX_REG_DOUBLE_REGS_R31_30

Definition at line 201 of file hexagon.h.

             {
    HEX_REG_DOUBLE_REGS_R1_0 = 0,
    HEX_REG_DOUBLE_REGS_R3_2 = 2,
    HEX_REG_DOUBLE_REGS_R5_4 = 4,
    HEX_REG_DOUBLE_REGS_R7_6 = 6,
    HEX_REG_DOUBLE_REGS_R9_8 = 8,
    HEX_REG_DOUBLE_REGS_R11_10 = 10,
    HEX_REG_DOUBLE_REGS_R13_12 = 12,
    HEX_REG_DOUBLE_REGS_R15_14 = 14,
    HEX_REG_DOUBLE_REGS_R17_16 = 16,
    HEX_REG_DOUBLE_REGS_R19_18 = 18,
    HEX_REG_DOUBLE_REGS_R21_20 = 20,
    HEX_REG_DOUBLE_REGS_R23_22 = 22,
    HEX_REG_DOUBLE_REGS_R25_24 = 24,
    HEX_REG_DOUBLE_REGS_R27_26 = 26,
    HEX_REG_DOUBLE_REGS_R29_28 = 28,
    HEX_REG_DOUBLE_REGS_R31_30 = 30, // lr:fp
} HEX_DOUBLE_REGS; // DoubleRegs

HEX_GENERAL_DOUBLE_LOW8_REGS

enum HEX_GENERAL_DOUBLE_LOW8_REGS

Enumerator
HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R1_0
HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R3_2
HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R5_4
HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R7_6
HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R17_16
HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R19_18
HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R21_20
HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R23_22

Definition at line 220 of file hexagon.h.

             {
    HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R1_0 = 0,
    HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R3_2 = 2,
    HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R5_4 = 4,
    HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R7_6 = 6,
    HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R17_16 = 16,
    HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R19_18 = 18,
    HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R21_20 = 20,
    HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R23_22 = 22,
} HEX_GENERAL_DOUBLE_LOW8_REGS; // GeneralDoubleLow8Regs

HEX_GENERAL_SUB_REGS

enum HEX_GENERAL_SUB_REGS

Enumerator
HEX_REG_GENERAL_SUB_REGS_R0
HEX_REG_GENERAL_SUB_REGS_R1
HEX_REG_GENERAL_SUB_REGS_R2
HEX_REG_GENERAL_SUB_REGS_R3
HEX_REG_GENERAL_SUB_REGS_R4
HEX_REG_GENERAL_SUB_REGS_R5
HEX_REG_GENERAL_SUB_REGS_R6
HEX_REG_GENERAL_SUB_REGS_R7
HEX_REG_GENERAL_SUB_REGS_R16
HEX_REG_GENERAL_SUB_REGS_R17
HEX_REG_GENERAL_SUB_REGS_R18
HEX_REG_GENERAL_SUB_REGS_R19
HEX_REG_GENERAL_SUB_REGS_R20
HEX_REG_GENERAL_SUB_REGS_R21
HEX_REG_GENERAL_SUB_REGS_R22
HEX_REG_GENERAL_SUB_REGS_R23

Definition at line 231 of file hexagon.h.

             {
    HEX_REG_GENERAL_SUB_REGS_R0 = 0,
    HEX_REG_GENERAL_SUB_REGS_R1 = 1,
    HEX_REG_GENERAL_SUB_REGS_R2 = 2,
    HEX_REG_GENERAL_SUB_REGS_R3 = 3,
    HEX_REG_GENERAL_SUB_REGS_R4 = 4,
    HEX_REG_GENERAL_SUB_REGS_R5 = 5,
    HEX_REG_GENERAL_SUB_REGS_R6 = 6,
    HEX_REG_GENERAL_SUB_REGS_R7 = 7,
    HEX_REG_GENERAL_SUB_REGS_R16 = 16,
    HEX_REG_GENERAL_SUB_REGS_R17 = 17,
    HEX_REG_GENERAL_SUB_REGS_R18 = 18,
    HEX_REG_GENERAL_SUB_REGS_R19 = 19,
    HEX_REG_GENERAL_SUB_REGS_R20 = 20,
    HEX_REG_GENERAL_SUB_REGS_R21 = 21,
    HEX_REG_GENERAL_SUB_REGS_R22 = 22,
    HEX_REG_GENERAL_SUB_REGS_R23 = 23,
} HEX_GENERAL_SUB_REGS; // GeneralSubRegs

HEX_GUEST_REGS

enum HEX_GUEST_REGS

Enumerator
HEX_REG_GUEST_REGS_G0
HEX_REG_GUEST_REGS_G1
HEX_REG_GUEST_REGS_G2
HEX_REG_GUEST_REGS_G3
HEX_REG_GUEST_REGS_G4
HEX_REG_GUEST_REGS_G5
HEX_REG_GUEST_REGS_G6
HEX_REG_GUEST_REGS_G7
HEX_REG_GUEST_REGS_G8
HEX_REG_GUEST_REGS_G9
HEX_REG_GUEST_REGS_G10
HEX_REG_GUEST_REGS_G11
HEX_REG_GUEST_REGS_G12
HEX_REG_GUEST_REGS_G13
HEX_REG_GUEST_REGS_G14
HEX_REG_GUEST_REGS_G15
HEX_REG_GUEST_REGS_G16
HEX_REG_GUEST_REGS_G17
HEX_REG_GUEST_REGS_G18
HEX_REG_GUEST_REGS_G19
HEX_REG_GUEST_REGS_G20
HEX_REG_GUEST_REGS_G21
HEX_REG_GUEST_REGS_G22
HEX_REG_GUEST_REGS_G23
HEX_REG_GUEST_REGS_G24
HEX_REG_GUEST_REGS_G25
HEX_REG_GUEST_REGS_G26
HEX_REG_GUEST_REGS_G27
HEX_REG_GUEST_REGS_G28
HEX_REG_GUEST_REGS_G29
HEX_REG_GUEST_REGS_G30
HEX_REG_GUEST_REGS_G31

Definition at line 250 of file hexagon.h.

             {
    HEX_REG_GUEST_REGS_G0 = 0, // gelr
    HEX_REG_GUEST_REGS_G1 = 1, // gsr
    HEX_REG_GUEST_REGS_G2 = 2, // gosp
    HEX_REG_GUEST_REGS_G3 = 3, // gbadva
    HEX_REG_GUEST_REGS_G4 = 4,
    HEX_REG_GUEST_REGS_G5 = 5,
    HEX_REG_GUEST_REGS_G6 = 6,
    HEX_REG_GUEST_REGS_G7 = 7,
    HEX_REG_GUEST_REGS_G8 = 8,
    HEX_REG_GUEST_REGS_G9 = 9,
    HEX_REG_GUEST_REGS_G10 = 10,
    HEX_REG_GUEST_REGS_G11 = 11,
    HEX_REG_GUEST_REGS_G12 = 12,
    HEX_REG_GUEST_REGS_G13 = 13,
    HEX_REG_GUEST_REGS_G14 = 14,
    HEX_REG_GUEST_REGS_G15 = 15,
    HEX_REG_GUEST_REGS_G16 = 16, // gpmucnt4
    HEX_REG_GUEST_REGS_G17 = 17, // gpmucnt5
    HEX_REG_GUEST_REGS_G18 = 18, // gpmucnt6
    HEX_REG_GUEST_REGS_G19 = 19, // gpmucnt7
    HEX_REG_GUEST_REGS_G20 = 20,
    HEX_REG_GUEST_REGS_G21 = 21,
    HEX_REG_GUEST_REGS_G22 = 22,
    HEX_REG_GUEST_REGS_G23 = 23,
    HEX_REG_GUEST_REGS_G24 = 24, // gpcyclelo
    HEX_REG_GUEST_REGS_G25 = 25, // gpcyclehi
    HEX_REG_GUEST_REGS_G26 = 26, // gpmucnt0
    HEX_REG_GUEST_REGS_G27 = 27, // gpmucnt1
    HEX_REG_GUEST_REGS_G28 = 28, // gpmucnt2
    HEX_REG_GUEST_REGS_G29 = 29, // gpmucnt3
    HEX_REG_GUEST_REGS_G30 = 30,
    HEX_REG_GUEST_REGS_G31 = 31,
} HEX_GUEST_REGS; // GuestRegs

HEX_GUEST_REGS64

enum HEX_GUEST_REGS64

Enumerator
HEX_REG_GUEST_REGS64_G1_0
HEX_REG_GUEST_REGS64_G3_2
HEX_REG_GUEST_REGS64_G5_4
HEX_REG_GUEST_REGS64_G7_6
HEX_REG_GUEST_REGS64_G9_8
HEX_REG_GUEST_REGS64_G11_10
HEX_REG_GUEST_REGS64_G13_12
HEX_REG_GUEST_REGS64_G15_14
HEX_REG_GUEST_REGS64_G17_16
HEX_REG_GUEST_REGS64_G19_18
HEX_REG_GUEST_REGS64_G21_20
HEX_REG_GUEST_REGS64_G23_22
HEX_REG_GUEST_REGS64_G25_24
HEX_REG_GUEST_REGS64_G27_26
HEX_REG_GUEST_REGS64_G29_28
HEX_REG_GUEST_REGS64_G31_30

Definition at line 285 of file hexagon.h.

             {
    HEX_REG_GUEST_REGS64_G1_0 = 0,
    HEX_REG_GUEST_REGS64_G3_2 = 2,
    HEX_REG_GUEST_REGS64_G5_4 = 4,
    HEX_REG_GUEST_REGS64_G7_6 = 6,
    HEX_REG_GUEST_REGS64_G9_8 = 8,
    HEX_REG_GUEST_REGS64_G11_10 = 10,
    HEX_REG_GUEST_REGS64_G13_12 = 12,
    HEX_REG_GUEST_REGS64_G15_14 = 14,
    HEX_REG_GUEST_REGS64_G17_16 = 16,
    HEX_REG_GUEST_REGS64_G19_18 = 18,
    HEX_REG_GUEST_REGS64_G21_20 = 20,
    HEX_REG_GUEST_REGS64_G23_22 = 22,
    HEX_REG_GUEST_REGS64_G25_24 = 24,
    HEX_REG_GUEST_REGS64_G27_26 = 26,
    HEX_REG_GUEST_REGS64_G29_28 = 28,
    HEX_REG_GUEST_REGS64_G31_30 = 30,
} HEX_GUEST_REGS64; // GuestRegs64

HEX_HVX_QR

enum HEX_HVX_QR

Enumerator
HEX_REG_HVX_QR_Q0
HEX_REG_HVX_QR_Q1
HEX_REG_HVX_QR_Q2
HEX_REG_HVX_QR_Q3

Definition at line 304 of file hexagon.h.

             {
    HEX_REG_HVX_QR_Q0 = 0,
    HEX_REG_HVX_QR_Q1 = 1,
    HEX_REG_HVX_QR_Q2 = 2,
    HEX_REG_HVX_QR_Q3 = 3,
} HEX_HVX_QR; // HvxQR

HEX_HVX_VQR

enum HEX_HVX_VQR

Enumerator
HEX_REG_HVX_VQR_V3_0
HEX_REG_HVX_VQR_V7_4
HEX_REG_HVX_VQR_V11_8
HEX_REG_HVX_VQR_V15_12
HEX_REG_HVX_VQR_V19_16
HEX_REG_HVX_VQR_V23_20
HEX_REG_HVX_VQR_V27_24
HEX_REG_HVX_VQR_V31_28

Definition at line 311 of file hexagon.h.

             {
    HEX_REG_HVX_VQR_V3_0 = 0,
    HEX_REG_HVX_VQR_V7_4 = 4,
    HEX_REG_HVX_VQR_V11_8 = 8,
    HEX_REG_HVX_VQR_V15_12 = 12,
    HEX_REG_HVX_VQR_V19_16 = 16,
    HEX_REG_HVX_VQR_V23_20 = 20,
    HEX_REG_HVX_VQR_V27_24 = 24,
    HEX_REG_HVX_VQR_V31_28 = 28,
} HEX_HVX_VQR; // HvxVQR

HEX_HVX_VR

enum HEX_HVX_VR

Enumerator
HEX_REG_HVX_VR_V0
HEX_REG_HVX_VR_V1
HEX_REG_HVX_VR_V2
HEX_REG_HVX_VR_V3
HEX_REG_HVX_VR_V4
HEX_REG_HVX_VR_V5
HEX_REG_HVX_VR_V6
HEX_REG_HVX_VR_V7
HEX_REG_HVX_VR_V8
HEX_REG_HVX_VR_V9
HEX_REG_HVX_VR_V10
HEX_REG_HVX_VR_V11
HEX_REG_HVX_VR_V12
HEX_REG_HVX_VR_V13
HEX_REG_HVX_VR_V14
HEX_REG_HVX_VR_V15
HEX_REG_HVX_VR_V16
HEX_REG_HVX_VR_V17
HEX_REG_HVX_VR_V18
HEX_REG_HVX_VR_V19
HEX_REG_HVX_VR_V20
HEX_REG_HVX_VR_V21
HEX_REG_HVX_VR_V22
HEX_REG_HVX_VR_V23
HEX_REG_HVX_VR_V24
HEX_REG_HVX_VR_V25
HEX_REG_HVX_VR_V26
HEX_REG_HVX_VR_V27
HEX_REG_HVX_VR_V28
HEX_REG_HVX_VR_V29
HEX_REG_HVX_VR_V30
HEX_REG_HVX_VR_V31

Definition at line 322 of file hexagon.h.

             {
    HEX_REG_HVX_VR_V0 = 0,
    HEX_REG_HVX_VR_V1 = 1,
    HEX_REG_HVX_VR_V2 = 2,
    HEX_REG_HVX_VR_V3 = 3,
    HEX_REG_HVX_VR_V4 = 4,
    HEX_REG_HVX_VR_V5 = 5,
    HEX_REG_HVX_VR_V6 = 6,
    HEX_REG_HVX_VR_V7 = 7,
    HEX_REG_HVX_VR_V8 = 8,
    HEX_REG_HVX_VR_V9 = 9,
    HEX_REG_HVX_VR_V10 = 10,
    HEX_REG_HVX_VR_V11 = 11,
    HEX_REG_HVX_VR_V12 = 12,
    HEX_REG_HVX_VR_V13 = 13,
    HEX_REG_HVX_VR_V14 = 14,
    HEX_REG_HVX_VR_V15 = 15,
    HEX_REG_HVX_VR_V16 = 16,
    HEX_REG_HVX_VR_V17 = 17,
    HEX_REG_HVX_VR_V18 = 18,
    HEX_REG_HVX_VR_V19 = 19,
    HEX_REG_HVX_VR_V20 = 20,
    HEX_REG_HVX_VR_V21 = 21,
    HEX_REG_HVX_VR_V22 = 22,
    HEX_REG_HVX_VR_V23 = 23,
    HEX_REG_HVX_VR_V24 = 24,
    HEX_REG_HVX_VR_V25 = 25,
    HEX_REG_HVX_VR_V26 = 26,
    HEX_REG_HVX_VR_V27 = 27,
    HEX_REG_HVX_VR_V28 = 28,
    HEX_REG_HVX_VR_V29 = 29,
    HEX_REG_HVX_VR_V30 = 30,
    HEX_REG_HVX_VR_V31 = 31,
} HEX_HVX_VR; // HvxVR

HEX_HVX_WR

enum HEX_HVX_WR

Enumerator
HEX_REG_HVX_WR_V1_0
HEX_REG_HVX_WR_V3_2
HEX_REG_HVX_WR_V5_4
HEX_REG_HVX_WR_V7_6
HEX_REG_HVX_WR_V9_8
HEX_REG_HVX_WR_V11_10
HEX_REG_HVX_WR_V13_12
HEX_REG_HVX_WR_V15_14
HEX_REG_HVX_WR_V17_16
HEX_REG_HVX_WR_V19_18
HEX_REG_HVX_WR_V21_20
HEX_REG_HVX_WR_V23_22
HEX_REG_HVX_WR_V25_24
HEX_REG_HVX_WR_V27_26
HEX_REG_HVX_WR_V29_28
HEX_REG_HVX_WR_V31_30

Definition at line 357 of file hexagon.h.

             {
    HEX_REG_HVX_WR_V1_0 = 0,
    HEX_REG_HVX_WR_V3_2 = 2,
    HEX_REG_HVX_WR_V5_4 = 4,
    HEX_REG_HVX_WR_V7_6 = 6,
    HEX_REG_HVX_WR_V9_8 = 8,
    HEX_REG_HVX_WR_V11_10 = 10,
    HEX_REG_HVX_WR_V13_12 = 12,
    HEX_REG_HVX_WR_V15_14 = 14,
    HEX_REG_HVX_WR_V17_16 = 16,
    HEX_REG_HVX_WR_V19_18 = 18,
    HEX_REG_HVX_WR_V21_20 = 20,
    HEX_REG_HVX_WR_V23_22 = 22,
    HEX_REG_HVX_WR_V25_24 = 24,
    HEX_REG_HVX_WR_V27_26 = 26,
    HEX_REG_HVX_WR_V29_28 = 28,
    HEX_REG_HVX_WR_V31_30 = 30,
} HEX_HVX_WR; // HvxWR

HEX_INT_REGS

enum HEX_INT_REGS

Enumerator
HEX_REG_INT_REGS_R0
HEX_REG_INT_REGS_R1
HEX_REG_INT_REGS_R2
HEX_REG_INT_REGS_R3
HEX_REG_INT_REGS_R4
HEX_REG_INT_REGS_R5
HEX_REG_INT_REGS_R6
HEX_REG_INT_REGS_R7
HEX_REG_INT_REGS_R8
HEX_REG_INT_REGS_R9
HEX_REG_INT_REGS_R10
HEX_REG_INT_REGS_R11
HEX_REG_INT_REGS_R12
HEX_REG_INT_REGS_R13
HEX_REG_INT_REGS_R14
HEX_REG_INT_REGS_R15
HEX_REG_INT_REGS_R16
HEX_REG_INT_REGS_R17
HEX_REG_INT_REGS_R18
HEX_REG_INT_REGS_R19
HEX_REG_INT_REGS_R20
HEX_REG_INT_REGS_R21
HEX_REG_INT_REGS_R22
HEX_REG_INT_REGS_R23
HEX_REG_INT_REGS_R24
HEX_REG_INT_REGS_R25
HEX_REG_INT_REGS_R26
HEX_REG_INT_REGS_R27
HEX_REG_INT_REGS_R28
HEX_REG_INT_REGS_R29
HEX_REG_INT_REGS_R30
HEX_REG_INT_REGS_R31

Definition at line 376 of file hexagon.h.

             {
    HEX_REG_INT_REGS_R0 = 0,
    HEX_REG_INT_REGS_R1 = 1,
    HEX_REG_INT_REGS_R2 = 2,
    HEX_REG_INT_REGS_R3 = 3,
    HEX_REG_INT_REGS_R4 = 4,
    HEX_REG_INT_REGS_R5 = 5,
    HEX_REG_INT_REGS_R6 = 6,
    HEX_REG_INT_REGS_R7 = 7,
    HEX_REG_INT_REGS_R8 = 8,
    HEX_REG_INT_REGS_R9 = 9,
    HEX_REG_INT_REGS_R10 = 10,
    HEX_REG_INT_REGS_R11 = 11,
    HEX_REG_INT_REGS_R12 = 12,
    HEX_REG_INT_REGS_R13 = 13,
    HEX_REG_INT_REGS_R14 = 14,
    HEX_REG_INT_REGS_R15 = 15,
    HEX_REG_INT_REGS_R16 = 16,
    HEX_REG_INT_REGS_R17 = 17,
    HEX_REG_INT_REGS_R18 = 18,
    HEX_REG_INT_REGS_R19 = 19,
    HEX_REG_INT_REGS_R20 = 20,
    HEX_REG_INT_REGS_R21 = 21,
    HEX_REG_INT_REGS_R22 = 22,
    HEX_REG_INT_REGS_R23 = 23,
    HEX_REG_INT_REGS_R24 = 24,
    HEX_REG_INT_REGS_R25 = 25,
    HEX_REG_INT_REGS_R26 = 26,
    HEX_REG_INT_REGS_R27 = 27,
    HEX_REG_INT_REGS_R28 = 28,
    HEX_REG_INT_REGS_R29 = 29, // sp
    HEX_REG_INT_REGS_R30 = 30, // fp
    HEX_REG_INT_REGS_R31 = 31, // lr
} HEX_INT_REGS; // IntRegs

HEX_INT_REGS_LOW8

enum HEX_INT_REGS_LOW8

Enumerator
HEX_REG_INT_REGS_LOW8_R0
HEX_REG_INT_REGS_LOW8_R1
HEX_REG_INT_REGS_LOW8_R2
HEX_REG_INT_REGS_LOW8_R3
HEX_REG_INT_REGS_LOW8_R4
HEX_REG_INT_REGS_LOW8_R5
HEX_REG_INT_REGS_LOW8_R6
HEX_REG_INT_REGS_LOW8_R7

Definition at line 411 of file hexagon.h.

             {
    HEX_REG_INT_REGS_LOW8_R0 = 0,
    HEX_REG_INT_REGS_LOW8_R1 = 1,
    HEX_REG_INT_REGS_LOW8_R2 = 2,
    HEX_REG_INT_REGS_LOW8_R3 = 3,
    HEX_REG_INT_REGS_LOW8_R4 = 4,
    HEX_REG_INT_REGS_LOW8_R5 = 5,
    HEX_REG_INT_REGS_LOW8_R6 = 6,
    HEX_REG_INT_REGS_LOW8_R7 = 7,
} HEX_INT_REGS_LOW8; // IntRegsLow8

HEX_MOD_REGS

enum HEX_MOD_REGS

Enumerator
HEX_REG_MOD_REGS_C6
HEX_REG_MOD_REGS_C7

Definition at line 422 of file hexagon.h.

             {
    HEX_REG_MOD_REGS_C6 = 6, // m0
    HEX_REG_MOD_REGS_C7 = 7, // m1
} HEX_MOD_REGS; // ModRegs

HEX_PRED_REGS

enum HEX_PRED_REGS

Enumerator
HEX_REG_PRED_REGS_P0
HEX_REG_PRED_REGS_P1
HEX_REG_PRED_REGS_P2
HEX_REG_PRED_REGS_P3

Definition at line 427 of file hexagon.h.

             {
    HEX_REG_PRED_REGS_P0 = 0,
    HEX_REG_PRED_REGS_P1 = 1,
    HEX_REG_PRED_REGS_P2 = 2,
    HEX_REG_PRED_REGS_P3 = 3,
} HEX_PRED_REGS; // PredRegs

HEX_SYS_REGS

enum HEX_SYS_REGS

Enumerator
HEX_REG_SYS_REGS_S0
HEX_REG_SYS_REGS_S1
HEX_REG_SYS_REGS_S2
HEX_REG_SYS_REGS_S3
HEX_REG_SYS_REGS_S4
HEX_REG_SYS_REGS_S5
HEX_REG_SYS_REGS_S6
HEX_REG_SYS_REGS_S7
HEX_REG_SYS_REGS_S8
HEX_REG_SYS_REGS_S9
HEX_REG_SYS_REGS_S10
HEX_REG_SYS_REGS_S11
HEX_REG_SYS_REGS_S12
HEX_REG_SYS_REGS_S13
HEX_REG_SYS_REGS_S14
HEX_REG_SYS_REGS_S15
HEX_REG_SYS_REGS_S16
HEX_REG_SYS_REGS_S17
HEX_REG_SYS_REGS_S18
HEX_REG_SYS_REGS_S19
HEX_REG_SYS_REGS_S20
HEX_REG_SYS_REGS_S21
HEX_REG_SYS_REGS_S22
HEX_REG_SYS_REGS_S23
HEX_REG_SYS_REGS_S24
HEX_REG_SYS_REGS_S25
HEX_REG_SYS_REGS_S26
HEX_REG_SYS_REGS_S27
HEX_REG_SYS_REGS_S28
HEX_REG_SYS_REGS_S29
HEX_REG_SYS_REGS_S30
HEX_REG_SYS_REGS_S31
HEX_REG_SYS_REGS_S32
HEX_REG_SYS_REGS_S33
HEX_REG_SYS_REGS_S34
HEX_REG_SYS_REGS_S35
HEX_REG_SYS_REGS_S36
HEX_REG_SYS_REGS_S37
HEX_REG_SYS_REGS_S38
HEX_REG_SYS_REGS_S39
HEX_REG_SYS_REGS_S40
HEX_REG_SYS_REGS_S41
HEX_REG_SYS_REGS_S42
HEX_REG_SYS_REGS_S43
HEX_REG_SYS_REGS_S44
HEX_REG_SYS_REGS_S45
HEX_REG_SYS_REGS_S46
HEX_REG_SYS_REGS_S47
HEX_REG_SYS_REGS_S48
HEX_REG_SYS_REGS_S49
HEX_REG_SYS_REGS_S50
HEX_REG_SYS_REGS_S51
HEX_REG_SYS_REGS_S52
HEX_REG_SYS_REGS_S53
HEX_REG_SYS_REGS_S54
HEX_REG_SYS_REGS_S55
HEX_REG_SYS_REGS_S56
HEX_REG_SYS_REGS_S57
HEX_REG_SYS_REGS_S58
HEX_REG_SYS_REGS_S59
HEX_REG_SYS_REGS_S60
HEX_REG_SYS_REGS_S61
HEX_REG_SYS_REGS_S62
HEX_REG_SYS_REGS_S63
HEX_REG_SYS_REGS_S64
HEX_REG_SYS_REGS_S65
HEX_REG_SYS_REGS_S66
HEX_REG_SYS_REGS_S67
HEX_REG_SYS_REGS_S68
HEX_REG_SYS_REGS_S69
HEX_REG_SYS_REGS_S70
HEX_REG_SYS_REGS_S71
HEX_REG_SYS_REGS_S72
HEX_REG_SYS_REGS_S73
HEX_REG_SYS_REGS_S74
HEX_REG_SYS_REGS_S75
HEX_REG_SYS_REGS_S76
HEX_REG_SYS_REGS_S77
HEX_REG_SYS_REGS_S78
HEX_REG_SYS_REGS_S79
HEX_REG_SYS_REGS_S80

Definition at line 434 of file hexagon.h.

             {
    HEX_REG_SYS_REGS_S0 = 0, // sgp0
    HEX_REG_SYS_REGS_S1 = 1, // sgp1
    HEX_REG_SYS_REGS_S2 = 2, // stid
    HEX_REG_SYS_REGS_S3 = 3, // elr
    HEX_REG_SYS_REGS_S4 = 4, // badva0
    HEX_REG_SYS_REGS_S5 = 5, // badva1
    HEX_REG_SYS_REGS_S6 = 6, // ssr
    HEX_REG_SYS_REGS_S7 = 7, // ccr
    HEX_REG_SYS_REGS_S8 = 8, // htid
    HEX_REG_SYS_REGS_S9 = 9, // badva
    HEX_REG_SYS_REGS_S10 = 10, // imask
    HEX_REG_SYS_REGS_S11 = 11,
    HEX_REG_SYS_REGS_S12 = 12,
    HEX_REG_SYS_REGS_S13 = 13,
    HEX_REG_SYS_REGS_S14 = 14,
    HEX_REG_SYS_REGS_S15 = 15,
    HEX_REG_SYS_REGS_S16 = 16, // evb
    HEX_REG_SYS_REGS_S17 = 17, // modectl
    HEX_REG_SYS_REGS_S18 = 18, // syscfg
    HEX_REG_SYS_REGS_S19 = 19, // s19
    HEX_REG_SYS_REGS_S20 = 20, // s20
    HEX_REG_SYS_REGS_S21 = 21, // vid
    HEX_REG_SYS_REGS_S22 = 22, // s22
    HEX_REG_SYS_REGS_S23 = 23,
    HEX_REG_SYS_REGS_S24 = 24,
    HEX_REG_SYS_REGS_S25 = 25,
    HEX_REG_SYS_REGS_S26 = 26,
    HEX_REG_SYS_REGS_S27 = 27, // cfgbase
    HEX_REG_SYS_REGS_S28 = 28, // diag
    HEX_REG_SYS_REGS_S29 = 29, // rev
    HEX_REG_SYS_REGS_S30 = 30, // pcyclelo
    HEX_REG_SYS_REGS_S31 = 31, // pcyclehi
    HEX_REG_SYS_REGS_S32 = 32, // isdbst
    HEX_REG_SYS_REGS_S33 = 33, // isdbcfg0
    HEX_REG_SYS_REGS_S34 = 34, // isdbcfg1
    HEX_REG_SYS_REGS_S35 = 35,
    HEX_REG_SYS_REGS_S36 = 36, // brkptpc0
    HEX_REG_SYS_REGS_S37 = 37, // brkptcfg0
    HEX_REG_SYS_REGS_S38 = 38, // brkptpc1
    HEX_REG_SYS_REGS_S39 = 39, // brkptcfg1
    HEX_REG_SYS_REGS_S40 = 40, // isdbmbxin
    HEX_REG_SYS_REGS_S41 = 41, // isdbmbxout
    HEX_REG_SYS_REGS_S42 = 42, // isdben
    HEX_REG_SYS_REGS_S43 = 43, // isdbgpr
    HEX_REG_SYS_REGS_S44 = 44,
    HEX_REG_SYS_REGS_S45 = 45,
    HEX_REG_SYS_REGS_S46 = 46,
    HEX_REG_SYS_REGS_S47 = 47,
    HEX_REG_SYS_REGS_S48 = 48, // pmucnt0
    HEX_REG_SYS_REGS_S49 = 49, // pmucnt1
    HEX_REG_SYS_REGS_S50 = 50, // pmucnt2
    HEX_REG_SYS_REGS_S51 = 51, // pmucnt3
    HEX_REG_SYS_REGS_S52 = 52, // pmuevtcfg
    HEX_REG_SYS_REGS_S53 = 53, // pmucfg
    HEX_REG_SYS_REGS_S54 = 54,
    HEX_REG_SYS_REGS_S55 = 55,
    HEX_REG_SYS_REGS_S56 = 56,
    HEX_REG_SYS_REGS_S57 = 57,
    HEX_REG_SYS_REGS_S58 = 58,
    HEX_REG_SYS_REGS_S59 = 59,
    HEX_REG_SYS_REGS_S60 = 60,
    HEX_REG_SYS_REGS_S61 = 61,
    HEX_REG_SYS_REGS_S62 = 62,
    HEX_REG_SYS_REGS_S63 = 63,
    HEX_REG_SYS_REGS_S64 = 64,
    HEX_REG_SYS_REGS_S65 = 65,
    HEX_REG_SYS_REGS_S66 = 66,
    HEX_REG_SYS_REGS_S67 = 67,
    HEX_REG_SYS_REGS_S68 = 68,
    HEX_REG_SYS_REGS_S69 = 69,
    HEX_REG_SYS_REGS_S70 = 70,
    HEX_REG_SYS_REGS_S71 = 71,
    HEX_REG_SYS_REGS_S72 = 72,
    HEX_REG_SYS_REGS_S73 = 73,
    HEX_REG_SYS_REGS_S74 = 74,
    HEX_REG_SYS_REGS_S75 = 75,
    HEX_REG_SYS_REGS_S76 = 76,
    HEX_REG_SYS_REGS_S77 = 77,
    HEX_REG_SYS_REGS_S78 = 78,
    HEX_REG_SYS_REGS_S79 = 79,
    HEX_REG_SYS_REGS_S80 = 80,
} HEX_SYS_REGS; // SysRegs

HEX_SYS_REGS64

enum HEX_SYS_REGS64

Enumerator
HEX_REG_SYS_REGS64_S1_0
HEX_REG_SYS_REGS64_S3_2
HEX_REG_SYS_REGS64_S5_4
HEX_REG_SYS_REGS64_S7_6
HEX_REG_SYS_REGS64_S9_8
HEX_REG_SYS_REGS64_S11_10
HEX_REG_SYS_REGS64_S13_12
HEX_REG_SYS_REGS64_S15_14
HEX_REG_SYS_REGS64_S17_16
HEX_REG_SYS_REGS64_S19_18
HEX_REG_SYS_REGS64_S21_20
HEX_REG_SYS_REGS64_S23_22
HEX_REG_SYS_REGS64_S25_24
HEX_REG_SYS_REGS64_S27_26
HEX_REG_SYS_REGS64_S29_28
HEX_REG_SYS_REGS64_S31_30
HEX_REG_SYS_REGS64_S33_32
HEX_REG_SYS_REGS64_S35_34
HEX_REG_SYS_REGS64_S37_36
HEX_REG_SYS_REGS64_S39_38
HEX_REG_SYS_REGS64_S41_40
HEX_REG_SYS_REGS64_S43_42
HEX_REG_SYS_REGS64_S45_44
HEX_REG_SYS_REGS64_S47_46
HEX_REG_SYS_REGS64_S49_48
HEX_REG_SYS_REGS64_S51_50
HEX_REG_SYS_REGS64_S53_52
HEX_REG_SYS_REGS64_S55_54
HEX_REG_SYS_REGS64_S57_56
HEX_REG_SYS_REGS64_S59_58
HEX_REG_SYS_REGS64_S61_60
HEX_REG_SYS_REGS64_S63_62
HEX_REG_SYS_REGS64_S65_64
HEX_REG_SYS_REGS64_S67_66
HEX_REG_SYS_REGS64_S69_68
HEX_REG_SYS_REGS64_S71_70
HEX_REG_SYS_REGS64_S73_72
HEX_REG_SYS_REGS64_S75_74
HEX_REG_SYS_REGS64_S77_76
HEX_REG_SYS_REGS64_S79_78

Definition at line 518 of file hexagon.h.

             {
    HEX_REG_SYS_REGS64_S1_0 = 0, // sgp1:0
    HEX_REG_SYS_REGS64_S3_2 = 2,
    HEX_REG_SYS_REGS64_S5_4 = 4, // badva1:0
    HEX_REG_SYS_REGS64_S7_6 = 6, // ccr:ssr
    HEX_REG_SYS_REGS64_S9_8 = 8,
    HEX_REG_SYS_REGS64_S11_10 = 10,
    HEX_REG_SYS_REGS64_S13_12 = 12,
    HEX_REG_SYS_REGS64_S15_14 = 14,
    HEX_REG_SYS_REGS64_S17_16 = 16,
    HEX_REG_SYS_REGS64_S19_18 = 18,
    HEX_REG_SYS_REGS64_S21_20 = 20,
    HEX_REG_SYS_REGS64_S23_22 = 22,
    HEX_REG_SYS_REGS64_S25_24 = 24,
    HEX_REG_SYS_REGS64_S27_26 = 26,
    HEX_REG_SYS_REGS64_S29_28 = 28,
    HEX_REG_SYS_REGS64_S31_30 = 30, // pcycle
    HEX_REG_SYS_REGS64_S33_32 = 32,
    HEX_REG_SYS_REGS64_S35_34 = 34,
    HEX_REG_SYS_REGS64_S37_36 = 36,
    HEX_REG_SYS_REGS64_S39_38 = 38,
    HEX_REG_SYS_REGS64_S41_40 = 40,
    HEX_REG_SYS_REGS64_S43_42 = 42,
    HEX_REG_SYS_REGS64_S45_44 = 44,
    HEX_REG_SYS_REGS64_S47_46 = 46,
    HEX_REG_SYS_REGS64_S49_48 = 48,
    HEX_REG_SYS_REGS64_S51_50 = 50,
    HEX_REG_SYS_REGS64_S53_52 = 52,
    HEX_REG_SYS_REGS64_S55_54 = 54,
    HEX_REG_SYS_REGS64_S57_56 = 56,
    HEX_REG_SYS_REGS64_S59_58 = 58,
    HEX_REG_SYS_REGS64_S61_60 = 60,
    HEX_REG_SYS_REGS64_S63_62 = 62,
    HEX_REG_SYS_REGS64_S65_64 = 64,
    HEX_REG_SYS_REGS64_S67_66 = 66,
    HEX_REG_SYS_REGS64_S69_68 = 68,
    HEX_REG_SYS_REGS64_S71_70 = 70,
    HEX_REG_SYS_REGS64_S73_72 = 72,
    HEX_REG_SYS_REGS64_S75_74 = 74,
    HEX_REG_SYS_REGS64_S77_76 = 76,
    HEX_REG_SYS_REGS64_S79_78 = 78,
} HEX_SYS_REGS64; // SysRegs64

HexLoopAttr

enum HexLoopAttr

Enumerator
HEX_NO_LOOP
HEX_LOOP_0
HEX_LOOP_1
HEX_LOOP_01

Definition at line 71 of file hexagon.h.

             {
    HEX_NO_LOOP = 0,
    HEX_LOOP_0 = 1, // Is packet of loop0
    HEX_LOOP_1 = 1 << 1, // Is packet of loop1
    HEX_LOOP_01 = 1 << 2 // Belongs to loop 0 and 1
} HexLoopAttr;

HexOpAttr

enum HexOpAttr

Enumerator
HEX_OP_CONST_EXT
HEX_OP_REG_HI
HEX_OP_REG_LO
HEX_OP_REG_PAIR
HEX_OP_REG_QUADRUPLE
HEX_OP_REG_OUT
HEX_OP_IMM_SCALED

Definition at line 61 of file hexagon.h.

             {
    HEX_OP_CONST_EXT = 1 << 0, // Constant extender marker for Immediate
    HEX_OP_REG_HI = 1 << 1, // Rn.H marker
    HEX_OP_REG_LO = 1 << 2, // Rn.L marker
    HEX_OP_REG_PAIR = 1 << 3, // Is this a register pair?
    HEX_OP_REG_QUADRUPLE = 1 << 4, // Is it a register with 4 sub registers?
    HEX_OP_REG_OUT = 1 << 5, // Is the register the destination register?
    HEX_OP_IMM_SCALED = 1 << 6 // Is the immediate shifted?
} HexOpAttr;

HexOpType

enum HexOpType

Enumerator
HEX_OP_TYPE_IMM
HEX_OP_TYPE_REG

Definition at line 54 of file hexagon.h.

             {
    HEX_OP_TYPE_IMM,
    HEX_OP_TYPE_REG,
    // TODO It might be useful to differ between control, HVX, guest regs etc. Also see HexOp
} HexOpType;

HexPf

enum HexPf

Enumerator
HEX_PF_RND
HEX_PF_CRND
HEX_PF_RAW
HEX_PF_CHOP
HEX_PF_SAT
HEX_PF_HI
HEX_PF_LO
HEX_PF_LSH1
HEX_PF_LSH16
HEX_PF_RSH1
HEX_PF_NEG
HEX_PF_POS
HEX_PF_SCALE
HEX_PF_DEPRECATED

Definition at line 37 of file hexagon.h.

             {
    HEX_PF_RND = 1, // :rnd
    HEX_PF_CRND = 1 << 1, // :crnd
    HEX_PF_RAW = 1 << 2, // :raw
    HEX_PF_CHOP = 1 << 3, // :chop
    HEX_PF_SAT = 1 << 4, // :sat
    HEX_PF_HI = 1 << 5, // :hi
    HEX_PF_LO = 1 << 6, // :lo
    HEX_PF_LSH1 = 1 << 7, // :<<1
    HEX_PF_LSH16 = 1 << 8, // :<<16
    HEX_PF_RSH1 = 1 << 9, // :>>1
    HEX_PF_NEG = 1 << 10, // :neg
    HEX_PF_POS = 1 << 11, // :pos
    HEX_PF_SCALE = 1 << 12, // :scale, for FMA instructions
    HEX_PF_DEPRECATED = 1 << 15, // :deprecated
} HexPf;

HexPred

enum HexPred

Enumerator
HEX_NOPRED
HEX_PRED_TRUE
HEX_PRED_FALSE
HEX_PRED_NEW

Definition at line 28 of file hexagon.h.

             {
    HEX_NOPRED, // no conditional execution
    HEX_PRED_TRUE, // if (Pd) ...
    HEX_PRED_FALSE, // if (!Pd) ...
    HEX_PRED_NEW, // if (Pd.new) or if (!Pd.new)
} HexPred;

HexRegClass

enum HexRegClass

Enumerator
HEX_REG_CLASS_CTR_REGS
HEX_REG_CLASS_CTR_REGS64
HEX_REG_CLASS_DOUBLE_REGS
HEX_REG_CLASS_GENERAL_DOUBLE_LOW8_REGS
HEX_REG_CLASS_GENERAL_SUB_REGS
HEX_REG_CLASS_GUEST_REGS
HEX_REG_CLASS_GUEST_REGS64
HEX_REG_CLASS_HVX_QR
HEX_REG_CLASS_HVX_VQR
HEX_REG_CLASS_HVX_VR
HEX_REG_CLASS_HVX_WR
HEX_REG_CLASS_INT_REGS
HEX_REG_CLASS_INT_REGS_LOW8
HEX_REG_CLASS_MOD_REGS
HEX_REG_CLASS_PRED_REGS
HEX_REG_CLASS_SYS_REGS
HEX_REG_CLASS_SYS_REGS64

Definition at line 142 of file hexagon.h.

             {
    HEX_REG_CLASS_CTR_REGS,
    HEX_REG_CLASS_CTR_REGS64,
    HEX_REG_CLASS_DOUBLE_REGS,
    HEX_REG_CLASS_GENERAL_DOUBLE_LOW8_REGS,
    HEX_REG_CLASS_GENERAL_SUB_REGS,
    HEX_REG_CLASS_GUEST_REGS,
    HEX_REG_CLASS_GUEST_REGS64,
    HEX_REG_CLASS_HVX_QR,
    HEX_REG_CLASS_HVX_VQR,
    HEX_REG_CLASS_HVX_VR,
    HEX_REG_CLASS_HVX_WR,
    HEX_REG_CLASS_INT_REGS,
    HEX_REG_CLASS_INT_REGS_LOW8,
    HEX_REG_CLASS_MOD_REGS,
    HEX_REG_CLASS_PRED_REGS,
    HEX_REG_CLASS_SYS_REGS,
    HEX_REG_CLASS_SYS_REGS64
} HexRegClass;

Function Documentation

hex_extend_op()

RZ_API void hex_extend_op	(	HexState *	state,
		RZ_INOUT HexOp *	op,
		const bool	set_new_extender,
		const ut32	addr
	)

Applies the constant extender to the immediate value in op.

Parameters

state	The state to operade on.
op	The operand the extender is applied to or taken from.
set_new_extender	True if the immediate value of the op comes from immext() and sets the a new constant extender. False otherwise.
addr	The address of the currently disassembled instruction.

Definition at line 738 of file hexagon_arch.c.

                                                                                                             {
    if (rz_list_length(state->const_ext_l) > MAX_CONST_EXT) {
        rz_list_purge(state->const_ext_l);
    }
 
    if (op->type != HEX_OP_TYPE_IMM) {
        return;
    }
 
    HexConstExt *ce;
    if (set_new_extender) {
        ce = calloc(1, sizeof(HexConstExt));
        ce->addr = addr + 4;
        ce->const_ext = op->op.imm;
        rz_list_append(state->const_ext_l, ce);
        return;
    }
 
    ce = get_const_ext_from_addr(state->const_ext_l, addr);
    if (ce) {
        op->op.imm = imm_is_scaled(op->attr) ? (op->op.imm >> op->shift) : op->op.imm;
        op->op.imm = ((op->op.imm & 0x3F) | ce->const_ext);
        rz_list_delete_data(state->const_ext_l, ce);
        return;
    }
}

References HexConstExt::addr, addr, calloc(), HexConstExt::const_ext, get_const_ext_from_addr(), HEX_OP_TYPE_IMM, imm_is_scaled(), MAX_CONST_EXT, rz_list_append(), rz_list_delete_data(), rz_list_length(), and rz_list_purge().

Referenced by hex_disasm_with_templates().

hex_get_ctr_regs()

char* hex_get_ctr_regs	(	int	opcode_reg,
		bool	get_alias
	)

Definition at line 24 of file hexagon.c.

                                                       {
    switch (opcode_reg) {
    default: return "<err>";
    case HEX_REG_CTR_REGS_C1:
        return get_alias ? "LC0" : "C1";
    case HEX_REG_CTR_REGS_C0:
        return get_alias ? "SA0" : "C0";
    case HEX_REG_CTR_REGS_C3:
        return get_alias ? "LC1" : "C3";
    case HEX_REG_CTR_REGS_C2:
        return get_alias ? "SA1" : "C2";
    case HEX_REG_CTR_REGS_C4:
        return get_alias ? "P3:0" : "C4";
    case HEX_REG_CTR_REGS_C5:
        return get_alias ? "C5" : "C5";
    case HEX_REG_CTR_REGS_C9:
        return get_alias ? "PC" : "C9";
    case HEX_REG_CTR_REGS_C10:
        return get_alias ? "UGP" : "C10";
    case HEX_REG_CTR_REGS_C11:
        return get_alias ? "GP" : "C11";
    case HEX_REG_CTR_REGS_C12:
        return get_alias ? "CS0" : "C12";
    case HEX_REG_CTR_REGS_C13:
        return get_alias ? "CS1" : "C13";
    case HEX_REG_CTR_REGS_C14:
        return get_alias ? "UPCYCLELO" : "C14";
    case HEX_REG_CTR_REGS_C15:
        return get_alias ? "UPCYCLEHI" : "C15";
    case HEX_REG_CTR_REGS_C16:
        return get_alias ? "FRAMELIMIT" : "C16";
    case HEX_REG_CTR_REGS_C17:
        return get_alias ? "FRAMEKEY" : "C17";
    case HEX_REG_CTR_REGS_C18:
        return get_alias ? "PKTCOUNTLO" : "C18";
    case HEX_REG_CTR_REGS_C19:
        return get_alias ? "PKTCOUNTHI" : "C19";
    case HEX_REG_CTR_REGS_C30:
        return get_alias ? "UTIMERLO" : "C30";
    case HEX_REG_CTR_REGS_C31:
        return get_alias ? "UTIMERHI" : "C31";
    case HEX_REG_CTR_REGS_C6:
        return get_alias ? "M0" : "C6";
    case HEX_REG_CTR_REGS_C7:
        return get_alias ? "M1" : "C7";
    case HEX_REG_CTR_REGS_C8:
        return get_alias ? "USR" : "C8";
    }
}

References HEX_REG_CTR_REGS_C0, HEX_REG_CTR_REGS_C1, HEX_REG_CTR_REGS_C10, HEX_REG_CTR_REGS_C11, HEX_REG_CTR_REGS_C12, HEX_REG_CTR_REGS_C13, HEX_REG_CTR_REGS_C14, HEX_REG_CTR_REGS_C15, HEX_REG_CTR_REGS_C16, HEX_REG_CTR_REGS_C17, HEX_REG_CTR_REGS_C18, HEX_REG_CTR_REGS_C19, HEX_REG_CTR_REGS_C2, HEX_REG_CTR_REGS_C3, HEX_REG_CTR_REGS_C30, HEX_REG_CTR_REGS_C31, HEX_REG_CTR_REGS_C4, HEX_REG_CTR_REGS_C5, HEX_REG_CTR_REGS_C6, HEX_REG_CTR_REGS_C7, HEX_REG_CTR_REGS_C8, and HEX_REG_CTR_REGS_C9.

Referenced by hex_get_reg_in_class().

hex_get_ctr_regs64()

char* hex_get_ctr_regs64	(	int	opcode_reg,
		bool	get_alias
	)

Definition at line 74 of file hexagon.c.

                                                         {
    switch (opcode_reg) {
    default: return "<err>";
    case HEX_REG_CTR_REGS64_C1_0:
        return get_alias ? "LC0:SA0" : "C1:0";
    case HEX_REG_CTR_REGS64_C3_2:
        return get_alias ? "LC1:SA1" : "C3:2";
    case HEX_REG_CTR_REGS64_C5_4:
        return "C5:4";
    case HEX_REG_CTR_REGS64_C7_6:
        return get_alias ? "M1:0" : "C7:6";
    case HEX_REG_CTR_REGS64_C9_8:
        return "C9:8";
    case HEX_REG_CTR_REGS64_C11_10:
        return "C11:10";
    case HEX_REG_CTR_REGS64_C13_12:
        return get_alias ? "CS1:0" : "C13:12";
    case HEX_REG_CTR_REGS64_C15_14:
        return get_alias ? "UPCYCLE" : "C15:14";
    case HEX_REG_CTR_REGS64_C17_16:
        return "C17:16";
    case HEX_REG_CTR_REGS64_C19_18:
        return get_alias ? "PKTCOUNT" : "C19:18";
    case HEX_REG_CTR_REGS64_C31_30:
        return get_alias ? "UTIMER" : "C31:30";
    }
}

References HEX_REG_CTR_REGS64_C11_10, HEX_REG_CTR_REGS64_C13_12, HEX_REG_CTR_REGS64_C15_14, HEX_REG_CTR_REGS64_C17_16, HEX_REG_CTR_REGS64_C19_18, HEX_REG_CTR_REGS64_C1_0, HEX_REG_CTR_REGS64_C31_30, HEX_REG_CTR_REGS64_C3_2, HEX_REG_CTR_REGS64_C5_4, HEX_REG_CTR_REGS64_C7_6, and HEX_REG_CTR_REGS64_C9_8.

Referenced by hex_get_reg_in_class().

hex_get_double_regs()

char* hex_get_double_regs	(	int	opcode_reg,
		bool	get_alias
	)

Definition at line 102 of file hexagon.c.

                                                          {
    switch (opcode_reg) {
    default: return "<err>";
    case HEX_REG_DOUBLE_REGS_R1_0:
        return "R1:0";
    case HEX_REG_DOUBLE_REGS_R3_2:
        return "R3:2";
    case HEX_REG_DOUBLE_REGS_R5_4:
        return "R5:4";
    case HEX_REG_DOUBLE_REGS_R7_6:
        return "R7:6";
    case HEX_REG_DOUBLE_REGS_R9_8:
        return "R9:8";
    case HEX_REG_DOUBLE_REGS_R13_12:
        return "R13:12";
    case HEX_REG_DOUBLE_REGS_R15_14:
        return "R15:14";
    case HEX_REG_DOUBLE_REGS_R17_16:
        return "R17:16";
    case HEX_REG_DOUBLE_REGS_R19_18:
        return "R19:18";
    case HEX_REG_DOUBLE_REGS_R21_20:
        return "R21:20";
    case HEX_REG_DOUBLE_REGS_R23_22:
        return "R23:22";
    case HEX_REG_DOUBLE_REGS_R25_24:
        return "R25:24";
    case HEX_REG_DOUBLE_REGS_R27_26:
        return "R27:26";
    case HEX_REG_DOUBLE_REGS_R11_10:
        return "R11:10";
    case HEX_REG_DOUBLE_REGS_R29_28:
        return "R29:28";
    case HEX_REG_DOUBLE_REGS_R31_30:
        return get_alias ? "LR:FP" : "R31:30";
    }
}

References HEX_REG_DOUBLE_REGS_R11_10, HEX_REG_DOUBLE_REGS_R13_12, HEX_REG_DOUBLE_REGS_R15_14, HEX_REG_DOUBLE_REGS_R17_16, HEX_REG_DOUBLE_REGS_R19_18, HEX_REG_DOUBLE_REGS_R1_0, HEX_REG_DOUBLE_REGS_R21_20, HEX_REG_DOUBLE_REGS_R23_22, HEX_REG_DOUBLE_REGS_R25_24, HEX_REG_DOUBLE_REGS_R27_26, HEX_REG_DOUBLE_REGS_R29_28, HEX_REG_DOUBLE_REGS_R31_30, HEX_REG_DOUBLE_REGS_R3_2, HEX_REG_DOUBLE_REGS_R5_4, HEX_REG_DOUBLE_REGS_R7_6, and HEX_REG_DOUBLE_REGS_R9_8.

Referenced by hex_get_reg_in_class().

hex_get_general_double_low8_regs()

char* hex_get_general_double_low8_regs	(	int	opcode_reg,
		bool	get_alias
	)

Definition at line 140 of file hexagon.c.

                                                                       {
    opcode_reg = opcode_reg << 1;
    if (opcode_reg > 6) { // HEX_REG_D3 == 6
        opcode_reg = (opcode_reg & 0x7) | 0x10;
    }
    switch (opcode_reg) {
    default: return "<err>";
    case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R23_22:
        return "R23:22";
    case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R21_20:
        return "R21:20";
    case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R19_18:
        return "R19:18";
    case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R17_16:
        return "R17:16";
    case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R7_6:
        return "R7:6";
    case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R5_4:
        return "R5:4";
    case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R3_2:
        return "R3:2";
    case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R1_0:
        return "R1:0";
    }
}

References HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R17_16, HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R19_18, HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R1_0, HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R21_20, HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R23_22, HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R3_2, HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R5_4, and HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R7_6.

Referenced by hex_get_reg_in_class().

hex_get_general_sub_regs()

char* hex_get_general_sub_regs	(	int	opcode_reg,
		bool	get_alias
	)

Definition at line 166 of file hexagon.c.

                                                               {
    if (opcode_reg > 7) { // HEX_REG_R7 == 7
        opcode_reg = (opcode_reg & 0x7) | 0x10;
    }
    switch (opcode_reg) {
    default: return "<err>";
    case HEX_REG_GENERAL_SUB_REGS_R23:
        return "R23";
    case HEX_REG_GENERAL_SUB_REGS_R22:
        return "R22";
    case HEX_REG_GENERAL_SUB_REGS_R21:
        return "R21";
    case HEX_REG_GENERAL_SUB_REGS_R20:
        return "R20";
    case HEX_REG_GENERAL_SUB_REGS_R19:
        return "R19";
    case HEX_REG_GENERAL_SUB_REGS_R18:
        return "R18";
    case HEX_REG_GENERAL_SUB_REGS_R17:
        return "R17";
    case HEX_REG_GENERAL_SUB_REGS_R16:
        return "R16";
    case HEX_REG_GENERAL_SUB_REGS_R7:
        return "R7";
    case HEX_REG_GENERAL_SUB_REGS_R6:
        return "R6";
    case HEX_REG_GENERAL_SUB_REGS_R5:
        return "R5";
    case HEX_REG_GENERAL_SUB_REGS_R4:
        return "R4";
    case HEX_REG_GENERAL_SUB_REGS_R3:
        return "R3";
    case HEX_REG_GENERAL_SUB_REGS_R2:
        return "R2";
    case HEX_REG_GENERAL_SUB_REGS_R1:
        return "R1";
    case HEX_REG_GENERAL_SUB_REGS_R0:
        return "R0";
    }
}

References HEX_REG_GENERAL_SUB_REGS_R0, HEX_REG_GENERAL_SUB_REGS_R1, HEX_REG_GENERAL_SUB_REGS_R16, HEX_REG_GENERAL_SUB_REGS_R17, HEX_REG_GENERAL_SUB_REGS_R18, HEX_REG_GENERAL_SUB_REGS_R19, HEX_REG_GENERAL_SUB_REGS_R2, HEX_REG_GENERAL_SUB_REGS_R20, HEX_REG_GENERAL_SUB_REGS_R21, HEX_REG_GENERAL_SUB_REGS_R22, HEX_REG_GENERAL_SUB_REGS_R23, HEX_REG_GENERAL_SUB_REGS_R3, HEX_REG_GENERAL_SUB_REGS_R4, HEX_REG_GENERAL_SUB_REGS_R5, HEX_REG_GENERAL_SUB_REGS_R6, and HEX_REG_GENERAL_SUB_REGS_R7.

Referenced by hex_get_reg_in_class().

hex_get_guest_regs()

char* hex_get_guest_regs	(	int	opcode_reg,
		bool	get_alias
	)

Definition at line 207 of file hexagon.c.

                                                         {
    switch (opcode_reg) {
    default: return "<err>";
    case HEX_REG_GUEST_REGS_G0:
        return get_alias ? "GELR" : "G0";
    case HEX_REG_GUEST_REGS_G1:
        return get_alias ? "GSR" : "G1";
    case HEX_REG_GUEST_REGS_G2:
        return get_alias ? "GOSP" : "G2";
    case HEX_REG_GUEST_REGS_G3:
        return get_alias ? "GBADVA" : "G3";
    case HEX_REG_GUEST_REGS_G4:
        return "G4";
    case HEX_REG_GUEST_REGS_G5:
        return "G5";
    case HEX_REG_GUEST_REGS_G6:
        return "G6";
    case HEX_REG_GUEST_REGS_G7:
        return "G7";
    case HEX_REG_GUEST_REGS_G8:
        return "G8";
    case HEX_REG_GUEST_REGS_G9:
        return "G9";
    case HEX_REG_GUEST_REGS_G10:
        return "G10";
    case HEX_REG_GUEST_REGS_G11:
        return "G11";
    case HEX_REG_GUEST_REGS_G12:
        return "G12";
    case HEX_REG_GUEST_REGS_G13:
        return "G13";
    case HEX_REG_GUEST_REGS_G14:
        return "G14";
    case HEX_REG_GUEST_REGS_G15:
        return "G15";
    case HEX_REG_GUEST_REGS_G16:
        return get_alias ? "GPMUCNT4" : "G16";
    case HEX_REG_GUEST_REGS_G17:
        return get_alias ? "GPMUCNT5" : "G17";
    case HEX_REG_GUEST_REGS_G18:
        return get_alias ? "GPMUCNT6" : "G18";
    case HEX_REG_GUEST_REGS_G19:
        return get_alias ? "GPMUCNT7" : "G19";
    case HEX_REG_GUEST_REGS_G20:
        return "G20";
    case HEX_REG_GUEST_REGS_G21:
        return "G21";
    case HEX_REG_GUEST_REGS_G22:
        return "G22";
    case HEX_REG_GUEST_REGS_G23:
        return "G23";
    case HEX_REG_GUEST_REGS_G24:
        return get_alias ? "GPCYCLELO" : "G24";
    case HEX_REG_GUEST_REGS_G25:
        return get_alias ? "GPCYCLEHI" : "G25";
    case HEX_REG_GUEST_REGS_G26:
        return get_alias ? "GPMUCNT0" : "G26";
    case HEX_REG_GUEST_REGS_G27:
        return get_alias ? "GPMUCNT1" : "G27";
    case HEX_REG_GUEST_REGS_G28:
        return get_alias ? "GPMUCNT2" : "G28";
    case HEX_REG_GUEST_REGS_G29:
        return get_alias ? "GPMUCNT3" : "G29";
    case HEX_REG_GUEST_REGS_G30:
        return "G30";
    case HEX_REG_GUEST_REGS_G31:
        return "G31";
    }
}

References HEX_REG_GUEST_REGS_G0, HEX_REG_GUEST_REGS_G1, HEX_REG_GUEST_REGS_G10, HEX_REG_GUEST_REGS_G11, HEX_REG_GUEST_REGS_G12, HEX_REG_GUEST_REGS_G13, HEX_REG_GUEST_REGS_G14, HEX_REG_GUEST_REGS_G15, HEX_REG_GUEST_REGS_G16, HEX_REG_GUEST_REGS_G17, HEX_REG_GUEST_REGS_G18, HEX_REG_GUEST_REGS_G19, HEX_REG_GUEST_REGS_G2, HEX_REG_GUEST_REGS_G20, HEX_REG_GUEST_REGS_G21, HEX_REG_GUEST_REGS_G22, HEX_REG_GUEST_REGS_G23, HEX_REG_GUEST_REGS_G24, HEX_REG_GUEST_REGS_G25, HEX_REG_GUEST_REGS_G26, HEX_REG_GUEST_REGS_G27, HEX_REG_GUEST_REGS_G28, HEX_REG_GUEST_REGS_G29, HEX_REG_GUEST_REGS_G3, HEX_REG_GUEST_REGS_G30, HEX_REG_GUEST_REGS_G31, HEX_REG_GUEST_REGS_G4, HEX_REG_GUEST_REGS_G5, HEX_REG_GUEST_REGS_G6, HEX_REG_GUEST_REGS_G7, HEX_REG_GUEST_REGS_G8, and HEX_REG_GUEST_REGS_G9.

Referenced by hex_get_reg_in_class().

hex_get_guest_regs64()

char* hex_get_guest_regs64	(	int	opcode_reg,
		bool	get_alias
	)

Definition at line 277 of file hexagon.c.

                                                           {
    switch (opcode_reg) {
    default: return "<err>";
    case HEX_REG_GUEST_REGS64_G1_0:
        return "G1:0";
    case HEX_REG_GUEST_REGS64_G3_2:
        return "G3:2";
    case HEX_REG_GUEST_REGS64_G5_4:
        return "G5:4";
    case HEX_REG_GUEST_REGS64_G7_6:
        return "G7:6";
    case HEX_REG_GUEST_REGS64_G9_8:
        return "G9:8";
    case HEX_REG_GUEST_REGS64_G11_10:
        return "G11:10";
    case HEX_REG_GUEST_REGS64_G13_12:
        return "G13:12";
    case HEX_REG_GUEST_REGS64_G15_14:
        return "G15:14";
    case HEX_REG_GUEST_REGS64_G17_16:
        return "G17:16";
    case HEX_REG_GUEST_REGS64_G19_18:
        return "G19:18";
    case HEX_REG_GUEST_REGS64_G21_20:
        return "G21:20";
    case HEX_REG_GUEST_REGS64_G23_22:
        return "G23:22";
    case HEX_REG_GUEST_REGS64_G25_24:
        return "G25:24";
    case HEX_REG_GUEST_REGS64_G27_26:
        return "G27:26";
    case HEX_REG_GUEST_REGS64_G29_28:
        return "G29:28";
    case HEX_REG_GUEST_REGS64_G31_30:
        return "G31:30";
    }
}

References HEX_REG_GUEST_REGS64_G11_10, HEX_REG_GUEST_REGS64_G13_12, HEX_REG_GUEST_REGS64_G15_14, HEX_REG_GUEST_REGS64_G17_16, HEX_REG_GUEST_REGS64_G19_18, HEX_REG_GUEST_REGS64_G1_0, HEX_REG_GUEST_REGS64_G21_20, HEX_REG_GUEST_REGS64_G23_22, HEX_REG_GUEST_REGS64_G25_24, HEX_REG_GUEST_REGS64_G27_26, HEX_REG_GUEST_REGS64_G29_28, HEX_REG_GUEST_REGS64_G31_30, HEX_REG_GUEST_REGS64_G3_2, HEX_REG_GUEST_REGS64_G5_4, HEX_REG_GUEST_REGS64_G7_6, and HEX_REG_GUEST_REGS64_G9_8.

Referenced by hex_get_reg_in_class().

hex_get_hvx_qr()

char* hex_get_hvx_qr	(	int	opcode_reg,
		bool	get_alias
	)

Definition at line 315 of file hexagon.c.

                                                     {
    switch (opcode_reg) {
    default: return "<err>";
    case HEX_REG_HVX_QR_Q0:
        return "Q0";
    case HEX_REG_HVX_QR_Q1:
        return "Q1";
    case HEX_REG_HVX_QR_Q2:
        return "Q2";
    case HEX_REG_HVX_QR_Q3:
        return "Q3";
    }
}

References HEX_REG_HVX_QR_Q0, HEX_REG_HVX_QR_Q1, HEX_REG_HVX_QR_Q2, and HEX_REG_HVX_QR_Q3.

Referenced by hex_get_reg_in_class().

hex_get_hvx_vqr()

char* hex_get_hvx_vqr	(	int	opcode_reg,
		bool	get_alias
	)

Definition at line 329 of file hexagon.c.

                                                      {
    switch (opcode_reg) {
    default: return "<err>";
    case HEX_REG_HVX_VQR_V3_0:
        return "V3:0";
    case HEX_REG_HVX_VQR_V7_4:
        return "V7:4";
    case HEX_REG_HVX_VQR_V11_8:
        return "V11:8";
    case HEX_REG_HVX_VQR_V15_12:
        return "V15:12";
    case HEX_REG_HVX_VQR_V19_16:
        return "V19:16";
    case HEX_REG_HVX_VQR_V23_20:
        return "V23:20";
    case HEX_REG_HVX_VQR_V27_24:
        return "V27:24";
    case HEX_REG_HVX_VQR_V31_28:
        return "V31:28";
    }
}

References HEX_REG_HVX_VQR_V11_8, HEX_REG_HVX_VQR_V15_12, HEX_REG_HVX_VQR_V19_16, HEX_REG_HVX_VQR_V23_20, HEX_REG_HVX_VQR_V27_24, HEX_REG_HVX_VQR_V31_28, HEX_REG_HVX_VQR_V3_0, and HEX_REG_HVX_VQR_V7_4.

Referenced by hex_get_reg_in_class().

hex_get_hvx_vr()

char* hex_get_hvx_vr	(	int	opcode_reg,
		bool	get_alias
	)

Definition at line 351 of file hexagon.c.

                                                     {
    switch (opcode_reg) {
    default: return "<err>";
    case HEX_REG_HVX_VR_V0:
        return "V0";
    case HEX_REG_HVX_VR_V1:
        return "V1";
    case HEX_REG_HVX_VR_V2:
        return "V2";
    case HEX_REG_HVX_VR_V3:
        return "V3";
    case HEX_REG_HVX_VR_V4:
        return "V4";
    case HEX_REG_HVX_VR_V5:
        return "V5";
    case HEX_REG_HVX_VR_V6:
        return "V6";
    case HEX_REG_HVX_VR_V7:
        return "V7";
    case HEX_REG_HVX_VR_V8:
        return "V8";
    case HEX_REG_HVX_VR_V9:
        return "V9";
    case HEX_REG_HVX_VR_V10:
        return "V10";
    case HEX_REG_HVX_VR_V11:
        return "V11";
    case HEX_REG_HVX_VR_V12:
        return "V12";
    case HEX_REG_HVX_VR_V13:
        return "V13";
    case HEX_REG_HVX_VR_V14:
        return "V14";
    case HEX_REG_HVX_VR_V15:
        return "V15";
    case HEX_REG_HVX_VR_V16:
        return "V16";
    case HEX_REG_HVX_VR_V17:
        return "V17";
    case HEX_REG_HVX_VR_V18:
        return "V18";
    case HEX_REG_HVX_VR_V19:
        return "V19";
    case HEX_REG_HVX_VR_V20:
        return "V20";
    case HEX_REG_HVX_VR_V21:
        return "V21";
    case HEX_REG_HVX_VR_V22:
        return "V22";
    case HEX_REG_HVX_VR_V23:
        return "V23";
    case HEX_REG_HVX_VR_V24:
        return "V24";
    case HEX_REG_HVX_VR_V25:
        return "V25";
    case HEX_REG_HVX_VR_V26:
        return "V26";
    case HEX_REG_HVX_VR_V27:
        return "V27";
    case HEX_REG_HVX_VR_V28:
        return "V28";
    case HEX_REG_HVX_VR_V29:
        return "V29";
    case HEX_REG_HVX_VR_V30:
        return "V30";
    case HEX_REG_HVX_VR_V31:
        return "V31";
    }
}

References HEX_REG_HVX_VR_V0, HEX_REG_HVX_VR_V1, HEX_REG_HVX_VR_V10, HEX_REG_HVX_VR_V11, HEX_REG_HVX_VR_V12, HEX_REG_HVX_VR_V13, HEX_REG_HVX_VR_V14, HEX_REG_HVX_VR_V15, HEX_REG_HVX_VR_V16, HEX_REG_HVX_VR_V17, HEX_REG_HVX_VR_V18, HEX_REG_HVX_VR_V19, HEX_REG_HVX_VR_V2, HEX_REG_HVX_VR_V20, HEX_REG_HVX_VR_V21, HEX_REG_HVX_VR_V22, HEX_REG_HVX_VR_V23, HEX_REG_HVX_VR_V24, HEX_REG_HVX_VR_V25, HEX_REG_HVX_VR_V26, HEX_REG_HVX_VR_V27, HEX_REG_HVX_VR_V28, HEX_REG_HVX_VR_V29, HEX_REG_HVX_VR_V3, HEX_REG_HVX_VR_V30, HEX_REG_HVX_VR_V31, HEX_REG_HVX_VR_V4, HEX_REG_HVX_VR_V5, HEX_REG_HVX_VR_V6, HEX_REG_HVX_VR_V7, HEX_REG_HVX_VR_V8, and HEX_REG_HVX_VR_V9.

Referenced by hex_get_reg_in_class().

hex_get_hvx_wr()

char* hex_get_hvx_wr	(	int	opcode_reg,
		bool	get_alias
	)

Definition at line 421 of file hexagon.c.

                                                     {
    switch (opcode_reg) {
    default: return "<err>";
    case HEX_REG_HVX_WR_V1_0:
        return "V1:0";
    case HEX_REG_HVX_WR_V3_2:
        return "V3:2";
    case HEX_REG_HVX_WR_V5_4:
        return "V5:4";
    case HEX_REG_HVX_WR_V7_6:
        return "V7:6";
    case HEX_REG_HVX_WR_V9_8:
        return "V9:8";
    case HEX_REG_HVX_WR_V11_10:
        return "V11:10";
    case HEX_REG_HVX_WR_V13_12:
        return "V13:12";
    case HEX_REG_HVX_WR_V15_14:
        return "V15:14";
    case HEX_REG_HVX_WR_V17_16:
        return "V17:16";
    case HEX_REG_HVX_WR_V19_18:
        return "V19:18";
    case HEX_REG_HVX_WR_V21_20:
        return "V21:20";
    case HEX_REG_HVX_WR_V23_22:
        return "V23:22";
    case HEX_REG_HVX_WR_V25_24:
        return "V25:24";
    case HEX_REG_HVX_WR_V27_26:
        return "V27:26";
    case HEX_REG_HVX_WR_V29_28:
        return "V29:28";
    case HEX_REG_HVX_WR_V31_30:
        return "V31:30";
    }
}

References HEX_REG_HVX_WR_V11_10, HEX_REG_HVX_WR_V13_12, HEX_REG_HVX_WR_V15_14, HEX_REG_HVX_WR_V17_16, HEX_REG_HVX_WR_V19_18, HEX_REG_HVX_WR_V1_0, HEX_REG_HVX_WR_V21_20, HEX_REG_HVX_WR_V23_22, HEX_REG_HVX_WR_V25_24, HEX_REG_HVX_WR_V27_26, HEX_REG_HVX_WR_V29_28, HEX_REG_HVX_WR_V31_30, HEX_REG_HVX_WR_V3_2, HEX_REG_HVX_WR_V5_4, HEX_REG_HVX_WR_V7_6, and HEX_REG_HVX_WR_V9_8.

Referenced by hex_get_reg_in_class().

hex_get_int_regs()

char* hex_get_int_regs	(	int	opcode_reg,
		bool	get_alias
	)

Definition at line 459 of file hexagon.c.

                                                       {
    switch (opcode_reg) {
    default: return "<err>";
    case HEX_REG_INT_REGS_R0:
        return "R0";
    case HEX_REG_INT_REGS_R1:
        return "R1";
    case HEX_REG_INT_REGS_R2:
        return "R2";
    case HEX_REG_INT_REGS_R3:
        return "R3";
    case HEX_REG_INT_REGS_R4:
        return "R4";
    case HEX_REG_INT_REGS_R5:
        return "R5";
    case HEX_REG_INT_REGS_R6:
        return "R6";
    case HEX_REG_INT_REGS_R7:
        return "R7";
    case HEX_REG_INT_REGS_R8:
        return "R8";
    case HEX_REG_INT_REGS_R9:
        return "R9";
    case HEX_REG_INT_REGS_R12:
        return "R12";
    case HEX_REG_INT_REGS_R13:
        return "R13";
    case HEX_REG_INT_REGS_R14:
        return "R14";
    case HEX_REG_INT_REGS_R15:
        return "R15";
    case HEX_REG_INT_REGS_R16:
        return "R16";
    case HEX_REG_INT_REGS_R17:
        return "R17";
    case HEX_REG_INT_REGS_R18:
        return "R18";
    case HEX_REG_INT_REGS_R19:
        return "R19";
    case HEX_REG_INT_REGS_R20:
        return "R20";
    case HEX_REG_INT_REGS_R21:
        return "R21";
    case HEX_REG_INT_REGS_R22:
        return "R22";
    case HEX_REG_INT_REGS_R23:
        return "R23";
    case HEX_REG_INT_REGS_R24:
        return "R24";
    case HEX_REG_INT_REGS_R25:
        return "R25";
    case HEX_REG_INT_REGS_R26:
        return "R26";
    case HEX_REG_INT_REGS_R27:
        return "R27";
    case HEX_REG_INT_REGS_R28:
        return "R28";
    case HEX_REG_INT_REGS_R10:
        return "R10";
    case HEX_REG_INT_REGS_R11:
        return "R11";
    case HEX_REG_INT_REGS_R29:
        return get_alias ? "SP" : "R29";
    case HEX_REG_INT_REGS_R30:
        return get_alias ? "FP" : "R30";
    case HEX_REG_INT_REGS_R31:
        return get_alias ? "LR" : "R31";
    }
}

References HEX_REG_INT_REGS_R0, HEX_REG_INT_REGS_R1, HEX_REG_INT_REGS_R10, HEX_REG_INT_REGS_R11, HEX_REG_INT_REGS_R12, HEX_REG_INT_REGS_R13, HEX_REG_INT_REGS_R14, HEX_REG_INT_REGS_R15, HEX_REG_INT_REGS_R16, HEX_REG_INT_REGS_R17, HEX_REG_INT_REGS_R18, HEX_REG_INT_REGS_R19, HEX_REG_INT_REGS_R2, HEX_REG_INT_REGS_R20, HEX_REG_INT_REGS_R21, HEX_REG_INT_REGS_R22, HEX_REG_INT_REGS_R23, HEX_REG_INT_REGS_R24, HEX_REG_INT_REGS_R25, HEX_REG_INT_REGS_R26, HEX_REG_INT_REGS_R27, HEX_REG_INT_REGS_R28, HEX_REG_INT_REGS_R29, HEX_REG_INT_REGS_R3, HEX_REG_INT_REGS_R30, HEX_REG_INT_REGS_R31, HEX_REG_INT_REGS_R4, HEX_REG_INT_REGS_R5, HEX_REG_INT_REGS_R6, HEX_REG_INT_REGS_R7, HEX_REG_INT_REGS_R8, and HEX_REG_INT_REGS_R9.

Referenced by hex_get_reg_in_class().

hex_get_int_regs_low8()

char* hex_get_int_regs_low8	(	int	opcode_reg,
		bool	get_alias
	)

Definition at line 529 of file hexagon.c.

                                                            {
    switch (opcode_reg) {
    default: return "<err>";
    case HEX_REG_INT_REGS_LOW8_R7:
        return "R7";
    case HEX_REG_INT_REGS_LOW8_R6:
        return "R6";
    case HEX_REG_INT_REGS_LOW8_R5:
        return "R5";
    case HEX_REG_INT_REGS_LOW8_R4:
        return "R4";
    case HEX_REG_INT_REGS_LOW8_R3:
        return "R3";
    case HEX_REG_INT_REGS_LOW8_R2:
        return "R2";
    case HEX_REG_INT_REGS_LOW8_R1:
        return "R1";
    case HEX_REG_INT_REGS_LOW8_R0:
        return "R0";
    }
}

References HEX_REG_INT_REGS_LOW8_R0, HEX_REG_INT_REGS_LOW8_R1, HEX_REG_INT_REGS_LOW8_R2, HEX_REG_INT_REGS_LOW8_R3, HEX_REG_INT_REGS_LOW8_R4, HEX_REG_INT_REGS_LOW8_R5, HEX_REG_INT_REGS_LOW8_R6, and HEX_REG_INT_REGS_LOW8_R7.

Referenced by hex_get_reg_in_class().

hex_get_mod_regs()

char* hex_get_mod_regs	(	int	opcode_reg,
		bool	get_alias
	)

Definition at line 551 of file hexagon.c.

                                                       {
    opcode_reg |= 6;
    switch (opcode_reg) {
    default: return "<err>";
    case HEX_REG_MOD_REGS_C6:
        return get_alias ? "M0" : "C6";
    case HEX_REG_MOD_REGS_C7:
        return get_alias ? "M1" : "C7";
    }
}

References HEX_REG_MOD_REGS_C6, and HEX_REG_MOD_REGS_C7.

Referenced by hex_get_reg_in_class().

hex_get_pred_regs()

char* hex_get_pred_regs	(	int	opcode_reg,
		bool	get_alias
	)

Definition at line 562 of file hexagon.c.

                                                        {
    switch (opcode_reg) {
    default: return "<err>";
    case HEX_REG_PRED_REGS_P0:
        return "P0";
    case HEX_REG_PRED_REGS_P1:
        return "P1";
    case HEX_REG_PRED_REGS_P2:
        return "P2";
    case HEX_REG_PRED_REGS_P3:
        return "P3";
    }
}

References HEX_REG_PRED_REGS_P0, HEX_REG_PRED_REGS_P1, HEX_REG_PRED_REGS_P2, and HEX_REG_PRED_REGS_P3.

Referenced by hex_get_reg_in_class().

hex_get_reg_in_class()

char* hex_get_reg_in_class	(	HexRegClass	cls,
		int	opcode_reg,
		bool	get_alias
	)

Definition at line 829 of file hexagon.c.

                                                                            {
    switch (cls) {
    case HEX_REG_CLASS_CTR_REGS:
        return hex_get_ctr_regs(opcode_reg, get_alias);
    case HEX_REG_CLASS_CTR_REGS64:
        return hex_get_ctr_regs64(opcode_reg, get_alias);
    case HEX_REG_CLASS_DOUBLE_REGS:
        return hex_get_double_regs(opcode_reg, get_alias);
    case HEX_REG_CLASS_GENERAL_DOUBLE_LOW8_REGS:
        return hex_get_general_double_low8_regs(opcode_reg, get_alias);
    case HEX_REG_CLASS_GENERAL_SUB_REGS:
        return hex_get_general_sub_regs(opcode_reg, get_alias);
    case HEX_REG_CLASS_GUEST_REGS:
        return hex_get_guest_regs(opcode_reg, get_alias);
    case HEX_REG_CLASS_GUEST_REGS64:
        return hex_get_guest_regs64(opcode_reg, get_alias);
    case HEX_REG_CLASS_HVX_QR:
        return hex_get_hvx_qr(opcode_reg, get_alias);
    case HEX_REG_CLASS_HVX_VQR:
        return hex_get_hvx_vqr(opcode_reg, get_alias);
    case HEX_REG_CLASS_HVX_VR:
        return hex_get_hvx_vr(opcode_reg, get_alias);
    case HEX_REG_CLASS_HVX_WR:
        return hex_get_hvx_wr(opcode_reg, get_alias);
    case HEX_REG_CLASS_INT_REGS:
        return hex_get_int_regs(opcode_reg, get_alias);
    case HEX_REG_CLASS_INT_REGS_LOW8:
        return hex_get_int_regs_low8(opcode_reg, get_alias);
    case HEX_REG_CLASS_MOD_REGS:
        return hex_get_mod_regs(opcode_reg, get_alias);
    case HEX_REG_CLASS_PRED_REGS:
        return hex_get_pred_regs(opcode_reg, get_alias);
    case HEX_REG_CLASS_SYS_REGS:
        return hex_get_sys_regs(opcode_reg, get_alias);
    case HEX_REG_CLASS_SYS_REGS64:
        return hex_get_sys_regs64(opcode_reg, get_alias);
    default:
        return NULL;
    }
}

References cls(), hex_get_ctr_regs(), hex_get_ctr_regs64(), hex_get_double_regs(), hex_get_general_double_low8_regs(), hex_get_general_sub_regs(), hex_get_guest_regs(), hex_get_guest_regs64(), hex_get_hvx_qr(), hex_get_hvx_vqr(), hex_get_hvx_vr(), hex_get_hvx_wr(), hex_get_int_regs(), hex_get_int_regs_low8(), hex_get_mod_regs(), hex_get_pred_regs(), hex_get_sys_regs(), hex_get_sys_regs64(), HEX_REG_CLASS_CTR_REGS, HEX_REG_CLASS_CTR_REGS64, HEX_REG_CLASS_DOUBLE_REGS, HEX_REG_CLASS_GENERAL_DOUBLE_LOW8_REGS, HEX_REG_CLASS_GENERAL_SUB_REGS, HEX_REG_CLASS_GUEST_REGS, HEX_REG_CLASS_GUEST_REGS64, HEX_REG_CLASS_HVX_QR, HEX_REG_CLASS_HVX_VQR, HEX_REG_CLASS_HVX_VR, HEX_REG_CLASS_HVX_WR, HEX_REG_CLASS_INT_REGS, HEX_REG_CLASS_INT_REGS_LOW8, HEX_REG_CLASS_MOD_REGS, HEX_REG_CLASS_PRED_REGS, HEX_REG_CLASS_SYS_REGS, HEX_REG_CLASS_SYS_REGS64, and NULL.

Referenced by hex_disasm_with_templates().

hex_get_sys_regs()

char* hex_get_sys_regs	(	int	opcode_reg,
		bool	get_alias
	)

Definition at line 576 of file hexagon.c.

                                                       {
    switch (opcode_reg) {
    default: return "<err>";
    case HEX_REG_SYS_REGS_S0:
        return get_alias ? "SGP0" : "S0";
    case HEX_REG_SYS_REGS_S1:
        return get_alias ? "SGP1" : "S1";
    case HEX_REG_SYS_REGS_S2:
        return get_alias ? "STID" : "S2";
    case HEX_REG_SYS_REGS_S3:
        return get_alias ? "ELR" : "S3";
    case HEX_REG_SYS_REGS_S4:
        return get_alias ? "BADVA0" : "S4";
    case HEX_REG_SYS_REGS_S5:
        return get_alias ? "BADVA1" : "S5";
    case HEX_REG_SYS_REGS_S6:
        return get_alias ? "SSR" : "S6";
    case HEX_REG_SYS_REGS_S7:
        return get_alias ? "CCR" : "S7";
    case HEX_REG_SYS_REGS_S8:
        return get_alias ? "HTID" : "S8";
    case HEX_REG_SYS_REGS_S9:
        return get_alias ? "BADVA" : "S9";
    case HEX_REG_SYS_REGS_S10:
        return get_alias ? "IMASK" : "S10";
    case HEX_REG_SYS_REGS_S11:
        return "S11";
    case HEX_REG_SYS_REGS_S12:
        return "S12";
    case HEX_REG_SYS_REGS_S13:
        return "S13";
    case HEX_REG_SYS_REGS_S14:
        return "S14";
    case HEX_REG_SYS_REGS_S15:
        return "S15";
    case HEX_REG_SYS_REGS_S19:
        return get_alias ? "S19" : "S19";
    case HEX_REG_SYS_REGS_S23:
        return "S23";
    case HEX_REG_SYS_REGS_S25:
        return "S25";
    case HEX_REG_SYS_REGS_S16:
        return get_alias ? "EVB" : "S16";
    case HEX_REG_SYS_REGS_S17:
        return get_alias ? "MODECTL" : "S17";
    case HEX_REG_SYS_REGS_S18:
        return get_alias ? "SYSCFG" : "S18";
    case HEX_REG_SYS_REGS_S20:
        return get_alias ? "S20" : "S20";
    case HEX_REG_SYS_REGS_S21:
        return get_alias ? "VID" : "S21";
    case HEX_REG_SYS_REGS_S22:
        return get_alias ? "S22" : "S22";
    case HEX_REG_SYS_REGS_S24:
        return "S24";
    case HEX_REG_SYS_REGS_S26:
        return "S26";
    case HEX_REG_SYS_REGS_S27:
        return get_alias ? "CFGBASE" : "S27";
    case HEX_REG_SYS_REGS_S28:
        return get_alias ? "DIAG" : "S28";
    case HEX_REG_SYS_REGS_S29:
        return get_alias ? "REV" : "S29";
    case HEX_REG_SYS_REGS_S31:
        return get_alias ? "PCYCLEHI" : "S31";
    case HEX_REG_SYS_REGS_S30:
        return get_alias ? "PCYCLELO" : "S30";
    case HEX_REG_SYS_REGS_S32:
        return get_alias ? "ISDBST" : "S32";
    case HEX_REG_SYS_REGS_S33:
        return get_alias ? "ISDBCFG0" : "S33";
    case HEX_REG_SYS_REGS_S34:
        return get_alias ? "ISDBCFG1" : "S34";
    case HEX_REG_SYS_REGS_S35:
        return "S35";
    case HEX_REG_SYS_REGS_S36:
        return get_alias ? "BRKPTPC0" : "S36";
    case HEX_REG_SYS_REGS_S37:
        return get_alias ? "BRKPTCFG0" : "S37";
    case HEX_REG_SYS_REGS_S38:
        return get_alias ? "BRKPTPC1" : "S38";
    case HEX_REG_SYS_REGS_S39:
        return get_alias ? "BRKPTCFG1" : "S39";
    case HEX_REG_SYS_REGS_S40:
        return get_alias ? "ISDBMBXIN" : "S40";
    case HEX_REG_SYS_REGS_S41:
        return get_alias ? "ISDBMBXOUT" : "S41";
    case HEX_REG_SYS_REGS_S42:
        return get_alias ? "ISDBEN" : "S42";
    case HEX_REG_SYS_REGS_S43:
        return get_alias ? "ISDBGPR" : "S43";
    case HEX_REG_SYS_REGS_S44:
        return "S44";
    case HEX_REG_SYS_REGS_S45:
        return "S45";
    case HEX_REG_SYS_REGS_S46:
        return "S46";
    case HEX_REG_SYS_REGS_S47:
        return "S47";
    case HEX_REG_SYS_REGS_S48:
        return get_alias ? "PMUCNT0" : "S48";
    case HEX_REG_SYS_REGS_S49:
        return get_alias ? "PMUCNT1" : "S49";
    case HEX_REG_SYS_REGS_S50:
        return get_alias ? "PMUCNT2" : "S50";
    case HEX_REG_SYS_REGS_S51:
        return get_alias ? "PMUCNT3" : "S51";
    case HEX_REG_SYS_REGS_S52:
        return get_alias ? "PMUEVTCFG" : "S52";
    case HEX_REG_SYS_REGS_S53:
        return get_alias ? "PMUCFG" : "S53";
    case HEX_REG_SYS_REGS_S54:
        return "S54";
    case HEX_REG_SYS_REGS_S55:
        return "S55";
    case HEX_REG_SYS_REGS_S56:
        return "S56";
    case HEX_REG_SYS_REGS_S57:
        return "S57";
    case HEX_REG_SYS_REGS_S58:
        return "S58";
    case HEX_REG_SYS_REGS_S59:
        return "S59";
    case HEX_REG_SYS_REGS_S60:
        return "S60";
    case HEX_REG_SYS_REGS_S61:
        return "S61";
    case HEX_REG_SYS_REGS_S62:
        return "S62";
    case HEX_REG_SYS_REGS_S63:
        return "S63";
    case HEX_REG_SYS_REGS_S64:
        return "S64";
    case HEX_REG_SYS_REGS_S65:
        return "S65";
    case HEX_REG_SYS_REGS_S66:
        return "S66";
    case HEX_REG_SYS_REGS_S67:
        return "S67";
    case HEX_REG_SYS_REGS_S68:
        return "S68";
    case HEX_REG_SYS_REGS_S69:
        return "S69";
    case HEX_REG_SYS_REGS_S70:
        return "S70";
    case HEX_REG_SYS_REGS_S71:
        return "S71";
    case HEX_REG_SYS_REGS_S72:
        return "S72";
    case HEX_REG_SYS_REGS_S73:
        return "S73";
    case HEX_REG_SYS_REGS_S74:
        return "S74";
    case HEX_REG_SYS_REGS_S75:
        return "S75";
    case HEX_REG_SYS_REGS_S76:
        return "S76";
    case HEX_REG_SYS_REGS_S77:
        return "S77";
    case HEX_REG_SYS_REGS_S78:
        return "S78";
    case HEX_REG_SYS_REGS_S79:
        return "S79";
    case HEX_REG_SYS_REGS_S80:
        return "S80";
    }
}

References HEX_REG_SYS_REGS_S0, HEX_REG_SYS_REGS_S1, HEX_REG_SYS_REGS_S10, HEX_REG_SYS_REGS_S11, HEX_REG_SYS_REGS_S12, HEX_REG_SYS_REGS_S13, HEX_REG_SYS_REGS_S14, HEX_REG_SYS_REGS_S15, HEX_REG_SYS_REGS_S16, HEX_REG_SYS_REGS_S17, HEX_REG_SYS_REGS_S18, HEX_REG_SYS_REGS_S19, HEX_REG_SYS_REGS_S2, HEX_REG_SYS_REGS_S20, HEX_REG_SYS_REGS_S21, HEX_REG_SYS_REGS_S22, HEX_REG_SYS_REGS_S23, HEX_REG_SYS_REGS_S24, HEX_REG_SYS_REGS_S25, HEX_REG_SYS_REGS_S26, HEX_REG_SYS_REGS_S27, HEX_REG_SYS_REGS_S28, HEX_REG_SYS_REGS_S29, HEX_REG_SYS_REGS_S3, HEX_REG_SYS_REGS_S30, HEX_REG_SYS_REGS_S31, HEX_REG_SYS_REGS_S32, HEX_REG_SYS_REGS_S33, HEX_REG_SYS_REGS_S34, HEX_REG_SYS_REGS_S35, HEX_REG_SYS_REGS_S36, HEX_REG_SYS_REGS_S37, HEX_REG_SYS_REGS_S38, HEX_REG_SYS_REGS_S39, HEX_REG_SYS_REGS_S4, HEX_REG_SYS_REGS_S40, HEX_REG_SYS_REGS_S41, HEX_REG_SYS_REGS_S42, HEX_REG_SYS_REGS_S43, HEX_REG_SYS_REGS_S44, HEX_REG_SYS_REGS_S45, HEX_REG_SYS_REGS_S46, HEX_REG_SYS_REGS_S47, HEX_REG_SYS_REGS_S48, HEX_REG_SYS_REGS_S49, HEX_REG_SYS_REGS_S5, HEX_REG_SYS_REGS_S50, HEX_REG_SYS_REGS_S51, HEX_REG_SYS_REGS_S52, HEX_REG_SYS_REGS_S53, HEX_REG_SYS_REGS_S54, HEX_REG_SYS_REGS_S55, HEX_REG_SYS_REGS_S56, HEX_REG_SYS_REGS_S57, HEX_REG_SYS_REGS_S58, HEX_REG_SYS_REGS_S59, HEX_REG_SYS_REGS_S6, HEX_REG_SYS_REGS_S60, HEX_REG_SYS_REGS_S61, HEX_REG_SYS_REGS_S62, HEX_REG_SYS_REGS_S63, HEX_REG_SYS_REGS_S64, HEX_REG_SYS_REGS_S65, HEX_REG_SYS_REGS_S66, HEX_REG_SYS_REGS_S67, HEX_REG_SYS_REGS_S68, HEX_REG_SYS_REGS_S69, HEX_REG_SYS_REGS_S7, HEX_REG_SYS_REGS_S70, HEX_REG_SYS_REGS_S71, HEX_REG_SYS_REGS_S72, HEX_REG_SYS_REGS_S73, HEX_REG_SYS_REGS_S74, HEX_REG_SYS_REGS_S75, HEX_REG_SYS_REGS_S76, HEX_REG_SYS_REGS_S77, HEX_REG_SYS_REGS_S78, HEX_REG_SYS_REGS_S79, HEX_REG_SYS_REGS_S8, HEX_REG_SYS_REGS_S80, and HEX_REG_SYS_REGS_S9.

Referenced by hex_get_reg_in_class().

hex_get_sys_regs64()

char* hex_get_sys_regs64	(	int	opcode_reg,
		bool	get_alias
	)

Definition at line 744 of file hexagon.c.

                                                         {
    switch (opcode_reg) {
    default: return "<err>";
    case HEX_REG_SYS_REGS64_S1_0:
        return get_alias ? "SGP1:0" : "S1:0";
    case HEX_REG_SYS_REGS64_S3_2:
        return "S3:2";
    case HEX_REG_SYS_REGS64_S5_4:
        return get_alias ? "BADVA1:0" : "S5:4";
    case HEX_REG_SYS_REGS64_S7_6:
        return get_alias ? "CCR:SSR" : "S7:6";
    case HEX_REG_SYS_REGS64_S9_8:
        return "S9:8";
    case HEX_REG_SYS_REGS64_S11_10:
        return "S11:10";
    case HEX_REG_SYS_REGS64_S13_12:
        return "S13:12";
    case HEX_REG_SYS_REGS64_S15_14:
        return "S15:14";
    case HEX_REG_SYS_REGS64_S17_16:
        return "S17:16";
    case HEX_REG_SYS_REGS64_S19_18:
        return "S19:18";
    case HEX_REG_SYS_REGS64_S21_20:
        return "S21:20";
    case HEX_REG_SYS_REGS64_S23_22:
        return "S23:22";
    case HEX_REG_SYS_REGS64_S25_24:
        return "S25:24";
    case HEX_REG_SYS_REGS64_S27_26:
        return "S27:26";
    case HEX_REG_SYS_REGS64_S29_28:
        return "S29:28";
    case HEX_REG_SYS_REGS64_S31_30:
        return get_alias ? "PCYCLE" : "S31:30";
    case HEX_REG_SYS_REGS64_S33_32:
        return "S33:32";
    case HEX_REG_SYS_REGS64_S35_34:
        return "S35:34";
    case HEX_REG_SYS_REGS64_S37_36:
        return "S37:36";
    case HEX_REG_SYS_REGS64_S39_38:
        return "S39:38";
    case HEX_REG_SYS_REGS64_S41_40:
        return "S41:40";
    case HEX_REG_SYS_REGS64_S43_42:
        return "S43:42";
    case HEX_REG_SYS_REGS64_S45_44:
        return "S45:44";
    case HEX_REG_SYS_REGS64_S47_46:
        return "S47:46";
    case HEX_REG_SYS_REGS64_S49_48:
        return "S49:48";
    case HEX_REG_SYS_REGS64_S51_50:
        return "S51:50";
    case HEX_REG_SYS_REGS64_S53_52:
        return "S53:52";
    case HEX_REG_SYS_REGS64_S55_54:
        return "S55:54";
    case HEX_REG_SYS_REGS64_S57_56:
        return "S57:56";
    case HEX_REG_SYS_REGS64_S59_58:
        return "S59:58";
    case HEX_REG_SYS_REGS64_S61_60:
        return "S61:60";
    case HEX_REG_SYS_REGS64_S63_62:
        return "S63:62";
    case HEX_REG_SYS_REGS64_S65_64:
        return "S65:64";
    case HEX_REG_SYS_REGS64_S67_66:
        return "S67:66";
    case HEX_REG_SYS_REGS64_S69_68:
        return "S69:68";
    case HEX_REG_SYS_REGS64_S71_70:
        return "S71:70";
    case HEX_REG_SYS_REGS64_S73_72:
        return "S73:72";
    case HEX_REG_SYS_REGS64_S75_74:
        return "S75:74";
    case HEX_REG_SYS_REGS64_S77_76:
        return "S77:76";
    case HEX_REG_SYS_REGS64_S79_78:
        return "S79:78";
    }
}

References HEX_REG_SYS_REGS64_S11_10, HEX_REG_SYS_REGS64_S13_12, HEX_REG_SYS_REGS64_S15_14, HEX_REG_SYS_REGS64_S17_16, HEX_REG_SYS_REGS64_S19_18, HEX_REG_SYS_REGS64_S1_0, HEX_REG_SYS_REGS64_S21_20, HEX_REG_SYS_REGS64_S23_22, HEX_REG_SYS_REGS64_S25_24, HEX_REG_SYS_REGS64_S27_26, HEX_REG_SYS_REGS64_S29_28, HEX_REG_SYS_REGS64_S31_30, HEX_REG_SYS_REGS64_S33_32, HEX_REG_SYS_REGS64_S35_34, HEX_REG_SYS_REGS64_S37_36, HEX_REG_SYS_REGS64_S39_38, HEX_REG_SYS_REGS64_S3_2, HEX_REG_SYS_REGS64_S41_40, HEX_REG_SYS_REGS64_S43_42, HEX_REG_SYS_REGS64_S45_44, HEX_REG_SYS_REGS64_S47_46, HEX_REG_SYS_REGS64_S49_48, HEX_REG_SYS_REGS64_S51_50, HEX_REG_SYS_REGS64_S53_52, HEX_REG_SYS_REGS64_S55_54, HEX_REG_SYS_REGS64_S57_56, HEX_REG_SYS_REGS64_S59_58, HEX_REG_SYS_REGS64_S5_4, HEX_REG_SYS_REGS64_S61_60, HEX_REG_SYS_REGS64_S63_62, HEX_REG_SYS_REGS64_S65_64, HEX_REG_SYS_REGS64_S67_66, HEX_REG_SYS_REGS64_S69_68, HEX_REG_SYS_REGS64_S71_70, HEX_REG_SYS_REGS64_S73_72, HEX_REG_SYS_REGS64_S75_74, HEX_REG_SYS_REGS64_S77_76, HEX_REG_SYS_REGS64_S79_78, HEX_REG_SYS_REGS64_S7_6, and HEX_REG_SYS_REGS64_S9_8.

Referenced by hex_get_reg_in_class().

hexagon_disasm_0x0()

void hexagon_disasm_0x0	(	HexState *	state,
		const ut32	hi_u32,
		RZ_INOUT HexInsn *	hi,
		const ut32	addr,
		HexPkt *	pkt
	)

hexagon_disasm_0x1()

void hexagon_disasm_0x1	(	HexState *	state,
		const ut32	hi_u32,
		RZ_INOUT HexInsn *	hi,
		const ut32	addr,
		HexPkt *	pkt
	)

hexagon_disasm_0x2()

void hexagon_disasm_0x2	(	HexState *	state,
		const ut32	hi_u32,
		RZ_INOUT HexInsn *	hi,
		const ut32	addr,
		HexPkt *	pkt
	)

hexagon_disasm_0x3()

void hexagon_disasm_0x3	(	HexState *	state,
		const ut32	hi_u32,
		RZ_INOUT HexInsn *	hi,
		const ut32	addr,
		HexPkt *	pkt
	)

hexagon_disasm_0x4()

void hexagon_disasm_0x4	(	HexState *	state,
		const ut32	hi_u32,
		RZ_INOUT HexInsn *	hi,
		const ut32	addr,
		HexPkt *	pkt
	)

hexagon_disasm_0x5()

void hexagon_disasm_0x5	(	HexState *	state,
		const ut32	hi_u32,
		RZ_INOUT HexInsn *	hi,
		const ut32	addr,
		HexPkt *	pkt
	)

hexagon_disasm_0x6()

void hexagon_disasm_0x6	(	HexState *	state,
		const ut32	hi_u32,
		RZ_INOUT HexInsn *	hi,
		const ut32	addr,
		HexPkt *	pkt
	)

hexagon_disasm_0x7()

void hexagon_disasm_0x7	(	HexState *	state,
		const ut32	hi_u32,
		RZ_INOUT HexInsn *	hi,
		const ut32	addr,
		HexPkt *	pkt
	)

hexagon_disasm_0x8()

void hexagon_disasm_0x8	(	HexState *	state,
		const ut32	hi_u32,
		RZ_INOUT HexInsn *	hi,
		const ut32	addr,
		HexPkt *	pkt
	)

hexagon_disasm_0x9()

void hexagon_disasm_0x9	(	HexState *	state,
		const ut32	hi_u32,
		RZ_INOUT HexInsn *	hi,
		const ut32	addr,
		HexPkt *	pkt
	)

hexagon_disasm_0xa()

void hexagon_disasm_0xa	(	HexState *	state,
		const ut32	hi_u32,
		RZ_INOUT HexInsn *	hi,
		const ut32	addr,
		HexPkt *	pkt
	)

hexagon_disasm_0xb()

void hexagon_disasm_0xb	(	HexState *	state,
		const ut32	hi_u32,
		RZ_INOUT HexInsn *	hi,
		const ut32	addr,
		HexPkt *	pkt
	)

hexagon_disasm_0xc()

void hexagon_disasm_0xc	(	HexState *	state,
		const ut32	hi_u32,
		RZ_INOUT HexInsn *	hi,
		const ut32	addr,
		HexPkt *	pkt
	)

hexagon_disasm_0xd()

void hexagon_disasm_0xd	(	HexState *	state,
		const ut32	hi_u32,
		RZ_INOUT HexInsn *	hi,
		const ut32	addr,
		HexPkt *	pkt
	)

hexagon_disasm_0xe()

void hexagon_disasm_0xe	(	HexState *	state,
		const ut32	hi_u32,
		RZ_INOUT HexInsn *	hi,
		const ut32	addr,
		HexPkt *	pkt
	)

hexagon_disasm_duplex_0x0()

void hexagon_disasm_duplex_0x0	(	HexState *	state,
		const ut32	hi_u32,
		RZ_INOUT HexInsn *	hi,
		const ut32	addr,
		HexPkt *	pkt
	)

hexagon_disasm_duplex_0x1()

void hexagon_disasm_duplex_0x1	(	HexState *	state,
		const ut32	hi_u32,
		RZ_INOUT HexInsn *	hi,
		const ut32	addr,
		HexPkt *	pkt
	)

hexagon_disasm_duplex_0x2()

void hexagon_disasm_duplex_0x2	(	HexState *	state,
		const ut32	hi_u32,
		RZ_INOUT HexInsn *	hi,
		const ut32	addr,
		HexPkt *	pkt
	)

hexagon_disasm_duplex_0x3()

void hexagon_disasm_duplex_0x3	(	HexState *	state,
		const ut32	hi_u32,
		RZ_INOUT HexInsn *	hi,
		const ut32	addr,
		HexPkt *	pkt
	)

hexagon_disasm_duplex_0x4()

void hexagon_disasm_duplex_0x4	(	HexState *	state,
		const ut32	hi_u32,
		RZ_INOUT HexInsn *	hi,
		const ut32	addr,
		HexPkt *	pkt
	)

hexagon_disasm_duplex_0x5()

void hexagon_disasm_duplex_0x5	(	HexState *	state,
		const ut32	hi_u32,
		RZ_INOUT HexInsn *	hi,
		const ut32	addr,
		HexPkt *	pkt
	)

hexagon_disasm_duplex_0x6()

void hexagon_disasm_duplex_0x6	(	HexState *	state,
		const ut32	hi_u32,
		RZ_INOUT HexInsn *	hi,
		const ut32	addr,
		HexPkt *	pkt
	)

hexagon_disasm_duplex_0x7()

void hexagon_disasm_duplex_0x7	(	HexState *	state,
		const ut32	hi_u32,
		RZ_INOUT HexInsn *	hi,
		const ut32	addr,
		HexPkt *	pkt
	)

hexagon_disasm_duplex_0x8()

void hexagon_disasm_duplex_0x8	(	HexState *	state,
		const ut32	hi_u32,
		RZ_INOUT HexInsn *	hi,
		const ut32	addr,
		HexPkt *	pkt
	)

hexagon_disasm_duplex_0x9()

void hexagon_disasm_duplex_0x9	(	HexState *	state,
		const ut32	hi_u32,
		RZ_INOUT HexInsn *	hi,
		const ut32	addr,
		HexPkt *	pkt
	)

hexagon_disasm_duplex_0xa()

void hexagon_disasm_duplex_0xa	(	HexState *	state,
		const ut32	hi_u32,
		RZ_INOUT HexInsn *	hi,
		const ut32	addr,
		HexPkt *	pkt
	)

hexagon_disasm_duplex_0xb()

void hexagon_disasm_duplex_0xb	(	HexState *	state,
		const ut32	hi_u32,
		RZ_INOUT HexInsn *	hi,
		const ut32	addr,
		HexPkt *	pkt
	)

hexagon_disasm_duplex_0xc()

void hexagon_disasm_duplex_0xc	(	HexState *	state,
		const ut32	hi_u32,
		RZ_INOUT HexInsn *	hi,
		const ut32	addr,
		HexPkt *	pkt
	)

hexagon_disasm_duplex_0xd()

void hexagon_disasm_duplex_0xd	(	HexState *	state,
		const ut32	hi_u32,
		RZ_INOUT HexInsn *	hi,
		const ut32	addr,
		HexPkt *	pkt
	)

hexagon_disasm_duplex_0xe()

void hexagon_disasm_duplex_0xe	(	HexState *	state,
		const ut32	hi_u32,
		RZ_INOUT HexInsn *	hi,
		const ut32	addr,
		HexPkt *	pkt
	)

hexagon_disasm_instruction()

int hexagon_disasm_instruction	(	HexState *	state,
		const ut32	hi_u32,
		RZ_INOUT HexInsn *	hi,
		HexPkt *	pkt
	)

Definition at line 53620 of file hexagon_disas.c.

                                                                                                      {
    ut32 addr = hi->addr;
    if (hi->pkt_info.last_insn) {
        switch (hex_get_loop_flag(pkt)) {
        default: break;
        case HEX_LOOP_01:
            hi->ana_op.prefix = RZ_ANALYSIS_OP_PREFIX_HWLOOP_END;
            hi->ana_op.fail = pkt->hw_loop0_addr;
            hi->ana_op.jump = pkt->hw_loop1_addr;
            hi->ana_op.val = hi->ana_op.jump;
            break;
        case HEX_LOOP_0:
            hi->ana_op.prefix = RZ_ANALYSIS_OP_PREFIX_HWLOOP_END;
            hi->ana_op.jump = pkt->hw_loop0_addr;
            hi->ana_op.val = hi->ana_op.jump;
            break;
        case HEX_LOOP_1:
            hi->ana_op.prefix = RZ_ANALYSIS_OP_PREFIX_HWLOOP_END;
            hi->ana_op.jump = pkt->hw_loop1_addr;
            hi->ana_op.val = hi->ana_op.jump;
            break;
        }
    }
    if (hi_u32 != 0x00000000) {
        if (((hi_u32 >> 14) & 0x3) == 0) {
            // DUPLEXES
            ut32 cat = (((hi_u32 >> 29) & 0xF) << 1) | ((hi_u32 >> 13) & 1);
            if (cat < 0xf) {
                hex_disasm_with_templates(templates_duplex[cat], state, hi_u32, hi, addr, pkt);
                hi->duplex = true;
            }
        } else {
            ut32 cat = (hi_u32 >> 28) & 0xF;
            hex_disasm_with_templates(templates_normal[cat], state, hi_u32, hi, addr, pkt);
        }
    }
    if (pkt->is_eob && is_last_instr(hi->parse_bits)) {
        hi->ana_op.eob = true;
    }
    if (hi->instruction == HEX_INS_INVALID_DECODE) {
        hi->parse_bits = ((hi_u32)&0xc000) >> 14;
        hi->ana_op.type = RZ_ANALYSIS_OP_TYPE_ILL;
        sprintf(hi->mnem_infix, "invalid");
        sprintf(hi->mnem, "%s%s%s", hi->pkt_info.mnem_prefix, hi->mnem_infix, hi->pkt_info.mnem_postfix);
    }
 
    return 4;
}

References addr, cat(), hex_disasm_with_templates(), hex_get_loop_flag(), HEX_INS_INVALID_DECODE, HEX_LOOP_0, HEX_LOOP_01, HEX_LOOP_1, hi(), HexPkt::hw_loop0_addr, HexPkt::hw_loop1_addr, HexPkt::is_eob, is_last_instr(), RZ_ANALYSIS_OP_PREFIX_HWLOOP_END, RZ_ANALYSIS_OP_TYPE_ILL, sprintf, templates_duplex, and templates_normal.

Referenced by hexagon_reverse_opcode().

hexagon_get_config()

RZ_API RZ_BORROW RzConfig* hexagon_get_config

(

)

resolve_n_register()

int resolve_n_register	(	const int	reg_num,
		const ut32	addr,
		const HexPkt *	p
	)

Resolves the 3 bit value of an Nt.new reg to the general register of the producer.

Parameters

addr	The address of the current instruction.
reg_num	Bits of Nt.new reg.
p	The current packet.

Returns

int The number of the general register. Or UT32_MAX if any error occured.

Definition at line 878 of file hexagon.c.

                                                                            {
    // .new values are documented in Programmers Reference Manual
    if (reg_num <= 1 || reg_num >= 8) {
        return UT32_MAX;
    }
 
    ut8 ahead = (reg_num >> 1);
    ut8 i = hexagon_get_pkt_index_of_addr(addr, p);
    if (i == UT8_MAX) {
        return UT32_MAX;
    }
 
    ut8 prod_i = i; // Producer index
    HexInsn *hi;
    RzListIter *it;
    rz_list_foreach_prev(p->insn, it, hi) {
        if (ahead == 0) {
            break;
        }
        if (hi->addr < addr) {
            if (hi->instruction == HEX_INS_A4_EXT) {
                --prod_i;
                continue;
            }
            --ahead;
            --prod_i;
        }
    }
 
    hi = rz_list_get_n(p->insn, prod_i);
 
    if (!hi) {
        return UT32_MAX;
    }
    if (hi->instruction == HEX_INS_A4_EXT) {
        return UT32_MAX;
    }
 
    for (ut8 i = 0; i < 6; ++i) {
        if (hi->ops[i].attr & HEX_OP_REG_OUT) {
            return hi->ops[i].op.reg;
        }
    }
    return UT32_MAX;
}

References addr, HEX_INS_A4_EXT, HEX_OP_REG_OUT, hexagon_get_pkt_index_of_addr(), hi(), i, p, rz_list_get_n(), UT32_MAX, and UT8_MAX.

Referenced by hex_disasm_with_templates().