asm_mips_cs.c File Reference

#include <rz_asm.h>
#include <rz_lib.h>
#include <capstone/capstone.h>
#include "cs_mnemonics.c"

Go to the source code of this file.

Functions
RZ_IPI int	mips_assemble (const char *str, ut64 pc, ut8 *out)
static int	disassemble (RzAsm *a, RzAsmOp *op, const ut8 *buf, int len)
static int	assemble (RzAsm *a, RzAsmOp *op, const char *str)

Variables
static csh	cd = 0
RzAsmPlugin	rz_asm_plugin_mips_cs
RZ_API RzLibStruct	rizin_plugin

Function Documentation

assemble()

static int assemble ( RzAsm *  a, RzAsmOp *  op, const char *  str  )

static

Definition at line 73 of file asm_mips_cs.c.

                                                            {
    ut8 *opbuf = (ut8 *)rz_strbuf_get(&op->buf);
    int ret = mips_assemble(str, a->pc, opbuf);
    if (a->big_endian) {
        ut8 *buf = opbuf;
        ut8 tmp = buf[0];
        buf[0] = buf[3];
        buf[3] = tmp;
        tmp = buf[1];
        buf[1] = buf[2];
        buf[2] = tmp;
    }
    return ret;
}

References a, mips_assemble(), rz_strbuf_get(), cmd_descs_generate::str, and autogen_x86imm::tmp.

disassemble()

static int disassemble ( RzAsm *  a, RzAsmOp *  op, const ut8 *  buf, int  len  )

static

Definition at line 13 of file asm_mips_cs.c.

                                                                       {
    cs_insn *insn;
    int mode, n, ret = -1;
    mode = (a->big_endian) ? CS_MODE_BIG_ENDIAN : CS_MODE_LITTLE_ENDIAN;
    if (!op) {
        return 0;
    }
    if (a->cpu && *a->cpu) {
        if (!strcmp(a->cpu, "micro")) {
            mode |= CS_MODE_MICRO;
        } else if (!strcmp(a->cpu, "r6")) {
            mode |= CS_MODE_MIPS32R6;
        } else if (!strcmp(a->cpu, "v3")) {
            mode |= CS_MODE_MIPS3;
        } else if (!strcmp(a->cpu, "v2")) {
#if CS_API_MAJOR > 3
            mode |= CS_MODE_MIPS2;
#endif
        }
    }
    mode |= (a->bits == 64) ? CS_MODE_MIPS64 : CS_MODE_MIPS32;
    memset(op, 0, sizeof(RzAsmOp));
    op->size = 4;
    if (cd != 0) {
        cs_close(&cd);
    }
    ret = cs_open(CS_ARCH_MIPS, mode, &cd);
    if (ret) {
        goto fin;
    }
    if (a->syntax == RZ_ASM_SYNTAX_REGNUM) {
        cs_option(cd, CS_OPT_SYNTAX, CS_OPT_SYNTAX_NOREGNAME);
    } else {
        cs_option(cd, CS_OPT_SYNTAX, CS_OPT_SYNTAX_DEFAULT);
    }
    cs_option(cd, CS_OPT_DETAIL, CS_OPT_OFF);
    n = cs_disasm(cd, (ut8 *)buf, len, a->pc, 1, &insn);
    if (n < 1) {
        rz_asm_op_set_asm(op, "invalid");
        op->size = 4;
        goto beach;
    }
    if (insn->size < 1) {
        goto beach;
    }
    op->size = insn->size;
    char *str = rz_str_newf("%s%s%s", insn->mnemonic, insn->op_str[0] ? " " : "", insn->op_str);
    if (str) {
        rz_str_replace_char(str, '$', 0);
        // remove the '$'<registername> in the string
        rz_asm_op_set_asm(op, str);
        free(str);
    }
    cs_free(insn, n);
beach:
    // cs_close (&cd);
fin:
    return op->size;
}

References a, cd, CS_ARCH_MIPS, cs_close(), cs_disasm(), cs_free(), CS_MODE_BIG_ENDIAN, CS_MODE_LITTLE_ENDIAN, CS_MODE_MICRO, CS_MODE_MIPS2, CS_MODE_MIPS3, CS_MODE_MIPS32, CS_MODE_MIPS32R6, CS_MODE_MIPS64, cs_open(), CS_OPT_DETAIL, CS_OPT_OFF, CS_OPT_SYNTAX, CS_OPT_SYNTAX_DEFAULT, CS_OPT_SYNTAX_NOREGNAME, cs_option(), free(), len, memset(), n, rz_asm_op_set_asm(), RZ_ASM_SYNTAX_REGNUM, rz_str_newf(), rz_str_replace_char(), and cmd_descs_generate::str.

mips_assemble()

RZ_IPI int mips_assemble	(	const char *	str,
		ut64	pc,
		ut8 *	out
	)

Definition at line 148 of file mipsasm.c.

                                                             {
    int i, hasp;
    char w0[32], w1[32], w2[32], w3[32];
    char *s = strdup(str);
    if (!s) {
        return -1;
    }
 
    rz_str_replace_char(s, ',', ' ');
    hasp = rz_str_replace_char(s, '(', ' ');
    rz_str_replace_char(s, ')', ' ');
 
    *out = 0;
    *w0 = 0;
    *w1 = 0;
    *w2 = 0;
    *w3 = 0;
 
    if (!strncmp(s, "jalr", 4) && !strchr(s, ',')) {
        char opstr[32];
        const char *arg = strchr(s, ' ');
        if (arg) {
            snprintf(opstr, sizeof(opstr), "jalr ra ra %s", arg + 1);
            free(s);
            s = strdup(opstr);
            if (!s) {
                return -1;
            }
        }
    }
 
    sscanf(s, "%31s", w0);
    if (*w0) {
        for (i = 0; ops[i].name; i++) {
            if (!strcmp(ops[i].name, w0)) {
                switch (ops[i].args) {
                case 3: sscanf(s, "%31s %31s %31s %31s", w0, w1, w2, w3); break;
                case -3: sscanf(s, "%31s %31s %31s %31s", w0, w1, w2, w3); break;
                case 2: sscanf(s, "%31s %31s %31s", w0, w1, w2); break;
                case -2: sscanf(s, "%31s %31s %31s", w0, w1, w2); break;
                case 1: sscanf(s, "%31s %31s", w0, w1); break;
                case -1: sscanf(s, "%31s %31s", w0, w1); break;
                case 0: sscanf(s, "%31s", w0); break;
                }
                if (hasp) {
                    char tmp[32];
                    strcpy(tmp, w2);
                    strcpy(w2, w3);
                    strcpy(w3, tmp);
                }
                switch (ops[i].type) {
                case 'R': {
                    // reg order diff per instruction 'group' - ordered to number of likelyhood to call (add > mfhi)
                    int op = 0, rs = 0, rt = 0, rd = 0, sa = 0, fn = 0;
                    bool invalid = false;
                    switch (ops[i].args) {
                    case 3:
                        rs = getreg(w2);
                        rt = getreg(w3);
                        rd = getreg(w1);
                        fn = ops[i].n;
                        break;
                    case -3:
                        if (ops[i].n > -1) {
                            rt = getreg(w2);
                            rd = getreg(w1);
                            sa = getreg(w3);
                            fn = ops[i].n;
                        } else {
                            rs = getreg(w3);
                            rt = getreg(w2);
                            rd = getreg(w1);
                            fn = (-1 * ops[i].n);
                        }
                        break;
                    case 2:
                        rs = getreg(w1);
                        rt = getreg(w2);
                        fn = ops[i].n;
                        break;
                    case 1:
                        rs = getreg(w1);
                        fn = ops[i].n;
                        break;
                    case -2:
                        rs = getreg(w2);
                        rd = getreg(w1);
                        fn = ops[i].n;
                        break;
                    case -1:
                        rd = getreg(w1);
                        fn = ops[i].n;
                        break;
                    case 0:
                        fn = ops[i].n;
                        break;
                    default:
                        invalid = true;
                        break;
                    }
                    if (!invalid) {
                        free(s);
                        return mips_r(out, op, rs, rt, rd, sa, fn);
                    }
                    break;
                }
                case 'I':
                case 'B': {
                    bool invalid = false;
                    int op = 0, rs = 0, rt = 0, imm = 0, is_branch = ops[i].type == 'B';
                    switch (ops[i].args) {
                    case 2:
                        op = ops[i].n;
                        rt = getreg(w1);
                        imm = getreg(w2);
                        break;
                    case 3:
                        op = ops[i].n;
                        rs = getreg(w2);
                        rt = getreg(w1);
                        imm = getreg(w3);
                        break;
                    case -2:
                        if (ops[i].n > 0) {
                            op = ops[i].n;
                            rs = getreg(w1);
                            imm = getreg(w2);
                        } else {
                            op = (-1 * ops[i].n);
                            rs = getreg(w1);
                            rt = ops[i].x;
                            imm = getreg(w2);
                        }
                        break;
                    case -1:
                        if (ops[i].n > 0) {
                            op = ops[i].n;
                            imm = getreg(w1);
                        } else {
                            op = (-1 * ops[i].n);
                            rt = ops[i].x;
                            imm = getreg(w1);
                        }
                        break;
                    default:
                        invalid = true;
                        break;
                    }
                    if (!invalid) {
                        free(s);
                        return mips_i(out, op, rs, rt, imm, is_branch);
                    }
                    break;
                }
                case 'J':
                    if (ops[i].args == 1) {
                        free(s);
                        return mips_j(out, ops[i].n, getreg(w1));
                    }
                    break;
                case 'N': // nop
                    memset(out, 0, 4);
                    free(s);
                    return 4;
                }
                free(s);
                return -1;
            }
        }
    }
    free(s);
    return -1;
}

Referenced by assemble().

Variable Documentation

cd

csh cd = 0

static

Definition at line 10 of file asm_mips_cs.c.

Referenced by _zip_cdir_free(), _zip_cdir_grow(), _zip_cdir_new(), _zip_checkcons(), _zip_read_cdir(), _zip_read_eocd(), _zip_read_eocd64(), ARC_CGEN_EXTRACT_FN(), args_preprocessing(), argv_call_cb(), argv_get_help(), autocmplt_cmd_arg(), autocmplt_cmd_arg_reg_filter(), build(), cab_error(), calc_padding_len(), call_cd(), cd_suffix2mode(), cmd_desc_free(), cmd_desc_remove_from_ht_cmds(), cmd_desc_set_parent(), cmd_desc_unset_parent(), cmd_foreach_cmdname(), cmd_foreach_cmdname_modes(), cmd_get_desc_best(), DEFINE_HANDLE_TS_FCN_AND_SYMBOL(), disassemble(), do_print_child_help(), fake_get_help(), fill_args(), fill_args_json(), fill_argv_modes_help_strbuf(), fill_children_chars(), fill_details(), fill_details_cb(), fill_details_static(), fill_modes_children_chars(), fill_usage_strbuf(), get_cd_default_mode(), get_cd_details(), get_cd_details_cb(), get_cd_from_cmdid(), get_help(), get_minmax_argc(), group_get_help(), has_cd_default_mode(), has_cd_submodes(), help_search_cmd_desc_entry(), is_valid_argv_modes(), mnemonics(), print_child_help(), rz_cmd_call_parsed_args(), rz_cmd_desc_get_arg(), rz_cmd_desc_get_exec(), rz_cmd_desc_has_handler(), rz_cmd_desc_parent(), rz_cmd_desc_remove(), rz_cmd_desc_set_default_mode(), rz_cmd_example_init(), rz_cmd_foreach_cmdname(), rz_cmd_get_help(), rz_cmd_get_help_json(), rz_cmd_get_help_strbuf(), show_children_shortcut(), sort_groups(), and update_minmax_len().

rizin_plugin

RZ_API RzLibStruct rizin_plugin

Initial value:

= {
    .type = RZ_LIB_TYPE_ASM,
    .data = &rz_asm_plugin_mips_cs,
    .version = RZ_VERSION
}

Definition at line 102 of file asm_mips_cs.c.

rz_asm_plugin_mips_cs

RzAsmPlugin rz_asm_plugin_mips_cs

Initial value:

= {
    .name = "mips",
    .desc = "Capstone MIPS disassembler",
    .license = "BSD",
    .arch = "mips",
    .cpus = "mips32/64,micro,r6,v3,v2",
    .bits = 16 | 32 | 64,
    .endian = RZ_SYS_ENDIAN_LITTLE | RZ_SYS_ENDIAN_BIG,
    .disassemble = &disassemble,
    .mnemonics = mnemonics,
    .assemble = &assemble
}

Definition at line 88 of file asm_mips_cs.c.