|
| int | capstone.arm64_const.ARM64_SFT_INVALID = 0 |
| |
| int | capstone.arm64_const.ARM64_SFT_LSL = 1 |
| |
| int | capstone.arm64_const.ARM64_SFT_MSL = 2 |
| |
| int | capstone.arm64_const.ARM64_SFT_LSR = 3 |
| |
| int | capstone.arm64_const.ARM64_SFT_ASR = 4 |
| |
| int | capstone.arm64_const.ARM64_SFT_ROR = 5 |
| |
| int | capstone.arm64_const.ARM64_EXT_INVALID = 0 |
| |
| int | capstone.arm64_const.ARM64_EXT_UXTB = 1 |
| |
| int | capstone.arm64_const.ARM64_EXT_UXTH = 2 |
| |
| int | capstone.arm64_const.ARM64_EXT_UXTW = 3 |
| |
| int | capstone.arm64_const.ARM64_EXT_UXTX = 4 |
| |
| int | capstone.arm64_const.ARM64_EXT_SXTB = 5 |
| |
| int | capstone.arm64_const.ARM64_EXT_SXTH = 6 |
| |
| int | capstone.arm64_const.ARM64_EXT_SXTW = 7 |
| |
| int | capstone.arm64_const.ARM64_EXT_SXTX = 8 |
| |
| int | capstone.arm64_const.ARM64_CC_INVALID = 0 |
| |
| int | capstone.arm64_const.ARM64_CC_EQ = 1 |
| |
| int | capstone.arm64_const.ARM64_CC_NE = 2 |
| |
| int | capstone.arm64_const.ARM64_CC_HS = 3 |
| |
| int | capstone.arm64_const.ARM64_CC_LO = 4 |
| |
| int | capstone.arm64_const.ARM64_CC_MI = 5 |
| |
| int | capstone.arm64_const.ARM64_CC_PL = 6 |
| |
| int | capstone.arm64_const.ARM64_CC_VS = 7 |
| |
| int | capstone.arm64_const.ARM64_CC_VC = 8 |
| |
| int | capstone.arm64_const.ARM64_CC_HI = 9 |
| |
| int | capstone.arm64_const.ARM64_CC_LS = 10 |
| |
| int | capstone.arm64_const.ARM64_CC_GE = 11 |
| |
| int | capstone.arm64_const.ARM64_CC_LT = 12 |
| |
| int | capstone.arm64_const.ARM64_CC_GT = 13 |
| |
| int | capstone.arm64_const.ARM64_CC_LE = 14 |
| |
| int | capstone.arm64_const.ARM64_CC_AL = 15 |
| |
| int | capstone.arm64_const.ARM64_CC_NV = 16 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_INVALID = 0 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_MDCCSR_EL0 = 0x9808 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_DBGDTRRX_EL0 = 0x9828 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_MDRAR_EL1 = 0x8080 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_OSLSR_EL1 = 0x808c |
| |
| int | capstone.arm64_const.ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 0x83f6 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_PMCEID0_EL0 = 0xdce6 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_PMCEID1_EL0 = 0xdce7 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_MIDR_EL1 = 0xc000 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_CCSIDR_EL1 = 0xc800 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_CLIDR_EL1 = 0xc801 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_CTR_EL0 = 0xd801 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_MPIDR_EL1 = 0xc005 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_REVIDR_EL1 = 0xc006 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_AIDR_EL1 = 0xc807 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_DCZID_EL0 = 0xd807 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ID_PFR0_EL1 = 0xc008 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ID_PFR1_EL1 = 0xc009 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ID_DFR0_EL1 = 0xc00a |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ID_AFR0_EL1 = 0xc00b |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ID_MMFR0_EL1 = 0xc00c |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ID_MMFR1_EL1 = 0xc00d |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ID_MMFR2_EL1 = 0xc00e |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ID_MMFR3_EL1 = 0xc00f |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ID_ISAR0_EL1 = 0xc010 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ID_ISAR1_EL1 = 0xc011 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ID_ISAR2_EL1 = 0xc012 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ID_ISAR3_EL1 = 0xc013 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ID_ISAR4_EL1 = 0xc014 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ID_ISAR5_EL1 = 0xc015 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ID_A64PFR0_EL1 = 0xc020 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ID_A64PFR1_EL1 = 0xc021 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ID_A64DFR0_EL1 = 0xc028 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ID_A64DFR1_EL1 = 0xc029 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ID_A64AFR0_EL1 = 0xc02c |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ID_A64AFR1_EL1 = 0xc02d |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ID_A64ISAR0_EL1 = 0xc030 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ID_A64ISAR1_EL1 = 0xc031 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ID_A64MMFR0_EL1 = 0xc038 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ID_A64MMFR1_EL1 = 0xc039 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_MVFR0_EL1 = 0xc018 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_MVFR1_EL1 = 0xc019 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_MVFR2_EL1 = 0xc01a |
| |
| int | capstone.arm64_const.ARM64_SYSREG_RVBAR_EL1 = 0xc601 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_RVBAR_EL2 = 0xe601 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_RVBAR_EL3 = 0xf601 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ISR_EL1 = 0xc608 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_CNTPCT_EL0 = 0xdf01 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_CNTVCT_EL0 = 0xdf02 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCSTATR = 0x8818 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCIDR8 = 0x8806 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCIDR9 = 0x880e |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCIDR10 = 0x8816 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCIDR11 = 0x881e |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCIDR12 = 0x8826 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCIDR13 = 0x882e |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCIDR0 = 0x8847 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCIDR1 = 0x884f |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCIDR2 = 0x8857 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCIDR3 = 0x885f |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCIDR4 = 0x8867 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCIDR5 = 0x886f |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCIDR6 = 0x8877 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCIDR7 = 0x887f |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCOSLSR = 0x888c |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCPDSR = 0x88ac |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCDEVAFF0 = 0x8bd6 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCDEVAFF1 = 0x8bde |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCLSR = 0x8bee |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCAUTHSTATUS = 0x8bf6 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCDEVARCH = 0x8bfe |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCDEVID = 0x8b97 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCDEVTYPE = 0x8b9f |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCPIDR4 = 0x8ba7 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCPIDR5 = 0x8baf |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCPIDR6 = 0x8bb7 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCPIDR7 = 0x8bbf |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCPIDR0 = 0x8bc7 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCPIDR1 = 0x8bcf |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCPIDR2 = 0x8bd7 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCPIDR3 = 0x8bdf |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCCIDR0 = 0x8be7 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCCIDR1 = 0x8bef |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCCIDR2 = 0x8bf7 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCCIDR3 = 0x8bff |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ICC_IAR1_EL1 = 0xc660 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ICC_IAR0_EL1 = 0xc640 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ICC_HPPIR1_EL1 = 0xc662 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ICC_HPPIR0_EL1 = 0xc642 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ICC_RPR_EL1 = 0xc65b |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ICH_VTR_EL2 = 0xe659 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ICH_EISR_EL2 = 0xe65b |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ICH_ELSR_EL2 = 0xe65d |
| |
| int | capstone.arm64_const.ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_OSLAR_EL1 = 0x8084 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_PMSWINC_EL0 = 0xdce4 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCOSLAR = 0x8884 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_TRCLAR = 0x8be6 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ICC_EOIR1_EL1 = 0xc661 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ICC_EOIR0_EL1 = 0xc641 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ICC_DIR_EL1 = 0xc659 |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ICC_SGI1R_EL1 = 0xc65d |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ICC_ASGI1R_EL1 = 0xc65e |
| |
| int | capstone.arm64_const.ARM64_SYSREG_ICC_SGI0R_EL1 = 0xc65f |
| |
| int | capstone.arm64_const.ARM64_PSTATE_INVALID = 0 |
| |
| int | capstone.arm64_const.ARM64_PSTATE_SPSEL = 0x05 |
| |
| int | capstone.arm64_const.ARM64_PSTATE_DAIFSET = 0x1e |
| |
| int | capstone.arm64_const.ARM64_PSTATE_DAIFCLR = 0x1f |
| |
| int | capstone.arm64_const.ARM64_VAS_INVALID = 0 |
| |
| int | capstone.arm64_const.ARM64_VAS_8B = 1 |
| |
| int | capstone.arm64_const.ARM64_VAS_16B = 2 |
| |
| int | capstone.arm64_const.ARM64_VAS_4H = 3 |
| |
| int | capstone.arm64_const.ARM64_VAS_8H = 4 |
| |
| int | capstone.arm64_const.ARM64_VAS_2S = 5 |
| |
| int | capstone.arm64_const.ARM64_VAS_4S = 6 |
| |
| int | capstone.arm64_const.ARM64_VAS_1D = 7 |
| |
| int | capstone.arm64_const.ARM64_VAS_2D = 8 |
| |
| int | capstone.arm64_const.ARM64_VAS_1Q = 9 |
| |
| int | capstone.arm64_const.ARM64_VESS_INVALID = 0 |
| |
| int | capstone.arm64_const.ARM64_VESS_B = 1 |
| |
| int | capstone.arm64_const.ARM64_VESS_H = 2 |
| |
| int | capstone.arm64_const.ARM64_VESS_S = 3 |
| |
| int | capstone.arm64_const.ARM64_VESS_D = 4 |
| |
| int | capstone.arm64_const.ARM64_BARRIER_INVALID = 0 |
| |
| int | capstone.arm64_const.ARM64_BARRIER_OSHLD = 0x1 |
| |
| int | capstone.arm64_const.ARM64_BARRIER_OSHST = 0x2 |
| |
| int | capstone.arm64_const.ARM64_BARRIER_OSH = 0x3 |
| |
| int | capstone.arm64_const.ARM64_BARRIER_NSHLD = 0x5 |
| |
| int | capstone.arm64_const.ARM64_BARRIER_NSHST = 0x6 |
| |
| int | capstone.arm64_const.ARM64_BARRIER_NSH = 0x7 |
| |
| int | capstone.arm64_const.ARM64_BARRIER_ISHLD = 0x9 |
| |
| int | capstone.arm64_const.ARM64_BARRIER_ISHST = 0xa |
| |
| int | capstone.arm64_const.ARM64_BARRIER_ISH = 0xb |
| |
| int | capstone.arm64_const.ARM64_BARRIER_LD = 0xd |
| |
| int | capstone.arm64_const.ARM64_BARRIER_ST = 0xe |
| |
| int | capstone.arm64_const.ARM64_BARRIER_SY = 0xf |
| |
| int | capstone.arm64_const.ARM64_OP_INVALID = 0 |
| |
| int | capstone.arm64_const.ARM64_OP_REG = 1 |
| |
| int | capstone.arm64_const.ARM64_OP_IMM = 2 |
| |
| int | capstone.arm64_const.ARM64_OP_MEM = 3 |
| |
| int | capstone.arm64_const.ARM64_OP_FP = 4 |
| |
| int | capstone.arm64_const.ARM64_OP_CIMM = 64 |
| |
| int | capstone.arm64_const.ARM64_OP_REG_MRS = 65 |
| |
| int | capstone.arm64_const.ARM64_OP_REG_MSR = 66 |
| |
| int | capstone.arm64_const.ARM64_OP_PSTATE = 67 |
| |
| int | capstone.arm64_const.ARM64_OP_SYS = 68 |
| |
| int | capstone.arm64_const.ARM64_OP_PREFETCH = 69 |
| |
| int | capstone.arm64_const.ARM64_OP_BARRIER = 70 |
| |
| int | capstone.arm64_const.ARM64_TLBI_INVALID = 0 |
| |
| int | capstone.arm64_const.ARM64_TLBI_VMALLE1IS = 1 |
| |
| int | capstone.arm64_const.ARM64_TLBI_VAE1IS = 2 |
| |
| int | capstone.arm64_const.ARM64_TLBI_ASIDE1IS = 3 |
| |
| int | capstone.arm64_const.ARM64_TLBI_VAAE1IS = 4 |
| |
| int | capstone.arm64_const.ARM64_TLBI_VALE1IS = 5 |
| |
| int | capstone.arm64_const.ARM64_TLBI_VAALE1IS = 6 |
| |
| int | capstone.arm64_const.ARM64_TLBI_ALLE2IS = 7 |
| |
| int | capstone.arm64_const.ARM64_TLBI_VAE2IS = 8 |
| |
| int | capstone.arm64_const.ARM64_TLBI_ALLE1IS = 9 |
| |
| int | capstone.arm64_const.ARM64_TLBI_VALE2IS = 10 |
| |
| int | capstone.arm64_const.ARM64_TLBI_VMALLS12E1IS = 11 |
| |
| int | capstone.arm64_const.ARM64_TLBI_ALLE3IS = 12 |
| |
| int | capstone.arm64_const.ARM64_TLBI_VAE3IS = 13 |
| |
| int | capstone.arm64_const.ARM64_TLBI_VALE3IS = 14 |
| |
| int | capstone.arm64_const.ARM64_TLBI_IPAS2E1IS = 15 |
| |
| int | capstone.arm64_const.ARM64_TLBI_IPAS2LE1IS = 16 |
| |
| int | capstone.arm64_const.ARM64_TLBI_IPAS2E1 = 17 |
| |
| int | capstone.arm64_const.ARM64_TLBI_IPAS2LE1 = 18 |
| |
| int | capstone.arm64_const.ARM64_TLBI_VMALLE1 = 19 |
| |
| int | capstone.arm64_const.ARM64_TLBI_VAE1 = 20 |
| |
| int | capstone.arm64_const.ARM64_TLBI_ASIDE1 = 21 |
| |
| int | capstone.arm64_const.ARM64_TLBI_VAAE1 = 22 |
| |
| int | capstone.arm64_const.ARM64_TLBI_VALE1 = 23 |
| |
| int | capstone.arm64_const.ARM64_TLBI_VAALE1 = 24 |
| |
| int | capstone.arm64_const.ARM64_TLBI_ALLE2 = 25 |
| |
| int | capstone.arm64_const.ARM64_TLBI_VAE2 = 26 |
| |
| int | capstone.arm64_const.ARM64_TLBI_ALLE1 = 27 |
| |
| int | capstone.arm64_const.ARM64_TLBI_VALE2 = 28 |
| |
| int | capstone.arm64_const.ARM64_TLBI_VMALLS12E1 = 29 |
| |
| int | capstone.arm64_const.ARM64_TLBI_ALLE3 = 30 |
| |
| int | capstone.arm64_const.ARM64_TLBI_VAE3 = 31 |
| |
| int | capstone.arm64_const.ARM64_TLBI_VALE3 = 32 |
| |
| int | capstone.arm64_const.ARM64_AT_S1E1R = 33 |
| |
| int | capstone.arm64_const.ARM64_AT_S1E1W = 34 |
| |
| int | capstone.arm64_const.ARM64_AT_S1E0R = 35 |
| |
| int | capstone.arm64_const.ARM64_AT_S1E0W = 36 |
| |
| int | capstone.arm64_const.ARM64_AT_S1E2R = 37 |
| |
| int | capstone.arm64_const.ARM64_AT_S1E2W = 38 |
| |
| int | capstone.arm64_const.ARM64_AT_S12E1R = 39 |
| |
| int | capstone.arm64_const.ARM64_AT_S12E1W = 40 |
| |
| int | capstone.arm64_const.ARM64_AT_S12E0R = 41 |
| |
| int | capstone.arm64_const.ARM64_AT_S12E0W = 42 |
| |
| int | capstone.arm64_const.ARM64_AT_S1E3R = 43 |
| |
| int | capstone.arm64_const.ARM64_AT_S1E3W = 44 |
| |
| int | capstone.arm64_const.ARM64_DC_INVALID = 0 |
| |
| int | capstone.arm64_const.ARM64_DC_ZVA = 1 |
| |
| int | capstone.arm64_const.ARM64_DC_IVAC = 2 |
| |
| int | capstone.arm64_const.ARM64_DC_ISW = 3 |
| |
| int | capstone.arm64_const.ARM64_DC_CVAC = 4 |
| |
| int | capstone.arm64_const.ARM64_DC_CSW = 5 |
| |
| int | capstone.arm64_const.ARM64_DC_CVAU = 6 |
| |
| int | capstone.arm64_const.ARM64_DC_CIVAC = 7 |
| |
| int | capstone.arm64_const.ARM64_DC_CISW = 8 |
| |
| int | capstone.arm64_const.ARM64_IC_INVALID = 0 |
| |
| int | capstone.arm64_const.ARM64_IC_IALLUIS = 1 |
| |
| int | capstone.arm64_const.ARM64_IC_IALLU = 2 |
| |
| int | capstone.arm64_const.ARM64_IC_IVAU = 3 |
| |
| int | capstone.arm64_const.ARM64_PRFM_INVALID = 0 |
| |
| int | capstone.arm64_const.ARM64_PRFM_PLDL1KEEP = 0x00+1 |
| |
| int | capstone.arm64_const.ARM64_PRFM_PLDL1STRM = 0x01+1 |
| |
| int | capstone.arm64_const.ARM64_PRFM_PLDL2KEEP = 0x02+1 |
| |
| int | capstone.arm64_const.ARM64_PRFM_PLDL2STRM = 0x03+1 |
| |
| int | capstone.arm64_const.ARM64_PRFM_PLDL3KEEP = 0x04+1 |
| |
| int | capstone.arm64_const.ARM64_PRFM_PLDL3STRM = 0x05+1 |
| |
| int | capstone.arm64_const.ARM64_PRFM_PLIL1KEEP = 0x08+1 |
| |
| int | capstone.arm64_const.ARM64_PRFM_PLIL1STRM = 0x09+1 |
| |
| int | capstone.arm64_const.ARM64_PRFM_PLIL2KEEP = 0x0a+1 |
| |
| int | capstone.arm64_const.ARM64_PRFM_PLIL2STRM = 0x0b+1 |
| |
| int | capstone.arm64_const.ARM64_PRFM_PLIL3KEEP = 0x0c+1 |
| |
| int | capstone.arm64_const.ARM64_PRFM_PLIL3STRM = 0x0d+1 |
| |
| int | capstone.arm64_const.ARM64_PRFM_PSTL1KEEP = 0x10+1 |
| |
| int | capstone.arm64_const.ARM64_PRFM_PSTL1STRM = 0x11+1 |
| |
| int | capstone.arm64_const.ARM64_PRFM_PSTL2KEEP = 0x12+1 |
| |
| int | capstone.arm64_const.ARM64_PRFM_PSTL2STRM = 0x13+1 |
| |
| int | capstone.arm64_const.ARM64_PRFM_PSTL3KEEP = 0x14+1 |
| |
| int | capstone.arm64_const.ARM64_PRFM_PSTL3STRM = 0x15+1 |
| |
| int | capstone.arm64_const.ARM64_REG_INVALID = 0 |
| |
| int | capstone.arm64_const.ARM64_REG_X29 = 1 |
| |
| int | capstone.arm64_const.ARM64_REG_X30 = 2 |
| |
| int | capstone.arm64_const.ARM64_REG_NZCV = 3 |
| |
| int | capstone.arm64_const.ARM64_REG_SP = 4 |
| |
| int | capstone.arm64_const.ARM64_REG_WSP = 5 |
| |
| int | capstone.arm64_const.ARM64_REG_WZR = 6 |
| |
| int | capstone.arm64_const.ARM64_REG_XZR = 7 |
| |
| int | capstone.arm64_const.ARM64_REG_B0 = 8 |
| |
| int | capstone.arm64_const.ARM64_REG_B1 = 9 |
| |
| int | capstone.arm64_const.ARM64_REG_B2 = 10 |
| |
| int | capstone.arm64_const.ARM64_REG_B3 = 11 |
| |
| int | capstone.arm64_const.ARM64_REG_B4 = 12 |
| |
| int | capstone.arm64_const.ARM64_REG_B5 = 13 |
| |
| int | capstone.arm64_const.ARM64_REG_B6 = 14 |
| |
| int | capstone.arm64_const.ARM64_REG_B7 = 15 |
| |
| int | capstone.arm64_const.ARM64_REG_B8 = 16 |
| |
| int | capstone.arm64_const.ARM64_REG_B9 = 17 |
| |
| int | capstone.arm64_const.ARM64_REG_B10 = 18 |
| |
| int | capstone.arm64_const.ARM64_REG_B11 = 19 |
| |
| int | capstone.arm64_const.ARM64_REG_B12 = 20 |
| |
| int | capstone.arm64_const.ARM64_REG_B13 = 21 |
| |
| int | capstone.arm64_const.ARM64_REG_B14 = 22 |
| |
| int | capstone.arm64_const.ARM64_REG_B15 = 23 |
| |
| int | capstone.arm64_const.ARM64_REG_B16 = 24 |
| |
| int | capstone.arm64_const.ARM64_REG_B17 = 25 |
| |
| int | capstone.arm64_const.ARM64_REG_B18 = 26 |
| |
| int | capstone.arm64_const.ARM64_REG_B19 = 27 |
| |
| int | capstone.arm64_const.ARM64_REG_B20 = 28 |
| |
| int | capstone.arm64_const.ARM64_REG_B21 = 29 |
| |
| int | capstone.arm64_const.ARM64_REG_B22 = 30 |
| |
| int | capstone.arm64_const.ARM64_REG_B23 = 31 |
| |
| int | capstone.arm64_const.ARM64_REG_B24 = 32 |
| |
| int | capstone.arm64_const.ARM64_REG_B25 = 33 |
| |
| int | capstone.arm64_const.ARM64_REG_B26 = 34 |
| |
| int | capstone.arm64_const.ARM64_REG_B27 = 35 |
| |
| int | capstone.arm64_const.ARM64_REG_B28 = 36 |
| |
| int | capstone.arm64_const.ARM64_REG_B29 = 37 |
| |
| int | capstone.arm64_const.ARM64_REG_B30 = 38 |
| |
| int | capstone.arm64_const.ARM64_REG_B31 = 39 |
| |
| int | capstone.arm64_const.ARM64_REG_D0 = 40 |
| |
| int | capstone.arm64_const.ARM64_REG_D1 = 41 |
| |
| int | capstone.arm64_const.ARM64_REG_D2 = 42 |
| |
| int | capstone.arm64_const.ARM64_REG_D3 = 43 |
| |
| int | capstone.arm64_const.ARM64_REG_D4 = 44 |
| |
| int | capstone.arm64_const.ARM64_REG_D5 = 45 |
| |
| int | capstone.arm64_const.ARM64_REG_D6 = 46 |
| |
| int | capstone.arm64_const.ARM64_REG_D7 = 47 |
| |
| int | capstone.arm64_const.ARM64_REG_D8 = 48 |
| |
| int | capstone.arm64_const.ARM64_REG_D9 = 49 |
| |
| int | capstone.arm64_const.ARM64_REG_D10 = 50 |
| |
| int | capstone.arm64_const.ARM64_REG_D11 = 51 |
| |
| int | capstone.arm64_const.ARM64_REG_D12 = 52 |
| |
| int | capstone.arm64_const.ARM64_REG_D13 = 53 |
| |
| int | capstone.arm64_const.ARM64_REG_D14 = 54 |
| |
| int | capstone.arm64_const.ARM64_REG_D15 = 55 |
| |
| int | capstone.arm64_const.ARM64_REG_D16 = 56 |
| |
| int | capstone.arm64_const.ARM64_REG_D17 = 57 |
| |
| int | capstone.arm64_const.ARM64_REG_D18 = 58 |
| |
| int | capstone.arm64_const.ARM64_REG_D19 = 59 |
| |
| int | capstone.arm64_const.ARM64_REG_D20 = 60 |
| |
| int | capstone.arm64_const.ARM64_REG_D21 = 61 |
| |
| int | capstone.arm64_const.ARM64_REG_D22 = 62 |
| |
| int | capstone.arm64_const.ARM64_REG_D23 = 63 |
| |
| int | capstone.arm64_const.ARM64_REG_D24 = 64 |
| |
| int | capstone.arm64_const.ARM64_REG_D25 = 65 |
| |
| int | capstone.arm64_const.ARM64_REG_D26 = 66 |
| |
| int | capstone.arm64_const.ARM64_REG_D27 = 67 |
| |
| int | capstone.arm64_const.ARM64_REG_D28 = 68 |
| |
| int | capstone.arm64_const.ARM64_REG_D29 = 69 |
| |
| int | capstone.arm64_const.ARM64_REG_D30 = 70 |
| |
| int | capstone.arm64_const.ARM64_REG_D31 = 71 |
| |
| int | capstone.arm64_const.ARM64_REG_H0 = 72 |
| |
| int | capstone.arm64_const.ARM64_REG_H1 = 73 |
| |
| int | capstone.arm64_const.ARM64_REG_H2 = 74 |
| |
| int | capstone.arm64_const.ARM64_REG_H3 = 75 |
| |
| int | capstone.arm64_const.ARM64_REG_H4 = 76 |
| |
| int | capstone.arm64_const.ARM64_REG_H5 = 77 |
| |
| int | capstone.arm64_const.ARM64_REG_H6 = 78 |
| |
| int | capstone.arm64_const.ARM64_REG_H7 = 79 |
| |
| int | capstone.arm64_const.ARM64_REG_H8 = 80 |
| |
| int | capstone.arm64_const.ARM64_REG_H9 = 81 |
| |
| int | capstone.arm64_const.ARM64_REG_H10 = 82 |
| |
| int | capstone.arm64_const.ARM64_REG_H11 = 83 |
| |
| int | capstone.arm64_const.ARM64_REG_H12 = 84 |
| |
| int | capstone.arm64_const.ARM64_REG_H13 = 85 |
| |
| int | capstone.arm64_const.ARM64_REG_H14 = 86 |
| |
| int | capstone.arm64_const.ARM64_REG_H15 = 87 |
| |
| int | capstone.arm64_const.ARM64_REG_H16 = 88 |
| |
| int | capstone.arm64_const.ARM64_REG_H17 = 89 |
| |
| int | capstone.arm64_const.ARM64_REG_H18 = 90 |
| |
| int | capstone.arm64_const.ARM64_REG_H19 = 91 |
| |
| int | capstone.arm64_const.ARM64_REG_H20 = 92 |
| |
| int | capstone.arm64_const.ARM64_REG_H21 = 93 |
| |
| int | capstone.arm64_const.ARM64_REG_H22 = 94 |
| |
| int | capstone.arm64_const.ARM64_REG_H23 = 95 |
| |
| int | capstone.arm64_const.ARM64_REG_H24 = 96 |
| |
| int | capstone.arm64_const.ARM64_REG_H25 = 97 |
| |
| int | capstone.arm64_const.ARM64_REG_H26 = 98 |
| |
| int | capstone.arm64_const.ARM64_REG_H27 = 99 |
| |
| int | capstone.arm64_const.ARM64_REG_H28 = 100 |
| |
| int | capstone.arm64_const.ARM64_REG_H29 = 101 |
| |
| int | capstone.arm64_const.ARM64_REG_H30 = 102 |
| |
| int | capstone.arm64_const.ARM64_REG_H31 = 103 |
| |
| int | capstone.arm64_const.ARM64_REG_Q0 = 104 |
| |
| int | capstone.arm64_const.ARM64_REG_Q1 = 105 |
| |
| int | capstone.arm64_const.ARM64_REG_Q2 = 106 |
| |
| int | capstone.arm64_const.ARM64_REG_Q3 = 107 |
| |
| int | capstone.arm64_const.ARM64_REG_Q4 = 108 |
| |
| int | capstone.arm64_const.ARM64_REG_Q5 = 109 |
| |
| int | capstone.arm64_const.ARM64_REG_Q6 = 110 |
| |
| int | capstone.arm64_const.ARM64_REG_Q7 = 111 |
| |
| int | capstone.arm64_const.ARM64_REG_Q8 = 112 |
| |
| int | capstone.arm64_const.ARM64_REG_Q9 = 113 |
| |
| int | capstone.arm64_const.ARM64_REG_Q10 = 114 |
| |
| int | capstone.arm64_const.ARM64_REG_Q11 = 115 |
| |
| int | capstone.arm64_const.ARM64_REG_Q12 = 116 |
| |
| int | capstone.arm64_const.ARM64_REG_Q13 = 117 |
| |
| int | capstone.arm64_const.ARM64_REG_Q14 = 118 |
| |
| int | capstone.arm64_const.ARM64_REG_Q15 = 119 |
| |
| int | capstone.arm64_const.ARM64_REG_Q16 = 120 |
| |
| int | capstone.arm64_const.ARM64_REG_Q17 = 121 |
| |
| int | capstone.arm64_const.ARM64_REG_Q18 = 122 |
| |
| int | capstone.arm64_const.ARM64_REG_Q19 = 123 |
| |
| int | capstone.arm64_const.ARM64_REG_Q20 = 124 |
| |
| int | capstone.arm64_const.ARM64_REG_Q21 = 125 |
| |
| int | capstone.arm64_const.ARM64_REG_Q22 = 126 |
| |
| int | capstone.arm64_const.ARM64_REG_Q23 = 127 |
| |
| int | capstone.arm64_const.ARM64_REG_Q24 = 128 |
| |
| int | capstone.arm64_const.ARM64_REG_Q25 = 129 |
| |
| int | capstone.arm64_const.ARM64_REG_Q26 = 130 |
| |
| int | capstone.arm64_const.ARM64_REG_Q27 = 131 |
| |
| int | capstone.arm64_const.ARM64_REG_Q28 = 132 |
| |
| int | capstone.arm64_const.ARM64_REG_Q29 = 133 |
| |
| int | capstone.arm64_const.ARM64_REG_Q30 = 134 |
| |
| int | capstone.arm64_const.ARM64_REG_Q31 = 135 |
| |
| int | capstone.arm64_const.ARM64_REG_S0 = 136 |
| |
| int | capstone.arm64_const.ARM64_REG_S1 = 137 |
| |
| int | capstone.arm64_const.ARM64_REG_S2 = 138 |
| |
| int | capstone.arm64_const.ARM64_REG_S3 = 139 |
| |
| int | capstone.arm64_const.ARM64_REG_S4 = 140 |
| |
| int | capstone.arm64_const.ARM64_REG_S5 = 141 |
| |
| int | capstone.arm64_const.ARM64_REG_S6 = 142 |
| |
| int | capstone.arm64_const.ARM64_REG_S7 = 143 |
| |
| int | capstone.arm64_const.ARM64_REG_S8 = 144 |
| |
| int | capstone.arm64_const.ARM64_REG_S9 = 145 |
| |
| int | capstone.arm64_const.ARM64_REG_S10 = 146 |
| |
| int | capstone.arm64_const.ARM64_REG_S11 = 147 |
| |
| int | capstone.arm64_const.ARM64_REG_S12 = 148 |
| |
| int | capstone.arm64_const.ARM64_REG_S13 = 149 |
| |
| int | capstone.arm64_const.ARM64_REG_S14 = 150 |
| |
| int | capstone.arm64_const.ARM64_REG_S15 = 151 |
| |
| int | capstone.arm64_const.ARM64_REG_S16 = 152 |
| |
| int | capstone.arm64_const.ARM64_REG_S17 = 153 |
| |
| int | capstone.arm64_const.ARM64_REG_S18 = 154 |
| |
| int | capstone.arm64_const.ARM64_REG_S19 = 155 |
| |
| int | capstone.arm64_const.ARM64_REG_S20 = 156 |
| |
| int | capstone.arm64_const.ARM64_REG_S21 = 157 |
| |
| int | capstone.arm64_const.ARM64_REG_S22 = 158 |
| |
| int | capstone.arm64_const.ARM64_REG_S23 = 159 |
| |
| int | capstone.arm64_const.ARM64_REG_S24 = 160 |
| |
| int | capstone.arm64_const.ARM64_REG_S25 = 161 |
| |
| int | capstone.arm64_const.ARM64_REG_S26 = 162 |
| |
| int | capstone.arm64_const.ARM64_REG_S27 = 163 |
| |
| int | capstone.arm64_const.ARM64_REG_S28 = 164 |
| |
| int | capstone.arm64_const.ARM64_REG_S29 = 165 |
| |
| int | capstone.arm64_const.ARM64_REG_S30 = 166 |
| |
| int | capstone.arm64_const.ARM64_REG_S31 = 167 |
| |
| int | capstone.arm64_const.ARM64_REG_W0 = 168 |
| |
| int | capstone.arm64_const.ARM64_REG_W1 = 169 |
| |
| int | capstone.arm64_const.ARM64_REG_W2 = 170 |
| |
| int | capstone.arm64_const.ARM64_REG_W3 = 171 |
| |
| int | capstone.arm64_const.ARM64_REG_W4 = 172 |
| |
| int | capstone.arm64_const.ARM64_REG_W5 = 173 |
| |
| int | capstone.arm64_const.ARM64_REG_W6 = 174 |
| |
| int | capstone.arm64_const.ARM64_REG_W7 = 175 |
| |
| int | capstone.arm64_const.ARM64_REG_W8 = 176 |
| |
| int | capstone.arm64_const.ARM64_REG_W9 = 177 |
| |
| int | capstone.arm64_const.ARM64_REG_W10 = 178 |
| |
| int | capstone.arm64_const.ARM64_REG_W11 = 179 |
| |
| int | capstone.arm64_const.ARM64_REG_W12 = 180 |
| |
| int | capstone.arm64_const.ARM64_REG_W13 = 181 |
| |
| int | capstone.arm64_const.ARM64_REG_W14 = 182 |
| |
| int | capstone.arm64_const.ARM64_REG_W15 = 183 |
| |
| int | capstone.arm64_const.ARM64_REG_W16 = 184 |
| |
| int | capstone.arm64_const.ARM64_REG_W17 = 185 |
| |
| int | capstone.arm64_const.ARM64_REG_W18 = 186 |
| |
| int | capstone.arm64_const.ARM64_REG_W19 = 187 |
| |
| int | capstone.arm64_const.ARM64_REG_W20 = 188 |
| |
| int | capstone.arm64_const.ARM64_REG_W21 = 189 |
| |
| int | capstone.arm64_const.ARM64_REG_W22 = 190 |
| |
| int | capstone.arm64_const.ARM64_REG_W23 = 191 |
| |
| int | capstone.arm64_const.ARM64_REG_W24 = 192 |
| |
| int | capstone.arm64_const.ARM64_REG_W25 = 193 |
| |
| int | capstone.arm64_const.ARM64_REG_W26 = 194 |
| |
| int | capstone.arm64_const.ARM64_REG_W27 = 195 |
| |
| int | capstone.arm64_const.ARM64_REG_W28 = 196 |
| |
| int | capstone.arm64_const.ARM64_REG_W29 = 197 |
| |
| int | capstone.arm64_const.ARM64_REG_W30 = 198 |
| |
| int | capstone.arm64_const.ARM64_REG_X0 = 199 |
| |
| int | capstone.arm64_const.ARM64_REG_X1 = 200 |
| |
| int | capstone.arm64_const.ARM64_REG_X2 = 201 |
| |
| int | capstone.arm64_const.ARM64_REG_X3 = 202 |
| |
| int | capstone.arm64_const.ARM64_REG_X4 = 203 |
| |
| int | capstone.arm64_const.ARM64_REG_X5 = 204 |
| |
| int | capstone.arm64_const.ARM64_REG_X6 = 205 |
| |
| int | capstone.arm64_const.ARM64_REG_X7 = 206 |
| |
| int | capstone.arm64_const.ARM64_REG_X8 = 207 |
| |
| int | capstone.arm64_const.ARM64_REG_X9 = 208 |
| |
| int | capstone.arm64_const.ARM64_REG_X10 = 209 |
| |
| int | capstone.arm64_const.ARM64_REG_X11 = 210 |
| |
| int | capstone.arm64_const.ARM64_REG_X12 = 211 |
| |
| int | capstone.arm64_const.ARM64_REG_X13 = 212 |
| |
| int | capstone.arm64_const.ARM64_REG_X14 = 213 |
| |
| int | capstone.arm64_const.ARM64_REG_X15 = 214 |
| |
| int | capstone.arm64_const.ARM64_REG_X16 = 215 |
| |
| int | capstone.arm64_const.ARM64_REG_X17 = 216 |
| |
| int | capstone.arm64_const.ARM64_REG_X18 = 217 |
| |
| int | capstone.arm64_const.ARM64_REG_X19 = 218 |
| |
| int | capstone.arm64_const.ARM64_REG_X20 = 219 |
| |
| int | capstone.arm64_const.ARM64_REG_X21 = 220 |
| |
| int | capstone.arm64_const.ARM64_REG_X22 = 221 |
| |
| int | capstone.arm64_const.ARM64_REG_X23 = 222 |
| |
| int | capstone.arm64_const.ARM64_REG_X24 = 223 |
| |
| int | capstone.arm64_const.ARM64_REG_X25 = 224 |
| |
| int | capstone.arm64_const.ARM64_REG_X26 = 225 |
| |
| int | capstone.arm64_const.ARM64_REG_X27 = 226 |
| |
| int | capstone.arm64_const.ARM64_REG_X28 = 227 |
| |
| int | capstone.arm64_const.ARM64_REG_V0 = 228 |
| |
| int | capstone.arm64_const.ARM64_REG_V1 = 229 |
| |
| int | capstone.arm64_const.ARM64_REG_V2 = 230 |
| |
| int | capstone.arm64_const.ARM64_REG_V3 = 231 |
| |
| int | capstone.arm64_const.ARM64_REG_V4 = 232 |
| |
| int | capstone.arm64_const.ARM64_REG_V5 = 233 |
| |
| int | capstone.arm64_const.ARM64_REG_V6 = 234 |
| |
| int | capstone.arm64_const.ARM64_REG_V7 = 235 |
| |
| int | capstone.arm64_const.ARM64_REG_V8 = 236 |
| |
| int | capstone.arm64_const.ARM64_REG_V9 = 237 |
| |
| int | capstone.arm64_const.ARM64_REG_V10 = 238 |
| |
| int | capstone.arm64_const.ARM64_REG_V11 = 239 |
| |
| int | capstone.arm64_const.ARM64_REG_V12 = 240 |
| |
| int | capstone.arm64_const.ARM64_REG_V13 = 241 |
| |
| int | capstone.arm64_const.ARM64_REG_V14 = 242 |
| |
| int | capstone.arm64_const.ARM64_REG_V15 = 243 |
| |
| int | capstone.arm64_const.ARM64_REG_V16 = 244 |
| |
| int | capstone.arm64_const.ARM64_REG_V17 = 245 |
| |
| int | capstone.arm64_const.ARM64_REG_V18 = 246 |
| |
| int | capstone.arm64_const.ARM64_REG_V19 = 247 |
| |
| int | capstone.arm64_const.ARM64_REG_V20 = 248 |
| |
| int | capstone.arm64_const.ARM64_REG_V21 = 249 |
| |
| int | capstone.arm64_const.ARM64_REG_V22 = 250 |
| |
| int | capstone.arm64_const.ARM64_REG_V23 = 251 |
| |
| int | capstone.arm64_const.ARM64_REG_V24 = 252 |
| |
| int | capstone.arm64_const.ARM64_REG_V25 = 253 |
| |
| int | capstone.arm64_const.ARM64_REG_V26 = 254 |
| |
| int | capstone.arm64_const.ARM64_REG_V27 = 255 |
| |
| int | capstone.arm64_const.ARM64_REG_V28 = 256 |
| |
| int | capstone.arm64_const.ARM64_REG_V29 = 257 |
| |
| int | capstone.arm64_const.ARM64_REG_V30 = 258 |
| |
| int | capstone.arm64_const.ARM64_REG_V31 = 259 |
| |
| int | capstone.arm64_const.ARM64_REG_ENDING = 260 |
| |
| int | capstone.arm64_const.ARM64_REG_IP0 = ARM64_REG_X16 |
| |
| int | capstone.arm64_const.ARM64_REG_IP1 = ARM64_REG_X17 |
| |
| int | capstone.arm64_const.ARM64_REG_FP = ARM64_REG_X29 |
| |
| int | capstone.arm64_const.ARM64_REG_LR = ARM64_REG_X30 |
| |
| int | capstone.arm64_const.ARM64_INS_INVALID = 0 |
| |
| int | capstone.arm64_const.ARM64_INS_ABS = 1 |
| |
| int | capstone.arm64_const.ARM64_INS_ADC = 2 |
| |
| int | capstone.arm64_const.ARM64_INS_ADDHN = 3 |
| |
| int | capstone.arm64_const.ARM64_INS_ADDHN2 = 4 |
| |
| int | capstone.arm64_const.ARM64_INS_ADDP = 5 |
| |
| int | capstone.arm64_const.ARM64_INS_ADD = 6 |
| |
| int | capstone.arm64_const.ARM64_INS_ADDV = 7 |
| |
| int | capstone.arm64_const.ARM64_INS_ADR = 8 |
| |
| int | capstone.arm64_const.ARM64_INS_ADRP = 9 |
| |
| int | capstone.arm64_const.ARM64_INS_AESD = 10 |
| |
| int | capstone.arm64_const.ARM64_INS_AESE = 11 |
| |
| int | capstone.arm64_const.ARM64_INS_AESIMC = 12 |
| |
| int | capstone.arm64_const.ARM64_INS_AESMC = 13 |
| |
| int | capstone.arm64_const.ARM64_INS_AND = 14 |
| |
| int | capstone.arm64_const.ARM64_INS_ASR = 15 |
| |
| int | capstone.arm64_const.ARM64_INS_B = 16 |
| |
| int | capstone.arm64_const.ARM64_INS_BFM = 17 |
| |
| int | capstone.arm64_const.ARM64_INS_BIC = 18 |
| |
| int | capstone.arm64_const.ARM64_INS_BIF = 19 |
| |
| int | capstone.arm64_const.ARM64_INS_BIT = 20 |
| |
| int | capstone.arm64_const.ARM64_INS_BL = 21 |
| |
| int | capstone.arm64_const.ARM64_INS_BLR = 22 |
| |
| int | capstone.arm64_const.ARM64_INS_BR = 23 |
| |
| int | capstone.arm64_const.ARM64_INS_BRK = 24 |
| |
| int | capstone.arm64_const.ARM64_INS_BSL = 25 |
| |
| int | capstone.arm64_const.ARM64_INS_CBNZ = 26 |
| |
| int | capstone.arm64_const.ARM64_INS_CBZ = 27 |
| |
| int | capstone.arm64_const.ARM64_INS_CCMN = 28 |
| |
| int | capstone.arm64_const.ARM64_INS_CCMP = 29 |
| |
| int | capstone.arm64_const.ARM64_INS_CLREX = 30 |
| |
| int | capstone.arm64_const.ARM64_INS_CLS = 31 |
| |
| int | capstone.arm64_const.ARM64_INS_CLZ = 32 |
| |
| int | capstone.arm64_const.ARM64_INS_CMEQ = 33 |
| |
| int | capstone.arm64_const.ARM64_INS_CMGE = 34 |
| |
| int | capstone.arm64_const.ARM64_INS_CMGT = 35 |
| |
| int | capstone.arm64_const.ARM64_INS_CMHI = 36 |
| |
| int | capstone.arm64_const.ARM64_INS_CMHS = 37 |
| |
| int | capstone.arm64_const.ARM64_INS_CMLE = 38 |
| |
| int | capstone.arm64_const.ARM64_INS_CMLT = 39 |
| |
| int | capstone.arm64_const.ARM64_INS_CMTST = 40 |
| |
| int | capstone.arm64_const.ARM64_INS_CNT = 41 |
| |
| int | capstone.arm64_const.ARM64_INS_MOV = 42 |
| |
| int | capstone.arm64_const.ARM64_INS_CRC32B = 43 |
| |
| int | capstone.arm64_const.ARM64_INS_CRC32CB = 44 |
| |
| int | capstone.arm64_const.ARM64_INS_CRC32CH = 45 |
| |
| int | capstone.arm64_const.ARM64_INS_CRC32CW = 46 |
| |
| int | capstone.arm64_const.ARM64_INS_CRC32CX = 47 |
| |
| int | capstone.arm64_const.ARM64_INS_CRC32H = 48 |
| |
| int | capstone.arm64_const.ARM64_INS_CRC32W = 49 |
| |
| int | capstone.arm64_const.ARM64_INS_CRC32X = 50 |
| |
| int | capstone.arm64_const.ARM64_INS_CSEL = 51 |
| |
| int | capstone.arm64_const.ARM64_INS_CSINC = 52 |
| |
| int | capstone.arm64_const.ARM64_INS_CSINV = 53 |
| |
| int | capstone.arm64_const.ARM64_INS_CSNEG = 54 |
| |
| int | capstone.arm64_const.ARM64_INS_DCPS1 = 55 |
| |
| int | capstone.arm64_const.ARM64_INS_DCPS2 = 56 |
| |
| int | capstone.arm64_const.ARM64_INS_DCPS3 = 57 |
| |
| int | capstone.arm64_const.ARM64_INS_DMB = 58 |
| |
| int | capstone.arm64_const.ARM64_INS_DRPS = 59 |
| |
| int | capstone.arm64_const.ARM64_INS_DSB = 60 |
| |
| int | capstone.arm64_const.ARM64_INS_DUP = 61 |
| |
| int | capstone.arm64_const.ARM64_INS_EON = 62 |
| |
| int | capstone.arm64_const.ARM64_INS_EOR = 63 |
| |
| int | capstone.arm64_const.ARM64_INS_ERET = 64 |
| |
| int | capstone.arm64_const.ARM64_INS_EXTR = 65 |
| |
| int | capstone.arm64_const.ARM64_INS_EXT = 66 |
| |
| int | capstone.arm64_const.ARM64_INS_FABD = 67 |
| |
| int | capstone.arm64_const.ARM64_INS_FABS = 68 |
| |
| int | capstone.arm64_const.ARM64_INS_FACGE = 69 |
| |
| int | capstone.arm64_const.ARM64_INS_FACGT = 70 |
| |
| int | capstone.arm64_const.ARM64_INS_FADD = 71 |
| |
| int | capstone.arm64_const.ARM64_INS_FADDP = 72 |
| |
| int | capstone.arm64_const.ARM64_INS_FCCMP = 73 |
| |
| int | capstone.arm64_const.ARM64_INS_FCCMPE = 74 |
| |
| int | capstone.arm64_const.ARM64_INS_FCMEQ = 75 |
| |
| int | capstone.arm64_const.ARM64_INS_FCMGE = 76 |
| |
| int | capstone.arm64_const.ARM64_INS_FCMGT = 77 |
| |
| int | capstone.arm64_const.ARM64_INS_FCMLE = 78 |
| |
| int | capstone.arm64_const.ARM64_INS_FCMLT = 79 |
| |
| int | capstone.arm64_const.ARM64_INS_FCMP = 80 |
| |
| int | capstone.arm64_const.ARM64_INS_FCMPE = 81 |
| |
| int | capstone.arm64_const.ARM64_INS_FCSEL = 82 |
| |
| int | capstone.arm64_const.ARM64_INS_FCVTAS = 83 |
| |
| int | capstone.arm64_const.ARM64_INS_FCVTAU = 84 |
| |
| int | capstone.arm64_const.ARM64_INS_FCVT = 85 |
| |
| int | capstone.arm64_const.ARM64_INS_FCVTL = 86 |
| |
| int | capstone.arm64_const.ARM64_INS_FCVTL2 = 87 |
| |
| int | capstone.arm64_const.ARM64_INS_FCVTMS = 88 |
| |
| int | capstone.arm64_const.ARM64_INS_FCVTMU = 89 |
| |
| int | capstone.arm64_const.ARM64_INS_FCVTNS = 90 |
| |
| int | capstone.arm64_const.ARM64_INS_FCVTNU = 91 |
| |
| int | capstone.arm64_const.ARM64_INS_FCVTN = 92 |
| |
| int | capstone.arm64_const.ARM64_INS_FCVTN2 = 93 |
| |
| int | capstone.arm64_const.ARM64_INS_FCVTPS = 94 |
| |
| int | capstone.arm64_const.ARM64_INS_FCVTPU = 95 |
| |
| int | capstone.arm64_const.ARM64_INS_FCVTXN = 96 |
| |
| int | capstone.arm64_const.ARM64_INS_FCVTXN2 = 97 |
| |
| int | capstone.arm64_const.ARM64_INS_FCVTZS = 98 |
| |
| int | capstone.arm64_const.ARM64_INS_FCVTZU = 99 |
| |
| int | capstone.arm64_const.ARM64_INS_FDIV = 100 |
| |
| int | capstone.arm64_const.ARM64_INS_FMADD = 101 |
| |
| int | capstone.arm64_const.ARM64_INS_FMAX = 102 |
| |
| int | capstone.arm64_const.ARM64_INS_FMAXNM = 103 |
| |
| int | capstone.arm64_const.ARM64_INS_FMAXNMP = 104 |
| |
| int | capstone.arm64_const.ARM64_INS_FMAXNMV = 105 |
| |
| int | capstone.arm64_const.ARM64_INS_FMAXP = 106 |
| |
| int | capstone.arm64_const.ARM64_INS_FMAXV = 107 |
| |
| int | capstone.arm64_const.ARM64_INS_FMIN = 108 |
| |
| int | capstone.arm64_const.ARM64_INS_FMINNM = 109 |
| |
| int | capstone.arm64_const.ARM64_INS_FMINNMP = 110 |
| |
| int | capstone.arm64_const.ARM64_INS_FMINNMV = 111 |
| |
| int | capstone.arm64_const.ARM64_INS_FMINP = 112 |
| |
| int | capstone.arm64_const.ARM64_INS_FMINV = 113 |
| |
| int | capstone.arm64_const.ARM64_INS_FMLA = 114 |
| |
| int | capstone.arm64_const.ARM64_INS_FMLS = 115 |
| |
| int | capstone.arm64_const.ARM64_INS_FMOV = 116 |
| |
| int | capstone.arm64_const.ARM64_INS_FMSUB = 117 |
| |
| int | capstone.arm64_const.ARM64_INS_FMUL = 118 |
| |
| int | capstone.arm64_const.ARM64_INS_FMULX = 119 |
| |
| int | capstone.arm64_const.ARM64_INS_FNEG = 120 |
| |
| int | capstone.arm64_const.ARM64_INS_FNMADD = 121 |
| |
| int | capstone.arm64_const.ARM64_INS_FNMSUB = 122 |
| |
| int | capstone.arm64_const.ARM64_INS_FNMUL = 123 |
| |
| int | capstone.arm64_const.ARM64_INS_FRECPE = 124 |
| |
| int | capstone.arm64_const.ARM64_INS_FRECPS = 125 |
| |
| int | capstone.arm64_const.ARM64_INS_FRECPX = 126 |
| |
| int | capstone.arm64_const.ARM64_INS_FRINTA = 127 |
| |
| int | capstone.arm64_const.ARM64_INS_FRINTI = 128 |
| |
| int | capstone.arm64_const.ARM64_INS_FRINTM = 129 |
| |
| int | capstone.arm64_const.ARM64_INS_FRINTN = 130 |
| |
| int | capstone.arm64_const.ARM64_INS_FRINTP = 131 |
| |
| int | capstone.arm64_const.ARM64_INS_FRINTX = 132 |
| |
| int | capstone.arm64_const.ARM64_INS_FRINTZ = 133 |
| |
| int | capstone.arm64_const.ARM64_INS_FRSQRTE = 134 |
| |
| int | capstone.arm64_const.ARM64_INS_FRSQRTS = 135 |
| |
| int | capstone.arm64_const.ARM64_INS_FSQRT = 136 |
| |
| int | capstone.arm64_const.ARM64_INS_FSUB = 137 |
| |
| int | capstone.arm64_const.ARM64_INS_HINT = 138 |
| |
| int | capstone.arm64_const.ARM64_INS_HLT = 139 |
| |
| int | capstone.arm64_const.ARM64_INS_HVC = 140 |
| |
| int | capstone.arm64_const.ARM64_INS_INS = 141 |
| |
| int | capstone.arm64_const.ARM64_INS_ISB = 142 |
| |
| int | capstone.arm64_const.ARM64_INS_LD1 = 143 |
| |
| int | capstone.arm64_const.ARM64_INS_LD1R = 144 |
| |
| int | capstone.arm64_const.ARM64_INS_LD2R = 145 |
| |
| int | capstone.arm64_const.ARM64_INS_LD2 = 146 |
| |
| int | capstone.arm64_const.ARM64_INS_LD3R = 147 |
| |
| int | capstone.arm64_const.ARM64_INS_LD3 = 148 |
| |
| int | capstone.arm64_const.ARM64_INS_LD4 = 149 |
| |
| int | capstone.arm64_const.ARM64_INS_LD4R = 150 |
| |
| int | capstone.arm64_const.ARM64_INS_LDARB = 151 |
| |
| int | capstone.arm64_const.ARM64_INS_LDARH = 152 |
| |
| int | capstone.arm64_const.ARM64_INS_LDAR = 153 |
| |
| int | capstone.arm64_const.ARM64_INS_LDAXP = 154 |
| |
| int | capstone.arm64_const.ARM64_INS_LDAXRB = 155 |
| |
| int | capstone.arm64_const.ARM64_INS_LDAXRH = 156 |
| |
| int | capstone.arm64_const.ARM64_INS_LDAXR = 157 |
| |
| int | capstone.arm64_const.ARM64_INS_LDNP = 158 |
| |
| int | capstone.arm64_const.ARM64_INS_LDP = 159 |
| |
| int | capstone.arm64_const.ARM64_INS_LDPSW = 160 |
| |
| int | capstone.arm64_const.ARM64_INS_LDRB = 161 |
| |
| int | capstone.arm64_const.ARM64_INS_LDR = 162 |
| |
| int | capstone.arm64_const.ARM64_INS_LDRH = 163 |
| |
| int | capstone.arm64_const.ARM64_INS_LDRSB = 164 |
| |
| int | capstone.arm64_const.ARM64_INS_LDRSH = 165 |
| |
| int | capstone.arm64_const.ARM64_INS_LDRSW = 166 |
| |
| int | capstone.arm64_const.ARM64_INS_LDTRB = 167 |
| |
| int | capstone.arm64_const.ARM64_INS_LDTRH = 168 |
| |
| int | capstone.arm64_const.ARM64_INS_LDTRSB = 169 |
| |
| int | capstone.arm64_const.ARM64_INS_LDTRSH = 170 |
| |
| int | capstone.arm64_const.ARM64_INS_LDTRSW = 171 |
| |
| int | capstone.arm64_const.ARM64_INS_LDTR = 172 |
| |
| int | capstone.arm64_const.ARM64_INS_LDURB = 173 |
| |
| int | capstone.arm64_const.ARM64_INS_LDUR = 174 |
| |
| int | capstone.arm64_const.ARM64_INS_LDURH = 175 |
| |
| int | capstone.arm64_const.ARM64_INS_LDURSB = 176 |
| |
| int | capstone.arm64_const.ARM64_INS_LDURSH = 177 |
| |
| int | capstone.arm64_const.ARM64_INS_LDURSW = 178 |
| |
| int | capstone.arm64_const.ARM64_INS_LDXP = 179 |
| |
| int | capstone.arm64_const.ARM64_INS_LDXRB = 180 |
| |
| int | capstone.arm64_const.ARM64_INS_LDXRH = 181 |
| |
| int | capstone.arm64_const.ARM64_INS_LDXR = 182 |
| |
| int | capstone.arm64_const.ARM64_INS_LSL = 183 |
| |
| int | capstone.arm64_const.ARM64_INS_LSR = 184 |
| |
| int | capstone.arm64_const.ARM64_INS_MADD = 185 |
| |
| int | capstone.arm64_const.ARM64_INS_MLA = 186 |
| |
| int | capstone.arm64_const.ARM64_INS_MLS = 187 |
| |
| int | capstone.arm64_const.ARM64_INS_MOVI = 188 |
| |
| int | capstone.arm64_const.ARM64_INS_MOVK = 189 |
| |
| int | capstone.arm64_const.ARM64_INS_MOVN = 190 |
| |
| int | capstone.arm64_const.ARM64_INS_MOVZ = 191 |
| |
| int | capstone.arm64_const.ARM64_INS_MRS = 192 |
| |
| int | capstone.arm64_const.ARM64_INS_MSR = 193 |
| |
| int | capstone.arm64_const.ARM64_INS_MSUB = 194 |
| |
| int | capstone.arm64_const.ARM64_INS_MUL = 195 |
| |
| int | capstone.arm64_const.ARM64_INS_MVNI = 196 |
| |
| int | capstone.arm64_const.ARM64_INS_NEG = 197 |
| |
| int | capstone.arm64_const.ARM64_INS_NOT = 198 |
| |
| int | capstone.arm64_const.ARM64_INS_ORN = 199 |
| |
| int | capstone.arm64_const.ARM64_INS_ORR = 200 |
| |
| int | capstone.arm64_const.ARM64_INS_PMULL2 = 201 |
| |
| int | capstone.arm64_const.ARM64_INS_PMULL = 202 |
| |
| int | capstone.arm64_const.ARM64_INS_PMUL = 203 |
| |
| int | capstone.arm64_const.ARM64_INS_PRFM = 204 |
| |
| int | capstone.arm64_const.ARM64_INS_PRFUM = 205 |
| |
| int | capstone.arm64_const.ARM64_INS_RADDHN = 206 |
| |
| int | capstone.arm64_const.ARM64_INS_RADDHN2 = 207 |
| |
| int | capstone.arm64_const.ARM64_INS_RBIT = 208 |
| |
| int | capstone.arm64_const.ARM64_INS_RET = 209 |
| |
| int | capstone.arm64_const.ARM64_INS_REV16 = 210 |
| |
| int | capstone.arm64_const.ARM64_INS_REV32 = 211 |
| |
| int | capstone.arm64_const.ARM64_INS_REV64 = 212 |
| |
| int | capstone.arm64_const.ARM64_INS_REV = 213 |
| |
| int | capstone.arm64_const.ARM64_INS_ROR = 214 |
| |
| int | capstone.arm64_const.ARM64_INS_RSHRN2 = 215 |
| |
| int | capstone.arm64_const.ARM64_INS_RSHRN = 216 |
| |
| int | capstone.arm64_const.ARM64_INS_RSUBHN = 217 |
| |
| int | capstone.arm64_const.ARM64_INS_RSUBHN2 = 218 |
| |
| int | capstone.arm64_const.ARM64_INS_SABAL2 = 219 |
| |
| int | capstone.arm64_const.ARM64_INS_SABAL = 220 |
| |
| int | capstone.arm64_const.ARM64_INS_SABA = 221 |
| |
| int | capstone.arm64_const.ARM64_INS_SABDL2 = 222 |
| |
| int | capstone.arm64_const.ARM64_INS_SABDL = 223 |
| |
| int | capstone.arm64_const.ARM64_INS_SABD = 224 |
| |
| int | capstone.arm64_const.ARM64_INS_SADALP = 225 |
| |
| int | capstone.arm64_const.ARM64_INS_SADDLP = 226 |
| |
| int | capstone.arm64_const.ARM64_INS_SADDLV = 227 |
| |
| int | capstone.arm64_const.ARM64_INS_SADDL2 = 228 |
| |
| int | capstone.arm64_const.ARM64_INS_SADDL = 229 |
| |
| int | capstone.arm64_const.ARM64_INS_SADDW2 = 230 |
| |
| int | capstone.arm64_const.ARM64_INS_SADDW = 231 |
| |
| int | capstone.arm64_const.ARM64_INS_SBC = 232 |
| |
| int | capstone.arm64_const.ARM64_INS_SBFM = 233 |
| |
| int | capstone.arm64_const.ARM64_INS_SCVTF = 234 |
| |
| int | capstone.arm64_const.ARM64_INS_SDIV = 235 |
| |
| int | capstone.arm64_const.ARM64_INS_SHA1C = 236 |
| |
| int | capstone.arm64_const.ARM64_INS_SHA1H = 237 |
| |
| int | capstone.arm64_const.ARM64_INS_SHA1M = 238 |
| |
| int | capstone.arm64_const.ARM64_INS_SHA1P = 239 |
| |
| int | capstone.arm64_const.ARM64_INS_SHA1SU0 = 240 |
| |
| int | capstone.arm64_const.ARM64_INS_SHA1SU1 = 241 |
| |
| int | capstone.arm64_const.ARM64_INS_SHA256H2 = 242 |
| |
| int | capstone.arm64_const.ARM64_INS_SHA256H = 243 |
| |
| int | capstone.arm64_const.ARM64_INS_SHA256SU0 = 244 |
| |
| int | capstone.arm64_const.ARM64_INS_SHA256SU1 = 245 |
| |
| int | capstone.arm64_const.ARM64_INS_SHADD = 246 |
| |
| int | capstone.arm64_const.ARM64_INS_SHLL2 = 247 |
| |
| int | capstone.arm64_const.ARM64_INS_SHLL = 248 |
| |
| int | capstone.arm64_const.ARM64_INS_SHL = 249 |
| |
| int | capstone.arm64_const.ARM64_INS_SHRN2 = 250 |
| |
| int | capstone.arm64_const.ARM64_INS_SHRN = 251 |
| |
| int | capstone.arm64_const.ARM64_INS_SHSUB = 252 |
| |
| int | capstone.arm64_const.ARM64_INS_SLI = 253 |
| |
| int | capstone.arm64_const.ARM64_INS_SMADDL = 254 |
| |
| int | capstone.arm64_const.ARM64_INS_SMAXP = 255 |
| |
| int | capstone.arm64_const.ARM64_INS_SMAXV = 256 |
| |
| int | capstone.arm64_const.ARM64_INS_SMAX = 257 |
| |
| int | capstone.arm64_const.ARM64_INS_SMC = 258 |
| |
| int | capstone.arm64_const.ARM64_INS_SMINP = 259 |
| |
| int | capstone.arm64_const.ARM64_INS_SMINV = 260 |
| |
| int | capstone.arm64_const.ARM64_INS_SMIN = 261 |
| |
| int | capstone.arm64_const.ARM64_INS_SMLAL2 = 262 |
| |
| int | capstone.arm64_const.ARM64_INS_SMLAL = 263 |
| |
| int | capstone.arm64_const.ARM64_INS_SMLSL2 = 264 |
| |
| int | capstone.arm64_const.ARM64_INS_SMLSL = 265 |
| |
| int | capstone.arm64_const.ARM64_INS_SMOV = 266 |
| |
| int | capstone.arm64_const.ARM64_INS_SMSUBL = 267 |
| |
| int | capstone.arm64_const.ARM64_INS_SMULH = 268 |
| |
| int | capstone.arm64_const.ARM64_INS_SMULL2 = 269 |
| |
| int | capstone.arm64_const.ARM64_INS_SMULL = 270 |
| |
| int | capstone.arm64_const.ARM64_INS_SQABS = 271 |
| |
| int | capstone.arm64_const.ARM64_INS_SQADD = 272 |
| |
| int | capstone.arm64_const.ARM64_INS_SQDMLAL = 273 |
| |
| int | capstone.arm64_const.ARM64_INS_SQDMLAL2 = 274 |
| |
| int | capstone.arm64_const.ARM64_INS_SQDMLSL = 275 |
| |
| int | capstone.arm64_const.ARM64_INS_SQDMLSL2 = 276 |
| |
| int | capstone.arm64_const.ARM64_INS_SQDMULH = 277 |
| |
| int | capstone.arm64_const.ARM64_INS_SQDMULL = 278 |
| |
| int | capstone.arm64_const.ARM64_INS_SQDMULL2 = 279 |
| |
| int | capstone.arm64_const.ARM64_INS_SQNEG = 280 |
| |
| int | capstone.arm64_const.ARM64_INS_SQRDMULH = 281 |
| |
| int | capstone.arm64_const.ARM64_INS_SQRSHL = 282 |
| |
| int | capstone.arm64_const.ARM64_INS_SQRSHRN = 283 |
| |
| int | capstone.arm64_const.ARM64_INS_SQRSHRN2 = 284 |
| |
| int | capstone.arm64_const.ARM64_INS_SQRSHRUN = 285 |
| |
| int | capstone.arm64_const.ARM64_INS_SQRSHRUN2 = 286 |
| |
| int | capstone.arm64_const.ARM64_INS_SQSHLU = 287 |
| |
| int | capstone.arm64_const.ARM64_INS_SQSHL = 288 |
| |
| int | capstone.arm64_const.ARM64_INS_SQSHRN = 289 |
| |
| int | capstone.arm64_const.ARM64_INS_SQSHRN2 = 290 |
| |
| int | capstone.arm64_const.ARM64_INS_SQSHRUN = 291 |
| |
| int | capstone.arm64_const.ARM64_INS_SQSHRUN2 = 292 |
| |
| int | capstone.arm64_const.ARM64_INS_SQSUB = 293 |
| |
| int | capstone.arm64_const.ARM64_INS_SQXTN2 = 294 |
| |
| int | capstone.arm64_const.ARM64_INS_SQXTN = 295 |
| |
| int | capstone.arm64_const.ARM64_INS_SQXTUN2 = 296 |
| |
| int | capstone.arm64_const.ARM64_INS_SQXTUN = 297 |
| |
| int | capstone.arm64_const.ARM64_INS_SRHADD = 298 |
| |
| int | capstone.arm64_const.ARM64_INS_SRI = 299 |
| |
| int | capstone.arm64_const.ARM64_INS_SRSHL = 300 |
| |
| int | capstone.arm64_const.ARM64_INS_SRSHR = 301 |
| |
| int | capstone.arm64_const.ARM64_INS_SRSRA = 302 |
| |
| int | capstone.arm64_const.ARM64_INS_SSHLL2 = 303 |
| |
| int | capstone.arm64_const.ARM64_INS_SSHLL = 304 |
| |
| int | capstone.arm64_const.ARM64_INS_SSHL = 305 |
| |
| int | capstone.arm64_const.ARM64_INS_SSHR = 306 |
| |
| int | capstone.arm64_const.ARM64_INS_SSRA = 307 |
| |
| int | capstone.arm64_const.ARM64_INS_SSUBL2 = 308 |
| |
| int | capstone.arm64_const.ARM64_INS_SSUBL = 309 |
| |
| int | capstone.arm64_const.ARM64_INS_SSUBW2 = 310 |
| |
| int | capstone.arm64_const.ARM64_INS_SSUBW = 311 |
| |
| int | capstone.arm64_const.ARM64_INS_ST1 = 312 |
| |
| int | capstone.arm64_const.ARM64_INS_ST2 = 313 |
| |
| int | capstone.arm64_const.ARM64_INS_ST3 = 314 |
| |
| int | capstone.arm64_const.ARM64_INS_ST4 = 315 |
| |
| int | capstone.arm64_const.ARM64_INS_STLRB = 316 |
| |
| int | capstone.arm64_const.ARM64_INS_STLRH = 317 |
| |
| int | capstone.arm64_const.ARM64_INS_STLR = 318 |
| |
| int | capstone.arm64_const.ARM64_INS_STLXP = 319 |
| |
| int | capstone.arm64_const.ARM64_INS_STLXRB = 320 |
| |
| int | capstone.arm64_const.ARM64_INS_STLXRH = 321 |
| |
| int | capstone.arm64_const.ARM64_INS_STLXR = 322 |
| |
| int | capstone.arm64_const.ARM64_INS_STNP = 323 |
| |
| int | capstone.arm64_const.ARM64_INS_STP = 324 |
| |
| int | capstone.arm64_const.ARM64_INS_STRB = 325 |
| |
| int | capstone.arm64_const.ARM64_INS_STR = 326 |
| |
| int | capstone.arm64_const.ARM64_INS_STRH = 327 |
| |
| int | capstone.arm64_const.ARM64_INS_STTRB = 328 |
| |
| int | capstone.arm64_const.ARM64_INS_STTRH = 329 |
| |
| int | capstone.arm64_const.ARM64_INS_STTR = 330 |
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| int | capstone.arm64_const.ARM64_INS_STURB = 331 |
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| int | capstone.arm64_const.ARM64_INS_STUR = 332 |
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| int | capstone.arm64_const.ARM64_INS_STURH = 333 |
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| int | capstone.arm64_const.ARM64_INS_STXP = 334 |
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| int | capstone.arm64_const.ARM64_INS_STXRB = 335 |
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| int | capstone.arm64_const.ARM64_INS_STXRH = 336 |
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| int | capstone.arm64_const.ARM64_INS_STXR = 337 |
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| int | capstone.arm64_const.ARM64_INS_SUBHN = 338 |
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| int | capstone.arm64_const.ARM64_INS_SUBHN2 = 339 |
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| int | capstone.arm64_const.ARM64_INS_SUB = 340 |
| |
| int | capstone.arm64_const.ARM64_INS_SUQADD = 341 |
| |
| int | capstone.arm64_const.ARM64_INS_SVC = 342 |
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| int | capstone.arm64_const.ARM64_INS_SYSL = 343 |
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| int | capstone.arm64_const.ARM64_INS_SYS = 344 |
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| int | capstone.arm64_const.ARM64_INS_TBL = 345 |
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| int | capstone.arm64_const.ARM64_INS_TBNZ = 346 |
| |
| int | capstone.arm64_const.ARM64_INS_TBX = 347 |
| |
| int | capstone.arm64_const.ARM64_INS_TBZ = 348 |
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| int | capstone.arm64_const.ARM64_INS_TRN1 = 349 |
| |
| int | capstone.arm64_const.ARM64_INS_TRN2 = 350 |
| |
| int | capstone.arm64_const.ARM64_INS_UABAL2 = 351 |
| |
| int | capstone.arm64_const.ARM64_INS_UABAL = 352 |
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| int | capstone.arm64_const.ARM64_INS_UABA = 353 |
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| int | capstone.arm64_const.ARM64_INS_UABDL2 = 354 |
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| int | capstone.arm64_const.ARM64_INS_UABDL = 355 |
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| int | capstone.arm64_const.ARM64_INS_UABD = 356 |
| |
| int | capstone.arm64_const.ARM64_INS_UADALP = 357 |
| |
| int | capstone.arm64_const.ARM64_INS_UADDLP = 358 |
| |
| int | capstone.arm64_const.ARM64_INS_UADDLV = 359 |
| |
| int | capstone.arm64_const.ARM64_INS_UADDL2 = 360 |
| |
| int | capstone.arm64_const.ARM64_INS_UADDL = 361 |
| |
| int | capstone.arm64_const.ARM64_INS_UADDW2 = 362 |
| |
| int | capstone.arm64_const.ARM64_INS_UADDW = 363 |
| |
| int | capstone.arm64_const.ARM64_INS_UBFM = 364 |
| |
| int | capstone.arm64_const.ARM64_INS_UCVTF = 365 |
| |
| int | capstone.arm64_const.ARM64_INS_UDIV = 366 |
| |
| int | capstone.arm64_const.ARM64_INS_UHADD = 367 |
| |
| int | capstone.arm64_const.ARM64_INS_UHSUB = 368 |
| |
| int | capstone.arm64_const.ARM64_INS_UMADDL = 369 |
| |
| int | capstone.arm64_const.ARM64_INS_UMAXP = 370 |
| |
| int | capstone.arm64_const.ARM64_INS_UMAXV = 371 |
| |
| int | capstone.arm64_const.ARM64_INS_UMAX = 372 |
| |
| int | capstone.arm64_const.ARM64_INS_UMINP = 373 |
| |
| int | capstone.arm64_const.ARM64_INS_UMINV = 374 |
| |
| int | capstone.arm64_const.ARM64_INS_UMIN = 375 |
| |
| int | capstone.arm64_const.ARM64_INS_UMLAL2 = 376 |
| |
| int | capstone.arm64_const.ARM64_INS_UMLAL = 377 |
| |
| int | capstone.arm64_const.ARM64_INS_UMLSL2 = 378 |
| |
| int | capstone.arm64_const.ARM64_INS_UMLSL = 379 |
| |
| int | capstone.arm64_const.ARM64_INS_UMOV = 380 |
| |
| int | capstone.arm64_const.ARM64_INS_UMSUBL = 381 |
| |
| int | capstone.arm64_const.ARM64_INS_UMULH = 382 |
| |
| int | capstone.arm64_const.ARM64_INS_UMULL2 = 383 |
| |
| int | capstone.arm64_const.ARM64_INS_UMULL = 384 |
| |
| int | capstone.arm64_const.ARM64_INS_UQADD = 385 |
| |
| int | capstone.arm64_const.ARM64_INS_UQRSHL = 386 |
| |
| int | capstone.arm64_const.ARM64_INS_UQRSHRN = 387 |
| |
| int | capstone.arm64_const.ARM64_INS_UQRSHRN2 = 388 |
| |
| int | capstone.arm64_const.ARM64_INS_UQSHL = 389 |
| |
| int | capstone.arm64_const.ARM64_INS_UQSHRN = 390 |
| |
| int | capstone.arm64_const.ARM64_INS_UQSHRN2 = 391 |
| |
| int | capstone.arm64_const.ARM64_INS_UQSUB = 392 |
| |
| int | capstone.arm64_const.ARM64_INS_UQXTN2 = 393 |
| |
| int | capstone.arm64_const.ARM64_INS_UQXTN = 394 |
| |
| int | capstone.arm64_const.ARM64_INS_URECPE = 395 |
| |
| int | capstone.arm64_const.ARM64_INS_URHADD = 396 |
| |
| int | capstone.arm64_const.ARM64_INS_URSHL = 397 |
| |
| int | capstone.arm64_const.ARM64_INS_URSHR = 398 |
| |
| int | capstone.arm64_const.ARM64_INS_URSQRTE = 399 |
| |
| int | capstone.arm64_const.ARM64_INS_URSRA = 400 |
| |
| int | capstone.arm64_const.ARM64_INS_USHLL2 = 401 |
| |
| int | capstone.arm64_const.ARM64_INS_USHLL = 402 |
| |
| int | capstone.arm64_const.ARM64_INS_USHL = 403 |
| |
| int | capstone.arm64_const.ARM64_INS_USHR = 404 |
| |
| int | capstone.arm64_const.ARM64_INS_USQADD = 405 |
| |
| int | capstone.arm64_const.ARM64_INS_USRA = 406 |
| |
| int | capstone.arm64_const.ARM64_INS_USUBL2 = 407 |
| |
| int | capstone.arm64_const.ARM64_INS_USUBL = 408 |
| |
| int | capstone.arm64_const.ARM64_INS_USUBW2 = 409 |
| |
| int | capstone.arm64_const.ARM64_INS_USUBW = 410 |
| |
| int | capstone.arm64_const.ARM64_INS_UZP1 = 411 |
| |
| int | capstone.arm64_const.ARM64_INS_UZP2 = 412 |
| |
| int | capstone.arm64_const.ARM64_INS_XTN2 = 413 |
| |
| int | capstone.arm64_const.ARM64_INS_XTN = 414 |
| |
| int | capstone.arm64_const.ARM64_INS_ZIP1 = 415 |
| |
| int | capstone.arm64_const.ARM64_INS_ZIP2 = 416 |
| |
| int | capstone.arm64_const.ARM64_INS_MNEG = 417 |
| |
| int | capstone.arm64_const.ARM64_INS_UMNEGL = 418 |
| |
| int | capstone.arm64_const.ARM64_INS_SMNEGL = 419 |
| |
| int | capstone.arm64_const.ARM64_INS_NOP = 420 |
| |
| int | capstone.arm64_const.ARM64_INS_YIELD = 421 |
| |
| int | capstone.arm64_const.ARM64_INS_WFE = 422 |
| |
| int | capstone.arm64_const.ARM64_INS_WFI = 423 |
| |
| int | capstone.arm64_const.ARM64_INS_SEV = 424 |
| |
| int | capstone.arm64_const.ARM64_INS_SEVL = 425 |
| |
| int | capstone.arm64_const.ARM64_INS_NGC = 426 |
| |
| int | capstone.arm64_const.ARM64_INS_SBFIZ = 427 |
| |
| int | capstone.arm64_const.ARM64_INS_UBFIZ = 428 |
| |
| int | capstone.arm64_const.ARM64_INS_SBFX = 429 |
| |
| int | capstone.arm64_const.ARM64_INS_UBFX = 430 |
| |
| int | capstone.arm64_const.ARM64_INS_BFI = 431 |
| |
| int | capstone.arm64_const.ARM64_INS_BFXIL = 432 |
| |
| int | capstone.arm64_const.ARM64_INS_CMN = 433 |
| |
| int | capstone.arm64_const.ARM64_INS_MVN = 434 |
| |
| int | capstone.arm64_const.ARM64_INS_TST = 435 |
| |
| int | capstone.arm64_const.ARM64_INS_CSET = 436 |
| |
| int | capstone.arm64_const.ARM64_INS_CINC = 437 |
| |
| int | capstone.arm64_const.ARM64_INS_CSETM = 438 |
| |
| int | capstone.arm64_const.ARM64_INS_CINV = 439 |
| |
| int | capstone.arm64_const.ARM64_INS_CNEG = 440 |
| |
| int | capstone.arm64_const.ARM64_INS_SXTB = 441 |
| |
| int | capstone.arm64_const.ARM64_INS_SXTH = 442 |
| |
| int | capstone.arm64_const.ARM64_INS_SXTW = 443 |
| |
| int | capstone.arm64_const.ARM64_INS_CMP = 444 |
| |
| int | capstone.arm64_const.ARM64_INS_UXTB = 445 |
| |
| int | capstone.arm64_const.ARM64_INS_UXTH = 446 |
| |
| int | capstone.arm64_const.ARM64_INS_UXTW = 447 |
| |
| int | capstone.arm64_const.ARM64_INS_IC = 448 |
| |
| int | capstone.arm64_const.ARM64_INS_DC = 449 |
| |
| int | capstone.arm64_const.ARM64_INS_AT = 450 |
| |
| int | capstone.arm64_const.ARM64_INS_TLBI = 451 |
| |
| int | capstone.arm64_const.ARM64_INS_NEGS = 452 |
| |
| int | capstone.arm64_const.ARM64_INS_NGCS = 453 |
| |
| int | capstone.arm64_const.ARM64_INS_ENDING = 454 |
| |
| int | capstone.arm64_const.ARM64_GRP_INVALID = 0 |
| |
| int | capstone.arm64_const.ARM64_GRP_JUMP = 1 |
| |
| int | capstone.arm64_const.ARM64_GRP_CALL = 2 |
| |
| int | capstone.arm64_const.ARM64_GRP_RET = 3 |
| |
| int | capstone.arm64_const.ARM64_GRP_INT = 4 |
| |
| int | capstone.arm64_const.ARM64_GRP_PRIVILEGE = 6 |
| |
| int | capstone.arm64_const.ARM64_GRP_BRANCH_RELATIVE = 7 |
| |
| int | capstone.arm64_const.ARM64_GRP_CRYPTO = 128 |
| |
| int | capstone.arm64_const.ARM64_GRP_FPARMV8 = 129 |
| |
| int | capstone.arm64_const.ARM64_GRP_NEON = 130 |
| |
| int | capstone.arm64_const.ARM64_GRP_CRC = 131 |
| |
| int | capstone.arm64_const.ARM64_GRP_ENDING = 132 |
| |
1.9.1 
