Rizin
unix-like reverse engineering framework and cli tools
analysis_il_trace.c
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1 // SPDX-FileCopyrightText: 2021 heersin <teablearcher@gmail.com>
2 // SPDX-License-Identifier: LGPL-3.0-only
3 
4 #include <rz_analysis.h>
5 
14 static void htup_vector_free(HtUPKv *kv) {
15  rz_vector_free(kv->value);
16 }
17 
26  size_t i;
28  if (!trace) {
29  return NULL;
30  }
31 
32  // TODO : maybe we could remove memory && register in rzil trace ?
33  trace->registers = ht_up_new(NULL, htup_vector_free, NULL);
34  if (!trace->registers) {
35  RZ_LOG_ERROR("rzil: Cannot allocate hasmap for trace registers\n");
36  goto error;
37  }
38  trace->memory = ht_up_new(NULL, htup_vector_free, NULL);
39  if (!trace->memory) {
40  RZ_LOG_ERROR("rzil: Cannot allocate hasmap for trace memory\n");
41  goto error;
42  }
44  if (!trace->instructions) {
45  RZ_LOG_ERROR("rzil: Cannot allocate vector for trace instructions\n");
46  goto error;
47  }
48 
49  // TODO : Integrate with stack panel in the future
50 
51  // Save initial registers arenas
52  for (i = 0; i < RZ_REG_TYPE_LAST; i++) {
53  RzRegArena *a = analysis->reg->regset[i].arena;
54  RzRegArena *b = rz_reg_arena_new(a->size);
55  if (!b) {
56  RZ_LOG_ERROR("rzil: Cannot allocate register arena for trace\n");
57  goto error;
58  }
59  if (b->bytes && a->bytes && b->size > 0) {
60  memcpy(b->bytes, a->bytes, b->size);
61  }
62  trace->arena[i] = b;
63  }
64  return trace;
65 error:
67  return NULL;
68 }
69 
75  size_t i;
76  if (!trace) {
77  return;
78  }
79 
80  ht_up_free(trace->registers);
81  ht_up_free(trace->memory);
82  for (i = 0; i < RZ_REG_TYPE_LAST; i++) {
83  rz_reg_arena_free(trace->arena[i]);
84  }
86  trace->instructions = NULL;
87  RZ_FREE(trace);
88 }
89 
98  // TODO : rewrite this file when migrate to new op structure
99 }
static void htup_vector_free(HtUPKv *kv)
RZ_API RzAnalysisRzilTrace * rz_analysis_rzil_trace_new(RzAnalysis *analysis, RZ_NONNULL RzAnalysisILVM *rzil)
RZ_API void rz_analysis_rzil_trace_op(RzAnalysis *analysis, RZ_NONNULL RzAnalysisILVM *rzil, RZ_NONNULL RzAnalysisLiftedILOp op)
RZ_API void rz_analysis_rzil_trace_free(RzAnalysisEsilTrace *trace)
lzma_index ** i
Definition: index.h:629
RZ_API RzRegArena * rz_reg_arena_new(size_t size)
Definition: arena.c:170
RZ_API void rz_reg_arena_free(RzRegArena *ra)
Definition: arena.c:189
#define RZ_API
#define NULL
Definition: cris-opc.c:27
RZ_API void rz_analysis_esil_trace_free(RzAnalysisEsilTrace *trace)
Definition: esil_trace.c:79
RZ_API void rz_analysis_il_trace_instruction_free(RzILTraceInstruction *instruction)
Definition: il_trace.c:53
memcpy(mem, inblock.get(), min(CONTAINING_RECORD(inblock.get(), MEMBLOCK, data) ->size, size))
#define rz_return_val_if_fail(expr, val)
Definition: rz_assert.h:108
#define RZ_LOG_ERROR(fmtstr,...)
Definition: rz_log.h:58
@ RZ_REG_TYPE_LAST
Definition: rz_reg.h:34
#define RZ_NEW0(x)
Definition: rz_types.h:284
#define RZ_NONNULL
Definition: rz_types.h:64
#define RZ_FREE(x)
Definition: rz_types.h:369
RZ_API RzPVector * rz_pvector_new(RzPVectorFree free)
Definition: vector.c:302
void(* RzPVectorFree)(void *e)
Definition: rz_vector.h:43
RZ_API void rz_vector_free(RzVector *vec)
Definition: vector.c:75
RZ_API void rz_pvector_free(RzPVector *vec)
Definition: vector.c:336
#define b(i)
Definition: sha256.c:42
#define a(i)
Definition: sha256.c:41
RzRegArena * arena[RZ_REG_TYPE_LAST]
Definition: rz_analysis.h:1017
High-level RzIL vm to emulate disassembled code.
Definition: rz_analysis.h:1155
RzRegArena * arena
Definition: rz_reg.h:136
RzRegSet regset[RZ_REG_TYPE_LAST]
Definition: rz_reg.h:150
Definition: dis.c:32
void error(const char *msg)
Definition: untgz.c:593