Rizin
unix-like reverse engineering framework and cli tools
XCoreDisassembler.c
Go to the documentation of this file.
1 //===------ XCoreDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 /* Capstone Disassembly Engine */
11 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
12 
13 #ifdef CAPSTONE_HAS_XCORE
14 
15 #include <stdio.h> // DEBUG
16 #include <stdlib.h>
17 #include <string.h>
18 
19 #include "../../cs_priv.h"
20 #include "../../utils.h"
21 
22 #include "XCoreDisassembler.h"
23 
24 #include "../../MCInst.h"
25 #include "../../MCInstrDesc.h"
26 #include "../../MCFixedLenDisassembler.h"
27 #include "../../MCRegisterInfo.h"
28 #include "../../MCDisassembler.h"
29 #include "../../MathExtras.h"
30 
31 static uint64_t getFeatureBits(int mode)
32 {
33  // support everything
34  return (uint64_t)-1;
35 }
36 
37 static bool readInstruction16(const uint8_t *code, size_t code_len, uint16_t *insn)
38 {
39  if (code_len < 2)
40  // insufficient data
41  return false;
42 
43  // Encoded as a little-endian 16-bit word in the stream.
44  *insn = (code[0] << 0) | (code[1] << 8);
45  return true;
46 }
47 
48 static bool readInstruction32(const uint8_t *code, size_t code_len, uint32_t *insn)
49 {
50  if (code_len < 4)
51  // insufficient data
52  return false;
53 
54  // Encoded as a little-endian 32-bit word in the stream.
55  *insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) | ((uint32_t) code[3] << 24);
56 
57  return true;
58 }
59 
60 static unsigned getReg(const MCRegisterInfo *MRI, unsigned RC, unsigned RegNo)
61 {
62  const MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC);
63  return rc->RegsBegin[RegNo];
64 }
65 
66 static DecodeStatus DecodeGRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
67  uint64_t Address, const void *Decoder);
68 
69 static DecodeStatus DecodeRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
70  uint64_t Address, const void *Decoder);
71 
72 static DecodeStatus DecodeBitpOperand(MCInst *Inst, unsigned Val,
73  uint64_t Address, const void *Decoder);
74 
75 static DecodeStatus DecodeNegImmOperand(MCInst *Inst, unsigned Val,
76  uint64_t Address, const void *Decoder);
77 
78 static DecodeStatus Decode2RInstruction(MCInst *Inst, unsigned Insn,
79  uint64_t Address, const void *Decoder);
80 
81 static DecodeStatus Decode2RImmInstruction(MCInst *Inst, unsigned Insn,
82  uint64_t Address, const void *Decoder);
83 
84 static DecodeStatus DecodeR2RInstruction(MCInst *Inst, unsigned Insn,
85  uint64_t Address, const void *Decoder);
86 
87 static DecodeStatus Decode2RSrcDstInstruction(MCInst *Inst, unsigned Insn,
88  uint64_t Address, const void *Decoder);
89 
90 static DecodeStatus DecodeRUSInstruction(MCInst *Inst, unsigned Insn,
91  uint64_t Address, const void *Decoder);
92 
93 static DecodeStatus DecodeRUSBitpInstruction(MCInst *Inst, unsigned Insn,
94  uint64_t Address, const void *Decoder);
95 
96 static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst *Inst, unsigned Insn,
97  uint64_t Address, const void *Decoder);
98 
99 static DecodeStatus DecodeL2RInstruction(MCInst *Inst, unsigned Insn,
100  uint64_t Address, const void *Decoder);
101 
102 static DecodeStatus DecodeLR2RInstruction(MCInst *Inst, unsigned Insn,
103  uint64_t Address, const void *Decoder);
104 
105 static DecodeStatus Decode3RInstruction(MCInst *Inst, unsigned Insn,
106  uint64_t Address, const void *Decoder);
107 
108 static DecodeStatus Decode3RImmInstruction(MCInst *Inst, unsigned Insn,
109  uint64_t Address, const void *Decoder);
110 
111 static DecodeStatus Decode2RUSInstruction(MCInst *Inst, unsigned Insn,
112  uint64_t Address, const void *Decoder);
113 
114 static DecodeStatus Decode2RUSBitpInstruction(MCInst *Inst, unsigned Insn,
115  uint64_t Address, const void *Decoder);
116 
117 static DecodeStatus DecodeL3RInstruction(MCInst *Inst, unsigned Insn,
118  uint64_t Address, const void *Decoder);
119 
120 static DecodeStatus DecodeL3RSrcDstInstruction(MCInst *Inst, unsigned Insn,
121  uint64_t Address, const void *Decoder);
122 
123 static DecodeStatus DecodeL2RUSInstruction(MCInst *Inst, unsigned Insn,
124  uint64_t Address, const void *Decoder);
125 
126 static DecodeStatus DecodeL2RUSBitpInstruction(MCInst *Inst, unsigned Insn,
127  uint64_t Address, const void *Decoder);
128 
129 static DecodeStatus DecodeL6RInstruction(MCInst *Inst, unsigned Insn,
130  uint64_t Address, const void *Decoder);
131 
132 static DecodeStatus DecodeL5RInstruction(MCInst *Inst, unsigned Insn,
133  uint64_t Address, const void *Decoder);
134 
135 static DecodeStatus DecodeL4RSrcDstInstruction(MCInst *Inst, unsigned Insn,
136  uint64_t Address, const void *Decoder);
137 
138 static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst *Inst, unsigned Insn,
139  uint64_t Address, const void *Decoder);
140 
141 #include "XCoreGenDisassemblerTables.inc"
142 
143 #define GET_REGINFO_ENUM
144 #define GET_REGINFO_MC_DESC
145 #include "XCoreGenRegisterInfo.inc"
146 
147 static DecodeStatus DecodeGRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
148  uint64_t Address, const void *Decoder)
149 {
150  unsigned Reg;
151 
152  if (RegNo > 11)
153  return MCDisassembler_Fail;
154 
155  Reg = getReg(Decoder, XCore_GRRegsRegClassID, RegNo);
156  MCOperand_CreateReg0(Inst, Reg);
157 
158  return MCDisassembler_Success;
159 }
160 
161 static DecodeStatus DecodeRRegsRegisterClass(MCInst *Inst, unsigned RegNo,
162  uint64_t Address, const void *Decoder)
163 {
164  unsigned Reg;
165  if (RegNo > 15)
166  return MCDisassembler_Fail;
167 
168  Reg = getReg(Decoder, XCore_RRegsRegClassID, RegNo);
169  MCOperand_CreateReg0(Inst, Reg);
170 
171  return MCDisassembler_Success;
172 }
173 
174 static DecodeStatus DecodeBitpOperand(MCInst *Inst, unsigned Val,
175  uint64_t Address, const void *Decoder)
176 {
177  static const unsigned Values[] = {
178  32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32
179  };
180 
181  if (Val > 11)
182  return MCDisassembler_Fail;
183 
184  MCOperand_CreateImm0(Inst, Values[Val]);
185  return MCDisassembler_Success;
186 }
187 
188 static DecodeStatus DecodeNegImmOperand(MCInst *Inst, unsigned Val,
189  uint64_t Address, const void *Decoder)
190 {
191  MCOperand_CreateImm0(Inst, -(int64_t)Val);
192  return MCDisassembler_Success;
193 }
194 
195 static DecodeStatus Decode2OpInstruction(unsigned Insn, unsigned *Op1, unsigned *Op2)
196 {
197  unsigned Op1High, Op2High;
198  unsigned Combined = fieldFromInstruction_4(Insn, 6, 5);
199 
200  if (Combined < 27)
201  return MCDisassembler_Fail;
202 
203  if (fieldFromInstruction_4(Insn, 5, 1)) {
204  if (Combined == 31)
205  return MCDisassembler_Fail;
206  Combined += 5;
207  }
208 
209  Combined -= 27;
210  Op1High = Combined % 3;
211  Op2High = Combined / 3;
212  *Op1 = (Op1High << 2) | fieldFromInstruction_4(Insn, 2, 2);
213  *Op2 = (Op2High << 2) | fieldFromInstruction_4(Insn, 0, 2);
214 
215  return MCDisassembler_Success;
216 }
217 
218 static DecodeStatus Decode3OpInstruction(unsigned Insn,
219  unsigned *Op1, unsigned *Op2, unsigned *Op3)
220 {
221  unsigned Op1High, Op2High, Op3High;
222  unsigned Combined = fieldFromInstruction_4(Insn, 6, 5);
223  if (Combined >= 27)
224  return MCDisassembler_Fail;
225 
226  Op1High = Combined % 3;
227  Op2High = (Combined / 3) % 3;
228  Op3High = Combined / 9;
229  *Op1 = (Op1High << 2) | fieldFromInstruction_4(Insn, 4, 2);
230  *Op2 = (Op2High << 2) | fieldFromInstruction_4(Insn, 2, 2);
231  *Op3 = (Op3High << 2) | fieldFromInstruction_4(Insn, 0, 2);
232 
233  return MCDisassembler_Success;
234 }
235 
236 #define GET_INSTRINFO_ENUM
237 #include "XCoreGenInstrInfo.inc"
238 static DecodeStatus Decode2OpInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address,
239  const void *Decoder)
240 {
241  // Try and decode as a 3R instruction.
242  unsigned Opcode = fieldFromInstruction_4(Insn, 11, 5);
243  switch (Opcode) {
244  case 0x0:
245  MCInst_setOpcode(Inst, XCore_STW_2rus);
246  return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
247  case 0x1:
248  MCInst_setOpcode(Inst, XCore_LDW_2rus);
249  return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
250  case 0x2:
251  MCInst_setOpcode(Inst, XCore_ADD_3r);
252  return Decode3RInstruction(Inst, Insn, Address, Decoder);
253  case 0x3:
254  MCInst_setOpcode(Inst, XCore_SUB_3r);
255  return Decode3RInstruction(Inst, Insn, Address, Decoder);
256  case 0x4:
257  MCInst_setOpcode(Inst, XCore_SHL_3r);
258  return Decode3RInstruction(Inst, Insn, Address, Decoder);
259  case 0x5:
260  MCInst_setOpcode(Inst, XCore_SHR_3r);
261  return Decode3RInstruction(Inst, Insn, Address, Decoder);
262  case 0x6:
263  MCInst_setOpcode(Inst, XCore_EQ_3r);
264  return Decode3RInstruction(Inst, Insn, Address, Decoder);
265  case 0x7:
266  MCInst_setOpcode(Inst, XCore_AND_3r);
267  return Decode3RInstruction(Inst, Insn, Address, Decoder);
268  case 0x8:
269  MCInst_setOpcode(Inst, XCore_OR_3r);
270  return Decode3RInstruction(Inst, Insn, Address, Decoder);
271  case 0x9:
272  MCInst_setOpcode(Inst, XCore_LDW_3r);
273  return Decode3RInstruction(Inst, Insn, Address, Decoder);
274  case 0x10:
275  MCInst_setOpcode(Inst, XCore_LD16S_3r);
276  return Decode3RInstruction(Inst, Insn, Address, Decoder);
277  case 0x11:
278  MCInst_setOpcode(Inst, XCore_LD8U_3r);
279  return Decode3RInstruction(Inst, Insn, Address, Decoder);
280  case 0x12:
281  MCInst_setOpcode(Inst, XCore_ADD_2rus);
282  return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
283  case 0x13:
284  MCInst_setOpcode(Inst, XCore_SUB_2rus);
285  return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
286  case 0x14:
287  MCInst_setOpcode(Inst, XCore_SHL_2rus);
288  return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
289  case 0x15:
290  MCInst_setOpcode(Inst, XCore_SHR_2rus);
291  return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
292  case 0x16:
293  MCInst_setOpcode(Inst, XCore_EQ_2rus);
294  return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
295  case 0x17:
296  MCInst_setOpcode(Inst, XCore_TSETR_3r);
297  return Decode3RImmInstruction(Inst, Insn, Address, Decoder);
298  case 0x18:
299  MCInst_setOpcode(Inst, XCore_LSS_3r);
300  return Decode3RInstruction(Inst, Insn, Address, Decoder);
301  case 0x19:
302  MCInst_setOpcode(Inst, XCore_LSU_3r);
303  return Decode3RInstruction(Inst, Insn, Address, Decoder);
304  }
305 
306  return MCDisassembler_Fail;
307 }
308 
309 static DecodeStatus Decode2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
310  const void *Decoder)
311 {
312  unsigned Op1, Op2;
313  DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
314  if (S != MCDisassembler_Success)
315  return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
316 
317  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
318  DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
319 
320  return S;
321 }
322 
323 static DecodeStatus Decode2RImmInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
324  const void *Decoder)
325 {
326  unsigned Op1, Op2;
327  DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
328  if (S != MCDisassembler_Success)
329  return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
330 
331  MCOperand_CreateImm0(Inst, Op1);
332  DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
333 
334  return S;
335 }
336 
337 static DecodeStatus DecodeR2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
338  const void *Decoder)
339 {
340  unsigned Op1, Op2;
341  DecodeStatus S = Decode2OpInstruction(Insn, &Op2, &Op1);
342  if (S != MCDisassembler_Success)
343  return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
344 
345  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
346  DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
347 
348  return S;
349 }
350 
351 static DecodeStatus Decode2RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
352  const void *Decoder)
353 {
354  unsigned Op1, Op2;
355  DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
356  if (S != MCDisassembler_Success)
357  return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
358 
359  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
360  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
361  DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
362 
363  return S;
364 }
365 
366 static DecodeStatus DecodeRUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
367  const void *Decoder)
368 {
369  unsigned Op1, Op2;
370  DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
371  if (S != MCDisassembler_Success)
372  return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
373 
374  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
375  MCOperand_CreateImm0(Inst, Op2);
376 
377  return S;
378 }
379 
380 static DecodeStatus DecodeRUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
381  const void *Decoder)
382 {
383  unsigned Op1, Op2;
384  DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
385  if (S != MCDisassembler_Success)
386  return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
387 
388  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
389  DecodeBitpOperand(Inst, Op2, Address, Decoder);
390 
391  return S;
392 }
393 
394 static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
395  const void *Decoder)
396 {
397  unsigned Op1, Op2;
398  DecodeStatus S = Decode2OpInstruction(Insn, &Op1, &Op2);
399  if (S != MCDisassembler_Success)
400  return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
401 
402  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
403  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
404  DecodeBitpOperand(Inst, Op2, Address, Decoder);
405 
406  return S;
407 }
408 
409 static DecodeStatus DecodeL2OpInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address,
410  const void *Decoder)
411 {
412  // Try and decode as a L3R / L2RUS instruction.
413  unsigned Opcode = fieldFromInstruction_4(Insn, 16, 4) |
414  fieldFromInstruction_4(Insn, 27, 5) << 4;
415  switch (Opcode) {
416  case 0x0c:
417  MCInst_setOpcode(Inst, XCore_STW_l3r);
418  return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
419  case 0x1c:
420  MCInst_setOpcode(Inst, XCore_XOR_l3r);
421  return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
422  case 0x2c:
423  MCInst_setOpcode(Inst, XCore_ASHR_l3r);
424  return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
425  case 0x3c:
426  MCInst_setOpcode(Inst, XCore_LDAWF_l3r);
427  return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
428  case 0x4c:
429  MCInst_setOpcode(Inst, XCore_LDAWB_l3r);
430  return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
431  case 0x5c:
432  MCInst_setOpcode(Inst, XCore_LDA16F_l3r);
433  return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
434  case 0x6c:
435  MCInst_setOpcode(Inst, XCore_LDA16B_l3r);
436  return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
437  case 0x7c:
438  MCInst_setOpcode(Inst, XCore_MUL_l3r);
439  return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
440  case 0x8c:
441  MCInst_setOpcode(Inst, XCore_DIVS_l3r);
442  return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
443  case 0x9c:
444  MCInst_setOpcode(Inst, XCore_DIVU_l3r);
445  return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
446  case 0x10c:
447  MCInst_setOpcode(Inst, XCore_ST16_l3r);
448  return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
449  case 0x11c:
450  MCInst_setOpcode(Inst, XCore_ST8_l3r);
451  return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
452  case 0x12c:
453  MCInst_setOpcode(Inst, XCore_ASHR_l2rus);
454  return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
455  case 0x12d:
456  MCInst_setOpcode(Inst, XCore_OUTPW_l2rus);
457  return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
458  case 0x12e:
459  MCInst_setOpcode(Inst, XCore_INPW_l2rus);
460  return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
461  case 0x13c:
462  MCInst_setOpcode(Inst, XCore_LDAWF_l2rus);
463  return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
464  case 0x14c:
465  MCInst_setOpcode(Inst, XCore_LDAWB_l2rus);
466  return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
467  case 0x15c:
468  MCInst_setOpcode(Inst, XCore_CRC_l3r);
469  return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder);
470  case 0x18c:
471  MCInst_setOpcode(Inst, XCore_REMS_l3r);
472  return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
473  case 0x19c:
474  MCInst_setOpcode(Inst, XCore_REMU_l3r);
475  return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
476  }
477 
478  return MCDisassembler_Fail;
479 }
480 
481 static DecodeStatus DecodeL2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
482  const void *Decoder)
483 {
484  unsigned Op1, Op2;
485  DecodeStatus S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2);
486  if (S != MCDisassembler_Success)
487  return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
488 
489  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
490  DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
491 
492  return S;
493 }
494 
495 static DecodeStatus DecodeLR2RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
496  const void *Decoder)
497 {
498  unsigned Op1, Op2;
499  DecodeStatus S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2);
500  if (S != MCDisassembler_Success)
501  return DecodeL2OpInstructionFail(Inst, Insn, Address, Decoder);
502 
503  DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
504  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
505 
506  return S;
507 }
508 
509 static DecodeStatus Decode3RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
510  const void *Decoder)
511 {
512  unsigned Op1, Op2, Op3;
513  DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3);
514  if (S == MCDisassembler_Success) {
515  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
516  DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
517  DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
518  }
519 
520  return S;
521 }
522 
523 static DecodeStatus Decode3RImmInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
524  const void *Decoder)
525 {
526  unsigned Op1, Op2, Op3;
527  DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3);
528  if (S == MCDisassembler_Success) {
529  MCOperand_CreateImm0(Inst, Op1);
530  DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
531  DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
532  }
533 
534  return S;
535 }
536 
537 static DecodeStatus Decode2RUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
538  const void *Decoder)
539 {
540  unsigned Op1, Op2, Op3;
541  DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3);
542  if (S == MCDisassembler_Success) {
543  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
544  DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
545  MCOperand_CreateImm0(Inst, Op3);
546  }
547 
548  return S;
549 }
550 
551 static DecodeStatus Decode2RUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
552  const void *Decoder)
553 {
554  unsigned Op1, Op2, Op3;
555  DecodeStatus S = Decode3OpInstruction(Insn, &Op1, &Op2, &Op3);
556  if (S == MCDisassembler_Success) {
557  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
558  DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
559  DecodeBitpOperand(Inst, Op3, Address, Decoder);
560  }
561 
562  return S;
563 }
564 
565 static DecodeStatus DecodeL3RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
566  const void *Decoder)
567 {
568  unsigned Op1, Op2, Op3;
569  DecodeStatus S =
570  Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
571  if (S == MCDisassembler_Success) {
572  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
573  DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
574  DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
575  }
576 
577  return S;
578 }
579 
580 static DecodeStatus DecodeL3RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
581  const void *Decoder)
582 {
583  unsigned Op1, Op2, Op3;
584  DecodeStatus S =
585  Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
586  if (S == MCDisassembler_Success) {
587  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
588  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
589  DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
590  DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
591  }
592 
593  return S;
594 }
595 
596 static DecodeStatus DecodeL2RUSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
597  const void *Decoder)
598 {
599  unsigned Op1, Op2, Op3;
600  DecodeStatus S =
601  Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
602  if (S == MCDisassembler_Success) {
603  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
604  DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
605  MCOperand_CreateImm0(Inst, Op3);
606  }
607 
608  return S;
609 }
610 
611 static DecodeStatus DecodeL2RUSBitpInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
612  const void *Decoder)
613 {
614  unsigned Op1, Op2, Op3;
615  DecodeStatus S =
616  Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
617  if (S == MCDisassembler_Success) {
618  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
619  DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
620  DecodeBitpOperand(Inst, Op3, Address, Decoder);
621  }
622 
623  return S;
624 }
625 
626 static DecodeStatus DecodeL6RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
627  const void *Decoder)
628 {
629  unsigned Op1, Op2, Op3, Op4, Op5, Op6;
630  DecodeStatus S =
631  Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
632  if (S != MCDisassembler_Success)
633  return S;
634 
635  S = Decode3OpInstruction(fieldFromInstruction_4(Insn, 16, 16), &Op4, &Op5, &Op6);
636  if (S != MCDisassembler_Success)
637  return S;
638 
639  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
640  DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
641  DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
642  DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
643  DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
644  DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder);
645  return S;
646 }
647 
648 static DecodeStatus DecodeL5RInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address,
649  const void *Decoder)
650 {
651  unsigned Opcode;
652 
653  // Try and decode as a L6R instruction.
654  MCInst_clear(Inst);
655  Opcode = fieldFromInstruction_4(Insn, 27, 5);
656  switch (Opcode) {
657  default:
658  break;
659  case 0x00:
660  MCInst_setOpcode(Inst, XCore_LMUL_l6r);
661  return DecodeL6RInstruction(Inst, Insn, Address, Decoder);
662  }
663 
664  return MCDisassembler_Fail;
665 }
666 
667 static DecodeStatus DecodeL5RInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
668  const void *Decoder)
669 {
670  unsigned Op1, Op2, Op3, Op4, Op5;
671  DecodeStatus S =
672  Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
673  if (S != MCDisassembler_Success)
674  return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
675 
676  S = Decode2OpInstruction(fieldFromInstruction_4(Insn, 16, 16), &Op4, &Op5);
677  if (S != MCDisassembler_Success)
678  return DecodeL5RInstructionFail(Inst, Insn, Address, Decoder);
679 
680  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
681  DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
682  DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
683  DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
684  DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder);
685  return S;
686 }
687 
688 static DecodeStatus DecodeL4RSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
689  const void *Decoder)
690 {
691  unsigned Op1, Op2, Op3;
692  unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4);
693  DecodeStatus S =
694  Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
695  if (S == MCDisassembler_Success) {
696  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
697  S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
698  }
699 
700  if (S == MCDisassembler_Success) {
701  DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
702  DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
703  DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
704  }
705  return S;
706 }
707 
708 static DecodeStatus DecodeL4RSrcDstSrcDstInstruction(MCInst *Inst, unsigned Insn, uint64_t Address,
709  const void *Decoder)
710 {
711  unsigned Op1, Op2, Op3;
712  unsigned Op4 = fieldFromInstruction_4(Insn, 16, 4);
713  DecodeStatus S =
714  Decode3OpInstruction(fieldFromInstruction_4(Insn, 0, 16), &Op1, &Op2, &Op3);
715  if (S == MCDisassembler_Success) {
716  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
717  S = DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
718  }
719 
720  if (S == MCDisassembler_Success) {
721  DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
722  DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder);
723  DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
724  DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
725  }
726 
727  return S;
728 }
729 
730 #define GET_SUBTARGETINFO_ENUM
731 #include "XCoreGenInstrInfo.inc"
732 bool XCore_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI,
733  uint16_t *size, uint64_t address, void *info)
734 {
735  uint16_t insn16;
736  uint32_t insn32;
737  DecodeStatus Result;
738 
739  if (!readInstruction16(code, code_len, &insn16)) {
740  return false;
741  }
742 
743  if (MI->flat_insn->detail) {
744  memset(MI->flat_insn->detail, 0, offsetof(cs_detail, xcore)+sizeof(cs_xcore));
745  }
746 
747  // Calling the auto-generated decoder function.
748  Result = decodeInstruction_2(DecoderTable16, MI, insn16, address, info, 0);
749  if (Result != MCDisassembler_Fail) {
750  *size = 2;
751  return true;
752  }
753 
754  if (!readInstruction32(code, code_len, &insn32)) {
755  return false;
756  }
757 
758  // Calling the auto-generated decoder function.
759  Result = decodeInstruction_4(DecoderTable32, MI, insn32, address, info, 0);
760  if (Result != MCDisassembler_Fail) {
761  *size = 4;
762  return true;
763  }
764 
765  return false;
766 }
767 
768 void XCore_init(MCRegisterInfo *MRI)
769 {
770  /*
771  InitMCRegisterInfo(XCoreRegDesc, 17, RA, PC,
772  XCoreMCRegisterClasses, 2,
773  XCoreRegUnitRoots,
774  16,
775  XCoreRegDiffLists,
776  XCoreRegStrings,
777  XCoreSubRegIdxLists,
778  1,
779  XCoreSubRegIdxRanges,
780  XCoreRegEncodingTable);
781  */
782 
783 
784  MCRegisterInfo_InitMCRegisterInfo(MRI, XCoreRegDesc, 17,
785  0, 0,
786  XCoreMCRegisterClasses, 2,
787  0, 0,
788  XCoreRegDiffLists,
789  0,
790  XCoreSubRegIdxLists, 1,
791  0);
792 }
793 
794 #endif
DecodeStatus
DecodeStatus
Definition: MCDisassembler.h:7
MCDisassembler_Success
@ MCDisassembler_Success
Definition: MCDisassembler.h:10
MCDisassembler_Fail
@ MCDisassembler_Fail
Definition: MCDisassembler.h:8
MCInst_clear
void MCInst_clear(MCInst *inst)
Definition: MCInst.c:40
MCOperand_CreateReg0
void MCOperand_CreateReg0(MCInst *mcInst, unsigned Reg)
Definition: MCInst.c:158
MCInst_setOpcode
void MCInst_setOpcode(MCInst *inst, unsigned Op)
Definition: MCInst.c:58
MCOperand_CreateImm0
void MCOperand_CreateImm0(MCInst *mcInst, int64_t Val)
Definition: MCInst.c:177
MCRegisterInfo_getRegClass
const MCRegisterClass * MCRegisterInfo_getRegClass(const MCRegisterInfo *RI, unsigned i)
Definition: MCRegisterInfo.c:126
MCRegisterInfo_InitMCRegisterInfo
void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI, const MCRegisterDesc *D, unsigned NR, unsigned RA, unsigned PC, const MCRegisterClass *C, unsigned NC, uint16_t(*RURoots)[2], unsigned NRU, const MCPhysReg *DL, const char *Strings, const uint16_t *SubIndices, unsigned NumIndices, const uint16_t *RET)
Definition: MCRegisterInfo.c:28
XCore_getInstruction
bool XCore_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info)
XCore_init
void XCore_init(MCRegisterInfo *MRI)
Opcode
struct Opcode_t Opcode
info
RzBinInfo * info(RzBinFile *bf)
Definition: bin_ne.c:86
csh
size_t csh
Definition: capstone.h:71
size
voidpf void uLong size
Definition: ioapi.h:138
mode
const char int mode
Definition: ioapi.h:137
offsetof
#define offsetof(type, member)
Definition: jemalloc_internal_decls.h:46
memset
return memset(p, 0, total)
uint16_t
unsigned short uint16_t
Definition: sftypes.h:30
int64_t
long int64_t
Definition: sftypes.h:32
uint32_t
unsigned int uint32_t
Definition: sftypes.h:29
uint64_t
unsigned long uint64_t
Definition: sftypes.h:28
uint8_t
unsigned char uint8_t
Definition: sftypes.h:31
MCInst
Definition: MCInst.h:88
MCInst::flat_insn
cs_insn * flat_insn
Definition: MCInst.h:95
MCRegisterClass::RegsBegin
iterator RegsBegin
Definition: MCRegisterInfo.h:30
Opcode_t
Definition: armass64.c:77
code
Definition: inftree9.h:24
cs_xcore
Instruction structure.
Definition: xcore.h:85
S
#define S
Definition: zip_err_str.c:9