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unix-like reverse engineering framework and cli tools
MipsGenRegisterInfo.inc
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1 /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2 |* *|
3 |*Target Register Enum Values *|
4 |* *|
5 |* Automatically generated file, do not edit! *|
6 |* *|
7 \*===----------------------------------------------------------------------===*/
8 
9 /* Capstone Disassembly Engine, http://www.capstone-engine.org */
10 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
11 
12 
13 #ifdef GET_REGINFO_ENUM
14 #undef GET_REGINFO_ENUM
15 
16 enum {
17  Mips_NoRegister,
18  Mips_AT = 1,
19  Mips_DSPCCond = 2,
20  Mips_DSPCarry = 3,
21  Mips_DSPEFI = 4,
22  Mips_DSPOutFlag = 5,
23  Mips_DSPPos = 6,
24  Mips_DSPSCount = 7,
25  Mips_FP = 8,
26  Mips_GP = 9,
27  Mips_MSAAccess = 10,
28  Mips_MSACSR = 11,
29  Mips_MSAIR = 12,
30  Mips_MSAMap = 13,
31  Mips_MSAModify = 14,
32  Mips_MSARequest = 15,
33  Mips_MSASave = 16,
34  Mips_MSAUnmap = 17,
35  Mips_PC = 18,
36  Mips_RA = 19,
37  Mips_SP = 20,
38  Mips_ZERO = 21,
39  Mips_A0 = 22,
40  Mips_A1 = 23,
41  Mips_A2 = 24,
42  Mips_A3 = 25,
43  Mips_AC0 = 26,
44  Mips_AC1 = 27,
45  Mips_AC2 = 28,
46  Mips_AC3 = 29,
47  Mips_AT_64 = 30,
48  Mips_CC0 = 31,
49  Mips_CC1 = 32,
50  Mips_CC2 = 33,
51  Mips_CC3 = 34,
52  Mips_CC4 = 35,
53  Mips_CC5 = 36,
54  Mips_CC6 = 37,
55  Mips_CC7 = 38,
56  Mips_COP20 = 39,
57  Mips_COP21 = 40,
58  Mips_COP22 = 41,
59  Mips_COP23 = 42,
60  Mips_COP24 = 43,
61  Mips_COP25 = 44,
62  Mips_COP26 = 45,
63  Mips_COP27 = 46,
64  Mips_COP28 = 47,
65  Mips_COP29 = 48,
66  Mips_COP30 = 49,
67  Mips_COP31 = 50,
68  Mips_COP32 = 51,
69  Mips_COP33 = 52,
70  Mips_COP34 = 53,
71  Mips_COP35 = 54,
72  Mips_COP36 = 55,
73  Mips_COP37 = 56,
74  Mips_COP38 = 57,
75  Mips_COP39 = 58,
76  Mips_COP210 = 59,
77  Mips_COP211 = 60,
78  Mips_COP212 = 61,
79  Mips_COP213 = 62,
80  Mips_COP214 = 63,
81  Mips_COP215 = 64,
82  Mips_COP216 = 65,
83  Mips_COP217 = 66,
84  Mips_COP218 = 67,
85  Mips_COP219 = 68,
86  Mips_COP220 = 69,
87  Mips_COP221 = 70,
88  Mips_COP222 = 71,
89  Mips_COP223 = 72,
90  Mips_COP224 = 73,
91  Mips_COP225 = 74,
92  Mips_COP226 = 75,
93  Mips_COP227 = 76,
94  Mips_COP228 = 77,
95  Mips_COP229 = 78,
96  Mips_COP230 = 79,
97  Mips_COP231 = 80,
98  Mips_COP310 = 81,
99  Mips_COP311 = 82,
100  Mips_COP312 = 83,
101  Mips_COP313 = 84,
102  Mips_COP314 = 85,
103  Mips_COP315 = 86,
104  Mips_COP316 = 87,
105  Mips_COP317 = 88,
106  Mips_COP318 = 89,
107  Mips_COP319 = 90,
108  Mips_COP320 = 91,
109  Mips_COP321 = 92,
110  Mips_COP322 = 93,
111  Mips_COP323 = 94,
112  Mips_COP324 = 95,
113  Mips_COP325 = 96,
114  Mips_COP326 = 97,
115  Mips_COP327 = 98,
116  Mips_COP328 = 99,
117  Mips_COP329 = 100,
118  Mips_COP330 = 101,
119  Mips_COP331 = 102,
120  Mips_D0 = 103,
121  Mips_D1 = 104,
122  Mips_D2 = 105,
123  Mips_D3 = 106,
124  Mips_D4 = 107,
125  Mips_D5 = 108,
126  Mips_D6 = 109,
127  Mips_D7 = 110,
128  Mips_D8 = 111,
129  Mips_D9 = 112,
130  Mips_D10 = 113,
131  Mips_D11 = 114,
132  Mips_D12 = 115,
133  Mips_D13 = 116,
134  Mips_D14 = 117,
135  Mips_D15 = 118,
136  Mips_DSPOutFlag20 = 119,
137  Mips_DSPOutFlag21 = 120,
138  Mips_DSPOutFlag22 = 121,
139  Mips_DSPOutFlag23 = 122,
140  Mips_F0 = 123,
141  Mips_F1 = 124,
142  Mips_F2 = 125,
143  Mips_F3 = 126,
144  Mips_F4 = 127,
145  Mips_F5 = 128,
146  Mips_F6 = 129,
147  Mips_F7 = 130,
148  Mips_F8 = 131,
149  Mips_F9 = 132,
150  Mips_F10 = 133,
151  Mips_F11 = 134,
152  Mips_F12 = 135,
153  Mips_F13 = 136,
154  Mips_F14 = 137,
155  Mips_F15 = 138,
156  Mips_F16 = 139,
157  Mips_F17 = 140,
158  Mips_F18 = 141,
159  Mips_F19 = 142,
160  Mips_F20 = 143,
161  Mips_F21 = 144,
162  Mips_F22 = 145,
163  Mips_F23 = 146,
164  Mips_F24 = 147,
165  Mips_F25 = 148,
166  Mips_F26 = 149,
167  Mips_F27 = 150,
168  Mips_F28 = 151,
169  Mips_F29 = 152,
170  Mips_F30 = 153,
171  Mips_F31 = 154,
172  Mips_FCC0 = 155,
173  Mips_FCC1 = 156,
174  Mips_FCC2 = 157,
175  Mips_FCC3 = 158,
176  Mips_FCC4 = 159,
177  Mips_FCC5 = 160,
178  Mips_FCC6 = 161,
179  Mips_FCC7 = 162,
180  Mips_FCR0 = 163,
181  Mips_FCR1 = 164,
182  Mips_FCR2 = 165,
183  Mips_FCR3 = 166,
184  Mips_FCR4 = 167,
185  Mips_FCR5 = 168,
186  Mips_FCR6 = 169,
187  Mips_FCR7 = 170,
188  Mips_FCR8 = 171,
189  Mips_FCR9 = 172,
190  Mips_FCR10 = 173,
191  Mips_FCR11 = 174,
192  Mips_FCR12 = 175,
193  Mips_FCR13 = 176,
194  Mips_FCR14 = 177,
195  Mips_FCR15 = 178,
196  Mips_FCR16 = 179,
197  Mips_FCR17 = 180,
198  Mips_FCR18 = 181,
199  Mips_FCR19 = 182,
200  Mips_FCR20 = 183,
201  Mips_FCR21 = 184,
202  Mips_FCR22 = 185,
203  Mips_FCR23 = 186,
204  Mips_FCR24 = 187,
205  Mips_FCR25 = 188,
206  Mips_FCR26 = 189,
207  Mips_FCR27 = 190,
208  Mips_FCR28 = 191,
209  Mips_FCR29 = 192,
210  Mips_FCR30 = 193,
211  Mips_FCR31 = 194,
212  Mips_FP_64 = 195,
213  Mips_F_HI0 = 196,
214  Mips_F_HI1 = 197,
215  Mips_F_HI2 = 198,
216  Mips_F_HI3 = 199,
217  Mips_F_HI4 = 200,
218  Mips_F_HI5 = 201,
219  Mips_F_HI6 = 202,
220  Mips_F_HI7 = 203,
221  Mips_F_HI8 = 204,
222  Mips_F_HI9 = 205,
223  Mips_F_HI10 = 206,
224  Mips_F_HI11 = 207,
225  Mips_F_HI12 = 208,
226  Mips_F_HI13 = 209,
227  Mips_F_HI14 = 210,
228  Mips_F_HI15 = 211,
229  Mips_F_HI16 = 212,
230  Mips_F_HI17 = 213,
231  Mips_F_HI18 = 214,
232  Mips_F_HI19 = 215,
233  Mips_F_HI20 = 216,
234  Mips_F_HI21 = 217,
235  Mips_F_HI22 = 218,
236  Mips_F_HI23 = 219,
237  Mips_F_HI24 = 220,
238  Mips_F_HI25 = 221,
239  Mips_F_HI26 = 222,
240  Mips_F_HI27 = 223,
241  Mips_F_HI28 = 224,
242  Mips_F_HI29 = 225,
243  Mips_F_HI30 = 226,
244  Mips_F_HI31 = 227,
245  Mips_GP_64 = 228,
246  Mips_HI0 = 229,
247  Mips_HI1 = 230,
248  Mips_HI2 = 231,
249  Mips_HI3 = 232,
250  Mips_HWR0 = 233,
251  Mips_HWR1 = 234,
252  Mips_HWR2 = 235,
253  Mips_HWR3 = 236,
254  Mips_HWR4 = 237,
255  Mips_HWR5 = 238,
256  Mips_HWR6 = 239,
257  Mips_HWR7 = 240,
258  Mips_HWR8 = 241,
259  Mips_HWR9 = 242,
260  Mips_HWR10 = 243,
261  Mips_HWR11 = 244,
262  Mips_HWR12 = 245,
263  Mips_HWR13 = 246,
264  Mips_HWR14 = 247,
265  Mips_HWR15 = 248,
266  Mips_HWR16 = 249,
267  Mips_HWR17 = 250,
268  Mips_HWR18 = 251,
269  Mips_HWR19 = 252,
270  Mips_HWR20 = 253,
271  Mips_HWR21 = 254,
272  Mips_HWR22 = 255,
273  Mips_HWR23 = 256,
274  Mips_HWR24 = 257,
275  Mips_HWR25 = 258,
276  Mips_HWR26 = 259,
277  Mips_HWR27 = 260,
278  Mips_HWR28 = 261,
279  Mips_HWR29 = 262,
280  Mips_HWR30 = 263,
281  Mips_HWR31 = 264,
282  Mips_K0 = 265,
283  Mips_K1 = 266,
284  Mips_LO0 = 267,
285  Mips_LO1 = 268,
286  Mips_LO2 = 269,
287  Mips_LO3 = 270,
288  Mips_MPL0 = 271,
289  Mips_MPL1 = 272,
290  Mips_MPL2 = 273,
291  Mips_P0 = 274,
292  Mips_P1 = 275,
293  Mips_P2 = 276,
294  Mips_RA_64 = 277,
295  Mips_S0 = 278,
296  Mips_S1 = 279,
297  Mips_S2 = 280,
298  Mips_S3 = 281,
299  Mips_S4 = 282,
300  Mips_S5 = 283,
301  Mips_S6 = 284,
302  Mips_S7 = 285,
303  Mips_SP_64 = 286,
304  Mips_T0 = 287,
305  Mips_T1 = 288,
306  Mips_T2 = 289,
307  Mips_T3 = 290,
308  Mips_T4 = 291,
309  Mips_T5 = 292,
310  Mips_T6 = 293,
311  Mips_T7 = 294,
312  Mips_T8 = 295,
313  Mips_T9 = 296,
314  Mips_V0 = 297,
315  Mips_V1 = 298,
316  Mips_W0 = 299,
317  Mips_W1 = 300,
318  Mips_W2 = 301,
319  Mips_W3 = 302,
320  Mips_W4 = 303,
321  Mips_W5 = 304,
322  Mips_W6 = 305,
323  Mips_W7 = 306,
324  Mips_W8 = 307,
325  Mips_W9 = 308,
326  Mips_W10 = 309,
327  Mips_W11 = 310,
328  Mips_W12 = 311,
329  Mips_W13 = 312,
330  Mips_W14 = 313,
331  Mips_W15 = 314,
332  Mips_W16 = 315,
333  Mips_W17 = 316,
334  Mips_W18 = 317,
335  Mips_W19 = 318,
336  Mips_W20 = 319,
337  Mips_W21 = 320,
338  Mips_W22 = 321,
339  Mips_W23 = 322,
340  Mips_W24 = 323,
341  Mips_W25 = 324,
342  Mips_W26 = 325,
343  Mips_W27 = 326,
344  Mips_W28 = 327,
345  Mips_W29 = 328,
346  Mips_W30 = 329,
347  Mips_W31 = 330,
348  Mips_ZERO_64 = 331,
349  Mips_A0_64 = 332,
350  Mips_A1_64 = 333,
351  Mips_A2_64 = 334,
352  Mips_A3_64 = 335,
353  Mips_AC0_64 = 336,
354  Mips_D0_64 = 337,
355  Mips_D1_64 = 338,
356  Mips_D2_64 = 339,
357  Mips_D3_64 = 340,
358  Mips_D4_64 = 341,
359  Mips_D5_64 = 342,
360  Mips_D6_64 = 343,
361  Mips_D7_64 = 344,
362  Mips_D8_64 = 345,
363  Mips_D9_64 = 346,
364  Mips_D10_64 = 347,
365  Mips_D11_64 = 348,
366  Mips_D12_64 = 349,
367  Mips_D13_64 = 350,
368  Mips_D14_64 = 351,
369  Mips_D15_64 = 352,
370  Mips_D16_64 = 353,
371  Mips_D17_64 = 354,
372  Mips_D18_64 = 355,
373  Mips_D19_64 = 356,
374  Mips_D20_64 = 357,
375  Mips_D21_64 = 358,
376  Mips_D22_64 = 359,
377  Mips_D23_64 = 360,
378  Mips_D24_64 = 361,
379  Mips_D25_64 = 362,
380  Mips_D26_64 = 363,
381  Mips_D27_64 = 364,
382  Mips_D28_64 = 365,
383  Mips_D29_64 = 366,
384  Mips_D30_64 = 367,
385  Mips_D31_64 = 368,
386  Mips_DSPOutFlag16_19 = 369,
387  Mips_HI0_64 = 370,
388  Mips_K0_64 = 371,
389  Mips_K1_64 = 372,
390  Mips_LO0_64 = 373,
391  Mips_S0_64 = 374,
392  Mips_S1_64 = 375,
393  Mips_S2_64 = 376,
394  Mips_S3_64 = 377,
395  Mips_S4_64 = 378,
396  Mips_S5_64 = 379,
397  Mips_S6_64 = 380,
398  Mips_S7_64 = 381,
399  Mips_T0_64 = 382,
400  Mips_T1_64 = 383,
401  Mips_T2_64 = 384,
402  Mips_T3_64 = 385,
403  Mips_T4_64 = 386,
404  Mips_T5_64 = 387,
405  Mips_T6_64 = 388,
406  Mips_T7_64 = 389,
407  Mips_T8_64 = 390,
408  Mips_T9_64 = 391,
409  Mips_V0_64 = 392,
410  Mips_V1_64 = 393,
411  Mips_NUM_TARGET_REGS // 394
412 };
413 
414 // Register classes
415 enum {
416  Mips_OddSPRegClassID = 0,
417  Mips_CCRRegClassID = 1,
418  Mips_COP2RegClassID = 2,
419  Mips_COP3RegClassID = 3,
420  Mips_DSPRRegClassID = 4,
421  Mips_FGR32RegClassID = 5,
422  Mips_FGRCCRegClassID = 6,
423  Mips_FGRH32RegClassID = 7,
424  Mips_GPR32RegClassID = 8,
425  Mips_HWRegsRegClassID = 9,
426  Mips_OddSP_with_sub_hiRegClassID = 10,
427  Mips_FGR32_and_OddSPRegClassID = 11,
428  Mips_FGRH32_and_OddSPRegClassID = 12,
429  Mips_OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClassID = 13,
430  Mips_CPU16RegsPlusSPRegClassID = 14,
431  Mips_CCRegClassID = 15,
432  Mips_CPU16RegsRegClassID = 16,
433  Mips_FCCRegClassID = 17,
434  Mips_GPRMM16RegClassID = 18,
435  Mips_GPRMM16MovePRegClassID = 19,
436  Mips_GPRMM16ZeroRegClassID = 20,
437  Mips_MSACtrlRegClassID = 21,
438  Mips_OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClassID = 22,
439  Mips_CPU16Regs_and_GPRMM16ZeroRegClassID = 23,
440  Mips_CPU16Regs_and_GPRMM16MovePRegClassID = 24,
441  Mips_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 25,
442  Mips_HI32DSPRegClassID = 26,
443  Mips_LO32DSPRegClassID = 27,
444  Mips_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 28,
445  Mips_CPURARegRegClassID = 29,
446  Mips_CPUSPRegRegClassID = 30,
447  Mips_DSPCCRegClassID = 31,
448  Mips_HI32RegClassID = 32,
449  Mips_LO32RegClassID = 33,
450  Mips_FGR64RegClassID = 34,
451  Mips_GPR64RegClassID = 35,
452  Mips_AFGR64RegClassID = 36,
453  Mips_FGR64_and_OddSPRegClassID = 37,
454  Mips_GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID = 38,
455  Mips_AFGR64_and_OddSPRegClassID = 39,
456  Mips_GPR64_with_sub_32_in_CPU16RegsRegClassID = 40,
457  Mips_GPR64_with_sub_32_in_GPRMM16MovePRegClassID = 41,
458  Mips_GPR64_with_sub_32_in_GPRMM16ZeroRegClassID = 42,
459  Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID = 43,
460  Mips_ACC64DSPRegClassID = 44,
461  Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID = 45,
462  Mips_GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID = 46,
463  Mips_GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID = 47,
464  Mips_OCTEON_MPLRegClassID = 48,
465  Mips_OCTEON_PRegClassID = 49,
466  Mips_ACC64RegClassID = 50,
467  Mips_GPR64_with_sub_32_in_CPURARegRegClassID = 51,
468  Mips_GPR64_with_sub_32_in_CPUSPRegRegClassID = 52,
469  Mips_HI64RegClassID = 53,
470  Mips_LO64RegClassID = 54,
471  Mips_MSA128BRegClassID = 55,
472  Mips_MSA128DRegClassID = 56,
473  Mips_MSA128HRegClassID = 57,
474  Mips_MSA128WRegClassID = 58,
475  Mips_MSA128B_with_sub_64_in_OddSPRegClassID = 59,
476  Mips_MSA128WEvensRegClassID = 60,
477  Mips_ACC128RegClassID = 61,
478 };
479 
480 #endif // GET_REGINFO_ENUM
481 
482 /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
483 |* *|
484 |*MC Register Information *|
485 |* *|
486 |* Automatically generated file, do not edit! *|
487 |* *|
488 \*===----------------------------------------------------------------------===*/
489 
490 /* Capstone Disassembly Engine, http://www.capstone-engine.org */
491 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
492 
493 
494 #ifdef GET_REGINFO_MC_DESC
495 #undef GET_REGINFO_MC_DESC
496 
497 static MCPhysReg MipsRegDiffLists[] = {
498  /* 0 */ 0, 0,
499  /* 2 */ 4, 1, 1, 1, 1, 0,
500  /* 8 */ 364, 65286, 1, 1, 1, 0,
501  /* 14 */ 20, 1, 0,
502  /* 17 */ 21, 1, 0,
503  /* 20 */ 22, 1, 0,
504  /* 23 */ 23, 1, 0,
505  /* 26 */ 24, 1, 0,
506  /* 29 */ 25, 1, 0,
507  /* 32 */ 26, 1, 0,
508  /* 35 */ 27, 1, 0,
509  /* 38 */ 28, 1, 0,
510  /* 41 */ 29, 1, 0,
511  /* 44 */ 30, 1, 0,
512  /* 47 */ 31, 1, 0,
513  /* 50 */ 32, 1, 0,
514  /* 53 */ 33, 1, 0,
515  /* 56 */ 34, 1, 0,
516  /* 59 */ 35, 1, 0,
517  /* 62 */ 65439, 1, 0,
518  /* 65 */ 65513, 1, 0,
519  /* 68 */ 3, 0,
520  /* 70 */ 4, 0,
521  /* 72 */ 6, 0,
522  /* 74 */ 11, 0,
523  /* 76 */ 12, 0,
524  /* 78 */ 22, 0,
525  /* 80 */ 23, 0,
526  /* 82 */ 29, 0,
527  /* 84 */ 30, 0,
528  /* 86 */ 65308, 72, 0,
529  /* 89 */ 65346, 72, 0,
530  /* 92 */ 38, 65322, 73, 0,
531  /* 96 */ 95, 0,
532  /* 98 */ 96, 0,
533  /* 100 */ 106, 0,
534  /* 102 */ 187, 0,
535  /* 104 */ 219, 0,
536  /* 106 */ 258, 0,
537  /* 108 */ 266, 0,
538  /* 110 */ 310, 0,
539  /* 112 */ 65031, 0,
540  /* 114 */ 65108, 0,
541  /* 116 */ 65172, 0,
542  /* 118 */ 65226, 0,
543  /* 120 */ 65229, 0,
544  /* 122 */ 65270, 0,
545  /* 124 */ 65278, 0,
546  /* 126 */ 65295, 0,
547  /* 128 */ 65317, 0,
548  /* 130 */ 37, 65430, 103, 65395, 65333, 0,
549  /* 136 */ 65349, 0,
550  /* 138 */ 65395, 0,
551  /* 140 */ 65410, 0,
552  /* 142 */ 65415, 0,
553  /* 144 */ 65419, 0,
554  /* 146 */ 65420, 0,
555  /* 148 */ 65421, 0,
556  /* 150 */ 65422, 0,
557  /* 152 */ 65430, 0,
558  /* 154 */ 65440, 0,
559  /* 156 */ 65441, 0,
560  /* 158 */ 141, 65498, 0,
561  /* 161 */ 65516, 234, 65498, 0,
562  /* 165 */ 65515, 235, 65498, 0,
563  /* 169 */ 65514, 236, 65498, 0,
564  /* 173 */ 65513, 237, 65498, 0,
565  /* 177 */ 65512, 238, 65498, 0,
566  /* 181 */ 65511, 239, 65498, 0,
567  /* 185 */ 65510, 240, 65498, 0,
568  /* 189 */ 65509, 241, 65498, 0,
569  /* 193 */ 65508, 242, 65498, 0,
570  /* 197 */ 65507, 243, 65498, 0,
571  /* 201 */ 65506, 244, 65498, 0,
572  /* 205 */ 65505, 245, 65498, 0,
573  /* 209 */ 65504, 246, 65498, 0,
574  /* 213 */ 65503, 247, 65498, 0,
575  /* 217 */ 65502, 248, 65498, 0,
576  /* 221 */ 65501, 249, 65498, 0,
577  /* 225 */ 65500, 250, 65498, 0,
578  /* 229 */ 65295, 347, 65499, 0,
579  /* 233 */ 65333, 344, 65502, 0,
580  /* 237 */ 65507, 0,
581  /* 239 */ 65510, 0,
582  /* 241 */ 65511, 0,
583  /* 243 */ 65512, 0,
584  /* 245 */ 65516, 0,
585  /* 247 */ 65521, 0,
586  /* 249 */ 65522, 0,
587  /* 251 */ 65535, 0,
588 };
589 
590 static uint16_t MipsSubRegIdxLists[] = {
591  /* 0 */ 1, 0,
592  /* 2 */ 3, 4, 5, 6, 7, 0,
593  /* 8 */ 2, 9, 8, 0,
594  /* 12 */ 9, 1, 8, 10, 11, 0,
595 };
596 
597 static MCRegisterDesc MipsRegDesc[] = { // Descriptors
598  { 6, 0, 0, 0, 0, 0 },
599  { 2007, 1, 82, 1, 4017, 0 },
600  { 2010, 1, 1, 1, 4017, 0 },
601  { 2102, 1, 1, 1, 4017, 0 },
602  { 1973, 1, 1, 1, 4017, 0 },
603  { 2027, 8, 1, 2, 32, 4 },
604  { 2054, 1, 1, 1, 1089, 0 },
605  { 2071, 1, 1, 1, 1089, 0 },
606  { 1985, 1, 102, 1, 1089, 0 },
607  { 1988, 1, 104, 1, 1089, 0 },
608  { 2061, 1, 1, 1, 1089, 0 },
609  { 2000, 1, 1, 1, 1089, 0 },
610  { 1994, 1, 1, 1, 1089, 0 },
611  { 2038, 1, 1, 1, 1089, 0 },
612  { 2092, 1, 1, 1, 1089, 0 },
613  { 2081, 1, 1, 1, 1089, 0 },
614  { 2019, 1, 1, 1, 1089, 0 },
615  { 2045, 1, 1, 1, 1089, 0 },
616  { 1970, 1, 1, 1, 1089, 0 },
617  { 1967, 1, 106, 1, 1089, 0 },
618  { 1991, 1, 108, 1, 1089, 0 },
619  { 1980, 1, 110, 1, 1089, 0 },
620  { 152, 1, 110, 1, 1089, 0 },
621  { 365, 1, 110, 1, 1089, 0 },
622  { 537, 1, 110, 1, 1089, 0 },
623  { 703, 1, 110, 1, 1089, 0 },
624  { 155, 190, 110, 9, 1042, 10 },
625  { 368, 190, 1, 9, 1042, 10 },
626  { 540, 190, 1, 9, 1042, 10 },
627  { 706, 190, 1, 9, 1042, 10 },
628  { 1271, 237, 1, 0, 0, 2 },
629  { 160, 1, 1, 1, 1153, 0 },
630  { 373, 1, 1, 1, 1153, 0 },
631  { 545, 1, 1, 1, 1153, 0 },
632  { 711, 1, 1, 1, 1153, 0 },
633  { 1278, 1, 1, 1, 1153, 0 },
634  { 1412, 1, 1, 1, 1153, 0 },
635  { 1542, 1, 1, 1, 1153, 0 },
636  { 1672, 1, 1, 1, 1153, 0 },
637  { 70, 1, 1, 1, 1153, 0 },
638  { 283, 1, 1, 1, 1153, 0 },
639  { 496, 1, 1, 1, 1153, 0 },
640  { 662, 1, 1, 1, 1153, 0 },
641  { 820, 1, 1, 1, 1153, 0 },
642  { 1383, 1, 1, 1, 1153, 0 },
643  { 1513, 1, 1, 1, 1153, 0 },
644  { 1643, 1, 1, 1, 1153, 0 },
645  { 1773, 1, 1, 1, 1153, 0 },
646  { 1911, 1, 1, 1, 1153, 0 },
647  { 130, 1, 1, 1, 1153, 0 },
648  { 343, 1, 1, 1, 1153, 0 },
649  { 531, 1, 1, 1, 1153, 0 },
650  { 697, 1, 1, 1, 1153, 0 },
651  { 842, 1, 1, 1, 1153, 0 },
652  { 1405, 1, 1, 1, 1153, 0 },
653  { 1535, 1, 1, 1, 1153, 0 },
654  { 1665, 1, 1, 1, 1153, 0 },
655  { 1795, 1, 1, 1, 1153, 0 },
656  { 1933, 1, 1, 1, 1153, 0 },
657  { 0, 1, 1, 1, 1153, 0 },
658  { 213, 1, 1, 1, 1153, 0 },
659  { 426, 1, 1, 1, 1153, 0 },
660  { 592, 1, 1, 1, 1153, 0 },
661  { 750, 1, 1, 1, 1153, 0 },
662  { 1313, 1, 1, 1, 1153, 0 },
663  { 1447, 1, 1, 1, 1153, 0 },
664  { 1577, 1, 1, 1, 1153, 0 },
665  { 1707, 1, 1, 1, 1153, 0 },
666  { 1829, 1, 1, 1, 1153, 0 },
667  { 45, 1, 1, 1, 1153, 0 },
668  { 258, 1, 1, 1, 1153, 0 },
669  { 471, 1, 1, 1, 1153, 0 },
670  { 637, 1, 1, 1, 1153, 0 },
671  { 795, 1, 1, 1, 1153, 0 },
672  { 1358, 1, 1, 1, 1153, 0 },
673  { 1488, 1, 1, 1, 1153, 0 },
674  { 1618, 1, 1, 1, 1153, 0 },
675  { 1748, 1, 1, 1, 1153, 0 },
676  { 1886, 1, 1, 1, 1153, 0 },
677  { 105, 1, 1, 1, 1153, 0 },
678  { 318, 1, 1, 1, 1153, 0 },
679  { 7, 1, 1, 1, 1153, 0 },
680  { 220, 1, 1, 1, 1153, 0 },
681  { 433, 1, 1, 1, 1153, 0 },
682  { 599, 1, 1, 1, 1153, 0 },
683  { 757, 1, 1, 1, 1153, 0 },
684  { 1320, 1, 1, 1, 1153, 0 },
685  { 1454, 1, 1, 1, 1153, 0 },
686  { 1584, 1, 1, 1, 1153, 0 },
687  { 1714, 1, 1, 1, 1153, 0 },
688  { 1836, 1, 1, 1, 1153, 0 },
689  { 52, 1, 1, 1, 1153, 0 },
690  { 265, 1, 1, 1, 1153, 0 },
691  { 478, 1, 1, 1, 1153, 0 },
692  { 644, 1, 1, 1, 1153, 0 },
693  { 802, 1, 1, 1, 1153, 0 },
694  { 1365, 1, 1, 1, 1153, 0 },
695  { 1495, 1, 1, 1, 1153, 0 },
696  { 1625, 1, 1, 1, 1153, 0 },
697  { 1755, 1, 1, 1, 1153, 0 },
698  { 1893, 1, 1, 1, 1153, 0 },
699  { 112, 1, 1, 1, 1153, 0 },
700  { 325, 1, 1, 1, 1153, 0 },
701  { 164, 14, 1, 9, 994, 10 },
702  { 377, 17, 1, 9, 994, 10 },
703  { 549, 20, 1, 9, 994, 10 },
704  { 715, 23, 1, 9, 994, 10 },
705  { 1282, 26, 1, 9, 994, 10 },
706  { 1416, 29, 1, 9, 994, 10 },
707  { 1546, 32, 1, 9, 994, 10 },
708  { 1676, 35, 1, 9, 994, 10 },
709  { 1801, 38, 1, 9, 994, 10 },
710  { 1939, 41, 1, 9, 994, 10 },
711  { 14, 44, 1, 9, 994, 10 },
712  { 227, 47, 1, 9, 994, 10 },
713  { 440, 50, 1, 9, 994, 10 },
714  { 606, 53, 1, 9, 994, 10 },
715  { 764, 56, 1, 9, 994, 10 },
716  { 1327, 59, 1, 9, 994, 10 },
717  { 92, 1, 150, 1, 2401, 0 },
718  { 305, 1, 148, 1, 2401, 0 },
719  { 518, 1, 146, 1, 2401, 0 },
720  { 684, 1, 144, 1, 2401, 0 },
721  { 167, 1, 161, 1, 3985, 0 },
722  { 380, 1, 165, 1, 3985, 0 },
723  { 552, 1, 165, 1, 3985, 0 },
724  { 718, 1, 169, 1, 3985, 0 },
725  { 1285, 1, 169, 1, 3985, 0 },
726  { 1419, 1, 173, 1, 3985, 0 },
727  { 1549, 1, 173, 1, 3985, 0 },
728  { 1679, 1, 177, 1, 3985, 0 },
729  { 1804, 1, 177, 1, 3985, 0 },
730  { 1942, 1, 181, 1, 3985, 0 },
731  { 18, 1, 181, 1, 3985, 0 },
732  { 231, 1, 185, 1, 3985, 0 },
733  { 444, 1, 185, 1, 3985, 0 },
734  { 610, 1, 189, 1, 3985, 0 },
735  { 768, 1, 189, 1, 3985, 0 },
736  { 1331, 1, 193, 1, 3985, 0 },
737  { 1461, 1, 193, 1, 3985, 0 },
738  { 1591, 1, 197, 1, 3985, 0 },
739  { 1721, 1, 197, 1, 3985, 0 },
740  { 1843, 1, 201, 1, 3985, 0 },
741  { 59, 1, 201, 1, 3985, 0 },
742  { 272, 1, 205, 1, 3985, 0 },
743  { 485, 1, 205, 1, 3985, 0 },
744  { 651, 1, 209, 1, 3985, 0 },
745  { 809, 1, 209, 1, 3985, 0 },
746  { 1372, 1, 213, 1, 3985, 0 },
747  { 1502, 1, 213, 1, 3985, 0 },
748  { 1632, 1, 217, 1, 3985, 0 },
749  { 1762, 1, 217, 1, 3985, 0 },
750  { 1900, 1, 221, 1, 3985, 0 },
751  { 119, 1, 221, 1, 3985, 0 },
752  { 332, 1, 225, 1, 3985, 0 },
753  { 159, 1, 1, 1, 3985, 0 },
754  { 372, 1, 1, 1, 3985, 0 },
755  { 544, 1, 1, 1, 3985, 0 },
756  { 710, 1, 1, 1, 3985, 0 },
757  { 1277, 1, 1, 1, 3985, 0 },
758  { 1411, 1, 1, 1, 3985, 0 },
759  { 1541, 1, 1, 1, 3985, 0 },
760  { 1671, 1, 1, 1, 3985, 0 },
761  { 191, 1, 1, 1, 3985, 0 },
762  { 404, 1, 1, 1, 3985, 0 },
763  { 573, 1, 1, 1, 3985, 0 },
764  { 731, 1, 1, 1, 3985, 0 },
765  { 1294, 1, 1, 1, 3985, 0 },
766  { 1428, 1, 1, 1, 3985, 0 },
767  { 1558, 1, 1, 1, 3985, 0 },
768  { 1688, 1, 1, 1, 3985, 0 },
769  { 1813, 1, 1, 1, 3985, 0 },
770  { 1951, 1, 1, 1, 3985, 0 },
771  { 29, 1, 1, 1, 3985, 0 },
772  { 242, 1, 1, 1, 3985, 0 },
773  { 455, 1, 1, 1, 3985, 0 },
774  { 621, 1, 1, 1, 3985, 0 },
775  { 779, 1, 1, 1, 3985, 0 },
776  { 1342, 1, 1, 1, 3985, 0 },
777  { 1472, 1, 1, 1, 3985, 0 },
778  { 1602, 1, 1, 1, 3985, 0 },
779  { 1732, 1, 1, 1, 3985, 0 },
780  { 1854, 1, 1, 1, 3985, 0 },
781  { 76, 1, 1, 1, 3985, 0 },
782  { 289, 1, 1, 1, 3985, 0 },
783  { 502, 1, 1, 1, 3985, 0 },
784  { 668, 1, 1, 1, 3985, 0 },
785  { 826, 1, 1, 1, 3985, 0 },
786  { 1389, 1, 1, 1, 3985, 0 },
787  { 1519, 1, 1, 1, 3985, 0 },
788  { 1649, 1, 1, 1, 3985, 0 },
789  { 1779, 1, 1, 1, 3985, 0 },
790  { 1917, 1, 1, 1, 3985, 0 },
791  { 136, 1, 1, 1, 3985, 0 },
792  { 349, 1, 1, 1, 3985, 0 },
793  { 1253, 136, 1, 0, 1184, 2 },
794  { 170, 1, 158, 1, 3953, 0 },
795  { 383, 1, 158, 1, 3953, 0 },
796  { 555, 1, 158, 1, 3953, 0 },
797  { 721, 1, 158, 1, 3953, 0 },
798  { 1288, 1, 158, 1, 3953, 0 },
799  { 1422, 1, 158, 1, 3953, 0 },
800  { 1552, 1, 158, 1, 3953, 0 },
801  { 1682, 1, 158, 1, 3953, 0 },
802  { 1807, 1, 158, 1, 3953, 0 },
803  { 1945, 1, 158, 1, 3953, 0 },
804  { 22, 1, 158, 1, 3953, 0 },
805  { 235, 1, 158, 1, 3953, 0 },
806  { 448, 1, 158, 1, 3953, 0 },
807  { 614, 1, 158, 1, 3953, 0 },
808  { 772, 1, 158, 1, 3953, 0 },
809  { 1335, 1, 158, 1, 3953, 0 },
810  { 1465, 1, 158, 1, 3953, 0 },
811  { 1595, 1, 158, 1, 3953, 0 },
812  { 1725, 1, 158, 1, 3953, 0 },
813  { 1847, 1, 158, 1, 3953, 0 },
814  { 63, 1, 158, 1, 3953, 0 },
815  { 276, 1, 158, 1, 3953, 0 },
816  { 489, 1, 158, 1, 3953, 0 },
817  { 655, 1, 158, 1, 3953, 0 },
818  { 813, 1, 158, 1, 3953, 0 },
819  { 1376, 1, 158, 1, 3953, 0 },
820  { 1506, 1, 158, 1, 3953, 0 },
821  { 1636, 1, 158, 1, 3953, 0 },
822  { 1766, 1, 158, 1, 3953, 0 },
823  { 1904, 1, 158, 1, 3953, 0 },
824  { 123, 1, 158, 1, 3953, 0 },
825  { 336, 1, 158, 1, 3953, 0 },
826  { 1259, 128, 1, 0, 1216, 2 },
827  { 172, 1, 233, 1, 1826, 0 },
828  { 385, 1, 134, 1, 1826, 0 },
829  { 557, 1, 134, 1, 1826, 0 },
830  { 723, 1, 134, 1, 1826, 0 },
831  { 196, 1, 1, 1, 3921, 0 },
832  { 409, 1, 1, 1, 3921, 0 },
833  { 578, 1, 1, 1, 3921, 0 },
834  { 736, 1, 1, 1, 3921, 0 },
835  { 1299, 1, 1, 1, 3921, 0 },
836  { 1433, 1, 1, 1, 3921, 0 },
837  { 1563, 1, 1, 1, 3921, 0 },
838  { 1693, 1, 1, 1, 3921, 0 },
839  { 1818, 1, 1, 1, 3921, 0 },
840  { 1956, 1, 1, 1, 3921, 0 },
841  { 35, 1, 1, 1, 3921, 0 },
842  { 248, 1, 1, 1, 3921, 0 },
843  { 461, 1, 1, 1, 3921, 0 },
844  { 627, 1, 1, 1, 3921, 0 },
845  { 785, 1, 1, 1, 3921, 0 },
846  { 1348, 1, 1, 1, 3921, 0 },
847  { 1478, 1, 1, 1, 3921, 0 },
848  { 1608, 1, 1, 1, 3921, 0 },
849  { 1738, 1, 1, 1, 3921, 0 },
850  { 1860, 1, 1, 1, 3921, 0 },
851  { 82, 1, 1, 1, 3921, 0 },
852  { 295, 1, 1, 1, 3921, 0 },
853  { 508, 1, 1, 1, 3921, 0 },
854  { 674, 1, 1, 1, 3921, 0 },
855  { 832, 1, 1, 1, 3921, 0 },
856  { 1395, 1, 1, 1, 3921, 0 },
857  { 1525, 1, 1, 1, 3921, 0 },
858  { 1655, 1, 1, 1, 3921, 0 },
859  { 1785, 1, 1, 1, 3921, 0 },
860  { 1923, 1, 1, 1, 3921, 0 },
861  { 142, 1, 1, 1, 3921, 0 },
862  { 355, 1, 1, 1, 3921, 0 },
863  { 176, 1, 100, 1, 3921, 0 },
864  { 389, 1, 100, 1, 3921, 0 },
865  { 184, 1, 229, 1, 1794, 0 },
866  { 397, 1, 126, 1, 1794, 0 },
867  { 566, 1, 126, 1, 1794, 0 },
868  { 727, 1, 126, 1, 1794, 0 },
869  { 179, 1, 1, 1, 3889, 0 },
870  { 392, 1, 1, 1, 3889, 0 },
871  { 561, 1, 1, 1, 3889, 0 },
872  { 188, 1, 1, 1, 3889, 0 },
873  { 401, 1, 1, 1, 3889, 0 },
874  { 570, 1, 1, 1, 3889, 0 },
875  { 1239, 124, 1, 0, 1248, 2 },
876  { 201, 1, 98, 1, 3857, 0 },
877  { 414, 1, 98, 1, 3857, 0 },
878  { 583, 1, 98, 1, 3857, 0 },
879  { 741, 1, 98, 1, 3857, 0 },
880  { 1304, 1, 98, 1, 3857, 0 },
881  { 1438, 1, 98, 1, 3857, 0 },
882  { 1568, 1, 98, 1, 3857, 0 },
883  { 1698, 1, 98, 1, 3857, 0 },
884  { 1265, 122, 1, 0, 1280, 2 },
885  { 204, 1, 96, 1, 3825, 0 },
886  { 417, 1, 96, 1, 3825, 0 },
887  { 586, 1, 96, 1, 3825, 0 },
888  { 744, 1, 96, 1, 3825, 0 },
889  { 1307, 1, 96, 1, 3825, 0 },
890  { 1441, 1, 96, 1, 3825, 0 },
891  { 1571, 1, 96, 1, 3825, 0 },
892  { 1701, 1, 96, 1, 3825, 0 },
893  { 1823, 1, 96, 1, 3825, 0 },
894  { 1961, 1, 96, 1, 3825, 0 },
895  { 207, 1, 96, 1, 3825, 0 },
896  { 420, 1, 96, 1, 3825, 0 },
897  { 210, 92, 1, 8, 1425, 10 },
898  { 423, 92, 1, 8, 1425, 10 },
899  { 589, 92, 1, 8, 1425, 10 },
900  { 747, 92, 1, 8, 1425, 10 },
901  { 1310, 92, 1, 8, 1425, 10 },
902  { 1444, 92, 1, 8, 1425, 10 },
903  { 1574, 92, 1, 8, 1425, 10 },
904  { 1704, 92, 1, 8, 1425, 10 },
905  { 1826, 92, 1, 8, 1425, 10 },
906  { 1964, 92, 1, 8, 1425, 10 },
907  { 41, 92, 1, 8, 1425, 10 },
908  { 254, 92, 1, 8, 1425, 10 },
909  { 467, 92, 1, 8, 1425, 10 },
910  { 633, 92, 1, 8, 1425, 10 },
911  { 791, 92, 1, 8, 1425, 10 },
912  { 1354, 92, 1, 8, 1425, 10 },
913  { 1484, 92, 1, 8, 1425, 10 },
914  { 1614, 92, 1, 8, 1425, 10 },
915  { 1744, 92, 1, 8, 1425, 10 },
916  { 1866, 92, 1, 8, 1425, 10 },
917  { 88, 92, 1, 8, 1425, 10 },
918  { 301, 92, 1, 8, 1425, 10 },
919  { 514, 92, 1, 8, 1425, 10 },
920  { 680, 92, 1, 8, 1425, 10 },
921  { 838, 92, 1, 8, 1425, 10 },
922  { 1401, 92, 1, 8, 1425, 10 },
923  { 1531, 92, 1, 8, 1425, 10 },
924  { 1661, 92, 1, 8, 1425, 10 },
925  { 1791, 92, 1, 8, 1425, 10 },
926  { 1929, 92, 1, 8, 1425, 10 },
927  { 148, 92, 1, 8, 1425, 10 },
928  { 361, 92, 1, 8, 1425, 10 },
929  { 1245, 118, 1, 0, 1921, 2 },
930  { 869, 118, 1, 0, 1921, 2 },
931  { 947, 118, 1, 0, 1921, 2 },
932  { 997, 118, 1, 0, 1921, 2 },
933  { 1035, 118, 1, 0, 1921, 2 },
934  { 875, 130, 1, 12, 656, 10 },
935  { 882, 93, 159, 9, 1377, 10 },
936  { 953, 93, 159, 9, 1377, 10 },
937  { 1003, 93, 159, 9, 1377, 10 },
938  { 1041, 93, 159, 9, 1377, 10 },
939  { 1073, 93, 159, 9, 1377, 10 },
940  { 1105, 93, 159, 9, 1377, 10 },
941  { 1137, 93, 159, 9, 1377, 10 },
942  { 1169, 93, 159, 9, 1377, 10 },
943  { 1201, 93, 159, 9, 1377, 10 },
944  { 1227, 93, 159, 9, 1377, 10 },
945  { 848, 93, 159, 9, 1377, 10 },
946  { 926, 93, 159, 9, 1377, 10 },
947  { 983, 93, 159, 9, 1377, 10 },
948  { 1021, 93, 159, 9, 1377, 10 },
949  { 1059, 93, 159, 9, 1377, 10 },
950  { 1091, 93, 159, 9, 1377, 10 },
951  { 1123, 93, 159, 9, 1377, 10 },
952  { 1155, 93, 159, 9, 1377, 10 },
953  { 1187, 93, 159, 9, 1377, 10 },
954  { 1213, 93, 159, 9, 1377, 10 },
955  { 855, 93, 159, 9, 1377, 10 },
956  { 933, 93, 159, 9, 1377, 10 },
957  { 990, 93, 159, 9, 1377, 10 },
958  { 1028, 93, 159, 9, 1377, 10 },
959  { 1066, 93, 159, 9, 1377, 10 },
960  { 1098, 93, 159, 9, 1377, 10 },
961  { 1130, 93, 159, 9, 1377, 10 },
962  { 1162, 93, 159, 9, 1377, 10 },
963  { 1194, 93, 159, 9, 1377, 10 },
964  { 1220, 93, 159, 9, 1377, 10 },
965  { 862, 93, 159, 9, 1377, 10 },
966  { 940, 93, 159, 9, 1377, 10 },
967  { 1870, 1, 116, 1, 1120, 0 },
968  { 888, 138, 235, 0, 1344, 2 },
969  { 895, 152, 1, 0, 2241, 2 },
970  { 959, 152, 1, 0, 2241, 2 },
971  { 901, 152, 231, 0, 1312, 2 },
972  { 908, 154, 1, 0, 2273, 2 },
973  { 965, 154, 1, 0, 2273, 2 },
974  { 1009, 154, 1, 0, 2273, 2 },
975  { 1047, 154, 1, 0, 2273, 2 },
976  { 1079, 154, 1, 0, 2273, 2 },
977  { 1111, 154, 1, 0, 2273, 2 },
978  { 1143, 154, 1, 0, 2273, 2 },
979  { 1175, 154, 1, 0, 2273, 2 },
980  { 914, 156, 1, 0, 2273, 2 },
981  { 971, 156, 1, 0, 2273, 2 },
982  { 1015, 156, 1, 0, 2273, 2 },
983  { 1053, 156, 1, 0, 2273, 2 },
984  { 1085, 156, 1, 0, 2273, 2 },
985  { 1117, 156, 1, 0, 2273, 2 },
986  { 1149, 156, 1, 0, 2273, 2 },
987  { 1181, 156, 1, 0, 2273, 2 },
988  { 1207, 156, 1, 0, 2273, 2 },
989  { 1233, 156, 1, 0, 2273, 2 },
990  { 920, 156, 1, 0, 2273, 2 },
991  { 977, 156, 1, 0, 2273, 2 },
992 };
993 
994  // OddSP Register Class...
995  static MCPhysReg OddSP[] = {
996  Mips_F1, Mips_F3, Mips_F5, Mips_F7, Mips_F9, Mips_F11, Mips_F13, Mips_F15, Mips_F17, Mips_F19, Mips_F21, Mips_F23, Mips_F25, Mips_F27, Mips_F29, Mips_F31, Mips_F_HI1, Mips_F_HI3, Mips_F_HI5, Mips_F_HI7, Mips_F_HI9, Mips_F_HI11, Mips_F_HI13, Mips_F_HI15, Mips_F_HI17, Mips_F_HI19, Mips_F_HI21, Mips_F_HI23, Mips_F_HI25, Mips_F_HI27, Mips_F_HI29, Mips_F_HI31, Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64,
997  };
998 
999  // OddSP Bit set.
1000  static uint8_t OddSPBits[] = {
1001  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x50, 0x55, 0x55, 0x55, 0x05, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
1002  };
1003 
1004  // CCR Register Class...
1005  static MCPhysReg CCR[] = {
1006  Mips_FCR0, Mips_FCR1, Mips_FCR2, Mips_FCR3, Mips_FCR4, Mips_FCR5, Mips_FCR6, Mips_FCR7, Mips_FCR8, Mips_FCR9, Mips_FCR10, Mips_FCR11, Mips_FCR12, Mips_FCR13, Mips_FCR14, Mips_FCR15, Mips_FCR16, Mips_FCR17, Mips_FCR18, Mips_FCR19, Mips_FCR20, Mips_FCR21, Mips_FCR22, Mips_FCR23, Mips_FCR24, Mips_FCR25, Mips_FCR26, Mips_FCR27, Mips_FCR28, Mips_FCR29, Mips_FCR30, Mips_FCR31,
1007  };
1008 
1009  // CCR Bit set.
1010  static uint8_t CCRBits[] = {
1011  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1012  };
1013 
1014  // COP2 Register Class...
1015  static MCPhysReg COP2[] = {
1016  Mips_COP20, Mips_COP21, Mips_COP22, Mips_COP23, Mips_COP24, Mips_COP25, Mips_COP26, Mips_COP27, Mips_COP28, Mips_COP29, Mips_COP210, Mips_COP211, Mips_COP212, Mips_COP213, Mips_COP214, Mips_COP215, Mips_COP216, Mips_COP217, Mips_COP218, Mips_COP219, Mips_COP220, Mips_COP221, Mips_COP222, Mips_COP223, Mips_COP224, Mips_COP225, Mips_COP226, Mips_COP227, Mips_COP228, Mips_COP229, Mips_COP230, Mips_COP231,
1017  };
1018 
1019  // COP2 Bit set.
1020  static uint8_t COP2Bits[] = {
1021  0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x01, 0xf8, 0xff, 0xff, 0x01,
1022  };
1023 
1024  // COP3 Register Class...
1025  static MCPhysReg COP3[] = {
1026  Mips_COP30, Mips_COP31, Mips_COP32, Mips_COP33, Mips_COP34, Mips_COP35, Mips_COP36, Mips_COP37, Mips_COP38, Mips_COP39, Mips_COP310, Mips_COP311, Mips_COP312, Mips_COP313, Mips_COP314, Mips_COP315, Mips_COP316, Mips_COP317, Mips_COP318, Mips_COP319, Mips_COP320, Mips_COP321, Mips_COP322, Mips_COP323, Mips_COP324, Mips_COP325, Mips_COP326, Mips_COP327, Mips_COP328, Mips_COP329, Mips_COP330, Mips_COP331,
1027  };
1028 
1029  // COP3 Bit set.
1030  static uint8_t COP3Bits[] = {
1031  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x07, 0x00, 0x00, 0xfe, 0xff, 0x7f,
1032  };
1033 
1034  // DSPR Register Class...
1035  static MCPhysReg DSPR[] = {
1036  Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA,
1037  };
1038 
1039  // DSPR Bit set.
1040  static uint8_t DSPRBits[] = {
1041  0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07,
1042  };
1043 
1044  // FGR32 Register Class...
1045  static MCPhysReg FGR32[] = {
1046  Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31,
1047  };
1048 
1049  // FGR32 Bit set.
1050  static uint8_t FGR32Bits[] = {
1051  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1052  };
1053 
1054  // FGRCC Register Class...
1055  static MCPhysReg FGRCC[] = {
1056  Mips_F0, Mips_F1, Mips_F2, Mips_F3, Mips_F4, Mips_F5, Mips_F6, Mips_F7, Mips_F8, Mips_F9, Mips_F10, Mips_F11, Mips_F12, Mips_F13, Mips_F14, Mips_F15, Mips_F16, Mips_F17, Mips_F18, Mips_F19, Mips_F20, Mips_F21, Mips_F22, Mips_F23, Mips_F24, Mips_F25, Mips_F26, Mips_F27, Mips_F28, Mips_F29, Mips_F30, Mips_F31,
1057  };
1058 
1059  // FGRCC Bit set.
1060  static uint8_t FGRCCBits[] = {
1061  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1062  };
1063 
1064  // FGRH32 Register Class...
1065  static MCPhysReg FGRH32[] = {
1066  Mips_F_HI0, Mips_F_HI1, Mips_F_HI2, Mips_F_HI3, Mips_F_HI4, Mips_F_HI5, Mips_F_HI6, Mips_F_HI7, Mips_F_HI8, Mips_F_HI9, Mips_F_HI10, Mips_F_HI11, Mips_F_HI12, Mips_F_HI13, Mips_F_HI14, Mips_F_HI15, Mips_F_HI16, Mips_F_HI17, Mips_F_HI18, Mips_F_HI19, Mips_F_HI20, Mips_F_HI21, Mips_F_HI22, Mips_F_HI23, Mips_F_HI24, Mips_F_HI25, Mips_F_HI26, Mips_F_HI27, Mips_F_HI28, Mips_F_HI29, Mips_F_HI30, Mips_F_HI31,
1067  };
1068 
1069  // FGRH32 Bit set.
1070  static uint8_t FGRH32Bits[] = {
1071  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
1072  };
1073 
1074  // GPR32 Register Class...
1075  static MCPhysReg GPR32[] = {
1076  Mips_ZERO, Mips_AT, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_T0, Mips_T1, Mips_T2, Mips_T3, Mips_T4, Mips_T5, Mips_T6, Mips_T7, Mips_S0, Mips_S1, Mips_S2, Mips_S3, Mips_S4, Mips_S5, Mips_S6, Mips_S7, Mips_T8, Mips_T9, Mips_K0, Mips_K1, Mips_GP, Mips_SP, Mips_FP, Mips_RA,
1077  };
1078 
1079  // GPR32 Bit set.
1080  static uint8_t GPR32Bits[] = {
1081  0x02, 0x03, 0xf8, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xc0, 0xbf, 0xff, 0x07,
1082  };
1083 
1084  // HWRegs Register Class...
1085  static MCPhysReg HWRegs[] = {
1086  Mips_HWR0, Mips_HWR1, Mips_HWR2, Mips_HWR3, Mips_HWR4, Mips_HWR5, Mips_HWR6, Mips_HWR7, Mips_HWR8, Mips_HWR9, Mips_HWR10, Mips_HWR11, Mips_HWR12, Mips_HWR13, Mips_HWR14, Mips_HWR15, Mips_HWR16, Mips_HWR17, Mips_HWR18, Mips_HWR19, Mips_HWR20, Mips_HWR21, Mips_HWR22, Mips_HWR23, Mips_HWR24, Mips_HWR25, Mips_HWR26, Mips_HWR27, Mips_HWR28, Mips_HWR29, Mips_HWR30, Mips_HWR31,
1087  };
1088 
1089  // HWRegs Bit set.
1090  static uint8_t HWRegsBits[] = {
1091  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
1092  };
1093 
1094  // OddSP_with_sub_hi Register Class...
1095  static MCPhysReg OddSP_with_sub_hi[] = {
1096  Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15, Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64,
1097  };
1098 
1099  // OddSP_with_sub_hi Bit set.
1100  static uint8_t OddSP_with_sub_hiBits[] = {
1101  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
1102  };
1103 
1104  // FGR32_and_OddSP Register Class...
1105  static MCPhysReg FGR32_and_OddSP[] = {
1106  Mips_F1, Mips_F3, Mips_F5, Mips_F7, Mips_F9, Mips_F11, Mips_F13, Mips_F15, Mips_F17, Mips_F19, Mips_F21, Mips_F23, Mips_F25, Mips_F27, Mips_F29, Mips_F31,
1107  };
1108 
1109  // FGR32_and_OddSP Bit set.
1110  static uint8_t FGR32_and_OddSPBits[] = {
1111  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05,
1112  };
1113 
1114  // FGRH32_and_OddSP Register Class...
1115  static MCPhysReg FGRH32_and_OddSP[] = {
1116  Mips_F_HI1, Mips_F_HI3, Mips_F_HI5, Mips_F_HI7, Mips_F_HI9, Mips_F_HI11, Mips_F_HI13, Mips_F_HI15, Mips_F_HI17, Mips_F_HI19, Mips_F_HI21, Mips_F_HI23, Mips_F_HI25, Mips_F_HI27, Mips_F_HI29, Mips_F_HI31,
1117  };
1118 
1119  // FGRH32_and_OddSP Bit set.
1120  static uint8_t FGRH32_and_OddSPBits[] = {
1121  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xaa, 0xaa, 0xaa, 0x0a,
1122  };
1123 
1124  // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Register Class...
1125  static MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGRH32[] = {
1126  Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64,
1127  };
1128 
1129  // OddSP_with_sub_hi_with_sub_hi_in_FGRH32 Bit set.
1130  static uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits[] = {
1131  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
1132  };
1133 
1134  // CPU16RegsPlusSP Register Class...
1135  static MCPhysReg CPU16RegsPlusSP[] = {
1136  Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1, Mips_SP,
1137  };
1138 
1139  // CPU16RegsPlusSP Bit set.
1140  static uint8_t CPU16RegsPlusSPBits[] = {
1141  0x00, 0x00, 0xd0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
1142  };
1143 
1144  // CC Register Class...
1145  static MCPhysReg CC[] = {
1146  Mips_CC0, Mips_CC1, Mips_CC2, Mips_CC3, Mips_CC4, Mips_CC5, Mips_CC6, Mips_CC7,
1147  };
1148 
1149  // CC Bit set.
1150  static uint8_t CCBits[] = {
1151  0x00, 0x00, 0x00, 0x80, 0x7f,
1152  };
1153 
1154  // CPU16Regs Register Class...
1155  static MCPhysReg CPU16Regs[] = {
1156  Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3, Mips_S0, Mips_S1,
1157  };
1158 
1159  // CPU16Regs Bit set.
1160  static uint8_t CPU16RegsBits[] = {
1161  0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
1162  };
1163 
1164  // FCC Register Class...
1165  static MCPhysReg FCC[] = {
1166  Mips_FCC0, Mips_FCC1, Mips_FCC2, Mips_FCC3, Mips_FCC4, Mips_FCC5, Mips_FCC6, Mips_FCC7,
1167  };
1168 
1169  // FCC Bit set.
1170  static uint8_t FCCBits[] = {
1171  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
1172  };
1173 
1174  // GPRMM16 Register Class...
1175  static MCPhysReg GPRMM16[] = {
1176  Mips_S0, Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3,
1177  };
1178 
1179  // GPRMM16 Bit set.
1180  static uint8_t GPRMM16Bits[] = {
1181  0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
1182  };
1183 
1184  // GPRMM16MoveP Register Class...
1185  static MCPhysReg GPRMM16MoveP[] = {
1186  Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, Mips_S0, Mips_S2, Mips_S3, Mips_S4,
1187  };
1188 
1189  // GPRMM16MoveP Bit set.
1190  static uint8_t GPRMM16MovePBits[] = {
1191  0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x06,
1192  };
1193 
1194  // GPRMM16Zero Register Class...
1195  static MCPhysReg GPRMM16Zero[] = {
1196  Mips_ZERO, Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3,
1197  };
1198 
1199  // GPRMM16Zero Bit set.
1200  static uint8_t GPRMM16ZeroBits[] = {
1201  0x00, 0x00, 0xe0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
1202  };
1203 
1204  // MSACtrl Register Class...
1205  static MCPhysReg MSACtrl[] = {
1206  Mips_MSAIR, Mips_MSACSR, Mips_MSAAccess, Mips_MSASave, Mips_MSAModify, Mips_MSARequest, Mips_MSAMap, Mips_MSAUnmap,
1207  };
1208 
1209  // MSACtrl Bit set.
1210  static uint8_t MSACtrlBits[] = {
1211  0x00, 0xfc, 0x03,
1212  };
1213 
1214  // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Register Class...
1215  static MCPhysReg OddSP_with_sub_hi_with_sub_hi_in_FGR32[] = {
1216  Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15,
1217  };
1218 
1219  // OddSP_with_sub_hi_with_sub_hi_in_FGR32 Bit set.
1220  static uint8_t OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits[] = {
1221  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55,
1222  };
1223 
1224  // CPU16Regs_and_GPRMM16Zero Register Class...
1225  static MCPhysReg CPU16Regs_and_GPRMM16Zero[] = {
1226  Mips_S1, Mips_V0, Mips_V1, Mips_A0, Mips_A1, Mips_A2, Mips_A3,
1227  };
1228 
1229  // CPU16Regs_and_GPRMM16Zero Bit set.
1230  static uint8_t CPU16Regs_and_GPRMM16ZeroBits[] = {
1231  0x00, 0x00, 0xc0, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
1232  };
1233 
1234  // CPU16Regs_and_GPRMM16MoveP Register Class...
1235  static MCPhysReg CPU16Regs_and_GPRMM16MoveP[] = {
1236  Mips_S1, Mips_V0, Mips_V1, Mips_S0,
1237  };
1238 
1239  // CPU16Regs_and_GPRMM16MoveP Bit set.
1240  static uint8_t CPU16Regs_and_GPRMM16MovePBits[] = {
1241  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x06,
1242  };
1243 
1244  // GPRMM16MoveP_and_GPRMM16Zero Register Class...
1245  static MCPhysReg GPRMM16MoveP_and_GPRMM16Zero[] = {
1246  Mips_ZERO, Mips_S1, Mips_V0, Mips_V1,
1247  };
1248 
1249  // GPRMM16MoveP_and_GPRMM16Zero Bit set.
1250  static uint8_t GPRMM16MoveP_and_GPRMM16ZeroBits[] = {
1251  0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
1252  };
1253 
1254  // HI32DSP Register Class...
1255  static MCPhysReg HI32DSP[] = {
1256  Mips_HI0, Mips_HI1, Mips_HI2, Mips_HI3,
1257  };
1258 
1259  // HI32DSP Bit set.
1260  static uint8_t HI32DSPBits[] = {
1261  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
1262  };
1263 
1264  // LO32DSP Register Class...
1265  static MCPhysReg LO32DSP[] = {
1266  Mips_LO0, Mips_LO1, Mips_LO2, Mips_LO3,
1267  };
1268 
1269  // LO32DSP Bit set.
1270  static uint8_t LO32DSPBits[] = {
1271  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
1272  };
1273 
1274  // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...
1275  static MCPhysReg GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {
1276  Mips_S1, Mips_V0, Mips_V1,
1277  };
1278 
1279  // GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.
1280  static uint8_t GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {
1281  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x06,
1282  };
1283 
1284  // CPURAReg Register Class...
1285  static MCPhysReg CPURAReg[] = {
1286  Mips_RA,
1287  };
1288 
1289  // CPURAReg Bit set.
1290  static uint8_t CPURARegBits[] = {
1291  0x00, 0x00, 0x08,
1292  };
1293 
1294  // CPUSPReg Register Class...
1295  static MCPhysReg CPUSPReg[] = {
1296  Mips_SP,
1297  };
1298 
1299  // CPUSPReg Bit set.
1300  static uint8_t CPUSPRegBits[] = {
1301  0x00, 0x00, 0x10,
1302  };
1303 
1304  // DSPCC Register Class...
1305  static MCPhysReg DSPCC[] = {
1306  Mips_DSPCCond,
1307  };
1308 
1309  // DSPCC Bit set.
1310  static uint8_t DSPCCBits[] = {
1311  0x04,
1312  };
1313 
1314  // HI32 Register Class...
1315  static MCPhysReg HI32[] = {
1316  Mips_HI0,
1317  };
1318 
1319  // HI32 Bit set.
1320  static uint8_t HI32Bits[] = {
1321  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
1322  };
1323 
1324  // LO32 Register Class...
1325  static MCPhysReg LO32[] = {
1326  Mips_LO0,
1327  };
1328 
1329  // LO32 Bit set.
1330  static uint8_t LO32Bits[] = {
1331  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
1332  };
1333 
1334  // FGR64 Register Class...
1335  static MCPhysReg FGR64[] = {
1336  Mips_D0_64, Mips_D1_64, Mips_D2_64, Mips_D3_64, Mips_D4_64, Mips_D5_64, Mips_D6_64, Mips_D7_64, Mips_D8_64, Mips_D9_64, Mips_D10_64, Mips_D11_64, Mips_D12_64, Mips_D13_64, Mips_D14_64, Mips_D15_64, Mips_D16_64, Mips_D17_64, Mips_D18_64, Mips_D19_64, Mips_D20_64, Mips_D21_64, Mips_D22_64, Mips_D23_64, Mips_D24_64, Mips_D25_64, Mips_D26_64, Mips_D27_64, Mips_D28_64, Mips_D29_64, Mips_D30_64, Mips_D31_64,
1337  };
1338 
1339  // FGR64 Bit set.
1340  static uint8_t FGR64Bits[] = {
1341  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
1342  };
1343 
1344  // GPR64 Register Class...
1345  static MCPhysReg GPR64[] = {
1346  Mips_ZERO_64, Mips_AT_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_T0_64, Mips_T1_64, Mips_T2_64, Mips_T3_64, Mips_T4_64, Mips_T5_64, Mips_T6_64, Mips_T7_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64, Mips_S5_64, Mips_S6_64, Mips_S7_64, Mips_T8_64, Mips_T9_64, Mips_K0_64, Mips_K1_64, Mips_GP_64, Mips_SP_64, Mips_FP_64, Mips_RA_64,
1347  };
1348 
1349  // GPR64 Bit set.
1350  static uint8_t GPR64Bits[] = {
1351  0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0xd8, 0xff, 0xff, 0x03,
1352  };
1353 
1354  // AFGR64 Register Class...
1355  static MCPhysReg AFGR64[] = {
1356  Mips_D0, Mips_D1, Mips_D2, Mips_D3, Mips_D4, Mips_D5, Mips_D6, Mips_D7, Mips_D8, Mips_D9, Mips_D10, Mips_D11, Mips_D12, Mips_D13, Mips_D14, Mips_D15,
1357  };
1358 
1359  // AFGR64 Bit set.
1360  static uint8_t AFGR64Bits[] = {
1361  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
1362  };
1363 
1364  // FGR64_and_OddSP Register Class...
1365  static MCPhysReg FGR64_and_OddSP[] = {
1366  Mips_D1_64, Mips_D3_64, Mips_D5_64, Mips_D7_64, Mips_D9_64, Mips_D11_64, Mips_D13_64, Mips_D15_64, Mips_D17_64, Mips_D19_64, Mips_D21_64, Mips_D23_64, Mips_D25_64, Mips_D27_64, Mips_D29_64, Mips_D31_64,
1367  };
1368 
1369  // FGR64_and_OddSP Bit set.
1370  static uint8_t FGR64_and_OddSPBits[] = {
1371  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x01,
1372  };
1373 
1374  // GPR64_with_sub_32_in_CPU16RegsPlusSP Register Class...
1375  static MCPhysReg GPR64_with_sub_32_in_CPU16RegsPlusSP[] = {
1376  Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64, Mips_SP_64,
1377  };
1378 
1379  // GPR64_with_sub_32_in_CPU16RegsPlusSP Bit set.
1380  static uint8_t GPR64_with_sub_32_in_CPU16RegsPlusSPBits[] = {
1381  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
1382  };
1383 
1384  // AFGR64_and_OddSP Register Class...
1385  static MCPhysReg AFGR64_and_OddSP[] = {
1386  Mips_D1, Mips_D3, Mips_D5, Mips_D7, Mips_D9, Mips_D11, Mips_D13, Mips_D15,
1387  };
1388 
1389  // AFGR64_and_OddSP Bit set.
1390  static uint8_t AFGR64_and_OddSPBits[] = {
1391  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55,
1392  };
1393 
1394  // GPR64_with_sub_32_in_CPU16Regs Register Class...
1395  static MCPhysReg GPR64_with_sub_32_in_CPU16Regs[] = {
1396  Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S0_64, Mips_S1_64,
1397  };
1398 
1399  // GPR64_with_sub_32_in_CPU16Regs Bit set.
1400  static uint8_t GPR64_with_sub_32_in_CPU16RegsBits[] = {
1401  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
1402  };
1403 
1404  // GPR64_with_sub_32_in_GPRMM16MoveP Register Class...
1405  static MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP[] = {
1406  Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_S0_64, Mips_S1_64, Mips_S2_64, Mips_S3_64, Mips_S4_64,
1407  };
1408 
1409  // GPR64_with_sub_32_in_GPRMM16MoveP Bit set.
1410  static uint8_t GPR64_with_sub_32_in_GPRMM16MovePBits[] = {
1411  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x07, 0x00, 0x03,
1412  };
1413 
1414  // GPR64_with_sub_32_in_GPRMM16Zero Register Class...
1415  static MCPhysReg GPR64_with_sub_32_in_GPRMM16Zero[] = {
1416  Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S1_64,
1417  };
1418 
1419  // GPR64_with_sub_32_in_GPRMM16Zero Bit set.
1420  static uint8_t GPR64_with_sub_32_in_GPRMM16ZeroBits[] = {
1421  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
1422  };
1423 
1424  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Register Class...
1425  static MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero[] = {
1426  Mips_V0_64, Mips_V1_64, Mips_A0_64, Mips_A1_64, Mips_A2_64, Mips_A3_64, Mips_S1_64,
1427  };
1428 
1429  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero Bit set.
1430  static uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits[] = {
1431  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
1432  };
1433 
1434  // ACC64DSP Register Class...
1435  static MCPhysReg ACC64DSP[] = {
1436  Mips_AC0, Mips_AC1, Mips_AC2, Mips_AC3,
1437  };
1438 
1439  // ACC64DSP Bit set.
1440  static uint8_t ACC64DSPBits[] = {
1441  0x00, 0x00, 0x00, 0x3c,
1442  };
1443 
1444  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Register Class...
1445  static MCPhysReg GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP[] = {
1446  Mips_V0_64, Mips_V1_64, Mips_S0_64, Mips_S1_64,
1447  };
1448 
1449  // GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP Bit set.
1450  static uint8_t GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits[] = {
1451  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x03,
1452  };
1453 
1454  // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Register Class...
1455  static MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero[] = {
1456  Mips_ZERO_64, Mips_V0_64, Mips_V1_64, Mips_S1_64,
1457  };
1458 
1459  // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero Bit set.
1460  static uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits[] = {
1461  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
1462  };
1463 
1464  // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Register Class...
1465  static MCPhysReg GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero[] = {
1466  Mips_V0_64, Mips_V1_64, Mips_S1_64,
1467  };
1468 
1469  // GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero Bit set.
1470  static uint8_t GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits[] = {
1471  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x03,
1472  };
1473 
1474  // OCTEON_MPL Register Class...
1475  static MCPhysReg OCTEON_MPL[] = {
1476  Mips_MPL0, Mips_MPL1, Mips_MPL2,
1477  };
1478 
1479  // OCTEON_MPL Bit set.
1480  static uint8_t OCTEON_MPLBits[] = {
1481  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x03,
1482  };
1483 
1484  // OCTEON_P Register Class...
1485  static MCPhysReg OCTEON_P[] = {
1486  Mips_P0, Mips_P1, Mips_P2,
1487  };
1488 
1489  // OCTEON_P Bit set.
1490  static uint8_t OCTEON_PBits[] = {
1491  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c,
1492  };
1493 
1494  // ACC64 Register Class...
1495  static MCPhysReg ACC64[] = {
1496  Mips_AC0,
1497  };
1498 
1499  // ACC64 Bit set.
1500  static uint8_t ACC64Bits[] = {
1501  0x00, 0x00, 0x00, 0x04,
1502  };
1503 
1504  // GPR64_with_sub_32_in_CPURAReg Register Class...
1505  static MCPhysReg GPR64_with_sub_32_in_CPURAReg[] = {
1506  Mips_RA_64,
1507  };
1508 
1509  // GPR64_with_sub_32_in_CPURAReg Bit set.
1510  static uint8_t GPR64_with_sub_32_in_CPURARegBits[] = {
1511  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
1512  };
1513 
1514  // GPR64_with_sub_32_in_CPUSPReg Register Class...
1515  static MCPhysReg GPR64_with_sub_32_in_CPUSPReg[] = {
1516  Mips_SP_64,
1517  };
1518 
1519  // GPR64_with_sub_32_in_CPUSPReg Bit set.
1520  static uint8_t GPR64_with_sub_32_in_CPUSPRegBits[] = {
1521  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
1522  };
1523 
1524  // HI64 Register Class...
1525  static MCPhysReg HI64[] = {
1526  Mips_HI0_64,
1527  };
1528 
1529  // HI64 Bit set.
1530  static uint8_t HI64Bits[] = {
1531  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
1532  };
1533 
1534  // LO64 Register Class...
1535  static MCPhysReg LO64[] = {
1536  Mips_LO0_64,
1537  };
1538 
1539  // LO64 Bit set.
1540  static uint8_t LO64Bits[] = {
1541  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
1542  };
1543 
1544  // MSA128B Register Class...
1545  static MCPhysReg MSA128B[] = {
1546  Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31,
1547  };
1548 
1549  // MSA128B Bit set.
1550  static uint8_t MSA128BBits[] = {
1551  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1552  };
1553 
1554  // MSA128D Register Class...
1555  static MCPhysReg MSA128D[] = {
1556  Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31,
1557  };
1558 
1559  // MSA128D Bit set.
1560  static uint8_t MSA128DBits[] = {
1561  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1562  };
1563 
1564  // MSA128H Register Class...
1565  static MCPhysReg MSA128H[] = {
1566  Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31,
1567  };
1568 
1569  // MSA128H Bit set.
1570  static uint8_t MSA128HBits[] = {
1571  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1572  };
1573 
1574  // MSA128W Register Class...
1575  static MCPhysReg MSA128W[] = {
1576  Mips_W0, Mips_W1, Mips_W2, Mips_W3, Mips_W4, Mips_W5, Mips_W6, Mips_W7, Mips_W8, Mips_W9, Mips_W10, Mips_W11, Mips_W12, Mips_W13, Mips_W14, Mips_W15, Mips_W16, Mips_W17, Mips_W18, Mips_W19, Mips_W20, Mips_W21, Mips_W22, Mips_W23, Mips_W24, Mips_W25, Mips_W26, Mips_W27, Mips_W28, Mips_W29, Mips_W30, Mips_W31,
1577  };
1578 
1579  // MSA128W Bit set.
1580  static uint8_t MSA128WBits[] = {
1581  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
1582  };
1583 
1584  // MSA128B_with_sub_64_in_OddSP Register Class...
1585  static MCPhysReg MSA128B_with_sub_64_in_OddSP[] = {
1586  Mips_W1, Mips_W3, Mips_W5, Mips_W7, Mips_W9, Mips_W11, Mips_W13, Mips_W15, Mips_W17, Mips_W19, Mips_W21, Mips_W23, Mips_W25, Mips_W27, Mips_W29, Mips_W31,
1587  };
1588 
1589  // MSA128B_with_sub_64_in_OddSP Bit set.
1590  static uint8_t MSA128B_with_sub_64_in_OddSPBits[] = {
1591  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x55, 0x55, 0x55, 0x05,
1592  };
1593 
1594  // MSA128WEvens Register Class...
1595  static MCPhysReg MSA128WEvens[] = {
1596  Mips_W0, Mips_W2, Mips_W4, Mips_W6, Mips_W8, Mips_W10, Mips_W12, Mips_W14, Mips_W16, Mips_W18, Mips_W20, Mips_W22, Mips_W24, Mips_W26, Mips_W28, Mips_W30,
1597  };
1598 
1599  // MSA128WEvens Bit set.
1600  static uint8_t MSA128WEvensBits[] = {
1601  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa8, 0xaa, 0xaa, 0xaa, 0x02,
1602  };
1603 
1604  // ACC128 Register Class...
1605  static MCPhysReg ACC128[] = {
1606  Mips_AC0_64,
1607  };
1608 
1609  // ACC128 Bit set.
1610  static uint8_t ACC128Bits[] = {
1611  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
1612  };
1613 
1614 static MCRegisterClass MipsMCRegisterClasses[] = {
1615  { OddSP, OddSPBits, 236, 56, sizeof(OddSPBits), Mips_OddSPRegClassID, 4, 4, 1, 0 },
1616  { CCR, CCRBits, 432, 32, sizeof(CCRBits), Mips_CCRRegClassID, 4, 4, 1, 0 },
1617  { COP2, COP2Bits, 95, 32, sizeof(COP2Bits), Mips_COP2RegClassID, 4, 4, 1, 0 },
1618  { COP3, COP3Bits, 100, 32, sizeof(COP3Bits), Mips_COP3RegClassID, 4, 4, 1, 0 },
1619  { DSPR, DSPRBits, 436, 32, sizeof(DSPRBits), Mips_DSPRRegClassID, 4, 4, 1, 1 },
1620  { FGR32, FGR32Bits, 83, 32, sizeof(FGR32Bits), Mips_FGR32RegClassID, 4, 4, 1, 1 },
1621  { FGRCC, FGRCCBits, 167, 32, sizeof(FGRCCBits), Mips_FGRCCRegClassID, 4, 4, 1, 1 },
1622  { FGRH32, FGRH32Bits, 33, 32, sizeof(FGRH32Bits), Mips_FGRH32RegClassID, 4, 4, 1, 0 },
1623  { GPR32, GPR32Bits, 89, 32, sizeof(GPR32Bits), Mips_GPR32RegClassID, 4, 4, 1, 1 },
1624  { HWRegs, HWRegsBits, 760, 32, sizeof(HWRegsBits), Mips_HWRegsRegClassID, 4, 4, 1, 0 },
1625  { OddSP_with_sub_hi, OddSP_with_sub_hiBits, 509, 24, sizeof(OddSP_with_sub_hiBits), Mips_OddSP_with_sub_hiRegClassID, 4, 4, 1, 0 },
1626  { FGR32_and_OddSP, FGR32_and_OddSPBits, 242, 16, sizeof(FGR32_and_OddSPBits), Mips_FGR32_and_OddSPRegClassID, 4, 4, 1, 1 },
1627  { FGRH32_and_OddSP, FGRH32_and_OddSPBits, 225, 16, sizeof(FGRH32_and_OddSPBits), Mips_FGRH32_and_OddSPRegClassID, 4, 4, 1, 0 },
1628  { OddSP_with_sub_hi_with_sub_hi_in_FGRH32, OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits, 0, 16, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGRH32Bits), Mips_OddSP_with_sub_hi_with_sub_hi_in_FGRH32RegClassID, 4, 4, 1, 0 },
1629  { CPU16RegsPlusSP, CPU16RegsPlusSPBits, 325, 9, sizeof(CPU16RegsPlusSPBits), Mips_CPU16RegsPlusSPRegClassID, 4, 4, 1, 1 },
1630  { CC, CCBits, 158, 8, sizeof(CCBits), Mips_CCRegClassID, 4, 4, 1, 0 },
1631  { CPU16Regs, CPU16RegsBits, 750, 8, sizeof(CPU16RegsBits), Mips_CPU16RegsRegClassID, 4, 4, 1, 1 },
1632  { FCC, FCCBits, 157, 8, sizeof(FCCBits), Mips_FCCRegClassID, 4, 4, 1, 0 },
1633  { GPRMM16, GPRMM16Bits, 134, 8, sizeof(GPRMM16Bits), Mips_GPRMM16RegClassID, 4, 4, 1, 1 },
1634  { GPRMM16MoveP, GPRMM16MovePBits, 385, 8, sizeof(GPRMM16MovePBits), Mips_GPRMM16MovePRegClassID, 4, 4, 1, 1 },
1635  { GPRMM16Zero, GPRMM16ZeroBits, 573, 8, sizeof(GPRMM16ZeroBits), Mips_GPRMM16ZeroRegClassID, 4, 4, 1, 1 },
1636  { MSACtrl, MSACtrlBits, 527, 8, sizeof(MSACtrlBits), Mips_MSACtrlRegClassID, 4, 4, 1, 1 },
1637  { OddSP_with_sub_hi_with_sub_hi_in_FGR32, OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits, 50, 8, sizeof(OddSP_with_sub_hi_with_sub_hi_in_FGR32Bits), Mips_OddSP_with_sub_hi_with_sub_hi_in_FGR32RegClassID, 4, 4, 1, 0 },
1638  { CPU16Regs_and_GPRMM16Zero, CPU16Regs_and_GPRMM16ZeroBits, 623, 7, sizeof(CPU16Regs_and_GPRMM16ZeroBits), Mips_CPU16Regs_and_GPRMM16ZeroRegClassID, 4, 4, 1, 1 },
1639  { CPU16Regs_and_GPRMM16MoveP, CPU16Regs_and_GPRMM16MovePBits, 371, 4, sizeof(CPU16Regs_and_GPRMM16MovePBits), Mips_CPU16Regs_and_GPRMM16MovePRegClassID, 4, 4, 1, 1 },
1640  { GPRMM16MoveP_and_GPRMM16Zero, GPRMM16MoveP_and_GPRMM16ZeroBits, 556, 4, sizeof(GPRMM16MoveP_and_GPRMM16ZeroBits), Mips_GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 4, 4, 1, 1 },
1641  { HI32DSP, HI32DSPBits, 200, 4, sizeof(HI32DSPBits), Mips_HI32DSPRegClassID, 4, 4, 1, 1 },
1642  { LO32DSP, LO32DSPBits, 208, 4, sizeof(LO32DSPBits), Mips_LO32DSPRegClassID, 4, 4, 1, 1 },
1643  { GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 606, 3, sizeof(GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 4, 4, 1, 1 },
1644  { CPURAReg, CPURARegBits, 470, 1, sizeof(CPURARegBits), Mips_CPURARegRegClassID, 4, 4, 1, 0 },
1645  { CPUSPReg, CPUSPRegBits, 500, 1, sizeof(CPUSPRegBits), Mips_CPUSPRegRegClassID, 4, 4, 1, 0 },
1646  { DSPCC, DSPCCBits, 161, 1, sizeof(DSPCCBits), Mips_DSPCCRegClassID, 4, 4, 1, 1 },
1647  { HI32, HI32Bits, 40, 1, sizeof(HI32Bits), Mips_HI32RegClassID, 4, 4, 1, 1 },
1648  { LO32, LO32Bits, 45, 1, sizeof(LO32Bits), Mips_LO32RegClassID, 4, 4, 1, 1 },
1649  { FGR64, FGR64Bits, 122, 32, sizeof(FGR64Bits), Mips_FGR64RegClassID, 8, 8, 1, 1 },
1650  { GPR64, GPR64Bits, 128, 32, sizeof(GPR64Bits), Mips_GPR64RegClassID, 8, 8, 1, 1 },
1651  { AFGR64, AFGR64Bits, 121, 16, sizeof(AFGR64Bits), Mips_AFGR64RegClassID, 8, 8, 1, 1 },
1652  { FGR64_and_OddSP, FGR64_and_OddSPBits, 259, 16, sizeof(FGR64_and_OddSPBits), Mips_FGR64_and_OddSPRegClassID, 8, 8, 1, 1 },
1653  { GPR64_with_sub_32_in_CPU16RegsPlusSP, GPR64_with_sub_32_in_CPU16RegsPlusSPBits, 304, 9, sizeof(GPR64_with_sub_32_in_CPU16RegsPlusSPBits), Mips_GPR64_with_sub_32_in_CPU16RegsPlusSPRegClassID, 8, 8, 1, 1 },
1654  { AFGR64_and_OddSP, AFGR64_and_OddSPBits, 258, 8, sizeof(AFGR64_and_OddSPBits), Mips_AFGR64_and_OddSPRegClassID, 8, 8, 1, 1 },
1655  { GPR64_with_sub_32_in_CPU16Regs, GPR64_with_sub_32_in_CPU16RegsBits, 729, 8, sizeof(GPR64_with_sub_32_in_CPU16RegsBits), Mips_GPR64_with_sub_32_in_CPU16RegsRegClassID, 8, 8, 1, 1 },
1656  { GPR64_with_sub_32_in_GPRMM16MoveP, GPR64_with_sub_32_in_GPRMM16MovePBits, 398, 8, sizeof(GPR64_with_sub_32_in_GPRMM16MovePBits), Mips_GPR64_with_sub_32_in_GPRMM16MovePRegClassID, 8, 8, 1, 1 },
1657  { GPR64_with_sub_32_in_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16ZeroBits, 696, 8, sizeof(GPR64_with_sub_32_in_GPRMM16ZeroBits), Mips_GPR64_with_sub_32_in_GPRMM16ZeroRegClassID, 8, 8, 1, 1 },
1658  { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits, 649, 7, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroBits), Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClassID, 8, 8, 1, 1 },
1659  { ACC64DSP, ACC64DSPBits, 216, 4, sizeof(ACC64DSPBits), Mips_ACC64DSPRegClassID, 8, 8, 1, 1 },
1660  { GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MoveP, GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits, 350, 4, sizeof(GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePBits), Mips_GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClassID, 8, 8, 1, 1 },
1661  { GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits, 535, 4, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroBits), Mips_GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID, 8, 8, 1, 1 },
1662  { GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16Zero, GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits, 585, 3, sizeof(GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroBits), Mips_GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID, 8, 8, 1, 1 },
1663  { OCTEON_MPL, OCTEON_MPLBits, 189, 3, sizeof(OCTEON_MPLBits), Mips_OCTEON_MPLRegClassID, 8, 8, 1, 0 },
1664  { OCTEON_P, OCTEON_PBits, 341, 3, sizeof(OCTEON_PBits), Mips_OCTEON_PRegClassID, 8, 8, 1, 0 },
1665  { ACC64, ACC64Bits, 105, 1, sizeof(ACC64Bits), Mips_ACC64RegClassID, 8, 8, 1, 1 },
1666  { GPR64_with_sub_32_in_CPURAReg, GPR64_with_sub_32_in_CPURARegBits, 449, 1, sizeof(GPR64_with_sub_32_in_CPURARegBits), Mips_GPR64_with_sub_32_in_CPURARegRegClassID, 8, 8, 1, 1 },
1667  { GPR64_with_sub_32_in_CPUSPReg, GPR64_with_sub_32_in_CPUSPRegBits, 479, 1, sizeof(GPR64_with_sub_32_in_CPUSPRegBits), Mips_GPR64_with_sub_32_in_CPUSPRegRegClassID, 8, 8, 1, 1 },
1668  { HI64, HI64Bits, 111, 1, sizeof(HI64Bits), Mips_HI64RegClassID, 8, 8, 1, 1 },
1669  { LO64, LO64Bits, 116, 1, sizeof(LO64Bits), Mips_LO64RegClassID, 8, 8, 1, 1 },
1670  { MSA128B, MSA128BBits, 149, 32, sizeof(MSA128BBits), Mips_MSA128BRegClassID, 16, 16, 1, 1 },
1671  { MSA128D, MSA128DBits, 173, 32, sizeof(MSA128DBits), Mips_MSA128DRegClassID, 16, 16, 1, 1 },
1672  { MSA128H, MSA128HBits, 181, 32, sizeof(MSA128HBits), Mips_MSA128HRegClassID, 16, 16, 1, 1 },
1673  { MSA128W, MSA128WBits, 441, 32, sizeof(MSA128WBits), Mips_MSA128WRegClassID, 16, 16, 1, 1 },
1674  { MSA128B_with_sub_64_in_OddSP, MSA128B_with_sub_64_in_OddSPBits, 275, 16, sizeof(MSA128B_with_sub_64_in_OddSPBits), Mips_MSA128B_with_sub_64_in_OddSPRegClassID, 16, 16, 1, 1 },
1675  { MSA128WEvens, MSA128WEvensBits, 767, 16, sizeof(MSA128WEvensBits), Mips_MSA128WEvensRegClassID, 16, 16, 1, 1 },
1676  { ACC128, ACC128Bits, 142, 1, sizeof(ACC128Bits), Mips_ACC128RegClassID, 16, 16, 1, 1 },
1677 };
1678 
1679 #endif // GET_REGINFO_MC_DESC
MCPhysReg
uint16_t MCPhysReg
Definition: MCRegisterInfo.h:26
COP2
#define COP2
Definition: rsp_idec.c:510
uint16_t
unsigned short uint16_t
Definition: sftypes.h:30
uint8_t
unsigned char uint8_t
Definition: sftypes.h:31
FCC
#define FCC(x)
Definition: sparc-opc.c:160