ARMAddressingModes.h File Reference

#include "capstone/platform.h"
#include "../../MathExtras.h"

Go to the source code of this file.

Typedefs
typedef enum ARM_AM_ShiftOpc	ARM_AM_ShiftOpc
	ARM_AM - ARM Addressing Mode Stuff. More...
typedef enum ARM_AM_AddrOpc	ARM_AM_AddrOpc
typedef enum ARM_AM_AMSubMode	ARM_AM_AMSubMode

Enumerations
enum	ARM_AM_ShiftOpc {   ARM_AM_no_shift = 0 , ARM_AM_asr , ARM_AM_lsl , ARM_AM_lsr ,   ARM_AM_ror , ARM_AM_rrx }
	ARM_AM - ARM Addressing Mode Stuff. More...
enum	ARM_AM_AddrOpc { ARM_AM_sub = 0 , ARM_AM_add }
enum	ARM_AM_AMSubMode {   ARM_AM_bad_am_submode = 0 , ARM_AM_ia , ARM_AM_ib , ARM_AM_da ,   ARM_AM_db }

Functions
static const char *	ARM_AM_getAddrOpcStr (ARM_AM_AddrOpc Op)
static const char *	ARM_AM_getShiftOpcStr (ARM_AM_ShiftOpc Op)
static unsigned	ARM_AM_getShiftOpcEncoding (ARM_AM_ShiftOpc Op)
static const char *	ARM_AM_getAMSubModeStr (ARM_AM_AMSubMode Mode)
static unsigned	rotr32 (unsigned Val, unsigned Amt)
static unsigned	rotl32 (unsigned Val, unsigned Amt)
static unsigned	getSORegOpc (ARM_AM_ShiftOpc ShOp, unsigned Imm)
static unsigned	getSORegOffset (unsigned Op)
static ARM_AM_ShiftOpc	ARM_AM_getSORegShOp (unsigned Op)
static unsigned	getSOImmValImm (unsigned Imm)
static unsigned	getSOImmValRot (unsigned Imm)
static unsigned	getSOImmValRotate (unsigned Imm)
static int	getSOImmVal (unsigned Arg)
static bool	isSOImmTwoPartVal (unsigned V)
static unsigned	getSOImmTwoPartFirst (unsigned V)
static unsigned	getSOImmTwoPartSecond (unsigned V)
static unsigned	getThumbImmValShift (unsigned Imm)
static bool	isThumbImmShiftedVal (unsigned V)
static unsigned	getThumbImm16ValShift (unsigned Imm)
static bool	isThumbImm16ShiftedVal (unsigned V)
static unsigned	getThumbImmNonShiftedVal (unsigned V)
static int	getT2SOImmValSplatVal (unsigned V)
static int	getT2SOImmValRotateVal (unsigned V)
static int	getT2SOImmVal (unsigned Arg)
static unsigned	getT2SOImmValRotate (unsigned V)
static bool	isT2SOImmTwoPartVal (unsigned Imm)
static unsigned	getT2SOImmTwoPartFirst (unsigned Imm)
static unsigned	getT2SOImmTwoPartSecond (unsigned Imm)
static unsigned	ARM_AM_getAM2Opc (ARM_AM_AddrOpc Opc, unsigned Imm12, ARM_AM_ShiftOpc SO, unsigned IdxMode)
static unsigned	getAM2Offset (unsigned AM2Opc)
static ARM_AM_AddrOpc	getAM2Op (unsigned AM2Opc)
static ARM_AM_ShiftOpc	getAM2ShiftOpc (unsigned AM2Opc)
static unsigned	getAM2IdxMode (unsigned AM2Opc)
static unsigned	getAM3Opc (ARM_AM_AddrOpc Opc, unsigned char Offset, unsigned IdxMode)
	getAM3Opc - This function encodes the addrmode3 opc field. More...
static unsigned char	getAM3Offset (unsigned AM3Opc)
static ARM_AM_AddrOpc	getAM3Op (unsigned AM3Opc)
static unsigned	getAM3IdxMode (unsigned AM3Opc)
static ARM_AM_AMSubMode	getAM4SubMode (unsigned Mode)
static unsigned	getAM4ModeImm (ARM_AM_AMSubMode SubMode)
static unsigned	ARM_AM_getAM5Opc (ARM_AM_AddrOpc Opc, unsigned char Offset)
	getAM5Opc - This function encodes the addrmode5 opc field. More...
static unsigned char	ARM_AM_getAM5Offset (unsigned AM5Opc)
static ARM_AM_AddrOpc	ARM_AM_getAM5Op (unsigned AM5Opc)
static unsigned	createNEONModImm (unsigned OpCmode, unsigned Val)
static unsigned	getNEONModImmOpCmode (unsigned ModImm)
static unsigned	getNEONModImmVal (unsigned ModImm)
static uint64_t	ARM_AM_decodeNEONModImm (unsigned ModImm, unsigned *EltBits)
ARM_AM_AMSubMode	getLoadStoreMultipleSubMode (int Opcode)
static float	getFPImmFloat (unsigned Imm)

Typedef Documentation

ARM_AM_AddrOpc

typedef enum ARM_AM_AddrOpc ARM_AM_AddrOpc

ARM_AM_AMSubMode

typedef enum ARM_AM_AMSubMode ARM_AM_AMSubMode

ARM_AM_ShiftOpc

typedef enum ARM_AM_ShiftOpc ARM_AM_ShiftOpc

ARM_AM - ARM Addressing Mode Stuff.

Enumeration Type Documentation

ARM_AM_AddrOpc

enum ARM_AM_AddrOpc

Enumerator
ARM_AM_sub
ARM_AM_add

Definition at line 33 of file ARMAddressingModes.h.

                            {
    ARM_AM_sub = 0,
    ARM_AM_add
} ARM_AM_AddrOpc;

ARM_AM_AMSubMode

enum ARM_AM_AMSubMode

Enumerator
ARM_AM_bad_am_submode
ARM_AM_ia
ARM_AM_ib
ARM_AM_da
ARM_AM_db

Definition at line 66 of file ARMAddressingModes.h.

                              {
    ARM_AM_bad_am_submode = 0,
    ARM_AM_ia,
    ARM_AM_ib,
    ARM_AM_da,
    ARM_AM_db
} ARM_AM_AMSubMode;

ARM_AM_ShiftOpc

enum ARM_AM_ShiftOpc

ARM_AM - ARM Addressing Mode Stuff.

Enumerator
ARM_AM_no_shift
ARM_AM_asr
ARM_AM_lsl
ARM_AM_lsr
ARM_AM_ror
ARM_AM_rrx

Definition at line 24 of file ARMAddressingModes.h.

                             {
    ARM_AM_no_shift = 0,
    ARM_AM_asr,
    ARM_AM_lsl,
    ARM_AM_lsr,
    ARM_AM_ror,
    ARM_AM_rrx
} ARM_AM_ShiftOpc;

Function Documentation

ARM_AM_decodeNEONModImm()

static uint64_t ARM_AM_decodeNEONModImm ( unsigned  ModImm, unsigned *  EltBits  )

inlinestatic

decodeNEONModImm - Decode a NEON modified immediate value into the element value and the element size in bits. (If the element size is smaller than the vector, it is splatted into all the elements.)

Definition at line 599 of file ARMAddressingModes.h.

{
    unsigned OpCmode = getNEONModImmOpCmode(ModImm);
    unsigned Imm8 = getNEONModImmVal(ModImm);
    uint64_t Val = 0;
    unsigned ByteNum;
 
    if (OpCmode == 0xe) {
        // 8-bit vector elements
        Val = Imm8;
        *EltBits = 8;
    } else if ((OpCmode & 0xc) == 0x8) {
        // 16-bit vector elements
        ByteNum = (OpCmode & 0x6) >> 1;
        Val = (uint64_t)Imm8 << (8 * ByteNum);
        *EltBits = 16;
    } else if ((OpCmode & 0x8) == 0) {
        // 32-bit vector elements, zero with one byte set
        ByteNum = (OpCmode & 0x6) >> 1;
        Val = (uint64_t)Imm8 << (8 * ByteNum);
        *EltBits = 32;
    } else if ((OpCmode & 0xe) == 0xc) {
        // 32-bit vector elements, one byte with low bits set
        ByteNum = 1 + (OpCmode & 0x1);
        Val = (Imm8 << (8 * ByteNum)) | (0xffff >> (8 * (2 - ByteNum)));
        *EltBits = 32;
    } else if (OpCmode == 0x1e) {
        // 64-bit vector elements
        for (ByteNum = 0; ByteNum < 8; ++ByteNum) {
            if ((ModImm >> ByteNum) & 1)
                Val |= (uint64_t)0xff << (8 * ByteNum);
        }
        *EltBits = 64;
    } else {
        //llvm_unreachable("Unsupported NEON immediate");
    }
    return Val;
}

References getNEONModImmOpCmode(), and getNEONModImmVal().

ARM_AM_getAddrOpcStr()

static const char* ARM_AM_getAddrOpcStr ( ARM_AM_AddrOpc  Op )

inlinestatic

Definition at line 38 of file ARMAddressingModes.h.

{
    return Op == ARM_AM_sub ? "-" : "";
}

References ARM_AM_sub.

ARM_AM_getAM2Opc()

static unsigned ARM_AM_getAM2Opc ( ARM_AM_AddrOpc  Opc, unsigned  Imm12, ARM_AM_ShiftOpc  SO, unsigned  IdxMode  )

inlinestatic

Definition at line 442 of file ARMAddressingModes.h.

{
    //assert(Imm12 < (1 << 12) && "Imm too large!");
    bool isSub = Opc == ARM_AM_sub;
    return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ;
}

References ARM_AM_sub, and int.

ARM_AM_getAM5Offset()

static unsigned char ARM_AM_getAM5Offset ( unsigned  AM5Opc )

inlinestatic

Definition at line 549 of file ARMAddressingModes.h.

{
    return AM5Opc & 0xFF;
}

ARM_AM_getAM5Op()

static ARM_AM_AddrOpc ARM_AM_getAM5Op ( unsigned  AM5Opc )

inlinestatic

Definition at line 553 of file ARMAddressingModes.h.

{
    return ((AM5Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add;
}

References ARM_AM_add, and ARM_AM_sub.

ARM_AM_getAM5Opc()

static unsigned ARM_AM_getAM5Opc ( ARM_AM_AddrOpc  Opc, unsigned char  Offset  )

inlinestatic

getAM5Opc - This function encodes the addrmode5 opc field.

Definition at line 544 of file ARMAddressingModes.h.

{
    bool isSub = Opc == ARM_AM_sub;
    return ((int)isSub << 8) | Offset;
}

References ARM_AM_sub, and Offset.

ARM_AM_getAMSubModeStr()

static const char* ARM_AM_getAMSubModeStr ( ARM_AM_AMSubMode  Mode )

inlinestatic

Definition at line 74 of file ARMAddressingModes.h.

{
    switch (Mode) {
        default: return "";
        case ARM_AM_ia: return "ia";
        case ARM_AM_ib: return "ib";
        case ARM_AM_da: return "da";
        case ARM_AM_db: return "db";
    }
}

References ARM_AM_da, ARM_AM_db, ARM_AM_ia, and ARM_AM_ib.

ARM_AM_getShiftOpcEncoding()

static unsigned ARM_AM_getShiftOpcEncoding ( ARM_AM_ShiftOpc  Op )

inlinestatic

Definition at line 55 of file ARMAddressingModes.h.

{
    switch (Op) {
        default: return (unsigned int)-1;   //llvm_unreachable("Unknown shift opc!");
        case ARM_AM_asr: return 2;
        case ARM_AM_lsl: return 0;
        case ARM_AM_lsr: return 1;
        case ARM_AM_ror: return 3;
    }
}

References ARM_AM_asr, ARM_AM_lsl, ARM_AM_lsr, and ARM_AM_ror.

ARM_AM_getShiftOpcStr()

static const char* ARM_AM_getShiftOpcStr ( ARM_AM_ShiftOpc  Op )

inlinestatic

Definition at line 43 of file ARMAddressingModes.h.

{
    switch (Op) {
        default: return ""; //llvm_unreachable("Unknown shift opc!");
        case ARM_AM_asr: return "asr";
        case ARM_AM_lsl: return "lsl";
        case ARM_AM_lsr: return "lsr";
        case ARM_AM_ror: return "ror";
        case ARM_AM_rrx: return "rrx";
    }
}

References ARM_AM_asr, ARM_AM_lsl, ARM_AM_lsr, ARM_AM_ror, and ARM_AM_rrx.

ARM_AM_getSORegShOp()

static ARM_AM_ShiftOpc ARM_AM_getSORegShOp ( unsigned  Op )

inlinestatic

Definition at line 125 of file ARMAddressingModes.h.

{
    return (ARM_AM_ShiftOpc)(Op & 7);
}

createNEONModImm()

static unsigned createNEONModImm ( unsigned  OpCmode, unsigned  Val  )

inlinestatic

Definition at line 583 of file ARMAddressingModes.h.

{
    return (OpCmode << 8) | Val;
}

getAM2IdxMode()

static unsigned getAM2IdxMode ( unsigned  AM2Opc )

inlinestatic

Definition at line 465 of file ARMAddressingModes.h.

{
    return (AM2Opc >> 16);
}

getAM2Offset()

static unsigned getAM2Offset ( unsigned  AM2Opc )

inlinestatic

Definition at line 450 of file ARMAddressingModes.h.

{
    return AM2Opc & ((1 << 12)-1);
}

getAM2Op()

static ARM_AM_AddrOpc getAM2Op ( unsigned  AM2Opc )

inlinestatic

Definition at line 455 of file ARMAddressingModes.h.

{
    return ((AM2Opc >> 12) & 1) ? ARM_AM_sub : ARM_AM_add;
}

References ARM_AM_add, and ARM_AM_sub.

getAM2ShiftOpc()

static ARM_AM_ShiftOpc getAM2ShiftOpc ( unsigned  AM2Opc )

inlinestatic

Definition at line 460 of file ARMAddressingModes.h.

{
    return (ARM_AM_ShiftOpc)((AM2Opc >> 13) & 7);
}

getAM3IdxMode()

static unsigned getAM3IdxMode ( unsigned  AM3Opc )

inlinestatic

Definition at line 502 of file ARMAddressingModes.h.

{
    return (AM3Opc >> 9);
}

getAM3Offset()

static unsigned char getAM3Offset ( unsigned  AM3Opc )

inlinestatic

Definition at line 492 of file ARMAddressingModes.h.

{
    return AM3Opc & 0xFF;
}

getAM3Op()

static ARM_AM_AddrOpc getAM3Op ( unsigned  AM3Opc )

inlinestatic

Definition at line 497 of file ARMAddressingModes.h.

{
    return ((AM3Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add;
}

References ARM_AM_add, and ARM_AM_sub.

getAM3Opc()

static unsigned getAM3Opc ( ARM_AM_AddrOpc  Opc, unsigned char  Offset, unsigned  IdxMode  )

inlinestatic

getAM3Opc - This function encodes the addrmode3 opc field.

Definition at line 485 of file ARMAddressingModes.h.

{
    bool isSub = Opc == ARM_AM_sub;
    return ((int)isSub << 8) | Offset | (IdxMode << 9);
}

References ARM_AM_sub, and Offset.

getAM4ModeImm()

static unsigned getAM4ModeImm ( ARM_AM_AMSubMode  SubMode )

inlinestatic

Definition at line 527 of file ARMAddressingModes.h.

{
    return (int)SubMode;
}

getAM4SubMode()

static ARM_AM_AMSubMode getAM4SubMode ( unsigned  Mode )

inlinestatic

Definition at line 522 of file ARMAddressingModes.h.

{
    return (ARM_AM_AMSubMode)(Mode & 0x7);
}

getFPImmFloat()

static float getFPImmFloat ( unsigned  Imm )

inlinestatic

Definition at line 643 of file ARMAddressingModes.h.

{
    // We expect an 8-bit binary encoding of a floating-point number here.
    union {
        uint32_t I;
        float F;
    } FPUnion;
 
    uint8_t Sign = (Imm >> 7) & 0x1;
    uint8_t Exp = (Imm >> 4) & 0x7;
    uint8_t Mantissa = Imm & 0xf;
 
    //   8-bit FP    iEEEE Float Encoding
    //   abcd efgh   aBbbbbbc defgh000 00000000 00000000
    //
    // where B = NOT(b);
 
    FPUnion.I = 0;
    FPUnion.I |= ((uint32_t) Sign) << 31;
    FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
    FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
    FPUnion.I |= (Exp & 0x3) << 23;
    FPUnion.I |= Mantissa << 19;
    return FPUnion.F;
}

References F, and I.

getLoadStoreMultipleSubMode()

ARM_AM_AMSubMode getLoadStoreMultipleSubMode

(

int

Opcode

)

getNEONModImmOpCmode()

static unsigned getNEONModImmOpCmode ( unsigned  ModImm )

inlinestatic

Definition at line 587 of file ARMAddressingModes.h.

{
    return (ModImm >> 8) & 0x1f;
}

Referenced by ARM_AM_decodeNEONModImm().

getNEONModImmVal()

static unsigned getNEONModImmVal ( unsigned  ModImm )

inlinestatic

Definition at line 591 of file ARMAddressingModes.h.

{
    return ModImm & 0xff;
}

Referenced by ARM_AM_decodeNEONModImm().

getSOImmTwoPartFirst()

static unsigned getSOImmTwoPartFirst ( unsigned  V )

inlinestatic

getSOImmTwoPartFirst - If V is a value that satisfies isSOImmTwoPartVal, return the first chunk of it.

Definition at line 217 of file ARMAddressingModes.h.

{
    return rotr32(255U, getSOImmValRotate(V)) & V;
}

References getSOImmValRotate(), rotr32(), and V.

getSOImmTwoPartSecond()

static unsigned getSOImmTwoPartSecond ( unsigned  V )

inlinestatic

getSOImmTwoPartSecond - If V is a value that satisfies isSOImmTwoPartVal, return the second chunk of it.

Definition at line 224 of file ARMAddressingModes.h.

{
    // Mask out the first hunk.
    V = rotr32(~255U, getSOImmValRotate(V)) & V;
 
    // Take what's left.
    //assert(V == (rotr32(255U, getSOImmValRotate(V)) & V));
    return V;
}

References getSOImmValRotate(), rotr32(), and V.

getSOImmVal()

static int getSOImmVal ( unsigned  Arg )

inlinestatic

getSOImmVal - Given a 32-bit immediate, if it is something that can fit into an shifter_operand immediate operand, return the 12-bit encoding for it. If not, return -1.

Definition at line 184 of file ARMAddressingModes.h.

{
    unsigned RotAmt;
    // 8-bit (or less) immediates are trivially shifter_operands with a rotate
    // of zero.
    if ((Arg & ~255U) == 0) return Arg;
 
    RotAmt = getSOImmValRotate(Arg);
 
    // If this cannot be handled with a single shifter_op, bail out.
    if (rotr32(~255U, RotAmt) & Arg)
        return -1;
 
    // Encode this correctly.
    return rotl32(Arg, RotAmt) | ((RotAmt>>1) << 8);
}

References getSOImmValRotate(), rotl32(), and rotr32().

getSOImmValImm()

static unsigned getSOImmValImm ( unsigned  Imm )

inlinestatic

getSOImmValImm - Given an encoded imm field for the reg/imm form, return the 8-bit imm value.

Definition at line 132 of file ARMAddressingModes.h.

{
    return Imm & 0xFF;
}

getSOImmValRot()

static unsigned getSOImmValRot ( unsigned  Imm )

inlinestatic

getSOImmValRot - Given an encoded imm field for the reg/imm form, return the rotate amount.

Definition at line 139 of file ARMAddressingModes.h.

{
    return (Imm >> 8) * 2;
}

getSOImmValRotate()

static unsigned getSOImmValRotate ( unsigned  Imm )

inlinestatic

getSOImmValRotate - Try to handle Imm with an immediate shifter operand, computing the rotate amount to use. If this immediate value cannot be handled with a single shifter-op, determine a good rotate amount that will take a maximal chunk of bits out of the immediate.

Definition at line 148 of file ARMAddressingModes.h.

{
    unsigned TZ, RotAmt;
    // 8-bit (or less) immediates are trivially shifter_operands with a rotate
    // of zero.
    if ((Imm & ~255U) == 0) return 0;
 
    // Use CTZ to compute the rotate amount.
    TZ = CountTrailingZeros_32(Imm);
 
    // Rotate amount must be even.  Something like 0x200 must be rotated 8 bits,
    // not 9.
    RotAmt = TZ & ~1;
 
    // If we can handle this spread, return it.
    if ((rotr32(Imm, RotAmt) & ~255U) == 0)
        return (32-RotAmt)&31;  // HW rotates right, not left.
 
    // For values like 0xF000000F, we should ignore the low 6 bits, then
    // retry the hunt.
    if (Imm & 63U) {
        unsigned TZ2 = CountTrailingZeros_32(Imm & ~63U);
        unsigned RotAmt2 = TZ2 & ~1;
        if ((rotr32(Imm, RotAmt2) & ~255U) == 0)
            return (32-RotAmt2)&31;  // HW rotates right, not left.
    }
 
    // Otherwise, we have no way to cover this span of bits with a single
    // shifter_op immediate.  Return a chunk of bits that will be useful to
    // handle.
    return (32-RotAmt)&31;  // HW rotates right, not left.
}

References CountTrailingZeros_32(), and rotr32().

Referenced by getSOImmTwoPartFirst(), getSOImmTwoPartSecond(), getSOImmVal(), and isSOImmTwoPartVal().

getSORegOffset()

static unsigned getSORegOffset ( unsigned  Op )

inlinestatic

Definition at line 120 of file ARMAddressingModes.h.

{
    return Op >> 3;
}

getSORegOpc()

static unsigned getSORegOpc ( ARM_AM_ShiftOpc  ShOp, unsigned  Imm  )

inlinestatic

Definition at line 115 of file ARMAddressingModes.h.

{
    return ShOp | (Imm << 3);
}

getT2SOImmTwoPartFirst()

static unsigned getT2SOImmTwoPartFirst ( unsigned  Imm )

inlinestatic

Definition at line 395 of file ARMAddressingModes.h.

{
    //assert (isT2SOImmTwoPartVal(Imm) &&
    //        "Immedate cannot be encoded as two part immediate!");
    // Try a shifter operand as one part
    unsigned V = rotr32 (~(unsigned int)255, getT2SOImmValRotate(Imm)) & Imm;
    // If the rest is encodable as an immediate, then return it.
    if (getT2SOImmVal(V) != -1) return V;
 
    // Try masking out a splat value first.
    if (getT2SOImmValSplatVal(Imm & 0xff00ff00U) != -1)
        return Imm & 0xff00ff00U;
 
    // The other splat is all that's left as an option.
    //assert (getT2SOImmValSplatVal(Imm & 0x00ff00ffU) != -1);
    return Imm & 0x00ff00ffU;
}

References getT2SOImmVal(), getT2SOImmValRotate(), getT2SOImmValSplatVal(), rotr32(), and V.

Referenced by getT2SOImmTwoPartSecond().

getT2SOImmTwoPartSecond()

static unsigned getT2SOImmTwoPartSecond ( unsigned  Imm )

inlinestatic

Definition at line 413 of file ARMAddressingModes.h.

{
    // Mask out the first hunk
    Imm ^= getT2SOImmTwoPartFirst(Imm);
    // Return what's left
    //assert (getT2SOImmVal(Imm) != -1 &&
    //        "Unable to encode second part of T2 two part SO immediate");
    return Imm;
}

References getT2SOImmTwoPartFirst().

getT2SOImmVal()

static int getT2SOImmVal ( unsigned  Arg )

inlinestatic

getT2SOImmVal - Given a 32-bit immediate, if it is something that can fit into a Thumb-2 shifter_operand immediate operand, return the 12-bit encoding for it. If not, return -1. See ARM Reference Manual A6.3.2.

Definition at line 339 of file ARMAddressingModes.h.

{
    int Rot;
    // If 'Arg' is an 8-bit splat, then get the encoded value.
    int Splat = getT2SOImmValSplatVal(Arg);
    if (Splat != -1)
        return Splat;
 
    // If 'Arg' can be handled with a single shifter_op return the value.
    Rot = getT2SOImmValRotateVal(Arg);
    if (Rot != -1)
        return Rot;
 
    return -1;
}

References getT2SOImmValRotateVal(), and getT2SOImmValSplatVal().

Referenced by getT2SOImmTwoPartFirst(), and isT2SOImmTwoPartVal().

getT2SOImmValRotate()

static unsigned getT2SOImmValRotate ( unsigned  V )

inlinestatic

Definition at line 355 of file ARMAddressingModes.h.

{
    unsigned RotAmt;
 
    if ((V & ~255U) == 0)
        return 0;
 
    // Use CTZ to compute the rotate amount.
    RotAmt = CountTrailingZeros_32(V);
    return (32 - RotAmt) & 31;
}

References CountTrailingZeros_32(), and V.

Referenced by getT2SOImmTwoPartFirst(), and isT2SOImmTwoPartVal().

getT2SOImmValRotateVal()

static int getT2SOImmValRotateVal ( unsigned  V )

inlinestatic

getT2SOImmValRotateVal - Return the 12-bit encoded representation if the specified value is a rotated 8-bit value. Return -1 if no rotation encoding is possible. See ARM Reference Manual A6.3.2.

Definition at line 322 of file ARMAddressingModes.h.

{
    unsigned RotAmt = CountLeadingZeros_32(V);
    if (RotAmt >= 24)
        return -1;
 
    // If 'Arg' can be handled with a single shifter_op return the value.
    if ((rotr32(0xff000000U, RotAmt) & V) == V)
        return (rotr32(V, 24 - RotAmt) & 0x7f) | ((RotAmt + 8) << 7);
 
    return -1;
}

References CountLeadingZeros_32(), rotr32(), and V.

Referenced by getT2SOImmVal().

getT2SOImmValSplatVal()

static int getT2SOImmValSplatVal ( unsigned  V )

inlinestatic

getT2SOImmValSplat - Return the 12-bit encoded representation if the specified value can be obtained by splatting the low 8 bits into every other byte or every byte of a 32-bit value. i.e., 00000000 00000000 00000000 abcdefgh control = 0 00000000 abcdefgh 00000000 abcdefgh control = 1 abcdefgh 00000000 abcdefgh 00000000 control = 2 abcdefgh abcdefgh abcdefgh abcdefgh control = 3 Return -1 if none of the above apply. See ARM Reference Manual A6.3.2.

Definition at line 293 of file ARMAddressingModes.h.

{
    unsigned u, Vs, Imm;
    // control = 0
    if ((V & 0xffffff00) == 0)
        return V;
 
    // If the value is zeroes in the first byte, just shift those off
    Vs = ((V & 0xff) == 0) ? V >> 8 : V;
    // Any passing value only has 8 bits of payload, splatted across the word
    Imm = Vs & 0xff;
    // Likewise, any passing values have the payload splatted into the 3rd byte
    u = Imm | (Imm << 16);
 
    // control = 1 or 2
    if (Vs == u)
        return (((Vs == V) ? 1 : 2) << 8) | Imm;
 
    // control = 3
    if (Vs == (u | (u << 8)))
        return (3 << 8) | Imm;
 
    return -1;
}

References V.

Referenced by getT2SOImmTwoPartFirst(), getT2SOImmVal(), and isT2SOImmTwoPartVal().

getThumbImm16ValShift()

static unsigned getThumbImm16ValShift ( unsigned  Imm )

inlinestatic

getThumbImm16ValShift - Try to handle Imm with a 16-bit immediate followed by a left shift. Returns the shift amount to use.

Definition at line 257 of file ARMAddressingModes.h.

{
    // 16-bit (or less) immediates are trivially immediate operand with a shift
    // of zero.
    if ((Imm & ~65535U) == 0) return 0;
 
    // Use CTZ to compute the shift amount.
    return CountTrailingZeros_32(Imm);
}

References CountTrailingZeros_32().

Referenced by isThumbImm16ShiftedVal().

getThumbImmNonShiftedVal()

static unsigned getThumbImmNonShiftedVal ( unsigned  V )

inlinestatic

getThumbImmNonShiftedVal - If V is a value that satisfies isThumbImmShiftedVal, return the non-shiftd value.

Definition at line 278 of file ARMAddressingModes.h.

{
    return V >> getThumbImmValShift(V);
}

References getThumbImmValShift(), and V.

getThumbImmValShift()

static unsigned getThumbImmValShift ( unsigned  Imm )

inlinestatic

getThumbImmValShift - Try to handle Imm with a 8-bit immediate followed by a left shift. Returns the shift amount to use.

Definition at line 236 of file ARMAddressingModes.h.

{
    // 8-bit (or less) immediates are trivially immediate operand with a shift
    // of zero.
    if ((Imm & ~255U) == 0) return 0;
 
    // Use CTZ to compute the shift amount.
    return CountTrailingZeros_32(Imm);
}

References CountTrailingZeros_32().

Referenced by getThumbImmNonShiftedVal(), and isThumbImmShiftedVal().

isSOImmTwoPartVal()

static bool isSOImmTwoPartVal ( unsigned  V )

inlinestatic

isSOImmTwoPartVal - Return true if the specified value can be obtained by or'ing together two SOImmVal's.

Definition at line 203 of file ARMAddressingModes.h.

{
    // If this can be handled with a single shifter_op, bail out.
    V = rotr32(~255U, getSOImmValRotate(V)) & V;
    if (V == 0)
        return false;
 
    // If this can be handled with two shifter_op's, accept.
    V = rotr32(~255U, getSOImmValRotate(V)) & V;
    return V == 0;
}

References getSOImmValRotate(), rotr32(), and V.

isT2SOImmTwoPartVal()

static bool isT2SOImmTwoPartVal ( unsigned  Imm )

inlinestatic

Definition at line 367 of file ARMAddressingModes.h.

{
    unsigned V = Imm;
    // Passing values can be any combination of splat values and shifter
    // values. If this can be handled with a single shifter or splat, bail
    // out. Those should be handled directly, not with a two-part val.
    if (getT2SOImmValSplatVal(V) != -1)
        return false;
    V = rotr32 (~255U, getT2SOImmValRotate(V)) & V;
    if (V == 0)
        return false;
 
    // If this can be handled as an immediate, accept.
    if (getT2SOImmVal(V) != -1) return true;
 
    // Likewise, try masking out a splat value first.
    V = Imm;
    if (getT2SOImmValSplatVal(V & 0xff00ff00U) != -1)
        V &= ~0xff00ff00U;
    else if (getT2SOImmValSplatVal(V & 0x00ff00ffU) != -1)
        V &= ~0x00ff00ffU;
    // If what's left can be handled as an immediate, accept.
    if (getT2SOImmVal(V) != -1) return true;
 
    // Otherwise, do not accept.
    return false;
}

References getT2SOImmVal(), getT2SOImmValRotate(), getT2SOImmValSplatVal(), rotr32(), and V.

isThumbImm16ShiftedVal()

static bool isThumbImm16ShiftedVal ( unsigned  V )

inlinestatic

isThumbImm16ShiftedVal - Return true if the specified value can be obtained by left shifting a 16-bit immediate.

Definition at line 269 of file ARMAddressingModes.h.

{
    // If this can be handled with
    V = (~65535U << getThumbImm16ValShift(V)) & V;
    return V == 0;
}

References getThumbImm16ValShift(), and V.

isThumbImmShiftedVal()

static bool isThumbImmShiftedVal ( unsigned  V )

inlinestatic

isThumbImmShiftedVal - Return true if the specified value can be obtained by left shifting a 8-bit immediate.

Definition at line 248 of file ARMAddressingModes.h.

{
    // If this can be handled with
    V = (~255U << getThumbImmValShift(V)) & V;
    return V == 0;
}

References getThumbImmValShift(), and V.

rotl32()

static unsigned rotl32 ( unsigned  Val, unsigned  Amt  )

inlinestatic

rotl32 - Rotate a 32-bit unsigned value left by a specified # bits.

Definition at line 95 of file ARMAddressingModes.h.

{
    //assert(Amt < 32 && "Invalid rotate amount");
    return (Val << Amt) | (Val >> ((32-Amt)&31));
}

Referenced by getSOImmVal().

rotr32()

static unsigned rotr32 ( unsigned  Val, unsigned  Amt  )

inlinestatic

rotr32 - Rotate a 32-bit unsigned value right by a specified # bits.

Definition at line 87 of file ARMAddressingModes.h.

{
    //assert(Amt < 32 && "Invalid rotate amount");
    return (Val >> Amt) | (Val << ((32-Amt)&31));
}

Referenced by getSOImmTwoPartFirst(), getSOImmTwoPartSecond(), getSOImmVal(), getSOImmValRotate(), getT2SOImmTwoPartFirst(), getT2SOImmValRotateVal(), isSOImmTwoPartVal(), and isT2SOImmTwoPartVal().