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AArch64Disassembler.c
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1 //===- AArch64Disassembler.cpp - Disassembler for AArch64 ISA -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the functions necessary to decode AArch64 instruction
11 // bitpatterns into MCInsts (with the help of TableGenerated information from
12 // the instruction definitions).
13 //
14 //===----------------------------------------------------------------------===//
15 
16 /* Capstone Disassembly Engine */
17 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
18 
19 #ifdef CAPSTONE_HAS_ARM64
20 
21 #include <stdio.h> // DEBUG
22 #include <stdlib.h>
23 
24 #include "../../cs_priv.h"
25 #include "../../utils.h"
26 
27 #include "AArch64Disassembler.h"
28 
29 #include "../../MCInst.h"
30 #include "../../MCInstrDesc.h"
31 #include "../../MCFixedLenDisassembler.h"
32 #include "../../MCRegisterInfo.h"
33 #include "../../MCDisassembler.h"
34 
35 #include "AArch64BaseInfo.h"
36 #include "AArch64AddressingModes.h"
37 
38 
39 // Forward declare these because the autogenerated code will reference them.
40 // Definitions are further down.
41 static DecodeStatus DecodeFPR128RegisterClass(MCInst *Inst,
42  unsigned RegNo, uint64_t Address,
43  const void *Decoder);
44 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst *Inst,
45  unsigned RegNo,
46  uint64_t Address,
47  const void *Decoder);
48 static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo,
49  uint64_t Address,
50  const void *Decoder);
51 static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo,
52  uint64_t Address,
53  const void *Decoder);
54 static DecodeStatus DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo,
55  uint64_t Address,
56  const void *Decoder);
57 static DecodeStatus DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo,
58  uint64_t Address,
59  const void *Decoder);
60 static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo,
61  uint64_t Address,
62  const void *Decoder);
63 static DecodeStatus DecodeGPR64spRegisterClass(MCInst *Inst,
64  unsigned RegNo, uint64_t Address,
65  const void *Decoder);
66 static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo,
67  uint64_t Address,
68  const void *Decoder);
69 static DecodeStatus DecodeGPR32spRegisterClass(MCInst *Inst,
70  unsigned RegNo, uint64_t Address,
71  const void *Decoder);
72 static DecodeStatus DecodeQQRegisterClass(MCInst *Inst, unsigned RegNo,
73  uint64_t Address,
74  const void *Decoder);
75 static DecodeStatus DecodeQQQRegisterClass(MCInst *Inst, unsigned RegNo,
76  uint64_t Address,
77  const void *Decoder);
78 static DecodeStatus DecodeQQQQRegisterClass(MCInst *Inst, unsigned RegNo,
79  uint64_t Address,
80  const void *Decoder);
81 static DecodeStatus DecodeDDRegisterClass(MCInst *Inst, unsigned RegNo,
82  uint64_t Address,
83  const void *Decoder);
84 static DecodeStatus DecodeDDDRegisterClass(MCInst *Inst, unsigned RegNo,
85  uint64_t Address,
86  const void *Decoder);
87 static DecodeStatus DecodeDDDDRegisterClass(MCInst *Inst, unsigned RegNo,
88  uint64_t Address,
89  const void *Decoder);
90 
91 static DecodeStatus DecodeFixedPointScaleImm32(MCInst *Inst, unsigned Imm,
92  uint64_t Address,
93  const void *Decoder);
94 static DecodeStatus DecodeFixedPointScaleImm64(MCInst *Inst, unsigned Imm,
95  uint64_t Address,
96  const void *Decoder);
97 static DecodeStatus DecodePCRelLabel19(MCInst *Inst, unsigned Imm,
98  uint64_t Address, const void *Decoder);
99 static DecodeStatus DecodeMemExtend(MCInst *Inst, unsigned Imm,
100  uint64_t Address, const void *Decoder);
101 static DecodeStatus DecodeMRSSystemRegister(MCInst *Inst, unsigned Imm,
102  uint64_t Address, const void *Decoder);
103 static DecodeStatus DecodeMSRSystemRegister(MCInst *Inst, unsigned Imm,
104  uint64_t Address, const void *Decoder);
105 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst *Inst,
106  uint32_t insn,
107  uint64_t Address,
108  const void *Decoder);
109 static DecodeStatus DecodeMoveImmInstruction(MCInst *Inst, uint32_t insn,
110  uint64_t Address,
111  const void *Decoder);
112 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst *Inst,
113  uint32_t insn,
114  uint64_t Address,
115  const void *Decoder);
116 static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst,
117  uint32_t insn, uint64_t Address,
118  const void *Decoder);
119 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst *Inst,
120  uint32_t insn,
121  uint64_t Address,
122  const void *Decoder);
123 static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn,
124  uint64_t Address,
125  const void *Decoder);
126 static DecodeStatus DecodeAddSubERegInstruction(MCInst *Inst,
127  uint32_t insn, uint64_t Address,
128  const void *Decoder);
129 static DecodeStatus DecodeLogicalImmInstruction(MCInst *Inst,
130  uint32_t insn, uint64_t Address,
131  const void *Decoder);
132 static DecodeStatus DecodeModImmInstruction(MCInst *Inst, uint32_t insn,
133  uint64_t Address,
134  const void *Decoder);
135 static DecodeStatus DecodeModImmTiedInstruction(MCInst *Inst,
136  uint32_t insn, uint64_t Address,
137  const void *Decoder);
138 static DecodeStatus DecodeAdrInstruction(MCInst *Inst, uint32_t insn,
139  uint64_t Address, const void *Decoder);
140 static DecodeStatus DecodeBaseAddSubImm(MCInst *Inst, uint32_t insn,
141  uint64_t Address, const void *Decoder);
142 static DecodeStatus DecodeUnconditionalBranch(MCInst *Inst, uint32_t insn,
143  uint64_t Address,
144  const void *Decoder);
145 static DecodeStatus DecodeSystemPStateInstruction(MCInst *Inst,
146  uint32_t insn,
147  uint64_t Address,
148  const void *Decoder);
149 static DecodeStatus DecodeTestAndBranch(MCInst *Inst, uint32_t insn,
150  uint64_t Address, const void *Decoder);
151 
152 static DecodeStatus DecodeFMOVLaneInstruction(MCInst *Inst, unsigned Insn,
153  uint64_t Address,
154  const void *Decoder);
155 static DecodeStatus DecodeVecShiftR64Imm(MCInst *Inst, unsigned Imm,
156  uint64_t Addr, const void *Decoder);
157 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst *Inst, unsigned Imm,
158  uint64_t Addr,
159  const void *Decoder);
160 static DecodeStatus DecodeVecShiftR32Imm(MCInst *Inst, unsigned Imm,
161  uint64_t Addr, const void *Decoder);
162 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst *Inst, unsigned Imm,
163  uint64_t Addr,
164  const void *Decoder);
165 static DecodeStatus DecodeVecShiftR16Imm(MCInst *Inst, unsigned Imm,
166  uint64_t Addr, const void *Decoder);
167 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst *Inst, unsigned Imm,
168  uint64_t Addr,
169  const void *Decoder);
170 static DecodeStatus DecodeVecShiftR8Imm(MCInst *Inst, unsigned Imm,
171  uint64_t Addr, const void *Decoder);
172 static DecodeStatus DecodeVecShiftL64Imm(MCInst *Inst, unsigned Imm,
173  uint64_t Addr, const void *Decoder);
174 static DecodeStatus DecodeVecShiftL32Imm(MCInst *Inst, unsigned Imm,
175  uint64_t Addr, const void *Decoder);
176 static DecodeStatus DecodeVecShiftL16Imm(MCInst *Inst, unsigned Imm,
177  uint64_t Addr, const void *Decoder);
178 static DecodeStatus DecodeVecShiftL8Imm(MCInst *Inst, unsigned Imm,
179  uint64_t Addr, const void *Decoder);
180 
181 static bool Check(DecodeStatus *Out, DecodeStatus In)
182 {
183  switch (In) {
184  default: // never reach
185  return true;
186  case MCDisassembler_Success:
187  // Out stays the same.
188  return true;
189  case MCDisassembler_SoftFail:
190  *Out = In;
191  return true;
192  case MCDisassembler_Fail:
193  *Out = In;
194  return false;
195  }
196  // llvm_unreachable("Invalid DecodeStatus!");
197 }
198 
199 // Hacky: enable all features for disassembler
200 static uint64_t getFeatureBits(int feature)
201 {
202  // enable all features
203  return (uint64_t)-1;
204 }
205 
206 #define GET_SUBTARGETINFO_ENUM
207 #include "AArch64GenSubtargetInfo.inc"
208 
209 #include "AArch64GenDisassemblerTables.inc"
210 
211 #define GET_INSTRINFO_ENUM
212 #include "AArch64GenInstrInfo.inc"
213 
214 #define GET_REGINFO_ENUM
215 #define GET_REGINFO_MC_DESC
216 #include "AArch64GenRegisterInfo.inc"
217 
218 #define Success MCDisassembler_Success
219 #define Fail MCDisassembler_Fail
220 #define SoftFail MCDisassembler_SoftFail
221 
222 static DecodeStatus _getInstruction(cs_struct *ud, MCInst *MI,
223  const uint8_t *code, size_t code_len,
224  uint16_t *Size,
225  uint64_t Address, MCRegisterInfo *MRI)
226 {
227  uint32_t insn;
228  DecodeStatus result;
229  size_t i;
230 
231  if (code_len < 4) {
232  // not enough data
233  *Size = 0;
234  return MCDisassembler_Fail;
235  }
236 
237  if (MI->flat_insn->detail) {
238  memset(MI->flat_insn->detail, 0, offsetof(cs_detail, arm64)+sizeof(cs_arm64));
239  for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm64.operands); i++)
240  MI->flat_insn->detail->arm64.operands[i].vector_index = -1;
241  }
242 
243  if (MODE_IS_BIG_ENDIAN(ud->mode))
244  insn = (code[3] << 0) | (code[2] << 8) |
245  (code[1] << 16) | ((uint32_t) code[0] << 24);
246  else
247  insn = ((uint32_t) code[3] << 24) | (code[2] << 16) |
248  (code[1] << 8) | (code[0] << 0);
249 
250  // Calling the auto-generated decoder function.
251  result = decodeInstruction(DecoderTable32, MI, insn, Address, MRI, 0);
252  if (result != MCDisassembler_Fail) {
253  *Size = 4;
254  return result;
255  }
256 
257  MCInst_clear(MI);
258  *Size = 0;
259  return MCDisassembler_Fail;
260 }
261 
262 bool AArch64_getInstruction(csh ud, const uint8_t *code, size_t code_len,
263  MCInst *instr, uint16_t *size, uint64_t address, void *info)
264 {
265  DecodeStatus status = _getInstruction((cs_struct *)ud, instr,
266  code, code_len,
267  size,
268  address, (MCRegisterInfo *)info);
269 
270  return status == MCDisassembler_Success;
271 }
272 
273 static const unsigned FPR128DecoderTable[] = {
274  AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4,
275  AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9,
276  AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14,
277  AArch64_Q15, AArch64_Q16, AArch64_Q17, AArch64_Q18, AArch64_Q19,
278  AArch64_Q20, AArch64_Q21, AArch64_Q22, AArch64_Q23, AArch64_Q24,
279  AArch64_Q25, AArch64_Q26, AArch64_Q27, AArch64_Q28, AArch64_Q29,
280  AArch64_Q30, AArch64_Q31
281 };
282 
283 static DecodeStatus DecodeFPR128RegisterClass(MCInst *Inst, unsigned RegNo,
284  uint64_t Addr,
285  const void *Decoder)
286 {
287  unsigned Register;
288  if (RegNo > 31)
289  return Fail;
290 
291  Register = FPR128DecoderTable[RegNo];
292  MCOperand_CreateReg0(Inst, Register);
293  return Success;
294 }
295 
296 static DecodeStatus DecodeFPR128_loRegisterClass(MCInst *Inst, unsigned RegNo,
297  uint64_t Addr,
298  const void *Decoder)
299 {
300  if (RegNo > 15)
301  return Fail;
302 
303  return DecodeFPR128RegisterClass(Inst, RegNo, Addr, Decoder);
304 }
305 
306 static const unsigned FPR64DecoderTable[] = {
307  AArch64_D0, AArch64_D1, AArch64_D2, AArch64_D3, AArch64_D4,
308  AArch64_D5, AArch64_D6, AArch64_D7, AArch64_D8, AArch64_D9,
309  AArch64_D10, AArch64_D11, AArch64_D12, AArch64_D13, AArch64_D14,
310  AArch64_D15, AArch64_D16, AArch64_D17, AArch64_D18, AArch64_D19,
311  AArch64_D20, AArch64_D21, AArch64_D22, AArch64_D23, AArch64_D24,
312  AArch64_D25, AArch64_D26, AArch64_D27, AArch64_D28, AArch64_D29,
313  AArch64_D30, AArch64_D31
314 };
315 
316 static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo,
317  uint64_t Addr,
318  const void *Decoder)
319 {
320  unsigned Register;
321 
322  if (RegNo > 31)
323  return Fail;
324 
325  Register = FPR64DecoderTable[RegNo];
326  MCOperand_CreateReg0(Inst, Register);
327  return Success;
328 }
329 
330 static const unsigned FPR32DecoderTable[] = {
331  AArch64_S0, AArch64_S1, AArch64_S2, AArch64_S3, AArch64_S4,
332  AArch64_S5, AArch64_S6, AArch64_S7, AArch64_S8, AArch64_S9,
333  AArch64_S10, AArch64_S11, AArch64_S12, AArch64_S13, AArch64_S14,
334  AArch64_S15, AArch64_S16, AArch64_S17, AArch64_S18, AArch64_S19,
335  AArch64_S20, AArch64_S21, AArch64_S22, AArch64_S23, AArch64_S24,
336  AArch64_S25, AArch64_S26, AArch64_S27, AArch64_S28, AArch64_S29,
337  AArch64_S30, AArch64_S31
338 };
339 
340 static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo,
341  uint64_t Addr,
342  const void *Decoder)
343 {
344  unsigned Register;
345 
346  if (RegNo > 31)
347  return Fail;
348 
349  Register = FPR32DecoderTable[RegNo];
350  MCOperand_CreateReg0(Inst, Register);
351  return Success;
352 }
353 
354 static const unsigned FPR16DecoderTable[] = {
355  AArch64_H0, AArch64_H1, AArch64_H2, AArch64_H3, AArch64_H4,
356  AArch64_H5, AArch64_H6, AArch64_H7, AArch64_H8, AArch64_H9,
357  AArch64_H10, AArch64_H11, AArch64_H12, AArch64_H13, AArch64_H14,
358  AArch64_H15, AArch64_H16, AArch64_H17, AArch64_H18, AArch64_H19,
359  AArch64_H20, AArch64_H21, AArch64_H22, AArch64_H23, AArch64_H24,
360  AArch64_H25, AArch64_H26, AArch64_H27, AArch64_H28, AArch64_H29,
361  AArch64_H30, AArch64_H31
362 };
363 
364 static DecodeStatus DecodeFPR16RegisterClass(MCInst *Inst, unsigned RegNo,
365  uint64_t Addr,
366  const void *Decoder)
367 {
368  unsigned Register;
369 
370  if (RegNo > 31)
371  return Fail;
372 
373  Register = FPR16DecoderTable[RegNo];
374  MCOperand_CreateReg0(Inst, Register);
375  return Success;
376 }
377 
378 static const unsigned FPR8DecoderTable[] = {
379  AArch64_B0, AArch64_B1, AArch64_B2, AArch64_B3, AArch64_B4,
380  AArch64_B5, AArch64_B6, AArch64_B7, AArch64_B8, AArch64_B9,
381  AArch64_B10, AArch64_B11, AArch64_B12, AArch64_B13, AArch64_B14,
382  AArch64_B15, AArch64_B16, AArch64_B17, AArch64_B18, AArch64_B19,
383  AArch64_B20, AArch64_B21, AArch64_B22, AArch64_B23, AArch64_B24,
384  AArch64_B25, AArch64_B26, AArch64_B27, AArch64_B28, AArch64_B29,
385  AArch64_B30, AArch64_B31
386 };
387 
388 static DecodeStatus DecodeFPR8RegisterClass(MCInst *Inst, unsigned RegNo,
389  uint64_t Addr,
390  const void *Decoder)
391 {
392  unsigned Register;
393 
394  if (RegNo > 31)
395  return Fail;
396 
397  Register = FPR8DecoderTable[RegNo];
398  MCOperand_CreateReg0(Inst, Register);
399  return Success;
400 }
401 
402 static const unsigned GPR64DecoderTable[] = {
403  AArch64_X0, AArch64_X1, AArch64_X2, AArch64_X3, AArch64_X4,
404  AArch64_X5, AArch64_X6, AArch64_X7, AArch64_X8, AArch64_X9,
405  AArch64_X10, AArch64_X11, AArch64_X12, AArch64_X13, AArch64_X14,
406  AArch64_X15, AArch64_X16, AArch64_X17, AArch64_X18, AArch64_X19,
407  AArch64_X20, AArch64_X21, AArch64_X22, AArch64_X23, AArch64_X24,
408  AArch64_X25, AArch64_X26, AArch64_X27, AArch64_X28, AArch64_FP,
409  AArch64_LR, AArch64_XZR
410 };
411 
412 static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo,
413  uint64_t Addr,
414  const void *Decoder)
415 {
416  unsigned Register;
417 
418  if (RegNo > 31)
419  return Fail;
420 
421  Register = GPR64DecoderTable[RegNo];
422  MCOperand_CreateReg0(Inst, Register);
423  return Success;
424 }
425 
426 static DecodeStatus DecodeGPR64spRegisterClass(MCInst *Inst, unsigned RegNo,
427  uint64_t Addr,
428  const void *Decoder)
429 {
430  unsigned Register;
431 
432  if (RegNo > 31)
433  return Fail;
434 
435  Register = GPR64DecoderTable[RegNo];
436  if (Register == AArch64_XZR)
437  Register = AArch64_SP;
438 
439  MCOperand_CreateReg0(Inst, Register);
440 
441  return Success;
442 }
443 
444 static const unsigned GPR32DecoderTable[] = {
445  AArch64_W0, AArch64_W1, AArch64_W2, AArch64_W3, AArch64_W4,
446  AArch64_W5, AArch64_W6, AArch64_W7, AArch64_W8, AArch64_W9,
447  AArch64_W10, AArch64_W11, AArch64_W12, AArch64_W13, AArch64_W14,
448  AArch64_W15, AArch64_W16, AArch64_W17, AArch64_W18, AArch64_W19,
449  AArch64_W20, AArch64_W21, AArch64_W22, AArch64_W23, AArch64_W24,
450  AArch64_W25, AArch64_W26, AArch64_W27, AArch64_W28, AArch64_W29,
451  AArch64_W30, AArch64_WZR
452 };
453 
454 static DecodeStatus DecodeGPR32RegisterClass(MCInst *Inst, unsigned RegNo,
455  uint64_t Addr,
456  const void *Decoder)
457 {
458  unsigned Register;
459 
460  if (RegNo > 31)
461  return Fail;
462 
463  Register = GPR32DecoderTable[RegNo];
464  MCOperand_CreateReg0(Inst, Register);
465  return Success;
466 }
467 
468 static DecodeStatus DecodeGPR32spRegisterClass(MCInst *Inst, unsigned RegNo,
469  uint64_t Addr,
470  const void *Decoder)
471 {
472  unsigned Register;
473 
474  if (RegNo > 31)
475  return Fail;
476 
477  Register = GPR32DecoderTable[RegNo];
478  if (Register == AArch64_WZR)
479  Register = AArch64_WSP;
480 
481  MCOperand_CreateReg0(Inst, Register);
482  return Success;
483 }
484 
485 static const unsigned VectorDecoderTable[] = {
486  AArch64_Q0, AArch64_Q1, AArch64_Q2, AArch64_Q3, AArch64_Q4,
487  AArch64_Q5, AArch64_Q6, AArch64_Q7, AArch64_Q8, AArch64_Q9,
488  AArch64_Q10, AArch64_Q11, AArch64_Q12, AArch64_Q13, AArch64_Q14,
489  AArch64_Q15, AArch64_Q16, AArch64_Q17, AArch64_Q18, AArch64_Q19,
490  AArch64_Q20, AArch64_Q21, AArch64_Q22, AArch64_Q23, AArch64_Q24,
491  AArch64_Q25, AArch64_Q26, AArch64_Q27, AArch64_Q28, AArch64_Q29,
492  AArch64_Q30, AArch64_Q31
493 };
494 
495 static DecodeStatus DecodeVectorRegisterClass(MCInst *Inst, unsigned RegNo,
496  uint64_t Addr,
497  const void *Decoder)
498 {
499  unsigned Register;
500 
501  if (RegNo > 31)
502  return Fail;
503 
504  Register = VectorDecoderTable[RegNo];
505  MCOperand_CreateReg0(Inst, Register);
506  return Success;
507 }
508 
509 static const unsigned QQDecoderTable[] = {
510  AArch64_Q0_Q1, AArch64_Q1_Q2, AArch64_Q2_Q3, AArch64_Q3_Q4,
511  AArch64_Q4_Q5, AArch64_Q5_Q6, AArch64_Q6_Q7, AArch64_Q7_Q8,
512  AArch64_Q8_Q9, AArch64_Q9_Q10, AArch64_Q10_Q11, AArch64_Q11_Q12,
513  AArch64_Q12_Q13, AArch64_Q13_Q14, AArch64_Q14_Q15, AArch64_Q15_Q16,
514  AArch64_Q16_Q17, AArch64_Q17_Q18, AArch64_Q18_Q19, AArch64_Q19_Q20,
515  AArch64_Q20_Q21, AArch64_Q21_Q22, AArch64_Q22_Q23, AArch64_Q23_Q24,
516  AArch64_Q24_Q25, AArch64_Q25_Q26, AArch64_Q26_Q27, AArch64_Q27_Q28,
517  AArch64_Q28_Q29, AArch64_Q29_Q30, AArch64_Q30_Q31, AArch64_Q31_Q0
518 };
519 
520 static DecodeStatus DecodeQQRegisterClass(MCInst *Inst, unsigned RegNo,
521  uint64_t Addr, const void *Decoder)
522 {
523  unsigned Register;
524 
525  if (RegNo > 31)
526  return Fail;
527 
528  Register = QQDecoderTable[RegNo];
529  MCOperand_CreateReg0(Inst, Register);
530  return Success;
531 }
532 
533 static const unsigned QQQDecoderTable[] = {
534  AArch64_Q0_Q1_Q2, AArch64_Q1_Q2_Q3, AArch64_Q2_Q3_Q4,
535  AArch64_Q3_Q4_Q5, AArch64_Q4_Q5_Q6, AArch64_Q5_Q6_Q7,
536  AArch64_Q6_Q7_Q8, AArch64_Q7_Q8_Q9, AArch64_Q8_Q9_Q10,
537  AArch64_Q9_Q10_Q11, AArch64_Q10_Q11_Q12, AArch64_Q11_Q12_Q13,
538  AArch64_Q12_Q13_Q14, AArch64_Q13_Q14_Q15, AArch64_Q14_Q15_Q16,
539  AArch64_Q15_Q16_Q17, AArch64_Q16_Q17_Q18, AArch64_Q17_Q18_Q19,
540  AArch64_Q18_Q19_Q20, AArch64_Q19_Q20_Q21, AArch64_Q20_Q21_Q22,
541  AArch64_Q21_Q22_Q23, AArch64_Q22_Q23_Q24, AArch64_Q23_Q24_Q25,
542  AArch64_Q24_Q25_Q26, AArch64_Q25_Q26_Q27, AArch64_Q26_Q27_Q28,
543  AArch64_Q27_Q28_Q29, AArch64_Q28_Q29_Q30, AArch64_Q29_Q30_Q31,
544  AArch64_Q30_Q31_Q0, AArch64_Q31_Q0_Q1
545 };
546 
547 static DecodeStatus DecodeQQQRegisterClass(MCInst *Inst, unsigned RegNo,
548  uint64_t Addr, const void *Decoder)
549 {
550  unsigned Register;
551 
552  if (RegNo > 31)
553  return Fail;
554 
555  Register = QQQDecoderTable[RegNo];
556  MCOperand_CreateReg0(Inst, Register);
557  return Success;
558 }
559 
560 static const unsigned QQQQDecoderTable[] = {
561  AArch64_Q0_Q1_Q2_Q3, AArch64_Q1_Q2_Q3_Q4, AArch64_Q2_Q3_Q4_Q5,
562  AArch64_Q3_Q4_Q5_Q6, AArch64_Q4_Q5_Q6_Q7, AArch64_Q5_Q6_Q7_Q8,
563  AArch64_Q6_Q7_Q8_Q9, AArch64_Q7_Q8_Q9_Q10, AArch64_Q8_Q9_Q10_Q11,
564  AArch64_Q9_Q10_Q11_Q12, AArch64_Q10_Q11_Q12_Q13, AArch64_Q11_Q12_Q13_Q14,
565  AArch64_Q12_Q13_Q14_Q15, AArch64_Q13_Q14_Q15_Q16, AArch64_Q14_Q15_Q16_Q17,
566  AArch64_Q15_Q16_Q17_Q18, AArch64_Q16_Q17_Q18_Q19, AArch64_Q17_Q18_Q19_Q20,
567  AArch64_Q18_Q19_Q20_Q21, AArch64_Q19_Q20_Q21_Q22, AArch64_Q20_Q21_Q22_Q23,
568  AArch64_Q21_Q22_Q23_Q24, AArch64_Q22_Q23_Q24_Q25, AArch64_Q23_Q24_Q25_Q26,
569  AArch64_Q24_Q25_Q26_Q27, AArch64_Q25_Q26_Q27_Q28, AArch64_Q26_Q27_Q28_Q29,
570  AArch64_Q27_Q28_Q29_Q30, AArch64_Q28_Q29_Q30_Q31, AArch64_Q29_Q30_Q31_Q0,
571  AArch64_Q30_Q31_Q0_Q1, AArch64_Q31_Q0_Q1_Q2
572 };
573 
574 static DecodeStatus DecodeQQQQRegisterClass(MCInst *Inst, unsigned RegNo,
575  uint64_t Addr,
576  const void *Decoder)
577 {
578  unsigned Register;
579  if (RegNo > 31)
580  return Fail;
581 
582  Register = QQQQDecoderTable[RegNo];
583  MCOperand_CreateReg0(Inst, Register);
584  return Success;
585 }
586 
587 static const unsigned DDDecoderTable[] = {
588  AArch64_D0_D1, AArch64_D1_D2, AArch64_D2_D3, AArch64_D3_D4,
589  AArch64_D4_D5, AArch64_D5_D6, AArch64_D6_D7, AArch64_D7_D8,
590  AArch64_D8_D9, AArch64_D9_D10, AArch64_D10_D11, AArch64_D11_D12,
591  AArch64_D12_D13, AArch64_D13_D14, AArch64_D14_D15, AArch64_D15_D16,
592  AArch64_D16_D17, AArch64_D17_D18, AArch64_D18_D19, AArch64_D19_D20,
593  AArch64_D20_D21, AArch64_D21_D22, AArch64_D22_D23, AArch64_D23_D24,
594  AArch64_D24_D25, AArch64_D25_D26, AArch64_D26_D27, AArch64_D27_D28,
595  AArch64_D28_D29, AArch64_D29_D30, AArch64_D30_D31, AArch64_D31_D0
596 };
597 
598 static DecodeStatus DecodeDDRegisterClass(MCInst *Inst, unsigned RegNo,
599  uint64_t Addr, const void *Decoder)
600 {
601  unsigned Register;
602 
603  if (RegNo > 31)
604  return Fail;
605 
606  Register = DDDecoderTable[RegNo];
607  MCOperand_CreateReg0(Inst, Register);
608  return Success;
609 }
610 
611 static const unsigned DDDDecoderTable[] = {
612  AArch64_D0_D1_D2, AArch64_D1_D2_D3, AArch64_D2_D3_D4,
613  AArch64_D3_D4_D5, AArch64_D4_D5_D6, AArch64_D5_D6_D7,
614  AArch64_D6_D7_D8, AArch64_D7_D8_D9, AArch64_D8_D9_D10,
615  AArch64_D9_D10_D11, AArch64_D10_D11_D12, AArch64_D11_D12_D13,
616  AArch64_D12_D13_D14, AArch64_D13_D14_D15, AArch64_D14_D15_D16,
617  AArch64_D15_D16_D17, AArch64_D16_D17_D18, AArch64_D17_D18_D19,
618  AArch64_D18_D19_D20, AArch64_D19_D20_D21, AArch64_D20_D21_D22,
619  AArch64_D21_D22_D23, AArch64_D22_D23_D24, AArch64_D23_D24_D25,
620  AArch64_D24_D25_D26, AArch64_D25_D26_D27, AArch64_D26_D27_D28,
621  AArch64_D27_D28_D29, AArch64_D28_D29_D30, AArch64_D29_D30_D31,
622  AArch64_D30_D31_D0, AArch64_D31_D0_D1
623 };
624 
625 static DecodeStatus DecodeDDDRegisterClass(MCInst *Inst, unsigned RegNo,
626  uint64_t Addr, const void *Decoder)
627 {
628  unsigned Register;
629 
630  if (RegNo > 31)
631  return Fail;
632 
633  Register = DDDDecoderTable[RegNo];
634  MCOperand_CreateReg0(Inst, Register);
635  return Success;
636 }
637 
638 static const unsigned DDDDDecoderTable[] = {
639  AArch64_D0_D1_D2_D3, AArch64_D1_D2_D3_D4, AArch64_D2_D3_D4_D5,
640  AArch64_D3_D4_D5_D6, AArch64_D4_D5_D6_D7, AArch64_D5_D6_D7_D8,
641  AArch64_D6_D7_D8_D9, AArch64_D7_D8_D9_D10, AArch64_D8_D9_D10_D11,
642  AArch64_D9_D10_D11_D12, AArch64_D10_D11_D12_D13, AArch64_D11_D12_D13_D14,
643  AArch64_D12_D13_D14_D15, AArch64_D13_D14_D15_D16, AArch64_D14_D15_D16_D17,
644  AArch64_D15_D16_D17_D18, AArch64_D16_D17_D18_D19, AArch64_D17_D18_D19_D20,
645  AArch64_D18_D19_D20_D21, AArch64_D19_D20_D21_D22, AArch64_D20_D21_D22_D23,
646  AArch64_D21_D22_D23_D24, AArch64_D22_D23_D24_D25, AArch64_D23_D24_D25_D26,
647  AArch64_D24_D25_D26_D27, AArch64_D25_D26_D27_D28, AArch64_D26_D27_D28_D29,
648  AArch64_D27_D28_D29_D30, AArch64_D28_D29_D30_D31, AArch64_D29_D30_D31_D0,
649  AArch64_D30_D31_D0_D1, AArch64_D31_D0_D1_D2
650 };
651 
652 static DecodeStatus DecodeDDDDRegisterClass(MCInst *Inst, unsigned RegNo,
653  uint64_t Addr,
654  const void *Decoder)
655 {
656  unsigned Register;
657 
658  if (RegNo > 31)
659  return Fail;
660 
661  Register = DDDDDecoderTable[RegNo];
662  MCOperand_CreateReg0(Inst, Register);
663  return Success;
664 }
665 
666 static DecodeStatus DecodeFixedPointScaleImm32(MCInst *Inst, unsigned Imm,
667  uint64_t Addr,
668  const void *Decoder)
669 {
670  // scale{5} is asserted as 1 in tblgen.
671  Imm |= 0x20;
672  MCOperand_CreateImm0(Inst, 64 - Imm);
673  return Success;
674 }
675 
676 static DecodeStatus DecodeFixedPointScaleImm64(MCInst *Inst, unsigned Imm,
677  uint64_t Addr,
678  const void *Decoder)
679 {
680  MCOperand_CreateImm0(Inst, 64 - Imm);
681  return Success;
682 }
683 
684 static DecodeStatus DecodePCRelLabel19(MCInst *Inst, unsigned Imm,
685  uint64_t Addr, const void *Decoder)
686 {
687  int64_t ImmVal = Imm;
688 
689  // Sign-extend 19-bit immediate.
690  if (ImmVal & (1 << (19 - 1)))
691  ImmVal |= ~((1LL << 19) - 1);
692 
693  MCOperand_CreateImm0(Inst, ImmVal);
694  return Success;
695 }
696 
697 static DecodeStatus DecodeMemExtend(MCInst *Inst, unsigned Imm,
698  uint64_t Address, const void *Decoder)
699 {
700  MCOperand_CreateImm0(Inst, (Imm >> 1) & 1);
701  MCOperand_CreateImm0(Inst, Imm & 1);
702  return Success;
703 }
704 
705 static DecodeStatus DecodeMRSSystemRegister(MCInst *Inst, unsigned Imm,
706  uint64_t Address, const void *Decoder)
707 {
708  MCOperand_CreateImm0(Inst, Imm);
709 
710  // Every system register in the encoding space is valid with the syntax
711  // S<op0>_<op1>_<Cn>_<Cm>_<op2>, so decoding system registers always succeeds.
712  return Success;
713 }
714 
715 static DecodeStatus DecodeMSRSystemRegister(MCInst *Inst, unsigned Imm,
716  uint64_t Address,
717  const void *Decoder)
718 {
719  MCOperand_CreateImm0(Inst, Imm);
720 
721  return Success;
722 }
723 
724 static DecodeStatus DecodeFMOVLaneInstruction(MCInst *Inst, unsigned Insn,
725  uint64_t Address,
726  const void *Decoder)
727 {
728  // This decoder exists to add the dummy Lane operand to the MCInst, which must
729  // be 1 in assembly but has no other real manifestation.
730  unsigned Rd = fieldFromInstruction(Insn, 0, 5);
731  unsigned Rn = fieldFromInstruction(Insn, 5, 5);
732  unsigned IsToVec = fieldFromInstruction(Insn, 16, 1);
733 
734  if (IsToVec) {
735  DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
736  DecodeGPR64RegisterClass(Inst, Rn, Address, Decoder);
737  } else {
738  DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder);
739  DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
740  }
741 
742  // Add the lane
743  MCOperand_CreateImm0(Inst, 1);
744 
745  return Success;
746 }
747 
748 static DecodeStatus DecodeVecShiftRImm(MCInst *Inst, unsigned Imm,
749  unsigned Add)
750 {
751  MCOperand_CreateImm0(Inst, Add - Imm);
752  return Success;
753 }
754 
755 static DecodeStatus DecodeVecShiftLImm(MCInst *Inst, unsigned Imm,
756  unsigned Add)
757 {
758  MCOperand_CreateImm0(Inst, (Imm + Add) & (Add - 1));
759  return Success;
760 }
761 
762 static DecodeStatus DecodeVecShiftR64Imm(MCInst *Inst, unsigned Imm,
763  uint64_t Addr, const void *Decoder)
764 {
765  return DecodeVecShiftRImm(Inst, Imm, 64);
766 }
767 
768 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst *Inst, unsigned Imm,
769  uint64_t Addr,
770  const void *Decoder)
771 {
772  return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
773 }
774 
775 static DecodeStatus DecodeVecShiftR32Imm(MCInst *Inst, unsigned Imm,
776  uint64_t Addr, const void *Decoder)
777 {
778  return DecodeVecShiftRImm(Inst, Imm, 32);
779 }
780 
781 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst *Inst, unsigned Imm,
782  uint64_t Addr,
783  const void *Decoder)
784 {
785  return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
786 }
787 
788 static DecodeStatus DecodeVecShiftR16Imm(MCInst *Inst, unsigned Imm,
789  uint64_t Addr, const void *Decoder)
790 {
791  return DecodeVecShiftRImm(Inst, Imm, 16);
792 }
793 
794 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst *Inst, unsigned Imm,
795  uint64_t Addr,
796  const void *Decoder)
797 {
798  return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
799 }
800 
801 static DecodeStatus DecodeVecShiftR8Imm(MCInst *Inst, unsigned Imm,
802  uint64_t Addr, const void *Decoder)
803 {
804  return DecodeVecShiftRImm(Inst, Imm, 8);
805 }
806 
807 static DecodeStatus DecodeVecShiftL64Imm(MCInst *Inst, unsigned Imm,
808  uint64_t Addr, const void *Decoder)
809 {
810  return DecodeVecShiftLImm(Inst, Imm, 64);
811 }
812 
813 static DecodeStatus DecodeVecShiftL32Imm(MCInst *Inst, unsigned Imm,
814  uint64_t Addr, const void *Decoder)
815 {
816  return DecodeVecShiftLImm(Inst, Imm, 32);
817 }
818 
819 static DecodeStatus DecodeVecShiftL16Imm(MCInst *Inst, unsigned Imm,
820  uint64_t Addr, const void *Decoder)
821 {
822  return DecodeVecShiftLImm(Inst, Imm, 16);
823 }
824 
825 static DecodeStatus DecodeVecShiftL8Imm(MCInst *Inst, unsigned Imm,
826  uint64_t Addr, const void *Decoder)
827 {
828  return DecodeVecShiftLImm(Inst, Imm, 8);
829 }
830 
831 static DecodeStatus DecodeThreeAddrSRegInstruction(MCInst *Inst,
832  uint32_t insn, uint64_t Addr,
833  const void *Decoder)
834 {
835  unsigned Rd = fieldFromInstruction(insn, 0, 5);
836  unsigned Rn = fieldFromInstruction(insn, 5, 5);
837  unsigned Rm = fieldFromInstruction(insn, 16, 5);
838  unsigned shiftHi = fieldFromInstruction(insn, 22, 2);
839  unsigned shiftLo = fieldFromInstruction(insn, 10, 6);
840  unsigned shift = (shiftHi << 6) | shiftLo;
841 
842  switch (MCInst_getOpcode(Inst)) {
843  default:
844  return Fail;
845  case AArch64_ADDWrs:
846  case AArch64_ADDSWrs:
847  case AArch64_SUBWrs:
848  case AArch64_SUBSWrs:
849  // if shift == '11' then ReservedValue()
850  if (shiftHi == 0x3)
851  return Fail;
852  // Deliberate fallthrough
853  case AArch64_ANDWrs:
854  case AArch64_ANDSWrs:
855  case AArch64_BICWrs:
856  case AArch64_BICSWrs:
857  case AArch64_ORRWrs:
858  case AArch64_ORNWrs:
859  case AArch64_EORWrs:
860  case AArch64_EONWrs: {
861  // if sf == '0' and imm6<5> == '1' then ReservedValue()
862  if (shiftLo >> 5 == 1)
863  return Fail;
864  DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
865  DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
866  DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
867  break;
868  }
869  case AArch64_ADDXrs:
870  case AArch64_ADDSXrs:
871  case AArch64_SUBXrs:
872  case AArch64_SUBSXrs:
873  // if shift == '11' then ReservedValue()
874  if (shiftHi == 0x3)
875  return Fail;
876  // Deliberate fallthrough
877  case AArch64_ANDXrs:
878  case AArch64_ANDSXrs:
879  case AArch64_BICXrs:
880  case AArch64_BICSXrs:
881  case AArch64_ORRXrs:
882  case AArch64_ORNXrs:
883  case AArch64_EORXrs:
884  case AArch64_EONXrs:
885  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
886  DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
887  DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
888  break;
889  }
890 
891  MCOperand_CreateImm0(Inst, shift);
892  return Success;
893 }
894 
895 static DecodeStatus DecodeMoveImmInstruction(MCInst *Inst, uint32_t insn,
896  uint64_t Addr,
897  const void *Decoder)
898 {
899  unsigned Rd = fieldFromInstruction(insn, 0, 5);
900  unsigned imm = fieldFromInstruction(insn, 5, 16);
901  unsigned shift = fieldFromInstruction(insn, 21, 2);
902 
903  shift <<= 4;
904 
905  switch (MCInst_getOpcode(Inst)) {
906  default:
907  return Fail;
908  case AArch64_MOVZWi:
909  case AArch64_MOVNWi:
910  case AArch64_MOVKWi:
911  if (shift & (1U << 5))
912  return Fail;
913  DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
914  break;
915  case AArch64_MOVZXi:
916  case AArch64_MOVNXi:
917  case AArch64_MOVKXi:
918  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
919  break;
920  }
921 
922  if (MCInst_getOpcode(Inst) == AArch64_MOVKWi ||
923  MCInst_getOpcode(Inst) == AArch64_MOVKXi)
924  MCInst_addOperand2(Inst, MCInst_getOperand(Inst, 0));
925 
926  MCOperand_CreateImm0(Inst, imm);
927  MCOperand_CreateImm0(Inst, shift);
928  return Success;
929 }
930 
931 static DecodeStatus DecodeUnsignedLdStInstruction(MCInst *Inst,
932  uint32_t insn, uint64_t Addr,
933  const void *Decoder)
934 {
935  unsigned Rt = fieldFromInstruction(insn, 0, 5);
936  unsigned Rn = fieldFromInstruction(insn, 5, 5);
937  unsigned offset = fieldFromInstruction(insn, 10, 12);
938 
939  switch (MCInst_getOpcode(Inst)) {
940  default:
941  return Fail;
942  case AArch64_PRFMui:
943  // Rt is an immediate in prefetch.
944  MCOperand_CreateImm0(Inst, Rt);
945  break;
946  case AArch64_STRBBui:
947  case AArch64_LDRBBui:
948  case AArch64_LDRSBWui:
949  case AArch64_STRHHui:
950  case AArch64_LDRHHui:
951  case AArch64_LDRSHWui:
952  case AArch64_STRWui:
953  case AArch64_LDRWui:
954  DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
955  break;
956  case AArch64_LDRSBXui:
957  case AArch64_LDRSHXui:
958  case AArch64_LDRSWui:
959  case AArch64_STRXui:
960  case AArch64_LDRXui:
961  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
962  break;
963  case AArch64_LDRQui:
964  case AArch64_STRQui:
965  DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
966  break;
967  case AArch64_LDRDui:
968  case AArch64_STRDui:
969  DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
970  break;
971  case AArch64_LDRSui:
972  case AArch64_STRSui:
973  DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
974  break;
975  case AArch64_LDRHui:
976  case AArch64_STRHui:
977  DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
978  break;
979  case AArch64_LDRBui:
980  case AArch64_STRBui:
981  DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
982  break;
983  }
984 
985  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
986  //if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4))
987  MCOperand_CreateImm0(Inst, offset);
988 
989  return Success;
990 }
991 
992 static DecodeStatus DecodeSignedLdStInstruction(MCInst *Inst,
993  uint32_t insn, uint64_t Addr,
994  const void *Decoder)
995 {
996  bool IsLoad;
997  bool IsIndexed;
998  bool IsFP;
999  unsigned Rt = fieldFromInstruction(insn, 0, 5);
1000  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1001  int64_t offset = fieldFromInstruction(insn, 12, 9);
1002 
1003  // offset is a 9-bit signed immediate, so sign extend it to
1004  // fill the unsigned.
1005  if (offset & (1 << (9 - 1)))
1006  offset |= ~((1LL << 9) - 1);
1007 
1008  // First operand is always the writeback to the address register, if needed.
1009  switch (MCInst_getOpcode(Inst)) {
1010  default:
1011  break;
1012  case AArch64_LDRSBWpre:
1013  case AArch64_LDRSHWpre:
1014  case AArch64_STRBBpre:
1015  case AArch64_LDRBBpre:
1016  case AArch64_STRHHpre:
1017  case AArch64_LDRHHpre:
1018  case AArch64_STRWpre:
1019  case AArch64_LDRWpre:
1020  case AArch64_LDRSBWpost:
1021  case AArch64_LDRSHWpost:
1022  case AArch64_STRBBpost:
1023  case AArch64_LDRBBpost:
1024  case AArch64_STRHHpost:
1025  case AArch64_LDRHHpost:
1026  case AArch64_STRWpost:
1027  case AArch64_LDRWpost:
1028  case AArch64_LDRSBXpre:
1029  case AArch64_LDRSHXpre:
1030  case AArch64_STRXpre:
1031  case AArch64_LDRSWpre:
1032  case AArch64_LDRXpre:
1033  case AArch64_LDRSBXpost:
1034  case AArch64_LDRSHXpost:
1035  case AArch64_STRXpost:
1036  case AArch64_LDRSWpost:
1037  case AArch64_LDRXpost:
1038  case AArch64_LDRQpre:
1039  case AArch64_STRQpre:
1040  case AArch64_LDRQpost:
1041  case AArch64_STRQpost:
1042  case AArch64_LDRDpre:
1043  case AArch64_STRDpre:
1044  case AArch64_LDRDpost:
1045  case AArch64_STRDpost:
1046  case AArch64_LDRSpre:
1047  case AArch64_STRSpre:
1048  case AArch64_LDRSpost:
1049  case AArch64_STRSpost:
1050  case AArch64_LDRHpre:
1051  case AArch64_STRHpre:
1052  case AArch64_LDRHpost:
1053  case AArch64_STRHpost:
1054  case AArch64_LDRBpre:
1055  case AArch64_STRBpre:
1056  case AArch64_LDRBpost:
1057  case AArch64_STRBpost:
1058  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1059  break;
1060  }
1061 
1062  switch (MCInst_getOpcode(Inst)) {
1063  default:
1064  return Fail;
1065  case AArch64_PRFUMi:
1066  // Rt is an immediate in prefetch.
1067  MCOperand_CreateImm0(Inst, Rt);
1068  break;
1069  case AArch64_STURBBi:
1070  case AArch64_LDURBBi:
1071  case AArch64_LDURSBWi:
1072  case AArch64_STURHHi:
1073  case AArch64_LDURHHi:
1074  case AArch64_LDURSHWi:
1075  case AArch64_STURWi:
1076  case AArch64_LDURWi:
1077  case AArch64_LDTRSBWi:
1078  case AArch64_LDTRSHWi:
1079  case AArch64_STTRWi:
1080  case AArch64_LDTRWi:
1081  case AArch64_STTRHi:
1082  case AArch64_LDTRHi:
1083  case AArch64_LDTRBi:
1084  case AArch64_STTRBi:
1085  case AArch64_LDRSBWpre:
1086  case AArch64_LDRSHWpre:
1087  case AArch64_STRBBpre:
1088  case AArch64_LDRBBpre:
1089  case AArch64_STRHHpre:
1090  case AArch64_LDRHHpre:
1091  case AArch64_STRWpre:
1092  case AArch64_LDRWpre:
1093  case AArch64_LDRSBWpost:
1094  case AArch64_LDRSHWpost:
1095  case AArch64_STRBBpost:
1096  case AArch64_LDRBBpost:
1097  case AArch64_STRHHpost:
1098  case AArch64_LDRHHpost:
1099  case AArch64_STRWpost:
1100  case AArch64_LDRWpost:
1101  DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1102  break;
1103  case AArch64_LDURSBXi:
1104  case AArch64_LDURSHXi:
1105  case AArch64_LDURSWi:
1106  case AArch64_STURXi:
1107  case AArch64_LDURXi:
1108  case AArch64_LDTRSBXi:
1109  case AArch64_LDTRSHXi:
1110  case AArch64_LDTRSWi:
1111  case AArch64_STTRXi:
1112  case AArch64_LDTRXi:
1113  case AArch64_LDRSBXpre:
1114  case AArch64_LDRSHXpre:
1115  case AArch64_STRXpre:
1116  case AArch64_LDRSWpre:
1117  case AArch64_LDRXpre:
1118  case AArch64_LDRSBXpost:
1119  case AArch64_LDRSHXpost:
1120  case AArch64_STRXpost:
1121  case AArch64_LDRSWpost:
1122  case AArch64_LDRXpost:
1123  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1124  break;
1125  case AArch64_LDURQi:
1126  case AArch64_STURQi:
1127  case AArch64_LDRQpre:
1128  case AArch64_STRQpre:
1129  case AArch64_LDRQpost:
1130  case AArch64_STRQpost:
1131  DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1132  break;
1133  case AArch64_LDURDi:
1134  case AArch64_STURDi:
1135  case AArch64_LDRDpre:
1136  case AArch64_STRDpre:
1137  case AArch64_LDRDpost:
1138  case AArch64_STRDpost:
1139  DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1140  break;
1141  case AArch64_LDURSi:
1142  case AArch64_STURSi:
1143  case AArch64_LDRSpre:
1144  case AArch64_STRSpre:
1145  case AArch64_LDRSpost:
1146  case AArch64_STRSpost:
1147  DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1148  break;
1149  case AArch64_LDURHi:
1150  case AArch64_STURHi:
1151  case AArch64_LDRHpre:
1152  case AArch64_STRHpre:
1153  case AArch64_LDRHpost:
1154  case AArch64_STRHpost:
1155  DecodeFPR16RegisterClass(Inst, Rt, Addr, Decoder);
1156  break;
1157  case AArch64_LDURBi:
1158  case AArch64_STURBi:
1159  case AArch64_LDRBpre:
1160  case AArch64_STRBpre:
1161  case AArch64_LDRBpost:
1162  case AArch64_STRBpost:
1163  DecodeFPR8RegisterClass(Inst, Rt, Addr, Decoder);
1164  break;
1165  }
1166 
1167  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1168  MCOperand_CreateImm0(Inst, offset);
1169 
1170  IsLoad = fieldFromInstruction(insn, 22, 1) != 0;
1171  IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
1172  IsFP = fieldFromInstruction(insn, 26, 1) != 0;
1173 
1174  // Cannot write back to a transfer register (but xzr != sp).
1175  if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn)
1176  return SoftFail;
1177 
1178  return Success;
1179 }
1180 
1181 static DecodeStatus DecodeExclusiveLdStInstruction(MCInst *Inst,
1182  uint32_t insn, uint64_t Addr,
1183  const void *Decoder)
1184 {
1185  unsigned Rt = fieldFromInstruction(insn, 0, 5);
1186  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1187  unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1188  unsigned Rs = fieldFromInstruction(insn, 16, 5);
1189  unsigned Opcode = MCInst_getOpcode(Inst);
1190 
1191  switch (Opcode) {
1192  default:
1193  return Fail;
1194  case AArch64_STLXRW:
1195  case AArch64_STLXRB:
1196  case AArch64_STLXRH:
1197  case AArch64_STXRW:
1198  case AArch64_STXRB:
1199  case AArch64_STXRH:
1200  DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1201  // FALLTHROUGH
1202  case AArch64_LDARW:
1203  case AArch64_LDARB:
1204  case AArch64_LDARH:
1205  case AArch64_LDAXRW:
1206  case AArch64_LDAXRB:
1207  case AArch64_LDAXRH:
1208  case AArch64_LDXRW:
1209  case AArch64_LDXRB:
1210  case AArch64_LDXRH:
1211  case AArch64_STLRW:
1212  case AArch64_STLRB:
1213  case AArch64_STLRH:
1214  DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1215  break;
1216  case AArch64_STLXRX:
1217  case AArch64_STXRX:
1218  DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1219  // FALLTHROUGH
1220  case AArch64_LDARX:
1221  case AArch64_LDAXRX:
1222  case AArch64_LDXRX:
1223  case AArch64_STLRX:
1224  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1225  break;
1226  case AArch64_STLXPW:
1227  case AArch64_STXPW:
1228  DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1229  // FALLTHROUGH
1230  case AArch64_LDAXPW:
1231  case AArch64_LDXPW:
1232  DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1233  DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1234  break;
1235  case AArch64_STLXPX:
1236  case AArch64_STXPX:
1237  DecodeGPR32RegisterClass(Inst, Rs, Addr, Decoder);
1238  // FALLTHROUGH
1239  case AArch64_LDAXPX:
1240  case AArch64_LDXPX:
1241  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1242  DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1243  break;
1244  }
1245 
1246  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1247 
1248  // You shouldn't load to the same register twice in an instruction...
1249  if ((Opcode == AArch64_LDAXPW || Opcode == AArch64_LDXPW ||
1250  Opcode == AArch64_LDAXPX || Opcode == AArch64_LDXPX) &&
1251  Rt == Rt2)
1252  return SoftFail;
1253 
1254  return Success;
1255 }
1256 
1257 static DecodeStatus DecodePairLdStInstruction(MCInst *Inst, uint32_t insn,
1258  uint64_t Addr,
1259  const void *Decoder)
1260 {
1261  unsigned Rt = fieldFromInstruction(insn, 0, 5);
1262  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1263  unsigned Rt2 = fieldFromInstruction(insn, 10, 5);
1264  int32_t offset = fieldFromInstruction(insn, 15, 7);
1265  bool IsLoad = fieldFromInstruction(insn, 22, 1) != 0;
1266  unsigned Opcode = MCInst_getOpcode(Inst);
1267  bool NeedsDisjointWritebackTransfer = false;
1268 
1269  // offset is a 7-bit signed immediate, so sign extend it to
1270  // fill the unsigned.
1271  if (offset & (1 << (7 - 1)))
1272  offset |= ~((1LL << 7) - 1);
1273 
1274  // First operand is always writeback of base register.
1275  switch (Opcode) {
1276  default:
1277  break;
1278  case AArch64_LDPXpost:
1279  case AArch64_STPXpost:
1280  case AArch64_LDPSWpost:
1281  case AArch64_LDPXpre:
1282  case AArch64_STPXpre:
1283  case AArch64_LDPSWpre:
1284  case AArch64_LDPWpost:
1285  case AArch64_STPWpost:
1286  case AArch64_LDPWpre:
1287  case AArch64_STPWpre:
1288  case AArch64_LDPQpost:
1289  case AArch64_STPQpost:
1290  case AArch64_LDPQpre:
1291  case AArch64_STPQpre:
1292  case AArch64_LDPDpost:
1293  case AArch64_STPDpost:
1294  case AArch64_LDPDpre:
1295  case AArch64_STPDpre:
1296  case AArch64_LDPSpost:
1297  case AArch64_STPSpost:
1298  case AArch64_LDPSpre:
1299  case AArch64_STPSpre:
1300  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1301  break;
1302  }
1303 
1304  switch (Opcode) {
1305  default:
1306  return Fail;
1307  case AArch64_LDPXpost:
1308  case AArch64_STPXpost:
1309  case AArch64_LDPSWpost:
1310  case AArch64_LDPXpre:
1311  case AArch64_STPXpre:
1312  case AArch64_LDPSWpre:
1313  NeedsDisjointWritebackTransfer = true;
1314  // Fallthrough
1315  case AArch64_LDNPXi:
1316  case AArch64_STNPXi:
1317  case AArch64_LDPXi:
1318  case AArch64_STPXi:
1319  case AArch64_LDPSWi:
1320  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1321  DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1322  break;
1323  case AArch64_LDPWpost:
1324  case AArch64_STPWpost:
1325  case AArch64_LDPWpre:
1326  case AArch64_STPWpre:
1327  NeedsDisjointWritebackTransfer = true;
1328  // Fallthrough
1329  case AArch64_LDNPWi:
1330  case AArch64_STNPWi:
1331  case AArch64_LDPWi:
1332  case AArch64_STPWi:
1333  DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1334  DecodeGPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1335  break;
1336  case AArch64_LDNPQi:
1337  case AArch64_STNPQi:
1338  case AArch64_LDPQpost:
1339  case AArch64_STPQpost:
1340  case AArch64_LDPQi:
1341  case AArch64_STPQi:
1342  case AArch64_LDPQpre:
1343  case AArch64_STPQpre:
1344  DecodeFPR128RegisterClass(Inst, Rt, Addr, Decoder);
1345  DecodeFPR128RegisterClass(Inst, Rt2, Addr, Decoder);
1346  break;
1347  case AArch64_LDNPDi:
1348  case AArch64_STNPDi:
1349  case AArch64_LDPDpost:
1350  case AArch64_STPDpost:
1351  case AArch64_LDPDi:
1352  case AArch64_STPDi:
1353  case AArch64_LDPDpre:
1354  case AArch64_STPDpre:
1355  DecodeFPR64RegisterClass(Inst, Rt, Addr, Decoder);
1356  DecodeFPR64RegisterClass(Inst, Rt2, Addr, Decoder);
1357  break;
1358  case AArch64_LDNPSi:
1359  case AArch64_STNPSi:
1360  case AArch64_LDPSpost:
1361  case AArch64_STPSpost:
1362  case AArch64_LDPSi:
1363  case AArch64_STPSi:
1364  case AArch64_LDPSpre:
1365  case AArch64_STPSpre:
1366  DecodeFPR32RegisterClass(Inst, Rt, Addr, Decoder);
1367  DecodeFPR32RegisterClass(Inst, Rt2, Addr, Decoder);
1368  break;
1369  }
1370 
1371  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1372  MCOperand_CreateImm0(Inst, offset);
1373 
1374  // You shouldn't load to the same register twice in an instruction...
1375  if (IsLoad && Rt == Rt2)
1376  return SoftFail;
1377 
1378  // ... or do any operation that writes-back to a transfer register. But note
1379  // that "stp xzr, xzr, [sp], #4" is fine because xzr and sp are different.
1380  if (NeedsDisjointWritebackTransfer && Rn != 31 && (Rt == Rn || Rt2 == Rn))
1381  return SoftFail;
1382 
1383  return Success;
1384 }
1385 
1386 static DecodeStatus DecodeAddSubERegInstruction(MCInst *Inst,
1387  uint32_t insn, uint64_t Addr,
1388  const void *Decoder)
1389 {
1390  unsigned Rd, Rn, Rm;
1391  unsigned extend = fieldFromInstruction(insn, 10, 6);
1392  unsigned shift = extend & 0x7;
1393 
1394  if (shift > 4)
1395  return Fail;
1396 
1397  Rd = fieldFromInstruction(insn, 0, 5);
1398  Rn = fieldFromInstruction(insn, 5, 5);
1399  Rm = fieldFromInstruction(insn, 16, 5);
1400 
1401  switch (MCInst_getOpcode(Inst)) {
1402  default:
1403  return Fail;
1404  case AArch64_ADDWrx:
1405  case AArch64_SUBWrx:
1406  DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1407  DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1408  DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1409  break;
1410  case AArch64_ADDSWrx:
1411  case AArch64_SUBSWrx:
1412  DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1413  DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1414  DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1415  break;
1416  case AArch64_ADDXrx:
1417  case AArch64_SUBXrx:
1418  DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1419  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1420  DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1421  break;
1422  case AArch64_ADDSXrx:
1423  case AArch64_SUBSXrx:
1424  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1425  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1426  DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
1427  break;
1428  case AArch64_ADDXrx64:
1429  case AArch64_SUBXrx64:
1430  DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1431  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1432  DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1433  break;
1434  case AArch64_SUBSXrx64:
1435  case AArch64_ADDSXrx64:
1436  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1437  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1438  DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
1439  break;
1440  }
1441 
1442  MCOperand_CreateImm0(Inst, extend);
1443  return Success;
1444 }
1445 
1446 static DecodeStatus DecodeLogicalImmInstruction(MCInst *Inst,
1447  uint32_t insn, uint64_t Addr,
1448  const void *Decoder)
1449 {
1450  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1451  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1452  unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1453  unsigned imm;
1454 
1455  if (Datasize) {
1456  if (MCInst_getOpcode(Inst) == AArch64_ANDSXri)
1457  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1458  else
1459  DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1460  DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
1461  imm = fieldFromInstruction(insn, 10, 13);
1462  if (!AArch64_AM_isValidDecodeLogicalImmediate(imm, 64))
1463  return Fail;
1464  } else {
1465  if (MCInst_getOpcode(Inst) == AArch64_ANDSWri)
1466  DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1467  else
1468  DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1469  DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
1470  imm = fieldFromInstruction(insn, 10, 12);
1471  if (!AArch64_AM_isValidDecodeLogicalImmediate(imm, 32))
1472  return Fail;
1473  }
1474 
1475  MCOperand_CreateImm0(Inst, imm);
1476  return Success;
1477 }
1478 
1479 static DecodeStatus DecodeModImmInstruction(MCInst *Inst, uint32_t insn,
1480  uint64_t Addr,
1481  const void *Decoder)
1482 {
1483  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1484  unsigned cmode = fieldFromInstruction(insn, 12, 4);
1485  unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1486  imm |= fieldFromInstruction(insn, 5, 5);
1487 
1488  if (MCInst_getOpcode(Inst) == AArch64_MOVID)
1489  DecodeFPR64RegisterClass(Inst, Rd, Addr, Decoder);
1490  else
1491  DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1492 
1493  MCOperand_CreateImm0(Inst, imm);
1494 
1495  switch (MCInst_getOpcode(Inst)) {
1496  default:
1497  break;
1498  case AArch64_MOVIv4i16:
1499  case AArch64_MOVIv8i16:
1500  case AArch64_MVNIv4i16:
1501  case AArch64_MVNIv8i16:
1502  case AArch64_MOVIv2i32:
1503  case AArch64_MOVIv4i32:
1504  case AArch64_MVNIv2i32:
1505  case AArch64_MVNIv4i32:
1506  MCOperand_CreateImm0(Inst, (cmode & 6) << 2);
1507  break;
1508  case AArch64_MOVIv2s_msl:
1509  case AArch64_MOVIv4s_msl:
1510  case AArch64_MVNIv2s_msl:
1511  case AArch64_MVNIv4s_msl:
1512  MCOperand_CreateImm0(Inst, cmode & 1 ? 0x110 : 0x108);
1513  break;
1514  }
1515 
1516  return Success;
1517 }
1518 
1519 static DecodeStatus DecodeModImmTiedInstruction(MCInst *Inst,
1520  uint32_t insn, uint64_t Addr,
1521  const void *Decoder)
1522 {
1523  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1524  unsigned cmode = fieldFromInstruction(insn, 12, 4);
1525  unsigned imm = fieldFromInstruction(insn, 16, 3) << 5;
1526  imm |= fieldFromInstruction(insn, 5, 5);
1527 
1528  // Tied operands added twice.
1529  DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1530  DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
1531 
1532  MCOperand_CreateImm0(Inst, imm);
1533  MCOperand_CreateImm0(Inst, (cmode & 6) << 2);
1534 
1535  return Success;
1536 }
1537 
1538 static DecodeStatus DecodeAdrInstruction(MCInst *Inst, uint32_t insn,
1539  uint64_t Addr, const void *Decoder)
1540 {
1541  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1542  int64_t imm = fieldFromInstruction(insn, 5, 19) << 2;
1543  imm |= fieldFromInstruction(insn, 29, 2);
1544 
1545  // Sign-extend the 21-bit immediate.
1546  if (imm & (1 << (21 - 1)))
1547  imm |= ~((1LL << 21) - 1);
1548 
1549  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1550  //if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4))
1551  MCOperand_CreateImm0(Inst, imm);
1552 
1553  return Success;
1554 }
1555 
1556 static DecodeStatus DecodeBaseAddSubImm(MCInst *Inst, uint32_t insn,
1557  uint64_t Addr, const void *Decoder)
1558 {
1559  unsigned Rd = fieldFromInstruction(insn, 0, 5);
1560  unsigned Rn = fieldFromInstruction(insn, 5, 5);
1561  unsigned Imm = fieldFromInstruction(insn, 10, 14);
1562  unsigned S = fieldFromInstruction(insn, 29, 1);
1563  unsigned Datasize = fieldFromInstruction(insn, 31, 1);
1564 
1565  unsigned ShifterVal = (Imm >> 12) & 3;
1566  unsigned ImmVal = Imm & 0xFFF;
1567 
1568  if (ShifterVal != 0 && ShifterVal != 1)
1569  return Fail;
1570 
1571  if (Datasize) {
1572  if (Rd == 31 && !S)
1573  DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder);
1574  else
1575  DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
1576  DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1577  } else {
1578  if (Rd == 31 && !S)
1579  DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder);
1580  else
1581  DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
1582  DecodeGPR32spRegisterClass(Inst, Rn, Addr, Decoder);
1583  }
1584 
1585  //if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4))
1586  MCOperand_CreateImm0(Inst, ImmVal);
1587  MCOperand_CreateImm0(Inst, 12 * ShifterVal);
1588  return Success;
1589 }
1590 
1591 static DecodeStatus DecodeUnconditionalBranch(MCInst *Inst, uint32_t insn,
1592  uint64_t Addr,
1593  const void *Decoder)
1594 {
1595  int64_t imm = fieldFromInstruction(insn, 0, 26);
1596 
1597  // Sign-extend the 26-bit immediate.
1598  if (imm & (1 << (26 - 1)))
1599  imm |= ~((1LL << 26) - 1);
1600 
1601  // if (!Dis->tryAddingSymbolicOperand(Inst, imm << 2, Addr, true, 0, 4))
1602  MCOperand_CreateImm0(Inst, imm);
1603 
1604  return Success;
1605 }
1606 
1607 static DecodeStatus DecodeSystemPStateInstruction(MCInst *Inst,
1608  uint32_t insn, uint64_t Addr,
1609  const void *Decoder)
1610 {
1611  uint32_t op1 = fieldFromInstruction(insn, 16, 3);
1612  uint32_t op2 = fieldFromInstruction(insn, 5, 3);
1613  uint32_t crm = fieldFromInstruction(insn, 8, 4);
1614  bool ValidNamed;
1615  uint32_t pstate_field = (op1 << 3) | op2;
1616 
1617  MCOperand_CreateImm0(Inst, pstate_field);
1618  MCOperand_CreateImm0(Inst, crm);
1619 
1620  A64NamedImmMapper_toString(&A64PState_PStateMapper, pstate_field, &ValidNamed);
1621 
1622  return ValidNamed ? Success : Fail;
1623 }
1624 
1625 static DecodeStatus DecodeTestAndBranch(MCInst *Inst, uint32_t insn,
1626  uint64_t Addr, const void *Decoder)
1627 {
1628  uint32_t Rt = fieldFromInstruction(insn, 0, 5);
1629  uint32_t bit = fieldFromInstruction(insn, 31, 1) << 5;
1630  uint64_t dst = fieldFromInstruction(insn, 5, 14);
1631 
1632  bit |= fieldFromInstruction(insn, 19, 5);
1633 
1634  // Sign-extend 14-bit immediate.
1635  if (dst & (1 << (14 - 1)))
1636  dst |= ~((1LL << 14) - 1);
1637 
1638  if (fieldFromInstruction(insn, 31, 1) == 0)
1639  DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
1640  else
1641  DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1642 
1643  MCOperand_CreateImm0(Inst, bit);
1644  //if (!Dis->tryAddingSymbolicOperand(Inst, dst << 2, Addr, true, 0, 4))
1645  MCOperand_CreateImm0(Inst, dst);
1646 
1647  return Success;
1648 }
1649 
1650 void AArch64_init(MCRegisterInfo *MRI)
1651 {
1652  /*
1653  InitMCRegisterInfo(AArch64RegDesc, 420,
1654  RA, PC,
1655  AArch64MCRegisterClasses, 43,
1656  AArch64RegUnitRoots, 66, AArch64RegDiffLists,
1657  AArch64RegStrings,
1658  AArch64SubRegIdxLists, 53,
1659  AArch64SubRegIdxRanges,
1660  AArch64RegEncodingTable);
1661  */
1662 
1663  MCRegisterInfo_InitMCRegisterInfo(MRI, AArch64RegDesc, 420,
1664  0, 0,
1665  AArch64MCRegisterClasses, 43,
1666  0, 0, AArch64RegDiffLists,
1667  0,
1668  AArch64SubRegIdxLists, 53,
1669  0);
1670 }
1671 
1672 #endif
AArch64_AM_isValidDecodeLogicalImmediate
static bool AArch64_AM_isValidDecodeLogicalImmediate(uint64_t val, unsigned regSize)
Definition: AArch64AddressingModes.h:158
A64PState_PStateMapper
const A64NamedImmMapper A64PState_PStateMapper
A64NamedImmMapper_toString
const char * A64NamedImmMapper_toString(const A64NamedImmMapper *N, uint32_t Value, bool *Valid)
AArch64_getInstruction
bool AArch64_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info)
AArch64_init
void AArch64_init(MCRegisterInfo *MRI)
DecodeStatus
DecodeStatus
Definition: MCDisassembler.h:7
MCDisassembler_SoftFail
@ MCDisassembler_SoftFail
Definition: MCDisassembler.h:9
MCDisassembler_Success
@ MCDisassembler_Success
Definition: MCDisassembler.h:10
MCDisassembler_Fail
@ MCDisassembler_Fail
Definition: MCDisassembler.h:8
MCInst_getOpcode
unsigned MCInst_getOpcode(const MCInst *inst)
Definition: MCInst.c:68
MCInst_clear
void MCInst_clear(MCInst *inst)
Definition: MCInst.c:40
MCInst_getOperand
MCOperand * MCInst_getOperand(MCInst *inst, unsigned i)
Definition: MCInst.c:78
MCOperand_CreateReg0
void MCOperand_CreateReg0(MCInst *mcInst, unsigned Reg)
Definition: MCInst.c:158
MCInst_addOperand2
void MCInst_addOperand2(MCInst *inst, MCOperand *Op)
Definition: MCInst.c:89
MCOperand_CreateImm0
void MCOperand_CreateImm0(MCInst *mcInst, int64_t Val)
Definition: MCInst.c:177
MCRegisterInfo_InitMCRegisterInfo
void MCRegisterInfo_InitMCRegisterInfo(MCRegisterInfo *RI, const MCRegisterDesc *D, unsigned NR, unsigned RA, unsigned PC, const MCRegisterClass *C, unsigned NC, uint16_t(*RURoots)[2], unsigned NRU, const MCPhysReg *DL, const char *Strings, const uint16_t *SubIndices, unsigned NumIndices, const uint16_t *RET)
Definition: MCRegisterInfo.c:28
decodeInstruction
int decodeInstruction(struct InternalInstruction *insn, byteReader_t reader, const void *readerArg, uint64_t startLoc, DisassemblerMode mode)
imm
#define imm
Definition: analysis_h8300.c:43
i
lzma_index ** i
Definition: index.h:629
shift
static RZ_NULLABLE RzILOpBitVector * shift(RzILOpBitVector *val, RZ_NULLABLE RzILOpBool **carry_out, arm_shifter type, RZ_OWN RzILOpBitVector *dist)
Definition: arm_il32.c:190
extend
static RzILOpBitVector * extend(ut32 dst_bits, arm64_extender ext, RZ_OWN RzILOpBitVector *v, ut32 v_bits)
Definition: arm_il64.c:270
Register
enum register_t Register
info
RzBinInfo * info(RzBinFile *bf)
Definition: bin_ne.c:86
csh
size_t csh
Definition: capstone.h:71
bit
RzCryptoSelector bit
Definition: crypto.c:16
MODE_IS_BIG_ENDIAN
#define MODE_IS_BIG_ENDIAN(mode)
Definition: cs_priv.h:84
size
voidpf void uLong size
Definition: ioapi.h:138
offset
voidpf uLong offset
Definition: ioapi.h:144
offsetof
#define offsetof(type, member)
Definition: jemalloc_internal_decls.h:46
memset
return memset(p, 0, total)
status
static const char struct stat static buf struct stat static buf static vhangup int status
Definition: sflib.h:145
dst
char * dst
Definition: lz4.h:724
ARR_SIZE
#define ARR_SIZE(a)
Definition: ocaml.c:13
uint16_t
unsigned short uint16_t
Definition: sftypes.h:30
int64_t
long int64_t
Definition: sftypes.h:32
int32_t
int int32_t
Definition: sftypes.h:33
uint32_t
unsigned int uint32_t
Definition: sftypes.h:29
uint64_t
unsigned long uint64_t
Definition: sftypes.h:28
uint8_t
unsigned char uint8_t
Definition: sftypes.h:31
MCInst
Definition: MCInst.h:88
MCInst::flat_insn
cs_insn * flat_insn
Definition: MCInst.h:95
Opcode_t
Definition: armass64.c:77
code
Definition: inftree9.h:24
cs_arm64
Instruction structure.
Definition: arm64.h:658
cs_struct
Definition: cs_priv.h:54
cs_struct::mode
cs_mode mode
Definition: cs_priv.h:56
S
#define S
Definition: zip_err_str.c:9