Rizin
unix-like reverse engineering framework and cli tools
linux-x86.h
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1 // SPDX-FileCopyrightText: 2015 pancake <pancake@nopcode.org>
2 // SPDX-License-Identifier: LGPL-3.0-only
3 
4 // 32bit host debugging 32bit target
5 return strdup(
6  "=PC eip\n"
7  "=SP esp\n"
8  "=BP ebp\n"
9  "=A0 eax\n"
10  "=A1 ebx\n"
11  "=A2 ecx\n"
12  "=A3 edx\n"
13  "=SN oeax\n"
14  "gpr eax .32 24 0\n"
15  "gpr ax .16 24 0\n"
16  "gpr ah .8 25 0\n"
17  "gpr al .8 24 0\n"
18  "gpr ebx .32 0 0\n"
19  "gpr bx .16 0 0\n"
20  "gpr bh .8 1 0\n"
21  "gpr bl .8 0 0\n"
22  "gpr ecx .32 4 0\n"
23  "gpr cx .16 4 0\n"
24  "gpr ch .8 5 0\n"
25  "gpr cl .8 4 0\n"
26  "gpr edx .32 8 0\n"
27  "gpr dx .16 8 0\n"
28  "gpr dh .8 9 0\n"
29  "gpr dl .8 8 0\n"
30  "gpr esi .32 12 0\n"
31  "gpr si .16 12 0\n"
32  "gpr edi .32 16 0\n"
33  "gpr di .16 16 0\n"
34  "gpr esp .32 60 0\n"
35  "gpr sp .16 60 0\n"
36  "gpr ebp .32 20 0\n"
37  "gpr bp .16 20 0\n"
38  "gpr eip .32 48 0\n"
39  "gpr ip .16 48 0\n"
40  "seg@gpr xfs .32 36 0\n"
41  "seg@gpr xgs .32 40 0\n"
42  "seg@gpr xcs .32 52 0\n"
43  "seg@gpr cs .16 52 0\n"
44  "seg@gpr xss .32 52 0\n"
45  "gpr eflags .32 56 0 c1p.a.zstido.n.rv\n"
46  "gpr flags .16 56 0\n"
47  "gpr cf .1 .448 0 carry\n"
48  "gpr pf .1 .450 0 parity\n"
49  "gpr af .1 .452 0 adjust\n"
50  "gpr zf .1 .454 0 zero\n"
51  "gpr sf .1 .455 0 sign\n"
52  "gpr tf .1 .456 0 trap\n"
53  "gpr if .1 .457 0 interrupt\n"
54  "gpr df .1 .458 0 direction\n"
55  "gpr of .1 .459 0 overflow\n"
56  "gpr oeax .32 44 0\n"
57  "drx dr0 .32 0 0\n"
58  "drx dr1 .32 4 0\n"
59  "drx dr2 .32 8 0\n"
60  "drx dr3 .32 12 0\n"
61  //"drx dr4 .32 16 0\n"
62  //"drx dr5 .32 20 0\n"
63  "drx dr6 .32 24 0\n"
64  "drx dr7 .32 28 0\n"
65  /*struct user_fpxregs_struct
66 {
67  unsigned short int cwd;
68  unsigned short int swd;
69  unsigned short int twd;
70  unsigned short int fop;
71  long int fip;
72  long int fcs;
73  long int foo;
74  long int fos;
75  long int mxcsr;
76  long int reserved;
77  long int st_space[32]; // 8*16 bytes for each FP-reg = 128 bytes
78  long int xmm_space[32]; // 8*16 bytes for each XMM-reg = 128 bytes
79  long int padding[56];
80 };*/
81  "fpu cwd .16 0 0\n"
82  "fpu swd .16 2 0\n"
83  "fpu twd .16 4 0\n"
84  "fpu fop .16 6 0\n"
85  "fpu fip .32 8 0\n"
86  "fpu fcs .32 12 0\n"
87  "fpu foo .32 16 0\n"
88  "fpu fos .32 20 0\n"
89  "fpu mxcsr .32 24 0\n"
90 
91  "fpu st0 .64 32 0\n"
92  "fpu st1 .64 48 0\n"
93  "fpu st2 .64 64 0\n"
94  "fpu st3 .64 80 0\n"
95  "fpu st4 .64 96 0\n"
96  "fpu st5 .64 112 0\n"
97  "fpu st6 .64 128 0\n"
98  "fpu st7 .64 144 0\n"
99 
100  "fpu xmm0h .64 160 0\n"
101  "fpu xmm0l .64 168 0\n"
102 
103  "fpu xmm1h .64 176 0\n"
104  "fpu xmm1l .64 184 0\n"
105 
106  "fpu xmm2h .64 192 0\n"
107  "fpu xmm2l .64 200 0\n"
108 
109  "fpu xmm3h .64 208 0\n"
110  "fpu xmm3l .64 216 0\n"
111 
112  "fpu xmm4h .64 224 0\n"
113  "fpu xmm4l .64 232 0\n"
114 
115  "fpu xmm5h .64 240 0\n"
116  "fpu xmm5l .64 248 0\n"
117 
118  "fpu xmm6h .64 256 0\n"
119  "fpu xmm6l .64 264 0\n"
120 
121  "fpu xmm7h .64 272 0\n"
122  "fpu xmm7l .64 280 0\n"
123  "fpu x86 .64 288 0\n"
124 
125 );
strdup
return strdup("=PC eip\n" "=SP esp\n" "=BP ebp\n" "=A0 eax\n" "=A1 ebx\n" "=A2 ecx\n" "=A3 edx\n" "=SN oeax\n" "gpr eax .32 24 0\n" "gpr ax .16 24 0\n" "gpr ah .8 25 0\n" "gpr al .8 24 0\n" "gpr ebx .32 0 0\n" "gpr bx .16 0 0\n" "gpr bh .8 1 0\n" "gpr bl .8 0 0\n" "gpr ecx .32 4 0\n" "gpr cx .16 4 0\n" "gpr ch .8 5 0\n" "gpr cl .8 4 0\n" "gpr edx .32 8 0\n" "gpr dx .16 8 0\n" "gpr dh .8 9 0\n" "gpr dl .8 8 0\n" "gpr esi .32 12 0\n" "gpr si .16 12 0\n" "gpr edi .32 16 0\n" "gpr di .16 16 0\n" "gpr esp .32 60 0\n" "gpr sp .16 60 0\n" "gpr ebp .32 20 0\n" "gpr bp .16 20 0\n" "gpr eip .32 48 0\n" "gpr ip .16 48 0\n" "seg@gpr xfs .32 36 0\n" "seg@gpr xgs .32 40 0\n" "seg@gpr xcs .32 52 0\n" "seg@gpr cs .16 52 0\n" "seg@gpr xss .32 52 0\n" "gpr eflags .32 56 0 c1p.a.zstido.n.rv\n" "gpr flags .16 56 0\n" "gpr cf .1 .448 0 carry\n" "gpr pf .1 .450 0 parity\n" "gpr af .1 .452 0 adjust\n" "gpr zf .1 .454 0 zero\n" "gpr sf .1 .455 0 sign\n" "gpr tf .1 .456 0 trap\n" "gpr if .1 .457 0 interrupt\n" "gpr df .1 .458 0 direction\n" "gpr of .1 .459 0 overflow\n" "gpr oeax .32 44 0\n" "drx dr0 .32 0 0\n" "drx dr1 .32 4 0\n" "drx dr2 .32 8 0\n" "drx dr3 .32 12 0\n" "drx dr6 .32 24 0\n" "drx dr7 .32 28 0\n" "fpu cwd .16 0 0\n" "fpu swd .16 2 0\n" "fpu twd .16 4 0\n" "fpu fop .16 6 0\n" "fpu fip .32 8 0\n" "fpu fcs .32 12 0\n" "fpu foo .32 16 0\n" "fpu fos .32 20 0\n" "fpu mxcsr .32 24 0\n" "fpu st0 .64 32 0\n" "fpu st1 .64 48 0\n" "fpu st2 .64 64 0\n" "fpu st3 .64 80 0\n" "fpu st4 .64 96 0\n" "fpu st5 .64 112 0\n" "fpu st6 .64 128 0\n" "fpu st7 .64 144 0\n" "fpu xmm0h .64 160 0\n" "fpu xmm0l .64 168 0\n" "fpu xmm1h .64 176 0\n" "fpu xmm1l .64 184 0\n" "fpu xmm2h .64 192 0\n" "fpu xmm2l .64 200 0\n" "fpu xmm3h .64 208 0\n" "fpu xmm3l .64 216 0\n" "fpu xmm4h .64 224 0\n" "fpu xmm4l .64 232 0\n" "fpu xmm5h .64 240 0\n" "fpu xmm5l .64 248 0\n" "fpu xmm6h .64 256 0\n" "fpu xmm6l .64 264 0\n" "fpu xmm7h .64 272 0\n" "fpu xmm7l .64 280 0\n" "fpu x86 .64 288 0\n")