Rizin
unix-like reverse engineering framework and cli tools
linux-x64-32.h
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1 // SPDX-FileCopyrightText: 2015 pancake <pancake@nopcode.org>
2 // SPDX-License-Identifier: LGPL-3.0-only
3 
4 // 64bit host debugging 32bit binary
5 return strdup(
6  "=PC eip\n"
7  "=SP esp\n"
8  "=BP ebp\n"
9  "=A0 eax\n"
10  "=A1 ebx\n"
11  "=A2 ecx\n"
12  "=A3 edx\n"
13  "=ZF zf\n"
14  "=SF sf\n"
15  "=OF of\n"
16  "=CF cf\n"
17  "=SN oeax\n"
18  "gpr eax .32 80 0\n"
19  "gpr ax .16 80 0\n"
20  "gpr ah .8 81 0\n"
21  "gpr al .8 80 0\n"
22  "gpr ebx .32 40 0\n"
23  "gpr bx .16 40 0\n"
24  "gpr bh .8 41 0\n"
25  "gpr bl .8 40 0\n"
26  "gpr ecx .32 88 0\n"
27  "gpr cx .16 88 0\n"
28  "gpr ch .8 89 0\n"
29  "gpr cl .8 88 0\n"
30  "gpr edx .32 96 0\n"
31  "gpr dx .16 96 0\n"
32  "gpr dh .8 97 0\n"
33  "gpr dl .8 96 0\n"
34  "gpr esi .32 104 0\n"
35  "gpr si .16 104 0\n"
36  "gpr edi .32 112 0\n"
37  "gpr di .16 112 0\n"
38  "gpr esp .32 152 0\n"
39  "gpr sp .16 152 0\n"
40  "gpr ebp .32 32 0\n"
41  "gpr bp .16 32 0\n"
42  "gpr eip .32 128 0\n"
43  "gpr ip .16 128 0\n"
44  "seg@gpr xfs .32 200 0\n"
45  "seg@gpr xgs .32 208 0\n"
46  "seg@gpr xcs .32 136 0\n"
47  "seg@gpr cs .16 136 0\n"
48  "seg@gpr xss .32 160 0\n"
49  "gpr flags .16 144 0\n"
50  "gpr eflags .32 144 0 c1p.a.zstido.n.rv\n"
51  "gpr rflags .64 144 0 c1p.a.zstido.n.rv\n"
52  "gpr cf .1 .1152 0 carry\n"
53  "gpr pf .1 .1154 0 parity\n"
54  "gpr af .1 .1156 0 adjust\n"
55  "gpr zf .1 .1158 0 zero\n"
56  "gpr sf .1 .1159 0 sign\n"
57  "gpr tf .1 .1160 0 trap\n"
58  "gpr if .1 .1161 0 interrupt\n"
59  "gpr df .1 .1162 0 direction\n"
60  "gpr of .1 .1163 0 overflow\n"
61  "gpr oeax .32 120 0\n"
62 #if 0
63 "drx dr0 .64 0 0\n"
64 "drx dr1 .64 8 0\n"
65 "drx dr2 .64 16 0\n"
66 "drx dr3 .64 24 0\n"
67 // dr4 32
68 // dr5 40
69 "drx dr6 .64 48 0\n"
70 "drx dr7 .64 56 0\n"
71 #endif
72  "drx dr0 .32 0 0\n"
73  "drx dr1 .32 4 0\n"
74  "drx dr2 .32 8 0\n"
75  "drx dr3 .32 12 0\n"
76  //"drx dr4 .32 16 0\n"
77  //"drx dr5 .32 20 0\n"
78  "drx dr6 .32 24 0\n"
79  "drx dr7 .32 28 0\n"
80 
81  /*0030 struct user_fpregs_struct
82 0031 {
83 0032 __uint16_t cwd;
84 0033 __uint16_t swd;
85 0034 __uint16_t ftw;
86 0035 __uint16_t fop;
87 0036 __uint64_t rip;
88 0037 __uint64_t rdp;
89 0038 __uint32_t mxcsr;
90 0039 __uint32_t mxcr_mask;
91 0040 __uint32_t st_space[32]; // 8*16 bytes for each FP-reg = 128 bytes
92 0041 __uint32_t xmm_space[64]; // 16*16 bytes for each XMM-reg = 256 bytes
93 0042 __uint32_t padding[24];
94 0043 };
95 */
96 
97  "fpu cwd .16 0 0\n"
98  "fpu swd .16 2 0\n"
99  "fpu ftw .16 4 0\n"
100  "fpu fop .16 6 0\n"
101  "fpu frip .64 8 0\n"
102  "fpu frdp .64 16 0\n"
103  "fpu mxcsr .32 24 0\n"
104  "fpu mxcr_mask .32 28 0\n"
105 
106  "fpu st0 .64 32 0\n"
107  "fpu st1 .64 48 0\n"
108  "fpu st2 .64 64 0\n"
109  "fpu st3 .64 80 0\n"
110  "fpu st4 .64 96 0\n"
111  "fpu st5 .64 112 0\n"
112  "fpu st6 .64 128 0\n"
113  "fpu st7 .64 144 0\n"
114 
115  "fpu xmm0h .64 160 0\n"
116  "fpu xmm0l .64 168 0\n"
117 
118  "fpu xmm1h .64 176 0\n"
119  "fpu xmm1l .64 184 0\n"
120 
121  "fpu xmm2h .64 192 0\n"
122  "fpu xmm2l .64 200 0\n"
123 
124  "fpu xmm3h .64 208 0\n"
125  "fpu xmm3l .64 216 0\n"
126 
127  "fpu xmm4h .64 224 0\n"
128  "fpu xmm4l .64 232 0\n"
129 
130  "fpu xmm5h .64 240 0\n"
131  "fpu xmm5l .64 248 0\n"
132 
133  "fpu xmm6h .64 256 0\n"
134  "fpu xmm6l .64 264 0\n"
135 
136  "fpu xmm7h .64 272 0\n"
137  "fpu xmm7l .64 280 0\n"
138  "fpu x64-32 .64 288 0\n"
139 
140 );
strdup
return strdup("=PC eip\n" "=SP esp\n" "=BP ebp\n" "=A0 eax\n" "=A1 ebx\n" "=A2 ecx\n" "=A3 edx\n" "=ZF zf\n" "=SF sf\n" "=OF of\n" "=CF cf\n" "=SN oeax\n" "gpr eax .32 80 0\n" "gpr ax .16 80 0\n" "gpr ah .8 81 0\n" "gpr al .8 80 0\n" "gpr ebx .32 40 0\n" "gpr bx .16 40 0\n" "gpr bh .8 41 0\n" "gpr bl .8 40 0\n" "gpr ecx .32 88 0\n" "gpr cx .16 88 0\n" "gpr ch .8 89 0\n" "gpr cl .8 88 0\n" "gpr edx .32 96 0\n" "gpr dx .16 96 0\n" "gpr dh .8 97 0\n" "gpr dl .8 96 0\n" "gpr esi .32 104 0\n" "gpr si .16 104 0\n" "gpr edi .32 112 0\n" "gpr di .16 112 0\n" "gpr esp .32 152 0\n" "gpr sp .16 152 0\n" "gpr ebp .32 32 0\n" "gpr bp .16 32 0\n" "gpr eip .32 128 0\n" "gpr ip .16 128 0\n" "seg@gpr xfs .32 200 0\n" "seg@gpr xgs .32 208 0\n" "seg@gpr xcs .32 136 0\n" "seg@gpr cs .16 136 0\n" "seg@gpr xss .32 160 0\n" "gpr flags .16 144 0\n" "gpr eflags .32 144 0 c1p.a.zstido.n.rv\n" "gpr rflags .64 144 0 c1p.a.zstido.n.rv\n" "gpr cf .1 .1152 0 carry\n" "gpr pf .1 .1154 0 parity\n" "gpr af .1 .1156 0 adjust\n" "gpr zf .1 .1158 0 zero\n" "gpr sf .1 .1159 0 sign\n" "gpr tf .1 .1160 0 trap\n" "gpr if .1 .1161 0 interrupt\n" "gpr df .1 .1162 0 direction\n" "gpr of .1 .1163 0 overflow\n" "gpr oeax .32 120 0\n" "drx dr0 .32 0 0\n" "drx dr1 .32 4 0\n" "drx dr2 .32 8 0\n" "drx dr3 .32 12 0\n" "drx dr6 .32 24 0\n" "drx dr7 .32 28 0\n" "fpu cwd .16 0 0\n" "fpu swd .16 2 0\n" "fpu ftw .16 4 0\n" "fpu fop .16 6 0\n" "fpu frip .64 8 0\n" "fpu frdp .64 16 0\n" "fpu mxcsr .32 24 0\n" "fpu mxcr_mask .32 28 0\n" "fpu st0 .64 32 0\n" "fpu st1 .64 48 0\n" "fpu st2 .64 64 0\n" "fpu st3 .64 80 0\n" "fpu st4 .64 96 0\n" "fpu st5 .64 112 0\n" "fpu st6 .64 128 0\n" "fpu st7 .64 144 0\n" "fpu xmm0h .64 160 0\n" "fpu xmm0l .64 168 0\n" "fpu xmm1h .64 176 0\n" "fpu xmm1l .64 184 0\n" "fpu xmm2h .64 192 0\n" "fpu xmm2l .64 200 0\n" "fpu xmm3h .64 208 0\n" "fpu xmm3l .64 216 0\n" "fpu xmm4h .64 224 0\n" "fpu xmm4l .64 232 0\n" "fpu xmm5h .64 240 0\n" "fpu xmm5l .64 248 0\n" "fpu xmm6h .64 256 0\n" "fpu xmm6l .64 264 0\n" "fpu xmm7h .64 272 0\n" "fpu xmm7l .64 280 0\n" "fpu x64-32 .64 288 0\n")