Rizin
unix-like reverse engineering framework and cli tools
arm.c
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1 // SPDX-FileCopyrightText: 2010 pancake <pancake@nopcode.org>
2 // SPDX-License-Identifier: LGPL-3.0-only
3 
4 /*
5 
6 handling exceptions
7 
8  http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0311d/I30195.html
9 
10 //-----//
11 
12 Flags
13 
14  Conditional instructions:
15  EQ = Z
16  NE = z
17  CS HS = C
18  CC LO = c
19  MI = N // negative
20  PL = n // positive
21  VS = V // overflow
22  VC = v // no overflow
23 
24  // unsigned
25  HI = zC (!z && c)
26  LS = Z || c (z || !c)
27 
28  // signed
29  GE = NV || nv ((n&&v) || (!n&&!v))
30  GT = NzV || nzv ((n&&!z&&v) || (!n&&!z&&!v))
31  LT = Nv || nV ((n&&!v)|| (!n&&v))
32  LE = Z || Nv || nV z || (n&&!v) || (!n && v)
33 
34  // INTEL X86 additions
35  // - Parity flag (lsb A)
36  // - counter register value != 0 (cx/ecx)
37 
38  http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0153n/CHDJEBEC.html
39 
40  Fields:
41  =======
42  31 n - negative (msb bit set)
43  30 z - zero (== 0)
44  29 c - carry
45  28 v - signed overflow
46  27 q - underflow
47  ...
48  24 j - Jazzele mode
49  ...
50  19 ge3 - ??
51  18 ge2 - ??
52  17 ge1 - ??
53  16 ge0 - ??
54  ...
55  9 e - Endianness (big endian if set)
56  8 a - if set disables the impreceise aborts
57  7 i - IRQs disabled if set
58  6 f - FIQ interrupts disabled if set
59  5 t - Thumb mode if set
60  ...
61  4 m4 - ??
62  3 m3
63  2 m2
64  1 m1
65  0 m0
66 
67 int armflag_N = (Cpsr>>31)&1;
68 int armflag_Z = (Cpsr>>30)&1;
69 int armflag_C = (Cpsr>>29)&1;
70 int armflag_V = (Cpsr>>28)&1;
71 int armflag_Q = (Cpsr>>27)&1;
72 int armflag_J = (Cpsr>>24)&1;
73 int armflag_GE = (Cpsr>>16)&7;
74 int armflag_E = (Cpsr>>9)&1;
75 int armflag_A = (Cpsr>>8)&1;
76 int armflag_I = (Cpsr>>7)&1;
77 int armflag_F = (Cpsr>>6)&1;
78 int armflag_T = (Cpsr>>5)&1;
79 int armflag_M = (Cpsr>>0)&15;
80 
81  state: JT bits:
82  ARM 0 (t) 0 (j)
83  Thumb 1 (T) 0 (j)
84  Btecode 0 (t) 1 (J)
85  ThumbEE 1 (T) 1 (J)
86 
87 */
88 
89 BX LR = {
90  int tbit = reg[14] & 1;
91 reg[15] = reg[14] & ~1;
92 if (tbit)
93  reg[16] |= 1 << 5;
94 }
reg
#define reg(n)