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elf_specs.h
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// SPDX-FileCopyrightText: 2021 08A <08A@riseup.net>
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// SPDX-FileCopyrightText: 2009 Nibble <nibble.ds@gmail.com>
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// SPDX-FileCopyrightText: 2009 pancake <pancake@nopcode.org>
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// SPDX-License-Identifier: LGPL-3.0-only
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#undef Elf_
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#undef Elf_Vword
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#undef ELF_ST_BIND
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#undef ELF_ST_TYPE
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#undef ELF_ST_INFO
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#undef ELF_ST_VISIBILITY
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#undef ELF_R_SYM
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#undef ELF_R_TYPE
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#undef ELF_R_INFO
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#undef ELF_M_SYM
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#undef ELF_M_SIZE
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#undef ELF_M_INFO
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#ifdef RZ_BIN_ELF64
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#define Elf_(name) Elf64_##name
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#define ELF_ST_BIND ELF64_ST_BIND
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#define ELF_ST_TYPE ELF64_ST_TYPE
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#define ELF_ST_INFO ELF64_ST_INFO
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#define ELF_ST_VISIBILITY ELF64_ST_VISIBILITY
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#define ELF_R_SYM ELF64_R_SYM
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#define ELF_R_TYPE ELF64_R_TYPE
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#define ELF_R_INFO ELF64_R_INFO
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#define ELF_M_SYM ELF64_M_SYM
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#define ELF_M_SIZE ELF64_M_SIZE
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#define ELF_M_INFO ELF64_M_INFO
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#else
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#define Elf_(name) Elf32_##name
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#define ELF_ST_BIND ELF32_ST_BIND
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#define ELF_ST_TYPE ELF32_ST_TYPE
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#define ELF_ST_INFO ELF32_ST_INFO
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#define ELF_ST_VISIBILITY ELF32_ST_VISIBILITY
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#define ELF_R_SYM ELF32_R_SYM
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#define ELF_R_TYPE ELF32_R_TYPE
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#define ELF_R_INFO ELF32_R_INFO
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#define ELF_M_SYM ELF32_M_SYM
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#define ELF_M_SIZE ELF32_M_SIZE
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#define ELF_M_INFO ELF32_M_INFO
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#endif
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#define E_IDENT_OFFSET offsetof(Elf_(Ehdr), e_ident)
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#define E_TYPE_OFFSET offsetof(Elf_(Ehdr), e_type)
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#define E_MACHINE_OFFSET offsetof(Elf_(Ehdr), e_machine)
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#define E_VERSION_OFFSET offsetof(Elf_(Ehdr), e_version)
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#define E_ENTRYPOINT_OFFSET offsetof(Elf_(Ehdr), e_entry)
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#define E_PHOFF_OFFSET offsetof(Elf_(Ehdr), e_phoff)
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#define E_SHOFF_OFFSET offsetof(Elf_(Ehdr), e_shoff)
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#define E_FLAGS_OFFSET offsetof(Elf_(Ehdr), e_flags)
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#define E_EHSIZE_OFFSET offsetof(Elf_(Ehdr), e_ehsize)
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#define E_PHENTSIZE_OFFSET offsetof(Elf_(Ehdr), e_phentsize)
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#define E_PHNUM_OFFSET offsetof(Elf_(Ehdr), e_phnum)
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#define E_SHENTSIZE_OFFSET offsetof(Elf_(Ehdr), e_shentsize)
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#define E_SHNUM_OFFSET offsetof(Elf_(Ehdr), e_shnum)
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#define E_SHSTRNDX_OFFSET offsetof(Elf_(Ehdr), e_shstrndx)
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/* MingW doesn't define __BEGIN_DECLS / __END_DECLS. */
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#ifndef __BEGIN_DECLS
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#ifdef __cplusplus
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#define __BEGIN_DECLS extern "C"
{
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#else
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#define __BEGIN_DECLS
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#endif
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#endif
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#ifndef __END_DECLS
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#ifdef __cplusplus
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#define __END_DECLS }
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#else
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#define __END_DECLS
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#endif
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#endif
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#include "
glibc_elf.h
"
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#ifndef _INCLUDE_ELF_SPECS_H
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#define _INCLUDE_ELF_SPECS_H
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// not strictly ELF, but close enough:
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#define CGCMAG "\177CGC"
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#define SCGCMAG 4
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#define ELFOSABI_HURD 4
/* GNU/HURD */
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#define ELFOSABI_86OPEN 5
/* 86open */
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#define ELFOSABI_OPENVMS 13
/* OpenVMS */
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#define ELFOSABI_ARM_AEABI 64
/* ARM EABI */
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#define EM_PROPELLER 0x5072
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#define EM_LANAI 0x8123
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#define EM_VIDEOCORE4 200
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#define EM_PDP10 64
/* Digital Equipment Corp. PDP-10 */
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#define EM_PDP11 65
/* Digital Equipment Corp. PDP-11 */
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#define EM_VIDEOCORE 95
/* Alphamosaic VideoCore processor */
// XXX dupe for EM_NUM
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#define EM_TMM_GPP 96
/* Thompson Multimedia General Purpose Processor */
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#define EM_NS32K 97
/* National Semiconductor 32000 series */
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#define EM_TPC 98
/* Tenor Network TPC processor */
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#define EM_SNP1K 99
/* Trebia SNP 1000 processor */
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#define EM_ST200 100
/* STMicroelectronics (www.st.com) ST200 microcontroller */
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#define EM_IP2K 101
/* Ubicom IP2xxx microcontroller family */
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#define EM_MAX 102
/* MAX Processor */
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#define EM_CR 103
/* National Semiconductor CompactRISC microprocessor */
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#define EM_F2MC16 104
/* Fujitsu F2MC16 */
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#define EM_MSP430 105
/* Texas Instruments embedded microcontroller msp430 */
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#define EM_BLACKFIN 106
/* Analog Devices Blackfin (DSP) processor */
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#define EM_SE_C33 107
/* S1C33 Family of Seiko Epson processors */
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#define EM_SEP 108
/* Sharp embedded microprocessor */
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#define EM_ARCA 109
/* Arca RISC Microprocessor */
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#define EM_UNICORE 110
/* Microprocessor series from PKU-Unity Ltd. and MPRC of Peking University */
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#define EM_EXCESS 111
/* eXcess: 16/32/64-bit configurable embedded CPU */
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#define EM_DXP 112
/* Icera Semiconductor Inc. Deep Execution Processor */
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// http://www.sco.com/developers/gabi/latest/ch4.eheader.html
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#define EM_CRX 114
/* National Semiconductor CompactRISC CRX microprocessor */
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#define EM_XGATE 115
/* Motorola XGATE embedded processor */
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#define EM_C166 116
/* Infineon C16x/XC16x processor */
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#define EM_M16C 117
/* Renesas M16C series microprocessors */
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#define EM_DSPIC30F 118
/* Microchip Technology dsPIC30F Digital Signal Controller */
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#define EM_CE 119
/* Freescale Communication Engine RISC core */
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#define EM_M32C 120
/* Renesas M32C series microprocessors */
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#define EM_TSK3000 131
/* Altium TSK3000 core */
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#define EM_RS08 132
/* Freescale RS08 embedded processor */
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#define EM_SHARC 133
/* Analog Devices SHARC family of 32-bit DSP processors */
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#define EM_ECOG2 134
/* Cyan Technology eCOG2 microprocessor */
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#define EM_SCORE7 135
/* Sunplus S+core7 RISC processor */
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#define EM_DSP24 136
/* New Japan Radio (NJR) 24-bit DSP Processor */
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#define EM_VIDEOCORE3 137
/* Broadcom VideoCore III processor */
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#define EM_LATTICEMICO32 138
/* RISC processor for Lattice FPGA architecture */
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#define EM_SE_C17 139
/* Seiko Epson C17 family */
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#define EM_TI_C6000 140
/* The Texas Instruments TMS320C6000 DSP family */
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#define EM_TI_C2000 141
/* The Texas Instruments TMS320C2000 DSP family */
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#define EM_TI_C5500 142
/* The Texas Instruments TMS320C55x DSP family */
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#define EM_TI_ARP32 143
/* Texas Instruments Application Specific RISC Processor, 32bit fetch */
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#define EM_TI_PRU 144
/* Texas Instruments Programmable Realtime Unit */
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#define EM_MMDSP_PLUS 160
/* STMicroelectronics 64bit VLIW Data Signal Processor */
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#define EM_CYPRESS_M8C 161
/* Cypress M8C microprocessor */
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#define EM_R32C 162
/* Renesas R32C series microprocessors */
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#define EM_TRIMEDIA 163
/* NXP Semiconductors TriMedia architecture family */
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#define EM_QDSP6 164
/* QUALCOMM DSP6 Processor */
// Nonstandard
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#define EM_8051 165
/* Intel 8051 and variants */
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#define EM_STXP7X 166
/* STMicroelectronics STxP7x family of configurable and extensible RISC processors */
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#define EM_NDS32 167
/* Andes Technology compact code size embedded RISC processor family */
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#define EM_ECOG1 168
/* Cyan Technology eCOG1X family */
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#define EM_MAXQ30 169
/* Dallas Semiconductor MAXQ30 Core Micro-controllers */
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#define EM_XIMO16 170
/* New Japan Radio (NJR) 16-bit DSP Processor */
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#define EM_MANIK 171
/* M2000 Reconfigurable RISC Microprocessor */
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#define EM_CRAYNV2 172
/* Cray Inc. NV2 vector architecture */
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#define EM_RX 173
/* Renesas RX family */
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#define EM_METAG 174
/* Imagination Technologies META processor architecture */
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#define EM_MCST_ELBRUS 175
/* MCST Elbrus general purpose hardware architecture */
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#define EM_ECOG16 176
/* Cyan Technology eCOG16 family */
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#define EM_CR16 177
/* National Semiconductor CompactRISC CR16 16-bit microprocessor */
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#define EM_ETPU 178
/* Freescale Extended Time Processing Unit */
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#define EM_SLE9X 179
/* Infineon Technologies SLE9X core */
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#define EM_L10M 180
/* Intel L10M */
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#define EM_K10M 181
/* Intel K10M */
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#define EM_AARCH64 183
/* ARM 64-bit architecture (AARCH64) */
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#define EM_AVR32 185
/* Atmel Corporation 32-bit microprocessor family */
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#define EM_STM8 186
/* STMicroeletronics STM8 8-bit microcontroller */
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#define EM_TILE64 187
/* Tilera TILE64 multicore architecture family */
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#define EM_TILEPRO 188
/* Tilera TILEPro multicore architecture family */
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#define EM_MICROBLAZE 189
/* Xilinx MicroBlaze 32-bit RISC soft processor core */
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#define EM_CUDA 190
/* NVIDIA CUDA architecture */
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#define EM_TILEGX 191
/* Tilera TILE-Gx multicore architecture family */
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#define EM_CLOUDSHIELD 192
/* CloudShield architecture family */
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#define EM_COREA_1ST 193
/* KIPO-KAIST Core-A 1st generation processor family */
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#define EM_COREA_2ND 194
/* KIPO-KAIST Core-A 2nd generation processor family */
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#define EM_ARC_COMPACT2 195
/* Synopsys ARCompact V2 */
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#define EM_OPEN8 196
/* Open8 8-bit RISC soft processor core */
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#define EM_RL78 197
/* Renesas RL78 family */
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#define EM_VIDEOCORE5 198
/* Broadcom VideoCore V processor */
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#define EM_78KOR 199
/* Renesas 78KOR family */
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#define EM_56800EX 200
/* Freescale 56800EX Digital Signal Controller (DSC) */
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#define EM_BA1 201
/* Beyond BA1 CPU architecture */
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#define EM_BA2 202
/* Beyond BA2 CPU architecture */
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#define EM_BA2_NON_STANDARD 0x8472
/* Beyond BA2 CPU architecture */
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#define EM_XCORE 203
/* XMOS xCORE processor family */
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#define EM_MCHP_PIC 204
/* Microchip 8-bit PIC(r) family */
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#define EM_INTEL205 205
/* Reserved by Intel */
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#define EM_INTEL206 206
/* Reserved by Intel */
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#define EM_INTEL207 207
/* Reserved by Intel */
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#define EM_INTEL208 208
/* Reserved by Intel */
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#define EM_INTEL209 209
/* Reserved by Intel */
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#define EM_KM32 210
/* KM211 KM32 32-bit processor */
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#define EM_KMX32 211
/* KM211 KMX32 32-bit processor */
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#define EM_KMX16 212
/* KM211 KMX16 16-bit processor */
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#define EM_KMX8 213
/* KM211 KMX8 8-bit processor */
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#define EM_KVARC 214
/* KM211 KVARC processor */
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#define EM_CDP 215
/* Paneve CDP architecture family */
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#define EM_COGE 216
/* Cognitive Smart Memory Processor */
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#define EM_COOL 217
/* Bluechip Systems CoolEngine */
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#define EM_NORC 218
/* Nanoradio Optimized RISC */
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#define EM_CSR_KALIMBA 219
/* CSR Kalimba architecture family */
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#define EM_Z80 220
/* Zilog Z80 */
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#define EM_VISIUM 221
/* Controls and Data Services VISIUMcore processor */
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#define EM_FT32 222
/* FTDI Chip FT32 high performance 32-bit RISC architecture */
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#define EM_MOXIE 223
/* Moxie processor family */
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#define EM_AMDGPU 224
/* AMD GPU architecture */
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#define EM_RISCV 243
/* RISC-V */
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#define EM_KVX 256
/* Kalray VLIW core of the MPPA processor family */
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// specific OpenBSD sections
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#ifndef PT_OPENBSD_RANDOMIZE
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#define PT_OPENBSD_RANDOMIZE 0x65a3dbe6
/* Random data */
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#define PT_OPENBSD_WXNEEDED 0x65a3dbe7
/* Allowing writable/executable mapping */
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#define PT_OPENBSD_BOOTDATA 0x65a41be6
/* Boot time data */
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#endif
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#endif
// _INCLUDE_ELF_SPECS_H
glibc_elf.h
librz
bin
format
elf
elf_specs.h
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