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unix-like reverse engineering framework and cli tools
TMS320C64xGenRegisterInfo.inc
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1 /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2 |* *|
3 |*Target Register Enum Values *|
4 |* *|
5 |* Automatically generated file, do not edit! *|
6 |* *|
7 \*===----------------------------------------------------------------------===*/
8 
9 
10 #ifdef GET_REGINFO_ENUM
11 #undef GET_REGINFO_ENUM
12 
13 enum {
14  TMS320C64x_NoRegister,
15  TMS320C64x_AMR = 1,
16  TMS320C64x_CSR = 2,
17  TMS320C64x_DIER = 3,
18  TMS320C64x_DNUM = 4,
19  TMS320C64x_ECR = 5,
20  TMS320C64x_GFPGFR = 6,
21  TMS320C64x_GPLYA = 7,
22  TMS320C64x_GPLYB = 8,
23  TMS320C64x_ICR = 9,
24  TMS320C64x_IER = 10,
25  TMS320C64x_IERR = 11,
26  TMS320C64x_ILC = 12,
27  TMS320C64x_IRP = 13,
28  TMS320C64x_ISR = 14,
29  TMS320C64x_ISTP = 15,
30  TMS320C64x_ITSR = 16,
31  TMS320C64x_NRP = 17,
32  TMS320C64x_NTSR = 18,
33  TMS320C64x_REP = 19,
34  TMS320C64x_RILC = 20,
35  TMS320C64x_SSR = 21,
36  TMS320C64x_TSCH = 22,
37  TMS320C64x_TSCL = 23,
38  TMS320C64x_TSR = 24,
39  TMS320C64x_A0 = 25,
40  TMS320C64x_A1 = 26,
41  TMS320C64x_A2 = 27,
42  TMS320C64x_A3 = 28,
43  TMS320C64x_A4 = 29,
44  TMS320C64x_A5 = 30,
45  TMS320C64x_A6 = 31,
46  TMS320C64x_A7 = 32,
47  TMS320C64x_A8 = 33,
48  TMS320C64x_A9 = 34,
49  TMS320C64x_A10 = 35,
50  TMS320C64x_A11 = 36,
51  TMS320C64x_A12 = 37,
52  TMS320C64x_A13 = 38,
53  TMS320C64x_A14 = 39,
54  TMS320C64x_A15 = 40,
55  TMS320C64x_A16 = 41,
56  TMS320C64x_A17 = 42,
57  TMS320C64x_A18 = 43,
58  TMS320C64x_A19 = 44,
59  TMS320C64x_A20 = 45,
60  TMS320C64x_A21 = 46,
61  TMS320C64x_A22 = 47,
62  TMS320C64x_A23 = 48,
63  TMS320C64x_A24 = 49,
64  TMS320C64x_A25 = 50,
65  TMS320C64x_A26 = 51,
66  TMS320C64x_A27 = 52,
67  TMS320C64x_A28 = 53,
68  TMS320C64x_A29 = 54,
69  TMS320C64x_A30 = 55,
70  TMS320C64x_A31 = 56,
71  TMS320C64x_B0 = 57,
72  TMS320C64x_B1 = 58,
73  TMS320C64x_B2 = 59,
74  TMS320C64x_B3 = 60,
75  TMS320C64x_B4 = 61,
76  TMS320C64x_B5 = 62,
77  TMS320C64x_B6 = 63,
78  TMS320C64x_B7 = 64,
79  TMS320C64x_B8 = 65,
80  TMS320C64x_B9 = 66,
81  TMS320C64x_B10 = 67,
82  TMS320C64x_B11 = 68,
83  TMS320C64x_B12 = 69,
84  TMS320C64x_B13 = 70,
85  TMS320C64x_B14 = 71,
86  TMS320C64x_B15 = 72,
87  TMS320C64x_B16 = 73,
88  TMS320C64x_B17 = 74,
89  TMS320C64x_B18 = 75,
90  TMS320C64x_B19 = 76,
91  TMS320C64x_B20 = 77,
92  TMS320C64x_B21 = 78,
93  TMS320C64x_B22 = 79,
94  TMS320C64x_B23 = 80,
95  TMS320C64x_B24 = 81,
96  TMS320C64x_B25 = 82,
97  TMS320C64x_B26 = 83,
98  TMS320C64x_B27 = 84,
99  TMS320C64x_B28 = 85,
100  TMS320C64x_B29 = 86,
101  TMS320C64x_B30 = 87,
102  TMS320C64x_B31 = 88,
103  TMS320C64x_PCE1 = 89,
104  TMS320C64x_NUM_TARGET_REGS // 90
105 };
106 
107 // Register classes
108 enum {
109  TMS320C64x_GPRegsRegClassID = 0,
110  TMS320C64x_AFRegsRegClassID = 1,
111  TMS320C64x_BFRegsRegClassID = 2,
112  TMS320C64x_ControlRegsRegClassID = 3,
113 
114  };
115 #endif // GET_REGINFO_ENUM
116 
117 /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
118 |* *|
119 |*MC Register Information *|
120 |* *|
121 |* Automatically generated file, do not edit! *|
122 |* *|
123 \*===----------------------------------------------------------------------===*/
124 
125 
126 #ifdef GET_REGINFO_MC_DESC
127 #undef GET_REGINFO_MC_DESC
128 
129 static MCPhysReg TMS320C64xRegDiffLists[] = {
130  /* 0 */ 65535, 0,
131 };
132 
133 static uint16_t TMS320C64xSubRegIdxLists[] = {
134  /* 0 */ 0,
135 };
136 
137 static MCRegisterDesc TMS320C64xRegDesc[] = { // Descriptors
138  { 3, 0, 0, 0, 0 },
139  { 310, 1, 1, 0, 1 },
140  { 319, 1, 1, 0, 1 },
141  { 298, 1, 1, 0, 1 },
142  { 268, 1, 1, 0, 1 },
143  { 290, 1, 1, 0, 1 },
144  { 303, 1, 1, 0, 1 },
145  { 241, 1, 1, 0, 1 },
146  { 247, 1, 1, 0, 1 },
147  { 294, 1, 1, 0, 1 },
148  { 299, 1, 1, 0, 1 },
149  { 314, 1, 1, 0, 1 },
150  { 254, 1, 1, 0, 1 },
151  { 277, 1, 1, 0, 1 },
152  { 323, 1, 1, 0, 1 },
153  { 285, 1, 1, 0, 1 },
154  { 331, 1, 1, 0, 1 },
155  { 281, 1, 1, 0, 1 },
156  { 336, 1, 1, 0, 1 },
157  { 273, 1, 1, 0, 1 },
158  { 253, 1, 1, 0, 1 },
159  { 327, 1, 1, 0, 1 },
160  { 258, 1, 1, 0, 1 },
161  { 263, 1, 1, 0, 1 },
162  { 332, 1, 1, 0, 1 },
163  { 24, 1, 1, 0, 1 },
164  { 54, 1, 1, 0, 1 },
165  { 81, 1, 1, 0, 1 },
166  { 103, 1, 1, 0, 1 },
167  { 125, 1, 1, 0, 1 },
168  { 147, 1, 1, 0, 1 },
169  { 169, 1, 1, 0, 1 },
170  { 191, 1, 1, 0, 1 },
171  { 213, 1, 1, 0, 1 },
172  { 235, 1, 1, 0, 1 },
173  { 0, 1, 1, 0, 1 },
174  { 30, 1, 1, 0, 1 },
175  { 65, 1, 1, 0, 1 },
176  { 87, 1, 1, 0, 1 },
177  { 109, 1, 1, 0, 1 },
178  { 131, 1, 1, 0, 1 },
179  { 153, 1, 1, 0, 1 },
180  { 175, 1, 1, 0, 1 },
181  { 197, 1, 1, 0, 1 },
182  { 219, 1, 1, 0, 1 },
183  { 8, 1, 1, 0, 1 },
184  { 38, 1, 1, 0, 1 },
185  { 73, 1, 1, 0, 1 },
186  { 95, 1, 1, 0, 1 },
187  { 117, 1, 1, 0, 1 },
188  { 139, 1, 1, 0, 1 },
189  { 161, 1, 1, 0, 1 },
190  { 183, 1, 1, 0, 1 },
191  { 205, 1, 1, 0, 1 },
192  { 227, 1, 1, 0, 1 },
193  { 16, 1, 1, 0, 1 },
194  { 46, 1, 1, 0, 1 },
195  { 27, 1, 1, 0, 1 },
196  { 57, 1, 1, 0, 1 },
197  { 84, 1, 1, 0, 1 },
198  { 106, 1, 1, 0, 1 },
199  { 128, 1, 1, 0, 1 },
200  { 150, 1, 1, 0, 1 },
201  { 172, 1, 1, 0, 1 },
202  { 194, 1, 1, 0, 1 },
203  { 216, 1, 1, 0, 1 },
204  { 238, 1, 1, 0, 1 },
205  { 4, 1, 1, 0, 1 },
206  { 34, 1, 1, 0, 1 },
207  { 69, 1, 1, 0, 1 },
208  { 91, 1, 1, 0, 1 },
209  { 113, 1, 1, 0, 1 },
210  { 135, 1, 1, 0, 1 },
211  { 157, 1, 1, 0, 1 },
212  { 179, 1, 1, 0, 1 },
213  { 201, 1, 1, 0, 1 },
214  { 223, 1, 1, 0, 1 },
215  { 12, 1, 1, 0, 1 },
216  { 42, 1, 1, 0, 1 },
217  { 77, 1, 1, 0, 1 },
218  { 99, 1, 1, 0, 1 },
219  { 121, 1, 1, 0, 1 },
220  { 143, 1, 1, 0, 1 },
221  { 165, 1, 1, 0, 1 },
222  { 187, 1, 1, 0, 1 },
223  { 209, 1, 1, 0, 1 },
224  { 231, 1, 1, 0, 1 },
225  { 20, 1, 1, 0, 1 },
226  { 50, 1, 1, 0, 1 },
227  { 60, 1, 1, 0, 1 },
228 };
229 
230 // GPRegs Register Class...
231 static MCPhysReg GPRegs[] = {
232  TMS320C64x_A0, TMS320C64x_A1, TMS320C64x_A2, TMS320C64x_A3, TMS320C64x_A4, TMS320C64x_A5, TMS320C64x_A6, TMS320C64x_A7, TMS320C64x_A8, TMS320C64x_A9, TMS320C64x_A10, TMS320C64x_A11, TMS320C64x_A12, TMS320C64x_A13, TMS320C64x_A14, TMS320C64x_A15, TMS320C64x_A16, TMS320C64x_A17, TMS320C64x_A18, TMS320C64x_A19, TMS320C64x_A20, TMS320C64x_A21, TMS320C64x_A22, TMS320C64x_A23, TMS320C64x_A24, TMS320C64x_A25, TMS320C64x_A26, TMS320C64x_A27, TMS320C64x_A28, TMS320C64x_A29, TMS320C64x_A30, TMS320C64x_A31, TMS320C64x_B0, TMS320C64x_B1, TMS320C64x_B2, TMS320C64x_B3, TMS320C64x_B4, TMS320C64x_B5, TMS320C64x_B6, TMS320C64x_B7, TMS320C64x_B8, TMS320C64x_B9, TMS320C64x_B10, TMS320C64x_B11, TMS320C64x_B12, TMS320C64x_B13, TMS320C64x_B14, TMS320C64x_B15, TMS320C64x_B16, TMS320C64x_B17, TMS320C64x_B18, TMS320C64x_B19, TMS320C64x_B20, TMS320C64x_B21, TMS320C64x_B22, TMS320C64x_B23, TMS320C64x_B24, TMS320C64x_B25, TMS320C64x_B26, TMS320C64x_B27, TMS320C64x_B28, TMS320C64x_B29, TMS320C64x_B30, TMS320C64x_B31,
233 };
234 
235 // GPRegs Bit set.
236 static uint8_t GPRegsBits[] = {
237  0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01,
238 };
239 
240 // AFRegs Register Class...
241 static MCPhysReg AFRegs[] = {
242  TMS320C64x_A0, TMS320C64x_A1, TMS320C64x_A2, TMS320C64x_A3, TMS320C64x_A4, TMS320C64x_A5, TMS320C64x_A6, TMS320C64x_A7, TMS320C64x_A8, TMS320C64x_A9, TMS320C64x_A10, TMS320C64x_A11, TMS320C64x_A12, TMS320C64x_A13, TMS320C64x_A14, TMS320C64x_A15, TMS320C64x_A16, TMS320C64x_A17, TMS320C64x_A18, TMS320C64x_A19, TMS320C64x_A20, TMS320C64x_A21, TMS320C64x_A22, TMS320C64x_A23, TMS320C64x_A24, TMS320C64x_A25, TMS320C64x_A26, TMS320C64x_A27, TMS320C64x_A28, TMS320C64x_A29, TMS320C64x_A30, TMS320C64x_A31,
243 };
244 
245 // AFRegs Bit set.
246 static uint8_t AFRegsBits[] = {
247  0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
248 };
249 
250 // BFRegs Register Class...
251 static MCPhysReg BFRegs[] = {
252  TMS320C64x_B0, TMS320C64x_B1, TMS320C64x_B2, TMS320C64x_B3, TMS320C64x_B4, TMS320C64x_B5, TMS320C64x_B6, TMS320C64x_B7, TMS320C64x_B8, TMS320C64x_B9, TMS320C64x_B10, TMS320C64x_B11, TMS320C64x_B12, TMS320C64x_B13, TMS320C64x_B14, TMS320C64x_B15, TMS320C64x_B16, TMS320C64x_B17, TMS320C64x_B18, TMS320C64x_B19, TMS320C64x_B20, TMS320C64x_B21, TMS320C64x_B22, TMS320C64x_B23, TMS320C64x_B24, TMS320C64x_B25, TMS320C64x_B26, TMS320C64x_B27, TMS320C64x_B28, TMS320C64x_B29, TMS320C64x_B30, TMS320C64x_B31,
253 };
254 
255 // BFRegs Bit set.
256 static uint8_t BFRegsBits[] = {
257  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
258 };
259 
260 // ControlRegs Register Class...
261 static MCPhysReg ControlRegs[] = {
262  TMS320C64x_AMR, TMS320C64x_CSR, TMS320C64x_DIER, TMS320C64x_DNUM, TMS320C64x_ECR, TMS320C64x_GFPGFR, TMS320C64x_GPLYA, TMS320C64x_GPLYB, TMS320C64x_ICR, TMS320C64x_IER, TMS320C64x_IERR, TMS320C64x_ILC, TMS320C64x_IRP, TMS320C64x_ISR, TMS320C64x_ISTP, TMS320C64x_ITSR, TMS320C64x_NRP, TMS320C64x_NTSR, TMS320C64x_PCE1, TMS320C64x_REP, TMS320C64x_RILC, TMS320C64x_SSR, TMS320C64x_TSCH, TMS320C64x_TSCL, TMS320C64x_TSR,
263 };
264 
265 // ControlRegs Bit set.
266 static uint8_t ControlRegsBits[] = {
267  0xfe, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
268 };
269 
270 static MCRegisterClass TMS320C64xMCRegisterClasses[] = {
271  { GPRegs, GPRegsBits, 64, sizeof(GPRegsBits), TMS320C64x_GPRegsRegClassID, 4, 4, 1, 1 },
272  { AFRegs, AFRegsBits, 32, sizeof(AFRegsBits), TMS320C64x_AFRegsRegClassID, 4, 4, 1, 1 },
273  { BFRegs, BFRegsBits, 32, sizeof(BFRegsBits), TMS320C64x_BFRegsRegClassID, 4, 4, 1, 1 },
274  { ControlRegs, ControlRegsBits, 25, sizeof(ControlRegsBits), TMS320C64x_ControlRegsRegClassID, 4, 4, 1, 1 },
275 };
276 
277 #endif // GET_REGINFO_MC_DESC
278 
MCPhysReg
uint16_t MCPhysReg
Definition: MCRegisterInfo.h:26
uint16_t
unsigned short uint16_t
Definition: sftypes.h:30
uint8_t
unsigned char uint8_t
Definition: sftypes.h:31