Rizin
unix-like reverse engineering framework and cli tools
TMS320C64xGenDisassemblerTables.inc
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1 /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2 |* *|
3 |* * TMS320C64x Disassembler *|
4 |* *|
5 |* Automatically generated file, do not edit! *|
6 |* *|
7 \*===----------------------------------------------------------------------===*/
8 
9 #include "../../MCInst.h"
10 #include "../../LEB128.h"
11 
12 // Helper function for extracting fields from encoded instructions.
13 #define FieldFromInstruction(fname, InsnType) \
14 static InsnType fname(InsnType insn, unsigned startBit, \
15  unsigned numBits) { \
16  InsnType fieldMask; \
17  if (numBits == sizeof(InsnType)*8) \
18  fieldMask = (InsnType)(-1LL); \
19  else \
20  fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
21  return (insn & fieldMask) >> startBit; \
22 }
23 
24 static uint8_t DecoderTable32[] = {
25 /* 0 */ MCD_OPC_ExtractField, 2, 5, // Inst{6-2} ...
26 /* 3 */ MCD_OPC_FilterValue, 0, 199, 0, // Skip to: 206
27 /* 7 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ...
28 /* 10 */ MCD_OPC_FilterValue, 0, 16, 0, // Skip to: 30
29 /* 14 */ MCD_OPC_CheckField, 17, 11, 0, 153, 8, // Skip to: 2221
30 /* 20 */ MCD_OPC_CheckField, 12, 1, 0, 147, 8, // Skip to: 2221
31 /* 26 */ MCD_OPC_Decode, 162, 1, 0, // Opcode: NOP_n
32 /* 30 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 38
33 /* 34 */ MCD_OPC_Decode, 140, 1, 1, // Opcode: MPYH_m4_rrr
34 /* 38 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 46
35 /* 42 */ MCD_OPC_Decode, 219, 1, 1, // Opcode: SMPYH_m4_rrr
36 /* 46 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 54
37 /* 50 */ MCD_OPC_Decode, 136, 1, 1, // Opcode: MPYHSU_m4_rrr
38 /* 54 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 62
39 /* 58 */ MCD_OPC_Decode, 138, 1, 1, // Opcode: MPYHUS_m4_rrr
40 /* 62 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 70
41 /* 66 */ MCD_OPC_Decode, 139, 1, 1, // Opcode: MPYHU_m4_rrr
42 /* 70 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 78
43 /* 74 */ MCD_OPC_Decode, 134, 1, 1, // Opcode: MPYHL_m4_rrr
44 /* 78 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 86
45 /* 82 */ MCD_OPC_Decode, 218, 1, 1, // Opcode: SMPYHL_m4_rrr
46 /* 86 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 94
47 /* 90 */ MCD_OPC_Decode, 135, 1, 1, // Opcode: MPYHSLU_m4_rrr
48 /* 94 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 102
49 /* 98 */ MCD_OPC_Decode, 137, 1, 1, // Opcode: MPYHULS_m4_rrr
50 /* 102 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 110
51 /* 106 */ MCD_OPC_Decode, 133, 1, 1, // Opcode: MPYHLU_m4_rrr
52 /* 110 */ MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 118
53 /* 114 */ MCD_OPC_Decode, 142, 1, 1, // Opcode: MPYLH_m4_rrr
54 /* 118 */ MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 126
55 /* 122 */ MCD_OPC_Decode, 220, 1, 1, // Opcode: SMPYLH_m4_rrr
56 /* 126 */ MCD_OPC_FilterValue, 19, 4, 0, // Skip to: 134
57 /* 130 */ MCD_OPC_Decode, 145, 1, 1, // Opcode: MPYLSHU_m4_rrr
58 /* 134 */ MCD_OPC_FilterValue, 21, 4, 0, // Skip to: 142
59 /* 138 */ MCD_OPC_Decode, 146, 1, 1, // Opcode: MPYLUHS_m4_rrr
60 /* 142 */ MCD_OPC_FilterValue, 23, 4, 0, // Skip to: 150
61 /* 146 */ MCD_OPC_Decode, 141, 1, 1, // Opcode: MPYLHU_m4_rrr
62 /* 150 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 158
63 /* 154 */ MCD_OPC_Decode, 153, 1, 2, // Opcode: MPY_m4_irr
64 /* 158 */ MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 166
65 /* 162 */ MCD_OPC_Decode, 154, 1, 1, // Opcode: MPY_m4_rrr
66 /* 166 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 174
67 /* 170 */ MCD_OPC_Decode, 221, 1, 1, // Opcode: SMPY_m4_rrr
68 /* 174 */ MCD_OPC_FilterValue, 27, 4, 0, // Skip to: 182
69 /* 178 */ MCD_OPC_Decode, 149, 1, 1, // Opcode: MPYSU_m4_rrr
70 /* 182 */ MCD_OPC_FilterValue, 29, 4, 0, // Skip to: 190
71 /* 186 */ MCD_OPC_Decode, 151, 1, 1, // Opcode: MPYUS_m4_rrr
72 /* 190 */ MCD_OPC_FilterValue, 30, 4, 0, // Skip to: 198
73 /* 194 */ MCD_OPC_Decode, 148, 1, 2, // Opcode: MPYSU_m4_irr
74 /* 198 */ MCD_OPC_FilterValue, 31, 227, 7, // Skip to: 2221
75 /* 202 */ MCD_OPC_Decode, 152, 1, 1, // Opcode: MPYU_m4_rrr
76 /* 206 */ MCD_OPC_FilterValue, 1, 9, 0, // Skip to: 219
77 /* 210 */ MCD_OPC_CheckField, 8, 1, 0, 213, 7, // Skip to: 2221
78 /* 216 */ MCD_OPC_Decode, 116, 3, // Opcode: LDHU_d5_mr
79 /* 219 */ MCD_OPC_FilterValue, 2, 18, 0, // Skip to: 241
80 /* 223 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ...
81 /* 226 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 233
82 /* 230 */ MCD_OPC_Decode, 102, 4, // Opcode: EXTU_s15_riir
83 /* 233 */ MCD_OPC_FilterValue, 1, 192, 7, // Skip to: 2221
84 /* 237 */ MCD_OPC_Decode, 192, 1, 4, // Opcode: SET_s15_riir
85 /* 241 */ MCD_OPC_FilterValue, 3, 3, 0, // Skip to: 248
86 /* 245 */ MCD_OPC_Decode, 117, 5, // Opcode: LDHU_d6_mr
87 /* 248 */ MCD_OPC_FilterValue, 4, 3, 0, // Skip to: 255
88 /* 252 */ MCD_OPC_Decode, 68, 6, // Opcode: B_s5_i
89 /* 255 */ MCD_OPC_FilterValue, 5, 9, 0, // Skip to: 268
90 /* 259 */ MCD_OPC_CheckField, 8, 1, 0, 164, 7, // Skip to: 2221
91 /* 265 */ MCD_OPC_Decode, 111, 3, // Opcode: LDBU_d5_mr
92 /* 268 */ MCD_OPC_FilterValue, 6, 157, 0, // Skip to: 429
93 /* 272 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ...
94 /* 275 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 283
95 /* 279 */ MCD_OPC_Decode, 171, 1, 1, // Opcode: PACK2_l1_rrr_x2
96 /* 283 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 291
97 /* 287 */ MCD_OPC_Decode, 242, 1, 1, // Opcode: SUB2_l1_rrr_x2
98 /* 291 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 299
99 /* 295 */ MCD_OPC_Decode, 176, 1, 1, // Opcode: PACKHL2_l1_rrr_x2
100 /* 299 */ MCD_OPC_FilterValue, 8, 3, 0, // Skip to: 306
101 /* 303 */ MCD_OPC_Decode, 45, 7, // Opcode: ADD_l1_ipp
102 /* 306 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 314
103 /* 310 */ MCD_OPC_Decode, 130, 2, 7, // Opcode: SUB_l1_ipp
104 /* 314 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 322
105 /* 318 */ MCD_OPC_Decode, 228, 1, 7, // Opcode: SSUB_l1_ipp
106 /* 322 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 330
107 /* 326 */ MCD_OPC_Decode, 186, 1, 7, // Opcode: SADD_l1_ipp
108 /* 330 */ MCD_OPC_FilterValue, 14, 9, 0, // Skip to: 343
109 /* 334 */ MCD_OPC_CheckField, 13, 5, 0, 89, 7, // Skip to: 2221
110 /* 340 */ MCD_OPC_Decode, 23, 8, // Opcode: ABS_l1_pp
111 /* 343 */ MCD_OPC_FilterValue, 16, 10, 0, // Skip to: 357
112 /* 347 */ MCD_OPC_CheckField, 13, 5, 0, 76, 7, // Skip to: 2221
113 /* 353 */ MCD_OPC_Decode, 191, 1, 9, // Opcode: SAT_l1_pr
114 /* 357 */ MCD_OPC_FilterValue, 17, 3, 0, // Skip to: 364
115 /* 361 */ MCD_OPC_Decode, 82, 10, // Opcode: CMPGT_l1_ipr
116 /* 364 */ MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 372
117 /* 368 */ MCD_OPC_Decode, 129, 1, 1, // Opcode: MINU4_l1_rrr_x2
118 /* 372 */ MCD_OPC_FilterValue, 19, 3, 0, // Skip to: 379
119 /* 376 */ MCD_OPC_Decode, 106, 11, // Opcode: GMPGTU_l1_ipr
120 /* 379 */ MCD_OPC_FilterValue, 20, 3, 0, // Skip to: 386
121 /* 383 */ MCD_OPC_Decode, 76, 10, // Opcode: CMPEQ_l1_ipr
122 /* 386 */ MCD_OPC_FilterValue, 21, 3, 0, // Skip to: 393
123 /* 390 */ MCD_OPC_Decode, 90, 10, // Opcode: CMPLT_l1_ipr
124 /* 393 */ MCD_OPC_FilterValue, 23, 3, 0, // Skip to: 400
125 /* 397 */ MCD_OPC_Decode, 86, 11, // Opcode: CMPLTU_l1_ipr
126 /* 400 */ MCD_OPC_FilterValue, 24, 10, 0, // Skip to: 414
127 /* 404 */ MCD_OPC_CheckField, 13, 5, 0, 19, 7, // Skip to: 2221
128 /* 410 */ MCD_OPC_Decode, 163, 1, 12, // Opcode: NORM_l1_pr
129 /* 414 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 422
130 /* 418 */ MCD_OPC_Decode, 178, 1, 1, // Opcode: PACKL4_l1_rrr_x2
131 /* 422 */ MCD_OPC_FilterValue, 31, 3, 7, // Skip to: 2221
132 /* 426 */ MCD_OPC_Decode, 53, 1, // Opcode: ANDN_l1_rrr_x2
133 /* 429 */ MCD_OPC_FilterValue, 7, 3, 0, // Skip to: 436
134 /* 433 */ MCD_OPC_Decode, 112, 5, // Opcode: LDBU_d6_mr
135 /* 436 */ MCD_OPC_FilterValue, 8, 222, 0, // Skip to: 662
136 /* 440 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ...
137 /* 443 */ MCD_OPC_FilterValue, 0, 17, 0, // Skip to: 464
138 /* 447 */ MCD_OPC_ExtractField, 12, 1, // Inst{12} ...
139 /* 450 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 457
140 /* 454 */ MCD_OPC_Decode, 67, 13, // Opcode: BPOS_s8_ir
141 /* 457 */ MCD_OPC_FilterValue, 1, 224, 6, // Skip to: 2221
142 /* 461 */ MCD_OPC_Decode, 63, 13, // Opcode: BDEC_s8_ir
143 /* 464 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 477
144 /* 468 */ MCD_OPC_CheckField, 12, 1, 0, 211, 6, // Skip to: 2221
145 /* 474 */ MCD_OPC_Decode, 66, 14, // Opcode: BNOP_s9_ii
146 /* 477 */ MCD_OPC_FilterValue, 3, 3, 0, // Skip to: 484
147 /* 481 */ MCD_OPC_Decode, 50, 2, // Opcode: ADD_s1_irr
148 /* 484 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 492
149 /* 488 */ MCD_OPC_Decode, 177, 1, 1, // Opcode: PACKHL2_s1_rrr
150 /* 492 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 500
151 /* 496 */ MCD_OPC_Decode, 148, 2, 2, // Opcode: XOR_s1_irr
152 /* 500 */ MCD_OPC_FilterValue, 7, 10, 0, // Skip to: 514
153 /* 504 */ MCD_OPC_CheckField, 13, 5, 0, 175, 6, // Skip to: 2221
154 /* 510 */ MCD_OPC_Decode, 156, 1, 15, // Opcode: MVC_s1_rr2
155 /* 514 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 522
156 /* 518 */ MCD_OPC_Decode, 180, 1, 1, // Opcode: PACKLH2_s1_rrr
157 /* 522 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 530
158 /* 526 */ MCD_OPC_Decode, 199, 1, 16, // Opcode: SHL_s1_rip
159 /* 530 */ MCD_OPC_FilterValue, 10, 3, 0, // Skip to: 537
160 /* 534 */ MCD_OPC_Decode, 80, 1, // Opcode: CMPGT2_s1_rrr
161 /* 537 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 545
162 /* 541 */ MCD_OPC_Decode, 136, 2, 2, // Opcode: SUB_s1_irr
163 /* 545 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 553
164 /* 549 */ MCD_OPC_Decode, 203, 1, 17, // Opcode: SHR2_s1_rir
165 /* 553 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 561
166 /* 557 */ MCD_OPC_Decode, 169, 1, 2, // Opcode: OR_s1_irr
167 /* 561 */ MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 568
168 /* 565 */ MCD_OPC_Decode, 75, 1, // Opcode: CMPEQ4_s1_rrr
169 /* 568 */ MCD_OPC_FilterValue, 15, 3, 0, // Skip to: 575
170 /* 572 */ MCD_OPC_Decode, 59, 2, // Opcode: AND_s1_irr
171 /* 575 */ MCD_OPC_FilterValue, 16, 4, 0, // Skip to: 583
172 /* 579 */ MCD_OPC_Decode, 190, 1, 1, // Opcode: SADD_s1_rrr
173 /* 583 */ MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 591
174 /* 587 */ MCD_OPC_Decode, 224, 1, 17, // Opcode: SSHL_s1_rir
175 /* 591 */ MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 599
176 /* 595 */ MCD_OPC_Decode, 209, 1, 18, // Opcode: SHRU_s1_pip
177 /* 599 */ MCD_OPC_FilterValue, 19, 4, 0, // Skip to: 607
178 /* 603 */ MCD_OPC_Decode, 211, 1, 17, // Opcode: SHRU_s1_rir
179 /* 607 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 615
180 /* 611 */ MCD_OPC_Decode, 197, 1, 19, // Opcode: SHL_s1_pip
181 /* 615 */ MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 623
182 /* 619 */ MCD_OPC_Decode, 200, 1, 20, // Opcode: SHL_s1_rir
183 /* 623 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 631
184 /* 627 */ MCD_OPC_Decode, 213, 1, 18, // Opcode: SHR_s1_pip
185 /* 631 */ MCD_OPC_FilterValue, 27, 4, 0, // Skip to: 639
186 /* 635 */ MCD_OPC_Decode, 215, 1, 17, // Opcode: SHR_s1_rir
187 /* 639 */ MCD_OPC_FilterValue, 30, 42, 6, // Skip to: 2221
188 /* 643 */ MCD_OPC_ExtractField, 13, 5, // Inst{17-13} ...
189 /* 646 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 654
190 /* 650 */ MCD_OPC_Decode, 143, 2, 21, // Opcode: UNPKLU4_s14_rr
191 /* 654 */ MCD_OPC_FilterValue, 3, 27, 6, // Skip to: 2221
192 /* 658 */ MCD_OPC_Decode, 141, 2, 21, // Opcode: UNPKHU4_s14_rr
193 /* 662 */ MCD_OPC_FilterValue, 9, 17, 0, // Skip to: 683
194 /* 666 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ...
195 /* 669 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 676
196 /* 673 */ MCD_OPC_Decode, 113, 3, // Opcode: LDB_d5_mr
197 /* 676 */ MCD_OPC_FilterValue, 1, 5, 6, // Skip to: 2221
198 /* 680 */ MCD_OPC_Decode, 120, 22, // Opcode: LDNDW_d8_mp
199 /* 683 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 691
200 /* 687 */ MCD_OPC_Decode, 159, 1, 23, // Opcode: MVKL_s12_ir
201 /* 691 */ MCD_OPC_FilterValue, 11, 3, 0, // Skip to: 698
202 /* 695 */ MCD_OPC_Decode, 114, 5, // Opcode: LDB_d6_mr
203 /* 698 */ MCD_OPC_FilterValue, 12, 194, 0, // Skip to: 896
204 /* 702 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ...
205 /* 705 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 713
206 /* 709 */ MCD_OPC_Decode, 130, 1, 24, // Opcode: MPY2_m1_rrp
207 /* 713 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 720
208 /* 717 */ MCD_OPC_Decode, 100, 1, // Opcode: DOTPSU4_m1_rrr
209 /* 720 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 728
210 /* 724 */ MCD_OPC_Decode, 150, 1, 24, // Opcode: MPYU4_m1_rrp
211 /* 728 */ MCD_OPC_FilterValue, 3, 3, 0, // Skip to: 735
212 /* 732 */ MCD_OPC_Decode, 101, 1, // Opcode: DOTPU4_m1_rrr
213 /* 735 */ MCD_OPC_FilterValue, 6, 3, 0, // Skip to: 742
214 /* 739 */ MCD_OPC_Decode, 96, 1, // Opcode: DOTP2_m1_rrr
215 /* 742 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 750
216 /* 746 */ MCD_OPC_Decode, 143, 1, 1, // Opcode: MPYLIR_m1_rrr
217 /* 750 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 758
218 /* 754 */ MCD_OPC_Decode, 131, 1, 1, // Opcode: MPYHIR_m1_rrr
219 /* 758 */ MCD_OPC_FilterValue, 9, 3, 0, // Skip to: 765
220 /* 762 */ MCD_OPC_Decode, 62, 1, // Opcode: AVGU4_m1_rrr
221 /* 765 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 773
222 /* 769 */ MCD_OPC_Decode, 132, 1, 24, // Opcode: MPYHI_m1_rrp
223 /* 773 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 781
224 /* 777 */ MCD_OPC_Decode, 227, 1, 1, // Opcode: SSHVR_m1_rrr
225 /* 781 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 789
226 /* 785 */ MCD_OPC_Decode, 226, 1, 1, // Opcode: SSHVL_m1_rrr
227 /* 789 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 797
228 /* 793 */ MCD_OPC_Decode, 181, 1, 17, // Opcode: ROTL_m1_rir
229 /* 797 */ MCD_OPC_FilterValue, 16, 3, 0, // Skip to: 804
230 /* 801 */ MCD_OPC_Decode, 52, 1, // Opcode: ANDN_d2_rrr
231 /* 804 */ MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 812
232 /* 808 */ MCD_OPC_Decode, 166, 1, 1, // Opcode: OR_d2_rrr
233 /* 812 */ MCD_OPC_FilterValue, 18, 3, 0, // Skip to: 819
234 /* 816 */ MCD_OPC_Decode, 25, 1, // Opcode: ADD2_d2_rrr
235 /* 819 */ MCD_OPC_FilterValue, 19, 3, 0, // Skip to: 826
236 /* 823 */ MCD_OPC_Decode, 56, 1, // Opcode: AND_d2_rrr
237 /* 826 */ MCD_OPC_FilterValue, 21, 3, 0, // Skip to: 833
238 /* 830 */ MCD_OPC_Decode, 44, 1, // Opcode: ADD_d2_rrr
239 /* 833 */ MCD_OPC_FilterValue, 22, 4, 0, // Skip to: 841
240 /* 837 */ MCD_OPC_Decode, 129, 2, 1, // Opcode: SUB_d2_rrr
241 /* 841 */ MCD_OPC_FilterValue, 23, 4, 0, // Skip to: 849
242 /* 845 */ MCD_OPC_Decode, 145, 2, 1, // Opcode: XOR_d2_rrr
243 /* 849 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 857
244 /* 853 */ MCD_OPC_Decode, 183, 1, 1, // Opcode: SADD2_s4_rrr
245 /* 857 */ MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 865
246 /* 861 */ MCD_OPC_Decode, 222, 1, 1, // Opcode: SPACK2_s4_rrr
247 /* 865 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 873
248 /* 869 */ MCD_OPC_Decode, 223, 1, 1, // Opcode: SPACKU4_s4_rrr
249 /* 873 */ MCD_OPC_FilterValue, 27, 3, 0, // Skip to: 880
250 /* 877 */ MCD_OPC_Decode, 54, 1, // Opcode: ANDN_s4_rrr
251 /* 880 */ MCD_OPC_FilterValue, 28, 4, 0, // Skip to: 888
252 /* 884 */ MCD_OPC_Decode, 208, 1, 1, // Opcode: SHRU2_s4_rrr
253 /* 888 */ MCD_OPC_FilterValue, 29, 49, 5, // Skip to: 2221
254 /* 892 */ MCD_OPC_Decode, 206, 1, 1, // Opcode: SHRMB_s4_rrr
255 /* 896 */ MCD_OPC_FilterValue, 13, 18, 0, // Skip to: 918
256 /* 900 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ...
257 /* 903 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 911
258 /* 907 */ MCD_OPC_Decode, 232, 1, 3, // Opcode: STB_d5_rm
259 /* 911 */ MCD_OPC_FilterValue, 1, 26, 5, // Skip to: 2221
260 /* 915 */ MCD_OPC_Decode, 121, 3, // Opcode: LDNW_d5_mr
261 /* 918 */ MCD_OPC_FilterValue, 14, 98, 0, // Skip to: 1020
262 /* 922 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ...
263 /* 925 */ MCD_OPC_FilterValue, 1, 3, 0, // Skip to: 932
264 /* 929 */ MCD_OPC_Decode, 26, 1, // Opcode: ADD2_l1_rrr_x2
265 /* 932 */ MCD_OPC_FilterValue, 8, 3, 0, // Skip to: 939
266 /* 936 */ MCD_OPC_Decode, 47, 25, // Opcode: ADD_l1_rpp
267 /* 939 */ MCD_OPC_FilterValue, 10, 3, 0, // Skip to: 946
268 /* 943 */ MCD_OPC_Decode, 39, 25, // Opcode: ADDU_l1_rpp
269 /* 946 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 954
270 /* 950 */ MCD_OPC_Decode, 188, 1, 25, // Opcode: SADD_l1_rpp
271 /* 954 */ MCD_OPC_FilterValue, 16, 4, 0, // Skip to: 962
272 /* 958 */ MCD_OPC_Decode, 128, 1, 1, // Opcode: MIN2_l1_rrr_x2
273 /* 962 */ MCD_OPC_FilterValue, 17, 3, 0, // Skip to: 969
274 /* 966 */ MCD_OPC_Decode, 84, 26, // Opcode: CMPGT_l1_rpr
275 /* 969 */ MCD_OPC_FilterValue, 19, 3, 0, // Skip to: 976
276 /* 973 */ MCD_OPC_Decode, 108, 26, // Opcode: GMPGTU_l1_rpr
277 /* 976 */ MCD_OPC_FilterValue, 20, 3, 0, // Skip to: 983
278 /* 980 */ MCD_OPC_Decode, 78, 26, // Opcode: CMPEQ_l1_rpr
279 /* 983 */ MCD_OPC_FilterValue, 21, 3, 0, // Skip to: 990
280 /* 987 */ MCD_OPC_Decode, 92, 26, // Opcode: CMPLT_l1_rpr
281 /* 990 */ MCD_OPC_FilterValue, 23, 3, 0, // Skip to: 997
282 /* 994 */ MCD_OPC_Decode, 88, 26, // Opcode: CMPLTU_l1_rpr
283 /* 997 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 1005
284 /* 1001 */ MCD_OPC_Decode, 195, 1, 1, // Opcode: SHLMB_l1_rrr_x2
285 /* 1005 */ MCD_OPC_FilterValue, 25, 3, 0, // Skip to: 1012
286 /* 1009 */ MCD_OPC_Decode, 28, 1, // Opcode: ADD4_l1_rrr_x2
287 /* 1012 */ MCD_OPC_FilterValue, 26, 181, 4, // Skip to: 2221
288 /* 1016 */ MCD_OPC_Decode, 175, 1, 1, // Opcode: PACKH4_l1_rrr_x2
289 /* 1020 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 1028
290 /* 1024 */ MCD_OPC_Decode, 233, 1, 5, // Opcode: STB_d6_rm
291 /* 1028 */ MCD_OPC_FilterValue, 16, 151, 0, // Skip to: 1183
292 /* 1032 */ MCD_OPC_ExtractField, 7, 6, // Inst{12-7} ...
293 /* 1035 */ MCD_OPC_FilterValue, 0, 10, 0, // Skip to: 1049
294 /* 1039 */ MCD_OPC_CheckField, 18, 5, 0, 152, 4, // Skip to: 2221
295 /* 1045 */ MCD_OPC_Decode, 160, 1, 27, // Opcode: MVK_d1_rr
296 /* 1049 */ MCD_OPC_FilterValue, 16, 3, 0, // Skip to: 1056
297 /* 1053 */ MCD_OPC_Decode, 42, 28, // Opcode: ADD_d1_rrr
298 /* 1056 */ MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 1064
299 /* 1060 */ MCD_OPC_Decode, 128, 2, 28, // Opcode: SUB_d1_rrr
300 /* 1064 */ MCD_OPC_FilterValue, 18, 3, 0, // Skip to: 1071
301 /* 1068 */ MCD_OPC_Decode, 41, 29, // Opcode: ADD_d1_rir
302 /* 1071 */ MCD_OPC_FilterValue, 19, 4, 0, // Skip to: 1079
303 /* 1075 */ MCD_OPC_Decode, 255, 1, 29, // Opcode: SUB_d1_rir
304 /* 1079 */ MCD_OPC_FilterValue, 48, 3, 0, // Skip to: 1086
305 /* 1083 */ MCD_OPC_Decode, 30, 28, // Opcode: ADDAB_d1_rrr
306 /* 1086 */ MCD_OPC_FilterValue, 49, 4, 0, // Skip to: 1094
307 /* 1090 */ MCD_OPC_Decode, 247, 1, 28, // Opcode: SUBAB_d1_rrr
308 /* 1094 */ MCD_OPC_FilterValue, 50, 3, 0, // Skip to: 1101
309 /* 1098 */ MCD_OPC_Decode, 29, 29, // Opcode: ADDAB_d1_rir
310 /* 1101 */ MCD_OPC_FilterValue, 51, 4, 0, // Skip to: 1109
311 /* 1105 */ MCD_OPC_Decode, 246, 1, 29, // Opcode: SUBAB_d1_rir
312 /* 1109 */ MCD_OPC_FilterValue, 52, 3, 0, // Skip to: 1116
313 /* 1113 */ MCD_OPC_Decode, 34, 28, // Opcode: ADDAH_d1_rrr
314 /* 1116 */ MCD_OPC_FilterValue, 53, 4, 0, // Skip to: 1124
315 /* 1120 */ MCD_OPC_Decode, 249, 1, 28, // Opcode: SUBAH_d1_rrr
316 /* 1124 */ MCD_OPC_FilterValue, 54, 3, 0, // Skip to: 1131
317 /* 1128 */ MCD_OPC_Decode, 33, 29, // Opcode: ADDAH_d1_rir
318 /* 1131 */ MCD_OPC_FilterValue, 55, 4, 0, // Skip to: 1139
319 /* 1135 */ MCD_OPC_Decode, 248, 1, 29, // Opcode: SUBAH_d1_rir
320 /* 1139 */ MCD_OPC_FilterValue, 56, 3, 0, // Skip to: 1146
321 /* 1143 */ MCD_OPC_Decode, 36, 28, // Opcode: ADDAW_d1_rrr
322 /* 1146 */ MCD_OPC_FilterValue, 57, 4, 0, // Skip to: 1154
323 /* 1150 */ MCD_OPC_Decode, 251, 1, 28, // Opcode: SUBAW_d1_rrr
324 /* 1154 */ MCD_OPC_FilterValue, 58, 3, 0, // Skip to: 1161
325 /* 1158 */ MCD_OPC_Decode, 35, 29, // Opcode: ADDAW_d1_rir
326 /* 1161 */ MCD_OPC_FilterValue, 59, 4, 0, // Skip to: 1169
327 /* 1165 */ MCD_OPC_Decode, 250, 1, 29, // Opcode: SUBAW_d1_rir
328 /* 1169 */ MCD_OPC_FilterValue, 60, 3, 0, // Skip to: 1176
329 /* 1173 */ MCD_OPC_Decode, 32, 28, // Opcode: ADDAD_d1_rrr
330 /* 1176 */ MCD_OPC_FilterValue, 61, 17, 4, // Skip to: 2221
331 /* 1180 */ MCD_OPC_Decode, 31, 29, // Opcode: ADDAD_d1_rir
332 /* 1183 */ MCD_OPC_FilterValue, 17, 18, 0, // Skip to: 1205
333 /* 1187 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ...
334 /* 1190 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1197
335 /* 1194 */ MCD_OPC_Decode, 118, 3, // Opcode: LDH_d5_mr
336 /* 1197 */ MCD_OPC_FilterValue, 1, 252, 3, // Skip to: 2221
337 /* 1201 */ MCD_OPC_Decode, 234, 1, 30, // Opcode: STDW_d7_pm
338 /* 1205 */ MCD_OPC_FilterValue, 18, 17, 0, // Skip to: 1226
339 /* 1209 */ MCD_OPC_ExtractField, 7, 1, // Inst{7} ...
340 /* 1212 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1219
341 /* 1216 */ MCD_OPC_Decode, 104, 4, // Opcode: EXT_s15_riir
342 /* 1219 */ MCD_OPC_FilterValue, 1, 230, 3, // Skip to: 2221
343 /* 1223 */ MCD_OPC_Decode, 72, 4, // Opcode: CLR_s15_riir
344 /* 1226 */ MCD_OPC_FilterValue, 19, 3, 0, // Skip to: 1233
345 /* 1230 */ MCD_OPC_Decode, 119, 5, // Opcode: LDH_d6_mr
346 /* 1233 */ MCD_OPC_FilterValue, 20, 3, 0, // Skip to: 1240
347 /* 1237 */ MCD_OPC_Decode, 38, 23, // Opcode: ADDK_s2_ir
348 /* 1240 */ MCD_OPC_FilterValue, 21, 19, 0, // Skip to: 1263
349 /* 1244 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ...
350 /* 1247 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1255
351 /* 1251 */ MCD_OPC_Decode, 235, 1, 3, // Opcode: STH_d5_rm
352 /* 1255 */ MCD_OPC_FilterValue, 1, 194, 3, // Skip to: 2221
353 /* 1259 */ MCD_OPC_Decode, 238, 1, 3, // Opcode: STNW_d5_rm
354 /* 1263 */ MCD_OPC_FilterValue, 22, 191, 0, // Skip to: 1458
355 /* 1267 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ...
356 /* 1270 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1277
357 /* 1274 */ MCD_OPC_Decode, 46, 2, // Opcode: ADD_l1_irr
358 /* 1277 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1285
359 /* 1281 */ MCD_OPC_Decode, 131, 2, 2, // Opcode: SUB_l1_irr
360 /* 1285 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 1293
361 /* 1289 */ MCD_OPC_Decode, 229, 1, 2, // Opcode: SSUB_l1_irr
362 /* 1293 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 1301
363 /* 1297 */ MCD_OPC_Decode, 187, 1, 2, // Opcode: SADD_l1_irr
364 /* 1301 */ MCD_OPC_FilterValue, 6, 49, 0, // Skip to: 1354
365 /* 1305 */ MCD_OPC_ExtractField, 13, 5, // Inst{17-13} ...
366 /* 1308 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1315
367 /* 1312 */ MCD_OPC_Decode, 24, 21, // Opcode: ABS_l1_rr
368 /* 1315 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 1323
369 /* 1319 */ MCD_OPC_Decode, 139, 2, 21, // Opcode: SWAP4_l2_rr
370 /* 1323 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 1331
371 /* 1327 */ MCD_OPC_Decode, 142, 2, 21, // Opcode: UNPKLU4_l2_rr
372 /* 1331 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 1339
373 /* 1335 */ MCD_OPC_Decode, 140, 2, 21, // Opcode: UNPKHU4_l2_rr
374 /* 1339 */ MCD_OPC_FilterValue, 4, 3, 0, // Skip to: 1346
375 /* 1343 */ MCD_OPC_Decode, 22, 21, // Opcode: ABS2_l2_rr
376 /* 1346 */ MCD_OPC_FilterValue, 5, 103, 3, // Skip to: 2221
377 /* 1350 */ MCD_OPC_Decode, 161, 1, 31, // Opcode: MVK_l2_ir
378 /* 1354 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 1362
379 /* 1358 */ MCD_OPC_Decode, 173, 1, 1, // Opcode: PACKH2_l1_rrr_x2
380 /* 1362 */ MCD_OPC_FilterValue, 16, 3, 0, // Skip to: 1369
381 /* 1366 */ MCD_OPC_Decode, 126, 1, // Opcode: MAX2_l1_rrr_x2
382 /* 1369 */ MCD_OPC_FilterValue, 17, 3, 0, // Skip to: 1376
383 /* 1373 */ MCD_OPC_Decode, 83, 2, // Opcode: CMPGT_l1_irr
384 /* 1376 */ MCD_OPC_FilterValue, 19, 3, 0, // Skip to: 1383
385 /* 1380 */ MCD_OPC_Decode, 107, 17, // Opcode: GMPGTU_l1_irr
386 /* 1383 */ MCD_OPC_FilterValue, 20, 3, 0, // Skip to: 1390
387 /* 1387 */ MCD_OPC_Decode, 77, 2, // Opcode: CMPEQ_l1_irr
388 /* 1390 */ MCD_OPC_FilterValue, 21, 3, 0, // Skip to: 1397
389 /* 1394 */ MCD_OPC_Decode, 91, 2, // Opcode: CMPLT_l1_irr
390 /* 1397 */ MCD_OPC_FilterValue, 22, 4, 0, // Skip to: 1405
391 /* 1401 */ MCD_OPC_Decode, 245, 1, 1, // Opcode: SUBABS4_l1_rrr_x2
392 /* 1405 */ MCD_OPC_FilterValue, 23, 3, 0, // Skip to: 1412
393 /* 1409 */ MCD_OPC_Decode, 87, 17, // Opcode: CMPLTU_l1_irr
394 /* 1412 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 1420
395 /* 1416 */ MCD_OPC_Decode, 205, 1, 1, // Opcode: SHRMB_l1_rrr_x2
396 /* 1420 */ MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 1428
397 /* 1424 */ MCD_OPC_Decode, 244, 1, 1, // Opcode: SUB4_l1_rrr_x2
398 /* 1428 */ MCD_OPC_FilterValue, 26, 3, 0, // Skip to: 1435
399 /* 1432 */ MCD_OPC_Decode, 124, 2, // Opcode: LMBD_l1_irr
400 /* 1435 */ MCD_OPC_FilterValue, 27, 4, 0, // Skip to: 1443
401 /* 1439 */ MCD_OPC_Decode, 146, 2, 2, // Opcode: XOR_l1_irr
402 /* 1443 */ MCD_OPC_FilterValue, 30, 3, 0, // Skip to: 1450
403 /* 1447 */ MCD_OPC_Decode, 57, 2, // Opcode: AND_l1_irr
404 /* 1450 */ MCD_OPC_FilterValue, 31, 255, 2, // Skip to: 2221
405 /* 1454 */ MCD_OPC_Decode, 167, 1, 2, // Opcode: OR_l1_irr
406 /* 1458 */ MCD_OPC_FilterValue, 23, 4, 0, // Skip to: 1466
407 /* 1462 */ MCD_OPC_Decode, 236, 1, 5, // Opcode: STH_d6_rm
408 /* 1466 */ MCD_OPC_FilterValue, 24, 6, 1, // Skip to: 1732
409 /* 1470 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ...
410 /* 1473 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1480
411 /* 1477 */ MCD_OPC_Decode, 27, 1, // Opcode: ADD2_s1_rrr
412 /* 1480 */ MCD_OPC_FilterValue, 1, 19, 0, // Skip to: 1503
413 /* 1484 */ MCD_OPC_ExtractField, 12, 16, // Inst{27-12} ...
414 /* 1487 */ MCD_OPC_FilterValue, 128, 3, 3, 0, // Skip to: 1495
415 /* 1492 */ MCD_OPC_Decode, 70, 32, // Opcode: B_s7_irp
416 /* 1495 */ MCD_OPC_FilterValue, 192, 3, 209, 2, // Skip to: 2221
417 /* 1500 */ MCD_OPC_Decode, 71, 32, // Opcode: B_s7_nrp
418 /* 1503 */ MCD_OPC_FilterValue, 2, 9, 0, // Skip to: 1516
419 /* 1507 */ MCD_OPC_CheckField, 12, 1, 0, 196, 2, // Skip to: 2221
420 /* 1513 */ MCD_OPC_Decode, 37, 33, // Opcode: ADDKPC_s3_iir
421 /* 1516 */ MCD_OPC_FilterValue, 3, 3, 0, // Skip to: 1523
422 /* 1520 */ MCD_OPC_Decode, 51, 1, // Opcode: ADD_s1_rrr
423 /* 1523 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 1531
424 /* 1527 */ MCD_OPC_Decode, 174, 1, 1, // Opcode: PACKH2_s1_rrr
425 /* 1531 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 1539
426 /* 1535 */ MCD_OPC_Decode, 149, 2, 1, // Opcode: XOR_s1_rrr
427 /* 1539 */ MCD_OPC_FilterValue, 6, 29, 0, // Skip to: 1572
428 /* 1543 */ MCD_OPC_ExtractField, 23, 5, // Inst{27-23} ...
429 /* 1546 */ MCD_OPC_FilterValue, 0, 9, 0, // Skip to: 1559
430 /* 1550 */ MCD_OPC_CheckField, 13, 5, 0, 153, 2, // Skip to: 2221
431 /* 1556 */ MCD_OPC_Decode, 69, 34, // Opcode: B_s6_r
432 /* 1559 */ MCD_OPC_FilterValue, 1, 146, 2, // Skip to: 2221
433 /* 1563 */ MCD_OPC_CheckField, 16, 2, 0, 140, 2, // Skip to: 2221
434 /* 1569 */ MCD_OPC_Decode, 65, 35, // Opcode: BNOP_s10_ri
435 /* 1572 */ MCD_OPC_FilterValue, 7, 10, 0, // Skip to: 1586
436 /* 1576 */ MCD_OPC_CheckField, 13, 5, 0, 127, 2, // Skip to: 2221
437 /* 1582 */ MCD_OPC_Decode, 155, 1, 36, // Opcode: MVC_s1_rr
438 /* 1586 */ MCD_OPC_FilterValue, 8, 4, 0, // Skip to: 1594
439 /* 1590 */ MCD_OPC_Decode, 243, 1, 1, // Opcode: SUB2_s1_rrr
440 /* 1594 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 1602
441 /* 1598 */ MCD_OPC_Decode, 201, 1, 37, // Opcode: SHL_s1_rrp
442 /* 1602 */ MCD_OPC_FilterValue, 10, 3, 0, // Skip to: 1609
443 /* 1606 */ MCD_OPC_Decode, 81, 1, // Opcode: CMPGTU4_s1_rrr
444 /* 1609 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 1617
445 /* 1613 */ MCD_OPC_Decode, 137, 2, 1, // Opcode: SUB_s1_rrr
446 /* 1617 */ MCD_OPC_FilterValue, 12, 4, 0, // Skip to: 1625
447 /* 1621 */ MCD_OPC_Decode, 207, 1, 17, // Opcode: SHRU2_s1_rir
448 /* 1625 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 1633
449 /* 1629 */ MCD_OPC_Decode, 170, 1, 1, // Opcode: OR_s1_rrr
450 /* 1633 */ MCD_OPC_FilterValue, 14, 3, 0, // Skip to: 1640
451 /* 1637 */ MCD_OPC_Decode, 74, 1, // Opcode: CMPEQ2_s1_rrr
452 /* 1640 */ MCD_OPC_FilterValue, 15, 3, 0, // Skip to: 1647
453 /* 1644 */ MCD_OPC_Decode, 60, 1, // Opcode: AND_s1_rrr
454 /* 1647 */ MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 1655
455 /* 1651 */ MCD_OPC_Decode, 225, 1, 1, // Opcode: SSHL_s1_rrr
456 /* 1655 */ MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 1663
457 /* 1659 */ MCD_OPC_Decode, 210, 1, 38, // Opcode: SHRU_s1_prp
458 /* 1663 */ MCD_OPC_FilterValue, 19, 4, 0, // Skip to: 1671
459 /* 1667 */ MCD_OPC_Decode, 212, 1, 1, // Opcode: SHRU_s1_rrr
460 /* 1671 */ MCD_OPC_FilterValue, 21, 3, 0, // Skip to: 1678
461 /* 1675 */ MCD_OPC_Decode, 103, 1, // Opcode: EXTU_s1_rrr
462 /* 1678 */ MCD_OPC_FilterValue, 23, 3, 0, // Skip to: 1685
463 /* 1682 */ MCD_OPC_Decode, 105, 1, // Opcode: EXT_s1_rrr
464 /* 1685 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 1693
465 /* 1689 */ MCD_OPC_Decode, 198, 1, 25, // Opcode: SHL_s1_prp
466 /* 1693 */ MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 1701
467 /* 1697 */ MCD_OPC_Decode, 202, 1, 39, // Opcode: SHL_s1_rrr
468 /* 1701 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 1709
469 /* 1705 */ MCD_OPC_Decode, 214, 1, 38, // Opcode: SHR_s1_prp
470 /* 1709 */ MCD_OPC_FilterValue, 27, 4, 0, // Skip to: 1717
471 /* 1713 */ MCD_OPC_Decode, 216, 1, 1, // Opcode: SHR_s1_rrr
472 /* 1717 */ MCD_OPC_FilterValue, 29, 4, 0, // Skip to: 1725
473 /* 1721 */ MCD_OPC_Decode, 193, 1, 1, // Opcode: SET_s1_rrr
474 /* 1725 */ MCD_OPC_FilterValue, 31, 236, 1, // Skip to: 2221
475 /* 1729 */ MCD_OPC_Decode, 73, 1, // Opcode: CLR_s1_rrr
476 /* 1732 */ MCD_OPC_FilterValue, 25, 17, 0, // Skip to: 1753
477 /* 1736 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ...
478 /* 1739 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 1746
479 /* 1743 */ MCD_OPC_Decode, 122, 3, // Opcode: LDW_d5_mr
480 /* 1746 */ MCD_OPC_FilterValue, 1, 215, 1, // Skip to: 2221
481 /* 1750 */ MCD_OPC_Decode, 115, 30, // Opcode: LDDW_d7_mp
482 /* 1753 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 1761
483 /* 1757 */ MCD_OPC_Decode, 158, 1, 23, // Opcode: MVKLH_s12_ir
484 /* 1761 */ MCD_OPC_FilterValue, 27, 3, 0, // Skip to: 1768
485 /* 1765 */ MCD_OPC_Decode, 123, 5, // Opcode: LDW_d6_mr
486 /* 1768 */ MCD_OPC_FilterValue, 28, 216, 0, // Skip to: 1988
487 /* 1772 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ...
488 /* 1775 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 1783
489 /* 1779 */ MCD_OPC_Decode, 217, 1, 24, // Opcode: SMPY2_m1_rrp
490 /* 1783 */ MCD_OPC_FilterValue, 1, 49, 0, // Skip to: 1836
491 /* 1787 */ MCD_OPC_ExtractField, 13, 5, // Inst{17-13} ...
492 /* 1790 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 1798
493 /* 1794 */ MCD_OPC_Decode, 151, 2, 21, // Opcode: XPND4_m2_rr
494 /* 1798 */ MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 1806
495 /* 1802 */ MCD_OPC_Decode, 150, 2, 21, // Opcode: XPND2_m2_rr
496 /* 1806 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 1814
497 /* 1810 */ MCD_OPC_Decode, 157, 1, 21, // Opcode: MVD_m2_rr
498 /* 1814 */ MCD_OPC_FilterValue, 28, 4, 0, // Skip to: 1822
499 /* 1818 */ MCD_OPC_Decode, 194, 1, 21, // Opcode: SHFL_m2_rr
500 /* 1822 */ MCD_OPC_FilterValue, 29, 3, 0, // Skip to: 1829
501 /* 1826 */ MCD_OPC_Decode, 94, 21, // Opcode: DEAL_m2_rr
502 /* 1829 */ MCD_OPC_FilterValue, 30, 132, 1, // Skip to: 2221
503 /* 1833 */ MCD_OPC_Decode, 64, 21, // Opcode: BITC4_m2_rr
504 /* 1836 */ MCD_OPC_FilterValue, 2, 4, 0, // Skip to: 1844
505 /* 1840 */ MCD_OPC_Decode, 147, 1, 24, // Opcode: MPYSU4_m1_rrp
506 /* 1844 */ MCD_OPC_FilterValue, 3, 3, 0, // Skip to: 1851
507 /* 1848 */ MCD_OPC_Decode, 98, 1, // Opcode: DOTPNRSU2_m1_rrr
508 /* 1851 */ MCD_OPC_FilterValue, 4, 3, 0, // Skip to: 1858
509 /* 1855 */ MCD_OPC_Decode, 97, 1, // Opcode: DOTPN2_m1_rrr
510 /* 1858 */ MCD_OPC_FilterValue, 5, 3, 0, // Skip to: 1865
511 /* 1862 */ MCD_OPC_Decode, 95, 24, // Opcode: DOTP2_m1_rrp
512 /* 1865 */ MCD_OPC_FilterValue, 6, 3, 0, // Skip to: 1872
513 /* 1869 */ MCD_OPC_Decode, 99, 1, // Opcode: DOTPRSU2_m1_rrr
514 /* 1872 */ MCD_OPC_FilterValue, 8, 3, 0, // Skip to: 1879
515 /* 1876 */ MCD_OPC_Decode, 110, 1, // Opcode: GMPY4_m1_rrr
516 /* 1879 */ MCD_OPC_FilterValue, 9, 3, 0, // Skip to: 1886
517 /* 1883 */ MCD_OPC_Decode, 61, 1, // Opcode: AVG2_m1_rrr
518 /* 1886 */ MCD_OPC_FilterValue, 10, 4, 0, // Skip to: 1894
519 /* 1890 */ MCD_OPC_Decode, 144, 1, 24, // Opcode: MPYLI_m1_rrp
520 /* 1894 */ MCD_OPC_FilterValue, 14, 4, 0, // Skip to: 1902
521 /* 1898 */ MCD_OPC_Decode, 182, 1, 1, // Opcode: ROTL_m1_rrr
522 /* 1902 */ MCD_OPC_FilterValue, 17, 4, 0, // Skip to: 1910
523 /* 1906 */ MCD_OPC_Decode, 165, 1, 2, // Opcode: OR_d2_rir
524 /* 1910 */ MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 1918
525 /* 1914 */ MCD_OPC_Decode, 241, 1, 1, // Opcode: SUB2_d2_rrr
526 /* 1918 */ MCD_OPC_FilterValue, 19, 3, 0, // Skip to: 1925
527 /* 1922 */ MCD_OPC_Decode, 55, 2, // Opcode: AND_d2_rir
528 /* 1925 */ MCD_OPC_FilterValue, 21, 3, 0, // Skip to: 1932
529 /* 1929 */ MCD_OPC_Decode, 43, 2, // Opcode: ADD_d2_rir
530 /* 1932 */ MCD_OPC_FilterValue, 23, 4, 0, // Skip to: 1940
531 /* 1936 */ MCD_OPC_Decode, 144, 2, 2, // Opcode: XOR_d2_rir
532 /* 1940 */ MCD_OPC_FilterValue, 24, 4, 0, // Skip to: 1948
533 /* 1944 */ MCD_OPC_Decode, 185, 1, 1, // Opcode: SADDUS2_s4_rrr
534 /* 1948 */ MCD_OPC_FilterValue, 25, 4, 0, // Skip to: 1956
535 /* 1952 */ MCD_OPC_Decode, 184, 1, 1, // Opcode: SADDU4_s4_rrr
536 /* 1956 */ MCD_OPC_FilterValue, 26, 4, 0, // Skip to: 1964
537 /* 1960 */ MCD_OPC_Decode, 138, 2, 1, // Opcode: SUB_s4_rrr
538 /* 1964 */ MCD_OPC_FilterValue, 27, 4, 0, // Skip to: 1972
539 /* 1968 */ MCD_OPC_Decode, 204, 1, 1, // Opcode: SHR2_s4_rrr
540 /* 1972 */ MCD_OPC_FilterValue, 28, 4, 0, // Skip to: 1980
541 /* 1976 */ MCD_OPC_Decode, 196, 1, 1, // Opcode: SHLMB_s4_rrr
542 /* 1980 */ MCD_OPC_FilterValue, 31, 237, 0, // Skip to: 2221
543 /* 1984 */ MCD_OPC_Decode, 172, 1, 1, // Opcode: PACK2_s4_rrr
544 /* 1988 */ MCD_OPC_FilterValue, 29, 19, 0, // Skip to: 2011
545 /* 1992 */ MCD_OPC_ExtractField, 8, 1, // Inst{8} ...
546 /* 1995 */ MCD_OPC_FilterValue, 0, 4, 0, // Skip to: 2003
547 /* 1999 */ MCD_OPC_Decode, 239, 1, 3, // Opcode: STW_d5_rm
548 /* 2003 */ MCD_OPC_FilterValue, 1, 214, 0, // Skip to: 2221
549 /* 2007 */ MCD_OPC_Decode, 237, 1, 22, // Opcode: STNDW_d8_pm
550 /* 2011 */ MCD_OPC_FilterValue, 30, 198, 0, // Skip to: 2213
551 /* 2015 */ MCD_OPC_ExtractField, 7, 5, // Inst{11-7} ...
552 /* 2018 */ MCD_OPC_FilterValue, 0, 3, 0, // Skip to: 2025
553 /* 2022 */ MCD_OPC_Decode, 49, 1, // Opcode: ADD_l1_rrr_x2
554 /* 2025 */ MCD_OPC_FilterValue, 1, 4, 0, // Skip to: 2033
555 /* 2029 */ MCD_OPC_Decode, 135, 2, 1, // Opcode: SUB_l1_rrr_x2
556 /* 2033 */ MCD_OPC_FilterValue, 3, 4, 0, // Skip to: 2041
557 /* 2037 */ MCD_OPC_Decode, 231, 1, 1, // Opcode: SSUB_l1_rrr_x2
558 /* 2041 */ MCD_OPC_FilterValue, 4, 4, 0, // Skip to: 2049
559 /* 2045 */ MCD_OPC_Decode, 189, 1, 1, // Opcode: SADD_l1_rrr_x2
560 /* 2049 */ MCD_OPC_FilterValue, 5, 4, 0, // Skip to: 2057
561 /* 2053 */ MCD_OPC_Decode, 134, 2, 39, // Opcode: SUB_l1_rrr_x1
562 /* 2057 */ MCD_OPC_FilterValue, 6, 4, 0, // Skip to: 2065
563 /* 2061 */ MCD_OPC_Decode, 179, 1, 1, // Opcode: PACKLH2_l1_rrr_x2
564 /* 2065 */ MCD_OPC_FilterValue, 7, 4, 0, // Skip to: 2073
565 /* 2069 */ MCD_OPC_Decode, 230, 1, 39, // Opcode: SSUB_l1_rrr_x1
566 /* 2073 */ MCD_OPC_FilterValue, 8, 3, 0, // Skip to: 2080
567 /* 2077 */ MCD_OPC_Decode, 48, 24, // Opcode: ADD_l1_rrp_x2
568 /* 2080 */ MCD_OPC_FilterValue, 9, 4, 0, // Skip to: 2088
569 /* 2084 */ MCD_OPC_Decode, 133, 2, 24, // Opcode: SUB_l1_rrp_x2
570 /* 2088 */ MCD_OPC_FilterValue, 10, 3, 0, // Skip to: 2095
571 /* 2092 */ MCD_OPC_Decode, 40, 24, // Opcode: ADDU_l1_rrp_x2
572 /* 2095 */ MCD_OPC_FilterValue, 11, 4, 0, // Skip to: 2103
573 /* 2099 */ MCD_OPC_Decode, 254, 1, 24, // Opcode: SUBU_l1_rrp_x2
574 /* 2103 */ MCD_OPC_FilterValue, 13, 4, 0, // Skip to: 2111
575 /* 2107 */ MCD_OPC_Decode, 132, 2, 37, // Opcode: SUB_l1_rrp_x1
576 /* 2111 */ MCD_OPC_FilterValue, 15, 4, 0, // Skip to: 2119
577 /* 2115 */ MCD_OPC_Decode, 253, 1, 37, // Opcode: SUBU_l1_rrp_x1
578 /* 2119 */ MCD_OPC_FilterValue, 16, 3, 0, // Skip to: 2126
579 /* 2123 */ MCD_OPC_Decode, 127, 1, // Opcode: MAXU4_l1_rrr_x2
580 /* 2126 */ MCD_OPC_FilterValue, 17, 3, 0, // Skip to: 2133
581 /* 2130 */ MCD_OPC_Decode, 85, 1, // Opcode: CMPGT_l1_rrr_x2
582 /* 2133 */ MCD_OPC_FilterValue, 18, 4, 0, // Skip to: 2141
583 /* 2137 */ MCD_OPC_Decode, 252, 1, 1, // Opcode: SUBC_l1_rrr_x2
584 /* 2141 */ MCD_OPC_FilterValue, 19, 3, 0, // Skip to: 2148
585 /* 2145 */ MCD_OPC_Decode, 109, 1, // Opcode: GMPGTU_l1_rrr_x2
586 /* 2148 */ MCD_OPC_FilterValue, 20, 3, 0, // Skip to: 2155
587 /* 2152 */ MCD_OPC_Decode, 79, 1, // Opcode: CMPEQ_l1_rrr_x2
588 /* 2155 */ MCD_OPC_FilterValue, 21, 3, 0, // Skip to: 2162
589 /* 2159 */ MCD_OPC_Decode, 93, 1, // Opcode: CMPLT_l1_rrr_x2
590 /* 2162 */ MCD_OPC_FilterValue, 23, 3, 0, // Skip to: 2169
591 /* 2166 */ MCD_OPC_Decode, 89, 1, // Opcode: CMPLTU_l1_rrr_x2
592 /* 2169 */ MCD_OPC_FilterValue, 24, 10, 0, // Skip to: 2183
593 /* 2173 */ MCD_OPC_CheckField, 13, 5, 0, 42, 0, // Skip to: 2221
594 /* 2179 */ MCD_OPC_Decode, 164, 1, 21, // Opcode: NORM_l1_rr
595 /* 2183 */ MCD_OPC_FilterValue, 26, 3, 0, // Skip to: 2190
596 /* 2187 */ MCD_OPC_Decode, 125, 1, // Opcode: LMBD_l1_rrr_x2
597 /* 2190 */ MCD_OPC_FilterValue, 27, 4, 0, // Skip to: 2198
598 /* 2194 */ MCD_OPC_Decode, 147, 2, 1, // Opcode: XOR_l1_rrr_x2
599 /* 2198 */ MCD_OPC_FilterValue, 30, 3, 0, // Skip to: 2205
600 /* 2202 */ MCD_OPC_Decode, 58, 1, // Opcode: AND_l1_rrr_x2
601 /* 2205 */ MCD_OPC_FilterValue, 31, 12, 0, // Skip to: 2221
602 /* 2209 */ MCD_OPC_Decode, 168, 1, 1, // Opcode: OR_l1_rrr_x2
603 /* 2213 */ MCD_OPC_FilterValue, 31, 4, 0, // Skip to: 2221
604 /* 2217 */ MCD_OPC_Decode, 240, 1, 5, // Opcode: STW_d6_rm
605 /* 2221 */ MCD_OPC_Fail,
606  0
607 };
608 
609 static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) {
610  return true;
611 }
612 
613 #define DecodeToMCInst(fname,fieldname, InsnType) \
614 static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \
615  uint64_t Address, void *Decoder) { \
616  InsnType tmp; \
617  switch (Idx) { \
618  default: \
619  case 0: \
620  tmp = fieldname(insn, 13, 4); \
621  if (DecodeNop(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
622  tmp = fieldname(insn, 29, 3); \
623  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
624  tmp = fieldname(insn, 28, 1); \
625  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
626  tmp = fieldname(insn, 1, 1); \
627  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
628  tmp = fieldname(insn, 0, 1); \
629  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
630  return S; \
631  case 1: \
632  tmp = fieldname(insn, 23, 5); \
633  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
634  tmp = fieldname(insn, 18, 5); \
635  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
636  tmp = fieldname(insn, 13, 5); \
637  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
638  tmp = fieldname(insn, 12, 1); \
639  if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
640  tmp = fieldname(insn, 29, 3); \
641  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
642  tmp = fieldname(insn, 28, 1); \
643  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
644  tmp = fieldname(insn, 1, 1); \
645  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
646  tmp = fieldname(insn, 0, 1); \
647  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
648  return S; \
649  case 2: \
650  tmp = fieldname(insn, 23, 5); \
651  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
652  tmp = fieldname(insn, 18, 5); \
653  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
654  tmp = fieldname(insn, 13, 5); \
655  if (DecodeScst5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
656  tmp = fieldname(insn, 12, 1); \
657  if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
658  tmp = fieldname(insn, 29, 3); \
659  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
660  tmp = fieldname(insn, 28, 1); \
661  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
662  tmp = fieldname(insn, 1, 1); \
663  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
664  tmp = fieldname(insn, 0, 1); \
665  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
666  return S; \
667  case 3: \
668  tmp = fieldname(insn, 23, 5); \
669  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
670  tmp = 0; \
671  tmp |= fieldname(insn, 7, 1) << 0; \
672  tmp |= fieldname(insn, 9, 14) << 1; \
673  if (DecodeMemOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
674  tmp = fieldname(insn, 29, 3); \
675  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
676  tmp = fieldname(insn, 28, 1); \
677  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
678  tmp = fieldname(insn, 1, 1); \
679  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
680  tmp = fieldname(insn, 0, 1); \
681  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
682  return S; \
683  case 4: \
684  tmp = fieldname(insn, 23, 5); \
685  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
686  tmp = fieldname(insn, 18, 5); \
687  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
688  tmp = fieldname(insn, 13, 5); \
689  MCOperand_CreateImm0(MI, tmp); \
690  tmp = fieldname(insn, 8, 5); \
691  MCOperand_CreateImm0(MI, tmp); \
692  tmp = fieldname(insn, 29, 3); \
693  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
694  tmp = fieldname(insn, 28, 1); \
695  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
696  tmp = fieldname(insn, 1, 1); \
697  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
698  tmp = fieldname(insn, 0, 1); \
699  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
700  return S; \
701  case 5: \
702  tmp = fieldname(insn, 23, 5); \
703  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
704  tmp = fieldname(insn, 7, 16); \
705  if (DecodeMemOperand2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
706  tmp = fieldname(insn, 29, 3); \
707  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
708  tmp = fieldname(insn, 28, 1); \
709  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
710  tmp = fieldname(insn, 1, 1); \
711  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
712  tmp = fieldname(insn, 0, 1); \
713  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
714  return S; \
715  case 6: \
716  tmp = fieldname(insn, 7, 21); \
717  if (DecodePCRelScst21(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
718  tmp = fieldname(insn, 29, 3); \
719  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
720  tmp = fieldname(insn, 28, 1); \
721  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
722  tmp = fieldname(insn, 1, 1); \
723  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
724  tmp = fieldname(insn, 0, 1); \
725  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
726  return S; \
727  case 7: \
728  tmp = fieldname(insn, 23, 5); \
729  if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
730  tmp = fieldname(insn, 18, 5); \
731  if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
732  tmp = fieldname(insn, 13, 5); \
733  if (DecodeScst5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
734  tmp = fieldname(insn, 12, 1); \
735  if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
736  tmp = fieldname(insn, 29, 3); \
737  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
738  tmp = fieldname(insn, 28, 1); \
739  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
740  tmp = fieldname(insn, 1, 1); \
741  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
742  tmp = fieldname(insn, 0, 1); \
743  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
744  return S; \
745  case 8: \
746  tmp = fieldname(insn, 23, 5); \
747  if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
748  tmp = fieldname(insn, 18, 5); \
749  if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
750  tmp = fieldname(insn, 12, 1); \
751  if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
752  tmp = fieldname(insn, 29, 3); \
753  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
754  tmp = fieldname(insn, 28, 1); \
755  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
756  tmp = fieldname(insn, 1, 1); \
757  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
758  tmp = fieldname(insn, 0, 1); \
759  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
760  return S; \
761  case 9: \
762  tmp = fieldname(insn, 23, 5); \
763  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
764  tmp = fieldname(insn, 18, 5); \
765  if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
766  tmp = fieldname(insn, 12, 1); \
767  if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
768  tmp = fieldname(insn, 29, 3); \
769  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
770  tmp = fieldname(insn, 28, 1); \
771  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
772  tmp = fieldname(insn, 1, 1); \
773  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
774  tmp = fieldname(insn, 0, 1); \
775  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
776  return S; \
777  case 10: \
778  tmp = fieldname(insn, 23, 5); \
779  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
780  tmp = fieldname(insn, 18, 5); \
781  if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
782  tmp = fieldname(insn, 13, 5); \
783  if (DecodeScst5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
784  tmp = fieldname(insn, 12, 1); \
785  if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
786  tmp = fieldname(insn, 29, 3); \
787  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
788  tmp = fieldname(insn, 28, 1); \
789  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
790  tmp = fieldname(insn, 1, 1); \
791  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
792  tmp = fieldname(insn, 0, 1); \
793  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
794  return S; \
795  case 11: \
796  tmp = fieldname(insn, 23, 5); \
797  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
798  tmp = fieldname(insn, 18, 5); \
799  if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
800  tmp = fieldname(insn, 13, 5); \
801  MCOperand_CreateImm0(MI, tmp); \
802  tmp = fieldname(insn, 12, 1); \
803  if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
804  tmp = fieldname(insn, 29, 3); \
805  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
806  tmp = fieldname(insn, 28, 1); \
807  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
808  tmp = fieldname(insn, 1, 1); \
809  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
810  tmp = fieldname(insn, 0, 1); \
811  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
812  return S; \
813  case 12: \
814  tmp = fieldname(insn, 23, 5); \
815  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
816  tmp = fieldname(insn, 18, 5); \
817  if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
818  tmp = fieldname(insn, 12, 1); \
819  if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
820  tmp = fieldname(insn, 29, 3); \
821  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
822  tmp = fieldname(insn, 28, 1); \
823  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
824  tmp = fieldname(insn, 1, 1); \
825  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
826  tmp = fieldname(insn, 0, 1); \
827  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
828  return S; \
829  case 13: \
830  tmp = fieldname(insn, 23, 5); \
831  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
832  tmp = fieldname(insn, 13, 10); \
833  if (DecodePCRelScst10(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
834  tmp = fieldname(insn, 29, 3); \
835  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
836  tmp = fieldname(insn, 28, 1); \
837  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
838  tmp = fieldname(insn, 1, 1); \
839  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
840  tmp = fieldname(insn, 0, 1); \
841  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
842  return S; \
843  case 14: \
844  tmp = fieldname(insn, 16, 12); \
845  if (DecodePCRelScst12(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
846  tmp = fieldname(insn, 13, 3); \
847  MCOperand_CreateImm0(MI, tmp); \
848  tmp = fieldname(insn, 29, 3); \
849  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
850  tmp = fieldname(insn, 28, 1); \
851  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
852  tmp = fieldname(insn, 1, 1); \
853  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
854  tmp = fieldname(insn, 0, 1); \
855  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
856  return S; \
857  case 15: \
858  tmp = fieldname(insn, 23, 5); \
859  if (DecodeControlRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
860  tmp = fieldname(insn, 18, 5); \
861  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
862  tmp = fieldname(insn, 12, 1); \
863  if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
864  tmp = fieldname(insn, 29, 3); \
865  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
866  tmp = fieldname(insn, 28, 1); \
867  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
868  tmp = fieldname(insn, 1, 1); \
869  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
870  tmp = fieldname(insn, 0, 1); \
871  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
872  return S; \
873  case 16: \
874  tmp = fieldname(insn, 23, 5); \
875  if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
876  tmp = fieldname(insn, 18, 5); \
877  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
878  tmp = fieldname(insn, 13, 5); \
879  MCOperand_CreateImm0(MI, tmp); \
880  tmp = fieldname(insn, 12, 1); \
881  if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
882  tmp = fieldname(insn, 29, 3); \
883  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
884  tmp = fieldname(insn, 28, 1); \
885  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
886  tmp = fieldname(insn, 1, 1); \
887  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
888  tmp = fieldname(insn, 0, 1); \
889  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
890  return S; \
891  case 17: \
892  tmp = fieldname(insn, 23, 5); \
893  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
894  tmp = fieldname(insn, 18, 5); \
895  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
896  tmp = fieldname(insn, 13, 5); \
897  MCOperand_CreateImm0(MI, tmp); \
898  tmp = fieldname(insn, 12, 1); \
899  if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
900  tmp = fieldname(insn, 29, 3); \
901  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
902  tmp = fieldname(insn, 28, 1); \
903  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
904  tmp = fieldname(insn, 1, 1); \
905  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
906  tmp = fieldname(insn, 0, 1); \
907  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
908  return S; \
909  case 18: \
910  tmp = fieldname(insn, 23, 5); \
911  if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
912  tmp = fieldname(insn, 18, 5); \
913  if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
914  tmp = fieldname(insn, 13, 5); \
915  MCOperand_CreateImm0(MI, tmp); \
916  tmp = fieldname(insn, 12, 1); \
917  if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
918  tmp = fieldname(insn, 29, 3); \
919  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
920  tmp = fieldname(insn, 28, 1); \
921  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
922  tmp = fieldname(insn, 1, 1); \
923  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
924  tmp = fieldname(insn, 0, 1); \
925  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
926  return S; \
927  case 19: \
928  tmp = fieldname(insn, 23, 5); \
929  if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
930  tmp = fieldname(insn, 18, 5); \
931  if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
932  tmp = fieldname(insn, 13, 5); \
933  MCOperand_CreateImm0(MI, tmp); \
934  tmp = fieldname(insn, 12, 1); \
935  if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
936  tmp = fieldname(insn, 29, 3); \
937  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
938  tmp = fieldname(insn, 28, 1); \
939  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
940  tmp = fieldname(insn, 1, 1); \
941  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
942  tmp = fieldname(insn, 0, 1); \
943  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
944  return S; \
945  case 20: \
946  tmp = fieldname(insn, 23, 5); \
947  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
948  tmp = fieldname(insn, 18, 5); \
949  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
950  tmp = fieldname(insn, 13, 5); \
951  MCOperand_CreateImm0(MI, tmp); \
952  tmp = fieldname(insn, 12, 1); \
953  if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
954  tmp = fieldname(insn, 29, 3); \
955  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
956  tmp = fieldname(insn, 28, 1); \
957  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
958  tmp = fieldname(insn, 1, 1); \
959  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
960  tmp = fieldname(insn, 0, 1); \
961  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
962  return S; \
963  case 21: \
964  tmp = fieldname(insn, 23, 5); \
965  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
966  tmp = fieldname(insn, 18, 5); \
967  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
968  tmp = fieldname(insn, 12, 1); \
969  if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
970  tmp = fieldname(insn, 29, 3); \
971  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
972  tmp = fieldname(insn, 28, 1); \
973  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
974  tmp = fieldname(insn, 1, 1); \
975  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
976  tmp = fieldname(insn, 0, 1); \
977  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
978  return S; \
979  case 22: \
980  tmp = fieldname(insn, 24, 4); \
981  if (DecodeRegPair4(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
982  tmp = 0; \
983  tmp |= fieldname(insn, 7, 1) << 0; \
984  tmp |= fieldname(insn, 9, 15) << 1; \
985  if (DecodeMemOperandSc(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
986  tmp = fieldname(insn, 29, 3); \
987  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
988  tmp = fieldname(insn, 28, 1); \
989  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
990  tmp = fieldname(insn, 1, 1); \
991  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
992  tmp = fieldname(insn, 0, 1); \
993  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
994  return S; \
995  case 23: \
996  tmp = fieldname(insn, 23, 5); \
997  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
998  tmp = fieldname(insn, 7, 16); \
999  if (DecodeScst16(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1000  tmp = fieldname(insn, 29, 3); \
1001  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1002  tmp = fieldname(insn, 28, 1); \
1003  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1004  tmp = fieldname(insn, 1, 1); \
1005  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1006  tmp = fieldname(insn, 0, 1); \
1007  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1008  return S; \
1009  case 24: \
1010  tmp = fieldname(insn, 23, 5); \
1011  if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1012  tmp = fieldname(insn, 18, 5); \
1013  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1014  tmp = fieldname(insn, 13, 5); \
1015  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1016  tmp = fieldname(insn, 12, 1); \
1017  if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1018  tmp = fieldname(insn, 29, 3); \
1019  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1020  tmp = fieldname(insn, 28, 1); \
1021  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1022  tmp = fieldname(insn, 1, 1); \
1023  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1024  tmp = fieldname(insn, 0, 1); \
1025  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1026  return S; \
1027  case 25: \
1028  tmp = fieldname(insn, 23, 5); \
1029  if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1030  tmp = fieldname(insn, 18, 5); \
1031  if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1032  tmp = fieldname(insn, 13, 5); \
1033  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1034  tmp = fieldname(insn, 12, 1); \
1035  if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1036  tmp = fieldname(insn, 29, 3); \
1037  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1038  tmp = fieldname(insn, 28, 1); \
1039  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1040  tmp = fieldname(insn, 1, 1); \
1041  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1042  tmp = fieldname(insn, 0, 1); \
1043  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1044  return S; \
1045  case 26: \
1046  tmp = fieldname(insn, 23, 5); \
1047  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1048  tmp = fieldname(insn, 18, 5); \
1049  if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1050  tmp = fieldname(insn, 13, 5); \
1051  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1052  tmp = fieldname(insn, 12, 1); \
1053  if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1054  tmp = fieldname(insn, 29, 3); \
1055  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1056  tmp = fieldname(insn, 28, 1); \
1057  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1058  tmp = fieldname(insn, 1, 1); \
1059  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1060  tmp = fieldname(insn, 0, 1); \
1061  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1062  return S; \
1063  case 27: \
1064  tmp = fieldname(insn, 23, 5); \
1065  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1066  tmp = fieldname(insn, 13, 5); \
1067  if (DecodeScst5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1068  tmp = fieldname(insn, 29, 3); \
1069  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1070  tmp = fieldname(insn, 28, 1); \
1071  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1072  tmp = fieldname(insn, 1, 1); \
1073  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1074  tmp = fieldname(insn, 0, 1); \
1075  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1076  return S; \
1077  case 28: \
1078  tmp = fieldname(insn, 23, 5); \
1079  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1080  tmp = fieldname(insn, 18, 5); \
1081  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1082  tmp = fieldname(insn, 13, 5); \
1083  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1084  tmp = fieldname(insn, 29, 3); \
1085  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1086  tmp = fieldname(insn, 28, 1); \
1087  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1088  tmp = fieldname(insn, 1, 1); \
1089  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1090  tmp = fieldname(insn, 0, 1); \
1091  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1092  return S; \
1093  case 29: \
1094  tmp = fieldname(insn, 23, 5); \
1095  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1096  tmp = fieldname(insn, 18, 5); \
1097  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1098  tmp = fieldname(insn, 13, 5); \
1099  MCOperand_CreateImm0(MI, tmp); \
1100  tmp = fieldname(insn, 29, 3); \
1101  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1102  tmp = fieldname(insn, 28, 1); \
1103  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1104  tmp = fieldname(insn, 1, 1); \
1105  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1106  tmp = fieldname(insn, 0, 1); \
1107  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1108  return S; \
1109  case 30: \
1110  tmp = fieldname(insn, 23, 5); \
1111  if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1112  tmp = 0; \
1113  tmp |= fieldname(insn, 7, 1) << 0; \
1114  tmp |= fieldname(insn, 9, 14) << 1; \
1115  if (DecodeMemOperand(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1116  tmp = fieldname(insn, 29, 3); \
1117  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1118  tmp = fieldname(insn, 28, 1); \
1119  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1120  tmp = fieldname(insn, 1, 1); \
1121  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1122  tmp = fieldname(insn, 0, 1); \
1123  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1124  return S; \
1125  case 31: \
1126  tmp = fieldname(insn, 23, 5); \
1127  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1128  tmp = fieldname(insn, 18, 5); \
1129  if (DecodeScst5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1130  tmp = fieldname(insn, 12, 1); \
1131  if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1132  tmp = fieldname(insn, 29, 3); \
1133  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1134  tmp = fieldname(insn, 28, 1); \
1135  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1136  tmp = fieldname(insn, 1, 1); \
1137  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1138  tmp = fieldname(insn, 0, 1); \
1139  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1140  return S; \
1141  case 32: \
1142  tmp = fieldname(insn, 29, 3); \
1143  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1144  tmp = fieldname(insn, 28, 1); \
1145  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1146  tmp = fieldname(insn, 1, 1); \
1147  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1148  tmp = fieldname(insn, 0, 1); \
1149  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1150  return S; \
1151  case 33: \
1152  tmp = fieldname(insn, 23, 5); \
1153  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1154  tmp = fieldname(insn, 16, 7); \
1155  if (DecodePCRelScst7(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1156  tmp = fieldname(insn, 13, 3); \
1157  MCOperand_CreateImm0(MI, tmp); \
1158  tmp = fieldname(insn, 29, 3); \
1159  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1160  tmp = fieldname(insn, 28, 1); \
1161  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1162  tmp = fieldname(insn, 1, 1); \
1163  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1164  tmp = fieldname(insn, 0, 1); \
1165  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1166  return S; \
1167  case 34: \
1168  tmp = fieldname(insn, 18, 5); \
1169  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1170  tmp = fieldname(insn, 12, 1); \
1171  if (DecodeCrosspathX1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1172  tmp = fieldname(insn, 29, 3); \
1173  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1174  tmp = fieldname(insn, 28, 1); \
1175  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1176  tmp = fieldname(insn, 1, 1); \
1177  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1178  tmp = fieldname(insn, 0, 1); \
1179  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1180  return S; \
1181  case 35: \
1182  tmp = fieldname(insn, 18, 5); \
1183  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1184  tmp = fieldname(insn, 13, 3); \
1185  MCOperand_CreateImm0(MI, tmp); \
1186  tmp = fieldname(insn, 12, 1); \
1187  if (DecodeCrosspathX1(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1188  tmp = fieldname(insn, 29, 3); \
1189  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1190  tmp = fieldname(insn, 28, 1); \
1191  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1192  tmp = fieldname(insn, 1, 1); \
1193  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1194  tmp = fieldname(insn, 0, 1); \
1195  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1196  return S; \
1197  case 36: \
1198  tmp = fieldname(insn, 23, 5); \
1199  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1200  tmp = fieldname(insn, 18, 5); \
1201  if (DecodeControlRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1202  tmp = fieldname(insn, 12, 1); \
1203  if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1204  tmp = fieldname(insn, 29, 3); \
1205  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1206  tmp = fieldname(insn, 28, 1); \
1207  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1208  tmp = fieldname(insn, 1, 1); \
1209  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1210  tmp = fieldname(insn, 0, 1); \
1211  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1212  return S; \
1213  case 37: \
1214  tmp = fieldname(insn, 23, 5); \
1215  if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1216  tmp = fieldname(insn, 18, 5); \
1217  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1218  tmp = fieldname(insn, 13, 5); \
1219  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1220  tmp = fieldname(insn, 12, 1); \
1221  if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1222  tmp = fieldname(insn, 29, 3); \
1223  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1224  tmp = fieldname(insn, 28, 1); \
1225  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1226  tmp = fieldname(insn, 1, 1); \
1227  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1228  tmp = fieldname(insn, 0, 1); \
1229  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1230  return S; \
1231  case 38: \
1232  tmp = fieldname(insn, 23, 5); \
1233  if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1234  tmp = fieldname(insn, 18, 5); \
1235  if (DecodeRegPair5(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1236  tmp = fieldname(insn, 13, 5); \
1237  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1238  tmp = fieldname(insn, 12, 1); \
1239  if (DecodeCrosspathX2(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1240  tmp = fieldname(insn, 29, 3); \
1241  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1242  tmp = fieldname(insn, 28, 1); \
1243  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1244  tmp = fieldname(insn, 1, 1); \
1245  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1246  tmp = fieldname(insn, 0, 1); \
1247  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1248  return S; \
1249  case 39: \
1250  tmp = fieldname(insn, 23, 5); \
1251  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1252  tmp = fieldname(insn, 18, 5); \
1253  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1254  tmp = fieldname(insn, 13, 5); \
1255  if (DecodeGPRegsRegisterClass(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1256  tmp = fieldname(insn, 12, 1); \
1257  if (DecodeCrosspathX3(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1258  tmp = fieldname(insn, 29, 3); \
1259  if (DecodeCondRegister(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1260  tmp = fieldname(insn, 28, 1); \
1261  if (DecodeCondRegisterZero(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1262  tmp = fieldname(insn, 1, 1); \
1263  if (DecodeSide(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1264  tmp = fieldname(insn, 0, 1); \
1265  if (DecodeParallel(MI, tmp, Address, Decoder) == MCDisassembler_Fail) return MCDisassembler_Fail; \
1266  return S; \
1267  } \
1268 }
1269 
1270 #define DecodeInstruction(fname, fieldname, decoder, InsnType) \
1271 static DecodeStatus fname(uint8_t DecodeTable[], MCInst *MI, \
1272  InsnType insn, uint64_t Address, \
1273  MCRegisterInfo *MRI, \
1274  int feature) { \
1275  uint64_t Bits = getFeatureBits(feature); \
1276  uint8_t *Ptr = DecodeTable; \
1277  uint32_t CurFieldValue = 0, ExpectedValue; \
1278  DecodeStatus S = MCDisassembler_Success; \
1279  unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \
1280  InsnType Val, FieldValue, PositiveMask, NegativeMask; \
1281  bool Pred, Fail; \
1282  for (;;) { \
1283  switch (*Ptr) { \
1284  default: \
1285  return MCDisassembler_Fail; \
1286  case MCD_OPC_ExtractField: { \
1287  Start = *++Ptr; \
1288  Len = *++Ptr; \
1289  ++Ptr; \
1290  CurFieldValue = (uint32_t) fieldname(insn, Start, Len); \
1291  break; \
1292  } \
1293  case MCD_OPC_FilterValue: { \
1294  Val = (InsnType) decodeULEB128(++Ptr, &Len); \
1295  Ptr += Len; \
1296  NumToSkip = *Ptr++; \
1297  NumToSkip |= (*Ptr++) << 8; \
1298  if (Val != CurFieldValue) \
1299  Ptr += NumToSkip; \
1300  break; \
1301  } \
1302  case MCD_OPC_CheckField: { \
1303  Start = *++Ptr; \
1304  Len = *++Ptr; \
1305  FieldValue = fieldname(insn, Start, Len); \
1306  ExpectedValue = (uint32_t) decodeULEB128(++Ptr, &Len); \
1307  Ptr += Len; \
1308  NumToSkip = *Ptr++; \
1309  NumToSkip |= (*Ptr++) << 8; \
1310  if (ExpectedValue != FieldValue) \
1311  Ptr += NumToSkip; \
1312  break; \
1313  } \
1314  case MCD_OPC_CheckPredicate: { \
1315  PIdx = (uint32_t) decodeULEB128(++Ptr, &Len); \
1316  Ptr += Len; \
1317  NumToSkip = *Ptr++; \
1318  NumToSkip |= (*Ptr++) << 8; \
1319  Pred = checkDecoderPredicate(PIdx, Bits); \
1320  if (!Pred) \
1321  Ptr += NumToSkip; \
1322  (void)Pred; \
1323  break; \
1324  } \
1325  case MCD_OPC_Decode: { \
1326  Opc = (unsigned) decodeULEB128(++Ptr, &Len); \
1327  Ptr += Len; \
1328  DecodeIdx = (unsigned) decodeULEB128(Ptr, &Len); \
1329  Ptr += Len; \
1330  MCInst_setOpcode(MI, Opc); \
1331  return decoder(S, DecodeIdx, insn, MI, Address, MRI); \
1332  } \
1333  case MCD_OPC_SoftFail: { \
1334  PositiveMask = (InsnType) decodeULEB128(++Ptr, &Len); \
1335  Ptr += Len; \
1336  NegativeMask = (InsnType) decodeULEB128(Ptr, &Len); \
1337  Ptr += Len; \
1338  Fail = (insn & PositiveMask) || (~insn & NegativeMask); \
1339  if (Fail) \
1340  S = MCDisassembler_SoftFail; \
1341  break; \
1342  } \
1343  case MCD_OPC_Fail: { \
1344  return MCDisassembler_Fail; \
1345  } \
1346  } \
1347  } \
1348 }
1349 
1350 FieldFromInstruction(fieldFromInstruction_4, uint32_t)
1351 DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4, uint32_t)
1352 DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4, uint32_t)
MCD_OPC_ExtractField
@ MCD_OPC_ExtractField
Definition: MCFixedLenDisassembler.h:20
MCD_OPC_Decode
@ MCD_OPC_Decode
Definition: MCFixedLenDisassembler.h:25
MCD_OPC_Fail
@ MCD_OPC_Fail
Definition: MCFixedLenDisassembler.h:27
MCD_OPC_FilterValue
@ MCD_OPC_FilterValue
Definition: MCFixedLenDisassembler.h:21
MCD_OPC_CheckField
@ MCD_OPC_CheckField
Definition: MCFixedLenDisassembler.h:22
uint32_t
unsigned int uint32_t
Definition: sftypes.h:29
uint64_t
unsigned long uint64_t
Definition: sftypes.h:28
uint8_t
unsigned char uint8_t
Definition: sftypes.h:31