Rizin
unix-like reverse engineering framework and cli tools
SparcGenRegisterInfo.inc
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1 /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2 |* *|
3 |*Target Register Enum Values *|
4 |* *|
5 |* Automatically generated file, do not edit! *|
6 |* *|
7 \*===----------------------------------------------------------------------===*/
8 
9 /* Capstone Disassembly Engine */
10 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
11 
12 
13 #ifdef GET_REGINFO_ENUM
14 #undef GET_REGINFO_ENUM
15 
16 enum {
17  SP_NoRegister,
18  SP_ICC = 1,
19  SP_Y = 2,
20  SP_D0 = 3,
21  SP_D1 = 4,
22  SP_D2 = 5,
23  SP_D3 = 6,
24  SP_D4 = 7,
25  SP_D5 = 8,
26  SP_D6 = 9,
27  SP_D7 = 10,
28  SP_D8 = 11,
29  SP_D9 = 12,
30  SP_D10 = 13,
31  SP_D11 = 14,
32  SP_D12 = 15,
33  SP_D13 = 16,
34  SP_D14 = 17,
35  SP_D15 = 18,
36  SP_D16 = 19,
37  SP_D17 = 20,
38  SP_D18 = 21,
39  SP_D19 = 22,
40  SP_D20 = 23,
41  SP_D21 = 24,
42  SP_D22 = 25,
43  SP_D23 = 26,
44  SP_D24 = 27,
45  SP_D25 = 28,
46  SP_D26 = 29,
47  SP_D27 = 30,
48  SP_D28 = 31,
49  SP_D29 = 32,
50  SP_D30 = 33,
51  SP_D31 = 34,
52  SP_F0 = 35,
53  SP_F1 = 36,
54  SP_F2 = 37,
55  SP_F3 = 38,
56  SP_F4 = 39,
57  SP_F5 = 40,
58  SP_F6 = 41,
59  SP_F7 = 42,
60  SP_F8 = 43,
61  SP_F9 = 44,
62  SP_F10 = 45,
63  SP_F11 = 46,
64  SP_F12 = 47,
65  SP_F13 = 48,
66  SP_F14 = 49,
67  SP_F15 = 50,
68  SP_F16 = 51,
69  SP_F17 = 52,
70  SP_F18 = 53,
71  SP_F19 = 54,
72  SP_F20 = 55,
73  SP_F21 = 56,
74  SP_F22 = 57,
75  SP_F23 = 58,
76  SP_F24 = 59,
77  SP_F25 = 60,
78  SP_F26 = 61,
79  SP_F27 = 62,
80  SP_F28 = 63,
81  SP_F29 = 64,
82  SP_F30 = 65,
83  SP_F31 = 66,
84  SP_FCC0 = 67,
85  SP_FCC1 = 68,
86  SP_FCC2 = 69,
87  SP_FCC3 = 70,
88  SP_G0 = 71,
89  SP_G1 = 72,
90  SP_G2 = 73,
91  SP_G3 = 74,
92  SP_G4 = 75,
93  SP_G5 = 76,
94  SP_G6 = 77,
95  SP_G7 = 78,
96  SP_I0 = 79,
97  SP_I1 = 80,
98  SP_I2 = 81,
99  SP_I3 = 82,
100  SP_I4 = 83,
101  SP_I5 = 84,
102  SP_I6 = 85,
103  SP_I7 = 86,
104  SP_L0 = 87,
105  SP_L1 = 88,
106  SP_L2 = 89,
107  SP_L3 = 90,
108  SP_L4 = 91,
109  SP_L5 = 92,
110  SP_L6 = 93,
111  SP_L7 = 94,
112  SP_O0 = 95,
113  SP_O1 = 96,
114  SP_O2 = 97,
115  SP_O3 = 98,
116  SP_O4 = 99,
117  SP_O5 = 100,
118  SP_O6 = 101,
119  SP_O7 = 102,
120  SP_Q0 = 103,
121  SP_Q1 = 104,
122  SP_Q2 = 105,
123  SP_Q3 = 106,
124  SP_Q4 = 107,
125  SP_Q5 = 108,
126  SP_Q6 = 109,
127  SP_Q7 = 110,
128  SP_Q8 = 111,
129  SP_Q9 = 112,
130  SP_Q10 = 113,
131  SP_Q11 = 114,
132  SP_Q12 = 115,
133  SP_Q13 = 116,
134  SP_Q14 = 117,
135  SP_Q15 = 118,
136  SP_NUM_TARGET_REGS // 119
137 };
138 
139 // Register classes
140 enum {
141  SP_FCCRegsRegClassID = 0,
142  SP_FPRegsRegClassID = 1,
143  SP_IntRegsRegClassID = 2,
144  SP_DFPRegsRegClassID = 3,
145  SP_I64RegsRegClassID = 4,
146  SP_DFPRegs_with_sub_evenRegClassID = 5,
147  SP_QFPRegsRegClassID = 6,
148  SP_QFPRegs_with_sub_evenRegClassID = 7
149 };
150 
151 #endif // GET_REGINFO_ENUM
152 
153 /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
154 |* *|
155 |*MC Register Information *|
156 |* *|
157 |* Automatically generated file, do not edit! *|
158 |* *|
159 \*===----------------------------------------------------------------------===*/
160 
161 
162 #ifdef GET_REGINFO_MC_DESC
163 #undef GET_REGINFO_MC_DESC
164 
165 static const MCPhysReg SparcRegDiffLists[] = {
166  /* 0 */ 65126, 1, 1, 1, 0,
167  /* 5 */ 32, 1, 0,
168  /* 8 */ 65436, 32, 1, 65504, 33, 1, 0,
169  /* 15 */ 34, 1, 0,
170  /* 18 */ 65437, 34, 1, 65502, 35, 1, 0,
171  /* 25 */ 36, 1, 0,
172  /* 28 */ 65438, 36, 1, 65500, 37, 1, 0,
173  /* 35 */ 38, 1, 0,
174  /* 38 */ 65439, 38, 1, 65498, 39, 1, 0,
175  /* 45 */ 40, 1, 0,
176  /* 48 */ 65440, 40, 1, 65496, 41, 1, 0,
177  /* 55 */ 42, 1, 0,
178  /* 58 */ 65441, 42, 1, 65494, 43, 1, 0,
179  /* 65 */ 44, 1, 0,
180  /* 68 */ 65442, 44, 1, 65492, 45, 1, 0,
181  /* 75 */ 46, 1, 0,
182  /* 78 */ 65443, 46, 1, 65490, 47, 1, 0,
183  /* 85 */ 65348, 1, 0,
184  /* 88 */ 65444, 1, 0,
185  /* 91 */ 65445, 1, 0,
186  /* 94 */ 65446, 1, 0,
187  /* 97 */ 65447, 1, 0,
188  /* 100 */ 65448, 1, 0,
189  /* 103 */ 65449, 1, 0,
190  /* 106 */ 65450, 1, 0,
191  /* 109 */ 65451, 1, 0,
192  /* 112 */ 65532, 1, 0,
193  /* 115 */ 15, 0,
194  /* 117 */ 84, 0,
195  /* 119 */ 85, 0,
196  /* 121 */ 86, 0,
197  /* 123 */ 87, 0,
198  /* 125 */ 88, 0,
199  /* 127 */ 89, 0,
200  /* 129 */ 90, 0,
201  /* 131 */ 91, 0,
202  /* 133 */ 65488, 92, 0,
203  /* 136 */ 65489, 92, 0,
204  /* 139 */ 65489, 93, 0,
205  /* 142 */ 65490, 93, 0,
206  /* 145 */ 65491, 93, 0,
207  /* 148 */ 65491, 94, 0,
208  /* 151 */ 65492, 94, 0,
209  /* 154 */ 65493, 94, 0,
210  /* 157 */ 65493, 95, 0,
211  /* 160 */ 65494, 95, 0,
212  /* 163 */ 65495, 95, 0,
213  /* 166 */ 65495, 96, 0,
214  /* 169 */ 65496, 96, 0,
215  /* 172 */ 65497, 96, 0,
216  /* 175 */ 65497, 97, 0,
217  /* 178 */ 65498, 97, 0,
218  /* 181 */ 65499, 97, 0,
219  /* 184 */ 65499, 98, 0,
220  /* 187 */ 65500, 98, 0,
221  /* 190 */ 65501, 98, 0,
222  /* 193 */ 65501, 99, 0,
223  /* 196 */ 65502, 99, 0,
224  /* 199 */ 65503, 99, 0,
225  /* 202 */ 65503, 100, 0,
226  /* 205 */ 65504, 100, 0,
227  /* 208 */ 65503, 0,
228  /* 210 */ 65519, 0,
229  /* 212 */ 65535, 0,
230 };
231 
232 static const uint16_t SparcSubRegIdxLists[] = {
233  /* 0 */ 1, 3, 0,
234  /* 3 */ 2, 4, 0,
235  /* 6 */ 2, 1, 3, 4, 5, 6, 0,
236 };
237 
238 static MCRegisterDesc SparcRegDesc[] = { // Descriptors
239  { 3, 0, 0, 0, 0, 0 },
240  { 406, 4, 4, 2, 3393, 0 },
241  { 410, 4, 4, 2, 3393, 0 },
242  { 33, 5, 203, 0, 1794, 2 },
243  { 87, 12, 194, 0, 1794, 2 },
244  { 133, 15, 194, 0, 1794, 2 },
245  { 179, 22, 185, 0, 1794, 2 },
246  { 220, 25, 185, 0, 1794, 2 },
247  { 261, 32, 176, 0, 1794, 2 },
248  { 298, 35, 176, 0, 1794, 2 },
249  { 335, 42, 167, 0, 1794, 2 },
250  { 372, 45, 167, 0, 1794, 2 },
251  { 397, 52, 158, 0, 1794, 2 },
252  { 0, 55, 158, 0, 1794, 2 },
253  { 54, 62, 149, 0, 1794, 2 },
254  { 108, 65, 149, 0, 1794, 2 },
255  { 154, 72, 140, 0, 1794, 2 },
256  { 200, 75, 140, 0, 1794, 2 },
257  { 241, 82, 134, 0, 1794, 2 },
258  { 282, 4, 134, 2, 1841, 0 },
259  { 319, 4, 131, 2, 1841, 0 },
260  { 356, 4, 131, 2, 1841, 0 },
261  { 381, 4, 129, 2, 1841, 0 },
262  { 12, 4, 129, 2, 1841, 0 },
263  { 66, 4, 127, 2, 1841, 0 },
264  { 120, 4, 127, 2, 1841, 0 },
265  { 166, 4, 125, 2, 1841, 0 },
266  { 212, 4, 125, 2, 1841, 0 },
267  { 253, 4, 123, 2, 1841, 0 },
268  { 290, 4, 123, 2, 1841, 0 },
269  { 327, 4, 121, 2, 1841, 0 },
270  { 364, 4, 121, 2, 1841, 0 },
271  { 389, 4, 119, 2, 1841, 0 },
272  { 20, 4, 119, 2, 1841, 0 },
273  { 74, 4, 117, 2, 1841, 0 },
274  { 36, 4, 205, 2, 3329, 0 },
275  { 90, 4, 202, 2, 3329, 0 },
276  { 136, 4, 199, 2, 3329, 0 },
277  { 182, 4, 196, 2, 3329, 0 },
278  { 223, 4, 196, 2, 3329, 0 },
279  { 264, 4, 193, 2, 3329, 0 },
280  { 301, 4, 190, 2, 3329, 0 },
281  { 338, 4, 187, 2, 3329, 0 },
282  { 375, 4, 187, 2, 3329, 0 },
283  { 400, 4, 184, 2, 3329, 0 },
284  { 4, 4, 181, 2, 3329, 0 },
285  { 58, 4, 178, 2, 3329, 0 },
286  { 112, 4, 178, 2, 3329, 0 },
287  { 158, 4, 175, 2, 3329, 0 },
288  { 204, 4, 172, 2, 3329, 0 },
289  { 245, 4, 169, 2, 3329, 0 },
290  { 286, 4, 169, 2, 3329, 0 },
291  { 323, 4, 166, 2, 3329, 0 },
292  { 360, 4, 163, 2, 3329, 0 },
293  { 385, 4, 160, 2, 3329, 0 },
294  { 16, 4, 160, 2, 3329, 0 },
295  { 70, 4, 157, 2, 3329, 0 },
296  { 124, 4, 154, 2, 3329, 0 },
297  { 170, 4, 151, 2, 3329, 0 },
298  { 216, 4, 151, 2, 3329, 0 },
299  { 257, 4, 148, 2, 3329, 0 },
300  { 294, 4, 145, 2, 3329, 0 },
301  { 331, 4, 142, 2, 3329, 0 },
302  { 368, 4, 142, 2, 3329, 0 },
303  { 393, 4, 139, 2, 3329, 0 },
304  { 24, 4, 136, 2, 3329, 0 },
305  { 78, 4, 133, 2, 3329, 0 },
306  { 28, 4, 4, 2, 3361, 0 },
307  { 82, 4, 4, 2, 3361, 0 },
308  { 128, 4, 4, 2, 3361, 0 },
309  { 174, 4, 4, 2, 3361, 0 },
310  { 39, 4, 4, 2, 3361, 0 },
311  { 93, 4, 4, 2, 3361, 0 },
312  { 139, 4, 4, 2, 3361, 0 },
313  { 185, 4, 4, 2, 3361, 0 },
314  { 226, 4, 4, 2, 3361, 0 },
315  { 267, 4, 4, 2, 3361, 0 },
316  { 304, 4, 4, 2, 3361, 0 },
317  { 341, 4, 4, 2, 3361, 0 },
318  { 42, 4, 4, 2, 3361, 0 },
319  { 96, 4, 4, 2, 3361, 0 },
320  { 142, 4, 4, 2, 3361, 0 },
321  { 188, 4, 4, 2, 3361, 0 },
322  { 229, 4, 4, 2, 3361, 0 },
323  { 270, 4, 4, 2, 3361, 0 },
324  { 307, 4, 4, 2, 3361, 0 },
325  { 344, 4, 4, 2, 3361, 0 },
326  { 45, 4, 4, 2, 3361, 0 },
327  { 99, 4, 4, 2, 3361, 0 },
328  { 145, 4, 4, 2, 3361, 0 },
329  { 191, 4, 4, 2, 3361, 0 },
330  { 232, 4, 4, 2, 3361, 0 },
331  { 273, 4, 4, 2, 3361, 0 },
332  { 310, 4, 4, 2, 3361, 0 },
333  { 347, 4, 4, 2, 3361, 0 },
334  { 48, 4, 4, 2, 3361, 0 },
335  { 102, 4, 4, 2, 3361, 0 },
336  { 148, 4, 4, 2, 3361, 0 },
337  { 194, 4, 4, 2, 3361, 0 },
338  { 235, 4, 4, 2, 3361, 0 },
339  { 276, 4, 4, 2, 3361, 0 },
340  { 313, 4, 4, 2, 3361, 0 },
341  { 350, 4, 4, 2, 3361, 0 },
342  { 51, 8, 4, 6, 4, 5 },
343  { 105, 18, 4, 6, 4, 5 },
344  { 151, 28, 4, 6, 4, 5 },
345  { 197, 38, 4, 6, 4, 5 },
346  { 238, 48, 4, 6, 4, 5 },
347  { 279, 58, 4, 6, 4, 5 },
348  { 316, 68, 4, 6, 4, 5 },
349  { 353, 78, 4, 6, 4, 5 },
350  { 378, 88, 4, 3, 1362, 10 },
351  { 403, 91, 4, 3, 1362, 10 },
352  { 8, 94, 4, 3, 1362, 10 },
353  { 62, 97, 4, 3, 1362, 10 },
354  { 116, 100, 4, 3, 1362, 10 },
355  { 162, 103, 4, 3, 1362, 10 },
356  { 208, 106, 4, 3, 1362, 10 },
357  { 249, 109, 4, 3, 1362, 10 },
358 };
359 
360  // FCCRegs Register Class...
361  static const MCPhysReg FCCRegs[] = {
362  SP_FCC0, SP_FCC1, SP_FCC2, SP_FCC3,
363  };
364 
365  // FCCRegs Bit set.
366  static const uint8_t FCCRegsBits[] = {
367  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
368  };
369 
370  // FPRegs Register Class...
371  static const MCPhysReg FPRegs[] = {
372  SP_F0, SP_F1, SP_F2, SP_F3, SP_F4, SP_F5, SP_F6, SP_F7, SP_F8, SP_F9, SP_F10, SP_F11, SP_F12, SP_F13, SP_F14, SP_F15, SP_F16, SP_F17, SP_F18, SP_F19, SP_F20, SP_F21, SP_F22, SP_F23, SP_F24, SP_F25, SP_F26, SP_F27, SP_F28, SP_F29, SP_F30, SP_F31,
373  };
374 
375  // FPRegs Bit set.
376  static const uint8_t FPRegsBits[] = {
377  0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
378  };
379 
380  // IntRegs Register Class...
381  static const MCPhysReg IntRegs[] = {
382  SP_I0, SP_I1, SP_I2, SP_I3, SP_I4, SP_I5, SP_I6, SP_I7, SP_G0, SP_G1, SP_G2, SP_G3, SP_G4, SP_G5, SP_G6, SP_G7, SP_L0, SP_L1, SP_L2, SP_L3, SP_L4, SP_L5, SP_L6, SP_L7, SP_O0, SP_O1, SP_O2, SP_O3, SP_O4, SP_O5, SP_O6, SP_O7,
383  };
384 
385  // IntRegs Bit set.
386  static const uint8_t IntRegsBits[] = {
387  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
388  };
389 
390  // DFPRegs Register Class...
391  static const MCPhysReg DFPRegs[] = {
392  SP_D0, SP_D1, SP_D2, SP_D3, SP_D4, SP_D5, SP_D6, SP_D7, SP_D8, SP_D9, SP_D10, SP_D11, SP_D12, SP_D13, SP_D14, SP_D15, SP_D16, SP_D17, SP_D18, SP_D19, SP_D20, SP_D21, SP_D22, SP_D23, SP_D24, SP_D25, SP_D26, SP_D27, SP_D28, SP_D29, SP_D30, SP_D31,
393  };
394 
395  // DFPRegs Bit set.
396  static const uint8_t DFPRegsBits[] = {
397  0xf8, 0xff, 0xff, 0xff, 0x07,
398  };
399 
400  // I64Regs Register Class...
401  static const MCPhysReg I64Regs[] = {
402  SP_I0, SP_I1, SP_I2, SP_I3, SP_I4, SP_I5, SP_I6, SP_I7, SP_G0, SP_G1, SP_G2, SP_G3, SP_G4, SP_G5, SP_G6, SP_G7, SP_L0, SP_L1, SP_L2, SP_L3, SP_L4, SP_L5, SP_L6, SP_L7, SP_O0, SP_O1, SP_O2, SP_O3, SP_O4, SP_O5, SP_O6, SP_O7,
403  };
404 
405  // I64Regs Bit set.
406  static const uint8_t I64RegsBits[] = {
407  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x7f,
408  };
409 
410  // DFPRegs_with_sub_even Register Class...
411  static const MCPhysReg DFPRegs_with_sub_even[] = {
412  SP_D0, SP_D1, SP_D2, SP_D3, SP_D4, SP_D5, SP_D6, SP_D7, SP_D8, SP_D9, SP_D10, SP_D11, SP_D12, SP_D13, SP_D14, SP_D15,
413  };
414 
415  // DFPRegs_with_sub_even Bit set.
416  static const uint8_t DFPRegs_with_sub_evenBits[] = {
417  0xf8, 0xff, 0x07,
418  };
419 
420  // QFPRegs Register Class...
421  static const MCPhysReg QFPRegs[] = {
422  SP_Q0, SP_Q1, SP_Q2, SP_Q3, SP_Q4, SP_Q5, SP_Q6, SP_Q7, SP_Q8, SP_Q9, SP_Q10, SP_Q11, SP_Q12, SP_Q13, SP_Q14, SP_Q15,
423  };
424 
425  // QFPRegs Bit set.
426  static const uint8_t QFPRegsBits[] = {
427  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
428  };
429 
430  // QFPRegs_with_sub_even Register Class...
431  static const MCPhysReg QFPRegs_with_sub_even[] = {
432  SP_Q0, SP_Q1, SP_Q2, SP_Q3, SP_Q4, SP_Q5, SP_Q6, SP_Q7,
433  };
434 
435  // QFPRegs_with_sub_even Bit set.
436  static const uint8_t QFPRegs_with_sub_evenBits[] = {
437  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
438  };
439 
440 static MCRegisterClass SparcMCRegisterClasses[] = {
441  { FCCRegs, FCCRegsBits, 52, 4, sizeof(FCCRegsBits), SP_FCCRegsRegClassID, 0, 0, 1, 1 },
442  { FPRegs, FPRegsBits, 61, 32, sizeof(FPRegsBits), SP_FPRegsRegClassID, 4, 4, 1, 1 },
443  { IntRegs, IntRegsBits, 76, 32, sizeof(IntRegsBits), SP_IntRegsRegClassID, 4, 4, 1, 1 },
444  { DFPRegs, DFPRegsBits, 60, 32, sizeof(DFPRegsBits), SP_DFPRegsRegClassID, 8, 8, 1, 1 },
445  { I64Regs, I64RegsBits, 44, 32, sizeof(I64RegsBits), SP_I64RegsRegClassID, 8, 8, 1, 1 },
446  { DFPRegs_with_sub_even, DFPRegs_with_sub_evenBits, 0, 16, sizeof(DFPRegs_with_sub_evenBits), SP_DFPRegs_with_sub_evenRegClassID, 8, 8, 1, 1 },
447  { QFPRegs, QFPRegsBits, 68, 16, sizeof(QFPRegsBits), SP_QFPRegsRegClassID, 16, 16, 1, 1 },
448  { QFPRegs_with_sub_even, QFPRegs_with_sub_evenBits, 22, 8, sizeof(QFPRegs_with_sub_evenBits), SP_QFPRegs_with_sub_evenRegClassID, 16, 16, 1, 1 },
449 };
450 
451 #endif // GET_REGINFO_MC_DESC
MCPhysReg
uint16_t MCPhysReg
Definition: MCRegisterInfo.h:26
uint16_t
unsigned short uint16_t
Definition: sftypes.h:30
uint8_t
unsigned char uint8_t
Definition: sftypes.h:31