Rizin
unix-like reverse engineering framework and cli tools
SparcGenAsmWriter.inc
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1 /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2 |* *|
3 |*Assembly Writer Source Fragment *|
4 |* *|
5 |* Automatically generated file, do not edit! *|
6 |* *|
7 \*===----------------------------------------------------------------------===*/
8 
9 /* Capstone Disassembly Engine */
10 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
11 
12 #include <stdio.h> // debug
13 #include <capstone/platform.h>
14 
15 
18 static void printInstruction(MCInst *MI, SStream *O, const MCRegisterInfo *MRI)
19 {
20  static const uint32_t OpInfo[] = {
21  0U, // PHI
22  0U, // INLINEASM
23  0U, // CFI_INSTRUCTION
24  0U, // EH_LABEL
25  0U, // GC_LABEL
26  0U, // KILL
27  0U, // EXTRACT_SUBREG
28  0U, // INSERT_SUBREG
29  0U, // IMPLICIT_DEF
30  0U, // SUBREG_TO_REG
31  0U, // COPY_TO_REGCLASS
32  2452U, // DBG_VALUE
33  0U, // REG_SEQUENCE
34  0U, // COPY
35  2445U, // BUNDLE
36  2462U, // LIFETIME_START
37  2432U, // LIFETIME_END
38  0U, // STACKMAP
39  0U, // PATCHPOINT
40  0U, // LOAD_STACK_GUARD
41  0U, // STATEPOINT
42  0U, // FRAME_ALLOC
43  4688U, // ADDCCri
44  4688U, // ADDCCrr
45  5925U, // ADDCri
46  5925U, // ADDCrr
47  4772U, // ADDEri
48  4772U, // ADDErr
49  4786U, // ADDXC
50  4678U, // ADDXCCC
51  4808U, // ADDXri
52  4808U, // ADDXrr
53  4808U, // ADDri
54  4808U, // ADDrr
55  74166U, // ADJCALLSTACKDOWN
56  74185U, // ADJCALLSTACKUP
57  5497U, // ALIGNADDR
58  5127U, // ALIGNADDRL
59  4695U, // ANDCCri
60  4695U, // ANDCCrr
61  4718U, // ANDNCCri
62  4718U, // ANDNCCrr
63  5182U, // ANDNri
64  5182U, // ANDNrr
65  5182U, // ANDXNrr
66  4876U, // ANDXri
67  4876U, // ANDXrr
68  4876U, // ANDri
69  4876U, // ANDrr
70  4502U, // ARRAY16
71  4255U, // ARRAY32
72  4526U, // ARRAY8
73  0U, // ATOMIC_LOAD_ADD_32
74  0U, // ATOMIC_LOAD_ADD_64
75  0U, // ATOMIC_LOAD_AND_32
76  0U, // ATOMIC_LOAD_AND_64
77  0U, // ATOMIC_LOAD_MAX_32
78  0U, // ATOMIC_LOAD_MAX_64
79  0U, // ATOMIC_LOAD_MIN_32
80  0U, // ATOMIC_LOAD_MIN_64
81  0U, // ATOMIC_LOAD_NAND_32
82  0U, // ATOMIC_LOAD_NAND_64
83  0U, // ATOMIC_LOAD_OR_32
84  0U, // ATOMIC_LOAD_OR_64
85  0U, // ATOMIC_LOAD_SUB_32
86  0U, // ATOMIC_LOAD_SUB_64
87  0U, // ATOMIC_LOAD_UMAX_32
88  0U, // ATOMIC_LOAD_UMAX_64
89  0U, // ATOMIC_LOAD_UMIN_32
90  0U, // ATOMIC_LOAD_UMIN_64
91  0U, // ATOMIC_LOAD_XOR_32
92  0U, // ATOMIC_LOAD_XOR_64
93  0U, // ATOMIC_SWAP_64
94  74271U, // BA
95  1194492U, // BCOND
96  1260028U, // BCONDA
97  17659U, // BINDri
98  17659U, // BINDrr
99  5065U, // BMASK
100  145915U, // BPFCC
101  211451U, // BPFCCA
102  276987U, // BPFCCANT
103  342523U, // BPFCCNT
104  2106465U, // BPGEZapn
105  2105838U, // BPGEZapt
106  2106532U, // BPGEZnapn
107  2107288U, // BPGEZnapt
108  2106489U, // BPGZapn
109  2105856U, // BPGZapt
110  2106552U, // BPGZnapn
111  2107384U, // BPGZnapt
112  1456636U, // BPICC
113  473596U, // BPICCA
114  539132U, // BPICCANT
115  604668U, // BPICCNT
116  2106477U, // BPLEZapn
117  2105847U, // BPLEZapt
118  2106542U, // BPLEZnapn
119  2107337U, // BPLEZnapt
120  2106500U, // BPLZapn
121  2105864U, // BPLZapt
122  2106561U, // BPLZnapn
123  2107428U, // BPLZnapt
124  2106511U, // BPNZapn
125  2105872U, // BPNZapt
126  2106570U, // BPNZnapn
127  2107472U, // BPNZnapt
128  1718780U, // BPXCC
129  735740U, // BPXCCA
130  801276U, // BPXCCANT
131  866812U, // BPXCCNT
132  2106522U, // BPZapn
133  2105880U, // BPZapt
134  2106579U, // BPZnapn
135  2107505U, // BPZnapt
136  4983U, // BSHUFFLE
137  74742U, // CALL
138  17398U, // CALLri
139  17398U, // CALLrr
140  924148U, // CASXrr
141  924129U, // CASrr
142  74001U, // CMASK16
143  73833U, // CMASK32
144  74150U, // CMASK8
145  2106607U, // CMPri
146  2106607U, // CMPrr
147  4332U, // EDGE16
148  5081U, // EDGE16L
149  5198U, // EDGE16LN
150  5165U, // EDGE16N
151  4164U, // EDGE32
152  5072U, // EDGE32L
153  5188U, // EDGE32LN
154  5156U, // EDGE32N
155  4511U, // EDGE8
156  5090U, // EDGE8L
157  5208U, // EDGE8LN
158  5174U, // EDGE8N
159  1053516U, // FABSD
160  1054031U, // FABSQ
161  1054376U, // FABSS
162  4813U, // FADDD
163  5383U, // FADDQ
164  5645U, // FADDS
165  4648U, // FALIGNADATA
166  4875U, // FAND
167  4112U, // FANDNOT1
168  5544U, // FANDNOT1S
169  4271U, // FANDNOT2
170  5591U, // FANDNOT2S
171  5677U, // FANDS
172  1194491U, // FBCOND
173  1260027U, // FBCONDA
174  4394U, // FCHKSM16
175  2106173U, // FCMPD
176  4413U, // FCMPEQ16
177  4226U, // FCMPEQ32
178  4432U, // FCMPGT16
179  4245U, // FCMPGT32
180  4340U, // FCMPLE16
181  4172U, // FCMPLE32
182  4350U, // FCMPNE16
183  4182U, // FCMPNE32
184  2106696U, // FCMPQ
185  2107005U, // FCMPS
186  4960U, // FDIVD
187  5475U, // FDIVQ
188  5815U, // FDIVS
189  5405U, // FDMULQ
190  1053620U, // FDTOI
191  1053996U, // FDTOQ
192  1054305U, // FDTOS
193  1054536U, // FDTOX
194  1053464U, // FEXPAND
195  4820U, // FHADDD
196  5652U, // FHADDS
197  4800U, // FHSUBD
198  5637U, // FHSUBS
199  1053473U, // FITOD
200  1054003U, // FITOQ
201  1054312U, // FITOS
202  6300484U, // FLCMPD
203  6301316U, // FLCMPS
204  2606U, // FLUSHW
205  4404U, // FMEAN16
206  1053543U, // FMOVD
207  1006078U, // FMOVD_FCC
208  23484926U, // FMOVD_ICC
209  23747070U, // FMOVD_XCC
210  1054058U, // FMOVQ
211  1006102U, // FMOVQ_FCC
212  23484950U, // FMOVQ_ICC
213  23747094U, // FMOVQ_XCC
214  6018U, // FMOVRGEZD
215  6029U, // FMOVRGEZQ
216  6056U, // FMOVRGEZS
217  6116U, // FMOVRGZD
218  6126U, // FMOVRGZQ
219  6150U, // FMOVRGZS
220  6067U, // FMOVRLEZD
221  6078U, // FMOVRLEZQ
222  6105U, // FMOVRLEZS
223  6160U, // FMOVRLZD
224  6170U, // FMOVRLZQ
225  6194U, // FMOVRLZS
226  6204U, // FMOVRNZD
227  6214U, // FMOVRNZQ
228  6238U, // FMOVRNZS
229  6009U, // FMOVRZD
230  6248U, // FMOVRZQ
231  6269U, // FMOVRZS
232  1054398U, // FMOVS
233  1006114U, // FMOVS_FCC
234  23484962U, // FMOVS_ICC
235  23747106U, // FMOVS_XCC
236  4490U, // FMUL8SUX16
237  4465U, // FMUL8ULX16
238  4442U, // FMUL8X16
239  5098U, // FMUL8X16AL
240  5849U, // FMUL8X16AU
241  4860U, // FMULD
242  4477U, // FMULD8SUX16
243  4452U, // FMULD8ULX16
244  5413U, // FMULQ
245  5714U, // FMULS
246  4837U, // FNADDD
247  5669U, // FNADDS
248  4881U, // FNAND
249  5684U, // FNANDS
250  1053429U, // FNEGD
251  1053974U, // FNEGQ
252  1054283U, // FNEGS
253  4828U, // FNHADDD
254  5660U, // FNHADDS
255  4828U, // FNMULD
256  5660U, // FNMULS
257  5513U, // FNOR
258  5778U, // FNORS
259  1052698U, // FNOT1
260  1054131U, // FNOT1S
261  1052857U, // FNOT2
262  1054178U, // FNOT2S
263  5660U, // FNSMULD
264  74625U, // FONE
265  75324U, // FONES
266  5508U, // FOR
267  4129U, // FORNOT1
268  5563U, // FORNOT1S
269  4288U, // FORNOT2
270  5610U, // FORNOT2S
271  5772U, // FORS
272  1052936U, // FPACK16
273  4192U, // FPACK32
274  1054507U, // FPACKFIX
275  4323U, // FPADD16
276  5620U, // FPADD16S
277  4155U, // FPADD32
278  5573U, // FPADD32S
279  4297U, // FPADD64
280  4974U, // FPMERGE
281  4314U, // FPSUB16
282  4580U, // FPSUB16S
283  4146U, // FPSUB32
284  4570U, // FPSUB32S
285  1053480U, // FQTOD
286  1053627U, // FQTOI
287  1054319U, // FQTOS
288  1054552U, // FQTOX
289  4423U, // FSLAS16
290  4236U, // FSLAS32
291  4378U, // FSLL16
292  4210U, // FSLL32
293  4867U, // FSMULD
294  1053523U, // FSQRTD
295  1054038U, // FSQRTQ
296  1054383U, // FSQRTS
297  4306U, // FSRA16
298  4138U, // FSRA32
299  1052681U, // FSRC1
300  1054112U, // FSRC1S
301  1052840U, // FSRC2
302  1054159U, // FSRC2S
303  4386U, // FSRL16
304  4218U, // FSRL32
305  1053487U, // FSTOD
306  1053634U, // FSTOI
307  1054010U, // FSTOQ
308  1054559U, // FSTOX
309  4793U, // FSUBD
310  5376U, // FSUBQ
311  5630U, // FSUBS
312  5519U, // FXNOR
313  5785U, // FXNORS
314  5526U, // FXOR
315  5793U, // FXORS
316  1053494U, // FXTOD
317  1054017U, // FXTOQ
318  1054326U, // FXTOS
319  74984U, // FZERO
320  75353U, // FZEROS
321  24584U, // GETPCX
322  1078273U, // JMPLri
323  1078273U, // JMPLrr
324  1997243U, // LDDFri
325  1997243U, // LDDFrr
326  1997249U, // LDFri
327  1997249U, // LDFrr
328  1997275U, // LDQFri
329  1997275U, // LDQFrr
330  1997229U, // LDSBri
331  1997229U, // LDSBrr
332  1997254U, // LDSHri
333  1997254U, // LDSHrr
334  1997287U, // LDSWri
335  1997287U, // LDSWrr
336  1997236U, // LDUBri
337  1997236U, // LDUBrr
338  1997261U, // LDUHri
339  1997261U, // LDUHrr
340  1997294U, // LDXri
341  1997294U, // LDXrr
342  1997249U, // LDri
343  1997249U, // LDrr
344  33480U, // LEAX_ADDri
345  33480U, // LEA_ADDri
346  1054405U, // LZCNT
347  75121U, // MEMBARi
348  1054543U, // MOVDTOX
349  1006122U, // MOVFCCri
350  1006122U, // MOVFCCrr
351  23484970U, // MOVICCri
352  23484970U, // MOVICCrr
353  6047U, // MOVRGEZri
354  6047U, // MOVRGEZrr
355  6142U, // MOVRGZri
356  6142U, // MOVRGZrr
357  6096U, // MOVRLEZri
358  6096U, // MOVRLEZrr
359  6186U, // MOVRLZri
360  6186U, // MOVRLZrr
361  6230U, // MOVRNZri
362  6230U, // MOVRNZrr
363  6262U, // MOVRRZri
364  6262U, // MOVRRZrr
365  1054469U, // MOVSTOSW
366  1054479U, // MOVSTOUW
367  1054543U, // MOVWTOS
368  23747114U, // MOVXCCri
369  23747114U, // MOVXCCrr
370  1054543U, // MOVXTOD
371  5954U, // MULXri
372  5954U, // MULXrr
373  2578U, // NOP
374  4735U, // ORCCri
375  4735U, // ORCCrr
376  4726U, // ORNCCri
377  4726U, // ORNCCrr
378  5339U, // ORNri
379  5339U, // ORNrr
380  5339U, // ORXNrr
381  5509U, // ORXri
382  5509U, // ORXrr
383  5509U, // ORri
384  5509U, // ORrr
385  5836U, // PDIST
386  5344U, // PDISTN
387  1053356U, // POPCrr
388  73729U, // RDY
389  4999U, // RESTOREri
390  4999U, // RESTORErr
391  76132U, // RET
392  76141U, // RETL
393  18131U, // RETTri
394  18131U, // RETTrr
395  5008U, // SAVEri
396  5008U, // SAVErr
397  4748U, // SDIVCCri
398  4748U, // SDIVCCrr
399  5995U, // SDIVXri
400  5995U, // SDIVXrr
401  5861U, // SDIVri
402  5861U, // SDIVrr
403  2182U, // SELECT_CC_DFP_FCC
404  2293U, // SELECT_CC_DFP_ICC
405  2238U, // SELECT_CC_FP_FCC
406  2349U, // SELECT_CC_FP_ICC
407  2265U, // SELECT_CC_Int_FCC
408  2376U, // SELECT_CC_Int_ICC
409  2210U, // SELECT_CC_QFP_FCC
410  2321U, // SELECT_CC_QFP_ICC
411  1053595U, // SETHIXi
412  1053595U, // SETHIi
413  2569U, // SHUTDOWN
414  2564U, // SIAM
415  5941U, // SLLXri
416  5941U, // SLLXrr
417  5116U, // SLLri
418  5116U, // SLLrr
419  4702U, // SMULCCri
420  4702U, // SMULCCrr
421  5144U, // SMULri
422  5144U, // SMULrr
423  5913U, // SRAXri
424  5913U, // SRAXrr
425  4643U, // SRAri
426  4643U, // SRArr
427  5947U, // SRLXri
428  5947U, // SRLXrr
429  5139U, // SRLri
430  5139U, // SRLrr
431  2588U, // STBAR
432  37428U, // STBri
433  37428U, // STBrr
434  37723U, // STDFri
435  37723U, // STDFrr
436  38607U, // STFri
437  38607U, // STFrr
438  37782U, // STHri
439  37782U, // STHrr
440  38238U, // STQFri
441  38238U, // STQFrr
442  38758U, // STXri
443  38758U, // STXrr
444  38607U, // STri
445  38607U, // STrr
446  4671U, // SUBCCri
447  4671U, // SUBCCrr
448  5919U, // SUBCri
449  5919U, // SUBCrr
450  4764U, // SUBEri
451  4764U, // SUBErr
452  4665U, // SUBXri
453  4665U, // SUBXrr
454  4665U, // SUBri
455  4665U, // SUBrr
456  1997268U, // SWAPri
457  1997268U, // SWAPrr
458  2422U, // TA3
459  2427U, // TA5
460  5883U, // TADDCCTVri
461  5883U, // TADDCCTVrr
462  4687U, // TADDCCri
463  4687U, // TADDCCrr
464  9873960U, // TICCri
465  9873960U, // TICCrr
466  37753544U, // TLS_ADDXrr
467  37753544U, // TLS_ADDrr
468  2106358U, // TLS_CALL
469  39746030U, // TLS_LDXrr
470  39745985U, // TLS_LDrr
471  5873U, // TSUBCCTVri
472  5873U, // TSUBCCTVrr
473  4670U, // TSUBCCri
474  4670U, // TSUBCCrr
475  10136104U, // TXCCri
476  10136104U, // TXCCrr
477  4756U, // UDIVCCri
478  4756U, // UDIVCCrr
479  6002U, // UDIVXri
480  6002U, // UDIVXrr
481  5867U, // UDIVri
482  5867U, // UDIVrr
483  4710U, // UMULCCri
484  4710U, // UMULCCrr
485  5026U, // UMULXHI
486  5150U, // UMULri
487  5150U, // UMULrr
488  74996U, // UNIMP
489  6300477U, // V9FCMPD
490  6300397U, // V9FCMPED
491  6300942U, // V9FCMPEQ
492  6301251U, // V9FCMPES
493  6301000U, // V9FCMPQ
494  6301309U, // V9FCMPS
495  47614U, // V9FMOVD_FCC
496  47638U, // V9FMOVQ_FCC
497  47650U, // V9FMOVS_FCC
498  47658U, // V9MOVFCCri
499  47658U, // V9MOVFCCrr
500  14689692U, // WRYri
501  14689692U, // WRYrr
502  5953U, // XMULX
503  5035U, // XMULXHI
504  4733U, // XNORCCri
505  4733U, // XNORCCrr
506  5520U, // XNORXrr
507  5520U, // XNORri
508  5520U, // XNORrr
509  4741U, // XORCCri
510  4741U, // XORCCrr
511  5527U, // XORXri
512  5527U, // XORXrr
513  5527U, // XORri
514  5527U, // XORrr
515  0U
516  };
517 
518 #ifndef CAPSTONE_DIET
519  static const char AsmStrs[] = {
520  /* 0 */ 'r', 'd', 32, '%', 'y', ',', 32, 0,
521  /* 8 */ 'f', 's', 'r', 'c', '1', 32, 0,
522  /* 15 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 32, 0,
523  /* 25 */ 'f', 'n', 'o', 't', '1', 32, 0,
524  /* 32 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 32, 0,
525  /* 41 */ 'f', 's', 'r', 'a', '3', '2', 32, 0,
526  /* 49 */ 'f', 'p', 's', 'u', 'b', '3', '2', 32, 0,
527  /* 58 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 32, 0,
528  /* 67 */ 'e', 'd', 'g', 'e', '3', '2', 32, 0,
529  /* 75 */ 'f', 'c', 'm', 'p', 'l', 'e', '3', '2', 32, 0,
530  /* 85 */ 'f', 'c', 'm', 'p', 'n', 'e', '3', '2', 32, 0,
531  /* 95 */ 'f', 'p', 'a', 'c', 'k', '3', '2', 32, 0,
532  /* 104 */ 'c', 'm', 'a', 's', 'k', '3', '2', 32, 0,
533  /* 113 */ 'f', 's', 'l', 'l', '3', '2', 32, 0,
534  /* 121 */ 'f', 's', 'r', 'l', '3', '2', 32, 0,
535  /* 129 */ 'f', 'c', 'm', 'p', 'e', 'q', '3', '2', 32, 0,
536  /* 139 */ 'f', 's', 'l', 'a', 's', '3', '2', 32, 0,
537  /* 148 */ 'f', 'c', 'm', 'p', 'g', 't', '3', '2', 32, 0,
538  /* 158 */ 'a', 'r', 'r', 'a', 'y', '3', '2', 32, 0,
539  /* 167 */ 'f', 's', 'r', 'c', '2', 32, 0,
540  /* 174 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 32, 0,
541  /* 184 */ 'f', 'n', 'o', 't', '2', 32, 0,
542  /* 191 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 32, 0,
543  /* 200 */ 'f', 'p', 'a', 'd', 'd', '6', '4', 32, 0,
544  /* 209 */ 'f', 's', 'r', 'a', '1', '6', 32, 0,
545  /* 217 */ 'f', 'p', 's', 'u', 'b', '1', '6', 32, 0,
546  /* 226 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 32, 0,
547  /* 235 */ 'e', 'd', 'g', 'e', '1', '6', 32, 0,
548  /* 243 */ 'f', 'c', 'm', 'p', 'l', 'e', '1', '6', 32, 0,
549  /* 253 */ 'f', 'c', 'm', 'p', 'n', 'e', '1', '6', 32, 0,
550  /* 263 */ 'f', 'p', 'a', 'c', 'k', '1', '6', 32, 0,
551  /* 272 */ 'c', 'm', 'a', 's', 'k', '1', '6', 32, 0,
552  /* 281 */ 'f', 's', 'l', 'l', '1', '6', 32, 0,
553  /* 289 */ 'f', 's', 'r', 'l', '1', '6', 32, 0,
554  /* 297 */ 'f', 'c', 'h', 'k', 's', 'm', '1', '6', 32, 0,
555  /* 307 */ 'f', 'm', 'e', 'a', 'n', '1', '6', 32, 0,
556  /* 316 */ 'f', 'c', 'm', 'p', 'e', 'q', '1', '6', 32, 0,
557  /* 326 */ 'f', 's', 'l', 'a', 's', '1', '6', 32, 0,
558  /* 335 */ 'f', 'c', 'm', 'p', 'g', 't', '1', '6', 32, 0,
559  /* 345 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 32, 0,
560  /* 355 */ 'f', 'm', 'u', 'l', 'd', '8', 'u', 'l', 'x', '1', '6', 32, 0,
561  /* 368 */ 'f', 'm', 'u', 'l', '8', 'u', 'l', 'x', '1', '6', 32, 0,
562  /* 380 */ 'f', 'm', 'u', 'l', 'd', '8', 's', 'u', 'x', '1', '6', 32, 0,
563  /* 393 */ 'f', 'm', 'u', 'l', '8', 's', 'u', 'x', '1', '6', 32, 0,
564  /* 405 */ 'a', 'r', 'r', 'a', 'y', '1', '6', 32, 0,
565  /* 414 */ 'e', 'd', 'g', 'e', '8', 32, 0,
566  /* 421 */ 'c', 'm', 'a', 's', 'k', '8', 32, 0,
567  /* 429 */ 'a', 'r', 'r', 'a', 'y', '8', 32, 0,
568  /* 437 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'D', 'O', 'W', 'N', 32, 0,
569  /* 456 */ '!', 'A', 'D', 'J', 'C', 'A', 'L', 'L', 'S', 'T', 'A', 'C', 'K', 'U', 'P', 32, 0,
570  /* 473 */ 'f', 'p', 's', 'u', 'b', '3', '2', 'S', 32, 0,
571  /* 483 */ 'f', 'p', 's', 'u', 'b', '1', '6', 'S', 32, 0,
572  /* 493 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', 32, 0,
573  /* 502 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', 32, 0,
574  /* 511 */ 'b', 'r', 'g', 'z', ',', 'a', 32, 0,
575  /* 519 */ 'b', 'r', 'l', 'z', ',', 'a', 32, 0,
576  /* 527 */ 'b', 'r', 'n', 'z', ',', 'a', 32, 0,
577  /* 535 */ 'b', 'r', 'z', ',', 'a', 32, 0,
578  /* 542 */ 'b', 'a', 32, 0,
579  /* 546 */ 's', 'r', 'a', 32, 0,
580  /* 551 */ 'f', 'a', 'l', 'i', 'g', 'n', 'd', 'a', 't', 'a', 32, 0,
581  /* 563 */ 's', 't', 'b', 32, 0,
582  /* 568 */ 's', 'u', 'b', 32, 0,
583  /* 573 */ 't', 's', 'u', 'b', 'c', 'c', 32, 0,
584  /* 581 */ 'a', 'd', 'd', 'x', 'c', 'c', 'c', 32, 0,
585  /* 590 */ 't', 'a', 'd', 'd', 'c', 'c', 32, 0,
586  /* 598 */ 'a', 'n', 'd', 'c', 'c', 32, 0,
587  /* 605 */ 's', 'm', 'u', 'l', 'c', 'c', 32, 0,
588  /* 613 */ 'u', 'm', 'u', 'l', 'c', 'c', 32, 0,
589  /* 621 */ 'a', 'n', 'd', 'n', 'c', 'c', 32, 0,
590  /* 629 */ 'o', 'r', 'n', 'c', 'c', 32, 0,
591  /* 636 */ 'x', 'n', 'o', 'r', 'c', 'c', 32, 0,
592  /* 644 */ 'x', 'o', 'r', 'c', 'c', 32, 0,
593  /* 651 */ 's', 'd', 'i', 'v', 'c', 'c', 32, 0,
594  /* 659 */ 'u', 'd', 'i', 'v', 'c', 'c', 32, 0,
595  /* 667 */ 's', 'u', 'b', 'x', 'c', 'c', 32, 0,
596  /* 675 */ 'a', 'd', 'd', 'x', 'c', 'c', 32, 0,
597  /* 683 */ 'p', 'o', 'p', 'c', 32, 0,
598  /* 689 */ 'a', 'd', 'd', 'x', 'c', 32, 0,
599  /* 696 */ 'f', 's', 'u', 'b', 'd', 32, 0,
600  /* 703 */ 'f', 'h', 's', 'u', 'b', 'd', 32, 0,
601  /* 711 */ 'a', 'd', 'd', 32, 0,
602  /* 716 */ 'f', 'a', 'd', 'd', 'd', 32, 0,
603  /* 723 */ 'f', 'h', 'a', 'd', 'd', 'd', 32, 0,
604  /* 731 */ 'f', 'n', 'h', 'a', 'd', 'd', 'd', 32, 0,
605  /* 740 */ 'f', 'n', 'a', 'd', 'd', 'd', 32, 0,
606  /* 748 */ 'f', 'c', 'm', 'p', 'e', 'd', 32, 0,
607  /* 756 */ 'f', 'n', 'e', 'g', 'd', 32, 0,
608  /* 763 */ 'f', 'm', 'u', 'l', 'd', 32, 0,
609  /* 770 */ 'f', 's', 'm', 'u', 'l', 'd', 32, 0,
610  /* 778 */ 'f', 'a', 'n', 'd', 32, 0,
611  /* 784 */ 'f', 'n', 'a', 'n', 'd', 32, 0,
612  /* 791 */ 'f', 'e', 'x', 'p', 'a', 'n', 'd', 32, 0,
613  /* 800 */ 'f', 'i', 't', 'o', 'd', 32, 0,
614  /* 807 */ 'f', 'q', 't', 'o', 'd', 32, 0,
615  /* 814 */ 'f', 's', 't', 'o', 'd', 32, 0,
616  /* 821 */ 'f', 'x', 't', 'o', 'd', 32, 0,
617  /* 828 */ 'f', 'c', 'm', 'p', 'd', 32, 0,
618  /* 835 */ 'f', 'l', 'c', 'm', 'p', 'd', 32, 0,
619  /* 843 */ 'f', 'a', 'b', 's', 'd', 32, 0,
620  /* 850 */ 'f', 's', 'q', 'r', 't', 'd', 32, 0,
621  /* 858 */ 's', 't', 'd', 32, 0,
622  /* 863 */ 'f', 'd', 'i', 'v', 'd', 32, 0,
623  /* 870 */ 'f', 'm', 'o', 'v', 'd', 32, 0,
624  /* 877 */ 'f', 'p', 'm', 'e', 'r', 'g', 'e', 32, 0,
625  /* 886 */ 'b', 's', 'h', 'u', 'f', 'f', 'l', 'e', 32, 0,
626  /* 896 */ 'f', 'o', 'n', 'e', 32, 0,
627  /* 902 */ 'r', 'e', 's', 't', 'o', 'r', 'e', 32, 0,
628  /* 911 */ 's', 'a', 'v', 'e', 32, 0,
629  /* 917 */ 's', 't', 'h', 32, 0,
630  /* 922 */ 's', 'e', 't', 'h', 'i', 32, 0,
631  /* 929 */ 'u', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
632  /* 938 */ 'x', 'm', 'u', 'l', 'x', 'h', 'i', 32, 0,
633  /* 947 */ 'f', 'd', 't', 'o', 'i', 32, 0,
634  /* 954 */ 'f', 'q', 't', 'o', 'i', 32, 0,
635  /* 961 */ 'f', 's', 't', 'o', 'i', 32, 0,
636  /* 968 */ 'b', 'm', 'a', 's', 'k', 32, 0,
637  /* 975 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 32, 0,
638  /* 984 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 32, 0,
639  /* 993 */ 'e', 'd', 'g', 'e', '8', 'l', 32, 0,
640  /* 1001 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'l', 32, 0,
641  /* 1013 */ 'c', 'a', 'l', 'l', 32, 0,
642  /* 1019 */ 's', 'l', 'l', 32, 0,
643  /* 1024 */ 'j', 'm', 'p', 'l', 32, 0,
644  /* 1030 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 'l', 32, 0,
645  /* 1042 */ 's', 'r', 'l', 32, 0,
646  /* 1047 */ 's', 'm', 'u', 'l', 32, 0,
647  /* 1053 */ 'u', 'm', 'u', 'l', 32, 0,
648  /* 1059 */ 'e', 'd', 'g', 'e', '3', '2', 'n', 32, 0,
649  /* 1068 */ 'e', 'd', 'g', 'e', '1', '6', 'n', 32, 0,
650  /* 1077 */ 'e', 'd', 'g', 'e', '8', 'n', 32, 0,
651  /* 1085 */ 'a', 'n', 'd', 'n', 32, 0,
652  /* 1091 */ 'e', 'd', 'g', 'e', '3', '2', 'l', 'n', 32, 0,
653  /* 1101 */ 'e', 'd', 'g', 'e', '1', '6', 'l', 'n', 32, 0,
654  /* 1111 */ 'e', 'd', 'g', 'e', '8', 'l', 'n', 32, 0,
655  /* 1120 */ 'b', 'r', 'g', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
656  /* 1132 */ 'b', 'r', 'l', 'e', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
657  /* 1144 */ 'b', 'r', 'g', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
658  /* 1155 */ 'b', 'r', 'l', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
659  /* 1166 */ 'b', 'r', 'n', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
660  /* 1177 */ 'b', 'r', 'z', ',', 'a', ',', 'p', 'n', 32, 0,
661  /* 1187 */ 'b', 'r', 'g', 'e', 'z', ',', 'p', 'n', 32, 0,
662  /* 1197 */ 'b', 'r', 'l', 'e', 'z', ',', 'p', 'n', 32, 0,
663  /* 1207 */ 'b', 'r', 'g', 'z', ',', 'p', 'n', 32, 0,
664  /* 1216 */ 'b', 'r', 'l', 'z', ',', 'p', 'n', 32, 0,
665  /* 1225 */ 'b', 'r', 'n', 'z', ',', 'p', 'n', 32, 0,
666  /* 1234 */ 'b', 'r', 'z', ',', 'p', 'n', 32, 0,
667  /* 1242 */ 'o', 'r', 'n', 32, 0,
668  /* 1247 */ 'p', 'd', 'i', 's', 't', 'n', 32, 0,
669  /* 1255 */ 'f', 'z', 'e', 'r', 'o', 32, 0,
670  /* 1262 */ 'c', 'm', 'p', 32, 0,
671  /* 1267 */ 'u', 'n', 'i', 'm', 'p', 32, 0,
672  /* 1274 */ 'j', 'm', 'p', 32, 0,
673  /* 1279 */ 'f', 's', 'u', 'b', 'q', 32, 0,
674  /* 1286 */ 'f', 'a', 'd', 'd', 'q', 32, 0,
675  /* 1293 */ 'f', 'c', 'm', 'p', 'e', 'q', 32, 0,
676  /* 1301 */ 'f', 'n', 'e', 'g', 'q', 32, 0,
677  /* 1308 */ 'f', 'd', 'm', 'u', 'l', 'q', 32, 0,
678  /* 1316 */ 'f', 'm', 'u', 'l', 'q', 32, 0,
679  /* 1323 */ 'f', 'd', 't', 'o', 'q', 32, 0,
680  /* 1330 */ 'f', 'i', 't', 'o', 'q', 32, 0,
681  /* 1337 */ 'f', 's', 't', 'o', 'q', 32, 0,
682  /* 1344 */ 'f', 'x', 't', 'o', 'q', 32, 0,
683  /* 1351 */ 'f', 'c', 'm', 'p', 'q', 32, 0,
684  /* 1358 */ 'f', 'a', 'b', 's', 'q', 32, 0,
685  /* 1365 */ 'f', 's', 'q', 'r', 't', 'q', 32, 0,
686  /* 1373 */ 's', 't', 'q', 32, 0,
687  /* 1378 */ 'f', 'd', 'i', 'v', 'q', 32, 0,
688  /* 1385 */ 'f', 'm', 'o', 'v', 'q', 32, 0,
689  /* 1392 */ 'm', 'e', 'm', 'b', 'a', 'r', 32, 0,
690  /* 1400 */ 'a', 'l', 'i', 'g', 'n', 'a', 'd', 'd', 'r', 32, 0,
691  /* 1411 */ 'f', 'o', 'r', 32, 0,
692  /* 1416 */ 'f', 'n', 'o', 'r', 32, 0,
693  /* 1422 */ 'f', 'x', 'n', 'o', 'r', 32, 0,
694  /* 1429 */ 'f', 'x', 'o', 'r', 32, 0,
695  /* 1435 */ 'w', 'r', 32, 0,
696  /* 1439 */ 'f', 's', 'r', 'c', '1', 's', 32, 0,
697  /* 1447 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '1', 's', 32, 0,
698  /* 1458 */ 'f', 'n', 'o', 't', '1', 's', 32, 0,
699  /* 1466 */ 'f', 'o', 'r', 'n', 'o', 't', '1', 's', 32, 0,
700  /* 1476 */ 'f', 'p', 'a', 'd', 'd', '3', '2', 's', 32, 0,
701  /* 1486 */ 'f', 's', 'r', 'c', '2', 's', 32, 0,
702  /* 1494 */ 'f', 'a', 'n', 'd', 'n', 'o', 't', '2', 's', 32, 0,
703  /* 1505 */ 'f', 'n', 'o', 't', '2', 's', 32, 0,
704  /* 1513 */ 'f', 'o', 'r', 'n', 'o', 't', '2', 's', 32, 0,
705  /* 1523 */ 'f', 'p', 'a', 'd', 'd', '1', '6', 's', 32, 0,
706  /* 1533 */ 'f', 's', 'u', 'b', 's', 32, 0,
707  /* 1540 */ 'f', 'h', 's', 'u', 'b', 's', 32, 0,
708  /* 1548 */ 'f', 'a', 'd', 'd', 's', 32, 0,
709  /* 1555 */ 'f', 'h', 'a', 'd', 'd', 's', 32, 0,
710  /* 1563 */ 'f', 'n', 'h', 'a', 'd', 'd', 's', 32, 0,
711  /* 1572 */ 'f', 'n', 'a', 'd', 'd', 's', 32, 0,
712  /* 1580 */ 'f', 'a', 'n', 'd', 's', 32, 0,
713  /* 1587 */ 'f', 'n', 'a', 'n', 'd', 's', 32, 0,
714  /* 1595 */ 'f', 'o', 'n', 'e', 's', 32, 0,
715  /* 1602 */ 'f', 'c', 'm', 'p', 'e', 's', 32, 0,
716  /* 1610 */ 'f', 'n', 'e', 'g', 's', 32, 0,
717  /* 1617 */ 'f', 'm', 'u', 'l', 's', 32, 0,
718  /* 1624 */ 'f', 'z', 'e', 'r', 'o', 's', 32, 0,
719  /* 1632 */ 'f', 'd', 't', 'o', 's', 32, 0,
720  /* 1639 */ 'f', 'i', 't', 'o', 's', 32, 0,
721  /* 1646 */ 'f', 'q', 't', 'o', 's', 32, 0,
722  /* 1653 */ 'f', 'x', 't', 'o', 's', 32, 0,
723  /* 1660 */ 'f', 'c', 'm', 'p', 's', 32, 0,
724  /* 1667 */ 'f', 'l', 'c', 'm', 'p', 's', 32, 0,
725  /* 1675 */ 'f', 'o', 'r', 's', 32, 0,
726  /* 1681 */ 'f', 'n', 'o', 'r', 's', 32, 0,
727  /* 1688 */ 'f', 'x', 'n', 'o', 'r', 's', 32, 0,
728  /* 1696 */ 'f', 'x', 'o', 'r', 's', 32, 0,
729  /* 1703 */ 'f', 'a', 'b', 's', 's', 32, 0,
730  /* 1710 */ 'f', 's', 'q', 'r', 't', 's', 32, 0,
731  /* 1718 */ 'f', 'd', 'i', 'v', 's', 32, 0,
732  /* 1725 */ 'f', 'm', 'o', 'v', 's', 32, 0,
733  /* 1732 */ 'l', 'z', 'c', 'n', 't', 32, 0,
734  /* 1739 */ 'p', 'd', 'i', 's', 't', 32, 0,
735  /* 1746 */ 'r', 'e', 't', 't', 32, 0,
736  /* 1752 */ 'f', 'm', 'u', 'l', '8', 'x', '1', '6', 'a', 'u', 32, 0,
737  /* 1764 */ 's', 'd', 'i', 'v', 32, 0,
738  /* 1770 */ 'u', 'd', 'i', 'v', 32, 0,
739  /* 1776 */ 't', 's', 'u', 'b', 'c', 'c', 't', 'v', 32, 0,
740  /* 1786 */ 't', 'a', 'd', 'd', 'c', 'c', 't', 'v', 32, 0,
741  /* 1796 */ 'm', 'o', 'v', 's', 't', 'o', 's', 'w', 32, 0,
742  /* 1806 */ 'm', 'o', 'v', 's', 't', 'o', 'u', 'w', 32, 0,
743  /* 1816 */ 's', 'r', 'a', 'x', 32, 0,
744  /* 1822 */ 's', 'u', 'b', 'x', 32, 0,
745  /* 1828 */ 'a', 'd', 'd', 'x', 32, 0,
746  /* 1834 */ 'f', 'p', 'a', 'c', 'k', 'f', 'i', 'x', 32, 0,
747  /* 1844 */ 's', 'l', 'l', 'x', 32, 0,
748  /* 1850 */ 's', 'r', 'l', 'x', 32, 0,
749  /* 1856 */ 'x', 'm', 'u', 'l', 'x', 32, 0,
750  /* 1863 */ 'f', 'd', 't', 'o', 'x', 32, 0,
751  /* 1870 */ 'm', 'o', 'v', 'd', 't', 'o', 'x', 32, 0,
752  /* 1879 */ 'f', 'q', 't', 'o', 'x', 32, 0,
753  /* 1886 */ 'f', 's', 't', 'o', 'x', 32, 0,
754  /* 1893 */ 's', 't', 'x', 32, 0,
755  /* 1898 */ 's', 'd', 'i', 'v', 'x', 32, 0,
756  /* 1905 */ 'u', 'd', 'i', 'v', 'x', 32, 0,
757  /* 1912 */ 'f', 'm', 'o', 'v', 'r', 'd', 'z', 32, 0,
758  /* 1921 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'e', 'z', 32, 0,
759  /* 1932 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'e', 'z', 32, 0,
760  /* 1943 */ 'b', 'r', 'g', 'e', 'z', 32, 0,
761  /* 1950 */ 'm', 'o', 'v', 'r', 'g', 'e', 'z', 32, 0,
762  /* 1959 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'e', 'z', 32, 0,
763  /* 1970 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'e', 'z', 32, 0,
764  /* 1981 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'e', 'z', 32, 0,
765  /* 1992 */ 'b', 'r', 'l', 'e', 'z', 32, 0,
766  /* 1999 */ 'm', 'o', 'v', 'r', 'l', 'e', 'z', 32, 0,
767  /* 2008 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'e', 'z', 32, 0,
768  /* 2019 */ 'f', 'm', 'o', 'v', 'r', 'd', 'g', 'z', 32, 0,
769  /* 2029 */ 'f', 'm', 'o', 'v', 'r', 'q', 'g', 'z', 32, 0,
770  /* 2039 */ 'b', 'r', 'g', 'z', 32, 0,
771  /* 2045 */ 'm', 'o', 'v', 'r', 'g', 'z', 32, 0,
772  /* 2053 */ 'f', 'm', 'o', 'v', 'r', 's', 'g', 'z', 32, 0,
773  /* 2063 */ 'f', 'm', 'o', 'v', 'r', 'd', 'l', 'z', 32, 0,
774  /* 2073 */ 'f', 'm', 'o', 'v', 'r', 'q', 'l', 'z', 32, 0,
775  /* 2083 */ 'b', 'r', 'l', 'z', 32, 0,
776  /* 2089 */ 'm', 'o', 'v', 'r', 'l', 'z', 32, 0,
777  /* 2097 */ 'f', 'm', 'o', 'v', 'r', 's', 'l', 'z', 32, 0,
778  /* 2107 */ 'f', 'm', 'o', 'v', 'r', 'd', 'n', 'z', 32, 0,
779  /* 2117 */ 'f', 'm', 'o', 'v', 'r', 'q', 'n', 'z', 32, 0,
780  /* 2127 */ 'b', 'r', 'n', 'z', 32, 0,
781  /* 2133 */ 'm', 'o', 'v', 'r', 'n', 'z', 32, 0,
782  /* 2141 */ 'f', 'm', 'o', 'v', 'r', 's', 'n', 'z', 32, 0,
783  /* 2151 */ 'f', 'm', 'o', 'v', 'r', 'q', 'z', 32, 0,
784  /* 2160 */ 'b', 'r', 'z', 32, 0,
785  /* 2165 */ 'm', 'o', 'v', 'r', 'z', 32, 0,
786  /* 2172 */ 'f', 'm', 'o', 'v', 'r', 's', 'z', 32, 0,
787  /* 2181 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
788  /* 2209 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
789  /* 2237 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
790  /* 2264 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'F', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
791  /* 2292 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'D', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
792  /* 2320 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'Q', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
793  /* 2348 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'F', 'P', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
794  /* 2375 */ ';', 32, 'S', 'E', 'L', 'E', 'C', 'T', '_', 'C', 'C', '_', 'I', 'n', 't', '_', 'I', 'C', 'C', 32, 'P', 'S', 'E', 'U', 'D', 'O', '!', 0,
795  /* 2403 */ 'j', 'm', 'p', 32, '%', 'i', '7', '+', 0,
796  /* 2412 */ 'j', 'm', 'p', 32, '%', 'o', '7', '+', 0,
797  /* 2421 */ 't', 'a', 32, '3', 0,
798  /* 2426 */ 't', 'a', 32, '5', 0,
799  /* 2431 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0,
800  /* 2444 */ 'B', 'U', 'N', 'D', 'L', 'E', 0,
801  /* 2451 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0,
802  /* 2461 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0,
803  /* 2476 */ 'l', 'd', 's', 'b', 32, '[', 0,
804  /* 2483 */ 'l', 'd', 'u', 'b', 32, '[', 0,
805  /* 2490 */ 'l', 'd', 'd', 32, '[', 0,
806  /* 2496 */ 'l', 'd', 32, '[', 0,
807  /* 2501 */ 'l', 'd', 's', 'h', 32, '[', 0,
808  /* 2508 */ 'l', 'd', 'u', 'h', 32, '[', 0,
809  /* 2515 */ 's', 'w', 'a', 'p', 32, '[', 0,
810  /* 2522 */ 'l', 'd', 'q', 32, '[', 0,
811  /* 2528 */ 'c', 'a', 's', 32, '[', 0,
812  /* 2534 */ 'l', 'd', 's', 'w', 32, '[', 0,
813  /* 2541 */ 'l', 'd', 'x', 32, '[', 0,
814  /* 2547 */ 'c', 'a', 's', 'x', 32, '[', 0,
815  /* 2554 */ 'f', 'b', 0,
816  /* 2557 */ 'f', 'm', 'o', 'v', 'd', 0,
817  /* 2563 */ 's', 'i', 'a', 'm', 0,
818  /* 2568 */ 's', 'h', 'u', 't', 'd', 'o', 'w', 'n', 0,
819  /* 2577 */ 'n', 'o', 'p', 0,
820  /* 2581 */ 'f', 'm', 'o', 'v', 'q', 0,
821  /* 2587 */ 's', 't', 'b', 'a', 'r', 0,
822  /* 2593 */ 'f', 'm', 'o', 'v', 's', 0,
823  /* 2599 */ 't', 0,
824  /* 2601 */ 'm', 'o', 'v', 0,
825  /* 2605 */ 'f', 'l', 'u', 's', 'h', 'w', 0,
826  };
827 #endif
828 
829  // Emit the opcode for the instruction.
830  uint32_t Bits = OpInfo[MCInst_getOpcode(MI)];
831 #ifndef CAPSTONE_DIET
832  // assert(Bits != 0 && "Cannot print this instruction.");
833  SStream_concat0(O, AsmStrs+(Bits & 4095)-1);
834 #endif
835 
836 
837  // Fragment 0 encoded into 4 bits for 12 unique commands.
838  // printf("Frag-0: %u\n", (Bits >> 12) & 15);
839  switch ((Bits >> 12) & 15) {
840  default: // unreachable.
841  case 0:
842  // DBG_VALUE, BUNDLE, LIFETIME_START, LIFETIME_END, FLUSHW, NOP, SELECT_C...
843  return;
844  break;
845  case 1:
846  // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
847  printOperand(MI, 1, O);
848  break;
849  case 2:
850  // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, BPGEZapn, BPGEZapt, BPGEZnapn, B...
851  printOperand(MI, 0, O);
852  break;
853  case 3:
854  // BCOND, BCONDA, BPFCC, BPFCCA, BPFCCANT, BPFCCNT, BPICC, BPICCA, BPICCA...
855  printCCOperand(MI, 1, O);
856  break;
857  case 4:
858  // BINDri, BINDrr, CALLri, CALLrr, RETTri, RETTrr
859  printMemOperand(MI, 0, O, NULL);
860  return;
861  break;
862  case 5:
863  // FMOVD_FCC, FMOVD_ICC, FMOVD_XCC, FMOVQ_FCC, FMOVQ_ICC, FMOVQ_XCC, FMOV...
864  printCCOperand(MI, 3, O);
865  break;
866  case 6:
867  // GETPCX
868  printGetPCX(MI, 0, O);
869  return;
870  break;
871  case 7:
872  // JMPLri, JMPLrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, ...
873  printMemOperand(MI, 1, O, NULL);
874  break;
875  case 8:
876  // LEAX_ADDri, LEA_ADDri
877  printMemOperand(MI, 1, O, "arith");
878  SStream_concat0(O, ", ");
879  printOperand(MI, 0, O);
880  return;
881  break;
882  case 9:
883  // STBri, STBrr, STDFri, STDFrr, STFri, STFrr, STHri, STHrr, STQFri, STQF...
884  printOperand(MI, 2, O);
885  SStream_concat0(O, ", [");
886  printMemOperand(MI, 0, O, NULL);
887  SStream_concat0(O, "]");
888  return;
889  break;
890  case 10:
891  // TICCri, TICCrr, TXCCri, TXCCrr
892  printCCOperand(MI, 2, O);
893  break;
894  case 11:
895  // V9FMOVD_FCC, V9FMOVQ_FCC, V9FMOVS_FCC, V9MOVFCCri, V9MOVFCCrr
896  printCCOperand(MI, 4, O);
897  SStream_concat0(O, " ");
898  printOperand(MI, 1, O);
899  SStream_concat0(O, ", ");
900  printOperand(MI, 2, O);
901  SStream_concat0(O, ", ");
902  printOperand(MI, 0, O);
903  return;
904  break;
905  }
906 
907 
908  // Fragment 1 encoded into 4 bits for 16 unique commands.
909  // printf("Frag-1: %u\n", (Bits >> 16) & 15);
910  switch ((Bits >> 16) & 15) {
911  default: // unreachable.
912  case 0:
913  // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
914  SStream_concat0(O, ", ");
915  break;
916  case 1:
917  // ADJCALLSTACKDOWN, ADJCALLSTACKUP, BA, CALL, CMASK16, CMASK32, CMASK8, ...
918  return;
919  break;
920  case 2:
921  // BCOND, BPFCC, FBCOND
922  SStream_concat0(O, " ");
923  break;
924  case 3:
925  // BCONDA, BPFCCA, FBCONDA
926  SStream_concat0(O, ",a ");
927  Sparc_add_hint(MI, SPARC_HINT_A);
928  break;
929  case 4:
930  // BPFCCANT
931  SStream_concat0(O, ",a,pn ");
932  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
933  printOperand(MI, 2, O);
934  SStream_concat0(O, ", ");
935  printOperand(MI, 0, O);
936  return;
937  break;
938  case 5:
939  // BPFCCNT
940  SStream_concat0(O, ",pn ");
941  Sparc_add_hint(MI, SPARC_HINT_PN);
942  printOperand(MI, 2, O);
943  SStream_concat0(O, ", ");
944  printOperand(MI, 0, O);
945  return;
946  break;
947  case 6:
948  // BPICC, FMOVD_ICC, FMOVQ_ICC, FMOVS_ICC, MOVICCri, MOVICCrr, TICCri, TI...
949  SStream_concat0(O, " %icc, ");
950  Sparc_add_reg(MI, SPARC_REG_ICC);
951  break;
952  case 7:
953  // BPICCA
954  SStream_concat0(O, ",a %icc, ");
955  Sparc_add_hint(MI, SPARC_HINT_A);
956  Sparc_add_reg(MI, SPARC_REG_ICC);
957  printOperand(MI, 0, O);
958  return;
959  break;
960  case 8:
961  // BPICCANT
962  SStream_concat0(O, ",a,pn %icc, ");
963  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
964  Sparc_add_reg(MI, SPARC_REG_ICC);
965  printOperand(MI, 0, O);
966  return;
967  break;
968  case 9:
969  // BPICCNT
970  SStream_concat0(O, ",pn %icc, ");
971  Sparc_add_hint(MI, SPARC_HINT_PN);
972  Sparc_add_reg(MI, SPARC_REG_ICC);
973  printOperand(MI, 0, O);
974  return;
975  break;
976  case 10:
977  // BPXCC, FMOVD_XCC, FMOVQ_XCC, FMOVS_XCC, MOVXCCri, MOVXCCrr, TXCCri, TX...
978  SStream_concat0(O, " %xcc, ");
979  Sparc_add_reg(MI, SPARC_REG_XCC);
980  break;
981  case 11:
982  // BPXCCA
983  SStream_concat0(O, ",a %xcc, ");
984  Sparc_add_hint(MI, SPARC_HINT_A);
985  Sparc_add_reg(MI, SPARC_REG_XCC);
986  printOperand(MI, 0, O);
987  return;
988  break;
989  case 12:
990  // BPXCCANT
991  SStream_concat0(O, ",a,pn %xcc, ");
992  Sparc_add_hint(MI, SPARC_HINT_A + SPARC_HINT_PN);
993  Sparc_add_reg(MI, SPARC_REG_XCC);
994  printOperand(MI, 0, O);
995  return;
996  break;
997  case 13:
998  // BPXCCNT
999  SStream_concat0(O, ",pn %xcc, ");
1000  Sparc_add_hint(MI, SPARC_HINT_PN);
1001  Sparc_add_reg(MI, SPARC_REG_XCC);
1002  printOperand(MI, 0, O);
1003  return;
1004  break;
1005  case 14:
1006  // CASXrr, CASrr, LDDFri, LDDFrr, LDFri, LDFrr, LDQFri, LDQFrr, LDSBri, L...
1007  SStream_concat0(O, "], ");
1008  break;
1009  case 15:
1010  // FMOVD_FCC, FMOVQ_FCC, FMOVS_FCC, MOVFCCri, MOVFCCrr
1011  SStream_concat0(O, " %fcc0, ");
1012  Sparc_add_reg(MI, SPARC_REG_FCC0);
1013  printOperand(MI, 1, O);
1014  SStream_concat0(O, ", ");
1015  printOperand(MI, 0, O);
1016  return;
1017  break;
1018  }
1019 
1020 
1021  // Fragment 2 encoded into 2 bits for 3 unique commands.
1022  // printf("Frag-2: %u\n", (Bits >> 20) & 3);
1023  switch ((Bits >> 20) & 3) {
1024  default: // unreachable.
1025  case 0:
1026  // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1027  printOperand(MI, 2, O);
1028  SStream_concat0(O, ", ");
1029  printOperand(MI, 0, O);
1030  break;
1031  case 1:
1032  // BCOND, BCONDA, BPICC, BPXCC, FABSD, FABSQ, FABSS, FBCOND, FBCONDA, FDT...
1033  printOperand(MI, 0, O);
1034  break;
1035  case 2:
1036  // BPGEZapn, BPGEZapt, BPGEZnapn, BPGEZnapt, BPGZapn, BPGZapt, BPGZnapn, ...
1037  printOperand(MI, 1, O);
1038  break;
1039  }
1040 
1041 
1042  // Fragment 3 encoded into 2 bits for 4 unique commands.
1043  // printf("Frag-3: %u\n", (Bits >> 22) & 3);
1044  switch ((Bits >> 22) & 3) {
1045  default: // unreachable.
1046  case 0:
1047  // ADDCCri, ADDCCrr, ADDCri, ADDCrr, ADDEri, ADDErr, ADDXC, ADDXCCC, ADDX...
1048  return;
1049  break;
1050  case 1:
1051  // FLCMPD, FLCMPS, FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC,...
1052  SStream_concat0(O, ", ");
1053  break;
1054  case 2:
1055  // TICCri, TICCrr, TXCCri, TXCCrr
1056  SStream_concat0(O, " + "); // qq
1057  printOperand(MI, 1, O);
1058  return;
1059  break;
1060  case 3:
1061  // WRYri, WRYrr
1062  SStream_concat0(O, ", %y");
1063  Sparc_add_reg(MI, SPARC_REG_Y);
1064  return;
1065  break;
1066  }
1067 
1068 
1069  // Fragment 4 encoded into 2 bits for 3 unique commands.
1070  // printf("Frag-4: %u\n", (Bits >> 24) & 3);
1071  switch ((Bits >> 24) & 3) {
1072  default: // unreachable.
1073  case 0:
1074  // FLCMPD, FLCMPS, V9FCMPD, V9FCMPED, V9FCMPEQ, V9FCMPES, V9FCMPQ, V9FCMP...
1075  printOperand(MI, 2, O);
1076  return;
1077  break;
1078  case 1:
1079  // FMOVD_ICC, FMOVD_XCC, FMOVQ_ICC, FMOVQ_XCC, FMOVS_ICC, FMOVS_XCC, MOVI...
1080  printOperand(MI, 0, O);
1081  return;
1082  break;
1083  case 2:
1084  // TLS_ADDXrr, TLS_ADDrr, TLS_LDXrr, TLS_LDrr
1085  printOperand(MI, 3, O);
1086  return;
1087  break;
1088  }
1089 }
1090 
1091 
1095 static const char *getRegisterName(unsigned RegNo)
1096 {
1097  // assert(RegNo && RegNo < 119 && "Invalid register number!");
1098 
1099 #ifndef CAPSTONE_DIET
1100  static const char AsmStrs[] = {
1101  /* 0 */ 'f', '1', '0', 0,
1102  /* 4 */ 'f', '2', '0', 0,
1103  /* 8 */ 'f', '3', '0', 0,
1104  /* 12 */ 'f', '4', '0', 0,
1105  /* 16 */ 'f', '5', '0', 0,
1106  /* 20 */ 'f', '6', '0', 0,
1107  /* 24 */ 'f', 'c', 'c', '0', 0,
1108  /* 29 */ 'f', '0', 0,
1109  /* 32 */ 'g', '0', 0,
1110  /* 35 */ 'i', '0', 0,
1111  /* 38 */ 'l', '0', 0,
1112  /* 41 */ 'o', '0', 0,
1113  /* 44 */ 'f', '1', '1', 0,
1114  /* 48 */ 'f', '2', '1', 0,
1115  /* 52 */ 'f', '3', '1', 0,
1116  /* 56 */ 'f', 'c', 'c', '1', 0,
1117  /* 61 */ 'f', '1', 0,
1118  /* 64 */ 'g', '1', 0,
1119  /* 67 */ 'i', '1', 0,
1120  /* 70 */ 'l', '1', 0,
1121  /* 73 */ 'o', '1', 0,
1122  /* 76 */ 'f', '1', '2', 0,
1123  /* 80 */ 'f', '2', '2', 0,
1124  /* 84 */ 'f', '3', '2', 0,
1125  /* 88 */ 'f', '4', '2', 0,
1126  /* 92 */ 'f', '5', '2', 0,
1127  /* 96 */ 'f', '6', '2', 0,
1128  /* 100 */ 'f', 'c', 'c', '2', 0,
1129  /* 105 */ 'f', '2', 0,
1130  /* 108 */ 'g', '2', 0,
1131  /* 111 */ 'i', '2', 0,
1132  /* 114 */ 'l', '2', 0,
1133  /* 117 */ 'o', '2', 0,
1134  /* 120 */ 'f', '1', '3', 0,
1135  /* 124 */ 'f', '2', '3', 0,
1136  /* 128 */ 'f', 'c', 'c', '3', 0,
1137  /* 133 */ 'f', '3', 0,
1138  /* 136 */ 'g', '3', 0,
1139  /* 139 */ 'i', '3', 0,
1140  /* 142 */ 'l', '3', 0,
1141  /* 145 */ 'o', '3', 0,
1142  /* 148 */ 'f', '1', '4', 0,
1143  /* 152 */ 'f', '2', '4', 0,
1144  /* 156 */ 'f', '3', '4', 0,
1145  /* 160 */ 'f', '4', '4', 0,
1146  /* 164 */ 'f', '5', '4', 0,
1147  /* 168 */ 'f', '4', 0,
1148  /* 171 */ 'g', '4', 0,
1149  /* 174 */ 'i', '4', 0,
1150  /* 177 */ 'l', '4', 0,
1151  /* 180 */ 'o', '4', 0,
1152  /* 183 */ 'f', '1', '5', 0,
1153  /* 187 */ 'f', '2', '5', 0,
1154  /* 191 */ 'f', '5', 0,
1155  /* 194 */ 'g', '5', 0,
1156  /* 197 */ 'i', '5', 0,
1157  /* 200 */ 'l', '5', 0,
1158  /* 203 */ 'o', '5', 0,
1159  /* 206 */ 'f', '1', '6', 0,
1160  /* 210 */ 'f', '2', '6', 0,
1161  /* 214 */ 'f', '3', '6', 0,
1162  /* 218 */ 'f', '4', '6', 0,
1163  /* 222 */ 'f', '5', '6', 0,
1164  /* 226 */ 'f', '6', 0,
1165  /* 229 */ 'g', '6', 0,
1166  /* 232 */ 'l', '6', 0,
1167  /* 235 */ 'f', '1', '7', 0,
1168  /* 239 */ 'f', '2', '7', 0,
1169  /* 243 */ 'f', '7', 0,
1170  /* 246 */ 'g', '7', 0,
1171  /* 249 */ 'i', '7', 0,
1172  /* 252 */ 'l', '7', 0,
1173  /* 255 */ 'o', '7', 0,
1174  /* 258 */ 'f', '1', '8', 0,
1175  /* 262 */ 'f', '2', '8', 0,
1176  /* 266 */ 'f', '3', '8', 0,
1177  /* 270 */ 'f', '4', '8', 0,
1178  /* 274 */ 'f', '5', '8', 0,
1179  /* 278 */ 'f', '8', 0,
1180  /* 281 */ 'f', '1', '9', 0,
1181  /* 285 */ 'f', '2', '9', 0,
1182  /* 289 */ 'f', '9', 0,
1183  /* 292 */ 'i', 'c', 'c', 0,
1184  /* 296 */ 'f', 'p', 0,
1185  /* 299 */ 's', 'p', 0,
1186  /* 302 */ 'y', 0,
1187  };
1188 
1189  static const uint16_t RegAsmOffset[] = {
1190  292, 302, 29, 105, 168, 226, 278, 0, 76, 148, 206, 258, 4, 80,
1191  152, 210, 262, 8, 84, 156, 214, 266, 12, 88, 160, 218, 270, 16,
1192  92, 164, 222, 274, 20, 96, 29, 61, 105, 133, 168, 191, 226, 243,
1193  278, 289, 0, 44, 76, 120, 148, 183, 206, 235, 258, 281, 4, 48,
1194  80, 124, 152, 187, 210, 239, 262, 285, 8, 52, 24, 56, 100, 128,
1195  32, 64, 108, 136, 171, 194, 229, 246, 35, 67, 111, 139, 174, 197,
1196  296, 249, 38, 70, 114, 142, 177, 200, 232, 252, 41, 73, 117, 145,
1197  180, 203, 299, 255, 29, 168, 278, 76, 206, 4, 152, 262, 84, 214,
1198  12, 160, 270, 92, 222, 20,
1199  };
1200 
1201  //int i;
1202  //for (i = 0; i < sizeof(RegAsmOffset)/2; i++)
1203  // printf("%s = %u\n", AsmStrs+RegAsmOffset[i], i + 1);
1204  //printf("*************************\n");
1205  if (RegNo < 1 || RegNo > sizeof (RegAsmOffset) / sizeof (*RegAsmOffset)) {
1206  return NULL;
1207  }
1208  return AsmStrs+RegAsmOffset[RegNo-1];
1209 #else
1210  return NULL;
1211 #endif
1212 }
1213 
1214 #ifdef PRINT_ALIAS_INSTR
1215 #undef PRINT_ALIAS_INSTR
1216 
1217 static void printCustomAliasOperand(MCInst *MI, unsigned OpIdx,
1218  unsigned PrintMethodIdx, SStream *OS)
1219 {
1220 }
1221 
1222 static char *printAliasInstr(MCInst *MI, SStream *OS, void *info)
1223 {
1224  #define GETREGCLASS_CONTAIN(_class, _reg) MCRegisterClass_contains(MCRegisterInfo_getRegClass(MRI, _class), MCOperand_getReg(MCInst_getOperand(MI, _reg)))
1225  const char *AsmString;
1226  char *tmp, *AsmMnem, *AsmOps, *c;
1227  int OpIdx, PrintMethodIdx;
1228  MCRegisterInfo *MRI = (MCRegisterInfo *)info;
1229  switch (MCInst_getOpcode(MI)) {
1230  default: return NULL;
1231  case SP_BCOND:
1232  if (MCInst_getNumOperands(MI) == 2 &&
1233  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1234  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1235  // (BCOND brtarget:$imm, 8)
1236  AsmString = "ba $\x01";
1237  break;
1238  }
1239  if (MCInst_getNumOperands(MI) == 2 &&
1240  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1241  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1242  // (BCOND brtarget:$imm, 0)
1243  AsmString = "bn $\x01";
1244  break;
1245  }
1246  if (MCInst_getNumOperands(MI) == 2 &&
1247  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1248  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1249  // (BCOND brtarget:$imm, 9)
1250  AsmString = "bne $\x01";
1251  break;
1252  }
1253  if (MCInst_getNumOperands(MI) == 2 &&
1254  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1255  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1256  // (BCOND brtarget:$imm, 1)
1257  AsmString = "be $\x01";
1258  break;
1259  }
1260  if (MCInst_getNumOperands(MI) == 2 &&
1261  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1262  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1263  // (BCOND brtarget:$imm, 10)
1264  AsmString = "bg $\x01";
1265  break;
1266  }
1267  if (MCInst_getNumOperands(MI) == 2 &&
1268  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1269  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1270  // (BCOND brtarget:$imm, 2)
1271  AsmString = "ble $\x01";
1272  break;
1273  }
1274  if (MCInst_getNumOperands(MI) == 2 &&
1275  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1276  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1277  // (BCOND brtarget:$imm, 11)
1278  AsmString = "bge $\x01";
1279  break;
1280  }
1281  if (MCInst_getNumOperands(MI) == 2 &&
1282  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1283  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1284  // (BCOND brtarget:$imm, 3)
1285  AsmString = "bl $\x01";
1286  break;
1287  }
1288  if (MCInst_getNumOperands(MI) == 2 &&
1289  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1290  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1291  // (BCOND brtarget:$imm, 12)
1292  AsmString = "bgu $\x01";
1293  break;
1294  }
1295  if (MCInst_getNumOperands(MI) == 2 &&
1296  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1297  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1298  // (BCOND brtarget:$imm, 4)
1299  AsmString = "bleu $\x01";
1300  break;
1301  }
1302  if (MCInst_getNumOperands(MI) == 2 &&
1303  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1304  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1305  // (BCOND brtarget:$imm, 13)
1306  AsmString = "bcc $\x01";
1307  break;
1308  }
1309  if (MCInst_getNumOperands(MI) == 2 &&
1310  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1311  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1312  // (BCOND brtarget:$imm, 5)
1313  AsmString = "bcs $\x01";
1314  break;
1315  }
1316  if (MCInst_getNumOperands(MI) == 2 &&
1317  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1318  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1319  // (BCOND brtarget:$imm, 14)
1320  AsmString = "bpos $\x01";
1321  break;
1322  }
1323  if (MCInst_getNumOperands(MI) == 2 &&
1324  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1325  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1326  // (BCOND brtarget:$imm, 6)
1327  AsmString = "bneg $\x01";
1328  break;
1329  }
1330  if (MCInst_getNumOperands(MI) == 2 &&
1331  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1332  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1333  // (BCOND brtarget:$imm, 15)
1334  AsmString = "bvc $\x01";
1335  break;
1336  }
1337  if (MCInst_getNumOperands(MI) == 2 &&
1338  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1339  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1340  // (BCOND brtarget:$imm, 7)
1341  AsmString = "bvs $\x01";
1342  break;
1343  }
1344  return NULL;
1345  case SP_BCONDA:
1346  if (MCInst_getNumOperands(MI) == 2 &&
1347  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1348  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1349  // (BCONDA brtarget:$imm, 8)
1350  AsmString = "ba,a $\x01";
1351  break;
1352  }
1353  if (MCInst_getNumOperands(MI) == 2 &&
1354  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1355  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1356  // (BCONDA brtarget:$imm, 0)
1357  AsmString = "bn,a $\x01";
1358  break;
1359  }
1360  if (MCInst_getNumOperands(MI) == 2 &&
1361  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1362  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1363  // (BCONDA brtarget:$imm, 9)
1364  AsmString = "bne,a $\x01";
1365  break;
1366  }
1367  if (MCInst_getNumOperands(MI) == 2 &&
1368  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1369  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1370  // (BCONDA brtarget:$imm, 1)
1371  AsmString = "be,a $\x01";
1372  break;
1373  }
1374  if (MCInst_getNumOperands(MI) == 2 &&
1375  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1376  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1377  // (BCONDA brtarget:$imm, 10)
1378  AsmString = "bg,a $\x01";
1379  break;
1380  }
1381  if (MCInst_getNumOperands(MI) == 2 &&
1382  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1383  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1384  // (BCONDA brtarget:$imm, 2)
1385  AsmString = "ble,a $\x01";
1386  break;
1387  }
1388  if (MCInst_getNumOperands(MI) == 2 &&
1389  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1390  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1391  // (BCONDA brtarget:$imm, 11)
1392  AsmString = "bge,a $\x01";
1393  break;
1394  }
1395  if (MCInst_getNumOperands(MI) == 2 &&
1396  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1397  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1398  // (BCONDA brtarget:$imm, 3)
1399  AsmString = "bl,a $\x01";
1400  break;
1401  }
1402  if (MCInst_getNumOperands(MI) == 2 &&
1403  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1404  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1405  // (BCONDA brtarget:$imm, 12)
1406  AsmString = "bgu,a $\x01";
1407  break;
1408  }
1409  if (MCInst_getNumOperands(MI) == 2 &&
1410  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1411  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1412  // (BCONDA brtarget:$imm, 4)
1413  AsmString = "bleu,a $\x01";
1414  break;
1415  }
1416  if (MCInst_getNumOperands(MI) == 2 &&
1417  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1418  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1419  // (BCONDA brtarget:$imm, 13)
1420  AsmString = "bcc,a $\x01";
1421  break;
1422  }
1423  if (MCInst_getNumOperands(MI) == 2 &&
1424  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1425  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1426  // (BCONDA brtarget:$imm, 5)
1427  AsmString = "bcs,a $\x01";
1428  break;
1429  }
1430  if (MCInst_getNumOperands(MI) == 2 &&
1431  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1432  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1433  // (BCONDA brtarget:$imm, 14)
1434  AsmString = "bpos,a $\x01";
1435  break;
1436  }
1437  if (MCInst_getNumOperands(MI) == 2 &&
1438  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1439  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1440  // (BCONDA brtarget:$imm, 6)
1441  AsmString = "bneg,a $\x01";
1442  break;
1443  }
1444  if (MCInst_getNumOperands(MI) == 2 &&
1445  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1446  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1447  // (BCONDA brtarget:$imm, 15)
1448  AsmString = "bvc,a $\x01";
1449  break;
1450  }
1451  if (MCInst_getNumOperands(MI) == 2 &&
1452  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1453  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1454  // (BCONDA brtarget:$imm, 7)
1455  AsmString = "bvs,a $\x01";
1456  break;
1457  }
1458  return NULL;
1459  case SP_BPFCCANT:
1460  if (MCInst_getNumOperands(MI) == 3 &&
1461  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1462  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1463  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1464  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1465  // (BPFCCANT brtarget:$imm, 0, FCCRegs:$cc)
1466  AsmString = "fba,a,pn $\x03, $\x01";
1467  break;
1468  }
1469  if (MCInst_getNumOperands(MI) == 3 &&
1470  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1471  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1472  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1473  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1474  // (BPFCCANT brtarget:$imm, 8, FCCRegs:$cc)
1475  AsmString = "fbn,a,pn $\x03, $\x01";
1476  break;
1477  }
1478  if (MCInst_getNumOperands(MI) == 3 &&
1479  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1480  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1481  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1482  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1483  // (BPFCCANT brtarget:$imm, 7, FCCRegs:$cc)
1484  AsmString = "fbu,a,pn $\x03, $\x01";
1485  break;
1486  }
1487  if (MCInst_getNumOperands(MI) == 3 &&
1488  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1489  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1490  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1491  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1492  // (BPFCCANT brtarget:$imm, 6, FCCRegs:$cc)
1493  AsmString = "fbg,a,pn $\x03, $\x01";
1494  break;
1495  }
1496  if (MCInst_getNumOperands(MI) == 3 &&
1497  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1498  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1499  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1500  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1501  // (BPFCCANT brtarget:$imm, 5, FCCRegs:$cc)
1502  AsmString = "fbug,a,pn $\x03, $\x01";
1503  break;
1504  }
1505  if (MCInst_getNumOperands(MI) == 3 &&
1506  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1507  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1508  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1509  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1510  // (BPFCCANT brtarget:$imm, 4, FCCRegs:$cc)
1511  AsmString = "fbl,a,pn $\x03, $\x01";
1512  break;
1513  }
1514  if (MCInst_getNumOperands(MI) == 3 &&
1515  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1516  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1517  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1518  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1519  // (BPFCCANT brtarget:$imm, 3, FCCRegs:$cc)
1520  AsmString = "fbul,a,pn $\x03, $\x01";
1521  break;
1522  }
1523  if (MCInst_getNumOperands(MI) == 3 &&
1524  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1525  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1526  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1527  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1528  // (BPFCCANT brtarget:$imm, 2, FCCRegs:$cc)
1529  AsmString = "fblg,a,pn $\x03, $\x01";
1530  break;
1531  }
1532  if (MCInst_getNumOperands(MI) == 3 &&
1533  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1534  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1535  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1536  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1537  // (BPFCCANT brtarget:$imm, 1, FCCRegs:$cc)
1538  AsmString = "fbne,a,pn $\x03, $\x01";
1539  break;
1540  }
1541  if (MCInst_getNumOperands(MI) == 3 &&
1542  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1543  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1544  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1545  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1546  // (BPFCCANT brtarget:$imm, 9, FCCRegs:$cc)
1547  AsmString = "fbe,a,pn $\x03, $\x01";
1548  break;
1549  }
1550  if (MCInst_getNumOperands(MI) == 3 &&
1551  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1552  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1553  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1554  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1555  // (BPFCCANT brtarget:$imm, 10, FCCRegs:$cc)
1556  AsmString = "fbue,a,pn $\x03, $\x01";
1557  break;
1558  }
1559  if (MCInst_getNumOperands(MI) == 3 &&
1560  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1561  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1562  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1563  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1564  // (BPFCCANT brtarget:$imm, 11, FCCRegs:$cc)
1565  AsmString = "fbge,a,pn $\x03, $\x01";
1566  break;
1567  }
1568  if (MCInst_getNumOperands(MI) == 3 &&
1569  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1570  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1571  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1572  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1573  // (BPFCCANT brtarget:$imm, 12, FCCRegs:$cc)
1574  AsmString = "fbuge,a,pn $\x03, $\x01";
1575  break;
1576  }
1577  if (MCInst_getNumOperands(MI) == 3 &&
1578  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1579  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1580  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1581  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1582  // (BPFCCANT brtarget:$imm, 13, FCCRegs:$cc)
1583  AsmString = "fble,a,pn $\x03, $\x01";
1584  break;
1585  }
1586  if (MCInst_getNumOperands(MI) == 3 &&
1587  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1588  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1589  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1590  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1591  // (BPFCCANT brtarget:$imm, 14, FCCRegs:$cc)
1592  AsmString = "fbule,a,pn $\x03, $\x01";
1593  break;
1594  }
1595  if (MCInst_getNumOperands(MI) == 3 &&
1596  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1597  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1598  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1599  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1600  // (BPFCCANT brtarget:$imm, 15, FCCRegs:$cc)
1601  AsmString = "fbo,a,pn $\x03, $\x01";
1602  break;
1603  }
1604  return NULL;
1605  case SP_BPFCCNT:
1606  if (MCInst_getNumOperands(MI) == 3 &&
1607  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1608  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0 &&
1609  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1610  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1611  // (BPFCCNT brtarget:$imm, 0, FCCRegs:$cc)
1612  AsmString = "fba,pn $\x03, $\x01";
1613  break;
1614  }
1615  if (MCInst_getNumOperands(MI) == 3 &&
1616  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1617  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8 &&
1618  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1619  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1620  // (BPFCCNT brtarget:$imm, 8, FCCRegs:$cc)
1621  AsmString = "fbn,pn $\x03, $\x01";
1622  break;
1623  }
1624  if (MCInst_getNumOperands(MI) == 3 &&
1625  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1626  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7 &&
1627  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1628  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1629  // (BPFCCNT brtarget:$imm, 7, FCCRegs:$cc)
1630  AsmString = "fbu,pn $\x03, $\x01";
1631  break;
1632  }
1633  if (MCInst_getNumOperands(MI) == 3 &&
1634  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1635  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6 &&
1636  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1637  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1638  // (BPFCCNT brtarget:$imm, 6, FCCRegs:$cc)
1639  AsmString = "fbg,pn $\x03, $\x01";
1640  break;
1641  }
1642  if (MCInst_getNumOperands(MI) == 3 &&
1643  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1644  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5 &&
1645  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1646  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1647  // (BPFCCNT brtarget:$imm, 5, FCCRegs:$cc)
1648  AsmString = "fbug,pn $\x03, $\x01";
1649  break;
1650  }
1651  if (MCInst_getNumOperands(MI) == 3 &&
1652  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1653  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4 &&
1654  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1655  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1656  // (BPFCCNT brtarget:$imm, 4, FCCRegs:$cc)
1657  AsmString = "fbl,pn $\x03, $\x01";
1658  break;
1659  }
1660  if (MCInst_getNumOperands(MI) == 3 &&
1661  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1662  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3 &&
1663  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1664  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1665  // (BPFCCNT brtarget:$imm, 3, FCCRegs:$cc)
1666  AsmString = "fbul,pn $\x03, $\x01";
1667  break;
1668  }
1669  if (MCInst_getNumOperands(MI) == 3 &&
1670  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1671  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2 &&
1672  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1673  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1674  // (BPFCCNT brtarget:$imm, 2, FCCRegs:$cc)
1675  AsmString = "fblg,pn $\x03, $\x01";
1676  break;
1677  }
1678  if (MCInst_getNumOperands(MI) == 3 &&
1679  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1680  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1 &&
1681  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1682  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1683  // (BPFCCNT brtarget:$imm, 1, FCCRegs:$cc)
1684  AsmString = "fbne,pn $\x03, $\x01";
1685  break;
1686  }
1687  if (MCInst_getNumOperands(MI) == 3 &&
1688  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1689  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9 &&
1690  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1691  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1692  // (BPFCCNT brtarget:$imm, 9, FCCRegs:$cc)
1693  AsmString = "fbe,pn $\x03, $\x01";
1694  break;
1695  }
1696  if (MCInst_getNumOperands(MI) == 3 &&
1697  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1698  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10 &&
1699  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1700  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1701  // (BPFCCNT brtarget:$imm, 10, FCCRegs:$cc)
1702  AsmString = "fbue,pn $\x03, $\x01";
1703  break;
1704  }
1705  if (MCInst_getNumOperands(MI) == 3 &&
1706  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1707  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11 &&
1708  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1709  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1710  // (BPFCCNT brtarget:$imm, 11, FCCRegs:$cc)
1711  AsmString = "fbge,pn $\x03, $\x01";
1712  break;
1713  }
1714  if (MCInst_getNumOperands(MI) == 3 &&
1715  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1716  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12 &&
1717  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1718  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1719  // (BPFCCNT brtarget:$imm, 12, FCCRegs:$cc)
1720  AsmString = "fbuge,pn $\x03, $\x01";
1721  break;
1722  }
1723  if (MCInst_getNumOperands(MI) == 3 &&
1724  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1725  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13 &&
1726  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1727  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1728  // (BPFCCNT brtarget:$imm, 13, FCCRegs:$cc)
1729  AsmString = "fble,pn $\x03, $\x01";
1730  break;
1731  }
1732  if (MCInst_getNumOperands(MI) == 3 &&
1733  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1734  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14 &&
1735  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1736  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1737  // (BPFCCNT brtarget:$imm, 14, FCCRegs:$cc)
1738  AsmString = "fbule,pn $\x03, $\x01";
1739  break;
1740  }
1741  if (MCInst_getNumOperands(MI) == 3 &&
1742  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1743  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15 &&
1744  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
1745  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 2)) {
1746  // (BPFCCNT brtarget:$imm, 15, FCCRegs:$cc)
1747  AsmString = "fbo,pn $\x03, $\x01";
1748  break;
1749  }
1750  return NULL;
1751  case SP_BPICCANT:
1752  if (MCInst_getNumOperands(MI) == 2 &&
1753  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1754  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1755  // (BPICCANT brtarget:$imm, 8)
1756  AsmString = "ba,a,pn %icc, $\x01";
1757  break;
1758  }
1759  if (MCInst_getNumOperands(MI) == 2 &&
1760  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1761  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1762  // (BPICCANT brtarget:$imm, 0)
1763  AsmString = "bn,a,pn %icc, $\x01";
1764  break;
1765  }
1766  if (MCInst_getNumOperands(MI) == 2 &&
1767  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1768  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1769  // (BPICCANT brtarget:$imm, 9)
1770  AsmString = "bne,a,pn %icc, $\x01";
1771  break;
1772  }
1773  if (MCInst_getNumOperands(MI) == 2 &&
1774  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1775  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1776  // (BPICCANT brtarget:$imm, 1)
1777  AsmString = "be,a,pn %icc, $\x01";
1778  break;
1779  }
1780  if (MCInst_getNumOperands(MI) == 2 &&
1781  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1782  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1783  // (BPICCANT brtarget:$imm, 10)
1784  AsmString = "bg,a,pn %icc, $\x01";
1785  break;
1786  }
1787  if (MCInst_getNumOperands(MI) == 2 &&
1788  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1789  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1790  // (BPICCANT brtarget:$imm, 2)
1791  AsmString = "ble,a,pn %icc, $\x01";
1792  break;
1793  }
1794  if (MCInst_getNumOperands(MI) == 2 &&
1795  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1796  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1797  // (BPICCANT brtarget:$imm, 11)
1798  AsmString = "bge,a,pn %icc, $\x01";
1799  break;
1800  }
1801  if (MCInst_getNumOperands(MI) == 2 &&
1802  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1803  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1804  // (BPICCANT brtarget:$imm, 3)
1805  AsmString = "bl,a,pn %icc, $\x01";
1806  break;
1807  }
1808  if (MCInst_getNumOperands(MI) == 2 &&
1809  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1810  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1811  // (BPICCANT brtarget:$imm, 12)
1812  AsmString = "bgu,a,pn %icc, $\x01";
1813  break;
1814  }
1815  if (MCInst_getNumOperands(MI) == 2 &&
1816  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1817  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1818  // (BPICCANT brtarget:$imm, 4)
1819  AsmString = "bleu,a,pn %icc, $\x01";
1820  break;
1821  }
1822  if (MCInst_getNumOperands(MI) == 2 &&
1823  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1824  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1825  // (BPICCANT brtarget:$imm, 13)
1826  AsmString = "bcc,a,pn %icc, $\x01";
1827  break;
1828  }
1829  if (MCInst_getNumOperands(MI) == 2 &&
1830  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1831  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1832  // (BPICCANT brtarget:$imm, 5)
1833  AsmString = "bcs,a,pn %icc, $\x01";
1834  break;
1835  }
1836  if (MCInst_getNumOperands(MI) == 2 &&
1837  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1838  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1839  // (BPICCANT brtarget:$imm, 14)
1840  AsmString = "bpos,a,pn %icc, $\x01";
1841  break;
1842  }
1843  if (MCInst_getNumOperands(MI) == 2 &&
1844  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1845  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1846  // (BPICCANT brtarget:$imm, 6)
1847  AsmString = "bneg,a,pn %icc, $\x01";
1848  break;
1849  }
1850  if (MCInst_getNumOperands(MI) == 2 &&
1851  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1852  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1853  // (BPICCANT brtarget:$imm, 15)
1854  AsmString = "bvc,a,pn %icc, $\x01";
1855  break;
1856  }
1857  if (MCInst_getNumOperands(MI) == 2 &&
1858  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1859  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1860  // (BPICCANT brtarget:$imm, 7)
1861  AsmString = "bvs,a,pn %icc, $\x01";
1862  break;
1863  }
1864  return NULL;
1865  case SP_BPICCNT:
1866  if (MCInst_getNumOperands(MI) == 2 &&
1867  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1868  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1869  // (BPICCNT brtarget:$imm, 8)
1870  AsmString = "ba,pn %icc, $\x01";
1871  break;
1872  }
1873  if (MCInst_getNumOperands(MI) == 2 &&
1874  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1875  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1876  // (BPICCNT brtarget:$imm, 0)
1877  AsmString = "bn,pn %icc, $\x01";
1878  break;
1879  }
1880  if (MCInst_getNumOperands(MI) == 2 &&
1881  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1882  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1883  // (BPICCNT brtarget:$imm, 9)
1884  AsmString = "bne,pn %icc, $\x01";
1885  break;
1886  }
1887  if (MCInst_getNumOperands(MI) == 2 &&
1888  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1889  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
1890  // (BPICCNT brtarget:$imm, 1)
1891  AsmString = "be,pn %icc, $\x01";
1892  break;
1893  }
1894  if (MCInst_getNumOperands(MI) == 2 &&
1895  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1896  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
1897  // (BPICCNT brtarget:$imm, 10)
1898  AsmString = "bg,pn %icc, $\x01";
1899  break;
1900  }
1901  if (MCInst_getNumOperands(MI) == 2 &&
1902  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1903  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
1904  // (BPICCNT brtarget:$imm, 2)
1905  AsmString = "ble,pn %icc, $\x01";
1906  break;
1907  }
1908  if (MCInst_getNumOperands(MI) == 2 &&
1909  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1910  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
1911  // (BPICCNT brtarget:$imm, 11)
1912  AsmString = "bge,pn %icc, $\x01";
1913  break;
1914  }
1915  if (MCInst_getNumOperands(MI) == 2 &&
1916  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1917  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
1918  // (BPICCNT brtarget:$imm, 3)
1919  AsmString = "bl,pn %icc, $\x01";
1920  break;
1921  }
1922  if (MCInst_getNumOperands(MI) == 2 &&
1923  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1924  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
1925  // (BPICCNT brtarget:$imm, 12)
1926  AsmString = "bgu,pn %icc, $\x01";
1927  break;
1928  }
1929  if (MCInst_getNumOperands(MI) == 2 &&
1930  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1931  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
1932  // (BPICCNT brtarget:$imm, 4)
1933  AsmString = "bleu,pn %icc, $\x01";
1934  break;
1935  }
1936  if (MCInst_getNumOperands(MI) == 2 &&
1937  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1938  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
1939  // (BPICCNT brtarget:$imm, 13)
1940  AsmString = "bcc,pn %icc, $\x01";
1941  break;
1942  }
1943  if (MCInst_getNumOperands(MI) == 2 &&
1944  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1945  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
1946  // (BPICCNT brtarget:$imm, 5)
1947  AsmString = "bcs,pn %icc, $\x01";
1948  break;
1949  }
1950  if (MCInst_getNumOperands(MI) == 2 &&
1951  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1952  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
1953  // (BPICCNT brtarget:$imm, 14)
1954  AsmString = "bpos,pn %icc, $\x01";
1955  break;
1956  }
1957  if (MCInst_getNumOperands(MI) == 2 &&
1958  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1959  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
1960  // (BPICCNT brtarget:$imm, 6)
1961  AsmString = "bneg,pn %icc, $\x01";
1962  break;
1963  }
1964  if (MCInst_getNumOperands(MI) == 2 &&
1965  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1966  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
1967  // (BPICCNT brtarget:$imm, 15)
1968  AsmString = "bvc,pn %icc, $\x01";
1969  break;
1970  }
1971  if (MCInst_getNumOperands(MI) == 2 &&
1972  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1973  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
1974  // (BPICCNT brtarget:$imm, 7)
1975  AsmString = "bvs,pn %icc, $\x01";
1976  break;
1977  }
1978  return NULL;
1979  case SP_BPXCCANT:
1980  if (MCInst_getNumOperands(MI) == 2 &&
1981  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1982  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
1983  // (BPXCCANT brtarget:$imm, 8)
1984  AsmString = "ba,a,pn %xcc, $\x01";
1985  break;
1986  }
1987  if (MCInst_getNumOperands(MI) == 2 &&
1988  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1989  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
1990  // (BPXCCANT brtarget:$imm, 0)
1991  AsmString = "bn,a,pn %xcc, $\x01";
1992  break;
1993  }
1994  if (MCInst_getNumOperands(MI) == 2 &&
1995  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
1996  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
1997  // (BPXCCANT brtarget:$imm, 9)
1998  AsmString = "bne,a,pn %xcc, $\x01";
1999  break;
2000  }
2001  if (MCInst_getNumOperands(MI) == 2 &&
2002  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2003  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
2004  // (BPXCCANT brtarget:$imm, 1)
2005  AsmString = "be,a,pn %xcc, $\x01";
2006  break;
2007  }
2008  if (MCInst_getNumOperands(MI) == 2 &&
2009  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2010  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2011  // (BPXCCANT brtarget:$imm, 10)
2012  AsmString = "bg,a,pn %xcc, $\x01";
2013  break;
2014  }
2015  if (MCInst_getNumOperands(MI) == 2 &&
2016  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2017  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2018  // (BPXCCANT brtarget:$imm, 2)
2019  AsmString = "ble,a,pn %xcc, $\x01";
2020  break;
2021  }
2022  if (MCInst_getNumOperands(MI) == 2 &&
2023  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2024  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2025  // (BPXCCANT brtarget:$imm, 11)
2026  AsmString = "bge,a,pn %xcc, $\x01";
2027  break;
2028  }
2029  if (MCInst_getNumOperands(MI) == 2 &&
2030  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2031  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2032  // (BPXCCANT brtarget:$imm, 3)
2033  AsmString = "bl,a,pn %xcc, $\x01";
2034  break;
2035  }
2036  if (MCInst_getNumOperands(MI) == 2 &&
2037  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2038  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2039  // (BPXCCANT brtarget:$imm, 12)
2040  AsmString = "bgu,a,pn %xcc, $\x01";
2041  break;
2042  }
2043  if (MCInst_getNumOperands(MI) == 2 &&
2044  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2045  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2046  // (BPXCCANT brtarget:$imm, 4)
2047  AsmString = "bleu,a,pn %xcc, $\x01";
2048  break;
2049  }
2050  if (MCInst_getNumOperands(MI) == 2 &&
2051  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2052  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2053  // (BPXCCANT brtarget:$imm, 13)
2054  AsmString = "bcc,a,pn %xcc, $\x01";
2055  break;
2056  }
2057  if (MCInst_getNumOperands(MI) == 2 &&
2058  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2059  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2060  // (BPXCCANT brtarget:$imm, 5)
2061  AsmString = "bcs,a,pn %xcc, $\x01";
2062  break;
2063  }
2064  if (MCInst_getNumOperands(MI) == 2 &&
2065  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2066  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2067  // (BPXCCANT brtarget:$imm, 14)
2068  AsmString = "bpos,a,pn %xcc, $\x01";
2069  break;
2070  }
2071  if (MCInst_getNumOperands(MI) == 2 &&
2072  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2073  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2074  // (BPXCCANT brtarget:$imm, 6)
2075  AsmString = "bneg,a,pn %xcc, $\x01";
2076  break;
2077  }
2078  if (MCInst_getNumOperands(MI) == 2 &&
2079  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2080  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2081  // (BPXCCANT brtarget:$imm, 15)
2082  AsmString = "bvc,a,pn %xcc, $\x01";
2083  break;
2084  }
2085  if (MCInst_getNumOperands(MI) == 2 &&
2086  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2087  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2088  // (BPXCCANT brtarget:$imm, 7)
2089  AsmString = "bvs,a,pn %xcc, $\x01";
2090  break;
2091  }
2092  return NULL;
2093  case SP_BPXCCNT:
2094  if (MCInst_getNumOperands(MI) == 2 &&
2095  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2096  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 8) {
2097  // (BPXCCNT brtarget:$imm, 8)
2098  AsmString = "ba,pn %xcc, $\x01";
2099  break;
2100  }
2101  if (MCInst_getNumOperands(MI) == 2 &&
2102  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2103  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 0) {
2104  // (BPXCCNT brtarget:$imm, 0)
2105  AsmString = "bn,pn %xcc, $\x01";
2106  break;
2107  }
2108  if (MCInst_getNumOperands(MI) == 2 &&
2109  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2110  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 9) {
2111  // (BPXCCNT brtarget:$imm, 9)
2112  AsmString = "bne,pn %xcc, $\x01";
2113  break;
2114  }
2115  if (MCInst_getNumOperands(MI) == 2 &&
2116  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2117  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 1) {
2118  // (BPXCCNT brtarget:$imm, 1)
2119  AsmString = "be,pn %xcc, $\x01";
2120  break;
2121  }
2122  if (MCInst_getNumOperands(MI) == 2 &&
2123  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2124  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 10) {
2125  // (BPXCCNT brtarget:$imm, 10)
2126  AsmString = "bg,pn %xcc, $\x01";
2127  break;
2128  }
2129  if (MCInst_getNumOperands(MI) == 2 &&
2130  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2131  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 2) {
2132  // (BPXCCNT brtarget:$imm, 2)
2133  AsmString = "ble,pn %xcc, $\x01";
2134  break;
2135  }
2136  if (MCInst_getNumOperands(MI) == 2 &&
2137  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2138  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 11) {
2139  // (BPXCCNT brtarget:$imm, 11)
2140  AsmString = "bge,pn %xcc, $\x01";
2141  break;
2142  }
2143  if (MCInst_getNumOperands(MI) == 2 &&
2144  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2145  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 3) {
2146  // (BPXCCNT brtarget:$imm, 3)
2147  AsmString = "bl,pn %xcc, $\x01";
2148  break;
2149  }
2150  if (MCInst_getNumOperands(MI) == 2 &&
2151  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2152  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 12) {
2153  // (BPXCCNT brtarget:$imm, 12)
2154  AsmString = "bgu,pn %xcc, $\x01";
2155  break;
2156  }
2157  if (MCInst_getNumOperands(MI) == 2 &&
2158  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2159  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 4) {
2160  // (BPXCCNT brtarget:$imm, 4)
2161  AsmString = "bleu,pn %xcc, $\x01";
2162  break;
2163  }
2164  if (MCInst_getNumOperands(MI) == 2 &&
2165  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2166  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 13) {
2167  // (BPXCCNT brtarget:$imm, 13)
2168  AsmString = "bcc,pn %xcc, $\x01";
2169  break;
2170  }
2171  if (MCInst_getNumOperands(MI) == 2 &&
2172  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2173  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 5) {
2174  // (BPXCCNT brtarget:$imm, 5)
2175  AsmString = "bcs,pn %xcc, $\x01";
2176  break;
2177  }
2178  if (MCInst_getNumOperands(MI) == 2 &&
2179  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2180  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 14) {
2181  // (BPXCCNT brtarget:$imm, 14)
2182  AsmString = "bpos,pn %xcc, $\x01";
2183  break;
2184  }
2185  if (MCInst_getNumOperands(MI) == 2 &&
2186  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2187  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 6) {
2188  // (BPXCCNT brtarget:$imm, 6)
2189  AsmString = "bneg,pn %xcc, $\x01";
2190  break;
2191  }
2192  if (MCInst_getNumOperands(MI) == 2 &&
2193  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2194  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 15) {
2195  // (BPXCCNT brtarget:$imm, 15)
2196  AsmString = "bvc,pn %xcc, $\x01";
2197  break;
2198  }
2199  if (MCInst_getNumOperands(MI) == 2 &&
2200  MCOperand_isImm(MCInst_getOperand(MI, 1)) &&
2201  MCOperand_getImm(MCInst_getOperand(MI, 1)) == 7) {
2202  // (BPXCCNT brtarget:$imm, 7)
2203  AsmString = "bvs,pn %xcc, $\x01";
2204  break;
2205  }
2206  return NULL;
2207  case SP_FMOVD_ICC:
2208  if (MCInst_getNumOperands(MI) == 3 &&
2209  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2210  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2211  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2212  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2213  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2214  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2215  // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 8)
2216  AsmString = "fmovda %icc, $\x02, $\x01";
2217  break;
2218  }
2219  if (MCInst_getNumOperands(MI) == 3 &&
2220  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2221  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2222  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2223  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2224  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2225  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2226  // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 0)
2227  AsmString = "fmovdn %icc, $\x02, $\x01";
2228  break;
2229  }
2230  if (MCInst_getNumOperands(MI) == 3 &&
2231  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2232  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2233  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2234  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2235  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2236  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2237  // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 9)
2238  AsmString = "fmovdne %icc, $\x02, $\x01";
2239  break;
2240  }
2241  if (MCInst_getNumOperands(MI) == 3 &&
2242  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2243  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2244  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2245  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2246  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2247  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2248  // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 1)
2249  AsmString = "fmovde %icc, $\x02, $\x01";
2250  break;
2251  }
2252  if (MCInst_getNumOperands(MI) == 3 &&
2253  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2254  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2255  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2256  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2257  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2258  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2259  // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 10)
2260  AsmString = "fmovdg %icc, $\x02, $\x01";
2261  break;
2262  }
2263  if (MCInst_getNumOperands(MI) == 3 &&
2264  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2265  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2266  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2267  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2268  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2269  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2270  // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 2)
2271  AsmString = "fmovdle %icc, $\x02, $\x01";
2272  break;
2273  }
2274  if (MCInst_getNumOperands(MI) == 3 &&
2275  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2276  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2277  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2278  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2279  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2280  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2281  // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 11)
2282  AsmString = "fmovdge %icc, $\x02, $\x01";
2283  break;
2284  }
2285  if (MCInst_getNumOperands(MI) == 3 &&
2286  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2287  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2288  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2289  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2290  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2291  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2292  // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 3)
2293  AsmString = "fmovdl %icc, $\x02, $\x01";
2294  break;
2295  }
2296  if (MCInst_getNumOperands(MI) == 3 &&
2297  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2298  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2299  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2300  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2301  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2302  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2303  // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 12)
2304  AsmString = "fmovdgu %icc, $\x02, $\x01";
2305  break;
2306  }
2307  if (MCInst_getNumOperands(MI) == 3 &&
2308  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2309  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2310  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2311  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2312  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2313  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2314  // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 4)
2315  AsmString = "fmovdleu %icc, $\x02, $\x01";
2316  break;
2317  }
2318  if (MCInst_getNumOperands(MI) == 3 &&
2319  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2320  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2321  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2322  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2323  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2324  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2325  // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 13)
2326  AsmString = "fmovdcc %icc, $\x02, $\x01";
2327  break;
2328  }
2329  if (MCInst_getNumOperands(MI) == 3 &&
2330  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2331  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2332  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2333  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2334  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2335  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2336  // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 5)
2337  AsmString = "fmovdcs %icc, $\x02, $\x01";
2338  break;
2339  }
2340  if (MCInst_getNumOperands(MI) == 3 &&
2341  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2342  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2343  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2344  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2345  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2346  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2347  // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 14)
2348  AsmString = "fmovdpos %icc, $\x02, $\x01";
2349  break;
2350  }
2351  if (MCInst_getNumOperands(MI) == 3 &&
2352  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2353  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2354  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2355  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2356  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2357  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2358  // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 6)
2359  AsmString = "fmovdneg %icc, $\x02, $\x01";
2360  break;
2361  }
2362  if (MCInst_getNumOperands(MI) == 3 &&
2363  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2364  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2365  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2366  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2367  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2368  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2369  // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 15)
2370  AsmString = "fmovdvc %icc, $\x02, $\x01";
2371  break;
2372  }
2373  if (MCInst_getNumOperands(MI) == 3 &&
2374  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2375  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2376  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2377  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2378  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2379  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2380  // (FMOVD_ICC DFPRegs:$rd, DFPRegs:$rs2, 7)
2381  AsmString = "fmovdvs %icc, $\x02, $\x01";
2382  break;
2383  }
2384  return NULL;
2385  case SP_FMOVD_XCC:
2386  if (MCInst_getNumOperands(MI) == 3 &&
2387  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2388  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2389  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2390  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2391  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2392  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2393  // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 8)
2394  AsmString = "fmovda %xcc, $\x02, $\x01";
2395  break;
2396  }
2397  if (MCInst_getNumOperands(MI) == 3 &&
2398  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2399  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2400  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2401  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2402  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2403  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2404  // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 0)
2405  AsmString = "fmovdn %xcc, $\x02, $\x01";
2406  break;
2407  }
2408  if (MCInst_getNumOperands(MI) == 3 &&
2409  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2410  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2411  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2412  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2413  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2414  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2415  // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 9)
2416  AsmString = "fmovdne %xcc, $\x02, $\x01";
2417  break;
2418  }
2419  if (MCInst_getNumOperands(MI) == 3 &&
2420  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2421  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2422  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2423  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2424  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2425  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2426  // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 1)
2427  AsmString = "fmovde %xcc, $\x02, $\x01";
2428  break;
2429  }
2430  if (MCInst_getNumOperands(MI) == 3 &&
2431  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2432  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2433  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2434  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2435  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2436  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2437  // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 10)
2438  AsmString = "fmovdg %xcc, $\x02, $\x01";
2439  break;
2440  }
2441  if (MCInst_getNumOperands(MI) == 3 &&
2442  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2443  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2444  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2445  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2446  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2447  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2448  // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 2)
2449  AsmString = "fmovdle %xcc, $\x02, $\x01";
2450  break;
2451  }
2452  if (MCInst_getNumOperands(MI) == 3 &&
2453  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2454  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2455  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2456  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2457  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2458  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2459  // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 11)
2460  AsmString = "fmovdge %xcc, $\x02, $\x01";
2461  break;
2462  }
2463  if (MCInst_getNumOperands(MI) == 3 &&
2464  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2465  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2466  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2467  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2468  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2469  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2470  // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 3)
2471  AsmString = "fmovdl %xcc, $\x02, $\x01";
2472  break;
2473  }
2474  if (MCInst_getNumOperands(MI) == 3 &&
2475  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2476  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2477  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2478  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2479  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2480  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2481  // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 12)
2482  AsmString = "fmovdgu %xcc, $\x02, $\x01";
2483  break;
2484  }
2485  if (MCInst_getNumOperands(MI) == 3 &&
2486  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2487  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2488  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2489  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2490  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2491  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2492  // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 4)
2493  AsmString = "fmovdleu %xcc, $\x02, $\x01";
2494  break;
2495  }
2496  if (MCInst_getNumOperands(MI) == 3 &&
2497  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2498  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2499  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2500  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2501  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2502  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2503  // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 13)
2504  AsmString = "fmovdcc %xcc, $\x02, $\x01";
2505  break;
2506  }
2507  if (MCInst_getNumOperands(MI) == 3 &&
2508  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2509  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2510  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2511  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2512  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2513  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2514  // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 5)
2515  AsmString = "fmovdcs %xcc, $\x02, $\x01";
2516  break;
2517  }
2518  if (MCInst_getNumOperands(MI) == 3 &&
2519  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2520  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2521  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2522  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2523  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2524  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2525  // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 14)
2526  AsmString = "fmovdpos %xcc, $\x02, $\x01";
2527  break;
2528  }
2529  if (MCInst_getNumOperands(MI) == 3 &&
2530  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2531  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2532  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2533  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2534  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2535  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2536  // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 6)
2537  AsmString = "fmovdneg %xcc, $\x02, $\x01";
2538  break;
2539  }
2540  if (MCInst_getNumOperands(MI) == 3 &&
2541  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2542  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2543  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2544  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2545  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2546  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2547  // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 15)
2548  AsmString = "fmovdvc %xcc, $\x02, $\x01";
2549  break;
2550  }
2551  if (MCInst_getNumOperands(MI) == 3 &&
2552  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2553  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
2554  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2555  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
2556  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2557  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2558  // (FMOVD_XCC DFPRegs:$rd, DFPRegs:$rs2, 7)
2559  AsmString = "fmovdvs %xcc, $\x02, $\x01";
2560  break;
2561  }
2562  return NULL;
2563  case SP_FMOVQ_ICC:
2564  if (MCInst_getNumOperands(MI) == 3 &&
2565  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2566  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2567  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2568  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2569  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2570  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2571  // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 8)
2572  AsmString = "fmovqa %icc, $\x02, $\x01";
2573  break;
2574  }
2575  if (MCInst_getNumOperands(MI) == 3 &&
2576  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2577  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2578  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2579  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2580  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2581  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2582  // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 0)
2583  AsmString = "fmovqn %icc, $\x02, $\x01";
2584  break;
2585  }
2586  if (MCInst_getNumOperands(MI) == 3 &&
2587  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2588  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2589  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2590  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2591  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2592  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2593  // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 9)
2594  AsmString = "fmovqne %icc, $\x02, $\x01";
2595  break;
2596  }
2597  if (MCInst_getNumOperands(MI) == 3 &&
2598  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2599  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2600  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2601  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2602  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2603  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2604  // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 1)
2605  AsmString = "fmovqe %icc, $\x02, $\x01";
2606  break;
2607  }
2608  if (MCInst_getNumOperands(MI) == 3 &&
2609  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2610  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2611  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2612  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2613  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2614  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2615  // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 10)
2616  AsmString = "fmovqg %icc, $\x02, $\x01";
2617  break;
2618  }
2619  if (MCInst_getNumOperands(MI) == 3 &&
2620  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2621  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2622  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2623  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2624  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2625  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2626  // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 2)
2627  AsmString = "fmovqle %icc, $\x02, $\x01";
2628  break;
2629  }
2630  if (MCInst_getNumOperands(MI) == 3 &&
2631  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2632  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2633  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2634  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2635  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2636  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2637  // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 11)
2638  AsmString = "fmovqge %icc, $\x02, $\x01";
2639  break;
2640  }
2641  if (MCInst_getNumOperands(MI) == 3 &&
2642  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2643  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2644  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2645  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2646  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2647  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2648  // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 3)
2649  AsmString = "fmovql %icc, $\x02, $\x01";
2650  break;
2651  }
2652  if (MCInst_getNumOperands(MI) == 3 &&
2653  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2654  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2655  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2656  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2657  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2658  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2659  // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 12)
2660  AsmString = "fmovqgu %icc, $\x02, $\x01";
2661  break;
2662  }
2663  if (MCInst_getNumOperands(MI) == 3 &&
2664  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2665  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2666  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2667  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2668  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2669  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2670  // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 4)
2671  AsmString = "fmovqleu %icc, $\x02, $\x01";
2672  break;
2673  }
2674  if (MCInst_getNumOperands(MI) == 3 &&
2675  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2676  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2677  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2678  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2679  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2680  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2681  // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 13)
2682  AsmString = "fmovqcc %icc, $\x02, $\x01";
2683  break;
2684  }
2685  if (MCInst_getNumOperands(MI) == 3 &&
2686  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2687  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2688  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2689  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2690  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2691  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2692  // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 5)
2693  AsmString = "fmovqcs %icc, $\x02, $\x01";
2694  break;
2695  }
2696  if (MCInst_getNumOperands(MI) == 3 &&
2697  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2698  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2699  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2700  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2701  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2702  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2703  // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 14)
2704  AsmString = "fmovqpos %icc, $\x02, $\x01";
2705  break;
2706  }
2707  if (MCInst_getNumOperands(MI) == 3 &&
2708  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2709  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2710  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2711  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2712  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2713  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2714  // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 6)
2715  AsmString = "fmovqneg %icc, $\x02, $\x01";
2716  break;
2717  }
2718  if (MCInst_getNumOperands(MI) == 3 &&
2719  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2720  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2721  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2722  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2723  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2724  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2725  // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 15)
2726  AsmString = "fmovqvc %icc, $\x02, $\x01";
2727  break;
2728  }
2729  if (MCInst_getNumOperands(MI) == 3 &&
2730  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2731  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2732  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2733  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2734  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2735  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2736  // (FMOVQ_ICC QFPRegs:$rd, QFPRegs:$rs2, 7)
2737  AsmString = "fmovqvs %icc, $\x02, $\x01";
2738  break;
2739  }
2740  return NULL;
2741  case SP_FMOVQ_XCC:
2742  if (MCInst_getNumOperands(MI) == 3 &&
2743  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2744  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2745  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2746  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2747  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2748  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2749  // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 8)
2750  AsmString = "fmovqa %xcc, $\x02, $\x01";
2751  break;
2752  }
2753  if (MCInst_getNumOperands(MI) == 3 &&
2754  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2755  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2756  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2757  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2758  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2759  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2760  // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 0)
2761  AsmString = "fmovqn %xcc, $\x02, $\x01";
2762  break;
2763  }
2764  if (MCInst_getNumOperands(MI) == 3 &&
2765  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2766  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2767  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2768  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2769  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2770  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2771  // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 9)
2772  AsmString = "fmovqne %xcc, $\x02, $\x01";
2773  break;
2774  }
2775  if (MCInst_getNumOperands(MI) == 3 &&
2776  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2777  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2778  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2779  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2780  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2781  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2782  // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 1)
2783  AsmString = "fmovqe %xcc, $\x02, $\x01";
2784  break;
2785  }
2786  if (MCInst_getNumOperands(MI) == 3 &&
2787  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2788  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2789  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2790  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2791  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2792  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2793  // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 10)
2794  AsmString = "fmovqg %xcc, $\x02, $\x01";
2795  break;
2796  }
2797  if (MCInst_getNumOperands(MI) == 3 &&
2798  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2799  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2800  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2801  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2802  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2803  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2804  // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 2)
2805  AsmString = "fmovqle %xcc, $\x02, $\x01";
2806  break;
2807  }
2808  if (MCInst_getNumOperands(MI) == 3 &&
2809  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2810  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2811  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2812  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2813  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2814  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2815  // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 11)
2816  AsmString = "fmovqge %xcc, $\x02, $\x01";
2817  break;
2818  }
2819  if (MCInst_getNumOperands(MI) == 3 &&
2820  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2821  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2822  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2823  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2824  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2825  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
2826  // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 3)
2827  AsmString = "fmovql %xcc, $\x02, $\x01";
2828  break;
2829  }
2830  if (MCInst_getNumOperands(MI) == 3 &&
2831  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2832  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2833  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2834  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2835  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2836  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
2837  // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 12)
2838  AsmString = "fmovqgu %xcc, $\x02, $\x01";
2839  break;
2840  }
2841  if (MCInst_getNumOperands(MI) == 3 &&
2842  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2843  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2844  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2845  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2846  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2847  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
2848  // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 4)
2849  AsmString = "fmovqleu %xcc, $\x02, $\x01";
2850  break;
2851  }
2852  if (MCInst_getNumOperands(MI) == 3 &&
2853  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2854  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2855  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2856  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2857  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2858  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
2859  // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 13)
2860  AsmString = "fmovqcc %xcc, $\x02, $\x01";
2861  break;
2862  }
2863  if (MCInst_getNumOperands(MI) == 3 &&
2864  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2865  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2866  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2867  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2868  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2869  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
2870  // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 5)
2871  AsmString = "fmovqcs %xcc, $\x02, $\x01";
2872  break;
2873  }
2874  if (MCInst_getNumOperands(MI) == 3 &&
2875  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2876  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2877  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2878  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2879  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2880  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
2881  // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 14)
2882  AsmString = "fmovqpos %xcc, $\x02, $\x01";
2883  break;
2884  }
2885  if (MCInst_getNumOperands(MI) == 3 &&
2886  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2887  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2888  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2889  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2890  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2891  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
2892  // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 6)
2893  AsmString = "fmovqneg %xcc, $\x02, $\x01";
2894  break;
2895  }
2896  if (MCInst_getNumOperands(MI) == 3 &&
2897  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2898  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2899  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2900  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2901  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2902  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
2903  // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 15)
2904  AsmString = "fmovqvc %xcc, $\x02, $\x01";
2905  break;
2906  }
2907  if (MCInst_getNumOperands(MI) == 3 &&
2908  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2909  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
2910  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2911  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
2912  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2913  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
2914  // (FMOVQ_XCC QFPRegs:$rd, QFPRegs:$rs2, 7)
2915  AsmString = "fmovqvs %xcc, $\x02, $\x01";
2916  break;
2917  }
2918  return NULL;
2919  case SP_FMOVS_ICC:
2920  if (MCInst_getNumOperands(MI) == 3 &&
2921  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2922  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2923  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2924  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2925  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2926  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
2927  // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 8)
2928  AsmString = "fmovsa %icc, $\x02, $\x01";
2929  break;
2930  }
2931  if (MCInst_getNumOperands(MI) == 3 &&
2932  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2933  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2934  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2935  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2936  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2937  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
2938  // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 0)
2939  AsmString = "fmovsn %icc, $\x02, $\x01";
2940  break;
2941  }
2942  if (MCInst_getNumOperands(MI) == 3 &&
2943  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2944  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2945  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2946  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2947  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2948  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
2949  // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 9)
2950  AsmString = "fmovsne %icc, $\x02, $\x01";
2951  break;
2952  }
2953  if (MCInst_getNumOperands(MI) == 3 &&
2954  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2955  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2956  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2957  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2958  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2959  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
2960  // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 1)
2961  AsmString = "fmovse %icc, $\x02, $\x01";
2962  break;
2963  }
2964  if (MCInst_getNumOperands(MI) == 3 &&
2965  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2966  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2967  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2968  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2969  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2970  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
2971  // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 10)
2972  AsmString = "fmovsg %icc, $\x02, $\x01";
2973  break;
2974  }
2975  if (MCInst_getNumOperands(MI) == 3 &&
2976  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2977  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2978  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2979  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2980  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2981  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
2982  // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 2)
2983  AsmString = "fmovsle %icc, $\x02, $\x01";
2984  break;
2985  }
2986  if (MCInst_getNumOperands(MI) == 3 &&
2987  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2988  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
2989  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
2990  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
2991  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
2992  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
2993  // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 11)
2994  AsmString = "fmovsge %icc, $\x02, $\x01";
2995  break;
2996  }
2997  if (MCInst_getNumOperands(MI) == 3 &&
2998  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
2999  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3000  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3001  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3002  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3003  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3004  // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 3)
3005  AsmString = "fmovsl %icc, $\x02, $\x01";
3006  break;
3007  }
3008  if (MCInst_getNumOperands(MI) == 3 &&
3009  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3010  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3011  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3012  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3013  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3014  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3015  // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 12)
3016  AsmString = "fmovsgu %icc, $\x02, $\x01";
3017  break;
3018  }
3019  if (MCInst_getNumOperands(MI) == 3 &&
3020  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3021  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3022  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3023  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3024  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3025  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3026  // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 4)
3027  AsmString = "fmovsleu %icc, $\x02, $\x01";
3028  break;
3029  }
3030  if (MCInst_getNumOperands(MI) == 3 &&
3031  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3032  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3033  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3034  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3035  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3036  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3037  // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 13)
3038  AsmString = "fmovscc %icc, $\x02, $\x01";
3039  break;
3040  }
3041  if (MCInst_getNumOperands(MI) == 3 &&
3042  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3043  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3044  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3045  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3046  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3047  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3048  // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 5)
3049  AsmString = "fmovscs %icc, $\x02, $\x01";
3050  break;
3051  }
3052  if (MCInst_getNumOperands(MI) == 3 &&
3053  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3054  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3055  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3056  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3057  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3058  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3059  // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 14)
3060  AsmString = "fmovspos %icc, $\x02, $\x01";
3061  break;
3062  }
3063  if (MCInst_getNumOperands(MI) == 3 &&
3064  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3065  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3066  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3067  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3068  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3069  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3070  // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 6)
3071  AsmString = "fmovsneg %icc, $\x02, $\x01";
3072  break;
3073  }
3074  if (MCInst_getNumOperands(MI) == 3 &&
3075  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3076  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3077  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3078  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3079  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3080  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3081  // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 15)
3082  AsmString = "fmovsvc %icc, $\x02, $\x01";
3083  break;
3084  }
3085  if (MCInst_getNumOperands(MI) == 3 &&
3086  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3087  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3088  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3089  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3090  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3091  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3092  // (FMOVS_ICC FPRegs:$rd, FPRegs:$rs2, 7)
3093  AsmString = "fmovsvs %icc, $\x02, $\x01";
3094  break;
3095  }
3096  return NULL;
3097  case SP_FMOVS_XCC:
3098  if (MCInst_getNumOperands(MI) == 3 &&
3099  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3100  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3101  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3102  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3103  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3104  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3105  // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 8)
3106  AsmString = "fmovsa %xcc, $\x02, $\x01";
3107  break;
3108  }
3109  if (MCInst_getNumOperands(MI) == 3 &&
3110  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3111  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3112  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3113  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3114  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3115  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3116  // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 0)
3117  AsmString = "fmovsn %xcc, $\x02, $\x01";
3118  break;
3119  }
3120  if (MCInst_getNumOperands(MI) == 3 &&
3121  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3122  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3123  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3124  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3125  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3126  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3127  // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 9)
3128  AsmString = "fmovsne %xcc, $\x02, $\x01";
3129  break;
3130  }
3131  if (MCInst_getNumOperands(MI) == 3 &&
3132  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3133  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3134  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3135  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3136  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3137  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3138  // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 1)
3139  AsmString = "fmovse %xcc, $\x02, $\x01";
3140  break;
3141  }
3142  if (MCInst_getNumOperands(MI) == 3 &&
3143  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3144  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3145  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3146  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3147  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3148  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3149  // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 10)
3150  AsmString = "fmovsg %xcc, $\x02, $\x01";
3151  break;
3152  }
3153  if (MCInst_getNumOperands(MI) == 3 &&
3154  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3155  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3156  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3157  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3158  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3159  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3160  // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 2)
3161  AsmString = "fmovsle %xcc, $\x02, $\x01";
3162  break;
3163  }
3164  if (MCInst_getNumOperands(MI) == 3 &&
3165  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3166  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3167  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3168  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3169  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3170  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3171  // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 11)
3172  AsmString = "fmovsge %xcc, $\x02, $\x01";
3173  break;
3174  }
3175  if (MCInst_getNumOperands(MI) == 3 &&
3176  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3177  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3178  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3179  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3180  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3181  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3182  // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 3)
3183  AsmString = "fmovsl %xcc, $\x02, $\x01";
3184  break;
3185  }
3186  if (MCInst_getNumOperands(MI) == 3 &&
3187  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3188  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3189  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3190  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3191  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3192  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3193  // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 12)
3194  AsmString = "fmovsgu %xcc, $\x02, $\x01";
3195  break;
3196  }
3197  if (MCInst_getNumOperands(MI) == 3 &&
3198  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3199  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3200  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3201  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3202  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3203  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3204  // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 4)
3205  AsmString = "fmovsleu %xcc, $\x02, $\x01";
3206  break;
3207  }
3208  if (MCInst_getNumOperands(MI) == 3 &&
3209  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3210  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3211  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3212  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3213  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3214  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3215  // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 13)
3216  AsmString = "fmovscc %xcc, $\x02, $\x01";
3217  break;
3218  }
3219  if (MCInst_getNumOperands(MI) == 3 &&
3220  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3221  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3222  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3223  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3224  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3225  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3226  // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 5)
3227  AsmString = "fmovscs %xcc, $\x02, $\x01";
3228  break;
3229  }
3230  if (MCInst_getNumOperands(MI) == 3 &&
3231  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3232  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3233  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3234  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3235  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3236  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3237  // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 14)
3238  AsmString = "fmovspos %xcc, $\x02, $\x01";
3239  break;
3240  }
3241  if (MCInst_getNumOperands(MI) == 3 &&
3242  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3243  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3244  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3245  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3246  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3247  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3248  // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 6)
3249  AsmString = "fmovsneg %xcc, $\x02, $\x01";
3250  break;
3251  }
3252  if (MCInst_getNumOperands(MI) == 3 &&
3253  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3254  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3255  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3256  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3257  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3258  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3259  // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 15)
3260  AsmString = "fmovsvc %xcc, $\x02, $\x01";
3261  break;
3262  }
3263  if (MCInst_getNumOperands(MI) == 3 &&
3264  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3265  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
3266  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3267  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
3268  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3269  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3270  // (FMOVS_XCC FPRegs:$rd, FPRegs:$rs2, 7)
3271  AsmString = "fmovsvs %xcc, $\x02, $\x01";
3272  break;
3273  }
3274  return NULL;
3275  case SP_MOVICCri:
3276  if (MCInst_getNumOperands(MI) == 3 &&
3277  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3278  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3279  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3280  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3281  // (MOVICCri IntRegs:$rd, i32imm:$simm11, 8)
3282  AsmString = "mova %icc, $\x02, $\x01";
3283  break;
3284  }
3285  if (MCInst_getNumOperands(MI) == 3 &&
3286  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3287  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3288  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3289  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3290  // (MOVICCri IntRegs:$rd, i32imm:$simm11, 0)
3291  AsmString = "movn %icc, $\x02, $\x01";
3292  break;
3293  }
3294  if (MCInst_getNumOperands(MI) == 3 &&
3295  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3296  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3297  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3298  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3299  // (MOVICCri IntRegs:$rd, i32imm:$simm11, 9)
3300  AsmString = "movne %icc, $\x02, $\x01";
3301  break;
3302  }
3303  if (MCInst_getNumOperands(MI) == 3 &&
3304  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3305  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3306  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3307  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3308  // (MOVICCri IntRegs:$rd, i32imm:$simm11, 1)
3309  AsmString = "move %icc, $\x02, $\x01";
3310  break;
3311  }
3312  if (MCInst_getNumOperands(MI) == 3 &&
3313  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3314  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3315  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3316  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3317  // (MOVICCri IntRegs:$rd, i32imm:$simm11, 10)
3318  AsmString = "movg %icc, $\x02, $\x01";
3319  break;
3320  }
3321  if (MCInst_getNumOperands(MI) == 3 &&
3322  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3323  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3324  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3325  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3326  // (MOVICCri IntRegs:$rd, i32imm:$simm11, 2)
3327  AsmString = "movle %icc, $\x02, $\x01";
3328  break;
3329  }
3330  if (MCInst_getNumOperands(MI) == 3 &&
3331  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3332  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3333  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3334  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3335  // (MOVICCri IntRegs:$rd, i32imm:$simm11, 11)
3336  AsmString = "movge %icc, $\x02, $\x01";
3337  break;
3338  }
3339  if (MCInst_getNumOperands(MI) == 3 &&
3340  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3341  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3342  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3343  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3344  // (MOVICCri IntRegs:$rd, i32imm:$simm11, 3)
3345  AsmString = "movl %icc, $\x02, $\x01";
3346  break;
3347  }
3348  if (MCInst_getNumOperands(MI) == 3 &&
3349  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3350  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3351  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3352  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3353  // (MOVICCri IntRegs:$rd, i32imm:$simm11, 12)
3354  AsmString = "movgu %icc, $\x02, $\x01";
3355  break;
3356  }
3357  if (MCInst_getNumOperands(MI) == 3 &&
3358  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3359  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3360  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3361  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3362  // (MOVICCri IntRegs:$rd, i32imm:$simm11, 4)
3363  AsmString = "movleu %icc, $\x02, $\x01";
3364  break;
3365  }
3366  if (MCInst_getNumOperands(MI) == 3 &&
3367  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3368  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3369  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3370  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3371  // (MOVICCri IntRegs:$rd, i32imm:$simm11, 13)
3372  AsmString = "movcc %icc, $\x02, $\x01";
3373  break;
3374  }
3375  if (MCInst_getNumOperands(MI) == 3 &&
3376  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3377  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3378  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3379  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3380  // (MOVICCri IntRegs:$rd, i32imm:$simm11, 5)
3381  AsmString = "movcs %icc, $\x02, $\x01";
3382  break;
3383  }
3384  if (MCInst_getNumOperands(MI) == 3 &&
3385  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3386  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3387  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3388  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3389  // (MOVICCri IntRegs:$rd, i32imm:$simm11, 14)
3390  AsmString = "movpos %icc, $\x02, $\x01";
3391  break;
3392  }
3393  if (MCInst_getNumOperands(MI) == 3 &&
3394  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3395  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3396  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3397  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3398  // (MOVICCri IntRegs:$rd, i32imm:$simm11, 6)
3399  AsmString = "movneg %icc, $\x02, $\x01";
3400  break;
3401  }
3402  if (MCInst_getNumOperands(MI) == 3 &&
3403  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3404  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3405  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3406  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3407  // (MOVICCri IntRegs:$rd, i32imm:$simm11, 15)
3408  AsmString = "movvc %icc, $\x02, $\x01";
3409  break;
3410  }
3411  if (MCInst_getNumOperands(MI) == 3 &&
3412  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3413  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3414  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3415  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3416  // (MOVICCri IntRegs:$rd, i32imm:$simm11, 7)
3417  AsmString = "movvs %icc, $\x02, $\x01";
3418  break;
3419  }
3420  return NULL;
3421  case SP_MOVICCrr:
3422  if (MCInst_getNumOperands(MI) == 3 &&
3423  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3424  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3425  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3426  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3427  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3428  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3429  // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 8)
3430  AsmString = "mova %icc, $\x02, $\x01";
3431  break;
3432  }
3433  if (MCInst_getNumOperands(MI) == 3 &&
3434  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3435  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3436  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3437  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3438  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3439  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3440  // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 0)
3441  AsmString = "movn %icc, $\x02, $\x01";
3442  break;
3443  }
3444  if (MCInst_getNumOperands(MI) == 3 &&
3445  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3446  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3447  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3448  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3449  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3450  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3451  // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 9)
3452  AsmString = "movne %icc, $\x02, $\x01";
3453  break;
3454  }
3455  if (MCInst_getNumOperands(MI) == 3 &&
3456  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3457  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3458  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3459  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3460  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3461  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3462  // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 1)
3463  AsmString = "move %icc, $\x02, $\x01";
3464  break;
3465  }
3466  if (MCInst_getNumOperands(MI) == 3 &&
3467  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3468  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3469  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3470  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3471  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3472  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3473  // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 10)
3474  AsmString = "movg %icc, $\x02, $\x01";
3475  break;
3476  }
3477  if (MCInst_getNumOperands(MI) == 3 &&
3478  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3479  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3480  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3481  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3482  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3483  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3484  // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 2)
3485  AsmString = "movle %icc, $\x02, $\x01";
3486  break;
3487  }
3488  if (MCInst_getNumOperands(MI) == 3 &&
3489  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3490  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3491  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3492  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3493  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3494  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3495  // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 11)
3496  AsmString = "movge %icc, $\x02, $\x01";
3497  break;
3498  }
3499  if (MCInst_getNumOperands(MI) == 3 &&
3500  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3501  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3502  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3503  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3504  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3505  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3506  // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 3)
3507  AsmString = "movl %icc, $\x02, $\x01";
3508  break;
3509  }
3510  if (MCInst_getNumOperands(MI) == 3 &&
3511  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3512  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3513  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3514  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3515  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3516  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3517  // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 12)
3518  AsmString = "movgu %icc, $\x02, $\x01";
3519  break;
3520  }
3521  if (MCInst_getNumOperands(MI) == 3 &&
3522  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3523  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3524  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3525  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3526  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3527  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3528  // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 4)
3529  AsmString = "movleu %icc, $\x02, $\x01";
3530  break;
3531  }
3532  if (MCInst_getNumOperands(MI) == 3 &&
3533  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3534  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3535  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3536  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3537  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3538  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3539  // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 13)
3540  AsmString = "movcc %icc, $\x02, $\x01";
3541  break;
3542  }
3543  if (MCInst_getNumOperands(MI) == 3 &&
3544  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3545  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3546  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3547  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3548  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3549  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3550  // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 5)
3551  AsmString = "movcs %icc, $\x02, $\x01";
3552  break;
3553  }
3554  if (MCInst_getNumOperands(MI) == 3 &&
3555  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3556  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3557  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3558  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3559  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3560  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3561  // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 14)
3562  AsmString = "movpos %icc, $\x02, $\x01";
3563  break;
3564  }
3565  if (MCInst_getNumOperands(MI) == 3 &&
3566  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3567  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3568  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3569  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3570  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3571  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3572  // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 6)
3573  AsmString = "movneg %icc, $\x02, $\x01";
3574  break;
3575  }
3576  if (MCInst_getNumOperands(MI) == 3 &&
3577  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3578  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3579  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3580  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3581  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3582  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3583  // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 15)
3584  AsmString = "movvc %icc, $\x02, $\x01";
3585  break;
3586  }
3587  if (MCInst_getNumOperands(MI) == 3 &&
3588  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3589  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3590  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3591  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3592  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3593  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3594  // (MOVICCrr IntRegs:$rd, IntRegs:$rs2, 7)
3595  AsmString = "movvs %icc, $\x02, $\x01";
3596  break;
3597  }
3598  return NULL;
3599  case SP_MOVXCCri:
3600  if (MCInst_getNumOperands(MI) == 3 &&
3601  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3602  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3603  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3604  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3605  // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 8)
3606  AsmString = "mova %xcc, $\x02, $\x01";
3607  break;
3608  }
3609  if (MCInst_getNumOperands(MI) == 3 &&
3610  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3611  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3612  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3613  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3614  // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 0)
3615  AsmString = "movn %xcc, $\x02, $\x01";
3616  break;
3617  }
3618  if (MCInst_getNumOperands(MI) == 3 &&
3619  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3620  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3621  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3622  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3623  // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 9)
3624  AsmString = "movne %xcc, $\x02, $\x01";
3625  break;
3626  }
3627  if (MCInst_getNumOperands(MI) == 3 &&
3628  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3629  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3630  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3631  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3632  // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 1)
3633  AsmString = "move %xcc, $\x02, $\x01";
3634  break;
3635  }
3636  if (MCInst_getNumOperands(MI) == 3 &&
3637  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3638  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3639  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3640  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3641  // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 10)
3642  AsmString = "movg %xcc, $\x02, $\x01";
3643  break;
3644  }
3645  if (MCInst_getNumOperands(MI) == 3 &&
3646  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3647  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3648  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3649  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3650  // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 2)
3651  AsmString = "movle %xcc, $\x02, $\x01";
3652  break;
3653  }
3654  if (MCInst_getNumOperands(MI) == 3 &&
3655  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3656  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3657  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3658  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3659  // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 11)
3660  AsmString = "movge %xcc, $\x02, $\x01";
3661  break;
3662  }
3663  if (MCInst_getNumOperands(MI) == 3 &&
3664  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3665  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3666  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3667  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3668  // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 3)
3669  AsmString = "movl %xcc, $\x02, $\x01";
3670  break;
3671  }
3672  if (MCInst_getNumOperands(MI) == 3 &&
3673  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3674  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3675  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3676  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3677  // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 12)
3678  AsmString = "movgu %xcc, $\x02, $\x01";
3679  break;
3680  }
3681  if (MCInst_getNumOperands(MI) == 3 &&
3682  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3683  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3684  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3685  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3686  // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 4)
3687  AsmString = "movleu %xcc, $\x02, $\x01";
3688  break;
3689  }
3690  if (MCInst_getNumOperands(MI) == 3 &&
3691  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3692  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3693  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3694  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3695  // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 13)
3696  AsmString = "movcc %xcc, $\x02, $\x01";
3697  break;
3698  }
3699  if (MCInst_getNumOperands(MI) == 3 &&
3700  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3701  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3702  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3703  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3704  // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 5)
3705  AsmString = "movcs %xcc, $\x02, $\x01";
3706  break;
3707  }
3708  if (MCInst_getNumOperands(MI) == 3 &&
3709  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3710  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3711  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3712  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3713  // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 14)
3714  AsmString = "movpos %xcc, $\x02, $\x01";
3715  break;
3716  }
3717  if (MCInst_getNumOperands(MI) == 3 &&
3718  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3719  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3720  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3721  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3722  // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 6)
3723  AsmString = "movneg %xcc, $\x02, $\x01";
3724  break;
3725  }
3726  if (MCInst_getNumOperands(MI) == 3 &&
3727  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3728  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3729  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3730  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3731  // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 15)
3732  AsmString = "movvc %xcc, $\x02, $\x01";
3733  break;
3734  }
3735  if (MCInst_getNumOperands(MI) == 3 &&
3736  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3737  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3738  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3739  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3740  // (MOVXCCri IntRegs:$rd, i32imm:$simm11, 7)
3741  AsmString = "movvs %xcc, $\x02, $\x01";
3742  break;
3743  }
3744  return NULL;
3745  case SP_MOVXCCrr:
3746  if (MCInst_getNumOperands(MI) == 3 &&
3747  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3748  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3749  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3750  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3751  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3752  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3753  // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 8)
3754  AsmString = "mova %xcc, $\x02, $\x01";
3755  break;
3756  }
3757  if (MCInst_getNumOperands(MI) == 3 &&
3758  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3759  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3760  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3761  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3762  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3763  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3764  // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 0)
3765  AsmString = "movn %xcc, $\x02, $\x01";
3766  break;
3767  }
3768  if (MCInst_getNumOperands(MI) == 3 &&
3769  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3770  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3771  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3772  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3773  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3774  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
3775  // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 9)
3776  AsmString = "movne %xcc, $\x02, $\x01";
3777  break;
3778  }
3779  if (MCInst_getNumOperands(MI) == 3 &&
3780  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3781  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3782  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3783  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3784  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3785  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
3786  // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 1)
3787  AsmString = "move %xcc, $\x02, $\x01";
3788  break;
3789  }
3790  if (MCInst_getNumOperands(MI) == 3 &&
3791  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3792  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3793  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3794  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3795  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3796  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
3797  // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 10)
3798  AsmString = "movg %xcc, $\x02, $\x01";
3799  break;
3800  }
3801  if (MCInst_getNumOperands(MI) == 3 &&
3802  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3803  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3804  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3805  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3806  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3807  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
3808  // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 2)
3809  AsmString = "movle %xcc, $\x02, $\x01";
3810  break;
3811  }
3812  if (MCInst_getNumOperands(MI) == 3 &&
3813  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3814  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3815  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3816  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3817  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3818  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
3819  // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 11)
3820  AsmString = "movge %xcc, $\x02, $\x01";
3821  break;
3822  }
3823  if (MCInst_getNumOperands(MI) == 3 &&
3824  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3825  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3826  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3827  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3828  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3829  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
3830  // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 3)
3831  AsmString = "movl %xcc, $\x02, $\x01";
3832  break;
3833  }
3834  if (MCInst_getNumOperands(MI) == 3 &&
3835  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3836  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3837  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3838  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3839  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3840  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
3841  // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 12)
3842  AsmString = "movgu %xcc, $\x02, $\x01";
3843  break;
3844  }
3845  if (MCInst_getNumOperands(MI) == 3 &&
3846  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3847  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3848  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3849  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3850  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3851  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
3852  // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 4)
3853  AsmString = "movleu %xcc, $\x02, $\x01";
3854  break;
3855  }
3856  if (MCInst_getNumOperands(MI) == 3 &&
3857  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3858  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3859  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3860  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3861  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3862  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
3863  // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 13)
3864  AsmString = "movcc %xcc, $\x02, $\x01";
3865  break;
3866  }
3867  if (MCInst_getNumOperands(MI) == 3 &&
3868  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3869  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3870  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3871  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3872  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3873  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
3874  // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 5)
3875  AsmString = "movcs %xcc, $\x02, $\x01";
3876  break;
3877  }
3878  if (MCInst_getNumOperands(MI) == 3 &&
3879  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3880  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3881  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3882  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3883  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3884  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
3885  // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 14)
3886  AsmString = "movpos %xcc, $\x02, $\x01";
3887  break;
3888  }
3889  if (MCInst_getNumOperands(MI) == 3 &&
3890  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3891  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3892  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3893  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3894  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3895  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
3896  // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 6)
3897  AsmString = "movneg %xcc, $\x02, $\x01";
3898  break;
3899  }
3900  if (MCInst_getNumOperands(MI) == 3 &&
3901  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3902  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3903  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3904  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3905  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3906  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
3907  // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 15)
3908  AsmString = "movvc %xcc, $\x02, $\x01";
3909  break;
3910  }
3911  if (MCInst_getNumOperands(MI) == 3 &&
3912  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3913  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3914  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
3915  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
3916  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3917  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
3918  // (MOVXCCrr IntRegs:$rd, IntRegs:$rs2, 7)
3919  AsmString = "movvs %xcc, $\x02, $\x01";
3920  break;
3921  }
3922  return NULL;
3923  case SP_ORri:
3924  if (MCInst_getNumOperands(MI) == 3 &&
3925  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3926  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3927  MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0) {
3928  // (ORri IntRegs:$rd, G0, i32imm:$simm13)
3929  AsmString = "mov $\x03, $\x01";
3930  break;
3931  }
3932  return NULL;
3933  case SP_ORrr:
3934  if (MCInst_getNumOperands(MI) == 3 &&
3935  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3936  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3937  MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3938  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
3939  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2)) {
3940  // (ORrr IntRegs:$rd, G0, IntRegs:$rs2)
3941  AsmString = "mov $\x03, $\x01";
3942  break;
3943  }
3944  return NULL;
3945  case SP_RESTORErr:
3946  if (MCInst_getNumOperands(MI) == 3 &&
3947  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3948  MCOperand_getReg(MCInst_getOperand(MI, 1)) == SP_G0 &&
3949  MCOperand_getReg(MCInst_getOperand(MI, 2)) == SP_G0) {
3950  // (RESTORErr G0, G0, G0)
3951  AsmString = "restore";
3952  break;
3953  }
3954  return NULL;
3955  case SP_RET:
3956  if (MCInst_getNumOperands(MI) == 1 &&
3957  MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3958  MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3959  // (RET 8)
3960  AsmString = "ret";
3961  break;
3962  }
3963  return NULL;
3964  case SP_RETL:
3965  if (MCInst_getNumOperands(MI) == 1 &&
3966  MCOperand_isImm(MCInst_getOperand(MI, 0)) &&
3967  MCOperand_getImm(MCInst_getOperand(MI, 0)) == 8) {
3968  // (RETL 8)
3969  AsmString = "retl";
3970  break;
3971  }
3972  return NULL;
3973  case SP_TXCCri:
3974  if (MCInst_getNumOperands(MI) == 3 &&
3975  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3976  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3977  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3978  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3979  // (TXCCri IntRegs:$rs1, i32imm:$imm, 8)
3980  AsmString = "ta %xcc, $\x01 + $\x02";
3981  break;
3982  }
3983  if (MCInst_getNumOperands(MI) == 3 &&
3984  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
3985  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3986  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
3987  // (TXCCri G0, i32imm:$imm, 8)
3988  AsmString = "ta %xcc, $\x02";
3989  break;
3990  }
3991  if (MCInst_getNumOperands(MI) == 3 &&
3992  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
3993  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
3994  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
3995  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
3996  // (TXCCri IntRegs:$rs1, i32imm:$imm, 0)
3997  AsmString = "tn %xcc, $\x01 + $\x02";
3998  break;
3999  }
4000  if (MCInst_getNumOperands(MI) == 3 &&
4001  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4002  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4003  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4004  // (TXCCri G0, i32imm:$imm, 0)
4005  AsmString = "tn %xcc, $\x02";
4006  break;
4007  }
4008  if (MCInst_getNumOperands(MI) == 3 &&
4009  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4010  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4011  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4012  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4013  // (TXCCri IntRegs:$rs1, i32imm:$imm, 9)
4014  AsmString = "tne %xcc, $\x01 + $\x02";
4015  break;
4016  }
4017  if (MCInst_getNumOperands(MI) == 3 &&
4018  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4019  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4020  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4021  // (TXCCri G0, i32imm:$imm, 9)
4022  AsmString = "tne %xcc, $\x02";
4023  break;
4024  }
4025  if (MCInst_getNumOperands(MI) == 3 &&
4026  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4027  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4028  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4029  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4030  // (TXCCri IntRegs:$rs1, i32imm:$imm, 1)
4031  AsmString = "te %xcc, $\x01 + $\x02";
4032  break;
4033  }
4034  if (MCInst_getNumOperands(MI) == 3 &&
4035  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4036  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4037  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4038  // (TXCCri G0, i32imm:$imm, 1)
4039  AsmString = "te %xcc, $\x02";
4040  break;
4041  }
4042  if (MCInst_getNumOperands(MI) == 3 &&
4043  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4044  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4045  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4046  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4047  // (TXCCri IntRegs:$rs1, i32imm:$imm, 10)
4048  AsmString = "tg %xcc, $\x01 + $\x02";
4049  break;
4050  }
4051  if (MCInst_getNumOperands(MI) == 3 &&
4052  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4053  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4054  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4055  // (TXCCri G0, i32imm:$imm, 10)
4056  AsmString = "tg %xcc, $\x02";
4057  break;
4058  }
4059  if (MCInst_getNumOperands(MI) == 3 &&
4060  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4061  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4062  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4063  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4064  // (TXCCri IntRegs:$rs1, i32imm:$imm, 2)
4065  AsmString = "tle %xcc, $\x01 + $\x02";
4066  break;
4067  }
4068  if (MCInst_getNumOperands(MI) == 3 &&
4069  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4070  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4071  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4072  // (TXCCri G0, i32imm:$imm, 2)
4073  AsmString = "tle %xcc, $\x02";
4074  break;
4075  }
4076  if (MCInst_getNumOperands(MI) == 3 &&
4077  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4078  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4079  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4080  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4081  // (TXCCri IntRegs:$rs1, i32imm:$imm, 11)
4082  AsmString = "tge %xcc, $\x01 + $\x02";
4083  break;
4084  }
4085  if (MCInst_getNumOperands(MI) == 3 &&
4086  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4087  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4088  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4089  // (TXCCri G0, i32imm:$imm, 11)
4090  AsmString = "tge %xcc, $\x02";
4091  break;
4092  }
4093  if (MCInst_getNumOperands(MI) == 3 &&
4094  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4095  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4096  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4097  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4098  // (TXCCri IntRegs:$rs1, i32imm:$imm, 3)
4099  AsmString = "tl %xcc, $\x01 + $\x02";
4100  break;
4101  }
4102  if (MCInst_getNumOperands(MI) == 3 &&
4103  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4104  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4105  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4106  // (TXCCri G0, i32imm:$imm, 3)
4107  AsmString = "tl %xcc, $\x02";
4108  break;
4109  }
4110  if (MCInst_getNumOperands(MI) == 3 &&
4111  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4112  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4113  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4114  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4115  // (TXCCri IntRegs:$rs1, i32imm:$imm, 12)
4116  AsmString = "tgu %xcc, $\x01 + $\x02";
4117  break;
4118  }
4119  if (MCInst_getNumOperands(MI) == 3 &&
4120  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4121  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4122  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4123  // (TXCCri G0, i32imm:$imm, 12)
4124  AsmString = "tgu %xcc, $\x02";
4125  break;
4126  }
4127  if (MCInst_getNumOperands(MI) == 3 &&
4128  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4129  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4130  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4131  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4132  // (TXCCri IntRegs:$rs1, i32imm:$imm, 4)
4133  AsmString = "tleu %xcc, $\x01 + $\x02";
4134  break;
4135  }
4136  if (MCInst_getNumOperands(MI) == 3 &&
4137  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4138  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4139  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4140  // (TXCCri G0, i32imm:$imm, 4)
4141  AsmString = "tleu %xcc, $\x02";
4142  break;
4143  }
4144  if (MCInst_getNumOperands(MI) == 3 &&
4145  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4146  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4147  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4148  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4149  // (TXCCri IntRegs:$rs1, i32imm:$imm, 13)
4150  AsmString = "tcc %xcc, $\x01 + $\x02";
4151  break;
4152  }
4153  if (MCInst_getNumOperands(MI) == 3 &&
4154  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4155  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4156  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4157  // (TXCCri G0, i32imm:$imm, 13)
4158  AsmString = "tcc %xcc, $\x02";
4159  break;
4160  }
4161  if (MCInst_getNumOperands(MI) == 3 &&
4162  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4163  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4164  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4165  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4166  // (TXCCri IntRegs:$rs1, i32imm:$imm, 5)
4167  AsmString = "tcs %xcc, $\x01 + $\x02";
4168  break;
4169  }
4170  if (MCInst_getNumOperands(MI) == 3 &&
4171  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4172  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4173  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4174  // (TXCCri G0, i32imm:$imm, 5)
4175  AsmString = "tcs %xcc, $\x02";
4176  break;
4177  }
4178  if (MCInst_getNumOperands(MI) == 3 &&
4179  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4180  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4181  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4182  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4183  // (TXCCri IntRegs:$rs1, i32imm:$imm, 14)
4184  AsmString = "tpos %xcc, $\x01 + $\x02";
4185  break;
4186  }
4187  if (MCInst_getNumOperands(MI) == 3 &&
4188  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4189  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4190  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4191  // (TXCCri G0, i32imm:$imm, 14)
4192  AsmString = "tpos %xcc, $\x02";
4193  break;
4194  }
4195  if (MCInst_getNumOperands(MI) == 3 &&
4196  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4197  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4198  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4199  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4200  // (TXCCri IntRegs:$rs1, i32imm:$imm, 6)
4201  AsmString = "tneg %xcc, $\x01 + $\x02";
4202  break;
4203  }
4204  if (MCInst_getNumOperands(MI) == 3 &&
4205  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4206  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4207  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4208  // (TXCCri G0, i32imm:$imm, 6)
4209  AsmString = "tneg %xcc, $\x02";
4210  break;
4211  }
4212  if (MCInst_getNumOperands(MI) == 3 &&
4213  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4214  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4215  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4216  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4217  // (TXCCri IntRegs:$rs1, i32imm:$imm, 15)
4218  AsmString = "tvc %xcc, $\x01 + $\x02";
4219  break;
4220  }
4221  if (MCInst_getNumOperands(MI) == 3 &&
4222  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4223  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4224  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4225  // (TXCCri G0, i32imm:$imm, 15)
4226  AsmString = "tvc %xcc, $\x02";
4227  break;
4228  }
4229  if (MCInst_getNumOperands(MI) == 3 &&
4230  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4231  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4232  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4233  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4234  // (TXCCri IntRegs:$rs1, i32imm:$imm, 7)
4235  AsmString = "tvs %xcc, $\x01 + $\x02";
4236  break;
4237  }
4238  if (MCInst_getNumOperands(MI) == 3 &&
4239  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4240  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4241  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4242  // (TXCCri G0, i32imm:$imm, 7)
4243  AsmString = "tvs %xcc, $\x02";
4244  break;
4245  }
4246  return NULL;
4247  case SP_TXCCrr:
4248  if (MCInst_getNumOperands(MI) == 3 &&
4249  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4250  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4251  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4252  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4253  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4254  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4255  // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 8)
4256  AsmString = "ta %xcc, $\x01 + $\x02";
4257  break;
4258  }
4259  if (MCInst_getNumOperands(MI) == 3 &&
4260  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4261  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4262  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4263  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4264  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 8) {
4265  // (TXCCrr G0, IntRegs:$rs2, 8)
4266  AsmString = "ta %xcc, $\x02";
4267  break;
4268  }
4269  if (MCInst_getNumOperands(MI) == 3 &&
4270  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4271  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4272  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4273  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4274  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4275  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4276  // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 0)
4277  AsmString = "tn %xcc, $\x01 + $\x02";
4278  break;
4279  }
4280  if (MCInst_getNumOperands(MI) == 3 &&
4281  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4282  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4283  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4284  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4285  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 0) {
4286  // (TXCCrr G0, IntRegs:$rs2, 0)
4287  AsmString = "tn %xcc, $\x02";
4288  break;
4289  }
4290  if (MCInst_getNumOperands(MI) == 3 &&
4291  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4292  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4293  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4294  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4295  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4296  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4297  // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 9)
4298  AsmString = "tne %xcc, $\x01 + $\x02";
4299  break;
4300  }
4301  if (MCInst_getNumOperands(MI) == 3 &&
4302  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4303  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4304  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4305  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4306  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 9) {
4307  // (TXCCrr G0, IntRegs:$rs2, 9)
4308  AsmString = "tne %xcc, $\x02";
4309  break;
4310  }
4311  if (MCInst_getNumOperands(MI) == 3 &&
4312  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4313  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4314  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4315  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4316  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4317  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4318  // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 1)
4319  AsmString = "te %xcc, $\x01 + $\x02";
4320  break;
4321  }
4322  if (MCInst_getNumOperands(MI) == 3 &&
4323  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4324  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4325  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4326  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4327  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 1) {
4328  // (TXCCrr G0, IntRegs:$rs2, 1)
4329  AsmString = "te %xcc, $\x02";
4330  break;
4331  }
4332  if (MCInst_getNumOperands(MI) == 3 &&
4333  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4334  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4335  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4336  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4337  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4338  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4339  // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 10)
4340  AsmString = "tg %xcc, $\x01 + $\x02";
4341  break;
4342  }
4343  if (MCInst_getNumOperands(MI) == 3 &&
4344  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4345  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4346  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4347  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4348  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 10) {
4349  // (TXCCrr G0, IntRegs:$rs2, 10)
4350  AsmString = "tg %xcc, $\x02";
4351  break;
4352  }
4353  if (MCInst_getNumOperands(MI) == 3 &&
4354  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4355  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4356  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4357  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4358  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4359  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4360  // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 2)
4361  AsmString = "tle %xcc, $\x01 + $\x02";
4362  break;
4363  }
4364  if (MCInst_getNumOperands(MI) == 3 &&
4365  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4366  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4367  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4368  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4369  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 2) {
4370  // (TXCCrr G0, IntRegs:$rs2, 2)
4371  AsmString = "tle %xcc, $\x02";
4372  break;
4373  }
4374  if (MCInst_getNumOperands(MI) == 3 &&
4375  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4376  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4377  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4378  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4379  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4380  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4381  // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 11)
4382  AsmString = "tge %xcc, $\x01 + $\x02";
4383  break;
4384  }
4385  if (MCInst_getNumOperands(MI) == 3 &&
4386  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4387  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4388  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4389  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4390  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 11) {
4391  // (TXCCrr G0, IntRegs:$rs2, 11)
4392  AsmString = "tge %xcc, $\x02";
4393  break;
4394  }
4395  if (MCInst_getNumOperands(MI) == 3 &&
4396  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4397  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4398  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4399  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4400  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4401  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4402  // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 3)
4403  AsmString = "tl %xcc, $\x01 + $\x02";
4404  break;
4405  }
4406  if (MCInst_getNumOperands(MI) == 3 &&
4407  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4408  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4409  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4410  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4411  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 3) {
4412  // (TXCCrr G0, IntRegs:$rs2, 3)
4413  AsmString = "tl %xcc, $\x02";
4414  break;
4415  }
4416  if (MCInst_getNumOperands(MI) == 3 &&
4417  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4418  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4419  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4420  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4421  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4422  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4423  // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 12)
4424  AsmString = "tgu %xcc, $\x01 + $\x02";
4425  break;
4426  }
4427  if (MCInst_getNumOperands(MI) == 3 &&
4428  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4429  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4430  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4431  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4432  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 12) {
4433  // (TXCCrr G0, IntRegs:$rs2, 12)
4434  AsmString = "tgu %xcc, $\x02";
4435  break;
4436  }
4437  if (MCInst_getNumOperands(MI) == 3 &&
4438  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4439  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4440  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4441  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4442  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4443  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4444  // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 4)
4445  AsmString = "tleu %xcc, $\x01 + $\x02";
4446  break;
4447  }
4448  if (MCInst_getNumOperands(MI) == 3 &&
4449  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4450  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4451  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4452  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4453  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 4) {
4454  // (TXCCrr G0, IntRegs:$rs2, 4)
4455  AsmString = "tleu %xcc, $\x02";
4456  break;
4457  }
4458  if (MCInst_getNumOperands(MI) == 3 &&
4459  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4460  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4461  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4462  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4463  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4464  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4465  // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 13)
4466  AsmString = "tcc %xcc, $\x01 + $\x02";
4467  break;
4468  }
4469  if (MCInst_getNumOperands(MI) == 3 &&
4470  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4471  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4472  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4473  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4474  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 13) {
4475  // (TXCCrr G0, IntRegs:$rs2, 13)
4476  AsmString = "tcc %xcc, $\x02";
4477  break;
4478  }
4479  if (MCInst_getNumOperands(MI) == 3 &&
4480  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4481  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4482  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4483  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4484  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4485  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4486  // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 5)
4487  AsmString = "tcs %xcc, $\x01 + $\x02";
4488  break;
4489  }
4490  if (MCInst_getNumOperands(MI) == 3 &&
4491  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4492  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4493  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4494  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4495  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 5) {
4496  // (TXCCrr G0, IntRegs:$rs2, 5)
4497  AsmString = "tcs %xcc, $\x02";
4498  break;
4499  }
4500  if (MCInst_getNumOperands(MI) == 3 &&
4501  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4502  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4503  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4504  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4505  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4506  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4507  // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 14)
4508  AsmString = "tpos %xcc, $\x01 + $\x02";
4509  break;
4510  }
4511  if (MCInst_getNumOperands(MI) == 3 &&
4512  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4513  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4514  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4515  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4516  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 14) {
4517  // (TXCCrr G0, IntRegs:$rs2, 14)
4518  AsmString = "tpos %xcc, $\x02";
4519  break;
4520  }
4521  if (MCInst_getNumOperands(MI) == 3 &&
4522  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4523  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4524  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4525  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4526  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4527  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4528  // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 6)
4529  AsmString = "tneg %xcc, $\x01 + $\x02";
4530  break;
4531  }
4532  if (MCInst_getNumOperands(MI) == 3 &&
4533  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4534  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4535  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4536  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4537  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 6) {
4538  // (TXCCrr G0, IntRegs:$rs2, 6)
4539  AsmString = "tneg %xcc, $\x02";
4540  break;
4541  }
4542  if (MCInst_getNumOperands(MI) == 3 &&
4543  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4544  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4545  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4546  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4547  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4548  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4549  // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 15)
4550  AsmString = "tvc %xcc, $\x01 + $\x02";
4551  break;
4552  }
4553  if (MCInst_getNumOperands(MI) == 3 &&
4554  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4555  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4556  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4557  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4558  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 15) {
4559  // (TXCCrr G0, IntRegs:$rs2, 15)
4560  AsmString = "tvc %xcc, $\x02";
4561  break;
4562  }
4563  if (MCInst_getNumOperands(MI) == 3 &&
4564  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4565  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
4566  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4567  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4568  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4569  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4570  // (TXCCrr IntRegs:$rs1, IntRegs:$rs2, 7)
4571  AsmString = "tvs %xcc, $\x01 + $\x02";
4572  break;
4573  }
4574  if (MCInst_getNumOperands(MI) == 3 &&
4575  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_G0 &&
4576  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4577  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 1) &&
4578  MCOperand_isImm(MCInst_getOperand(MI, 2)) &&
4579  MCOperand_getImm(MCInst_getOperand(MI, 2)) == 7) {
4580  // (TXCCrr G0, IntRegs:$rs2, 7)
4581  AsmString = "tvs %xcc, $\x02";
4582  break;
4583  }
4584  return NULL;
4585  case SP_V9FCMPD:
4586  if (MCInst_getNumOperands(MI) == 3 &&
4587  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4588  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4589  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4590  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4591  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4592  // (V9FCMPD FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4593  AsmString = "fcmpd $\x02, $\x03";
4594  break;
4595  }
4596  return NULL;
4597  case SP_V9FCMPED:
4598  if (MCInst_getNumOperands(MI) == 3 &&
4599  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4600  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4601  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 1) &&
4602  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4603  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2)) {
4604  // (V9FCMPED FCC0, DFPRegs:$rs1, DFPRegs:$rs2)
4605  AsmString = "fcmped $\x02, $\x03";
4606  break;
4607  }
4608  return NULL;
4609  case SP_V9FCMPEQ:
4610  if (MCInst_getNumOperands(MI) == 3 &&
4611  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4612  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4613  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4614  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4615  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4616  // (V9FCMPEQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4617  AsmString = "fcmpeq $\x02, $\x03";
4618  break;
4619  }
4620  return NULL;
4621  case SP_V9FCMPES:
4622  if (MCInst_getNumOperands(MI) == 3 &&
4623  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4624  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4625  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4626  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4627  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4628  // (V9FCMPES FCC0, FPRegs:$rs1, FPRegs:$rs2)
4629  AsmString = "fcmpes $\x02, $\x03";
4630  break;
4631  }
4632  return NULL;
4633  case SP_V9FCMPQ:
4634  if (MCInst_getNumOperands(MI) == 3 &&
4635  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4636  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4637  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 1) &&
4638  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4639  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2)) {
4640  // (V9FCMPQ FCC0, QFPRegs:$rs1, QFPRegs:$rs2)
4641  AsmString = "fcmpq $\x02, $\x03";
4642  break;
4643  }
4644  return NULL;
4645  case SP_V9FCMPS:
4646  if (MCInst_getNumOperands(MI) == 3 &&
4647  MCOperand_getReg(MCInst_getOperand(MI, 0)) == SP_FCC0 &&
4648  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4649  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 1) &&
4650  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4651  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2)) {
4652  // (V9FCMPS FCC0, FPRegs:$rs1, FPRegs:$rs2)
4653  AsmString = "fcmps $\x02, $\x03";
4654  break;
4655  }
4656  return NULL;
4657  case SP_V9FMOVD_FCC:
4658  if (MCInst_getNumOperands(MI) == 4 &&
4659  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4660  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4661  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4662  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4663  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4664  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4665  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4666  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4667  // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 0)
4668  AsmString = "fmovda $\x02, $\x03, $\x01";
4669  break;
4670  }
4671  if (MCInst_getNumOperands(MI) == 4 &&
4672  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4673  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4674  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4675  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4676  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4677  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4678  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4679  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4680  // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 8)
4681  AsmString = "fmovdn $\x02, $\x03, $\x01";
4682  break;
4683  }
4684  if (MCInst_getNumOperands(MI) == 4 &&
4685  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4686  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4687  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4688  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4689  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4690  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4691  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4692  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4693  // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 7)
4694  AsmString = "fmovdu $\x02, $\x03, $\x01";
4695  break;
4696  }
4697  if (MCInst_getNumOperands(MI) == 4 &&
4698  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4699  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4700  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4701  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4702  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4703  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4704  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4705  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4706  // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 6)
4707  AsmString = "fmovdg $\x02, $\x03, $\x01";
4708  break;
4709  }
4710  if (MCInst_getNumOperands(MI) == 4 &&
4711  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4712  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4713  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4714  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4715  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4716  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4717  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4718  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4719  // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 5)
4720  AsmString = "fmovdug $\x02, $\x03, $\x01";
4721  break;
4722  }
4723  if (MCInst_getNumOperands(MI) == 4 &&
4724  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4725  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4726  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4727  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4728  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4729  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4730  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4731  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4732  // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 4)
4733  AsmString = "fmovdl $\x02, $\x03, $\x01";
4734  break;
4735  }
4736  if (MCInst_getNumOperands(MI) == 4 &&
4737  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4738  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4739  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4740  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4741  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4742  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4743  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4744  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4745  // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 3)
4746  AsmString = "fmovdul $\x02, $\x03, $\x01";
4747  break;
4748  }
4749  if (MCInst_getNumOperands(MI) == 4 &&
4750  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4751  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4752  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4753  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4754  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4755  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4756  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4757  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4758  // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 2)
4759  AsmString = "fmovdlg $\x02, $\x03, $\x01";
4760  break;
4761  }
4762  if (MCInst_getNumOperands(MI) == 4 &&
4763  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4764  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4765  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4766  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4767  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4768  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4769  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4770  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4771  // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 1)
4772  AsmString = "fmovdne $\x02, $\x03, $\x01";
4773  break;
4774  }
4775  if (MCInst_getNumOperands(MI) == 4 &&
4776  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4777  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4778  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4779  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4780  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4781  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4782  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4783  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4784  // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 9)
4785  AsmString = "fmovde $\x02, $\x03, $\x01";
4786  break;
4787  }
4788  if (MCInst_getNumOperands(MI) == 4 &&
4789  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4790  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4791  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4792  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4793  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4794  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4795  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4796  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
4797  // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 10)
4798  AsmString = "fmovdue $\x02, $\x03, $\x01";
4799  break;
4800  }
4801  if (MCInst_getNumOperands(MI) == 4 &&
4802  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4803  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4804  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4805  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4806  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4807  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4808  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4809  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
4810  // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 11)
4811  AsmString = "fmovdge $\x02, $\x03, $\x01";
4812  break;
4813  }
4814  if (MCInst_getNumOperands(MI) == 4 &&
4815  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4816  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4817  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4818  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4819  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4820  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4821  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4822  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
4823  // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 12)
4824  AsmString = "fmovduge $\x02, $\x03, $\x01";
4825  break;
4826  }
4827  if (MCInst_getNumOperands(MI) == 4 &&
4828  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4829  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4830  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4831  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4832  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4833  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4834  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4835  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
4836  // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 13)
4837  AsmString = "fmovdle $\x02, $\x03, $\x01";
4838  break;
4839  }
4840  if (MCInst_getNumOperands(MI) == 4 &&
4841  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4842  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4843  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4844  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4845  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4846  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4847  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4848  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
4849  // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 14)
4850  AsmString = "fmovdule $\x02, $\x03, $\x01";
4851  break;
4852  }
4853  if (MCInst_getNumOperands(MI) == 4 &&
4854  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4855  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 0) &&
4856  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4857  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4858  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4859  GETREGCLASS_CONTAIN(SP_DFPRegsRegClassID, 2) &&
4860  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4861  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
4862  // (V9FMOVD_FCC DFPRegs:$rd, FCCRegs:$cc, DFPRegs:$rs2, 15)
4863  AsmString = "fmovdo $\x02, $\x03, $\x01";
4864  break;
4865  }
4866  return NULL;
4867  case SP_V9FMOVQ_FCC:
4868  if (MCInst_getNumOperands(MI) == 4 &&
4869  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4870  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4871  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4872  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4873  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4874  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4875  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4876  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
4877  // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 0)
4878  AsmString = "fmovqa $\x02, $\x03, $\x01";
4879  break;
4880  }
4881  if (MCInst_getNumOperands(MI) == 4 &&
4882  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4883  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4884  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4885  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4886  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4887  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4888  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4889  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
4890  // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 8)
4891  AsmString = "fmovqn $\x02, $\x03, $\x01";
4892  break;
4893  }
4894  if (MCInst_getNumOperands(MI) == 4 &&
4895  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4896  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4897  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4898  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4899  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4900  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4901  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4902  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
4903  // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 7)
4904  AsmString = "fmovqu $\x02, $\x03, $\x01";
4905  break;
4906  }
4907  if (MCInst_getNumOperands(MI) == 4 &&
4908  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4909  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4910  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4911  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4912  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4913  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4914  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4915  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
4916  // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 6)
4917  AsmString = "fmovqg $\x02, $\x03, $\x01";
4918  break;
4919  }
4920  if (MCInst_getNumOperands(MI) == 4 &&
4921  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4922  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4923  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4924  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4925  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4926  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4927  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4928  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
4929  // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 5)
4930  AsmString = "fmovqug $\x02, $\x03, $\x01";
4931  break;
4932  }
4933  if (MCInst_getNumOperands(MI) == 4 &&
4934  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4935  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4936  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4937  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4938  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4939  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4940  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4941  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
4942  // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 4)
4943  AsmString = "fmovql $\x02, $\x03, $\x01";
4944  break;
4945  }
4946  if (MCInst_getNumOperands(MI) == 4 &&
4947  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4948  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4949  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4950  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4951  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4952  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4953  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4954  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
4955  // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 3)
4956  AsmString = "fmovqul $\x02, $\x03, $\x01";
4957  break;
4958  }
4959  if (MCInst_getNumOperands(MI) == 4 &&
4960  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4961  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4962  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4963  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4964  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4965  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4966  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4967  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
4968  // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 2)
4969  AsmString = "fmovqlg $\x02, $\x03, $\x01";
4970  break;
4971  }
4972  if (MCInst_getNumOperands(MI) == 4 &&
4973  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4974  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4975  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4976  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4977  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4978  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4979  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4980  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
4981  // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 1)
4982  AsmString = "fmovqne $\x02, $\x03, $\x01";
4983  break;
4984  }
4985  if (MCInst_getNumOperands(MI) == 4 &&
4986  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
4987  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
4988  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
4989  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
4990  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
4991  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
4992  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
4993  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
4994  // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 9)
4995  AsmString = "fmovqe $\x02, $\x03, $\x01";
4996  break;
4997  }
4998  if (MCInst_getNumOperands(MI) == 4 &&
4999  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5000  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5001  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5002  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5003  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5004  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5005  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5006  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5007  // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 10)
5008  AsmString = "fmovque $\x02, $\x03, $\x01";
5009  break;
5010  }
5011  if (MCInst_getNumOperands(MI) == 4 &&
5012  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5013  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5014  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5015  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5016  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5017  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5018  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5019  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5020  // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 11)
5021  AsmString = "fmovqge $\x02, $\x03, $\x01";
5022  break;
5023  }
5024  if (MCInst_getNumOperands(MI) == 4 &&
5025  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5026  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5027  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5028  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5029  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5030  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5031  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5032  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5033  // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 12)
5034  AsmString = "fmovquge $\x02, $\x03, $\x01";
5035  break;
5036  }
5037  if (MCInst_getNumOperands(MI) == 4 &&
5038  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5039  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5040  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5041  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5042  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5043  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5044  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5045  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5046  // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 13)
5047  AsmString = "fmovqle $\x02, $\x03, $\x01";
5048  break;
5049  }
5050  if (MCInst_getNumOperands(MI) == 4 &&
5051  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5052  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5053  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5054  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5055  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5056  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5057  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5058  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5059  // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 14)
5060  AsmString = "fmovqule $\x02, $\x03, $\x01";
5061  break;
5062  }
5063  if (MCInst_getNumOperands(MI) == 4 &&
5064  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5065  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 0) &&
5066  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5067  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5068  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5069  GETREGCLASS_CONTAIN(SP_QFPRegsRegClassID, 2) &&
5070  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5071  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5072  // (V9FMOVQ_FCC QFPRegs:$rd, FCCRegs:$cc, QFPRegs:$rs2, 15)
5073  AsmString = "fmovqo $\x02, $\x03, $\x01";
5074  break;
5075  }
5076  return NULL;
5077  case SP_V9FMOVS_FCC:
5078  if (MCInst_getNumOperands(MI) == 4 &&
5079  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5080  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5081  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5082  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5083  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5084  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5085  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5086  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5087  // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 0)
5088  AsmString = "fmovsa $\x02, $\x03, $\x01";
5089  break;
5090  }
5091  if (MCInst_getNumOperands(MI) == 4 &&
5092  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5093  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5094  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5095  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5096  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5097  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5098  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5099  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5100  // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 8)
5101  AsmString = "fmovsn $\x02, $\x03, $\x01";
5102  break;
5103  }
5104  if (MCInst_getNumOperands(MI) == 4 &&
5105  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5106  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5107  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5108  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5109  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5110  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5111  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5112  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5113  // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 7)
5114  AsmString = "fmovsu $\x02, $\x03, $\x01";
5115  break;
5116  }
5117  if (MCInst_getNumOperands(MI) == 4 &&
5118  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5119  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5120  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5121  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5122  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5123  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5124  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5125  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5126  // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 6)
5127  AsmString = "fmovsg $\x02, $\x03, $\x01";
5128  break;
5129  }
5130  if (MCInst_getNumOperands(MI) == 4 &&
5131  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5132  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5133  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5134  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5135  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5136  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5137  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5138  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5139  // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 5)
5140  AsmString = "fmovsug $\x02, $\x03, $\x01";
5141  break;
5142  }
5143  if (MCInst_getNumOperands(MI) == 4 &&
5144  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5145  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5146  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5147  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5148  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5149  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5150  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5151  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5152  // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 4)
5153  AsmString = "fmovsl $\x02, $\x03, $\x01";
5154  break;
5155  }
5156  if (MCInst_getNumOperands(MI) == 4 &&
5157  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5158  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5159  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5160  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5161  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5162  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5163  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5164  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5165  // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 3)
5166  AsmString = "fmovsul $\x02, $\x03, $\x01";
5167  break;
5168  }
5169  if (MCInst_getNumOperands(MI) == 4 &&
5170  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5171  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5172  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5173  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5174  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5175  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5176  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5177  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5178  // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 2)
5179  AsmString = "fmovslg $\x02, $\x03, $\x01";
5180  break;
5181  }
5182  if (MCInst_getNumOperands(MI) == 4 &&
5183  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5184  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5185  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5186  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5187  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5188  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5189  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5190  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5191  // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 1)
5192  AsmString = "fmovsne $\x02, $\x03, $\x01";
5193  break;
5194  }
5195  if (MCInst_getNumOperands(MI) == 4 &&
5196  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5197  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5198  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5199  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5200  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5201  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5202  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5203  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5204  // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 9)
5205  AsmString = "fmovse $\x02, $\x03, $\x01";
5206  break;
5207  }
5208  if (MCInst_getNumOperands(MI) == 4 &&
5209  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5210  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5211  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5212  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5213  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5214  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5215  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5216  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5217  // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 10)
5218  AsmString = "fmovsue $\x02, $\x03, $\x01";
5219  break;
5220  }
5221  if (MCInst_getNumOperands(MI) == 4 &&
5222  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5223  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5224  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5225  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5226  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5227  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5228  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5229  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5230  // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 11)
5231  AsmString = "fmovsge $\x02, $\x03, $\x01";
5232  break;
5233  }
5234  if (MCInst_getNumOperands(MI) == 4 &&
5235  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5236  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5237  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5238  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5239  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5240  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5241  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5242  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5243  // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 12)
5244  AsmString = "fmovsuge $\x02, $\x03, $\x01";
5245  break;
5246  }
5247  if (MCInst_getNumOperands(MI) == 4 &&
5248  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5249  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5250  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5251  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5252  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5253  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5254  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5255  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5256  // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 13)
5257  AsmString = "fmovsle $\x02, $\x03, $\x01";
5258  break;
5259  }
5260  if (MCInst_getNumOperands(MI) == 4 &&
5261  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5262  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5263  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5264  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5265  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5266  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5267  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5268  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5269  // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 14)
5270  AsmString = "fmovsule $\x02, $\x03, $\x01";
5271  break;
5272  }
5273  if (MCInst_getNumOperands(MI) == 4 &&
5274  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5275  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 0) &&
5276  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5277  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5278  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5279  GETREGCLASS_CONTAIN(SP_FPRegsRegClassID, 2) &&
5280  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5281  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5282  // (V9FMOVS_FCC FPRegs:$rd, FCCRegs:$cc, FPRegs:$rs2, 15)
5283  AsmString = "fmovso $\x02, $\x03, $\x01";
5284  break;
5285  }
5286  return NULL;
5287  case SP_V9MOVFCCri:
5288  if (MCInst_getNumOperands(MI) == 4 &&
5289  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5290  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5291  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5292  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5293  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5294  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5295  // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 0)
5296  AsmString = "mova $\x02, $\x03, $\x01";
5297  break;
5298  }
5299  if (MCInst_getNumOperands(MI) == 4 &&
5300  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5301  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5302  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5303  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5304  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5305  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5306  // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 8)
5307  AsmString = "movn $\x02, $\x03, $\x01";
5308  break;
5309  }
5310  if (MCInst_getNumOperands(MI) == 4 &&
5311  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5312  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5313  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5314  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5315  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5316  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5317  // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 7)
5318  AsmString = "movu $\x02, $\x03, $\x01";
5319  break;
5320  }
5321  if (MCInst_getNumOperands(MI) == 4 &&
5322  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5323  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5324  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5325  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5326  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5327  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5328  // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 6)
5329  AsmString = "movg $\x02, $\x03, $\x01";
5330  break;
5331  }
5332  if (MCInst_getNumOperands(MI) == 4 &&
5333  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5334  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5335  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5336  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5337  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5338  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5339  // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 5)
5340  AsmString = "movug $\x02, $\x03, $\x01";
5341  break;
5342  }
5343  if (MCInst_getNumOperands(MI) == 4 &&
5344  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5345  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5346  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5347  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5348  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5349  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5350  // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 4)
5351  AsmString = "movl $\x02, $\x03, $\x01";
5352  break;
5353  }
5354  if (MCInst_getNumOperands(MI) == 4 &&
5355  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5356  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5357  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5358  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5359  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5360  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5361  // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 3)
5362  AsmString = "movul $\x02, $\x03, $\x01";
5363  break;
5364  }
5365  if (MCInst_getNumOperands(MI) == 4 &&
5366  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5367  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5368  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5369  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5370  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5371  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5372  // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 2)
5373  AsmString = "movlg $\x02, $\x03, $\x01";
5374  break;
5375  }
5376  if (MCInst_getNumOperands(MI) == 4 &&
5377  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5378  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5379  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5380  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5381  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5382  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5383  // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 1)
5384  AsmString = "movne $\x02, $\x03, $\x01";
5385  break;
5386  }
5387  if (MCInst_getNumOperands(MI) == 4 &&
5388  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5389  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5390  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5391  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5392  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5393  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5394  // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 9)
5395  AsmString = "move $\x02, $\x03, $\x01";
5396  break;
5397  }
5398  if (MCInst_getNumOperands(MI) == 4 &&
5399  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5400  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5401  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5402  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5403  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5404  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5405  // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 10)
5406  AsmString = "movue $\x02, $\x03, $\x01";
5407  break;
5408  }
5409  if (MCInst_getNumOperands(MI) == 4 &&
5410  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5411  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5412  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5413  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5414  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5415  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5416  // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 11)
5417  AsmString = "movge $\x02, $\x03, $\x01";
5418  break;
5419  }
5420  if (MCInst_getNumOperands(MI) == 4 &&
5421  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5422  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5423  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5424  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5425  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5426  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5427  // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 12)
5428  AsmString = "movuge $\x02, $\x03, $\x01";
5429  break;
5430  }
5431  if (MCInst_getNumOperands(MI) == 4 &&
5432  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5433  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5434  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5435  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5436  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5437  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5438  // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 13)
5439  AsmString = "movle $\x02, $\x03, $\x01";
5440  break;
5441  }
5442  if (MCInst_getNumOperands(MI) == 4 &&
5443  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5444  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5445  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5446  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5447  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5448  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5449  // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 14)
5450  AsmString = "movule $\x02, $\x03, $\x01";
5451  break;
5452  }
5453  if (MCInst_getNumOperands(MI) == 4 &&
5454  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5455  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5456  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5457  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5458  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5459  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5460  // (V9MOVFCCri IntRegs:$rd, FCCRegs:$cc, i32imm:$simm11, 15)
5461  AsmString = "movo $\x02, $\x03, $\x01";
5462  break;
5463  }
5464  return NULL;
5465  case SP_V9MOVFCCrr:
5466  if (MCInst_getNumOperands(MI) == 4 &&
5467  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5468  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5469  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5470  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5471  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5472  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5473  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5474  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 0) {
5475  // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 0)
5476  AsmString = "mova $\x02, $\x03, $\x01";
5477  break;
5478  }
5479  if (MCInst_getNumOperands(MI) == 4 &&
5480  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5481  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5482  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5483  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5484  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5485  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5486  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5487  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 8) {
5488  // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 8)
5489  AsmString = "movn $\x02, $\x03, $\x01";
5490  break;
5491  }
5492  if (MCInst_getNumOperands(MI) == 4 &&
5493  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5494  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5495  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5496  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5497  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5498  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5499  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5500  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 7) {
5501  // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 7)
5502  AsmString = "movu $\x02, $\x03, $\x01";
5503  break;
5504  }
5505  if (MCInst_getNumOperands(MI) == 4 &&
5506  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5507  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5508  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5509  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5510  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5511  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5512  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5513  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 6) {
5514  // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 6)
5515  AsmString = "movg $\x02, $\x03, $\x01";
5516  break;
5517  }
5518  if (MCInst_getNumOperands(MI) == 4 &&
5519  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5520  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5521  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5522  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5523  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5524  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5525  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5526  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 5) {
5527  // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 5)
5528  AsmString = "movug $\x02, $\x03, $\x01";
5529  break;
5530  }
5531  if (MCInst_getNumOperands(MI) == 4 &&
5532  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5533  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5534  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5535  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5536  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5537  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5538  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5539  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 4) {
5540  // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 4)
5541  AsmString = "movl $\x02, $\x03, $\x01";
5542  break;
5543  }
5544  if (MCInst_getNumOperands(MI) == 4 &&
5545  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5546  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5547  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5548  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5549  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5550  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5551  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5552  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 3) {
5553  // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 3)
5554  AsmString = "movul $\x02, $\x03, $\x01";
5555  break;
5556  }
5557  if (MCInst_getNumOperands(MI) == 4 &&
5558  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5559  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5560  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5561  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5562  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5563  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5564  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5565  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 2) {
5566  // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 2)
5567  AsmString = "movlg $\x02, $\x03, $\x01";
5568  break;
5569  }
5570  if (MCInst_getNumOperands(MI) == 4 &&
5571  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5572  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5573  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5574  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5575  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5576  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5577  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5578  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 1) {
5579  // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 1)
5580  AsmString = "movne $\x02, $\x03, $\x01";
5581  break;
5582  }
5583  if (MCInst_getNumOperands(MI) == 4 &&
5584  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5585  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5586  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5587  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5588  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5589  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5590  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5591  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 9) {
5592  // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 9)
5593  AsmString = "move $\x02, $\x03, $\x01";
5594  break;
5595  }
5596  if (MCInst_getNumOperands(MI) == 4 &&
5597  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5598  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5599  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5600  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5601  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5602  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5603  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5604  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 10) {
5605  // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 10)
5606  AsmString = "movue $\x02, $\x03, $\x01";
5607  break;
5608  }
5609  if (MCInst_getNumOperands(MI) == 4 &&
5610  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5611  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5612  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5613  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5614  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5615  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5616  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5617  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 11) {
5618  // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 11)
5619  AsmString = "movge $\x02, $\x03, $\x01";
5620  break;
5621  }
5622  if (MCInst_getNumOperands(MI) == 4 &&
5623  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5624  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5625  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5626  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5627  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5628  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5629  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5630  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 12) {
5631  // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 12)
5632  AsmString = "movuge $\x02, $\x03, $\x01";
5633  break;
5634  }
5635  if (MCInst_getNumOperands(MI) == 4 &&
5636  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5637  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5638  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5639  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5640  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5641  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5642  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5643  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 13) {
5644  // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 13)
5645  AsmString = "movle $\x02, $\x03, $\x01";
5646  break;
5647  }
5648  if (MCInst_getNumOperands(MI) == 4 &&
5649  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5650  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5651  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5652  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5653  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5654  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5655  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5656  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 14) {
5657  // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 14)
5658  AsmString = "movule $\x02, $\x03, $\x01";
5659  break;
5660  }
5661  if (MCInst_getNumOperands(MI) == 4 &&
5662  MCOperand_isReg(MCInst_getOperand(MI, 0)) &&
5663  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 0) &&
5664  MCOperand_isReg(MCInst_getOperand(MI, 1)) &&
5665  GETREGCLASS_CONTAIN(SP_FCCRegsRegClassID, 1) &&
5666  MCOperand_isReg(MCInst_getOperand(MI, 2)) &&
5667  GETREGCLASS_CONTAIN(SP_IntRegsRegClassID, 2) &&
5668  MCOperand_isImm(MCInst_getOperand(MI, 3)) &&
5669  MCOperand_getImm(MCInst_getOperand(MI, 3)) == 15) {
5670  // (V9MOVFCCrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, 15)
5671  AsmString = "movo $\x02, $\x03, $\x01";
5672  break;
5673  }
5674  return NULL;
5675  }
5676 
5677  tmp = cs_strdup(AsmString);
5678  AsmMnem = tmp;
5679  for(AsmOps = tmp; *AsmOps; AsmOps++) {
5680  if (*AsmOps == ' ' || *AsmOps == '\t') {
5681  *AsmOps = '\0';
5682  AsmOps++;
5683  break;
5684  }
5685  }
5686  SStream_concat0(OS, AsmMnem);
5687  if (*AsmOps) {
5688  SStream_concat0(OS, "\t");
5689  if (strstr(AsmOps, "icc"))
5690  Sparc_addReg(MI, SPARC_REG_ICC);
5691  if (strstr(AsmOps, "xcc"))
5692  Sparc_addReg(MI, SPARC_REG_XCC);
5693  for (c = AsmOps; *c; c++) {
5694  if (*c == '$') {
5695  c += 1;
5696  if (*c == (char)0xff) {
5697  c += 1;
5698  OpIdx = *c - 1;
5699  c += 1;
5700  PrintMethodIdx = *c - 1;
5701  printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, OS);
5702  } else
5703  printOperand(MI, *c - 1, OS);
5704  } else {
5705  SStream_concat(OS, "%c", *c);
5706  }
5707  }
5708  }
5709  return tmp;
5710 }
5711 
5712 #endif // PRINT_ALIAS_INSTR
MCInst_getOpcode
unsigned MCInst_getOpcode(const MCInst *inst)
Definition: MCInst.c:68
MCInst_getNumOperands
unsigned MCInst_getNumOperands(const MCInst *inst)
Definition: MCInst.c:83
MCInst_getOperand
MCOperand * MCInst_getOperand(MCInst *inst, unsigned i)
Definition: MCInst.c:78
MCOperand_isReg
bool MCOperand_isReg(const MCOperand *op)
Definition: MCInst.c:101
MCOperand_getImm
int64_t MCOperand_getImm(MCOperand *op)
Definition: MCInst.c:128
MCOperand_getReg
unsigned MCOperand_getReg(const MCOperand *op)
getReg - Returns the register number.
Definition: MCInst.c:117
MCOperand_isImm
bool MCOperand_isImm(const MCOperand *op)
Definition: MCInst.c:106
SStream_concat
void SStream_concat(SStream *ss, const char *fmt,...)
Definition: SStream.c:45
SStream_concat0
void SStream_concat0(SStream *ss, const char *s)
Definition: SStream.c:31
Sparc_addReg
void Sparc_addReg(MCInst *MI, int reg)
info
RzBinInfo * info(RzBinFile *bf)
Definition: bin_ne.c:86
NULL
#define NULL
Definition: cris-opc.c:27
OS
@ OS
Definition: inflate.h:24
autogen_x86imm.tmp
tmp
Definition: autogen_x86imm.py:12
O
#define O
Definition: rcond.c:14
uint16_t
unsigned short uint16_t
Definition: sftypes.h:30
uint32_t
unsigned int uint32_t
Definition: sftypes.h:29
c
#define c(i)
Definition: sha256.c:43
MCInst
Definition: MCInst.h:88
SStream
Definition: SStream.h:9
SPARC_HINT_A
@ SPARC_HINT_A
annul delay slot instruction
Definition: sparc.h:64
SPARC_HINT_PN
@ SPARC_HINT_PN
branch NOT taken
Definition: sparc.h:66
SPARC_REG_FCC0
@ SPARC_REG_FCC0
Definition: sparc.h:129
SPARC_REG_ICC
@ SPARC_REG_ICC
Definition: sparc.h:149
SPARC_REG_Y
@ SPARC_REG_Y
Definition: sparc.h:166
SPARC_REG_XCC
@ SPARC_REG_XCC
Definition: sparc.h:169
cs_strdup
char * cs_strdup(const char *str)
Definition: utils.c:92