Rizin
unix-like reverse engineering framework and cli tools
MipsMappingInsn.inc
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1 // This is auto-gen data for Capstone engine (www.capstone-engine.org)
2 // By Nguyen Anh Quynh <aquynh@gmail.com>
3 
4 {
5  Mips_ABSQ_S_PH, MIPS_INS_ABSQ_S,
6 #ifndef CAPSTONE_DIET
7  { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
8 #endif
9 },
10 {
11  Mips_ABSQ_S_QB, MIPS_INS_ABSQ_S,
12 #ifndef CAPSTONE_DIET
13  { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
14 #endif
15 },
16 {
17  Mips_ABSQ_S_W, MIPS_INS_ABSQ_S,
18 #ifndef CAPSTONE_DIET
19  { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
20 #endif
21 },
22 {
23  Mips_ADD, MIPS_INS_ADD,
24 #ifndef CAPSTONE_DIET
25  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
26 #endif
27 },
28 {
29  Mips_ADDIUPC, MIPS_INS_ADDIUPC,
30 #ifndef CAPSTONE_DIET
31  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
32 #endif
33 },
34 {
35  Mips_ADDIUPC_MM, MIPS_INS_ADDIUPC,
36 #ifndef CAPSTONE_DIET
37  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
38 #endif
39 },
40 {
41  Mips_ADDIUR1SP_MM, MIPS_INS_ADDIUR1SP,
42 #ifndef CAPSTONE_DIET
43  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
44 #endif
45 },
46 {
47  Mips_ADDIUR2_MM, MIPS_INS_ADDIUR2,
48 #ifndef CAPSTONE_DIET
49  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
50 #endif
51 },
52 {
53  Mips_ADDIUS5_MM, MIPS_INS_ADDIUS5,
54 #ifndef CAPSTONE_DIET
55  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
56 #endif
57 },
58 {
59  Mips_ADDIUSP_MM, MIPS_INS_ADDIUSP,
60 #ifndef CAPSTONE_DIET
61  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
62 #endif
63 },
64 {
65  Mips_ADDQH_PH, MIPS_INS_ADDQH,
66 #ifndef CAPSTONE_DIET
67  { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
68 #endif
69 },
70 {
71  Mips_ADDQH_R_PH, MIPS_INS_ADDQH_R,
72 #ifndef CAPSTONE_DIET
73  { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
74 #endif
75 },
76 {
77  Mips_ADDQH_R_W, MIPS_INS_ADDQH_R,
78 #ifndef CAPSTONE_DIET
79  { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
80 #endif
81 },
82 {
83  Mips_ADDQH_W, MIPS_INS_ADDQH,
84 #ifndef CAPSTONE_DIET
85  { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
86 #endif
87 },
88 {
89  Mips_ADDQ_PH, MIPS_INS_ADDQ,
90 #ifndef CAPSTONE_DIET
91  { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
92 #endif
93 },
94 {
95  Mips_ADDQ_S_PH, MIPS_INS_ADDQ_S,
96 #ifndef CAPSTONE_DIET
97  { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
98 #endif
99 },
100 {
101  Mips_ADDQ_S_W, MIPS_INS_ADDQ_S,
102 #ifndef CAPSTONE_DIET
103  { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
104 #endif
105 },
106 {
107  Mips_ADDSC, MIPS_INS_ADDSC,
108 #ifndef CAPSTONE_DIET
109  { 0 }, { MIPS_REG_DSPCARRY, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
110 #endif
111 },
112 {
113  Mips_ADDS_A_B, MIPS_INS_ADDS_A,
114 #ifndef CAPSTONE_DIET
115  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
116 #endif
117 },
118 {
119  Mips_ADDS_A_D, MIPS_INS_ADDS_A,
120 #ifndef CAPSTONE_DIET
121  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
122 #endif
123 },
124 {
125  Mips_ADDS_A_H, MIPS_INS_ADDS_A,
126 #ifndef CAPSTONE_DIET
127  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
128 #endif
129 },
130 {
131  Mips_ADDS_A_W, MIPS_INS_ADDS_A,
132 #ifndef CAPSTONE_DIET
133  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
134 #endif
135 },
136 {
137  Mips_ADDS_S_B, MIPS_INS_ADDS_S,
138 #ifndef CAPSTONE_DIET
139  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
140 #endif
141 },
142 {
143  Mips_ADDS_S_D, MIPS_INS_ADDS_S,
144 #ifndef CAPSTONE_DIET
145  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
146 #endif
147 },
148 {
149  Mips_ADDS_S_H, MIPS_INS_ADDS_S,
150 #ifndef CAPSTONE_DIET
151  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
152 #endif
153 },
154 {
155  Mips_ADDS_S_W, MIPS_INS_ADDS_S,
156 #ifndef CAPSTONE_DIET
157  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
158 #endif
159 },
160 {
161  Mips_ADDS_U_B, MIPS_INS_ADDS_U,
162 #ifndef CAPSTONE_DIET
163  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
164 #endif
165 },
166 {
167  Mips_ADDS_U_D, MIPS_INS_ADDS_U,
168 #ifndef CAPSTONE_DIET
169  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
170 #endif
171 },
172 {
173  Mips_ADDS_U_H, MIPS_INS_ADDS_U,
174 #ifndef CAPSTONE_DIET
175  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
176 #endif
177 },
178 {
179  Mips_ADDS_U_W, MIPS_INS_ADDS_U,
180 #ifndef CAPSTONE_DIET
181  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
182 #endif
183 },
184 {
185  Mips_ADDU16_MM, MIPS_INS_ADDU16,
186 #ifndef CAPSTONE_DIET
187  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
188 #endif
189 },
190 {
191  Mips_ADDUH_QB, MIPS_INS_ADDUH,
192 #ifndef CAPSTONE_DIET
193  { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
194 #endif
195 },
196 {
197  Mips_ADDUH_R_QB, MIPS_INS_ADDUH_R,
198 #ifndef CAPSTONE_DIET
199  { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
200 #endif
201 },
202 {
203  Mips_ADDU_PH, MIPS_INS_ADDU,
204 #ifndef CAPSTONE_DIET
205  { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
206 #endif
207 },
208 {
209  Mips_ADDU_QB, MIPS_INS_ADDU,
210 #ifndef CAPSTONE_DIET
211  { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
212 #endif
213 },
214 {
215  Mips_ADDU_S_PH, MIPS_INS_ADDU_S,
216 #ifndef CAPSTONE_DIET
217  { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
218 #endif
219 },
220 {
221  Mips_ADDU_S_QB, MIPS_INS_ADDU_S,
222 #ifndef CAPSTONE_DIET
223  { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
224 #endif
225 },
226 {
227  Mips_ADDVI_B, MIPS_INS_ADDVI,
228 #ifndef CAPSTONE_DIET
229  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
230 #endif
231 },
232 {
233  Mips_ADDVI_D, MIPS_INS_ADDVI,
234 #ifndef CAPSTONE_DIET
235  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
236 #endif
237 },
238 {
239  Mips_ADDVI_H, MIPS_INS_ADDVI,
240 #ifndef CAPSTONE_DIET
241  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
242 #endif
243 },
244 {
245  Mips_ADDVI_W, MIPS_INS_ADDVI,
246 #ifndef CAPSTONE_DIET
247  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
248 #endif
249 },
250 {
251  Mips_ADDV_B, MIPS_INS_ADDV,
252 #ifndef CAPSTONE_DIET
253  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
254 #endif
255 },
256 {
257  Mips_ADDV_D, MIPS_INS_ADDV,
258 #ifndef CAPSTONE_DIET
259  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
260 #endif
261 },
262 {
263  Mips_ADDV_H, MIPS_INS_ADDV,
264 #ifndef CAPSTONE_DIET
265  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
266 #endif
267 },
268 {
269  Mips_ADDV_W, MIPS_INS_ADDV,
270 #ifndef CAPSTONE_DIET
271  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
272 #endif
273 },
274 {
275  Mips_ADDWC, MIPS_INS_ADDWC,
276 #ifndef CAPSTONE_DIET
277  { MIPS_REG_DSPCARRY, 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
278 #endif
279 },
280 {
281  Mips_ADD_A_B, MIPS_INS_ADD_A,
282 #ifndef CAPSTONE_DIET
283  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
284 #endif
285 },
286 {
287  Mips_ADD_A_D, MIPS_INS_ADD_A,
288 #ifndef CAPSTONE_DIET
289  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
290 #endif
291 },
292 {
293  Mips_ADD_A_H, MIPS_INS_ADD_A,
294 #ifndef CAPSTONE_DIET
295  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
296 #endif
297 },
298 {
299  Mips_ADD_A_W, MIPS_INS_ADD_A,
300 #ifndef CAPSTONE_DIET
301  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
302 #endif
303 },
304 {
305  Mips_ADD_MM, MIPS_INS_ADD,
306 #ifndef CAPSTONE_DIET
307  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
308 #endif
309 },
310 {
311  Mips_ADDi, MIPS_INS_ADDI,
312 #ifndef CAPSTONE_DIET
313  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
314 #endif
315 },
316 {
317  Mips_ADDi_MM, MIPS_INS_ADDI,
318 #ifndef CAPSTONE_DIET
319  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
320 #endif
321 },
322 {
323  Mips_ADDiu, MIPS_INS_ADDIU,
324 #ifndef CAPSTONE_DIET
325  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
326 #endif
327 },
328 {
329  Mips_ADDiu_MM, MIPS_INS_ADDIU,
330 #ifndef CAPSTONE_DIET
331  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
332 #endif
333 },
334 {
335  Mips_ADDu, MIPS_INS_ADDU,
336 #ifndef CAPSTONE_DIET
337  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
338 #endif
339 },
340 {
341  Mips_ADDu_MM, MIPS_INS_ADDU,
342 #ifndef CAPSTONE_DIET
343  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
344 #endif
345 },
346 {
347  Mips_ALIGN, MIPS_INS_ALIGN,
348 #ifndef CAPSTONE_DIET
349  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
350 #endif
351 },
352 {
353  Mips_ALUIPC, MIPS_INS_ALUIPC,
354 #ifndef CAPSTONE_DIET
355  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
356 #endif
357 },
358 {
359  Mips_AND, MIPS_INS_AND,
360 #ifndef CAPSTONE_DIET
361  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
362 #endif
363 },
364 {
365  Mips_AND16_MM, MIPS_INS_AND16,
366 #ifndef CAPSTONE_DIET
367  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
368 #endif
369 },
370 {
371  Mips_AND64, MIPS_INS_AND,
372 #ifndef CAPSTONE_DIET
373  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
374 #endif
375 },
376 {
377  Mips_ANDI16_MM, MIPS_INS_ANDI16,
378 #ifndef CAPSTONE_DIET
379  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
380 #endif
381 },
382 {
383  Mips_ANDI_B, MIPS_INS_ANDI,
384 #ifndef CAPSTONE_DIET
385  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
386 #endif
387 },
388 {
389  Mips_AND_MM, MIPS_INS_AND,
390 #ifndef CAPSTONE_DIET
391  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
392 #endif
393 },
394 {
395  Mips_AND_V, MIPS_INS_AND,
396 #ifndef CAPSTONE_DIET
397  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
398 #endif
399 },
400 {
401  Mips_ANDi, MIPS_INS_ANDI,
402 #ifndef CAPSTONE_DIET
403  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
404 #endif
405 },
406 {
407  Mips_ANDi64, MIPS_INS_ANDI,
408 #ifndef CAPSTONE_DIET
409  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
410 #endif
411 },
412 {
413  Mips_ANDi_MM, MIPS_INS_ANDI,
414 #ifndef CAPSTONE_DIET
415  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
416 #endif
417 },
418 {
419  Mips_APPEND, MIPS_INS_APPEND,
420 #ifndef CAPSTONE_DIET
421  { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
422 #endif
423 },
424 {
425  Mips_ASUB_S_B, MIPS_INS_ASUB_S,
426 #ifndef CAPSTONE_DIET
427  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
428 #endif
429 },
430 {
431  Mips_ASUB_S_D, MIPS_INS_ASUB_S,
432 #ifndef CAPSTONE_DIET
433  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
434 #endif
435 },
436 {
437  Mips_ASUB_S_H, MIPS_INS_ASUB_S,
438 #ifndef CAPSTONE_DIET
439  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
440 #endif
441 },
442 {
443  Mips_ASUB_S_W, MIPS_INS_ASUB_S,
444 #ifndef CAPSTONE_DIET
445  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
446 #endif
447 },
448 {
449  Mips_ASUB_U_B, MIPS_INS_ASUB_U,
450 #ifndef CAPSTONE_DIET
451  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
452 #endif
453 },
454 {
455  Mips_ASUB_U_D, MIPS_INS_ASUB_U,
456 #ifndef CAPSTONE_DIET
457  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
458 #endif
459 },
460 {
461  Mips_ASUB_U_H, MIPS_INS_ASUB_U,
462 #ifndef CAPSTONE_DIET
463  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
464 #endif
465 },
466 {
467  Mips_ASUB_U_W, MIPS_INS_ASUB_U,
468 #ifndef CAPSTONE_DIET
469  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
470 #endif
471 },
472 {
473  Mips_AUI, MIPS_INS_AUI,
474 #ifndef CAPSTONE_DIET
475  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
476 #endif
477 },
478 {
479  Mips_AUIPC, MIPS_INS_AUIPC,
480 #ifndef CAPSTONE_DIET
481  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
482 #endif
483 },
484 {
485  Mips_AVER_S_B, MIPS_INS_AVER_S,
486 #ifndef CAPSTONE_DIET
487  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
488 #endif
489 },
490 {
491  Mips_AVER_S_D, MIPS_INS_AVER_S,
492 #ifndef CAPSTONE_DIET
493  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
494 #endif
495 },
496 {
497  Mips_AVER_S_H, MIPS_INS_AVER_S,
498 #ifndef CAPSTONE_DIET
499  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
500 #endif
501 },
502 {
503  Mips_AVER_S_W, MIPS_INS_AVER_S,
504 #ifndef CAPSTONE_DIET
505  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
506 #endif
507 },
508 {
509  Mips_AVER_U_B, MIPS_INS_AVER_U,
510 #ifndef CAPSTONE_DIET
511  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
512 #endif
513 },
514 {
515  Mips_AVER_U_D, MIPS_INS_AVER_U,
516 #ifndef CAPSTONE_DIET
517  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
518 #endif
519 },
520 {
521  Mips_AVER_U_H, MIPS_INS_AVER_U,
522 #ifndef CAPSTONE_DIET
523  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
524 #endif
525 },
526 {
527  Mips_AVER_U_W, MIPS_INS_AVER_U,
528 #ifndef CAPSTONE_DIET
529  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
530 #endif
531 },
532 {
533  Mips_AVE_S_B, MIPS_INS_AVE_S,
534 #ifndef CAPSTONE_DIET
535  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
536 #endif
537 },
538 {
539  Mips_AVE_S_D, MIPS_INS_AVE_S,
540 #ifndef CAPSTONE_DIET
541  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
542 #endif
543 },
544 {
545  Mips_AVE_S_H, MIPS_INS_AVE_S,
546 #ifndef CAPSTONE_DIET
547  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
548 #endif
549 },
550 {
551  Mips_AVE_S_W, MIPS_INS_AVE_S,
552 #ifndef CAPSTONE_DIET
553  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
554 #endif
555 },
556 {
557  Mips_AVE_U_B, MIPS_INS_AVE_U,
558 #ifndef CAPSTONE_DIET
559  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
560 #endif
561 },
562 {
563  Mips_AVE_U_D, MIPS_INS_AVE_U,
564 #ifndef CAPSTONE_DIET
565  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
566 #endif
567 },
568 {
569  Mips_AVE_U_H, MIPS_INS_AVE_U,
570 #ifndef CAPSTONE_DIET
571  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
572 #endif
573 },
574 {
575  Mips_AVE_U_W, MIPS_INS_AVE_U,
576 #ifndef CAPSTONE_DIET
577  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
578 #endif
579 },
580 {
581  Mips_AddiuRxImmX16, MIPS_INS_ADDIU,
582 #ifndef CAPSTONE_DIET
583  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
584 #endif
585 },
586 {
587  Mips_AddiuRxPcImmX16, MIPS_INS_ADDIU,
588 #ifndef CAPSTONE_DIET
589  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
590 #endif
591 },
592 {
593  Mips_AddiuRxRxImm16, MIPS_INS_ADDIU,
594 #ifndef CAPSTONE_DIET
595  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
596 #endif
597 },
598 {
599  Mips_AddiuRxRxImmX16, MIPS_INS_ADDIU,
600 #ifndef CAPSTONE_DIET
601  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
602 #endif
603 },
604 {
605  Mips_AddiuRxRyOffMemX16, MIPS_INS_ADDIU,
606 #ifndef CAPSTONE_DIET
607  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
608 #endif
609 },
610 {
611  Mips_AddiuSpImm16, MIPS_INS_ADDIU,
612 #ifndef CAPSTONE_DIET
613  { MIPS_REG_SP, 0 }, { MIPS_REG_SP, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
614 #endif
615 },
616 {
617  Mips_AddiuSpImmX16, MIPS_INS_ADDIU,
618 #ifndef CAPSTONE_DIET
619  { MIPS_REG_SP, 0 }, { MIPS_REG_SP, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
620 #endif
621 },
622 {
623  Mips_AdduRxRyRz16, MIPS_INS_ADDU,
624 #ifndef CAPSTONE_DIET
625  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
626 #endif
627 },
628 {
629  Mips_AndRxRxRy16, MIPS_INS_AND,
630 #ifndef CAPSTONE_DIET
631  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
632 #endif
633 },
634 {
635  Mips_B16_MM, MIPS_INS_B16,
636 #ifndef CAPSTONE_DIET
637  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
638 #endif
639 },
640 {
641  Mips_BADDu, MIPS_INS_BADDU,
642 #ifndef CAPSTONE_DIET
643  { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
644 #endif
645 },
646 {
647  Mips_BAL, MIPS_INS_BAL,
648 #ifndef CAPSTONE_DIET
649  { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
650 #endif
651 },
652 {
653  Mips_BALC, MIPS_INS_BALC,
654 #ifndef CAPSTONE_DIET
655  { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
656 #endif
657 },
658 {
659  Mips_BALIGN, MIPS_INS_BALIGN,
660 #ifndef CAPSTONE_DIET
661  { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
662 #endif
663 },
664 {
665  Mips_BBIT0, MIPS_INS_BBIT0,
666 #ifndef CAPSTONE_DIET
667  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_CNMIPS, 0 }, 1, 0
668 #endif
669 },
670 {
671  Mips_BBIT032, MIPS_INS_BBIT032,
672 #ifndef CAPSTONE_DIET
673  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_CNMIPS, 0 }, 1, 0
674 #endif
675 },
676 {
677  Mips_BBIT1, MIPS_INS_BBIT1,
678 #ifndef CAPSTONE_DIET
679  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_CNMIPS, 0 }, 1, 0
680 #endif
681 },
682 {
683  Mips_BBIT132, MIPS_INS_BBIT132,
684 #ifndef CAPSTONE_DIET
685  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_CNMIPS, 0 }, 1, 0
686 #endif
687 },
688 {
689  Mips_BC, MIPS_INS_BC,
690 #ifndef CAPSTONE_DIET
691  { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
692 #endif
693 },
694 {
695  Mips_BC0F, MIPS_INS_BC0F,
696 #ifndef CAPSTONE_DIET
697  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
698 #endif
699 },
700 {
701  Mips_BC0FL, MIPS_INS_BC0FL,
702 #ifndef CAPSTONE_DIET
703  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
704 #endif
705 },
706 {
707  Mips_BC0T, MIPS_INS_BC0T,
708 #ifndef CAPSTONE_DIET
709  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
710 #endif
711 },
712 {
713  Mips_BC0TL, MIPS_INS_BC0TL,
714 #ifndef CAPSTONE_DIET
715  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
716 #endif
717 },
718 {
719  Mips_BC1EQZ, MIPS_INS_BC1EQZ,
720 #ifndef CAPSTONE_DIET
721  { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
722 #endif
723 },
724 {
725  Mips_BC1F, MIPS_INS_BC1F,
726 #ifndef CAPSTONE_DIET
727  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
728 #endif
729 },
730 {
731  Mips_BC1FL, MIPS_INS_BC1FL,
732 #ifndef CAPSTONE_DIET
733  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
734 #endif
735 },
736 {
737  Mips_BC1F_MM, MIPS_INS_BC1F,
738 #ifndef CAPSTONE_DIET
739  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
740 #endif
741 },
742 {
743  Mips_BC1NEZ, MIPS_INS_BC1NEZ,
744 #ifndef CAPSTONE_DIET
745  { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
746 #endif
747 },
748 {
749  Mips_BC1T, MIPS_INS_BC1T,
750 #ifndef CAPSTONE_DIET
751  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
752 #endif
753 },
754 {
755  Mips_BC1TL, MIPS_INS_BC1TL,
756 #ifndef CAPSTONE_DIET
757  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
758 #endif
759 },
760 {
761  Mips_BC1T_MM, MIPS_INS_BC1T,
762 #ifndef CAPSTONE_DIET
763  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
764 #endif
765 },
766 {
767  Mips_BC2EQZ, MIPS_INS_BC2EQZ,
768 #ifndef CAPSTONE_DIET
769  { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
770 #endif
771 },
772 {
773  Mips_BC2F, MIPS_INS_BC2F,
774 #ifndef CAPSTONE_DIET
775  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
776 #endif
777 },
778 {
779  Mips_BC2FL, MIPS_INS_BC2FL,
780 #ifndef CAPSTONE_DIET
781  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
782 #endif
783 },
784 {
785  Mips_BC2NEZ, MIPS_INS_BC2NEZ,
786 #ifndef CAPSTONE_DIET
787  { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
788 #endif
789 },
790 {
791  Mips_BC2T, MIPS_INS_BC2T,
792 #ifndef CAPSTONE_DIET
793  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
794 #endif
795 },
796 {
797  Mips_BC2TL, MIPS_INS_BC2TL,
798 #ifndef CAPSTONE_DIET
799  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
800 #endif
801 },
802 {
803  Mips_BC3F, MIPS_INS_BC3F,
804 #ifndef CAPSTONE_DIET
805  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
806 #endif
807 },
808 {
809  Mips_BC3FL, MIPS_INS_BC3FL,
810 #ifndef CAPSTONE_DIET
811  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
812 #endif
813 },
814 {
815  Mips_BC3T, MIPS_INS_BC3T,
816 #ifndef CAPSTONE_DIET
817  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
818 #endif
819 },
820 {
821  Mips_BC3TL, MIPS_INS_BC3TL,
822 #ifndef CAPSTONE_DIET
823  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
824 #endif
825 },
826 {
827  Mips_BCLRI_B, MIPS_INS_BCLRI,
828 #ifndef CAPSTONE_DIET
829  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
830 #endif
831 },
832 {
833  Mips_BCLRI_D, MIPS_INS_BCLRI,
834 #ifndef CAPSTONE_DIET
835  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
836 #endif
837 },
838 {
839  Mips_BCLRI_H, MIPS_INS_BCLRI,
840 #ifndef CAPSTONE_DIET
841  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
842 #endif
843 },
844 {
845  Mips_BCLRI_W, MIPS_INS_BCLRI,
846 #ifndef CAPSTONE_DIET
847  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
848 #endif
849 },
850 {
851  Mips_BCLR_B, MIPS_INS_BCLR,
852 #ifndef CAPSTONE_DIET
853  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
854 #endif
855 },
856 {
857  Mips_BCLR_D, MIPS_INS_BCLR,
858 #ifndef CAPSTONE_DIET
859  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
860 #endif
861 },
862 {
863  Mips_BCLR_H, MIPS_INS_BCLR,
864 #ifndef CAPSTONE_DIET
865  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
866 #endif
867 },
868 {
869  Mips_BCLR_W, MIPS_INS_BCLR,
870 #ifndef CAPSTONE_DIET
871  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
872 #endif
873 },
874 {
875  Mips_BEQ, MIPS_INS_BEQ,
876 #ifndef CAPSTONE_DIET
877  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
878 #endif
879 },
880 {
881  Mips_BEQ64, MIPS_INS_BEQ,
882 #ifndef CAPSTONE_DIET
883  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
884 #endif
885 },
886 {
887  Mips_BEQC, MIPS_INS_BEQC,
888 #ifndef CAPSTONE_DIET
889  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
890 #endif
891 },
892 {
893  Mips_BEQL, MIPS_INS_BEQL,
894 #ifndef CAPSTONE_DIET
895  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
896 #endif
897 },
898 {
899  Mips_BEQZ16_MM, MIPS_INS_BEQZ16,
900 #ifndef CAPSTONE_DIET
901  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
902 #endif
903 },
904 {
905  Mips_BEQZALC, MIPS_INS_BEQZALC,
906 #ifndef CAPSTONE_DIET
907  { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
908 #endif
909 },
910 {
911  Mips_BEQZC, MIPS_INS_BEQZC,
912 #ifndef CAPSTONE_DIET
913  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
914 #endif
915 },
916 {
917  Mips_BEQZC_MM, MIPS_INS_BEQZC,
918 #ifndef CAPSTONE_DIET
919  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
920 #endif
921 },
922 {
923  Mips_BEQ_MM, MIPS_INS_BEQ,
924 #ifndef CAPSTONE_DIET
925  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
926 #endif
927 },
928 {
929  Mips_BGEC, MIPS_INS_BGEC,
930 #ifndef CAPSTONE_DIET
931  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
932 #endif
933 },
934 {
935  Mips_BGEUC, MIPS_INS_BGEUC,
936 #ifndef CAPSTONE_DIET
937  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
938 #endif
939 },
940 {
941  Mips_BGEZ, MIPS_INS_BGEZ,
942 #ifndef CAPSTONE_DIET
943  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
944 #endif
945 },
946 {
947  Mips_BGEZ64, MIPS_INS_BGEZ,
948 #ifndef CAPSTONE_DIET
949  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
950 #endif
951 },
952 {
953  Mips_BGEZAL, MIPS_INS_BGEZAL,
954 #ifndef CAPSTONE_DIET
955  { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
956 #endif
957 },
958 {
959  Mips_BGEZALC, MIPS_INS_BGEZALC,
960 #ifndef CAPSTONE_DIET
961  { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
962 #endif
963 },
964 {
965  Mips_BGEZALL, MIPS_INS_BGEZALL,
966 #ifndef CAPSTONE_DIET
967  { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
968 #endif
969 },
970 {
971  Mips_BGEZALS_MM, MIPS_INS_BGEZALS,
972 #ifndef CAPSTONE_DIET
973  { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 0, 0
974 #endif
975 },
976 {
977  Mips_BGEZAL_MM, MIPS_INS_BGEZAL,
978 #ifndef CAPSTONE_DIET
979  { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 0, 0
980 #endif
981 },
982 {
983  Mips_BGEZC, MIPS_INS_BGEZC,
984 #ifndef CAPSTONE_DIET
985  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
986 #endif
987 },
988 {
989  Mips_BGEZL, MIPS_INS_BGEZL,
990 #ifndef CAPSTONE_DIET
991  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
992 #endif
993 },
994 {
995  Mips_BGEZ_MM, MIPS_INS_BGEZ,
996 #ifndef CAPSTONE_DIET
997  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
998 #endif
999 },
1000 {
1001  Mips_BGTZ, MIPS_INS_BGTZ,
1002 #ifndef CAPSTONE_DIET
1003  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
1004 #endif
1005 },
1006 {
1007  Mips_BGTZ64, MIPS_INS_BGTZ,
1008 #ifndef CAPSTONE_DIET
1009  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
1010 #endif
1011 },
1012 {
1013  Mips_BGTZALC, MIPS_INS_BGTZALC,
1014 #ifndef CAPSTONE_DIET
1015  { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
1016 #endif
1017 },
1018 {
1019  Mips_BGTZC, MIPS_INS_BGTZC,
1020 #ifndef CAPSTONE_DIET
1021  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
1022 #endif
1023 },
1024 {
1025  Mips_BGTZL, MIPS_INS_BGTZL,
1026 #ifndef CAPSTONE_DIET
1027  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
1028 #endif
1029 },
1030 {
1031  Mips_BGTZ_MM, MIPS_INS_BGTZ,
1032 #ifndef CAPSTONE_DIET
1033  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
1034 #endif
1035 },
1036 {
1037  Mips_BINSLI_B, MIPS_INS_BINSLI,
1038 #ifndef CAPSTONE_DIET
1039  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1040 #endif
1041 },
1042 {
1043  Mips_BINSLI_D, MIPS_INS_BINSLI,
1044 #ifndef CAPSTONE_DIET
1045  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1046 #endif
1047 },
1048 {
1049  Mips_BINSLI_H, MIPS_INS_BINSLI,
1050 #ifndef CAPSTONE_DIET
1051  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1052 #endif
1053 },
1054 {
1055  Mips_BINSLI_W, MIPS_INS_BINSLI,
1056 #ifndef CAPSTONE_DIET
1057  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1058 #endif
1059 },
1060 {
1061  Mips_BINSL_B, MIPS_INS_BINSL,
1062 #ifndef CAPSTONE_DIET
1063  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1064 #endif
1065 },
1066 {
1067  Mips_BINSL_D, MIPS_INS_BINSL,
1068 #ifndef CAPSTONE_DIET
1069  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1070 #endif
1071 },
1072 {
1073  Mips_BINSL_H, MIPS_INS_BINSL,
1074 #ifndef CAPSTONE_DIET
1075  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1076 #endif
1077 },
1078 {
1079  Mips_BINSL_W, MIPS_INS_BINSL,
1080 #ifndef CAPSTONE_DIET
1081  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1082 #endif
1083 },
1084 {
1085  Mips_BINSRI_B, MIPS_INS_BINSRI,
1086 #ifndef CAPSTONE_DIET
1087  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1088 #endif
1089 },
1090 {
1091  Mips_BINSRI_D, MIPS_INS_BINSRI,
1092 #ifndef CAPSTONE_DIET
1093  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1094 #endif
1095 },
1096 {
1097  Mips_BINSRI_H, MIPS_INS_BINSRI,
1098 #ifndef CAPSTONE_DIET
1099  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1100 #endif
1101 },
1102 {
1103  Mips_BINSRI_W, MIPS_INS_BINSRI,
1104 #ifndef CAPSTONE_DIET
1105  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1106 #endif
1107 },
1108 {
1109  Mips_BINSR_B, MIPS_INS_BINSR,
1110 #ifndef CAPSTONE_DIET
1111  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1112 #endif
1113 },
1114 {
1115  Mips_BINSR_D, MIPS_INS_BINSR,
1116 #ifndef CAPSTONE_DIET
1117  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1118 #endif
1119 },
1120 {
1121  Mips_BINSR_H, MIPS_INS_BINSR,
1122 #ifndef CAPSTONE_DIET
1123  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1124 #endif
1125 },
1126 {
1127  Mips_BINSR_W, MIPS_INS_BINSR,
1128 #ifndef CAPSTONE_DIET
1129  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1130 #endif
1131 },
1132 {
1133  Mips_BITREV, MIPS_INS_BITREV,
1134 #ifndef CAPSTONE_DIET
1135  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
1136 #endif
1137 },
1138 {
1139  Mips_BITSWAP, MIPS_INS_BITSWAP,
1140 #ifndef CAPSTONE_DIET
1141  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
1142 #endif
1143 },
1144 {
1145  Mips_BLEZ, MIPS_INS_BLEZ,
1146 #ifndef CAPSTONE_DIET
1147  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
1148 #endif
1149 },
1150 {
1151  Mips_BLEZ64, MIPS_INS_BLEZ,
1152 #ifndef CAPSTONE_DIET
1153  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
1154 #endif
1155 },
1156 {
1157  Mips_BLEZALC, MIPS_INS_BLEZALC,
1158 #ifndef CAPSTONE_DIET
1159  { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
1160 #endif
1161 },
1162 {
1163  Mips_BLEZC, MIPS_INS_BLEZC,
1164 #ifndef CAPSTONE_DIET
1165  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
1166 #endif
1167 },
1168 {
1169  Mips_BLEZL, MIPS_INS_BLEZL,
1170 #ifndef CAPSTONE_DIET
1171  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
1172 #endif
1173 },
1174 {
1175  Mips_BLEZ_MM, MIPS_INS_BLEZ,
1176 #ifndef CAPSTONE_DIET
1177  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
1178 #endif
1179 },
1180 {
1181  Mips_BLTC, MIPS_INS_BLTC,
1182 #ifndef CAPSTONE_DIET
1183  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
1184 #endif
1185 },
1186 {
1187  Mips_BLTUC, MIPS_INS_BLTUC,
1188 #ifndef CAPSTONE_DIET
1189  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
1190 #endif
1191 },
1192 {
1193  Mips_BLTZ, MIPS_INS_BLTZ,
1194 #ifndef CAPSTONE_DIET
1195  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
1196 #endif
1197 },
1198 {
1199  Mips_BLTZ64, MIPS_INS_BLTZ,
1200 #ifndef CAPSTONE_DIET
1201  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
1202 #endif
1203 },
1204 {
1205  Mips_BLTZAL, MIPS_INS_BLTZAL,
1206 #ifndef CAPSTONE_DIET
1207  { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
1208 #endif
1209 },
1210 {
1211  Mips_BLTZALC, MIPS_INS_BLTZALC,
1212 #ifndef CAPSTONE_DIET
1213  { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
1214 #endif
1215 },
1216 {
1217  Mips_BLTZALL, MIPS_INS_BLTZALL,
1218 #ifndef CAPSTONE_DIET
1219  { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
1220 #endif
1221 },
1222 {
1223  Mips_BLTZALS_MM, MIPS_INS_BLTZALS,
1224 #ifndef CAPSTONE_DIET
1225  { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 0, 0
1226 #endif
1227 },
1228 {
1229  Mips_BLTZAL_MM, MIPS_INS_BLTZAL,
1230 #ifndef CAPSTONE_DIET
1231  { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 0, 0
1232 #endif
1233 },
1234 {
1235  Mips_BLTZC, MIPS_INS_BLTZC,
1236 #ifndef CAPSTONE_DIET
1237  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
1238 #endif
1239 },
1240 {
1241  Mips_BLTZL, MIPS_INS_BLTZL,
1242 #ifndef CAPSTONE_DIET
1243  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
1244 #endif
1245 },
1246 {
1247  Mips_BLTZ_MM, MIPS_INS_BLTZ,
1248 #ifndef CAPSTONE_DIET
1249  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
1250 #endif
1251 },
1252 {
1253  Mips_BMNZI_B, MIPS_INS_BMNZI,
1254 #ifndef CAPSTONE_DIET
1255  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1256 #endif
1257 },
1258 {
1259  Mips_BMNZ_V, MIPS_INS_BMNZ,
1260 #ifndef CAPSTONE_DIET
1261  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1262 #endif
1263 },
1264 {
1265  Mips_BMZI_B, MIPS_INS_BMZI,
1266 #ifndef CAPSTONE_DIET
1267  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1268 #endif
1269 },
1270 {
1271  Mips_BMZ_V, MIPS_INS_BMZ,
1272 #ifndef CAPSTONE_DIET
1273  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1274 #endif
1275 },
1276 {
1277  Mips_BNE, MIPS_INS_BNE,
1278 #ifndef CAPSTONE_DIET
1279  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
1280 #endif
1281 },
1282 {
1283  Mips_BNE64, MIPS_INS_BNE,
1284 #ifndef CAPSTONE_DIET
1285  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
1286 #endif
1287 },
1288 {
1289  Mips_BNEC, MIPS_INS_BNEC,
1290 #ifndef CAPSTONE_DIET
1291  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
1292 #endif
1293 },
1294 {
1295  Mips_BNEGI_B, MIPS_INS_BNEGI,
1296 #ifndef CAPSTONE_DIET
1297  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1298 #endif
1299 },
1300 {
1301  Mips_BNEGI_D, MIPS_INS_BNEGI,
1302 #ifndef CAPSTONE_DIET
1303  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1304 #endif
1305 },
1306 {
1307  Mips_BNEGI_H, MIPS_INS_BNEGI,
1308 #ifndef CAPSTONE_DIET
1309  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1310 #endif
1311 },
1312 {
1313  Mips_BNEGI_W, MIPS_INS_BNEGI,
1314 #ifndef CAPSTONE_DIET
1315  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1316 #endif
1317 },
1318 {
1319  Mips_BNEG_B, MIPS_INS_BNEG,
1320 #ifndef CAPSTONE_DIET
1321  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1322 #endif
1323 },
1324 {
1325  Mips_BNEG_D, MIPS_INS_BNEG,
1326 #ifndef CAPSTONE_DIET
1327  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1328 #endif
1329 },
1330 {
1331  Mips_BNEG_H, MIPS_INS_BNEG,
1332 #ifndef CAPSTONE_DIET
1333  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1334 #endif
1335 },
1336 {
1337  Mips_BNEG_W, MIPS_INS_BNEG,
1338 #ifndef CAPSTONE_DIET
1339  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1340 #endif
1341 },
1342 {
1343  Mips_BNEL, MIPS_INS_BNEL,
1344 #ifndef CAPSTONE_DIET
1345  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
1346 #endif
1347 },
1348 {
1349  Mips_BNEZ16_MM, MIPS_INS_BNEZ16,
1350 #ifndef CAPSTONE_DIET
1351  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
1352 #endif
1353 },
1354 {
1355  Mips_BNEZALC, MIPS_INS_BNEZALC,
1356 #ifndef CAPSTONE_DIET
1357  { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
1358 #endif
1359 },
1360 {
1361  Mips_BNEZC, MIPS_INS_BNEZC,
1362 #ifndef CAPSTONE_DIET
1363  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
1364 #endif
1365 },
1366 {
1367  Mips_BNEZC_MM, MIPS_INS_BNEZC,
1368 #ifndef CAPSTONE_DIET
1369  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
1370 #endif
1371 },
1372 {
1373  Mips_BNE_MM, MIPS_INS_BNE,
1374 #ifndef CAPSTONE_DIET
1375  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
1376 #endif
1377 },
1378 {
1379  Mips_BNVC, MIPS_INS_BNVC,
1380 #ifndef CAPSTONE_DIET
1381  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
1382 #endif
1383 },
1384 {
1385  Mips_BNZ_B, MIPS_INS_BNZ,
1386 #ifndef CAPSTONE_DIET
1387  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0
1388 #endif
1389 },
1390 {
1391  Mips_BNZ_D, MIPS_INS_BNZ,
1392 #ifndef CAPSTONE_DIET
1393  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0
1394 #endif
1395 },
1396 {
1397  Mips_BNZ_H, MIPS_INS_BNZ,
1398 #ifndef CAPSTONE_DIET
1399  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0
1400 #endif
1401 },
1402 {
1403  Mips_BNZ_V, MIPS_INS_BNZ,
1404 #ifndef CAPSTONE_DIET
1405  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0
1406 #endif
1407 },
1408 {
1409  Mips_BNZ_W, MIPS_INS_BNZ,
1410 #ifndef CAPSTONE_DIET
1411  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0
1412 #endif
1413 },
1414 {
1415  Mips_BOVC, MIPS_INS_BOVC,
1416 #ifndef CAPSTONE_DIET
1417  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
1418 #endif
1419 },
1420 {
1421  Mips_BPOSGE32, MIPS_INS_BPOSGE32,
1422 #ifndef CAPSTONE_DIET
1423  { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_DSP, 0 }, 1, 0
1424 #endif
1425 },
1426 {
1427  Mips_BREAK, MIPS_INS_BREAK,
1428 #ifndef CAPSTONE_DIET
1429  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
1430 #endif
1431 },
1432 {
1433  Mips_BREAK16_MM, MIPS_INS_BREAK16,
1434 #ifndef CAPSTONE_DIET
1435  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
1436 #endif
1437 },
1438 {
1439  Mips_BREAK_MM, MIPS_INS_BREAK,
1440 #ifndef CAPSTONE_DIET
1441  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
1442 #endif
1443 },
1444 {
1445  Mips_BSELI_B, MIPS_INS_BSELI,
1446 #ifndef CAPSTONE_DIET
1447  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1448 #endif
1449 },
1450 {
1451  Mips_BSEL_V, MIPS_INS_BSEL,
1452 #ifndef CAPSTONE_DIET
1453  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1454 #endif
1455 },
1456 {
1457  Mips_BSETI_B, MIPS_INS_BSETI,
1458 #ifndef CAPSTONE_DIET
1459  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1460 #endif
1461 },
1462 {
1463  Mips_BSETI_D, MIPS_INS_BSETI,
1464 #ifndef CAPSTONE_DIET
1465  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1466 #endif
1467 },
1468 {
1469  Mips_BSETI_H, MIPS_INS_BSETI,
1470 #ifndef CAPSTONE_DIET
1471  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1472 #endif
1473 },
1474 {
1475  Mips_BSETI_W, MIPS_INS_BSETI,
1476 #ifndef CAPSTONE_DIET
1477  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1478 #endif
1479 },
1480 {
1481  Mips_BSET_B, MIPS_INS_BSET,
1482 #ifndef CAPSTONE_DIET
1483  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1484 #endif
1485 },
1486 {
1487  Mips_BSET_D, MIPS_INS_BSET,
1488 #ifndef CAPSTONE_DIET
1489  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1490 #endif
1491 },
1492 {
1493  Mips_BSET_H, MIPS_INS_BSET,
1494 #ifndef CAPSTONE_DIET
1495  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1496 #endif
1497 },
1498 {
1499  Mips_BSET_W, MIPS_INS_BSET,
1500 #ifndef CAPSTONE_DIET
1501  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1502 #endif
1503 },
1504 {
1505  Mips_BZ_B, MIPS_INS_BZ,
1506 #ifndef CAPSTONE_DIET
1507  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0
1508 #endif
1509 },
1510 {
1511  Mips_BZ_D, MIPS_INS_BZ,
1512 #ifndef CAPSTONE_DIET
1513  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0
1514 #endif
1515 },
1516 {
1517  Mips_BZ_H, MIPS_INS_BZ,
1518 #ifndef CAPSTONE_DIET
1519  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0
1520 #endif
1521 },
1522 {
1523  Mips_BZ_V, MIPS_INS_BZ,
1524 #ifndef CAPSTONE_DIET
1525  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0
1526 #endif
1527 },
1528 {
1529  Mips_BZ_W, MIPS_INS_BZ,
1530 #ifndef CAPSTONE_DIET
1531  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0
1532 #endif
1533 },
1534 {
1535  Mips_BeqzRxImm16, MIPS_INS_BEQZ,
1536 #ifndef CAPSTONE_DIET
1537  { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0
1538 #endif
1539 },
1540 {
1541  Mips_BeqzRxImmX16, MIPS_INS_BEQZ,
1542 #ifndef CAPSTONE_DIET
1543  { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0
1544 #endif
1545 },
1546 {
1547  Mips_Bimm16, MIPS_INS_B,
1548 #ifndef CAPSTONE_DIET
1549  { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0
1550 #endif
1551 },
1552 {
1553  Mips_BimmX16, MIPS_INS_B,
1554 #ifndef CAPSTONE_DIET
1555  { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0
1556 #endif
1557 },
1558 {
1559  Mips_BnezRxImm16, MIPS_INS_BNEZ,
1560 #ifndef CAPSTONE_DIET
1561  { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0
1562 #endif
1563 },
1564 {
1565  Mips_BnezRxImmX16, MIPS_INS_BNEZ,
1566 #ifndef CAPSTONE_DIET
1567  { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0
1568 #endif
1569 },
1570 {
1571  Mips_Break16, MIPS_INS_BREAK,
1572 #ifndef CAPSTONE_DIET
1573  { 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 0, 0
1574 #endif
1575 },
1576 {
1577  Mips_Bteqz16, MIPS_INS_BTEQZ,
1578 #ifndef CAPSTONE_DIET
1579  { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0
1580 #endif
1581 },
1582 {
1583  Mips_BteqzX16, MIPS_INS_BTEQZ,
1584 #ifndef CAPSTONE_DIET
1585  { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0
1586 #endif
1587 },
1588 {
1589  Mips_Btnez16, MIPS_INS_BTNEZ,
1590 #ifndef CAPSTONE_DIET
1591  { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0
1592 #endif
1593 },
1594 {
1595  Mips_BtnezX16, MIPS_INS_BTNEZ,
1596 #ifndef CAPSTONE_DIET
1597  { MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0
1598 #endif
1599 },
1600 {
1601  Mips_CACHE, MIPS_INS_CACHE,
1602 #ifndef CAPSTONE_DIET
1603  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
1604 #endif
1605 },
1606 {
1607  Mips_CACHE_MM, MIPS_INS_CACHE,
1608 #ifndef CAPSTONE_DIET
1609  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
1610 #endif
1611 },
1612 {
1613  Mips_CACHE_R6, MIPS_INS_CACHE,
1614 #ifndef CAPSTONE_DIET
1615  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
1616 #endif
1617 },
1618 {
1619  Mips_CEIL_L_D64, MIPS_INS_CEIL,
1620 #ifndef CAPSTONE_DIET
1621  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
1622 #endif
1623 },
1624 {
1625  Mips_CEIL_L_S, MIPS_INS_CEIL,
1626 #ifndef CAPSTONE_DIET
1627  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
1628 #endif
1629 },
1630 {
1631  Mips_CEIL_W_D32, MIPS_INS_CEIL,
1632 #ifndef CAPSTONE_DIET
1633  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
1634 #endif
1635 },
1636 {
1637  Mips_CEIL_W_D64, MIPS_INS_CEIL,
1638 #ifndef CAPSTONE_DIET
1639  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0
1640 #endif
1641 },
1642 {
1643  Mips_CEIL_W_MM, MIPS_INS_CEIL,
1644 #ifndef CAPSTONE_DIET
1645  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
1646 #endif
1647 },
1648 {
1649  Mips_CEIL_W_S, MIPS_INS_CEIL,
1650 #ifndef CAPSTONE_DIET
1651  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
1652 #endif
1653 },
1654 {
1655  Mips_CEIL_W_S_MM, MIPS_INS_CEIL,
1656 #ifndef CAPSTONE_DIET
1657  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
1658 #endif
1659 },
1660 {
1661  Mips_CEQI_B, MIPS_INS_CEQI,
1662 #ifndef CAPSTONE_DIET
1663  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1664 #endif
1665 },
1666 {
1667  Mips_CEQI_D, MIPS_INS_CEQI,
1668 #ifndef CAPSTONE_DIET
1669  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1670 #endif
1671 },
1672 {
1673  Mips_CEQI_H, MIPS_INS_CEQI,
1674 #ifndef CAPSTONE_DIET
1675  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1676 #endif
1677 },
1678 {
1679  Mips_CEQI_W, MIPS_INS_CEQI,
1680 #ifndef CAPSTONE_DIET
1681  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1682 #endif
1683 },
1684 {
1685  Mips_CEQ_B, MIPS_INS_CEQ,
1686 #ifndef CAPSTONE_DIET
1687  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1688 #endif
1689 },
1690 {
1691  Mips_CEQ_D, MIPS_INS_CEQ,
1692 #ifndef CAPSTONE_DIET
1693  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1694 #endif
1695 },
1696 {
1697  Mips_CEQ_H, MIPS_INS_CEQ,
1698 #ifndef CAPSTONE_DIET
1699  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1700 #endif
1701 },
1702 {
1703  Mips_CEQ_W, MIPS_INS_CEQ,
1704 #ifndef CAPSTONE_DIET
1705  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1706 #endif
1707 },
1708 {
1709  Mips_CFC1, MIPS_INS_CFC1,
1710 #ifndef CAPSTONE_DIET
1711  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
1712 #endif
1713 },
1714 {
1715  Mips_CFC1_MM, MIPS_INS_CFC1,
1716 #ifndef CAPSTONE_DIET
1717  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
1718 #endif
1719 },
1720 {
1721  Mips_CFCMSA, MIPS_INS_CFCMSA,
1722 #ifndef CAPSTONE_DIET
1723  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1724 #endif
1725 },
1726 {
1727  Mips_CINS, MIPS_INS_CINS,
1728 #ifndef CAPSTONE_DIET
1729  { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
1730 #endif
1731 },
1732 {
1733  Mips_CINS32, MIPS_INS_CINS32,
1734 #ifndef CAPSTONE_DIET
1735  { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
1736 #endif
1737 },
1738 {
1739  Mips_CLASS_D, MIPS_INS_CLASS,
1740 #ifndef CAPSTONE_DIET
1741  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
1742 #endif
1743 },
1744 {
1745  Mips_CLASS_S, MIPS_INS_CLASS,
1746 #ifndef CAPSTONE_DIET
1747  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
1748 #endif
1749 },
1750 {
1751  Mips_CLEI_S_B, MIPS_INS_CLEI_S,
1752 #ifndef CAPSTONE_DIET
1753  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1754 #endif
1755 },
1756 {
1757  Mips_CLEI_S_D, MIPS_INS_CLEI_S,
1758 #ifndef CAPSTONE_DIET
1759  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1760 #endif
1761 },
1762 {
1763  Mips_CLEI_S_H, MIPS_INS_CLEI_S,
1764 #ifndef CAPSTONE_DIET
1765  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1766 #endif
1767 },
1768 {
1769  Mips_CLEI_S_W, MIPS_INS_CLEI_S,
1770 #ifndef CAPSTONE_DIET
1771  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1772 #endif
1773 },
1774 {
1775  Mips_CLEI_U_B, MIPS_INS_CLEI_U,
1776 #ifndef CAPSTONE_DIET
1777  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1778 #endif
1779 },
1780 {
1781  Mips_CLEI_U_D, MIPS_INS_CLEI_U,
1782 #ifndef CAPSTONE_DIET
1783  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1784 #endif
1785 },
1786 {
1787  Mips_CLEI_U_H, MIPS_INS_CLEI_U,
1788 #ifndef CAPSTONE_DIET
1789  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1790 #endif
1791 },
1792 {
1793  Mips_CLEI_U_W, MIPS_INS_CLEI_U,
1794 #ifndef CAPSTONE_DIET
1795  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1796 #endif
1797 },
1798 {
1799  Mips_CLE_S_B, MIPS_INS_CLE_S,
1800 #ifndef CAPSTONE_DIET
1801  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1802 #endif
1803 },
1804 {
1805  Mips_CLE_S_D, MIPS_INS_CLE_S,
1806 #ifndef CAPSTONE_DIET
1807  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1808 #endif
1809 },
1810 {
1811  Mips_CLE_S_H, MIPS_INS_CLE_S,
1812 #ifndef CAPSTONE_DIET
1813  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1814 #endif
1815 },
1816 {
1817  Mips_CLE_S_W, MIPS_INS_CLE_S,
1818 #ifndef CAPSTONE_DIET
1819  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1820 #endif
1821 },
1822 {
1823  Mips_CLE_U_B, MIPS_INS_CLE_U,
1824 #ifndef CAPSTONE_DIET
1825  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1826 #endif
1827 },
1828 {
1829  Mips_CLE_U_D, MIPS_INS_CLE_U,
1830 #ifndef CAPSTONE_DIET
1831  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1832 #endif
1833 },
1834 {
1835  Mips_CLE_U_H, MIPS_INS_CLE_U,
1836 #ifndef CAPSTONE_DIET
1837  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1838 #endif
1839 },
1840 {
1841  Mips_CLE_U_W, MIPS_INS_CLE_U,
1842 #ifndef CAPSTONE_DIET
1843  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1844 #endif
1845 },
1846 {
1847  Mips_CLO, MIPS_INS_CLO,
1848 #ifndef CAPSTONE_DIET
1849  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
1850 #endif
1851 },
1852 {
1853  Mips_CLO_MM, MIPS_INS_CLO,
1854 #ifndef CAPSTONE_DIET
1855  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
1856 #endif
1857 },
1858 {
1859  Mips_CLO_R6, MIPS_INS_CLO,
1860 #ifndef CAPSTONE_DIET
1861  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
1862 #endif
1863 },
1864 {
1865  Mips_CLTI_S_B, MIPS_INS_CLTI_S,
1866 #ifndef CAPSTONE_DIET
1867  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1868 #endif
1869 },
1870 {
1871  Mips_CLTI_S_D, MIPS_INS_CLTI_S,
1872 #ifndef CAPSTONE_DIET
1873  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1874 #endif
1875 },
1876 {
1877  Mips_CLTI_S_H, MIPS_INS_CLTI_S,
1878 #ifndef CAPSTONE_DIET
1879  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1880 #endif
1881 },
1882 {
1883  Mips_CLTI_S_W, MIPS_INS_CLTI_S,
1884 #ifndef CAPSTONE_DIET
1885  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1886 #endif
1887 },
1888 {
1889  Mips_CLTI_U_B, MIPS_INS_CLTI_U,
1890 #ifndef CAPSTONE_DIET
1891  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1892 #endif
1893 },
1894 {
1895  Mips_CLTI_U_D, MIPS_INS_CLTI_U,
1896 #ifndef CAPSTONE_DIET
1897  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1898 #endif
1899 },
1900 {
1901  Mips_CLTI_U_H, MIPS_INS_CLTI_U,
1902 #ifndef CAPSTONE_DIET
1903  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1904 #endif
1905 },
1906 {
1907  Mips_CLTI_U_W, MIPS_INS_CLTI_U,
1908 #ifndef CAPSTONE_DIET
1909  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1910 #endif
1911 },
1912 {
1913  Mips_CLT_S_B, MIPS_INS_CLT_S,
1914 #ifndef CAPSTONE_DIET
1915  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1916 #endif
1917 },
1918 {
1919  Mips_CLT_S_D, MIPS_INS_CLT_S,
1920 #ifndef CAPSTONE_DIET
1921  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1922 #endif
1923 },
1924 {
1925  Mips_CLT_S_H, MIPS_INS_CLT_S,
1926 #ifndef CAPSTONE_DIET
1927  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1928 #endif
1929 },
1930 {
1931  Mips_CLT_S_W, MIPS_INS_CLT_S,
1932 #ifndef CAPSTONE_DIET
1933  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1934 #endif
1935 },
1936 {
1937  Mips_CLT_U_B, MIPS_INS_CLT_U,
1938 #ifndef CAPSTONE_DIET
1939  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1940 #endif
1941 },
1942 {
1943  Mips_CLT_U_D, MIPS_INS_CLT_U,
1944 #ifndef CAPSTONE_DIET
1945  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1946 #endif
1947 },
1948 {
1949  Mips_CLT_U_H, MIPS_INS_CLT_U,
1950 #ifndef CAPSTONE_DIET
1951  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1952 #endif
1953 },
1954 {
1955  Mips_CLT_U_W, MIPS_INS_CLT_U,
1956 #ifndef CAPSTONE_DIET
1957  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
1958 #endif
1959 },
1960 {
1961  Mips_CLZ, MIPS_INS_CLZ,
1962 #ifndef CAPSTONE_DIET
1963  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
1964 #endif
1965 },
1966 {
1967  Mips_CLZ_MM, MIPS_INS_CLZ,
1968 #ifndef CAPSTONE_DIET
1969  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
1970 #endif
1971 },
1972 {
1973  Mips_CLZ_R6, MIPS_INS_CLZ,
1974 #ifndef CAPSTONE_DIET
1975  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
1976 #endif
1977 },
1978 {
1979  Mips_CMPGDU_EQ_QB, MIPS_INS_CMPGDU,
1980 #ifndef CAPSTONE_DIET
1981  { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
1982 #endif
1983 },
1984 {
1985  Mips_CMPGDU_LE_QB, MIPS_INS_CMPGDU,
1986 #ifndef CAPSTONE_DIET
1987  { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
1988 #endif
1989 },
1990 {
1991  Mips_CMPGDU_LT_QB, MIPS_INS_CMPGDU,
1992 #ifndef CAPSTONE_DIET
1993  { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
1994 #endif
1995 },
1996 {
1997  Mips_CMPGU_EQ_QB, MIPS_INS_CMPGU,
1998 #ifndef CAPSTONE_DIET
1999  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
2000 #endif
2001 },
2002 {
2003  Mips_CMPGU_LE_QB, MIPS_INS_CMPGU,
2004 #ifndef CAPSTONE_DIET
2005  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
2006 #endif
2007 },
2008 {
2009  Mips_CMPGU_LT_QB, MIPS_INS_CMPGU,
2010 #ifndef CAPSTONE_DIET
2011  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
2012 #endif
2013 },
2014 {
2015  Mips_CMPU_EQ_QB, MIPS_INS_CMPU,
2016 #ifndef CAPSTONE_DIET
2017  { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
2018 #endif
2019 },
2020 {
2021  Mips_CMPU_LE_QB, MIPS_INS_CMPU,
2022 #ifndef CAPSTONE_DIET
2023  { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
2024 #endif
2025 },
2026 {
2027  Mips_CMPU_LT_QB, MIPS_INS_CMPU,
2028 #ifndef CAPSTONE_DIET
2029  { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
2030 #endif
2031 },
2032 {
2033  Mips_CMP_EQ_D, MIPS_INS_CMP,
2034 #ifndef CAPSTONE_DIET
2035  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2036 #endif
2037 },
2038 {
2039  Mips_CMP_EQ_PH, MIPS_INS_CMP,
2040 #ifndef CAPSTONE_DIET
2041  { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
2042 #endif
2043 },
2044 {
2045  Mips_CMP_EQ_S, MIPS_INS_CMP,
2046 #ifndef CAPSTONE_DIET
2047  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2048 #endif
2049 },
2050 {
2051  Mips_CMP_F_D, MIPS_INS_CMP,
2052 #ifndef CAPSTONE_DIET
2053  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2054 #endif
2055 },
2056 {
2057  Mips_CMP_F_S, MIPS_INS_CMP,
2058 #ifndef CAPSTONE_DIET
2059  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2060 #endif
2061 },
2062 {
2063  Mips_CMP_LE_D, MIPS_INS_CMP,
2064 #ifndef CAPSTONE_DIET
2065  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2066 #endif
2067 },
2068 {
2069  Mips_CMP_LE_PH, MIPS_INS_CMP,
2070 #ifndef CAPSTONE_DIET
2071  { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
2072 #endif
2073 },
2074 {
2075  Mips_CMP_LE_S, MIPS_INS_CMP,
2076 #ifndef CAPSTONE_DIET
2077  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2078 #endif
2079 },
2080 {
2081  Mips_CMP_LT_D, MIPS_INS_CMP,
2082 #ifndef CAPSTONE_DIET
2083  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2084 #endif
2085 },
2086 {
2087  Mips_CMP_LT_PH, MIPS_INS_CMP,
2088 #ifndef CAPSTONE_DIET
2089  { 0 }, { MIPS_REG_DSPCCOND, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
2090 #endif
2091 },
2092 {
2093  Mips_CMP_LT_S, MIPS_INS_CMP,
2094 #ifndef CAPSTONE_DIET
2095  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2096 #endif
2097 },
2098 {
2099  Mips_CMP_SAF_D, MIPS_INS_CMP,
2100 #ifndef CAPSTONE_DIET
2101  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2102 #endif
2103 },
2104 {
2105  Mips_CMP_SAF_S, MIPS_INS_CMP,
2106 #ifndef CAPSTONE_DIET
2107  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2108 #endif
2109 },
2110 {
2111  Mips_CMP_SEQ_D, MIPS_INS_CMP,
2112 #ifndef CAPSTONE_DIET
2113  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2114 #endif
2115 },
2116 {
2117  Mips_CMP_SEQ_S, MIPS_INS_CMP,
2118 #ifndef CAPSTONE_DIET
2119  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2120 #endif
2121 },
2122 {
2123  Mips_CMP_SLE_D, MIPS_INS_CMP,
2124 #ifndef CAPSTONE_DIET
2125  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2126 #endif
2127 },
2128 {
2129  Mips_CMP_SLE_S, MIPS_INS_CMP,
2130 #ifndef CAPSTONE_DIET
2131  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2132 #endif
2133 },
2134 {
2135  Mips_CMP_SLT_D, MIPS_INS_CMP,
2136 #ifndef CAPSTONE_DIET
2137  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2138 #endif
2139 },
2140 {
2141  Mips_CMP_SLT_S, MIPS_INS_CMP,
2142 #ifndef CAPSTONE_DIET
2143  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2144 #endif
2145 },
2146 {
2147  Mips_CMP_SUEQ_D, MIPS_INS_CMP,
2148 #ifndef CAPSTONE_DIET
2149  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2150 #endif
2151 },
2152 {
2153  Mips_CMP_SUEQ_S, MIPS_INS_CMP,
2154 #ifndef CAPSTONE_DIET
2155  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2156 #endif
2157 },
2158 {
2159  Mips_CMP_SULE_D, MIPS_INS_CMP,
2160 #ifndef CAPSTONE_DIET
2161  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2162 #endif
2163 },
2164 {
2165  Mips_CMP_SULE_S, MIPS_INS_CMP,
2166 #ifndef CAPSTONE_DIET
2167  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2168 #endif
2169 },
2170 {
2171  Mips_CMP_SULT_D, MIPS_INS_CMP,
2172 #ifndef CAPSTONE_DIET
2173  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2174 #endif
2175 },
2176 {
2177  Mips_CMP_SULT_S, MIPS_INS_CMP,
2178 #ifndef CAPSTONE_DIET
2179  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2180 #endif
2181 },
2182 {
2183  Mips_CMP_SUN_D, MIPS_INS_CMP,
2184 #ifndef CAPSTONE_DIET
2185  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2186 #endif
2187 },
2188 {
2189  Mips_CMP_SUN_S, MIPS_INS_CMP,
2190 #ifndef CAPSTONE_DIET
2191  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2192 #endif
2193 },
2194 {
2195  Mips_CMP_UEQ_D, MIPS_INS_CMP,
2196 #ifndef CAPSTONE_DIET
2197  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2198 #endif
2199 },
2200 {
2201  Mips_CMP_UEQ_S, MIPS_INS_CMP,
2202 #ifndef CAPSTONE_DIET
2203  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2204 #endif
2205 },
2206 {
2207  Mips_CMP_ULE_D, MIPS_INS_CMP,
2208 #ifndef CAPSTONE_DIET
2209  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2210 #endif
2211 },
2212 {
2213  Mips_CMP_ULE_S, MIPS_INS_CMP,
2214 #ifndef CAPSTONE_DIET
2215  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2216 #endif
2217 },
2218 {
2219  Mips_CMP_ULT_D, MIPS_INS_CMP,
2220 #ifndef CAPSTONE_DIET
2221  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2222 #endif
2223 },
2224 {
2225  Mips_CMP_ULT_S, MIPS_INS_CMP,
2226 #ifndef CAPSTONE_DIET
2227  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2228 #endif
2229 },
2230 {
2231  Mips_CMP_UN_D, MIPS_INS_CMP,
2232 #ifndef CAPSTONE_DIET
2233  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2234 #endif
2235 },
2236 {
2237  Mips_CMP_UN_S, MIPS_INS_CMP,
2238 #ifndef CAPSTONE_DIET
2239  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2240 #endif
2241 },
2242 {
2243  Mips_COPY_S_B, MIPS_INS_COPY_S,
2244 #ifndef CAPSTONE_DIET
2245  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2246 #endif
2247 },
2248 {
2249  Mips_COPY_S_D, MIPS_INS_COPY_S,
2250 #ifndef CAPSTONE_DIET
2251  { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0
2252 #endif
2253 },
2254 {
2255  Mips_COPY_S_H, MIPS_INS_COPY_S,
2256 #ifndef CAPSTONE_DIET
2257  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2258 #endif
2259 },
2260 {
2261  Mips_COPY_S_W, MIPS_INS_COPY_S,
2262 #ifndef CAPSTONE_DIET
2263  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2264 #endif
2265 },
2266 {
2267  Mips_COPY_U_B, MIPS_INS_COPY_U,
2268 #ifndef CAPSTONE_DIET
2269  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2270 #endif
2271 },
2272 {
2273  Mips_COPY_U_D, MIPS_INS_COPY_U,
2274 #ifndef CAPSTONE_DIET
2275  { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0
2276 #endif
2277 },
2278 {
2279  Mips_COPY_U_H, MIPS_INS_COPY_U,
2280 #ifndef CAPSTONE_DIET
2281  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2282 #endif
2283 },
2284 {
2285  Mips_COPY_U_W, MIPS_INS_COPY_U,
2286 #ifndef CAPSTONE_DIET
2287  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2288 #endif
2289 },
2290 {
2291  Mips_CTC1, MIPS_INS_CTC1,
2292 #ifndef CAPSTONE_DIET
2293  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
2294 #endif
2295 },
2296 {
2297  Mips_CTC1_MM, MIPS_INS_CTC1,
2298 #ifndef CAPSTONE_DIET
2299  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
2300 #endif
2301 },
2302 {
2303  Mips_CTCMSA, MIPS_INS_CTCMSA,
2304 #ifndef CAPSTONE_DIET
2305  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2306 #endif
2307 },
2308 {
2309  Mips_CVT_D32_S, MIPS_INS_CVT,
2310 #ifndef CAPSTONE_DIET
2311  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2312 #endif
2313 },
2314 {
2315  Mips_CVT_D32_W, MIPS_INS_CVT,
2316 #ifndef CAPSTONE_DIET
2317  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2318 #endif
2319 },
2320 {
2321  Mips_CVT_D32_W_MM, MIPS_INS_CVT,
2322 #ifndef CAPSTONE_DIET
2323  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
2324 #endif
2325 },
2326 {
2327  Mips_CVT_D64_L, MIPS_INS_CVT,
2328 #ifndef CAPSTONE_DIET
2329  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
2330 #endif
2331 },
2332 {
2333  Mips_CVT_D64_S, MIPS_INS_CVT,
2334 #ifndef CAPSTONE_DIET
2335  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
2336 #endif
2337 },
2338 {
2339  Mips_CVT_D64_W, MIPS_INS_CVT,
2340 #ifndef CAPSTONE_DIET
2341  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
2342 #endif
2343 },
2344 {
2345  Mips_CVT_D_S_MM, MIPS_INS_CVT,
2346 #ifndef CAPSTONE_DIET
2347  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
2348 #endif
2349 },
2350 {
2351  Mips_CVT_L_D64, MIPS_INS_CVT,
2352 #ifndef CAPSTONE_DIET
2353  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32R2, 0 }, 0, 0
2354 #endif
2355 },
2356 {
2357  Mips_CVT_L_D64_MM, MIPS_INS_CVT,
2358 #ifndef CAPSTONE_DIET
2359  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
2360 #endif
2361 },
2362 {
2363  Mips_CVT_L_S, MIPS_INS_CVT,
2364 #ifndef CAPSTONE_DIET
2365  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32R2, 0 }, 0, 0
2366 #endif
2367 },
2368 {
2369  Mips_CVT_L_S_MM, MIPS_INS_CVT,
2370 #ifndef CAPSTONE_DIET
2371  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
2372 #endif
2373 },
2374 {
2375  Mips_CVT_S_D32, MIPS_INS_CVT,
2376 #ifndef CAPSTONE_DIET
2377  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2378 #endif
2379 },
2380 {
2381  Mips_CVT_S_D32_MM, MIPS_INS_CVT,
2382 #ifndef CAPSTONE_DIET
2383  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
2384 #endif
2385 },
2386 {
2387  Mips_CVT_S_D64, MIPS_INS_CVT,
2388 #ifndef CAPSTONE_DIET
2389  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
2390 #endif
2391 },
2392 {
2393  Mips_CVT_S_L, MIPS_INS_CVT,
2394 #ifndef CAPSTONE_DIET
2395  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
2396 #endif
2397 },
2398 {
2399  Mips_CVT_S_W, MIPS_INS_CVT,
2400 #ifndef CAPSTONE_DIET
2401  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
2402 #endif
2403 },
2404 {
2405  Mips_CVT_S_W_MM, MIPS_INS_CVT,
2406 #ifndef CAPSTONE_DIET
2407  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
2408 #endif
2409 },
2410 {
2411  Mips_CVT_W_D32, MIPS_INS_CVT,
2412 #ifndef CAPSTONE_DIET
2413  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2414 #endif
2415 },
2416 {
2417  Mips_CVT_W_D64, MIPS_INS_CVT,
2418 #ifndef CAPSTONE_DIET
2419  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
2420 #endif
2421 },
2422 {
2423  Mips_CVT_W_MM, MIPS_INS_CVT,
2424 #ifndef CAPSTONE_DIET
2425  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
2426 #endif
2427 },
2428 {
2429  Mips_CVT_W_S, MIPS_INS_CVT,
2430 #ifndef CAPSTONE_DIET
2431  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
2432 #endif
2433 },
2434 {
2435  Mips_CVT_W_S_MM, MIPS_INS_CVT,
2436 #ifndef CAPSTONE_DIET
2437  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
2438 #endif
2439 },
2440 {
2441  Mips_C_EQ_D32, MIPS_INS_C,
2442 #ifndef CAPSTONE_DIET
2443  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2444 #endif
2445 },
2446 {
2447  Mips_C_EQ_D64, MIPS_INS_C,
2448 #ifndef CAPSTONE_DIET
2449  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
2450 #endif
2451 },
2452 {
2453  Mips_C_EQ_S, MIPS_INS_C,
2454 #ifndef CAPSTONE_DIET
2455  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2456 #endif
2457 },
2458 {
2459  Mips_C_F_D32, MIPS_INS_C,
2460 #ifndef CAPSTONE_DIET
2461  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2462 #endif
2463 },
2464 {
2465  Mips_C_F_D64, MIPS_INS_C,
2466 #ifndef CAPSTONE_DIET
2467  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
2468 #endif
2469 },
2470 {
2471  Mips_C_F_S, MIPS_INS_C,
2472 #ifndef CAPSTONE_DIET
2473  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2474 #endif
2475 },
2476 {
2477  Mips_C_LE_D32, MIPS_INS_C,
2478 #ifndef CAPSTONE_DIET
2479  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2480 #endif
2481 },
2482 {
2483  Mips_C_LE_D64, MIPS_INS_C,
2484 #ifndef CAPSTONE_DIET
2485  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
2486 #endif
2487 },
2488 {
2489  Mips_C_LE_S, MIPS_INS_C,
2490 #ifndef CAPSTONE_DIET
2491  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2492 #endif
2493 },
2494 {
2495  Mips_C_LT_D32, MIPS_INS_C,
2496 #ifndef CAPSTONE_DIET
2497  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2498 #endif
2499 },
2500 {
2501  Mips_C_LT_D64, MIPS_INS_C,
2502 #ifndef CAPSTONE_DIET
2503  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
2504 #endif
2505 },
2506 {
2507  Mips_C_LT_S, MIPS_INS_C,
2508 #ifndef CAPSTONE_DIET
2509  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2510 #endif
2511 },
2512 {
2513  Mips_C_NGE_D32, MIPS_INS_C,
2514 #ifndef CAPSTONE_DIET
2515  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2516 #endif
2517 },
2518 {
2519  Mips_C_NGE_D64, MIPS_INS_C,
2520 #ifndef CAPSTONE_DIET
2521  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
2522 #endif
2523 },
2524 {
2525  Mips_C_NGE_S, MIPS_INS_C,
2526 #ifndef CAPSTONE_DIET
2527  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2528 #endif
2529 },
2530 {
2531  Mips_C_NGLE_D32, MIPS_INS_C,
2532 #ifndef CAPSTONE_DIET
2533  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2534 #endif
2535 },
2536 {
2537  Mips_C_NGLE_D64, MIPS_INS_C,
2538 #ifndef CAPSTONE_DIET
2539  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
2540 #endif
2541 },
2542 {
2543  Mips_C_NGLE_S, MIPS_INS_C,
2544 #ifndef CAPSTONE_DIET
2545  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2546 #endif
2547 },
2548 {
2549  Mips_C_NGL_D32, MIPS_INS_C,
2550 #ifndef CAPSTONE_DIET
2551  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2552 #endif
2553 },
2554 {
2555  Mips_C_NGL_D64, MIPS_INS_C,
2556 #ifndef CAPSTONE_DIET
2557  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
2558 #endif
2559 },
2560 {
2561  Mips_C_NGL_S, MIPS_INS_C,
2562 #ifndef CAPSTONE_DIET
2563  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2564 #endif
2565 },
2566 {
2567  Mips_C_NGT_D32, MIPS_INS_C,
2568 #ifndef CAPSTONE_DIET
2569  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2570 #endif
2571 },
2572 {
2573  Mips_C_NGT_D64, MIPS_INS_C,
2574 #ifndef CAPSTONE_DIET
2575  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
2576 #endif
2577 },
2578 {
2579  Mips_C_NGT_S, MIPS_INS_C,
2580 #ifndef CAPSTONE_DIET
2581  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2582 #endif
2583 },
2584 {
2585  Mips_C_OLE_D32, MIPS_INS_C,
2586 #ifndef CAPSTONE_DIET
2587  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2588 #endif
2589 },
2590 {
2591  Mips_C_OLE_D64, MIPS_INS_C,
2592 #ifndef CAPSTONE_DIET
2593  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
2594 #endif
2595 },
2596 {
2597  Mips_C_OLE_S, MIPS_INS_C,
2598 #ifndef CAPSTONE_DIET
2599  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2600 #endif
2601 },
2602 {
2603  Mips_C_OLT_D32, MIPS_INS_C,
2604 #ifndef CAPSTONE_DIET
2605  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2606 #endif
2607 },
2608 {
2609  Mips_C_OLT_D64, MIPS_INS_C,
2610 #ifndef CAPSTONE_DIET
2611  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
2612 #endif
2613 },
2614 {
2615  Mips_C_OLT_S, MIPS_INS_C,
2616 #ifndef CAPSTONE_DIET
2617  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2618 #endif
2619 },
2620 {
2621  Mips_C_SEQ_D32, MIPS_INS_C,
2622 #ifndef CAPSTONE_DIET
2623  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2624 #endif
2625 },
2626 {
2627  Mips_C_SEQ_D64, MIPS_INS_C,
2628 #ifndef CAPSTONE_DIET
2629  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
2630 #endif
2631 },
2632 {
2633  Mips_C_SEQ_S, MIPS_INS_C,
2634 #ifndef CAPSTONE_DIET
2635  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2636 #endif
2637 },
2638 {
2639  Mips_C_SF_D32, MIPS_INS_C,
2640 #ifndef CAPSTONE_DIET
2641  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2642 #endif
2643 },
2644 {
2645  Mips_C_SF_D64, MIPS_INS_C,
2646 #ifndef CAPSTONE_DIET
2647  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
2648 #endif
2649 },
2650 {
2651  Mips_C_SF_S, MIPS_INS_C,
2652 #ifndef CAPSTONE_DIET
2653  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2654 #endif
2655 },
2656 {
2657  Mips_C_UEQ_D32, MIPS_INS_C,
2658 #ifndef CAPSTONE_DIET
2659  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2660 #endif
2661 },
2662 {
2663  Mips_C_UEQ_D64, MIPS_INS_C,
2664 #ifndef CAPSTONE_DIET
2665  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
2666 #endif
2667 },
2668 {
2669  Mips_C_UEQ_S, MIPS_INS_C,
2670 #ifndef CAPSTONE_DIET
2671  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2672 #endif
2673 },
2674 {
2675  Mips_C_ULE_D32, MIPS_INS_C,
2676 #ifndef CAPSTONE_DIET
2677  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2678 #endif
2679 },
2680 {
2681  Mips_C_ULE_D64, MIPS_INS_C,
2682 #ifndef CAPSTONE_DIET
2683  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
2684 #endif
2685 },
2686 {
2687  Mips_C_ULE_S, MIPS_INS_C,
2688 #ifndef CAPSTONE_DIET
2689  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2690 #endif
2691 },
2692 {
2693  Mips_C_ULT_D32, MIPS_INS_C,
2694 #ifndef CAPSTONE_DIET
2695  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2696 #endif
2697 },
2698 {
2699  Mips_C_ULT_D64, MIPS_INS_C,
2700 #ifndef CAPSTONE_DIET
2701  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
2702 #endif
2703 },
2704 {
2705  Mips_C_ULT_S, MIPS_INS_C,
2706 #ifndef CAPSTONE_DIET
2707  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2708 #endif
2709 },
2710 {
2711  Mips_C_UN_D32, MIPS_INS_C,
2712 #ifndef CAPSTONE_DIET
2713  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
2714 #endif
2715 },
2716 {
2717  Mips_C_UN_D64, MIPS_INS_C,
2718 #ifndef CAPSTONE_DIET
2719  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
2720 #endif
2721 },
2722 {
2723  Mips_C_UN_S, MIPS_INS_C,
2724 #ifndef CAPSTONE_DIET
2725  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2726 #endif
2727 },
2728 {
2729  Mips_CmpRxRy16, MIPS_INS_CMP,
2730 #ifndef CAPSTONE_DIET
2731  { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
2732 #endif
2733 },
2734 {
2735  Mips_CmpiRxImm16, MIPS_INS_CMPI,
2736 #ifndef CAPSTONE_DIET
2737  { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
2738 #endif
2739 },
2740 {
2741  Mips_CmpiRxImmX16, MIPS_INS_CMPI,
2742 #ifndef CAPSTONE_DIET
2743  { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
2744 #endif
2745 },
2746 {
2747  Mips_DADD, MIPS_INS_DADD,
2748 #ifndef CAPSTONE_DIET
2749  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
2750 #endif
2751 },
2752 {
2753  Mips_DADDi, MIPS_INS_DADDI,
2754 #ifndef CAPSTONE_DIET
2755  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2756 #endif
2757 },
2758 {
2759  Mips_DADDiu, MIPS_INS_DADDIU,
2760 #ifndef CAPSTONE_DIET
2761  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
2762 #endif
2763 },
2764 {
2765  Mips_DADDu, MIPS_INS_DADDU,
2766 #ifndef CAPSTONE_DIET
2767  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
2768 #endif
2769 },
2770 {
2771  Mips_DAHI, MIPS_INS_DAHI,
2772 #ifndef CAPSTONE_DIET
2773  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
2774 #endif
2775 },
2776 {
2777  Mips_DALIGN, MIPS_INS_DALIGN,
2778 #ifndef CAPSTONE_DIET
2779  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
2780 #endif
2781 },
2782 {
2783  Mips_DATI, MIPS_INS_DATI,
2784 #ifndef CAPSTONE_DIET
2785  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
2786 #endif
2787 },
2788 {
2789  Mips_DAUI, MIPS_INS_DAUI,
2790 #ifndef CAPSTONE_DIET
2791  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
2792 #endif
2793 },
2794 {
2795  Mips_DBITSWAP, MIPS_INS_DBITSWAP,
2796 #ifndef CAPSTONE_DIET
2797  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
2798 #endif
2799 },
2800 {
2801  Mips_DCLO, MIPS_INS_DCLO,
2802 #ifndef CAPSTONE_DIET
2803  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2804 #endif
2805 },
2806 {
2807  Mips_DCLO_R6, MIPS_INS_DCLO,
2808 #ifndef CAPSTONE_DIET
2809  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
2810 #endif
2811 },
2812 {
2813  Mips_DCLZ, MIPS_INS_DCLZ,
2814 #ifndef CAPSTONE_DIET
2815  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
2816 #endif
2817 },
2818 {
2819  Mips_DCLZ_R6, MIPS_INS_DCLZ,
2820 #ifndef CAPSTONE_DIET
2821  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
2822 #endif
2823 },
2824 {
2825  Mips_DDIV, MIPS_INS_DDIV,
2826 #ifndef CAPSTONE_DIET
2827  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
2828 #endif
2829 },
2830 {
2831  Mips_DDIVU, MIPS_INS_DDIVU,
2832 #ifndef CAPSTONE_DIET
2833  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
2834 #endif
2835 },
2836 {
2837  Mips_DERET, MIPS_INS_DERET,
2838 #ifndef CAPSTONE_DIET
2839  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0
2840 #endif
2841 },
2842 {
2843  Mips_DERET_MM, MIPS_INS_DERET,
2844 #ifndef CAPSTONE_DIET
2845  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
2846 #endif
2847 },
2848 {
2849  Mips_DEXT, MIPS_INS_DEXT,
2850 #ifndef CAPSTONE_DIET
2851  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
2852 #endif
2853 },
2854 {
2855  Mips_DEXTM, MIPS_INS_DEXTM,
2856 #ifndef CAPSTONE_DIET
2857  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
2858 #endif
2859 },
2860 {
2861  Mips_DEXTU, MIPS_INS_DEXTU,
2862 #ifndef CAPSTONE_DIET
2863  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
2864 #endif
2865 },
2866 {
2867  Mips_DI, MIPS_INS_DI,
2868 #ifndef CAPSTONE_DIET
2869  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
2870 #endif
2871 },
2872 {
2873  Mips_DINS, MIPS_INS_DINS,
2874 #ifndef CAPSTONE_DIET
2875  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
2876 #endif
2877 },
2878 {
2879  Mips_DINSM, MIPS_INS_DINSM,
2880 #ifndef CAPSTONE_DIET
2881  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
2882 #endif
2883 },
2884 {
2885  Mips_DINSU, MIPS_INS_DINSU,
2886 #ifndef CAPSTONE_DIET
2887  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
2888 #endif
2889 },
2890 {
2891  Mips_DIV, MIPS_INS_DIV,
2892 #ifndef CAPSTONE_DIET
2893  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2894 #endif
2895 },
2896 {
2897  Mips_DIVU, MIPS_INS_DIVU,
2898 #ifndef CAPSTONE_DIET
2899  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
2900 #endif
2901 },
2902 {
2903  Mips_DIV_S_B, MIPS_INS_DIV_S,
2904 #ifndef CAPSTONE_DIET
2905  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2906 #endif
2907 },
2908 {
2909  Mips_DIV_S_D, MIPS_INS_DIV_S,
2910 #ifndef CAPSTONE_DIET
2911  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2912 #endif
2913 },
2914 {
2915  Mips_DIV_S_H, MIPS_INS_DIV_S,
2916 #ifndef CAPSTONE_DIET
2917  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2918 #endif
2919 },
2920 {
2921  Mips_DIV_S_W, MIPS_INS_DIV_S,
2922 #ifndef CAPSTONE_DIET
2923  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2924 #endif
2925 },
2926 {
2927  Mips_DIV_U_B, MIPS_INS_DIV_U,
2928 #ifndef CAPSTONE_DIET
2929  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2930 #endif
2931 },
2932 {
2933  Mips_DIV_U_D, MIPS_INS_DIV_U,
2934 #ifndef CAPSTONE_DIET
2935  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2936 #endif
2937 },
2938 {
2939  Mips_DIV_U_H, MIPS_INS_DIV_U,
2940 #ifndef CAPSTONE_DIET
2941  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2942 #endif
2943 },
2944 {
2945  Mips_DIV_U_W, MIPS_INS_DIV_U,
2946 #ifndef CAPSTONE_DIET
2947  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
2948 #endif
2949 },
2950 {
2951  Mips_DI_MM, MIPS_INS_DI,
2952 #ifndef CAPSTONE_DIET
2953  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
2954 #endif
2955 },
2956 {
2957  Mips_DLSA, MIPS_INS_DLSA,
2958 #ifndef CAPSTONE_DIET
2959  { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0
2960 #endif
2961 },
2962 {
2963  Mips_DLSA_R6, MIPS_INS_DLSA,
2964 #ifndef CAPSTONE_DIET
2965  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
2966 #endif
2967 },
2968 {
2969  Mips_DMFC0, MIPS_INS_DMFC0,
2970 #ifndef CAPSTONE_DIET
2971  { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0
2972 #endif
2973 },
2974 {
2975  Mips_DMFC1, MIPS_INS_DMFC1,
2976 #ifndef CAPSTONE_DIET
2977  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
2978 #endif
2979 },
2980 {
2981  Mips_DMFC2, MIPS_INS_DMFC2,
2982 #ifndef CAPSTONE_DIET
2983  { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0
2984 #endif
2985 },
2986 {
2987  Mips_DMOD, MIPS_INS_DMOD,
2988 #ifndef CAPSTONE_DIET
2989  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
2990 #endif
2991 },
2992 {
2993  Mips_DMODU, MIPS_INS_DMODU,
2994 #ifndef CAPSTONE_DIET
2995  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
2996 #endif
2997 },
2998 {
2999  Mips_DMTC0, MIPS_INS_DMTC0,
3000 #ifndef CAPSTONE_DIET
3001  { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0
3002 #endif
3003 },
3004 {
3005  Mips_DMTC1, MIPS_INS_DMTC1,
3006 #ifndef CAPSTONE_DIET
3007  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
3008 #endif
3009 },
3010 {
3011  Mips_DMTC2, MIPS_INS_DMTC2,
3012 #ifndef CAPSTONE_DIET
3013  { 0 }, { 0 }, { MIPS_GRP_MIPS64, 0 }, 0, 0
3014 #endif
3015 },
3016 {
3017  Mips_DMUH, MIPS_INS_DMUH,
3018 #ifndef CAPSTONE_DIET
3019  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
3020 #endif
3021 },
3022 {
3023  Mips_DMUHU, MIPS_INS_DMUHU,
3024 #ifndef CAPSTONE_DIET
3025  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
3026 #endif
3027 },
3028 {
3029  Mips_DMUL, MIPS_INS_DMUL,
3030 #ifndef CAPSTONE_DIET
3031  { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
3032 #endif
3033 },
3034 {
3035  Mips_DMULT, MIPS_INS_DMULT,
3036 #ifndef CAPSTONE_DIET
3037  { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
3038 #endif
3039 },
3040 {
3041  Mips_DMULTu, MIPS_INS_DMULTU,
3042 #ifndef CAPSTONE_DIET
3043  { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
3044 #endif
3045 },
3046 {
3047  Mips_DMULU, MIPS_INS_DMULU,
3048 #ifndef CAPSTONE_DIET
3049  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
3050 #endif
3051 },
3052 {
3053  Mips_DMUL_R6, MIPS_INS_DMUL,
3054 #ifndef CAPSTONE_DIET
3055  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
3056 #endif
3057 },
3058 {
3059  Mips_DOTP_S_D, MIPS_INS_DOTP_S,
3060 #ifndef CAPSTONE_DIET
3061  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3062 #endif
3063 },
3064 {
3065  Mips_DOTP_S_H, MIPS_INS_DOTP_S,
3066 #ifndef CAPSTONE_DIET
3067  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3068 #endif
3069 },
3070 {
3071  Mips_DOTP_S_W, MIPS_INS_DOTP_S,
3072 #ifndef CAPSTONE_DIET
3073  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3074 #endif
3075 },
3076 {
3077  Mips_DOTP_U_D, MIPS_INS_DOTP_U,
3078 #ifndef CAPSTONE_DIET
3079  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3080 #endif
3081 },
3082 {
3083  Mips_DOTP_U_H, MIPS_INS_DOTP_U,
3084 #ifndef CAPSTONE_DIET
3085  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3086 #endif
3087 },
3088 {
3089  Mips_DOTP_U_W, MIPS_INS_DOTP_U,
3090 #ifndef CAPSTONE_DIET
3091  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3092 #endif
3093 },
3094 {
3095  Mips_DPADD_S_D, MIPS_INS_DPADD_S,
3096 #ifndef CAPSTONE_DIET
3097  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3098 #endif
3099 },
3100 {
3101  Mips_DPADD_S_H, MIPS_INS_DPADD_S,
3102 #ifndef CAPSTONE_DIET
3103  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3104 #endif
3105 },
3106 {
3107  Mips_DPADD_S_W, MIPS_INS_DPADD_S,
3108 #ifndef CAPSTONE_DIET
3109  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3110 #endif
3111 },
3112 {
3113  Mips_DPADD_U_D, MIPS_INS_DPADD_U,
3114 #ifndef CAPSTONE_DIET
3115  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3116 #endif
3117 },
3118 {
3119  Mips_DPADD_U_H, MIPS_INS_DPADD_U,
3120 #ifndef CAPSTONE_DIET
3121  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3122 #endif
3123 },
3124 {
3125  Mips_DPADD_U_W, MIPS_INS_DPADD_U,
3126 #ifndef CAPSTONE_DIET
3127  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3128 #endif
3129 },
3130 {
3131  Mips_DPAQX_SA_W_PH, MIPS_INS_DPAQX_SA,
3132 #ifndef CAPSTONE_DIET
3133  { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
3134 #endif
3135 },
3136 {
3137  Mips_DPAQX_S_W_PH, MIPS_INS_DPAQX_S,
3138 #ifndef CAPSTONE_DIET
3139  { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
3140 #endif
3141 },
3142 {
3143  Mips_DPAQ_SA_L_W, MIPS_INS_DPAQ_SA,
3144 #ifndef CAPSTONE_DIET
3145  { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3146 #endif
3147 },
3148 {
3149  Mips_DPAQ_S_W_PH, MIPS_INS_DPAQ_S,
3150 #ifndef CAPSTONE_DIET
3151  { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3152 #endif
3153 },
3154 {
3155  Mips_DPAU_H_QBL, MIPS_INS_DPAU,
3156 #ifndef CAPSTONE_DIET
3157  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3158 #endif
3159 },
3160 {
3161  Mips_DPAU_H_QBR, MIPS_INS_DPAU,
3162 #ifndef CAPSTONE_DIET
3163  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3164 #endif
3165 },
3166 {
3167  Mips_DPAX_W_PH, MIPS_INS_DPAX,
3168 #ifndef CAPSTONE_DIET
3169  { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
3170 #endif
3171 },
3172 {
3173  Mips_DPA_W_PH, MIPS_INS_DPA,
3174 #ifndef CAPSTONE_DIET
3175  { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
3176 #endif
3177 },
3178 {
3179  Mips_DPOP, MIPS_INS_DPOP,
3180 #ifndef CAPSTONE_DIET
3181  { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
3182 #endif
3183 },
3184 {
3185  Mips_DPSQX_SA_W_PH, MIPS_INS_DPSQX_SA,
3186 #ifndef CAPSTONE_DIET
3187  { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
3188 #endif
3189 },
3190 {
3191  Mips_DPSQX_S_W_PH, MIPS_INS_DPSQX_S,
3192 #ifndef CAPSTONE_DIET
3193  { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
3194 #endif
3195 },
3196 {
3197  Mips_DPSQ_SA_L_W, MIPS_INS_DPSQ_SA,
3198 #ifndef CAPSTONE_DIET
3199  { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3200 #endif
3201 },
3202 {
3203  Mips_DPSQ_S_W_PH, MIPS_INS_DPSQ_S,
3204 #ifndef CAPSTONE_DIET
3205  { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3206 #endif
3207 },
3208 {
3209  Mips_DPSUB_S_D, MIPS_INS_DPSUB_S,
3210 #ifndef CAPSTONE_DIET
3211  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3212 #endif
3213 },
3214 {
3215  Mips_DPSUB_S_H, MIPS_INS_DPSUB_S,
3216 #ifndef CAPSTONE_DIET
3217  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3218 #endif
3219 },
3220 {
3221  Mips_DPSUB_S_W, MIPS_INS_DPSUB_S,
3222 #ifndef CAPSTONE_DIET
3223  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3224 #endif
3225 },
3226 {
3227  Mips_DPSUB_U_D, MIPS_INS_DPSUB_U,
3228 #ifndef CAPSTONE_DIET
3229  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3230 #endif
3231 },
3232 {
3233  Mips_DPSUB_U_H, MIPS_INS_DPSUB_U,
3234 #ifndef CAPSTONE_DIET
3235  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3236 #endif
3237 },
3238 {
3239  Mips_DPSUB_U_W, MIPS_INS_DPSUB_U,
3240 #ifndef CAPSTONE_DIET
3241  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3242 #endif
3243 },
3244 {
3245  Mips_DPSU_H_QBL, MIPS_INS_DPSU,
3246 #ifndef CAPSTONE_DIET
3247  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3248 #endif
3249 },
3250 {
3251  Mips_DPSU_H_QBR, MIPS_INS_DPSU,
3252 #ifndef CAPSTONE_DIET
3253  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3254 #endif
3255 },
3256 {
3257  Mips_DPSX_W_PH, MIPS_INS_DPSX,
3258 #ifndef CAPSTONE_DIET
3259  { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
3260 #endif
3261 },
3262 {
3263  Mips_DPS_W_PH, MIPS_INS_DPS,
3264 #ifndef CAPSTONE_DIET
3265  { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
3266 #endif
3267 },
3268 {
3269  Mips_DROTR, MIPS_INS_DROTR,
3270 #ifndef CAPSTONE_DIET
3271  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0
3272 #endif
3273 },
3274 {
3275  Mips_DROTR32, MIPS_INS_DROTR32,
3276 #ifndef CAPSTONE_DIET
3277  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0
3278 #endif
3279 },
3280 {
3281  Mips_DROTRV, MIPS_INS_DROTRV,
3282 #ifndef CAPSTONE_DIET
3283  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0
3284 #endif
3285 },
3286 {
3287  Mips_DSBH, MIPS_INS_DSBH,
3288 #ifndef CAPSTONE_DIET
3289  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0
3290 #endif
3291 },
3292 {
3293  Mips_DSDIV, MIPS_INS_DDIV,
3294 #ifndef CAPSTONE_DIET
3295  { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
3296 #endif
3297 },
3298 {
3299  Mips_DSHD, MIPS_INS_DSHD,
3300 #ifndef CAPSTONE_DIET
3301  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R2, 0 }, 0, 0
3302 #endif
3303 },
3304 {
3305  Mips_DSLL, MIPS_INS_DSLL,
3306 #ifndef CAPSTONE_DIET
3307  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
3308 #endif
3309 },
3310 {
3311  Mips_DSLL32, MIPS_INS_DSLL32,
3312 #ifndef CAPSTONE_DIET
3313  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
3314 #endif
3315 },
3316 {
3317  Mips_DSLL64_32, MIPS_INS_DSLL,
3318 #ifndef CAPSTONE_DIET
3319  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
3320 #endif
3321 },
3322 {
3323  Mips_DSLLV, MIPS_INS_DSLLV,
3324 #ifndef CAPSTONE_DIET
3325  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
3326 #endif
3327 },
3328 {
3329  Mips_DSRA, MIPS_INS_DSRA,
3330 #ifndef CAPSTONE_DIET
3331  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
3332 #endif
3333 },
3334 {
3335  Mips_DSRA32, MIPS_INS_DSRA32,
3336 #ifndef CAPSTONE_DIET
3337  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
3338 #endif
3339 },
3340 {
3341  Mips_DSRAV, MIPS_INS_DSRAV,
3342 #ifndef CAPSTONE_DIET
3343  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
3344 #endif
3345 },
3346 {
3347  Mips_DSRL, MIPS_INS_DSRL,
3348 #ifndef CAPSTONE_DIET
3349  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
3350 #endif
3351 },
3352 {
3353  Mips_DSRL32, MIPS_INS_DSRL32,
3354 #ifndef CAPSTONE_DIET
3355  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
3356 #endif
3357 },
3358 {
3359  Mips_DSRLV, MIPS_INS_DSRLV,
3360 #ifndef CAPSTONE_DIET
3361  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
3362 #endif
3363 },
3364 {
3365  Mips_DSUB, MIPS_INS_DSUB,
3366 #ifndef CAPSTONE_DIET
3367  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
3368 #endif
3369 },
3370 {
3371  Mips_DSUBu, MIPS_INS_DSUBU,
3372 #ifndef CAPSTONE_DIET
3373  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
3374 #endif
3375 },
3376 {
3377  Mips_DUDIV, MIPS_INS_DDIVU,
3378 #ifndef CAPSTONE_DIET
3379  { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
3380 #endif
3381 },
3382 {
3383  Mips_DivRxRy16, MIPS_INS_DIV,
3384 #ifndef CAPSTONE_DIET
3385  { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
3386 #endif
3387 },
3388 {
3389  Mips_DivuRxRy16, MIPS_INS_DIVU,
3390 #ifndef CAPSTONE_DIET
3391  { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
3392 #endif
3393 },
3394 {
3395  Mips_EHB, MIPS_INS_EHB,
3396 #ifndef CAPSTONE_DIET
3397  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
3398 #endif
3399 },
3400 {
3401  Mips_EHB_MM, MIPS_INS_EHB,
3402 #ifndef CAPSTONE_DIET
3403  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
3404 #endif
3405 },
3406 {
3407  Mips_EI, MIPS_INS_EI,
3408 #ifndef CAPSTONE_DIET
3409  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
3410 #endif
3411 },
3412 {
3413  Mips_EI_MM, MIPS_INS_EI,
3414 #ifndef CAPSTONE_DIET
3415  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
3416 #endif
3417 },
3418 {
3419  Mips_ERET, MIPS_INS_ERET,
3420 #ifndef CAPSTONE_DIET
3421  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, 0 }, 0, 0
3422 #endif
3423 },
3424 {
3425  Mips_ERET_MM, MIPS_INS_ERET,
3426 #ifndef CAPSTONE_DIET
3427  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
3428 #endif
3429 },
3430 {
3431  Mips_EXT, MIPS_INS_EXT,
3432 #ifndef CAPSTONE_DIET
3433  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
3434 #endif
3435 },
3436 {
3437  Mips_EXTP, MIPS_INS_EXTP,
3438 #ifndef CAPSTONE_DIET
3439  { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3440 #endif
3441 },
3442 {
3443  Mips_EXTPDP, MIPS_INS_EXTPDP,
3444 #ifndef CAPSTONE_DIET
3445  { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPPOS, MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3446 #endif
3447 },
3448 {
3449  Mips_EXTPDPV, MIPS_INS_EXTPDPV,
3450 #ifndef CAPSTONE_DIET
3451  { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPPOS, MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3452 #endif
3453 },
3454 {
3455  Mips_EXTPV, MIPS_INS_EXTPV,
3456 #ifndef CAPSTONE_DIET
3457  { MIPS_REG_DSPPOS, 0 }, { MIPS_REG_DSPEFI, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3458 #endif
3459 },
3460 {
3461  Mips_EXTRV_RS_W, MIPS_INS_EXTRV_RS,
3462 #ifndef CAPSTONE_DIET
3463  { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3464 #endif
3465 },
3466 {
3467  Mips_EXTRV_R_W, MIPS_INS_EXTRV_R,
3468 #ifndef CAPSTONE_DIET
3469  { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3470 #endif
3471 },
3472 {
3473  Mips_EXTRV_S_H, MIPS_INS_EXTRV_S,
3474 #ifndef CAPSTONE_DIET
3475  { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3476 #endif
3477 },
3478 {
3479  Mips_EXTRV_W, MIPS_INS_EXTRV,
3480 #ifndef CAPSTONE_DIET
3481  { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3482 #endif
3483 },
3484 {
3485  Mips_EXTR_RS_W, MIPS_INS_EXTR_RS,
3486 #ifndef CAPSTONE_DIET
3487  { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3488 #endif
3489 },
3490 {
3491  Mips_EXTR_R_W, MIPS_INS_EXTR_R,
3492 #ifndef CAPSTONE_DIET
3493  { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3494 #endif
3495 },
3496 {
3497  Mips_EXTR_S_H, MIPS_INS_EXTR_S,
3498 #ifndef CAPSTONE_DIET
3499  { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3500 #endif
3501 },
3502 {
3503  Mips_EXTR_W, MIPS_INS_EXTR,
3504 #ifndef CAPSTONE_DIET
3505  { 0 }, { MIPS_REG_DSPOUTFLAG23, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
3506 #endif
3507 },
3508 {
3509  Mips_EXTS, MIPS_INS_EXTS,
3510 #ifndef CAPSTONE_DIET
3511  { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
3512 #endif
3513 },
3514 {
3515  Mips_EXTS32, MIPS_INS_EXTS32,
3516 #ifndef CAPSTONE_DIET
3517  { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
3518 #endif
3519 },
3520 {
3521  Mips_EXT_MM, MIPS_INS_EXT,
3522 #ifndef CAPSTONE_DIET
3523  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
3524 #endif
3525 },
3526 {
3527  Mips_FABS_D32, MIPS_INS_ABS,
3528 #ifndef CAPSTONE_DIET
3529  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
3530 #endif
3531 },
3532 {
3533  Mips_FABS_D64, MIPS_INS_ABS,
3534 #ifndef CAPSTONE_DIET
3535  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
3536 #endif
3537 },
3538 {
3539  Mips_FABS_MM, MIPS_INS_ABS,
3540 #ifndef CAPSTONE_DIET
3541  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
3542 #endif
3543 },
3544 {
3545  Mips_FABS_S, MIPS_INS_ABS,
3546 #ifndef CAPSTONE_DIET
3547  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
3548 #endif
3549 },
3550 {
3551  Mips_FABS_S_MM, MIPS_INS_ABS,
3552 #ifndef CAPSTONE_DIET
3553  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
3554 #endif
3555 },
3556 {
3557  Mips_FADD_D, MIPS_INS_FADD,
3558 #ifndef CAPSTONE_DIET
3559  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3560 #endif
3561 },
3562 {
3563  Mips_FADD_D32, MIPS_INS_ADD,
3564 #ifndef CAPSTONE_DIET
3565  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
3566 #endif
3567 },
3568 {
3569  Mips_FADD_D64, MIPS_INS_ADD,
3570 #ifndef CAPSTONE_DIET
3571  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
3572 #endif
3573 },
3574 {
3575  Mips_FADD_MM, MIPS_INS_ADD,
3576 #ifndef CAPSTONE_DIET
3577  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
3578 #endif
3579 },
3580 {
3581  Mips_FADD_S, MIPS_INS_ADD,
3582 #ifndef CAPSTONE_DIET
3583  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
3584 #endif
3585 },
3586 {
3587  Mips_FADD_S_MM, MIPS_INS_ADD,
3588 #ifndef CAPSTONE_DIET
3589  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
3590 #endif
3591 },
3592 {
3593  Mips_FADD_W, MIPS_INS_FADD,
3594 #ifndef CAPSTONE_DIET
3595  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3596 #endif
3597 },
3598 {
3599  Mips_FCAF_D, MIPS_INS_FCAF,
3600 #ifndef CAPSTONE_DIET
3601  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3602 #endif
3603 },
3604 {
3605  Mips_FCAF_W, MIPS_INS_FCAF,
3606 #ifndef CAPSTONE_DIET
3607  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3608 #endif
3609 },
3610 {
3611  Mips_FCEQ_D, MIPS_INS_FCEQ,
3612 #ifndef CAPSTONE_DIET
3613  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3614 #endif
3615 },
3616 {
3617  Mips_FCEQ_W, MIPS_INS_FCEQ,
3618 #ifndef CAPSTONE_DIET
3619  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3620 #endif
3621 },
3622 {
3623  Mips_FCLASS_D, MIPS_INS_FCLASS,
3624 #ifndef CAPSTONE_DIET
3625  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3626 #endif
3627 },
3628 {
3629  Mips_FCLASS_W, MIPS_INS_FCLASS,
3630 #ifndef CAPSTONE_DIET
3631  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3632 #endif
3633 },
3634 {
3635  Mips_FCLE_D, MIPS_INS_FCLE,
3636 #ifndef CAPSTONE_DIET
3637  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3638 #endif
3639 },
3640 {
3641  Mips_FCLE_W, MIPS_INS_FCLE,
3642 #ifndef CAPSTONE_DIET
3643  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3644 #endif
3645 },
3646 {
3647  Mips_FCLT_D, MIPS_INS_FCLT,
3648 #ifndef CAPSTONE_DIET
3649  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3650 #endif
3651 },
3652 {
3653  Mips_FCLT_W, MIPS_INS_FCLT,
3654 #ifndef CAPSTONE_DIET
3655  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3656 #endif
3657 },
3658 {
3659  Mips_FCMP_D32, MIPS_INS_C,
3660 #ifndef CAPSTONE_DIET
3661  { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
3662 #endif
3663 },
3664 {
3665  Mips_FCMP_D32_MM, MIPS_INS_C,
3666 #ifndef CAPSTONE_DIET
3667  { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
3668 #endif
3669 },
3670 {
3671  Mips_FCMP_D64, MIPS_INS_C,
3672 #ifndef CAPSTONE_DIET
3673  { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_FP64BIT, 0 }, 0, 0
3674 #endif
3675 },
3676 {
3677  Mips_FCMP_S32, MIPS_INS_C,
3678 #ifndef CAPSTONE_DIET
3679  { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
3680 #endif
3681 },
3682 {
3683  Mips_FCMP_S32_MM, MIPS_INS_C,
3684 #ifndef CAPSTONE_DIET
3685  { 0 }, { MIPS_REG_FCC0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
3686 #endif
3687 },
3688 {
3689  Mips_FCNE_D, MIPS_INS_FCNE,
3690 #ifndef CAPSTONE_DIET
3691  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3692 #endif
3693 },
3694 {
3695  Mips_FCNE_W, MIPS_INS_FCNE,
3696 #ifndef CAPSTONE_DIET
3697  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3698 #endif
3699 },
3700 {
3701  Mips_FCOR_D, MIPS_INS_FCOR,
3702 #ifndef CAPSTONE_DIET
3703  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3704 #endif
3705 },
3706 {
3707  Mips_FCOR_W, MIPS_INS_FCOR,
3708 #ifndef CAPSTONE_DIET
3709  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3710 #endif
3711 },
3712 {
3713  Mips_FCUEQ_D, MIPS_INS_FCUEQ,
3714 #ifndef CAPSTONE_DIET
3715  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3716 #endif
3717 },
3718 {
3719  Mips_FCUEQ_W, MIPS_INS_FCUEQ,
3720 #ifndef CAPSTONE_DIET
3721  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3722 #endif
3723 },
3724 {
3725  Mips_FCULE_D, MIPS_INS_FCULE,
3726 #ifndef CAPSTONE_DIET
3727  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3728 #endif
3729 },
3730 {
3731  Mips_FCULE_W, MIPS_INS_FCULE,
3732 #ifndef CAPSTONE_DIET
3733  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3734 #endif
3735 },
3736 {
3737  Mips_FCULT_D, MIPS_INS_FCULT,
3738 #ifndef CAPSTONE_DIET
3739  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3740 #endif
3741 },
3742 {
3743  Mips_FCULT_W, MIPS_INS_FCULT,
3744 #ifndef CAPSTONE_DIET
3745  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3746 #endif
3747 },
3748 {
3749  Mips_FCUNE_D, MIPS_INS_FCUNE,
3750 #ifndef CAPSTONE_DIET
3751  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3752 #endif
3753 },
3754 {
3755  Mips_FCUNE_W, MIPS_INS_FCUNE,
3756 #ifndef CAPSTONE_DIET
3757  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3758 #endif
3759 },
3760 {
3761  Mips_FCUN_D, MIPS_INS_FCUN,
3762 #ifndef CAPSTONE_DIET
3763  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3764 #endif
3765 },
3766 {
3767  Mips_FCUN_W, MIPS_INS_FCUN,
3768 #ifndef CAPSTONE_DIET
3769  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3770 #endif
3771 },
3772 {
3773  Mips_FDIV_D, MIPS_INS_FDIV,
3774 #ifndef CAPSTONE_DIET
3775  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3776 #endif
3777 },
3778 {
3779  Mips_FDIV_D32, MIPS_INS_DIV,
3780 #ifndef CAPSTONE_DIET
3781  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
3782 #endif
3783 },
3784 {
3785  Mips_FDIV_D64, MIPS_INS_DIV,
3786 #ifndef CAPSTONE_DIET
3787  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
3788 #endif
3789 },
3790 {
3791  Mips_FDIV_MM, MIPS_INS_DIV,
3792 #ifndef CAPSTONE_DIET
3793  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
3794 #endif
3795 },
3796 {
3797  Mips_FDIV_S, MIPS_INS_DIV,
3798 #ifndef CAPSTONE_DIET
3799  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
3800 #endif
3801 },
3802 {
3803  Mips_FDIV_S_MM, MIPS_INS_DIV,
3804 #ifndef CAPSTONE_DIET
3805  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
3806 #endif
3807 },
3808 {
3809  Mips_FDIV_W, MIPS_INS_FDIV,
3810 #ifndef CAPSTONE_DIET
3811  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3812 #endif
3813 },
3814 {
3815  Mips_FEXDO_H, MIPS_INS_FEXDO,
3816 #ifndef CAPSTONE_DIET
3817  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3818 #endif
3819 },
3820 {
3821  Mips_FEXDO_W, MIPS_INS_FEXDO,
3822 #ifndef CAPSTONE_DIET
3823  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3824 #endif
3825 },
3826 {
3827  Mips_FEXP2_D, MIPS_INS_FEXP2,
3828 #ifndef CAPSTONE_DIET
3829  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3830 #endif
3831 },
3832 {
3833  Mips_FEXP2_W, MIPS_INS_FEXP2,
3834 #ifndef CAPSTONE_DIET
3835  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3836 #endif
3837 },
3838 {
3839  Mips_FEXUPL_D, MIPS_INS_FEXUPL,
3840 #ifndef CAPSTONE_DIET
3841  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3842 #endif
3843 },
3844 {
3845  Mips_FEXUPL_W, MIPS_INS_FEXUPL,
3846 #ifndef CAPSTONE_DIET
3847  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3848 #endif
3849 },
3850 {
3851  Mips_FEXUPR_D, MIPS_INS_FEXUPR,
3852 #ifndef CAPSTONE_DIET
3853  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3854 #endif
3855 },
3856 {
3857  Mips_FEXUPR_W, MIPS_INS_FEXUPR,
3858 #ifndef CAPSTONE_DIET
3859  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3860 #endif
3861 },
3862 {
3863  Mips_FFINT_S_D, MIPS_INS_FFINT_S,
3864 #ifndef CAPSTONE_DIET
3865  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3866 #endif
3867 },
3868 {
3869  Mips_FFINT_S_W, MIPS_INS_FFINT_S,
3870 #ifndef CAPSTONE_DIET
3871  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3872 #endif
3873 },
3874 {
3875  Mips_FFINT_U_D, MIPS_INS_FFINT_U,
3876 #ifndef CAPSTONE_DIET
3877  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3878 #endif
3879 },
3880 {
3881  Mips_FFINT_U_W, MIPS_INS_FFINT_U,
3882 #ifndef CAPSTONE_DIET
3883  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3884 #endif
3885 },
3886 {
3887  Mips_FFQL_D, MIPS_INS_FFQL,
3888 #ifndef CAPSTONE_DIET
3889  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3890 #endif
3891 },
3892 {
3893  Mips_FFQL_W, MIPS_INS_FFQL,
3894 #ifndef CAPSTONE_DIET
3895  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3896 #endif
3897 },
3898 {
3899  Mips_FFQR_D, MIPS_INS_FFQR,
3900 #ifndef CAPSTONE_DIET
3901  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3902 #endif
3903 },
3904 {
3905  Mips_FFQR_W, MIPS_INS_FFQR,
3906 #ifndef CAPSTONE_DIET
3907  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3908 #endif
3909 },
3910 {
3911  Mips_FILL_B, MIPS_INS_FILL,
3912 #ifndef CAPSTONE_DIET
3913  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3914 #endif
3915 },
3916 {
3917  Mips_FILL_D, MIPS_INS_FILL,
3918 #ifndef CAPSTONE_DIET
3919  { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0
3920 #endif
3921 },
3922 {
3923  Mips_FILL_H, MIPS_INS_FILL,
3924 #ifndef CAPSTONE_DIET
3925  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3926 #endif
3927 },
3928 {
3929  Mips_FILL_W, MIPS_INS_FILL,
3930 #ifndef CAPSTONE_DIET
3931  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3932 #endif
3933 },
3934 {
3935  Mips_FLOG2_D, MIPS_INS_FLOG2,
3936 #ifndef CAPSTONE_DIET
3937  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3938 #endif
3939 },
3940 {
3941  Mips_FLOG2_W, MIPS_INS_FLOG2,
3942 #ifndef CAPSTONE_DIET
3943  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3944 #endif
3945 },
3946 {
3947  Mips_FLOOR_L_D64, MIPS_INS_FLOOR,
3948 #ifndef CAPSTONE_DIET
3949  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
3950 #endif
3951 },
3952 {
3953  Mips_FLOOR_L_S, MIPS_INS_FLOOR,
3954 #ifndef CAPSTONE_DIET
3955  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
3956 #endif
3957 },
3958 {
3959  Mips_FLOOR_W_D32, MIPS_INS_FLOOR,
3960 #ifndef CAPSTONE_DIET
3961  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
3962 #endif
3963 },
3964 {
3965  Mips_FLOOR_W_D64, MIPS_INS_FLOOR,
3966 #ifndef CAPSTONE_DIET
3967  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0
3968 #endif
3969 },
3970 {
3971  Mips_FLOOR_W_MM, MIPS_INS_FLOOR,
3972 #ifndef CAPSTONE_DIET
3973  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
3974 #endif
3975 },
3976 {
3977  Mips_FLOOR_W_S, MIPS_INS_FLOOR,
3978 #ifndef CAPSTONE_DIET
3979  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
3980 #endif
3981 },
3982 {
3983  Mips_FLOOR_W_S_MM, MIPS_INS_FLOOR,
3984 #ifndef CAPSTONE_DIET
3985  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
3986 #endif
3987 },
3988 {
3989  Mips_FMADD_D, MIPS_INS_FMADD,
3990 #ifndef CAPSTONE_DIET
3991  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3992 #endif
3993 },
3994 {
3995  Mips_FMADD_W, MIPS_INS_FMADD,
3996 #ifndef CAPSTONE_DIET
3997  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
3998 #endif
3999 },
4000 {
4001  Mips_FMAX_A_D, MIPS_INS_FMAX_A,
4002 #ifndef CAPSTONE_DIET
4003  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4004 #endif
4005 },
4006 {
4007  Mips_FMAX_A_W, MIPS_INS_FMAX_A,
4008 #ifndef CAPSTONE_DIET
4009  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4010 #endif
4011 },
4012 {
4013  Mips_FMAX_D, MIPS_INS_FMAX,
4014 #ifndef CAPSTONE_DIET
4015  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4016 #endif
4017 },
4018 {
4019  Mips_FMAX_W, MIPS_INS_FMAX,
4020 #ifndef CAPSTONE_DIET
4021  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4022 #endif
4023 },
4024 {
4025  Mips_FMIN_A_D, MIPS_INS_FMIN_A,
4026 #ifndef CAPSTONE_DIET
4027  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4028 #endif
4029 },
4030 {
4031  Mips_FMIN_A_W, MIPS_INS_FMIN_A,
4032 #ifndef CAPSTONE_DIET
4033  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4034 #endif
4035 },
4036 {
4037  Mips_FMIN_D, MIPS_INS_FMIN,
4038 #ifndef CAPSTONE_DIET
4039  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4040 #endif
4041 },
4042 {
4043  Mips_FMIN_W, MIPS_INS_FMIN,
4044 #ifndef CAPSTONE_DIET
4045  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4046 #endif
4047 },
4048 {
4049  Mips_FMOV_D32, MIPS_INS_MOV,
4050 #ifndef CAPSTONE_DIET
4051  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
4052 #endif
4053 },
4054 {
4055  Mips_FMOV_D32_MM, MIPS_INS_MOV,
4056 #ifndef CAPSTONE_DIET
4057  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4058 #endif
4059 },
4060 {
4061  Mips_FMOV_D64, MIPS_INS_MOV,
4062 #ifndef CAPSTONE_DIET
4063  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
4064 #endif
4065 },
4066 {
4067  Mips_FMOV_S, MIPS_INS_MOV,
4068 #ifndef CAPSTONE_DIET
4069  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
4070 #endif
4071 },
4072 {
4073  Mips_FMOV_S_MM, MIPS_INS_MOV,
4074 #ifndef CAPSTONE_DIET
4075  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4076 #endif
4077 },
4078 {
4079  Mips_FMSUB_D, MIPS_INS_FMSUB,
4080 #ifndef CAPSTONE_DIET
4081  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4082 #endif
4083 },
4084 {
4085  Mips_FMSUB_W, MIPS_INS_FMSUB,
4086 #ifndef CAPSTONE_DIET
4087  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4088 #endif
4089 },
4090 {
4091  Mips_FMUL_D, MIPS_INS_FMUL,
4092 #ifndef CAPSTONE_DIET
4093  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4094 #endif
4095 },
4096 {
4097  Mips_FMUL_D32, MIPS_INS_MUL,
4098 #ifndef CAPSTONE_DIET
4099  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
4100 #endif
4101 },
4102 {
4103  Mips_FMUL_D64, MIPS_INS_MUL,
4104 #ifndef CAPSTONE_DIET
4105  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
4106 #endif
4107 },
4108 {
4109  Mips_FMUL_MM, MIPS_INS_MUL,
4110 #ifndef CAPSTONE_DIET
4111  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4112 #endif
4113 },
4114 {
4115  Mips_FMUL_S, MIPS_INS_MUL,
4116 #ifndef CAPSTONE_DIET
4117  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
4118 #endif
4119 },
4120 {
4121  Mips_FMUL_S_MM, MIPS_INS_MUL,
4122 #ifndef CAPSTONE_DIET
4123  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4124 #endif
4125 },
4126 {
4127  Mips_FMUL_W, MIPS_INS_FMUL,
4128 #ifndef CAPSTONE_DIET
4129  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4130 #endif
4131 },
4132 {
4133  Mips_FNEG_D32, MIPS_INS_NEG,
4134 #ifndef CAPSTONE_DIET
4135  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
4136 #endif
4137 },
4138 {
4139  Mips_FNEG_D64, MIPS_INS_NEG,
4140 #ifndef CAPSTONE_DIET
4141  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
4142 #endif
4143 },
4144 {
4145  Mips_FNEG_MM, MIPS_INS_NEG,
4146 #ifndef CAPSTONE_DIET
4147  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4148 #endif
4149 },
4150 {
4151  Mips_FNEG_S, MIPS_INS_NEG,
4152 #ifndef CAPSTONE_DIET
4153  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
4154 #endif
4155 },
4156 {
4157  Mips_FNEG_S_MM, MIPS_INS_NEG,
4158 #ifndef CAPSTONE_DIET
4159  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4160 #endif
4161 },
4162 {
4163  Mips_FRCP_D, MIPS_INS_FRCP,
4164 #ifndef CAPSTONE_DIET
4165  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4166 #endif
4167 },
4168 {
4169  Mips_FRCP_W, MIPS_INS_FRCP,
4170 #ifndef CAPSTONE_DIET
4171  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4172 #endif
4173 },
4174 {
4175  Mips_FRINT_D, MIPS_INS_FRINT,
4176 #ifndef CAPSTONE_DIET
4177  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4178 #endif
4179 },
4180 {
4181  Mips_FRINT_W, MIPS_INS_FRINT,
4182 #ifndef CAPSTONE_DIET
4183  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4184 #endif
4185 },
4186 {
4187  Mips_FRSQRT_D, MIPS_INS_FRSQRT,
4188 #ifndef CAPSTONE_DIET
4189  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4190 #endif
4191 },
4192 {
4193  Mips_FRSQRT_W, MIPS_INS_FRSQRT,
4194 #ifndef CAPSTONE_DIET
4195  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4196 #endif
4197 },
4198 {
4199  Mips_FSAF_D, MIPS_INS_FSAF,
4200 #ifndef CAPSTONE_DIET
4201  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4202 #endif
4203 },
4204 {
4205  Mips_FSAF_W, MIPS_INS_FSAF,
4206 #ifndef CAPSTONE_DIET
4207  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4208 #endif
4209 },
4210 {
4211  Mips_FSEQ_D, MIPS_INS_FSEQ,
4212 #ifndef CAPSTONE_DIET
4213  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4214 #endif
4215 },
4216 {
4217  Mips_FSEQ_W, MIPS_INS_FSEQ,
4218 #ifndef CAPSTONE_DIET
4219  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4220 #endif
4221 },
4222 {
4223  Mips_FSLE_D, MIPS_INS_FSLE,
4224 #ifndef CAPSTONE_DIET
4225  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4226 #endif
4227 },
4228 {
4229  Mips_FSLE_W, MIPS_INS_FSLE,
4230 #ifndef CAPSTONE_DIET
4231  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4232 #endif
4233 },
4234 {
4235  Mips_FSLT_D, MIPS_INS_FSLT,
4236 #ifndef CAPSTONE_DIET
4237  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4238 #endif
4239 },
4240 {
4241  Mips_FSLT_W, MIPS_INS_FSLT,
4242 #ifndef CAPSTONE_DIET
4243  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4244 #endif
4245 },
4246 {
4247  Mips_FSNE_D, MIPS_INS_FSNE,
4248 #ifndef CAPSTONE_DIET
4249  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4250 #endif
4251 },
4252 {
4253  Mips_FSNE_W, MIPS_INS_FSNE,
4254 #ifndef CAPSTONE_DIET
4255  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4256 #endif
4257 },
4258 {
4259  Mips_FSOR_D, MIPS_INS_FSOR,
4260 #ifndef CAPSTONE_DIET
4261  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4262 #endif
4263 },
4264 {
4265  Mips_FSOR_W, MIPS_INS_FSOR,
4266 #ifndef CAPSTONE_DIET
4267  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4268 #endif
4269 },
4270 {
4271  Mips_FSQRT_D, MIPS_INS_FSQRT,
4272 #ifndef CAPSTONE_DIET
4273  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4274 #endif
4275 },
4276 {
4277  Mips_FSQRT_D32, MIPS_INS_SQRT,
4278 #ifndef CAPSTONE_DIET
4279  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
4280 #endif
4281 },
4282 {
4283  Mips_FSQRT_D64, MIPS_INS_SQRT,
4284 #ifndef CAPSTONE_DIET
4285  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0
4286 #endif
4287 },
4288 {
4289  Mips_FSQRT_MM, MIPS_INS_SQRT,
4290 #ifndef CAPSTONE_DIET
4291  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4292 #endif
4293 },
4294 {
4295  Mips_FSQRT_S, MIPS_INS_SQRT,
4296 #ifndef CAPSTONE_DIET
4297  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
4298 #endif
4299 },
4300 {
4301  Mips_FSQRT_S_MM, MIPS_INS_SQRT,
4302 #ifndef CAPSTONE_DIET
4303  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4304 #endif
4305 },
4306 {
4307  Mips_FSQRT_W, MIPS_INS_FSQRT,
4308 #ifndef CAPSTONE_DIET
4309  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4310 #endif
4311 },
4312 {
4313  Mips_FSUB_D, MIPS_INS_FSUB,
4314 #ifndef CAPSTONE_DIET
4315  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4316 #endif
4317 },
4318 {
4319  Mips_FSUB_D32, MIPS_INS_SUB,
4320 #ifndef CAPSTONE_DIET
4321  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
4322 #endif
4323 },
4324 {
4325  Mips_FSUB_D64, MIPS_INS_SUB,
4326 #ifndef CAPSTONE_DIET
4327  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
4328 #endif
4329 },
4330 {
4331  Mips_FSUB_MM, MIPS_INS_SUB,
4332 #ifndef CAPSTONE_DIET
4333  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4334 #endif
4335 },
4336 {
4337  Mips_FSUB_S, MIPS_INS_SUB,
4338 #ifndef CAPSTONE_DIET
4339  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
4340 #endif
4341 },
4342 {
4343  Mips_FSUB_S_MM, MIPS_INS_SUB,
4344 #ifndef CAPSTONE_DIET
4345  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4346 #endif
4347 },
4348 {
4349  Mips_FSUB_W, MIPS_INS_FSUB,
4350 #ifndef CAPSTONE_DIET
4351  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4352 #endif
4353 },
4354 {
4355  Mips_FSUEQ_D, MIPS_INS_FSUEQ,
4356 #ifndef CAPSTONE_DIET
4357  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4358 #endif
4359 },
4360 {
4361  Mips_FSUEQ_W, MIPS_INS_FSUEQ,
4362 #ifndef CAPSTONE_DIET
4363  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4364 #endif
4365 },
4366 {
4367  Mips_FSULE_D, MIPS_INS_FSULE,
4368 #ifndef CAPSTONE_DIET
4369  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4370 #endif
4371 },
4372 {
4373  Mips_FSULE_W, MIPS_INS_FSULE,
4374 #ifndef CAPSTONE_DIET
4375  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4376 #endif
4377 },
4378 {
4379  Mips_FSULT_D, MIPS_INS_FSULT,
4380 #ifndef CAPSTONE_DIET
4381  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4382 #endif
4383 },
4384 {
4385  Mips_FSULT_W, MIPS_INS_FSULT,
4386 #ifndef CAPSTONE_DIET
4387  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4388 #endif
4389 },
4390 {
4391  Mips_FSUNE_D, MIPS_INS_FSUNE,
4392 #ifndef CAPSTONE_DIET
4393  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4394 #endif
4395 },
4396 {
4397  Mips_FSUNE_W, MIPS_INS_FSUNE,
4398 #ifndef CAPSTONE_DIET
4399  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4400 #endif
4401 },
4402 {
4403  Mips_FSUN_D, MIPS_INS_FSUN,
4404 #ifndef CAPSTONE_DIET
4405  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4406 #endif
4407 },
4408 {
4409  Mips_FSUN_W, MIPS_INS_FSUN,
4410 #ifndef CAPSTONE_DIET
4411  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4412 #endif
4413 },
4414 {
4415  Mips_FTINT_S_D, MIPS_INS_FTINT_S,
4416 #ifndef CAPSTONE_DIET
4417  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4418 #endif
4419 },
4420 {
4421  Mips_FTINT_S_W, MIPS_INS_FTINT_S,
4422 #ifndef CAPSTONE_DIET
4423  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4424 #endif
4425 },
4426 {
4427  Mips_FTINT_U_D, MIPS_INS_FTINT_U,
4428 #ifndef CAPSTONE_DIET
4429  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4430 #endif
4431 },
4432 {
4433  Mips_FTINT_U_W, MIPS_INS_FTINT_U,
4434 #ifndef CAPSTONE_DIET
4435  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4436 #endif
4437 },
4438 {
4439  Mips_FTQ_H, MIPS_INS_FTQ,
4440 #ifndef CAPSTONE_DIET
4441  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4442 #endif
4443 },
4444 {
4445  Mips_FTQ_W, MIPS_INS_FTQ,
4446 #ifndef CAPSTONE_DIET
4447  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4448 #endif
4449 },
4450 {
4451  Mips_FTRUNC_S_D, MIPS_INS_FTRUNC_S,
4452 #ifndef CAPSTONE_DIET
4453  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4454 #endif
4455 },
4456 {
4457  Mips_FTRUNC_S_W, MIPS_INS_FTRUNC_S,
4458 #ifndef CAPSTONE_DIET
4459  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4460 #endif
4461 },
4462 {
4463  Mips_FTRUNC_U_D, MIPS_INS_FTRUNC_U,
4464 #ifndef CAPSTONE_DIET
4465  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4466 #endif
4467 },
4468 {
4469  Mips_FTRUNC_U_W, MIPS_INS_FTRUNC_U,
4470 #ifndef CAPSTONE_DIET
4471  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4472 #endif
4473 },
4474 {
4475  Mips_HADD_S_D, MIPS_INS_HADD_S,
4476 #ifndef CAPSTONE_DIET
4477  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4478 #endif
4479 },
4480 {
4481  Mips_HADD_S_H, MIPS_INS_HADD_S,
4482 #ifndef CAPSTONE_DIET
4483  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4484 #endif
4485 },
4486 {
4487  Mips_HADD_S_W, MIPS_INS_HADD_S,
4488 #ifndef CAPSTONE_DIET
4489  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4490 #endif
4491 },
4492 {
4493  Mips_HADD_U_D, MIPS_INS_HADD_U,
4494 #ifndef CAPSTONE_DIET
4495  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4496 #endif
4497 },
4498 {
4499  Mips_HADD_U_H, MIPS_INS_HADD_U,
4500 #ifndef CAPSTONE_DIET
4501  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4502 #endif
4503 },
4504 {
4505  Mips_HADD_U_W, MIPS_INS_HADD_U,
4506 #ifndef CAPSTONE_DIET
4507  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4508 #endif
4509 },
4510 {
4511  Mips_HSUB_S_D, MIPS_INS_HSUB_S,
4512 #ifndef CAPSTONE_DIET
4513  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4514 #endif
4515 },
4516 {
4517  Mips_HSUB_S_H, MIPS_INS_HSUB_S,
4518 #ifndef CAPSTONE_DIET
4519  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4520 #endif
4521 },
4522 {
4523  Mips_HSUB_S_W, MIPS_INS_HSUB_S,
4524 #ifndef CAPSTONE_DIET
4525  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4526 #endif
4527 },
4528 {
4529  Mips_HSUB_U_D, MIPS_INS_HSUB_U,
4530 #ifndef CAPSTONE_DIET
4531  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4532 #endif
4533 },
4534 {
4535  Mips_HSUB_U_H, MIPS_INS_HSUB_U,
4536 #ifndef CAPSTONE_DIET
4537  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4538 #endif
4539 },
4540 {
4541  Mips_HSUB_U_W, MIPS_INS_HSUB_U,
4542 #ifndef CAPSTONE_DIET
4543  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4544 #endif
4545 },
4546 {
4547  Mips_ILVEV_B, MIPS_INS_ILVEV,
4548 #ifndef CAPSTONE_DIET
4549  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4550 #endif
4551 },
4552 {
4553  Mips_ILVEV_D, MIPS_INS_ILVEV,
4554 #ifndef CAPSTONE_DIET
4555  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4556 #endif
4557 },
4558 {
4559  Mips_ILVEV_H, MIPS_INS_ILVEV,
4560 #ifndef CAPSTONE_DIET
4561  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4562 #endif
4563 },
4564 {
4565  Mips_ILVEV_W, MIPS_INS_ILVEV,
4566 #ifndef CAPSTONE_DIET
4567  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4568 #endif
4569 },
4570 {
4571  Mips_ILVL_B, MIPS_INS_ILVL,
4572 #ifndef CAPSTONE_DIET
4573  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4574 #endif
4575 },
4576 {
4577  Mips_ILVL_D, MIPS_INS_ILVL,
4578 #ifndef CAPSTONE_DIET
4579  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4580 #endif
4581 },
4582 {
4583  Mips_ILVL_H, MIPS_INS_ILVL,
4584 #ifndef CAPSTONE_DIET
4585  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4586 #endif
4587 },
4588 {
4589  Mips_ILVL_W, MIPS_INS_ILVL,
4590 #ifndef CAPSTONE_DIET
4591  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4592 #endif
4593 },
4594 {
4595  Mips_ILVOD_B, MIPS_INS_ILVOD,
4596 #ifndef CAPSTONE_DIET
4597  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4598 #endif
4599 },
4600 {
4601  Mips_ILVOD_D, MIPS_INS_ILVOD,
4602 #ifndef CAPSTONE_DIET
4603  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4604 #endif
4605 },
4606 {
4607  Mips_ILVOD_H, MIPS_INS_ILVOD,
4608 #ifndef CAPSTONE_DIET
4609  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4610 #endif
4611 },
4612 {
4613  Mips_ILVOD_W, MIPS_INS_ILVOD,
4614 #ifndef CAPSTONE_DIET
4615  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4616 #endif
4617 },
4618 {
4619  Mips_ILVR_B, MIPS_INS_ILVR,
4620 #ifndef CAPSTONE_DIET
4621  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4622 #endif
4623 },
4624 {
4625  Mips_ILVR_D, MIPS_INS_ILVR,
4626 #ifndef CAPSTONE_DIET
4627  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4628 #endif
4629 },
4630 {
4631  Mips_ILVR_H, MIPS_INS_ILVR,
4632 #ifndef CAPSTONE_DIET
4633  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4634 #endif
4635 },
4636 {
4637  Mips_ILVR_W, MIPS_INS_ILVR,
4638 #ifndef CAPSTONE_DIET
4639  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4640 #endif
4641 },
4642 {
4643  Mips_INS, MIPS_INS_INS,
4644 #ifndef CAPSTONE_DIET
4645  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
4646 #endif
4647 },
4648 {
4649  Mips_INSERT_B, MIPS_INS_INSERT,
4650 #ifndef CAPSTONE_DIET
4651  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4652 #endif
4653 },
4654 {
4655  Mips_INSERT_D, MIPS_INS_INSERT,
4656 #ifndef CAPSTONE_DIET
4657  { 0 }, { 0 }, { MIPS_GRP_MSA, MIPS_GRP_MIPS64, 0 }, 0, 0
4658 #endif
4659 },
4660 {
4661  Mips_INSERT_H, MIPS_INS_INSERT,
4662 #ifndef CAPSTONE_DIET
4663  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4664 #endif
4665 },
4666 {
4667  Mips_INSERT_W, MIPS_INS_INSERT,
4668 #ifndef CAPSTONE_DIET
4669  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4670 #endif
4671 },
4672 {
4673  Mips_INSV, MIPS_INS_INSV,
4674 #ifndef CAPSTONE_DIET
4675  { MIPS_REG_DSPPOS, MIPS_REG_DSPSCOUNT, 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
4676 #endif
4677 },
4678 {
4679  Mips_INSVE_B, MIPS_INS_INSVE,
4680 #ifndef CAPSTONE_DIET
4681  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4682 #endif
4683 },
4684 {
4685  Mips_INSVE_D, MIPS_INS_INSVE,
4686 #ifndef CAPSTONE_DIET
4687  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4688 #endif
4689 },
4690 {
4691  Mips_INSVE_H, MIPS_INS_INSVE,
4692 #ifndef CAPSTONE_DIET
4693  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4694 #endif
4695 },
4696 {
4697  Mips_INSVE_W, MIPS_INS_INSVE,
4698 #ifndef CAPSTONE_DIET
4699  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4700 #endif
4701 },
4702 {
4703  Mips_INS_MM, MIPS_INS_INS,
4704 #ifndef CAPSTONE_DIET
4705  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4706 #endif
4707 },
4708 {
4709  Mips_J, MIPS_INS_J,
4710 #ifndef CAPSTONE_DIET
4711  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
4712 #endif
4713 },
4714 {
4715  Mips_JAL, MIPS_INS_JAL,
4716 #ifndef CAPSTONE_DIET
4717  { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
4718 #endif
4719 },
4720 {
4721  Mips_JALR, MIPS_INS_JALR,
4722 #ifndef CAPSTONE_DIET
4723  { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0
4724 #endif
4725 },
4726 {
4727  Mips_JALR16_MM, MIPS_INS_JALR,
4728 #ifndef CAPSTONE_DIET
4729  { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0
4730 #endif
4731 },
4732 {
4733  Mips_JALR64, MIPS_INS_JALR,
4734 #ifndef CAPSTONE_DIET
4735  { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_CALL, 0 }, 0, 0
4736 #endif
4737 },
4738 {
4739  Mips_JALRS16_MM, MIPS_INS_JALRS16,
4740 #ifndef CAPSTONE_DIET
4741  { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0
4742 #endif
4743 },
4744 {
4745  Mips_JALRS_MM, MIPS_INS_JALRS,
4746 #ifndef CAPSTONE_DIET
4747  { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0
4748 #endif
4749 },
4750 {
4751  Mips_JALR_HB, MIPS_INS_JALR_HB,
4752 #ifndef CAPSTONE_DIET
4753  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_CALL, 0 }, 0, 1
4754 #endif
4755 },
4756 {
4757  Mips_JALR_MM, MIPS_INS_JALR,
4758 #ifndef CAPSTONE_DIET
4759  { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_CALL, 0 }, 0, 0
4760 #endif
4761 },
4762 {
4763  Mips_JALS_MM, MIPS_INS_JALS,
4764 #ifndef CAPSTONE_DIET
4765  { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4766 #endif
4767 },
4768 {
4769  Mips_JALX, MIPS_INS_JALX,
4770 #ifndef CAPSTONE_DIET
4771  { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
4772 #endif
4773 },
4774 {
4775  Mips_JALX_MM, MIPS_INS_JALX,
4776 #ifndef CAPSTONE_DIET
4777  { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4778 #endif
4779 },
4780 {
4781  Mips_JAL_MM, MIPS_INS_JAL,
4782 #ifndef CAPSTONE_DIET
4783  { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4784 #endif
4785 },
4786 {
4787  Mips_JIALC, MIPS_INS_JIALC,
4788 #ifndef CAPSTONE_DIET
4789  { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
4790 #endif
4791 },
4792 {
4793  Mips_JIC, MIPS_INS_JIC,
4794 #ifndef CAPSTONE_DIET
4795  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
4796 #endif
4797 },
4798 {
4799  Mips_JR, MIPS_INS_JR,
4800 #ifndef CAPSTONE_DIET
4801  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 1, 1
4802 #endif
4803 },
4804 {
4805  Mips_JR16_MM, MIPS_INS_JR16,
4806 #ifndef CAPSTONE_DIET
4807  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1
4808 #endif
4809 },
4810 {
4811  Mips_JR64, MIPS_INS_JR,
4812 #ifndef CAPSTONE_DIET
4813  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 1, 1
4814 #endif
4815 },
4816 {
4817  Mips_JRADDIUSP, MIPS_INS_JRADDIUSP,
4818 #ifndef CAPSTONE_DIET
4819  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1
4820 #endif
4821 },
4822 {
4823  Mips_JRC16_MM, MIPS_INS_JRC,
4824 #ifndef CAPSTONE_DIET
4825  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1
4826 #endif
4827 },
4828 {
4829  Mips_JR_HB, MIPS_INS_JR,
4830 #ifndef CAPSTONE_DIET
4831  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 1
4832 #endif
4833 },
4834 {
4835  Mips_JR_HB_R6, MIPS_INS_JR_HB,
4836 #ifndef CAPSTONE_DIET
4837  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 1
4838 #endif
4839 },
4840 {
4841  Mips_JR_MM, MIPS_INS_JR,
4842 #ifndef CAPSTONE_DIET
4843  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 1
4844 #endif
4845 },
4846 {
4847  Mips_J_MM, MIPS_INS_J,
4848 #ifndef CAPSTONE_DIET
4849  { 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4850 #endif
4851 },
4852 {
4853  Mips_Jal16, MIPS_INS_JAL,
4854 #ifndef CAPSTONE_DIET
4855  { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
4856 #endif
4857 },
4858 {
4859  Mips_JrRa16, MIPS_INS_JR,
4860 #ifndef CAPSTONE_DIET
4861  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1
4862 #endif
4863 },
4864 {
4865  Mips_JrcRa16, MIPS_INS_JRC,
4866 #ifndef CAPSTONE_DIET
4867  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1
4868 #endif
4869 },
4870 {
4871  Mips_JrcRx16, MIPS_INS_JRC,
4872 #ifndef CAPSTONE_DIET
4873  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 1
4874 #endif
4875 },
4876 {
4877  Mips_JumpLinkReg16, MIPS_INS_JALRC,
4878 #ifndef CAPSTONE_DIET
4879  { 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MIPS16MODE, MIPS_GRP_CALL, 0 }, 0, 0
4880 #endif
4881 },
4882 {
4883  Mips_LB, MIPS_INS_LB,
4884 #ifndef CAPSTONE_DIET
4885  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
4886 #endif
4887 },
4888 {
4889  Mips_LB64, MIPS_INS_LB,
4890 #ifndef CAPSTONE_DIET
4891  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
4892 #endif
4893 },
4894 {
4895  Mips_LBU16_MM, MIPS_INS_LBU16,
4896 #ifndef CAPSTONE_DIET
4897  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4898 #endif
4899 },
4900 {
4901  Mips_LBUX, MIPS_INS_LBUX,
4902 #ifndef CAPSTONE_DIET
4903  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
4904 #endif
4905 },
4906 {
4907  Mips_LB_MM, MIPS_INS_LB,
4908 #ifndef CAPSTONE_DIET
4909  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4910 #endif
4911 },
4912 {
4913  Mips_LBu, MIPS_INS_LBU,
4914 #ifndef CAPSTONE_DIET
4915  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
4916 #endif
4917 },
4918 {
4919  Mips_LBu64, MIPS_INS_LBU,
4920 #ifndef CAPSTONE_DIET
4921  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
4922 #endif
4923 },
4924 {
4925  Mips_LBu_MM, MIPS_INS_LBU,
4926 #ifndef CAPSTONE_DIET
4927  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4928 #endif
4929 },
4930 {
4931  Mips_LD, MIPS_INS_LD,
4932 #ifndef CAPSTONE_DIET
4933  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
4934 #endif
4935 },
4936 {
4937  Mips_LDC1, MIPS_INS_LDC1,
4938 #ifndef CAPSTONE_DIET
4939  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0
4940 #endif
4941 },
4942 {
4943  Mips_LDC164, MIPS_INS_LDC1,
4944 #ifndef CAPSTONE_DIET
4945  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0
4946 #endif
4947 },
4948 {
4949  Mips_LDC1_MM, MIPS_INS_LDC1,
4950 #ifndef CAPSTONE_DIET
4951  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
4952 #endif
4953 },
4954 {
4955  Mips_LDC2, MIPS_INS_LDC2,
4956 #ifndef CAPSTONE_DIET
4957  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
4958 #endif
4959 },
4960 {
4961  Mips_LDC2_R6, MIPS_INS_LDC2,
4962 #ifndef CAPSTONE_DIET
4963  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
4964 #endif
4965 },
4966 {
4967  Mips_LDC3, MIPS_INS_LDC3,
4968 #ifndef CAPSTONE_DIET
4969  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
4970 #endif
4971 },
4972 {
4973  Mips_LDI_B, MIPS_INS_LDI,
4974 #ifndef CAPSTONE_DIET
4975  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4976 #endif
4977 },
4978 {
4979  Mips_LDI_D, MIPS_INS_LDI,
4980 #ifndef CAPSTONE_DIET
4981  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4982 #endif
4983 },
4984 {
4985  Mips_LDI_H, MIPS_INS_LDI,
4986 #ifndef CAPSTONE_DIET
4987  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4988 #endif
4989 },
4990 {
4991  Mips_LDI_W, MIPS_INS_LDI,
4992 #ifndef CAPSTONE_DIET
4993  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
4994 #endif
4995 },
4996 {
4997  Mips_LDL, MIPS_INS_LDL,
4998 #ifndef CAPSTONE_DIET
4999  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
5000 #endif
5001 },
5002 {
5003  Mips_LDPC, MIPS_INS_LDPC,
5004 #ifndef CAPSTONE_DIET
5005  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS64R6, 0 }, 0, 0
5006 #endif
5007 },
5008 {
5009  Mips_LDR, MIPS_INS_LDR,
5010 #ifndef CAPSTONE_DIET
5011  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
5012 #endif
5013 },
5014 {
5015  Mips_LDXC1, MIPS_INS_LDXC1,
5016 #ifndef CAPSTONE_DIET
5017  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_NOTNACL, 0 }, 0, 0
5018 #endif
5019 },
5020 {
5021  Mips_LDXC164, MIPS_INS_LDXC1,
5022 #ifndef CAPSTONE_DIET
5023  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
5024 #endif
5025 },
5026 {
5027  Mips_LD_B, MIPS_INS_LD,
5028 #ifndef CAPSTONE_DIET
5029  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5030 #endif
5031 },
5032 {
5033  Mips_LD_D, MIPS_INS_LD,
5034 #ifndef CAPSTONE_DIET
5035  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5036 #endif
5037 },
5038 {
5039  Mips_LD_H, MIPS_INS_LD,
5040 #ifndef CAPSTONE_DIET
5041  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5042 #endif
5043 },
5044 {
5045  Mips_LD_W, MIPS_INS_LD,
5046 #ifndef CAPSTONE_DIET
5047  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5048 #endif
5049 },
5050 {
5051  Mips_LEA_ADDiu, MIPS_INS_ADDIU,
5052 #ifndef CAPSTONE_DIET
5053  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
5054 #endif
5055 },
5056 {
5057  Mips_LEA_ADDiu64, MIPS_INS_DADDIU,
5058 #ifndef CAPSTONE_DIET
5059  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
5060 #endif
5061 },
5062 {
5063  Mips_LEA_ADDiu_MM, MIPS_INS_ADDIU,
5064 #ifndef CAPSTONE_DIET
5065  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5066 #endif
5067 },
5068 {
5069  Mips_LH, MIPS_INS_LH,
5070 #ifndef CAPSTONE_DIET
5071  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
5072 #endif
5073 },
5074 {
5075  Mips_LH64, MIPS_INS_LH,
5076 #ifndef CAPSTONE_DIET
5077  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
5078 #endif
5079 },
5080 {
5081  Mips_LHU16_MM, MIPS_INS_LHU16,
5082 #ifndef CAPSTONE_DIET
5083  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5084 #endif
5085 },
5086 {
5087  Mips_LHX, MIPS_INS_LHX,
5088 #ifndef CAPSTONE_DIET
5089  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
5090 #endif
5091 },
5092 {
5093  Mips_LH_MM, MIPS_INS_LH,
5094 #ifndef CAPSTONE_DIET
5095  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5096 #endif
5097 },
5098 {
5099  Mips_LHu, MIPS_INS_LHU,
5100 #ifndef CAPSTONE_DIET
5101  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
5102 #endif
5103 },
5104 {
5105  Mips_LHu64, MIPS_INS_LHU,
5106 #ifndef CAPSTONE_DIET
5107  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
5108 #endif
5109 },
5110 {
5111  Mips_LHu_MM, MIPS_INS_LHU,
5112 #ifndef CAPSTONE_DIET
5113  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5114 #endif
5115 },
5116 {
5117  Mips_LI16_MM, MIPS_INS_LI16,
5118 #ifndef CAPSTONE_DIET
5119  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5120 #endif
5121 },
5122 {
5123  Mips_LL, MIPS_INS_LL,
5124 #ifndef CAPSTONE_DIET
5125  { 0 }, { 0 }, { MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
5126 #endif
5127 },
5128 {
5129  Mips_LLD, MIPS_INS_LLD,
5130 #ifndef CAPSTONE_DIET
5131  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
5132 #endif
5133 },
5134 {
5135  Mips_LLD_R6, MIPS_INS_LLD,
5136 #ifndef CAPSTONE_DIET
5137  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5138 #endif
5139 },
5140 {
5141  Mips_LL_MM, MIPS_INS_LL,
5142 #ifndef CAPSTONE_DIET
5143  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5144 #endif
5145 },
5146 {
5147  Mips_LL_R6, MIPS_INS_LL,
5148 #ifndef CAPSTONE_DIET
5149  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5150 #endif
5151 },
5152 {
5153  Mips_LSA, MIPS_INS_LSA,
5154 #ifndef CAPSTONE_DIET
5155  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5156 #endif
5157 },
5158 {
5159  Mips_LSA_R6, MIPS_INS_LSA,
5160 #ifndef CAPSTONE_DIET
5161  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5162 #endif
5163 },
5164 {
5165  Mips_LUXC1, MIPS_INS_LUXC1,
5166 #ifndef CAPSTONE_DIET
5167  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0
5168 #endif
5169 },
5170 {
5171  Mips_LUXC164, MIPS_INS_LUXC1,
5172 #ifndef CAPSTONE_DIET
5173  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
5174 #endif
5175 },
5176 {
5177  Mips_LUXC1_MM, MIPS_INS_LUXC1,
5178 #ifndef CAPSTONE_DIET
5179  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5180 #endif
5181 },
5182 {
5183  Mips_LUi, MIPS_INS_LUI,
5184 #ifndef CAPSTONE_DIET
5185  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
5186 #endif
5187 },
5188 {
5189  Mips_LUi64, MIPS_INS_LUI,
5190 #ifndef CAPSTONE_DIET
5191  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
5192 #endif
5193 },
5194 {
5195  Mips_LUi_MM, MIPS_INS_LUI,
5196 #ifndef CAPSTONE_DIET
5197  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5198 #endif
5199 },
5200 {
5201  Mips_LW, MIPS_INS_LW,
5202 #ifndef CAPSTONE_DIET
5203  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
5204 #endif
5205 },
5206 {
5207  Mips_LW16_MM, MIPS_INS_LW16,
5208 #ifndef CAPSTONE_DIET
5209  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5210 #endif
5211 },
5212 {
5213  Mips_LW64, MIPS_INS_LW,
5214 #ifndef CAPSTONE_DIET
5215  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
5216 #endif
5217 },
5218 {
5219  Mips_LWC1, MIPS_INS_LWC1,
5220 #ifndef CAPSTONE_DIET
5221  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
5222 #endif
5223 },
5224 {
5225  Mips_LWC1_MM, MIPS_INS_LWC1,
5226 #ifndef CAPSTONE_DIET
5227  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5228 #endif
5229 },
5230 {
5231  Mips_LWC2, MIPS_INS_LWC2,
5232 #ifndef CAPSTONE_DIET
5233  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
5234 #endif
5235 },
5236 {
5237  Mips_LWC2_R6, MIPS_INS_LWC2,
5238 #ifndef CAPSTONE_DIET
5239  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5240 #endif
5241 },
5242 {
5243  Mips_LWC3, MIPS_INS_LWC3,
5244 #ifndef CAPSTONE_DIET
5245  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
5246 #endif
5247 },
5248 {
5249  Mips_LWGP_MM, MIPS_INS_LW,
5250 #ifndef CAPSTONE_DIET
5251  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5252 #endif
5253 },
5254 {
5255  Mips_LWL, MIPS_INS_LWL,
5256 #ifndef CAPSTONE_DIET
5257  { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
5258 #endif
5259 },
5260 {
5261  Mips_LWL64, MIPS_INS_LWL,
5262 #ifndef CAPSTONE_DIET
5263  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
5264 #endif
5265 },
5266 {
5267  Mips_LWL_MM, MIPS_INS_LWL,
5268 #ifndef CAPSTONE_DIET
5269  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5270 #endif
5271 },
5272 {
5273  Mips_LWM16_MM, MIPS_INS_LWM16,
5274 #ifndef CAPSTONE_DIET
5275  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5276 #endif
5277 },
5278 {
5279  Mips_LWM32_MM, MIPS_INS_LWM32,
5280 #ifndef CAPSTONE_DIET
5281  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5282 #endif
5283 },
5284 {
5285  Mips_LWPC, MIPS_INS_LWPC,
5286 #ifndef CAPSTONE_DIET
5287  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5288 #endif
5289 },
5290 {
5291  Mips_LWP_MM, MIPS_INS_LWP,
5292 #ifndef CAPSTONE_DIET
5293  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5294 #endif
5295 },
5296 {
5297  Mips_LWR, MIPS_INS_LWR,
5298 #ifndef CAPSTONE_DIET
5299  { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
5300 #endif
5301 },
5302 {
5303  Mips_LWR64, MIPS_INS_LWR,
5304 #ifndef CAPSTONE_DIET
5305  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
5306 #endif
5307 },
5308 {
5309  Mips_LWR_MM, MIPS_INS_LWR,
5310 #ifndef CAPSTONE_DIET
5311  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5312 #endif
5313 },
5314 {
5315  Mips_LWSP_MM, MIPS_INS_LW,
5316 #ifndef CAPSTONE_DIET
5317  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5318 #endif
5319 },
5320 {
5321  Mips_LWUPC, MIPS_INS_LWUPC,
5322 #ifndef CAPSTONE_DIET
5323  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5324 #endif
5325 },
5326 {
5327  Mips_LWU_MM, MIPS_INS_LWU,
5328 #ifndef CAPSTONE_DIET
5329  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5330 #endif
5331 },
5332 {
5333  Mips_LWX, MIPS_INS_LWX,
5334 #ifndef CAPSTONE_DIET
5335  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
5336 #endif
5337 },
5338 {
5339  Mips_LWXC1, MIPS_INS_LWXC1,
5340 #ifndef CAPSTONE_DIET
5341  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0
5342 #endif
5343 },
5344 {
5345  Mips_LWXC1_MM, MIPS_INS_LWXC1,
5346 #ifndef CAPSTONE_DIET
5347  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5348 #endif
5349 },
5350 {
5351  Mips_LWXS_MM, MIPS_INS_LWXS,
5352 #ifndef CAPSTONE_DIET
5353  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5354 #endif
5355 },
5356 {
5357  Mips_LW_MM, MIPS_INS_LW,
5358 #ifndef CAPSTONE_DIET
5359  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5360 #endif
5361 },
5362 {
5363  Mips_LWu, MIPS_INS_LWU,
5364 #ifndef CAPSTONE_DIET
5365  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
5366 #endif
5367 },
5368 {
5369  Mips_LbRxRyOffMemX16, MIPS_INS_LB,
5370 #ifndef CAPSTONE_DIET
5371  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
5372 #endif
5373 },
5374 {
5375  Mips_LbuRxRyOffMemX16, MIPS_INS_LBU,
5376 #ifndef CAPSTONE_DIET
5377  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
5378 #endif
5379 },
5380 {
5381  Mips_LhRxRyOffMemX16, MIPS_INS_LH,
5382 #ifndef CAPSTONE_DIET
5383  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
5384 #endif
5385 },
5386 {
5387  Mips_LhuRxRyOffMemX16, MIPS_INS_LHU,
5388 #ifndef CAPSTONE_DIET
5389  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
5390 #endif
5391 },
5392 {
5393  Mips_LiRxImm16, MIPS_INS_LI,
5394 #ifndef CAPSTONE_DIET
5395  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
5396 #endif
5397 },
5398 {
5399  Mips_LiRxImmX16, MIPS_INS_LI,
5400 #ifndef CAPSTONE_DIET
5401  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
5402 #endif
5403 },
5404 {
5405  Mips_LwRxPcTcp16, MIPS_INS_LW,
5406 #ifndef CAPSTONE_DIET
5407  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
5408 #endif
5409 },
5410 {
5411  Mips_LwRxPcTcpX16, MIPS_INS_LW,
5412 #ifndef CAPSTONE_DIET
5413  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
5414 #endif
5415 },
5416 {
5417  Mips_LwRxRyOffMemX16, MIPS_INS_LW,
5418 #ifndef CAPSTONE_DIET
5419  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
5420 #endif
5421 },
5422 {
5423  Mips_LwRxSpImmX16, MIPS_INS_LW,
5424 #ifndef CAPSTONE_DIET
5425  { MIPS_REG_SP, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
5426 #endif
5427 },
5428 {
5429  Mips_MADD, MIPS_INS_MADD,
5430 #ifndef CAPSTONE_DIET
5431  { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
5432 #endif
5433 },
5434 {
5435  Mips_MADDF_D, MIPS_INS_MADDF,
5436 #ifndef CAPSTONE_DIET
5437  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5438 #endif
5439 },
5440 {
5441  Mips_MADDF_S, MIPS_INS_MADDF,
5442 #ifndef CAPSTONE_DIET
5443  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5444 #endif
5445 },
5446 {
5447  Mips_MADDR_Q_H, MIPS_INS_MADDR_Q,
5448 #ifndef CAPSTONE_DIET
5449  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5450 #endif
5451 },
5452 {
5453  Mips_MADDR_Q_W, MIPS_INS_MADDR_Q,
5454 #ifndef CAPSTONE_DIET
5455  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5456 #endif
5457 },
5458 {
5459  Mips_MADDU, MIPS_INS_MADDU,
5460 #ifndef CAPSTONE_DIET
5461  { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
5462 #endif
5463 },
5464 {
5465  Mips_MADDU_DSP, MIPS_INS_MADDU,
5466 #ifndef CAPSTONE_DIET
5467  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
5468 #endif
5469 },
5470 {
5471  Mips_MADDU_MM, MIPS_INS_MADDU,
5472 #ifndef CAPSTONE_DIET
5473  { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5474 #endif
5475 },
5476 {
5477  Mips_MADDV_B, MIPS_INS_MADDV,
5478 #ifndef CAPSTONE_DIET
5479  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5480 #endif
5481 },
5482 {
5483  Mips_MADDV_D, MIPS_INS_MADDV,
5484 #ifndef CAPSTONE_DIET
5485  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5486 #endif
5487 },
5488 {
5489  Mips_MADDV_H, MIPS_INS_MADDV,
5490 #ifndef CAPSTONE_DIET
5491  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5492 #endif
5493 },
5494 {
5495  Mips_MADDV_W, MIPS_INS_MADDV,
5496 #ifndef CAPSTONE_DIET
5497  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5498 #endif
5499 },
5500 {
5501  Mips_MADD_D32, MIPS_INS_MADD,
5502 #ifndef CAPSTONE_DIET
5503  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
5504 #endif
5505 },
5506 {
5507  Mips_MADD_D32_MM, MIPS_INS_MADD,
5508 #ifndef CAPSTONE_DIET
5509  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5510 #endif
5511 },
5512 {
5513  Mips_MADD_D64, MIPS_INS_MADD,
5514 #ifndef CAPSTONE_DIET
5515  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
5516 #endif
5517 },
5518 {
5519  Mips_MADD_DSP, MIPS_INS_MADD,
5520 #ifndef CAPSTONE_DIET
5521  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
5522 #endif
5523 },
5524 {
5525  Mips_MADD_MM, MIPS_INS_MADD,
5526 #ifndef CAPSTONE_DIET
5527  { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5528 #endif
5529 },
5530 {
5531  Mips_MADD_Q_H, MIPS_INS_MADD_Q,
5532 #ifndef CAPSTONE_DIET
5533  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5534 #endif
5535 },
5536 {
5537  Mips_MADD_Q_W, MIPS_INS_MADD_Q,
5538 #ifndef CAPSTONE_DIET
5539  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5540 #endif
5541 },
5542 {
5543  Mips_MADD_S, MIPS_INS_MADD,
5544 #ifndef CAPSTONE_DIET
5545  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
5546 #endif
5547 },
5548 {
5549  Mips_MADD_S_MM, MIPS_INS_MADD,
5550 #ifndef CAPSTONE_DIET
5551  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5552 #endif
5553 },
5554 {
5555  Mips_MAQ_SA_W_PHL, MIPS_INS_MAQ_SA,
5556 #ifndef CAPSTONE_DIET
5557  { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
5558 #endif
5559 },
5560 {
5561  Mips_MAQ_SA_W_PHR, MIPS_INS_MAQ_SA,
5562 #ifndef CAPSTONE_DIET
5563  { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
5564 #endif
5565 },
5566 {
5567  Mips_MAQ_S_W_PHL, MIPS_INS_MAQ_S,
5568 #ifndef CAPSTONE_DIET
5569  { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
5570 #endif
5571 },
5572 {
5573  Mips_MAQ_S_W_PHR, MIPS_INS_MAQ_S,
5574 #ifndef CAPSTONE_DIET
5575  { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
5576 #endif
5577 },
5578 {
5579  Mips_MAXA_D, MIPS_INS_MAXA,
5580 #ifndef CAPSTONE_DIET
5581  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5582 #endif
5583 },
5584 {
5585  Mips_MAXA_S, MIPS_INS_MAXA,
5586 #ifndef CAPSTONE_DIET
5587  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5588 #endif
5589 },
5590 {
5591  Mips_MAXI_S_B, MIPS_INS_MAXI_S,
5592 #ifndef CAPSTONE_DIET
5593  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5594 #endif
5595 },
5596 {
5597  Mips_MAXI_S_D, MIPS_INS_MAXI_S,
5598 #ifndef CAPSTONE_DIET
5599  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5600 #endif
5601 },
5602 {
5603  Mips_MAXI_S_H, MIPS_INS_MAXI_S,
5604 #ifndef CAPSTONE_DIET
5605  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5606 #endif
5607 },
5608 {
5609  Mips_MAXI_S_W, MIPS_INS_MAXI_S,
5610 #ifndef CAPSTONE_DIET
5611  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5612 #endif
5613 },
5614 {
5615  Mips_MAXI_U_B, MIPS_INS_MAXI_U,
5616 #ifndef CAPSTONE_DIET
5617  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5618 #endif
5619 },
5620 {
5621  Mips_MAXI_U_D, MIPS_INS_MAXI_U,
5622 #ifndef CAPSTONE_DIET
5623  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5624 #endif
5625 },
5626 {
5627  Mips_MAXI_U_H, MIPS_INS_MAXI_U,
5628 #ifndef CAPSTONE_DIET
5629  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5630 #endif
5631 },
5632 {
5633  Mips_MAXI_U_W, MIPS_INS_MAXI_U,
5634 #ifndef CAPSTONE_DIET
5635  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5636 #endif
5637 },
5638 {
5639  Mips_MAX_A_B, MIPS_INS_MAX_A,
5640 #ifndef CAPSTONE_DIET
5641  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5642 #endif
5643 },
5644 {
5645  Mips_MAX_A_D, MIPS_INS_MAX_A,
5646 #ifndef CAPSTONE_DIET
5647  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5648 #endif
5649 },
5650 {
5651  Mips_MAX_A_H, MIPS_INS_MAX_A,
5652 #ifndef CAPSTONE_DIET
5653  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5654 #endif
5655 },
5656 {
5657  Mips_MAX_A_W, MIPS_INS_MAX_A,
5658 #ifndef CAPSTONE_DIET
5659  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5660 #endif
5661 },
5662 {
5663  Mips_MAX_D, MIPS_INS_MAX,
5664 #ifndef CAPSTONE_DIET
5665  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5666 #endif
5667 },
5668 {
5669  Mips_MAX_S, MIPS_INS_MAX,
5670 #ifndef CAPSTONE_DIET
5671  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5672 #endif
5673 },
5674 {
5675  Mips_MAX_S_B, MIPS_INS_MAX_S,
5676 #ifndef CAPSTONE_DIET
5677  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5678 #endif
5679 },
5680 {
5681  Mips_MAX_S_D, MIPS_INS_MAX_S,
5682 #ifndef CAPSTONE_DIET
5683  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5684 #endif
5685 },
5686 {
5687  Mips_MAX_S_H, MIPS_INS_MAX_S,
5688 #ifndef CAPSTONE_DIET
5689  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5690 #endif
5691 },
5692 {
5693  Mips_MAX_S_W, MIPS_INS_MAX_S,
5694 #ifndef CAPSTONE_DIET
5695  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5696 #endif
5697 },
5698 {
5699  Mips_MAX_U_B, MIPS_INS_MAX_U,
5700 #ifndef CAPSTONE_DIET
5701  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5702 #endif
5703 },
5704 {
5705  Mips_MAX_U_D, MIPS_INS_MAX_U,
5706 #ifndef CAPSTONE_DIET
5707  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5708 #endif
5709 },
5710 {
5711  Mips_MAX_U_H, MIPS_INS_MAX_U,
5712 #ifndef CAPSTONE_DIET
5713  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5714 #endif
5715 },
5716 {
5717  Mips_MAX_U_W, MIPS_INS_MAX_U,
5718 #ifndef CAPSTONE_DIET
5719  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5720 #endif
5721 },
5722 {
5723  Mips_MFC0, MIPS_INS_MFC0,
5724 #ifndef CAPSTONE_DIET
5725  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0
5726 #endif
5727 },
5728 {
5729  Mips_MFC1, MIPS_INS_MFC1,
5730 #ifndef CAPSTONE_DIET
5731  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
5732 #endif
5733 },
5734 {
5735  Mips_MFC1_MM, MIPS_INS_MFC1,
5736 #ifndef CAPSTONE_DIET
5737  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5738 #endif
5739 },
5740 {
5741  Mips_MFC2, MIPS_INS_MFC2,
5742 #ifndef CAPSTONE_DIET
5743  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
5744 #endif
5745 },
5746 {
5747  Mips_MFHC1_D32, MIPS_INS_MFHC1,
5748 #ifndef CAPSTONE_DIET
5749  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
5750 #endif
5751 },
5752 {
5753  Mips_MFHC1_D64, MIPS_INS_MFHC1,
5754 #ifndef CAPSTONE_DIET
5755  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_FP64BIT, 0 }, 0, 0
5756 #endif
5757 },
5758 {
5759  Mips_MFHC1_MM, MIPS_INS_MFHC1,
5760 #ifndef CAPSTONE_DIET
5761  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5762 #endif
5763 },
5764 {
5765  Mips_MFHI, MIPS_INS_MFHI,
5766 #ifndef CAPSTONE_DIET
5767  { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
5768 #endif
5769 },
5770 {
5771  Mips_MFHI16_MM, MIPS_INS_MFHI,
5772 #ifndef CAPSTONE_DIET
5773  { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5774 #endif
5775 },
5776 {
5777  Mips_MFHI64, MIPS_INS_MFHI,
5778 #ifndef CAPSTONE_DIET
5779  { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
5780 #endif
5781 },
5782 {
5783  Mips_MFHI_DSP, MIPS_INS_MFHI,
5784 #ifndef CAPSTONE_DIET
5785  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
5786 #endif
5787 },
5788 {
5789  Mips_MFHI_MM, MIPS_INS_MFHI,
5790 #ifndef CAPSTONE_DIET
5791  { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5792 #endif
5793 },
5794 {
5795  Mips_MFLO, MIPS_INS_MFLO,
5796 #ifndef CAPSTONE_DIET
5797  { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
5798 #endif
5799 },
5800 {
5801  Mips_MFLO16_MM, MIPS_INS_MFLO,
5802 #ifndef CAPSTONE_DIET
5803  { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5804 #endif
5805 },
5806 {
5807  Mips_MFLO64, MIPS_INS_MFLO,
5808 #ifndef CAPSTONE_DIET
5809  { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
5810 #endif
5811 },
5812 {
5813  Mips_MFLO_DSP, MIPS_INS_MFLO,
5814 #ifndef CAPSTONE_DIET
5815  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
5816 #endif
5817 },
5818 {
5819  Mips_MFLO_MM, MIPS_INS_MFLO,
5820 #ifndef CAPSTONE_DIET
5821  { MIPS_REG_AC0, 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
5822 #endif
5823 },
5824 {
5825  Mips_MINA_D, MIPS_INS_MINA,
5826 #ifndef CAPSTONE_DIET
5827  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5828 #endif
5829 },
5830 {
5831  Mips_MINA_S, MIPS_INS_MINA,
5832 #ifndef CAPSTONE_DIET
5833  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5834 #endif
5835 },
5836 {
5837  Mips_MINI_S_B, MIPS_INS_MINI_S,
5838 #ifndef CAPSTONE_DIET
5839  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5840 #endif
5841 },
5842 {
5843  Mips_MINI_S_D, MIPS_INS_MINI_S,
5844 #ifndef CAPSTONE_DIET
5845  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5846 #endif
5847 },
5848 {
5849  Mips_MINI_S_H, MIPS_INS_MINI_S,
5850 #ifndef CAPSTONE_DIET
5851  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5852 #endif
5853 },
5854 {
5855  Mips_MINI_S_W, MIPS_INS_MINI_S,
5856 #ifndef CAPSTONE_DIET
5857  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5858 #endif
5859 },
5860 {
5861  Mips_MINI_U_B, MIPS_INS_MINI_U,
5862 #ifndef CAPSTONE_DIET
5863  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5864 #endif
5865 },
5866 {
5867  Mips_MINI_U_D, MIPS_INS_MINI_U,
5868 #ifndef CAPSTONE_DIET
5869  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5870 #endif
5871 },
5872 {
5873  Mips_MINI_U_H, MIPS_INS_MINI_U,
5874 #ifndef CAPSTONE_DIET
5875  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5876 #endif
5877 },
5878 {
5879  Mips_MINI_U_W, MIPS_INS_MINI_U,
5880 #ifndef CAPSTONE_DIET
5881  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5882 #endif
5883 },
5884 {
5885  Mips_MIN_A_B, MIPS_INS_MIN_A,
5886 #ifndef CAPSTONE_DIET
5887  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5888 #endif
5889 },
5890 {
5891  Mips_MIN_A_D, MIPS_INS_MIN_A,
5892 #ifndef CAPSTONE_DIET
5893  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5894 #endif
5895 },
5896 {
5897  Mips_MIN_A_H, MIPS_INS_MIN_A,
5898 #ifndef CAPSTONE_DIET
5899  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5900 #endif
5901 },
5902 {
5903  Mips_MIN_A_W, MIPS_INS_MIN_A,
5904 #ifndef CAPSTONE_DIET
5905  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5906 #endif
5907 },
5908 {
5909  Mips_MIN_D, MIPS_INS_MIN,
5910 #ifndef CAPSTONE_DIET
5911  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5912 #endif
5913 },
5914 {
5915  Mips_MIN_S, MIPS_INS_MIN,
5916 #ifndef CAPSTONE_DIET
5917  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5918 #endif
5919 },
5920 {
5921  Mips_MIN_S_B, MIPS_INS_MIN_S,
5922 #ifndef CAPSTONE_DIET
5923  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5924 #endif
5925 },
5926 {
5927  Mips_MIN_S_D, MIPS_INS_MIN_S,
5928 #ifndef CAPSTONE_DIET
5929  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5930 #endif
5931 },
5932 {
5933  Mips_MIN_S_H, MIPS_INS_MIN_S,
5934 #ifndef CAPSTONE_DIET
5935  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5936 #endif
5937 },
5938 {
5939  Mips_MIN_S_W, MIPS_INS_MIN_S,
5940 #ifndef CAPSTONE_DIET
5941  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5942 #endif
5943 },
5944 {
5945  Mips_MIN_U_B, MIPS_INS_MIN_U,
5946 #ifndef CAPSTONE_DIET
5947  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5948 #endif
5949 },
5950 {
5951  Mips_MIN_U_D, MIPS_INS_MIN_U,
5952 #ifndef CAPSTONE_DIET
5953  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5954 #endif
5955 },
5956 {
5957  Mips_MIN_U_H, MIPS_INS_MIN_U,
5958 #ifndef CAPSTONE_DIET
5959  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5960 #endif
5961 },
5962 {
5963  Mips_MIN_U_W, MIPS_INS_MIN_U,
5964 #ifndef CAPSTONE_DIET
5965  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5966 #endif
5967 },
5968 {
5969  Mips_MOD, MIPS_INS_MOD,
5970 #ifndef CAPSTONE_DIET
5971  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5972 #endif
5973 },
5974 {
5975  Mips_MODSUB, MIPS_INS_MODSUB,
5976 #ifndef CAPSTONE_DIET
5977  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
5978 #endif
5979 },
5980 {
5981  Mips_MODU, MIPS_INS_MODU,
5982 #ifndef CAPSTONE_DIET
5983  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
5984 #endif
5985 },
5986 {
5987  Mips_MOD_S_B, MIPS_INS_MOD_S,
5988 #ifndef CAPSTONE_DIET
5989  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5990 #endif
5991 },
5992 {
5993  Mips_MOD_S_D, MIPS_INS_MOD_S,
5994 #ifndef CAPSTONE_DIET
5995  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
5996 #endif
5997 },
5998 {
5999  Mips_MOD_S_H, MIPS_INS_MOD_S,
6000 #ifndef CAPSTONE_DIET
6001  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6002 #endif
6003 },
6004 {
6005  Mips_MOD_S_W, MIPS_INS_MOD_S,
6006 #ifndef CAPSTONE_DIET
6007  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6008 #endif
6009 },
6010 {
6011  Mips_MOD_U_B, MIPS_INS_MOD_U,
6012 #ifndef CAPSTONE_DIET
6013  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6014 #endif
6015 },
6016 {
6017  Mips_MOD_U_D, MIPS_INS_MOD_U,
6018 #ifndef CAPSTONE_DIET
6019  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6020 #endif
6021 },
6022 {
6023  Mips_MOD_U_H, MIPS_INS_MOD_U,
6024 #ifndef CAPSTONE_DIET
6025  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6026 #endif
6027 },
6028 {
6029  Mips_MOD_U_W, MIPS_INS_MOD_U,
6030 #ifndef CAPSTONE_DIET
6031  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6032 #endif
6033 },
6034 {
6035  Mips_MOVE16_MM, MIPS_INS_MOVE,
6036 #ifndef CAPSTONE_DIET
6037  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6038 #endif
6039 },
6040 {
6041  Mips_MOVEP_MM, MIPS_INS_MOVEP,
6042 #ifndef CAPSTONE_DIET
6043  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6044 #endif
6045 },
6046 {
6047  Mips_MOVE_V, MIPS_INS_MOVE,
6048 #ifndef CAPSTONE_DIET
6049  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6050 #endif
6051 },
6052 {
6053  Mips_MOVF_D32, MIPS_INS_MOVF,
6054 #ifndef CAPSTONE_DIET
6055  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6056 #endif
6057 },
6058 {
6059  Mips_MOVF_D32_MM, MIPS_INS_MOVF,
6060 #ifndef CAPSTONE_DIET
6061  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6062 #endif
6063 },
6064 {
6065  Mips_MOVF_D64, MIPS_INS_MOVF,
6066 #ifndef CAPSTONE_DIET
6067  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6068 #endif
6069 },
6070 {
6071  Mips_MOVF_I, MIPS_INS_MOVF,
6072 #ifndef CAPSTONE_DIET
6073  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6074 #endif
6075 },
6076 {
6077  Mips_MOVF_I64, MIPS_INS_MOVF,
6078 #ifndef CAPSTONE_DIET
6079  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_GP64BIT, 0 }, 0, 0
6080 #endif
6081 },
6082 {
6083  Mips_MOVF_I_MM, MIPS_INS_MOVF,
6084 #ifndef CAPSTONE_DIET
6085  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6086 #endif
6087 },
6088 {
6089  Mips_MOVF_S, MIPS_INS_MOVF,
6090 #ifndef CAPSTONE_DIET
6091  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6092 #endif
6093 },
6094 {
6095  Mips_MOVF_S_MM, MIPS_INS_MOVF,
6096 #ifndef CAPSTONE_DIET
6097  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6098 #endif
6099 },
6100 {
6101  Mips_MOVN_I64_D64, MIPS_INS_MOVN,
6102 #ifndef CAPSTONE_DIET
6103  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6104 #endif
6105 },
6106 {
6107  Mips_MOVN_I64_I, MIPS_INS_MOVN,
6108 #ifndef CAPSTONE_DIET
6109  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6110 #endif
6111 },
6112 {
6113  Mips_MOVN_I64_I64, MIPS_INS_MOVN,
6114 #ifndef CAPSTONE_DIET
6115  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6116 #endif
6117 },
6118 {
6119  Mips_MOVN_I64_S, MIPS_INS_MOVN,
6120 #ifndef CAPSTONE_DIET
6121  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_GP64BIT, 0 }, 0, 0
6122 #endif
6123 },
6124 {
6125  Mips_MOVN_I_D32, MIPS_INS_MOVN,
6126 #ifndef CAPSTONE_DIET
6127  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6128 #endif
6129 },
6130 {
6131  Mips_MOVN_I_D32_MM, MIPS_INS_MOVN,
6132 #ifndef CAPSTONE_DIET
6133  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6134 #endif
6135 },
6136 {
6137  Mips_MOVN_I_D64, MIPS_INS_MOVN,
6138 #ifndef CAPSTONE_DIET
6139  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6140 #endif
6141 },
6142 {
6143  Mips_MOVN_I_I, MIPS_INS_MOVN,
6144 #ifndef CAPSTONE_DIET
6145  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6146 #endif
6147 },
6148 {
6149  Mips_MOVN_I_I64, MIPS_INS_MOVN,
6150 #ifndef CAPSTONE_DIET
6151  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6152 #endif
6153 },
6154 {
6155  Mips_MOVN_I_MM, MIPS_INS_MOVN,
6156 #ifndef CAPSTONE_DIET
6157  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6158 #endif
6159 },
6160 {
6161  Mips_MOVN_I_S, MIPS_INS_MOVN,
6162 #ifndef CAPSTONE_DIET
6163  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6164 #endif
6165 },
6166 {
6167  Mips_MOVN_I_S_MM, MIPS_INS_MOVN,
6168 #ifndef CAPSTONE_DIET
6169  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6170 #endif
6171 },
6172 {
6173  Mips_MOVT_D32, MIPS_INS_MOVT,
6174 #ifndef CAPSTONE_DIET
6175  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6176 #endif
6177 },
6178 {
6179  Mips_MOVT_D32_MM, MIPS_INS_MOVT,
6180 #ifndef CAPSTONE_DIET
6181  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6182 #endif
6183 },
6184 {
6185  Mips_MOVT_D64, MIPS_INS_MOVT,
6186 #ifndef CAPSTONE_DIET
6187  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6188 #endif
6189 },
6190 {
6191  Mips_MOVT_I, MIPS_INS_MOVT,
6192 #ifndef CAPSTONE_DIET
6193  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6194 #endif
6195 },
6196 {
6197  Mips_MOVT_I64, MIPS_INS_MOVT,
6198 #ifndef CAPSTONE_DIET
6199  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_GP64BIT, 0 }, 0, 0
6200 #endif
6201 },
6202 {
6203  Mips_MOVT_I_MM, MIPS_INS_MOVT,
6204 #ifndef CAPSTONE_DIET
6205  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6206 #endif
6207 },
6208 {
6209  Mips_MOVT_S, MIPS_INS_MOVT,
6210 #ifndef CAPSTONE_DIET
6211  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6212 #endif
6213 },
6214 {
6215  Mips_MOVT_S_MM, MIPS_INS_MOVT,
6216 #ifndef CAPSTONE_DIET
6217  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6218 #endif
6219 },
6220 {
6221  Mips_MOVZ_I64_D64, MIPS_INS_MOVZ,
6222 #ifndef CAPSTONE_DIET
6223  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6224 #endif
6225 },
6226 {
6227  Mips_MOVZ_I64_I, MIPS_INS_MOVZ,
6228 #ifndef CAPSTONE_DIET
6229  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6230 #endif
6231 },
6232 {
6233  Mips_MOVZ_I64_I64, MIPS_INS_MOVZ,
6234 #ifndef CAPSTONE_DIET
6235  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6236 #endif
6237 },
6238 {
6239  Mips_MOVZ_I64_S, MIPS_INS_MOVZ,
6240 #ifndef CAPSTONE_DIET
6241  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_MIPS64, 0 }, 0, 0
6242 #endif
6243 },
6244 {
6245  Mips_MOVZ_I_D32, MIPS_INS_MOVZ,
6246 #ifndef CAPSTONE_DIET
6247  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6248 #endif
6249 },
6250 {
6251  Mips_MOVZ_I_D32_MM, MIPS_INS_MOVZ,
6252 #ifndef CAPSTONE_DIET
6253  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6254 #endif
6255 },
6256 {
6257  Mips_MOVZ_I_D64, MIPS_INS_MOVZ,
6258 #ifndef CAPSTONE_DIET
6259  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6260 #endif
6261 },
6262 {
6263  Mips_MOVZ_I_I, MIPS_INS_MOVZ,
6264 #ifndef CAPSTONE_DIET
6265  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6266 #endif
6267 },
6268 {
6269  Mips_MOVZ_I_I64, MIPS_INS_MOVZ,
6270 #ifndef CAPSTONE_DIET
6271  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6272 #endif
6273 },
6274 {
6275  Mips_MOVZ_I_MM, MIPS_INS_MOVZ,
6276 #ifndef CAPSTONE_DIET
6277  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6278 #endif
6279 },
6280 {
6281  Mips_MOVZ_I_S, MIPS_INS_MOVZ,
6282 #ifndef CAPSTONE_DIET
6283  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6284 #endif
6285 },
6286 {
6287  Mips_MOVZ_I_S_MM, MIPS_INS_MOVZ,
6288 #ifndef CAPSTONE_DIET
6289  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6290 #endif
6291 },
6292 {
6293  Mips_MSUB, MIPS_INS_MSUB,
6294 #ifndef CAPSTONE_DIET
6295  { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6296 #endif
6297 },
6298 {
6299  Mips_MSUBF_D, MIPS_INS_MSUBF,
6300 #ifndef CAPSTONE_DIET
6301  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
6302 #endif
6303 },
6304 {
6305  Mips_MSUBF_S, MIPS_INS_MSUBF,
6306 #ifndef CAPSTONE_DIET
6307  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
6308 #endif
6309 },
6310 {
6311  Mips_MSUBR_Q_H, MIPS_INS_MSUBR_Q,
6312 #ifndef CAPSTONE_DIET
6313  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6314 #endif
6315 },
6316 {
6317  Mips_MSUBR_Q_W, MIPS_INS_MSUBR_Q,
6318 #ifndef CAPSTONE_DIET
6319  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6320 #endif
6321 },
6322 {
6323  Mips_MSUBU, MIPS_INS_MSUBU,
6324 #ifndef CAPSTONE_DIET
6325  { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6326 #endif
6327 },
6328 {
6329  Mips_MSUBU_DSP, MIPS_INS_MSUBU,
6330 #ifndef CAPSTONE_DIET
6331  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
6332 #endif
6333 },
6334 {
6335  Mips_MSUBU_MM, MIPS_INS_MSUBU,
6336 #ifndef CAPSTONE_DIET
6337  { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6338 #endif
6339 },
6340 {
6341  Mips_MSUBV_B, MIPS_INS_MSUBV,
6342 #ifndef CAPSTONE_DIET
6343  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6344 #endif
6345 },
6346 {
6347  Mips_MSUBV_D, MIPS_INS_MSUBV,
6348 #ifndef CAPSTONE_DIET
6349  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6350 #endif
6351 },
6352 {
6353  Mips_MSUBV_H, MIPS_INS_MSUBV,
6354 #ifndef CAPSTONE_DIET
6355  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6356 #endif
6357 },
6358 {
6359  Mips_MSUBV_W, MIPS_INS_MSUBV,
6360 #ifndef CAPSTONE_DIET
6361  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6362 #endif
6363 },
6364 {
6365  Mips_MSUB_D32, MIPS_INS_MSUB,
6366 #ifndef CAPSTONE_DIET
6367  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6368 #endif
6369 },
6370 {
6371  Mips_MSUB_D32_MM, MIPS_INS_MSUB,
6372 #ifndef CAPSTONE_DIET
6373  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6374 #endif
6375 },
6376 {
6377  Mips_MSUB_D64, MIPS_INS_MSUB,
6378 #ifndef CAPSTONE_DIET
6379  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6380 #endif
6381 },
6382 {
6383  Mips_MSUB_DSP, MIPS_INS_MSUB,
6384 #ifndef CAPSTONE_DIET
6385  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
6386 #endif
6387 },
6388 {
6389  Mips_MSUB_MM, MIPS_INS_MSUB,
6390 #ifndef CAPSTONE_DIET
6391  { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6392 #endif
6393 },
6394 {
6395  Mips_MSUB_Q_H, MIPS_INS_MSUB_Q,
6396 #ifndef CAPSTONE_DIET
6397  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6398 #endif
6399 },
6400 {
6401  Mips_MSUB_Q_W, MIPS_INS_MSUB_Q,
6402 #ifndef CAPSTONE_DIET
6403  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6404 #endif
6405 },
6406 {
6407  Mips_MSUB_S, MIPS_INS_MSUB,
6408 #ifndef CAPSTONE_DIET
6409  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6410 #endif
6411 },
6412 {
6413  Mips_MSUB_S_MM, MIPS_INS_MSUB,
6414 #ifndef CAPSTONE_DIET
6415  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6416 #endif
6417 },
6418 {
6419  Mips_MTC0, MIPS_INS_MTC0,
6420 #ifndef CAPSTONE_DIET
6421  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0
6422 #endif
6423 },
6424 {
6425  Mips_MTC1, MIPS_INS_MTC1,
6426 #ifndef CAPSTONE_DIET
6427  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
6428 #endif
6429 },
6430 {
6431  Mips_MTC1_MM, MIPS_INS_MTC1,
6432 #ifndef CAPSTONE_DIET
6433  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6434 #endif
6435 },
6436 {
6437  Mips_MTC2, MIPS_INS_MTC2,
6438 #ifndef CAPSTONE_DIET
6439  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
6440 #endif
6441 },
6442 {
6443  Mips_MTHC1_D32, MIPS_INS_MTHC1,
6444 #ifndef CAPSTONE_DIET
6445  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
6446 #endif
6447 },
6448 {
6449  Mips_MTHC1_D64, MIPS_INS_MTHC1,
6450 #ifndef CAPSTONE_DIET
6451  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, MIPS_GRP_FP64BIT, 0 }, 0, 0
6452 #endif
6453 },
6454 {
6455  Mips_MTHC1_MM, MIPS_INS_MTHC1,
6456 #ifndef CAPSTONE_DIET
6457  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6458 #endif
6459 },
6460 {
6461  Mips_MTHI, MIPS_INS_MTHI,
6462 #ifndef CAPSTONE_DIET
6463  { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6464 #endif
6465 },
6466 {
6467  Mips_MTHI64, MIPS_INS_MTHI,
6468 #ifndef CAPSTONE_DIET
6469  { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6470 #endif
6471 },
6472 {
6473  Mips_MTHI_DSP, MIPS_INS_MTHI,
6474 #ifndef CAPSTONE_DIET
6475  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
6476 #endif
6477 },
6478 {
6479  Mips_MTHI_MM, MIPS_INS_MTHI,
6480 #ifndef CAPSTONE_DIET
6481  { 0 }, { MIPS_REG_HI0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6482 #endif
6483 },
6484 {
6485  Mips_MTHLIP, MIPS_INS_MTHLIP,
6486 #ifndef CAPSTONE_DIET
6487  { 0 }, { MIPS_REG_DSPPOS, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
6488 #endif
6489 },
6490 {
6491  Mips_MTLO, MIPS_INS_MTLO,
6492 #ifndef CAPSTONE_DIET
6493  { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6494 #endif
6495 },
6496 {
6497  Mips_MTLO64, MIPS_INS_MTLO,
6498 #ifndef CAPSTONE_DIET
6499  { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6500 #endif
6501 },
6502 {
6503  Mips_MTLO_DSP, MIPS_INS_MTLO,
6504 #ifndef CAPSTONE_DIET
6505  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
6506 #endif
6507 },
6508 {
6509  Mips_MTLO_MM, MIPS_INS_MTLO,
6510 #ifndef CAPSTONE_DIET
6511  { 0 }, { MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6512 #endif
6513 },
6514 {
6515  Mips_MTM0, MIPS_INS_MTM0,
6516 #ifndef CAPSTONE_DIET
6517  { 0 }, { MIPS_REG_MPL0, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
6518 #endif
6519 },
6520 {
6521  Mips_MTM1, MIPS_INS_MTM1,
6522 #ifndef CAPSTONE_DIET
6523  { 0 }, { MIPS_REG_MPL1, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
6524 #endif
6525 },
6526 {
6527  Mips_MTM2, MIPS_INS_MTM2,
6528 #ifndef CAPSTONE_DIET
6529  { 0 }, { MIPS_REG_MPL2, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
6530 #endif
6531 },
6532 {
6533  Mips_MTP0, MIPS_INS_MTP0,
6534 #ifndef CAPSTONE_DIET
6535  { 0 }, { MIPS_REG_P0, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
6536 #endif
6537 },
6538 {
6539  Mips_MTP1, MIPS_INS_MTP1,
6540 #ifndef CAPSTONE_DIET
6541  { 0 }, { MIPS_REG_P1, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
6542 #endif
6543 },
6544 {
6545  Mips_MTP2, MIPS_INS_MTP2,
6546 #ifndef CAPSTONE_DIET
6547  { 0 }, { MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
6548 #endif
6549 },
6550 {
6551  Mips_MUH, MIPS_INS_MUH,
6552 #ifndef CAPSTONE_DIET
6553  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
6554 #endif
6555 },
6556 {
6557  Mips_MUHU, MIPS_INS_MUHU,
6558 #ifndef CAPSTONE_DIET
6559  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
6560 #endif
6561 },
6562 {
6563  Mips_MUL, MIPS_INS_MUL,
6564 #ifndef CAPSTONE_DIET
6565  { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6566 #endif
6567 },
6568 {
6569  Mips_MULEQ_S_W_PHL, MIPS_INS_MULEQ_S,
6570 #ifndef CAPSTONE_DIET
6571  { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
6572 #endif
6573 },
6574 {
6575  Mips_MULEQ_S_W_PHR, MIPS_INS_MULEQ_S,
6576 #ifndef CAPSTONE_DIET
6577  { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
6578 #endif
6579 },
6580 {
6581  Mips_MULEU_S_PH_QBL, MIPS_INS_MULEU_S,
6582 #ifndef CAPSTONE_DIET
6583  { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
6584 #endif
6585 },
6586 {
6587  Mips_MULEU_S_PH_QBR, MIPS_INS_MULEU_S,
6588 #ifndef CAPSTONE_DIET
6589  { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
6590 #endif
6591 },
6592 {
6593  Mips_MULQ_RS_PH, MIPS_INS_MULQ_RS,
6594 #ifndef CAPSTONE_DIET
6595  { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
6596 #endif
6597 },
6598 {
6599  Mips_MULQ_RS_W, MIPS_INS_MULQ_RS,
6600 #ifndef CAPSTONE_DIET
6601  { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
6602 #endif
6603 },
6604 {
6605  Mips_MULQ_S_PH, MIPS_INS_MULQ_S,
6606 #ifndef CAPSTONE_DIET
6607  { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
6608 #endif
6609 },
6610 {
6611  Mips_MULQ_S_W, MIPS_INS_MULQ_S,
6612 #ifndef CAPSTONE_DIET
6613  { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
6614 #endif
6615 },
6616 {
6617  Mips_MULR_Q_H, MIPS_INS_MULR_Q,
6618 #ifndef CAPSTONE_DIET
6619  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6620 #endif
6621 },
6622 {
6623  Mips_MULR_Q_W, MIPS_INS_MULR_Q,
6624 #ifndef CAPSTONE_DIET
6625  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6626 #endif
6627 },
6628 {
6629  Mips_MULSAQ_S_W_PH, MIPS_INS_MULSAQ_S,
6630 #ifndef CAPSTONE_DIET
6631  { 0 }, { MIPS_REG_DSPOUTFLAG16_19, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
6632 #endif
6633 },
6634 {
6635  Mips_MULSA_W_PH, MIPS_INS_MULSA,
6636 #ifndef CAPSTONE_DIET
6637  { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
6638 #endif
6639 },
6640 {
6641  Mips_MULT, MIPS_INS_MULT,
6642 #ifndef CAPSTONE_DIET
6643  { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6644 #endif
6645 },
6646 {
6647  Mips_MULTU_DSP, MIPS_INS_MULTU,
6648 #ifndef CAPSTONE_DIET
6649  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
6650 #endif
6651 },
6652 {
6653  Mips_MULT_DSP, MIPS_INS_MULT,
6654 #ifndef CAPSTONE_DIET
6655  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
6656 #endif
6657 },
6658 {
6659  Mips_MULT_MM, MIPS_INS_MULT,
6660 #ifndef CAPSTONE_DIET
6661  { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6662 #endif
6663 },
6664 {
6665  Mips_MULTu, MIPS_INS_MULTU,
6666 #ifndef CAPSTONE_DIET
6667  { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
6668 #endif
6669 },
6670 {
6671  Mips_MULTu_MM, MIPS_INS_MULTU,
6672 #ifndef CAPSTONE_DIET
6673  { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6674 #endif
6675 },
6676 {
6677  Mips_MULU, MIPS_INS_MULU,
6678 #ifndef CAPSTONE_DIET
6679  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
6680 #endif
6681 },
6682 {
6683  Mips_MULV_B, MIPS_INS_MULV,
6684 #ifndef CAPSTONE_DIET
6685  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6686 #endif
6687 },
6688 {
6689  Mips_MULV_D, MIPS_INS_MULV,
6690 #ifndef CAPSTONE_DIET
6691  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6692 #endif
6693 },
6694 {
6695  Mips_MULV_H, MIPS_INS_MULV,
6696 #ifndef CAPSTONE_DIET
6697  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6698 #endif
6699 },
6700 {
6701  Mips_MULV_W, MIPS_INS_MULV,
6702 #ifndef CAPSTONE_DIET
6703  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6704 #endif
6705 },
6706 {
6707  Mips_MUL_MM, MIPS_INS_MUL,
6708 #ifndef CAPSTONE_DIET
6709  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6710 #endif
6711 },
6712 {
6713  Mips_MUL_PH, MIPS_INS_MUL,
6714 #ifndef CAPSTONE_DIET
6715  { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
6716 #endif
6717 },
6718 {
6719  Mips_MUL_Q_H, MIPS_INS_MUL_Q,
6720 #ifndef CAPSTONE_DIET
6721  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6722 #endif
6723 },
6724 {
6725  Mips_MUL_Q_W, MIPS_INS_MUL_Q,
6726 #ifndef CAPSTONE_DIET
6727  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6728 #endif
6729 },
6730 {
6731  Mips_MUL_R6, MIPS_INS_MUL,
6732 #ifndef CAPSTONE_DIET
6733  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
6734 #endif
6735 },
6736 {
6737  Mips_MUL_S_PH, MIPS_INS_MUL_S,
6738 #ifndef CAPSTONE_DIET
6739  { 0 }, { MIPS_REG_DSPOUTFLAG21, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
6740 #endif
6741 },
6742 {
6743  Mips_Mfhi16, MIPS_INS_MFHI,
6744 #ifndef CAPSTONE_DIET
6745  { MIPS_REG_HI0, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
6746 #endif
6747 },
6748 {
6749  Mips_Mflo16, MIPS_INS_MFLO,
6750 #ifndef CAPSTONE_DIET
6751  { MIPS_REG_LO0, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
6752 #endif
6753 },
6754 {
6755  Mips_Move32R16, MIPS_INS_MOVE,
6756 #ifndef CAPSTONE_DIET
6757  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
6758 #endif
6759 },
6760 {
6761  Mips_MoveR3216, MIPS_INS_MOVE,
6762 #ifndef CAPSTONE_DIET
6763  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
6764 #endif
6765 },
6766 {
6767  Mips_NLOC_B, MIPS_INS_NLOC,
6768 #ifndef CAPSTONE_DIET
6769  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6770 #endif
6771 },
6772 {
6773  Mips_NLOC_D, MIPS_INS_NLOC,
6774 #ifndef CAPSTONE_DIET
6775  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6776 #endif
6777 },
6778 {
6779  Mips_NLOC_H, MIPS_INS_NLOC,
6780 #ifndef CAPSTONE_DIET
6781  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6782 #endif
6783 },
6784 {
6785  Mips_NLOC_W, MIPS_INS_NLOC,
6786 #ifndef CAPSTONE_DIET
6787  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6788 #endif
6789 },
6790 {
6791  Mips_NLZC_B, MIPS_INS_NLZC,
6792 #ifndef CAPSTONE_DIET
6793  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6794 #endif
6795 },
6796 {
6797  Mips_NLZC_D, MIPS_INS_NLZC,
6798 #ifndef CAPSTONE_DIET
6799  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6800 #endif
6801 },
6802 {
6803  Mips_NLZC_H, MIPS_INS_NLZC,
6804 #ifndef CAPSTONE_DIET
6805  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6806 #endif
6807 },
6808 {
6809  Mips_NLZC_W, MIPS_INS_NLZC,
6810 #ifndef CAPSTONE_DIET
6811  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6812 #endif
6813 },
6814 {
6815  Mips_NMADD_D32, MIPS_INS_NMADD,
6816 #ifndef CAPSTONE_DIET
6817  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0
6818 #endif
6819 },
6820 {
6821  Mips_NMADD_D32_MM, MIPS_INS_NMADD,
6822 #ifndef CAPSTONE_DIET
6823  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6824 #endif
6825 },
6826 {
6827  Mips_NMADD_D64, MIPS_INS_NMADD,
6828 #ifndef CAPSTONE_DIET
6829  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0
6830 #endif
6831 },
6832 {
6833  Mips_NMADD_S, MIPS_INS_NMADD,
6834 #ifndef CAPSTONE_DIET
6835  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0
6836 #endif
6837 },
6838 {
6839  Mips_NMADD_S_MM, MIPS_INS_NMADD,
6840 #ifndef CAPSTONE_DIET
6841  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6842 #endif
6843 },
6844 {
6845  Mips_NMSUB_D32, MIPS_INS_NMSUB,
6846 #ifndef CAPSTONE_DIET
6847  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0
6848 #endif
6849 },
6850 {
6851  Mips_NMSUB_D32_MM, MIPS_INS_NMSUB,
6852 #ifndef CAPSTONE_DIET
6853  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6854 #endif
6855 },
6856 {
6857  Mips_NMSUB_D64, MIPS_INS_NMSUB,
6858 #ifndef CAPSTONE_DIET
6859  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0
6860 #endif
6861 },
6862 {
6863  Mips_NMSUB_S, MIPS_INS_NMSUB,
6864 #ifndef CAPSTONE_DIET
6865  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NONANSFPMATH, 0 }, 0, 0
6866 #endif
6867 },
6868 {
6869  Mips_NMSUB_S_MM, MIPS_INS_NMSUB,
6870 #ifndef CAPSTONE_DIET
6871  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6872 #endif
6873 },
6874 {
6875  Mips_NOR, MIPS_INS_NOR,
6876 #ifndef CAPSTONE_DIET
6877  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
6878 #endif
6879 },
6880 {
6881  Mips_NOR64, MIPS_INS_NOR,
6882 #ifndef CAPSTONE_DIET
6883  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
6884 #endif
6885 },
6886 {
6887  Mips_NORI_B, MIPS_INS_NORI,
6888 #ifndef CAPSTONE_DIET
6889  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6890 #endif
6891 },
6892 {
6893  Mips_NOR_MM, MIPS_INS_NOR,
6894 #ifndef CAPSTONE_DIET
6895  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6896 #endif
6897 },
6898 {
6899  Mips_NOR_V, MIPS_INS_NOR,
6900 #ifndef CAPSTONE_DIET
6901  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6902 #endif
6903 },
6904 {
6905  Mips_NOT16_MM, MIPS_INS_NOT16,
6906 #ifndef CAPSTONE_DIET
6907  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6908 #endif
6909 },
6910 {
6911  Mips_NegRxRy16, MIPS_INS_NEG,
6912 #ifndef CAPSTONE_DIET
6913  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
6914 #endif
6915 },
6916 {
6917  Mips_NotRxRy16, MIPS_INS_NOT,
6918 #ifndef CAPSTONE_DIET
6919  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
6920 #endif
6921 },
6922 {
6923  Mips_OR, MIPS_INS_OR,
6924 #ifndef CAPSTONE_DIET
6925  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
6926 #endif
6927 },
6928 {
6929  Mips_OR16_MM, MIPS_INS_OR16,
6930 #ifndef CAPSTONE_DIET
6931  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6932 #endif
6933 },
6934 {
6935  Mips_OR64, MIPS_INS_OR,
6936 #ifndef CAPSTONE_DIET
6937  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
6938 #endif
6939 },
6940 {
6941  Mips_ORI_B, MIPS_INS_ORI,
6942 #ifndef CAPSTONE_DIET
6943  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6944 #endif
6945 },
6946 {
6947  Mips_OR_MM, MIPS_INS_OR,
6948 #ifndef CAPSTONE_DIET
6949  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6950 #endif
6951 },
6952 {
6953  Mips_OR_V, MIPS_INS_OR,
6954 #ifndef CAPSTONE_DIET
6955  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
6956 #endif
6957 },
6958 {
6959  Mips_ORi, MIPS_INS_ORI,
6960 #ifndef CAPSTONE_DIET
6961  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
6962 #endif
6963 },
6964 {
6965  Mips_ORi64, MIPS_INS_ORI,
6966 #ifndef CAPSTONE_DIET
6967  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
6968 #endif
6969 },
6970 {
6971  Mips_ORi_MM, MIPS_INS_ORI,
6972 #ifndef CAPSTONE_DIET
6973  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6974 #endif
6975 },
6976 {
6977  Mips_OrRxRxRy16, MIPS_INS_OR,
6978 #ifndef CAPSTONE_DIET
6979  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
6980 #endif
6981 },
6982 {
6983  Mips_PACKRL_PH, MIPS_INS_PACKRL,
6984 #ifndef CAPSTONE_DIET
6985  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
6986 #endif
6987 },
6988 {
6989  Mips_PAUSE, MIPS_INS_PAUSE,
6990 #ifndef CAPSTONE_DIET
6991  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
6992 #endif
6993 },
6994 {
6995  Mips_PAUSE_MM, MIPS_INS_PAUSE,
6996 #ifndef CAPSTONE_DIET
6997  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
6998 #endif
6999 },
7000 {
7001  Mips_PCKEV_B, MIPS_INS_PCKEV,
7002 #ifndef CAPSTONE_DIET
7003  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7004 #endif
7005 },
7006 {
7007  Mips_PCKEV_D, MIPS_INS_PCKEV,
7008 #ifndef CAPSTONE_DIET
7009  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7010 #endif
7011 },
7012 {
7013  Mips_PCKEV_H, MIPS_INS_PCKEV,
7014 #ifndef CAPSTONE_DIET
7015  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7016 #endif
7017 },
7018 {
7019  Mips_PCKEV_W, MIPS_INS_PCKEV,
7020 #ifndef CAPSTONE_DIET
7021  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7022 #endif
7023 },
7024 {
7025  Mips_PCKOD_B, MIPS_INS_PCKOD,
7026 #ifndef CAPSTONE_DIET
7027  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7028 #endif
7029 },
7030 {
7031  Mips_PCKOD_D, MIPS_INS_PCKOD,
7032 #ifndef CAPSTONE_DIET
7033  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7034 #endif
7035 },
7036 {
7037  Mips_PCKOD_H, MIPS_INS_PCKOD,
7038 #ifndef CAPSTONE_DIET
7039  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7040 #endif
7041 },
7042 {
7043  Mips_PCKOD_W, MIPS_INS_PCKOD,
7044 #ifndef CAPSTONE_DIET
7045  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7046 #endif
7047 },
7048 {
7049  Mips_PCNT_B, MIPS_INS_PCNT,
7050 #ifndef CAPSTONE_DIET
7051  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7052 #endif
7053 },
7054 {
7055  Mips_PCNT_D, MIPS_INS_PCNT,
7056 #ifndef CAPSTONE_DIET
7057  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7058 #endif
7059 },
7060 {
7061  Mips_PCNT_H, MIPS_INS_PCNT,
7062 #ifndef CAPSTONE_DIET
7063  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7064 #endif
7065 },
7066 {
7067  Mips_PCNT_W, MIPS_INS_PCNT,
7068 #ifndef CAPSTONE_DIET
7069  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7070 #endif
7071 },
7072 {
7073  Mips_PICK_PH, MIPS_INS_PICK,
7074 #ifndef CAPSTONE_DIET
7075  { MIPS_REG_DSPCCOND, 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7076 #endif
7077 },
7078 {
7079  Mips_PICK_QB, MIPS_INS_PICK,
7080 #ifndef CAPSTONE_DIET
7081  { MIPS_REG_DSPCCOND, 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7082 #endif
7083 },
7084 {
7085  Mips_POP, MIPS_INS_POP,
7086 #ifndef CAPSTONE_DIET
7087  { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
7088 #endif
7089 },
7090 {
7091  Mips_PRECEQU_PH_QBL, MIPS_INS_PRECEQU,
7092 #ifndef CAPSTONE_DIET
7093  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7094 #endif
7095 },
7096 {
7097  Mips_PRECEQU_PH_QBLA, MIPS_INS_PRECEQU,
7098 #ifndef CAPSTONE_DIET
7099  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7100 #endif
7101 },
7102 {
7103  Mips_PRECEQU_PH_QBR, MIPS_INS_PRECEQU,
7104 #ifndef CAPSTONE_DIET
7105  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7106 #endif
7107 },
7108 {
7109  Mips_PRECEQU_PH_QBRA, MIPS_INS_PRECEQU,
7110 #ifndef CAPSTONE_DIET
7111  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7112 #endif
7113 },
7114 {
7115  Mips_PRECEQ_W_PHL, MIPS_INS_PRECEQ,
7116 #ifndef CAPSTONE_DIET
7117  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7118 #endif
7119 },
7120 {
7121  Mips_PRECEQ_W_PHR, MIPS_INS_PRECEQ,
7122 #ifndef CAPSTONE_DIET
7123  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7124 #endif
7125 },
7126 {
7127  Mips_PRECEU_PH_QBL, MIPS_INS_PRECEU,
7128 #ifndef CAPSTONE_DIET
7129  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7130 #endif
7131 },
7132 {
7133  Mips_PRECEU_PH_QBLA, MIPS_INS_PRECEU,
7134 #ifndef CAPSTONE_DIET
7135  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7136 #endif
7137 },
7138 {
7139  Mips_PRECEU_PH_QBR, MIPS_INS_PRECEU,
7140 #ifndef CAPSTONE_DIET
7141  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7142 #endif
7143 },
7144 {
7145  Mips_PRECEU_PH_QBRA, MIPS_INS_PRECEU,
7146 #ifndef CAPSTONE_DIET
7147  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7148 #endif
7149 },
7150 {
7151  Mips_PRECRQU_S_QB_PH, MIPS_INS_PRECRQU_S,
7152 #ifndef CAPSTONE_DIET
7153  { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7154 #endif
7155 },
7156 {
7157  Mips_PRECRQ_PH_W, MIPS_INS_PRECRQ,
7158 #ifndef CAPSTONE_DIET
7159  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7160 #endif
7161 },
7162 {
7163  Mips_PRECRQ_QB_PH, MIPS_INS_PRECRQ,
7164 #ifndef CAPSTONE_DIET
7165  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7166 #endif
7167 },
7168 {
7169  Mips_PRECRQ_RS_PH_W, MIPS_INS_PRECRQ_RS,
7170 #ifndef CAPSTONE_DIET
7171  { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7172 #endif
7173 },
7174 {
7175  Mips_PRECR_QB_PH, MIPS_INS_PRECR,
7176 #ifndef CAPSTONE_DIET
7177  { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
7178 #endif
7179 },
7180 {
7181  Mips_PRECR_SRA_PH_W, MIPS_INS_PRECR_SRA,
7182 #ifndef CAPSTONE_DIET
7183  { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
7184 #endif
7185 },
7186 {
7187  Mips_PRECR_SRA_R_PH_W, MIPS_INS_PRECR_SRA_R,
7188 #ifndef CAPSTONE_DIET
7189  { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
7190 #endif
7191 },
7192 {
7193  Mips_PREF, MIPS_INS_PREF,
7194 #ifndef CAPSTONE_DIET
7195  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3_32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
7196 #endif
7197 },
7198 {
7199  Mips_PREF_MM, MIPS_INS_PREF,
7200 #ifndef CAPSTONE_DIET
7201  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7202 #endif
7203 },
7204 {
7205  Mips_PREF_R6, MIPS_INS_PREF,
7206 #ifndef CAPSTONE_DIET
7207  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7208 #endif
7209 },
7210 {
7211  Mips_PREPEND, MIPS_INS_PREPEND,
7212 #ifndef CAPSTONE_DIET
7213  { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
7214 #endif
7215 },
7216 {
7217  Mips_RADDU_W_QB, MIPS_INS_RADDU,
7218 #ifndef CAPSTONE_DIET
7219  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7220 #endif
7221 },
7222 {
7223  Mips_RDDSP, MIPS_INS_RDDSP,
7224 #ifndef CAPSTONE_DIET
7225  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7226 #endif
7227 },
7228 {
7229  Mips_RDHWR, MIPS_INS_RDHWR,
7230 #ifndef CAPSTONE_DIET
7231  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
7232 #endif
7233 },
7234 {
7235  Mips_RDHWR64, MIPS_INS_RDHWR,
7236 #ifndef CAPSTONE_DIET
7237  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
7238 #endif
7239 },
7240 {
7241  Mips_RDHWR_MM, MIPS_INS_RDHWR,
7242 #ifndef CAPSTONE_DIET
7243  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7244 #endif
7245 },
7246 {
7247  Mips_REPLV_PH, MIPS_INS_REPLV,
7248 #ifndef CAPSTONE_DIET
7249  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7250 #endif
7251 },
7252 {
7253  Mips_REPLV_QB, MIPS_INS_REPLV,
7254 #ifndef CAPSTONE_DIET
7255  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7256 #endif
7257 },
7258 {
7259  Mips_REPL_PH, MIPS_INS_REPL,
7260 #ifndef CAPSTONE_DIET
7261  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7262 #endif
7263 },
7264 {
7265  Mips_REPL_QB, MIPS_INS_REPL,
7266 #ifndef CAPSTONE_DIET
7267  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7268 #endif
7269 },
7270 {
7271  Mips_RINT_D, MIPS_INS_RINT,
7272 #ifndef CAPSTONE_DIET
7273  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7274 #endif
7275 },
7276 {
7277  Mips_RINT_S, MIPS_INS_RINT,
7278 #ifndef CAPSTONE_DIET
7279  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7280 #endif
7281 },
7282 {
7283  Mips_ROTR, MIPS_INS_ROTR,
7284 #ifndef CAPSTONE_DIET
7285  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
7286 #endif
7287 },
7288 {
7289  Mips_ROTRV, MIPS_INS_ROTRV,
7290 #ifndef CAPSTONE_DIET
7291  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
7292 #endif
7293 },
7294 {
7295  Mips_ROTRV_MM, MIPS_INS_ROTRV,
7296 #ifndef CAPSTONE_DIET
7297  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7298 #endif
7299 },
7300 {
7301  Mips_ROTR_MM, MIPS_INS_ROTR,
7302 #ifndef CAPSTONE_DIET
7303  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7304 #endif
7305 },
7306 {
7307  Mips_ROUND_L_D64, MIPS_INS_ROUND,
7308 #ifndef CAPSTONE_DIET
7309  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
7310 #endif
7311 },
7312 {
7313  Mips_ROUND_L_S, MIPS_INS_ROUND,
7314 #ifndef CAPSTONE_DIET
7315  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
7316 #endif
7317 },
7318 {
7319  Mips_ROUND_W_D32, MIPS_INS_ROUND,
7320 #ifndef CAPSTONE_DIET
7321  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
7322 #endif
7323 },
7324 {
7325  Mips_ROUND_W_D64, MIPS_INS_ROUND,
7326 #ifndef CAPSTONE_DIET
7327  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0
7328 #endif
7329 },
7330 {
7331  Mips_ROUND_W_MM, MIPS_INS_ROUND,
7332 #ifndef CAPSTONE_DIET
7333  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7334 #endif
7335 },
7336 {
7337  Mips_ROUND_W_S, MIPS_INS_ROUND,
7338 #ifndef CAPSTONE_DIET
7339  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
7340 #endif
7341 },
7342 {
7343  Mips_ROUND_W_S_MM, MIPS_INS_ROUND,
7344 #ifndef CAPSTONE_DIET
7345  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7346 #endif
7347 },
7348 {
7349  Mips_SAT_S_B, MIPS_INS_SAT_S,
7350 #ifndef CAPSTONE_DIET
7351  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7352 #endif
7353 },
7354 {
7355  Mips_SAT_S_D, MIPS_INS_SAT_S,
7356 #ifndef CAPSTONE_DIET
7357  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7358 #endif
7359 },
7360 {
7361  Mips_SAT_S_H, MIPS_INS_SAT_S,
7362 #ifndef CAPSTONE_DIET
7363  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7364 #endif
7365 },
7366 {
7367  Mips_SAT_S_W, MIPS_INS_SAT_S,
7368 #ifndef CAPSTONE_DIET
7369  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7370 #endif
7371 },
7372 {
7373  Mips_SAT_U_B, MIPS_INS_SAT_U,
7374 #ifndef CAPSTONE_DIET
7375  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7376 #endif
7377 },
7378 {
7379  Mips_SAT_U_D, MIPS_INS_SAT_U,
7380 #ifndef CAPSTONE_DIET
7381  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7382 #endif
7383 },
7384 {
7385  Mips_SAT_U_H, MIPS_INS_SAT_U,
7386 #ifndef CAPSTONE_DIET
7387  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7388 #endif
7389 },
7390 {
7391  Mips_SAT_U_W, MIPS_INS_SAT_U,
7392 #ifndef CAPSTONE_DIET
7393  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7394 #endif
7395 },
7396 {
7397  Mips_SB, MIPS_INS_SB,
7398 #ifndef CAPSTONE_DIET
7399  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
7400 #endif
7401 },
7402 {
7403  Mips_SB16_MM, MIPS_INS_SB16,
7404 #ifndef CAPSTONE_DIET
7405  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7406 #endif
7407 },
7408 {
7409  Mips_SB64, MIPS_INS_SB,
7410 #ifndef CAPSTONE_DIET
7411  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
7412 #endif
7413 },
7414 {
7415  Mips_SB_MM, MIPS_INS_SB,
7416 #ifndef CAPSTONE_DIET
7417  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7418 #endif
7419 },
7420 {
7421  Mips_SC, MIPS_INS_SC,
7422 #ifndef CAPSTONE_DIET
7423  { 0 }, { 0 }, { MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
7424 #endif
7425 },
7426 {
7427  Mips_SCD, MIPS_INS_SCD,
7428 #ifndef CAPSTONE_DIET
7429  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
7430 #endif
7431 },
7432 {
7433  Mips_SCD_R6, MIPS_INS_SCD,
7434 #ifndef CAPSTONE_DIET
7435  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7436 #endif
7437 },
7438 {
7439  Mips_SC_MM, MIPS_INS_SC,
7440 #ifndef CAPSTONE_DIET
7441  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7442 #endif
7443 },
7444 {
7445  Mips_SC_R6, MIPS_INS_SC,
7446 #ifndef CAPSTONE_DIET
7447  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7448 #endif
7449 },
7450 {
7451  Mips_SD, MIPS_INS_SD,
7452 #ifndef CAPSTONE_DIET
7453  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, 0 }, 0, 0
7454 #endif
7455 },
7456 {
7457  Mips_SDBBP, MIPS_INS_SDBBP,
7458 #ifndef CAPSTONE_DIET
7459  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
7460 #endif
7461 },
7462 {
7463  Mips_SDBBP16_MM, MIPS_INS_SDBBP16,
7464 #ifndef CAPSTONE_DIET
7465  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7466 #endif
7467 },
7468 {
7469  Mips_SDBBP_MM, MIPS_INS_SDBBP,
7470 #ifndef CAPSTONE_DIET
7471  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7472 #endif
7473 },
7474 {
7475  Mips_SDBBP_R6, MIPS_INS_SDBBP,
7476 #ifndef CAPSTONE_DIET
7477  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7478 #endif
7479 },
7480 {
7481  Mips_SDC1, MIPS_INS_SDC1,
7482 #ifndef CAPSTONE_DIET
7483  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0
7484 #endif
7485 },
7486 {
7487  Mips_SDC164, MIPS_INS_SDC1,
7488 #ifndef CAPSTONE_DIET
7489  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS2, 0 }, 0, 0
7490 #endif
7491 },
7492 {
7493  Mips_SDC1_MM, MIPS_INS_SDC1,
7494 #ifndef CAPSTONE_DIET
7495  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7496 #endif
7497 },
7498 {
7499  Mips_SDC2, MIPS_INS_SDC2,
7500 #ifndef CAPSTONE_DIET
7501  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
7502 #endif
7503 },
7504 {
7505  Mips_SDC2_R6, MIPS_INS_SDC2,
7506 #ifndef CAPSTONE_DIET
7507  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7508 #endif
7509 },
7510 {
7511  Mips_SDC3, MIPS_INS_SDC3,
7512 #ifndef CAPSTONE_DIET
7513  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
7514 #endif
7515 },
7516 {
7517  Mips_SDIV, MIPS_INS_DIV,
7518 #ifndef CAPSTONE_DIET
7519  { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
7520 #endif
7521 },
7522 {
7523  Mips_SDIV_MM, MIPS_INS_DIV,
7524 #ifndef CAPSTONE_DIET
7525  { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7526 #endif
7527 },
7528 {
7529  Mips_SDL, MIPS_INS_SDL,
7530 #ifndef CAPSTONE_DIET
7531  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
7532 #endif
7533 },
7534 {
7535  Mips_SDR, MIPS_INS_SDR,
7536 #ifndef CAPSTONE_DIET
7537  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS3, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
7538 #endif
7539 },
7540 {
7541  Mips_SDXC1, MIPS_INS_SDXC1,
7542 #ifndef CAPSTONE_DIET
7543  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, MIPS_GRP_NOTNACL, 0 }, 0, 0
7544 #endif
7545 },
7546 {
7547  Mips_SDXC164, MIPS_INS_SDXC1,
7548 #ifndef CAPSTONE_DIET
7549  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
7550 #endif
7551 },
7552 {
7553  Mips_SEB, MIPS_INS_SEB,
7554 #ifndef CAPSTONE_DIET
7555  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
7556 #endif
7557 },
7558 {
7559  Mips_SEB64, MIPS_INS_SEB,
7560 #ifndef CAPSTONE_DIET
7561  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
7562 #endif
7563 },
7564 {
7565  Mips_SEB_MM, MIPS_INS_SEB,
7566 #ifndef CAPSTONE_DIET
7567  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7568 #endif
7569 },
7570 {
7571  Mips_SEH, MIPS_INS_SEH,
7572 #ifndef CAPSTONE_DIET
7573  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
7574 #endif
7575 },
7576 {
7577  Mips_SEH64, MIPS_INS_SEH,
7578 #ifndef CAPSTONE_DIET
7579  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
7580 #endif
7581 },
7582 {
7583  Mips_SEH_MM, MIPS_INS_SEH,
7584 #ifndef CAPSTONE_DIET
7585  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7586 #endif
7587 },
7588 {
7589  Mips_SELEQZ, MIPS_INS_SELEQZ,
7590 #ifndef CAPSTONE_DIET
7591  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7592 #endif
7593 },
7594 {
7595  Mips_SELEQZ64, MIPS_INS_SELEQZ,
7596 #ifndef CAPSTONE_DIET
7597  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7598 #endif
7599 },
7600 {
7601  Mips_SELEQZ_D, MIPS_INS_SELEQZ,
7602 #ifndef CAPSTONE_DIET
7603  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7604 #endif
7605 },
7606 {
7607  Mips_SELEQZ_S, MIPS_INS_SELEQZ,
7608 #ifndef CAPSTONE_DIET
7609  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7610 #endif
7611 },
7612 {
7613  Mips_SELNEZ, MIPS_INS_SELNEZ,
7614 #ifndef CAPSTONE_DIET
7615  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP32BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7616 #endif
7617 },
7618 {
7619  Mips_SELNEZ64, MIPS_INS_SELNEZ,
7620 #ifndef CAPSTONE_DIET
7621  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_GP64BIT, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7622 #endif
7623 },
7624 {
7625  Mips_SELNEZ_D, MIPS_INS_SELNEZ,
7626 #ifndef CAPSTONE_DIET
7627  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7628 #endif
7629 },
7630 {
7631  Mips_SELNEZ_S, MIPS_INS_SELNEZ,
7632 #ifndef CAPSTONE_DIET
7633  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7634 #endif
7635 },
7636 {
7637  Mips_SEL_D, MIPS_INS_SEL,
7638 #ifndef CAPSTONE_DIET
7639  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7640 #endif
7641 },
7642 {
7643  Mips_SEL_S, MIPS_INS_SEL,
7644 #ifndef CAPSTONE_DIET
7645  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
7646 #endif
7647 },
7648 {
7649  Mips_SEQ, MIPS_INS_SEQ,
7650 #ifndef CAPSTONE_DIET
7651  { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
7652 #endif
7653 },
7654 {
7655  Mips_SEQi, MIPS_INS_SEQI,
7656 #ifndef CAPSTONE_DIET
7657  { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
7658 #endif
7659 },
7660 {
7661  Mips_SH, MIPS_INS_SH,
7662 #ifndef CAPSTONE_DIET
7663  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
7664 #endif
7665 },
7666 {
7667  Mips_SH16_MM, MIPS_INS_SH16,
7668 #ifndef CAPSTONE_DIET
7669  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7670 #endif
7671 },
7672 {
7673  Mips_SH64, MIPS_INS_SH,
7674 #ifndef CAPSTONE_DIET
7675  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
7676 #endif
7677 },
7678 {
7679  Mips_SHF_B, MIPS_INS_SHF,
7680 #ifndef CAPSTONE_DIET
7681  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7682 #endif
7683 },
7684 {
7685  Mips_SHF_H, MIPS_INS_SHF,
7686 #ifndef CAPSTONE_DIET
7687  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7688 #endif
7689 },
7690 {
7691  Mips_SHF_W, MIPS_INS_SHF,
7692 #ifndef CAPSTONE_DIET
7693  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7694 #endif
7695 },
7696 {
7697  Mips_SHILO, MIPS_INS_SHILO,
7698 #ifndef CAPSTONE_DIET
7699  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7700 #endif
7701 },
7702 {
7703  Mips_SHILOV, MIPS_INS_SHILOV,
7704 #ifndef CAPSTONE_DIET
7705  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7706 #endif
7707 },
7708 {
7709  Mips_SHLLV_PH, MIPS_INS_SHLLV,
7710 #ifndef CAPSTONE_DIET
7711  { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7712 #endif
7713 },
7714 {
7715  Mips_SHLLV_QB, MIPS_INS_SHLLV,
7716 #ifndef CAPSTONE_DIET
7717  { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7718 #endif
7719 },
7720 {
7721  Mips_SHLLV_S_PH, MIPS_INS_SHLLV_S,
7722 #ifndef CAPSTONE_DIET
7723  { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7724 #endif
7725 },
7726 {
7727  Mips_SHLLV_S_W, MIPS_INS_SHLLV_S,
7728 #ifndef CAPSTONE_DIET
7729  { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7730 #endif
7731 },
7732 {
7733  Mips_SHLL_PH, MIPS_INS_SHLL,
7734 #ifndef CAPSTONE_DIET
7735  { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7736 #endif
7737 },
7738 {
7739  Mips_SHLL_QB, MIPS_INS_SHLL,
7740 #ifndef CAPSTONE_DIET
7741  { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7742 #endif
7743 },
7744 {
7745  Mips_SHLL_S_PH, MIPS_INS_SHLL_S,
7746 #ifndef CAPSTONE_DIET
7747  { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7748 #endif
7749 },
7750 {
7751  Mips_SHLL_S_W, MIPS_INS_SHLL_S,
7752 #ifndef CAPSTONE_DIET
7753  { 0 }, { MIPS_REG_DSPOUTFLAG22, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7754 #endif
7755 },
7756 {
7757  Mips_SHRAV_PH, MIPS_INS_SHRAV,
7758 #ifndef CAPSTONE_DIET
7759  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7760 #endif
7761 },
7762 {
7763  Mips_SHRAV_QB, MIPS_INS_SHRAV,
7764 #ifndef CAPSTONE_DIET
7765  { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
7766 #endif
7767 },
7768 {
7769  Mips_SHRAV_R_PH, MIPS_INS_SHRAV_R,
7770 #ifndef CAPSTONE_DIET
7771  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7772 #endif
7773 },
7774 {
7775  Mips_SHRAV_R_QB, MIPS_INS_SHRAV_R,
7776 #ifndef CAPSTONE_DIET
7777  { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
7778 #endif
7779 },
7780 {
7781  Mips_SHRAV_R_W, MIPS_INS_SHRAV_R,
7782 #ifndef CAPSTONE_DIET
7783  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7784 #endif
7785 },
7786 {
7787  Mips_SHRA_PH, MIPS_INS_SHRA,
7788 #ifndef CAPSTONE_DIET
7789  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7790 #endif
7791 },
7792 {
7793  Mips_SHRA_QB, MIPS_INS_SHRA,
7794 #ifndef CAPSTONE_DIET
7795  { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
7796 #endif
7797 },
7798 {
7799  Mips_SHRA_R_PH, MIPS_INS_SHRA_R,
7800 #ifndef CAPSTONE_DIET
7801  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7802 #endif
7803 },
7804 {
7805  Mips_SHRA_R_QB, MIPS_INS_SHRA_R,
7806 #ifndef CAPSTONE_DIET
7807  { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
7808 #endif
7809 },
7810 {
7811  Mips_SHRA_R_W, MIPS_INS_SHRA_R,
7812 #ifndef CAPSTONE_DIET
7813  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7814 #endif
7815 },
7816 {
7817  Mips_SHRLV_PH, MIPS_INS_SHRLV,
7818 #ifndef CAPSTONE_DIET
7819  { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
7820 #endif
7821 },
7822 {
7823  Mips_SHRLV_QB, MIPS_INS_SHRLV,
7824 #ifndef CAPSTONE_DIET
7825  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7826 #endif
7827 },
7828 {
7829  Mips_SHRL_PH, MIPS_INS_SHRL,
7830 #ifndef CAPSTONE_DIET
7831  { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
7832 #endif
7833 },
7834 {
7835  Mips_SHRL_QB, MIPS_INS_SHRL,
7836 #ifndef CAPSTONE_DIET
7837  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
7838 #endif
7839 },
7840 {
7841  Mips_SH_MM, MIPS_INS_SH,
7842 #ifndef CAPSTONE_DIET
7843  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7844 #endif
7845 },
7846 {
7847  Mips_SLDI_B, MIPS_INS_SLDI,
7848 #ifndef CAPSTONE_DIET
7849  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7850 #endif
7851 },
7852 {
7853  Mips_SLDI_D, MIPS_INS_SLDI,
7854 #ifndef CAPSTONE_DIET
7855  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7856 #endif
7857 },
7858 {
7859  Mips_SLDI_H, MIPS_INS_SLDI,
7860 #ifndef CAPSTONE_DIET
7861  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7862 #endif
7863 },
7864 {
7865  Mips_SLDI_W, MIPS_INS_SLDI,
7866 #ifndef CAPSTONE_DIET
7867  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7868 #endif
7869 },
7870 {
7871  Mips_SLD_B, MIPS_INS_SLD,
7872 #ifndef CAPSTONE_DIET
7873  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7874 #endif
7875 },
7876 {
7877  Mips_SLD_D, MIPS_INS_SLD,
7878 #ifndef CAPSTONE_DIET
7879  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7880 #endif
7881 },
7882 {
7883  Mips_SLD_H, MIPS_INS_SLD,
7884 #ifndef CAPSTONE_DIET
7885  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7886 #endif
7887 },
7888 {
7889  Mips_SLD_W, MIPS_INS_SLD,
7890 #ifndef CAPSTONE_DIET
7891  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7892 #endif
7893 },
7894 {
7895  Mips_SLL, MIPS_INS_SLL,
7896 #ifndef CAPSTONE_DIET
7897  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
7898 #endif
7899 },
7900 {
7901  Mips_SLL16_MM, MIPS_INS_SLL16,
7902 #ifndef CAPSTONE_DIET
7903  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7904 #endif
7905 },
7906 {
7907  Mips_SLL64_32, MIPS_INS_SLL,
7908 #ifndef CAPSTONE_DIET
7909  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
7910 #endif
7911 },
7912 {
7913  Mips_SLL64_64, MIPS_INS_SLL,
7914 #ifndef CAPSTONE_DIET
7915  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
7916 #endif
7917 },
7918 {
7919  Mips_SLLI_B, MIPS_INS_SLLI,
7920 #ifndef CAPSTONE_DIET
7921  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7922 #endif
7923 },
7924 {
7925  Mips_SLLI_D, MIPS_INS_SLLI,
7926 #ifndef CAPSTONE_DIET
7927  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7928 #endif
7929 },
7930 {
7931  Mips_SLLI_H, MIPS_INS_SLLI,
7932 #ifndef CAPSTONE_DIET
7933  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7934 #endif
7935 },
7936 {
7937  Mips_SLLI_W, MIPS_INS_SLLI,
7938 #ifndef CAPSTONE_DIET
7939  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7940 #endif
7941 },
7942 {
7943  Mips_SLLV, MIPS_INS_SLLV,
7944 #ifndef CAPSTONE_DIET
7945  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
7946 #endif
7947 },
7948 {
7949  Mips_SLLV_MM, MIPS_INS_SLLV,
7950 #ifndef CAPSTONE_DIET
7951  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7952 #endif
7953 },
7954 {
7955  Mips_SLL_B, MIPS_INS_SLL,
7956 #ifndef CAPSTONE_DIET
7957  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7958 #endif
7959 },
7960 {
7961  Mips_SLL_D, MIPS_INS_SLL,
7962 #ifndef CAPSTONE_DIET
7963  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7964 #endif
7965 },
7966 {
7967  Mips_SLL_H, MIPS_INS_SLL,
7968 #ifndef CAPSTONE_DIET
7969  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7970 #endif
7971 },
7972 {
7973  Mips_SLL_MM, MIPS_INS_SLL,
7974 #ifndef CAPSTONE_DIET
7975  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
7976 #endif
7977 },
7978 {
7979  Mips_SLL_W, MIPS_INS_SLL,
7980 #ifndef CAPSTONE_DIET
7981  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
7982 #endif
7983 },
7984 {
7985  Mips_SLT, MIPS_INS_SLT,
7986 #ifndef CAPSTONE_DIET
7987  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
7988 #endif
7989 },
7990 {
7991  Mips_SLT64, MIPS_INS_SLT,
7992 #ifndef CAPSTONE_DIET
7993  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
7994 #endif
7995 },
7996 {
7997  Mips_SLT_MM, MIPS_INS_SLT,
7998 #ifndef CAPSTONE_DIET
7999  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8000 #endif
8001 },
8002 {
8003  Mips_SLTi, MIPS_INS_SLTI,
8004 #ifndef CAPSTONE_DIET
8005  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8006 #endif
8007 },
8008 {
8009  Mips_SLTi64, MIPS_INS_SLTI,
8010 #ifndef CAPSTONE_DIET
8011  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8012 #endif
8013 },
8014 {
8015  Mips_SLTi_MM, MIPS_INS_SLTI,
8016 #ifndef CAPSTONE_DIET
8017  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8018 #endif
8019 },
8020 {
8021  Mips_SLTiu, MIPS_INS_SLTIU,
8022 #ifndef CAPSTONE_DIET
8023  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8024 #endif
8025 },
8026 {
8027  Mips_SLTiu64, MIPS_INS_SLTIU,
8028 #ifndef CAPSTONE_DIET
8029  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8030 #endif
8031 },
8032 {
8033  Mips_SLTiu_MM, MIPS_INS_SLTIU,
8034 #ifndef CAPSTONE_DIET
8035  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8036 #endif
8037 },
8038 {
8039  Mips_SLTu, MIPS_INS_SLTU,
8040 #ifndef CAPSTONE_DIET
8041  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8042 #endif
8043 },
8044 {
8045  Mips_SLTu64, MIPS_INS_SLTU,
8046 #ifndef CAPSTONE_DIET
8047  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8048 #endif
8049 },
8050 {
8051  Mips_SLTu_MM, MIPS_INS_SLTU,
8052 #ifndef CAPSTONE_DIET
8053  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8054 #endif
8055 },
8056 {
8057  Mips_SNE, MIPS_INS_SNE,
8058 #ifndef CAPSTONE_DIET
8059  { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
8060 #endif
8061 },
8062 {
8063  Mips_SNEi, MIPS_INS_SNEI,
8064 #ifndef CAPSTONE_DIET
8065  { 0 }, { 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
8066 #endif
8067 },
8068 {
8069  Mips_SPLATI_B, MIPS_INS_SPLATI,
8070 #ifndef CAPSTONE_DIET
8071  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8072 #endif
8073 },
8074 {
8075  Mips_SPLATI_D, MIPS_INS_SPLATI,
8076 #ifndef CAPSTONE_DIET
8077  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8078 #endif
8079 },
8080 {
8081  Mips_SPLATI_H, MIPS_INS_SPLATI,
8082 #ifndef CAPSTONE_DIET
8083  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8084 #endif
8085 },
8086 {
8087  Mips_SPLATI_W, MIPS_INS_SPLATI,
8088 #ifndef CAPSTONE_DIET
8089  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8090 #endif
8091 },
8092 {
8093  Mips_SPLAT_B, MIPS_INS_SPLAT,
8094 #ifndef CAPSTONE_DIET
8095  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8096 #endif
8097 },
8098 {
8099  Mips_SPLAT_D, MIPS_INS_SPLAT,
8100 #ifndef CAPSTONE_DIET
8101  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8102 #endif
8103 },
8104 {
8105  Mips_SPLAT_H, MIPS_INS_SPLAT,
8106 #ifndef CAPSTONE_DIET
8107  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8108 #endif
8109 },
8110 {
8111  Mips_SPLAT_W, MIPS_INS_SPLAT,
8112 #ifndef CAPSTONE_DIET
8113  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8114 #endif
8115 },
8116 {
8117  Mips_SRA, MIPS_INS_SRA,
8118 #ifndef CAPSTONE_DIET
8119  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8120 #endif
8121 },
8122 {
8123  Mips_SRAI_B, MIPS_INS_SRAI,
8124 #ifndef CAPSTONE_DIET
8125  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8126 #endif
8127 },
8128 {
8129  Mips_SRAI_D, MIPS_INS_SRAI,
8130 #ifndef CAPSTONE_DIET
8131  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8132 #endif
8133 },
8134 {
8135  Mips_SRAI_H, MIPS_INS_SRAI,
8136 #ifndef CAPSTONE_DIET
8137  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8138 #endif
8139 },
8140 {
8141  Mips_SRAI_W, MIPS_INS_SRAI,
8142 #ifndef CAPSTONE_DIET
8143  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8144 #endif
8145 },
8146 {
8147  Mips_SRARI_B, MIPS_INS_SRARI,
8148 #ifndef CAPSTONE_DIET
8149  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8150 #endif
8151 },
8152 {
8153  Mips_SRARI_D, MIPS_INS_SRARI,
8154 #ifndef CAPSTONE_DIET
8155  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8156 #endif
8157 },
8158 {
8159  Mips_SRARI_H, MIPS_INS_SRARI,
8160 #ifndef CAPSTONE_DIET
8161  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8162 #endif
8163 },
8164 {
8165  Mips_SRARI_W, MIPS_INS_SRARI,
8166 #ifndef CAPSTONE_DIET
8167  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8168 #endif
8169 },
8170 {
8171  Mips_SRAR_B, MIPS_INS_SRAR,
8172 #ifndef CAPSTONE_DIET
8173  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8174 #endif
8175 },
8176 {
8177  Mips_SRAR_D, MIPS_INS_SRAR,
8178 #ifndef CAPSTONE_DIET
8179  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8180 #endif
8181 },
8182 {
8183  Mips_SRAR_H, MIPS_INS_SRAR,
8184 #ifndef CAPSTONE_DIET
8185  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8186 #endif
8187 },
8188 {
8189  Mips_SRAR_W, MIPS_INS_SRAR,
8190 #ifndef CAPSTONE_DIET
8191  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8192 #endif
8193 },
8194 {
8195  Mips_SRAV, MIPS_INS_SRAV,
8196 #ifndef CAPSTONE_DIET
8197  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8198 #endif
8199 },
8200 {
8201  Mips_SRAV_MM, MIPS_INS_SRAV,
8202 #ifndef CAPSTONE_DIET
8203  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8204 #endif
8205 },
8206 {
8207  Mips_SRA_B, MIPS_INS_SRA,
8208 #ifndef CAPSTONE_DIET
8209  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8210 #endif
8211 },
8212 {
8213  Mips_SRA_D, MIPS_INS_SRA,
8214 #ifndef CAPSTONE_DIET
8215  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8216 #endif
8217 },
8218 {
8219  Mips_SRA_H, MIPS_INS_SRA,
8220 #ifndef CAPSTONE_DIET
8221  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8222 #endif
8223 },
8224 {
8225  Mips_SRA_MM, MIPS_INS_SRA,
8226 #ifndef CAPSTONE_DIET
8227  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8228 #endif
8229 },
8230 {
8231  Mips_SRA_W, MIPS_INS_SRA,
8232 #ifndef CAPSTONE_DIET
8233  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8234 #endif
8235 },
8236 {
8237  Mips_SRL, MIPS_INS_SRL,
8238 #ifndef CAPSTONE_DIET
8239  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
8240 #endif
8241 },
8242 {
8243  Mips_SRL16_MM, MIPS_INS_SRL16,
8244 #ifndef CAPSTONE_DIET
8245  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8246 #endif
8247 },
8248 {
8249  Mips_SRLI_B, MIPS_INS_SRLI,
8250 #ifndef CAPSTONE_DIET
8251  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8252 #endif
8253 },
8254 {
8255  Mips_SRLI_D, MIPS_INS_SRLI,
8256 #ifndef CAPSTONE_DIET
8257  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8258 #endif
8259 },
8260 {
8261  Mips_SRLI_H, MIPS_INS_SRLI,
8262 #ifndef CAPSTONE_DIET
8263  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8264 #endif
8265 },
8266 {
8267  Mips_SRLI_W, MIPS_INS_SRLI,
8268 #ifndef CAPSTONE_DIET
8269  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8270 #endif
8271 },
8272 {
8273  Mips_SRLRI_B, MIPS_INS_SRLRI,
8274 #ifndef CAPSTONE_DIET
8275  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8276 #endif
8277 },
8278 {
8279  Mips_SRLRI_D, MIPS_INS_SRLRI,
8280 #ifndef CAPSTONE_DIET
8281  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8282 #endif
8283 },
8284 {
8285  Mips_SRLRI_H, MIPS_INS_SRLRI,
8286 #ifndef CAPSTONE_DIET
8287  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8288 #endif
8289 },
8290 {
8291  Mips_SRLRI_W, MIPS_INS_SRLRI,
8292 #ifndef CAPSTONE_DIET
8293  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8294 #endif
8295 },
8296 {
8297  Mips_SRLR_B, MIPS_INS_SRLR,
8298 #ifndef CAPSTONE_DIET
8299  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8300 #endif
8301 },
8302 {
8303  Mips_SRLR_D, MIPS_INS_SRLR,
8304 #ifndef CAPSTONE_DIET
8305  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8306 #endif
8307 },
8308 {
8309  Mips_SRLR_H, MIPS_INS_SRLR,
8310 #ifndef CAPSTONE_DIET
8311  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8312 #endif
8313 },
8314 {
8315  Mips_SRLR_W, MIPS_INS_SRLR,
8316 #ifndef CAPSTONE_DIET
8317  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8318 #endif
8319 },
8320 {
8321  Mips_SRLV, MIPS_INS_SRLV,
8322 #ifndef CAPSTONE_DIET
8323  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8324 #endif
8325 },
8326 {
8327  Mips_SRLV_MM, MIPS_INS_SRLV,
8328 #ifndef CAPSTONE_DIET
8329  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8330 #endif
8331 },
8332 {
8333  Mips_SRL_B, MIPS_INS_SRL,
8334 #ifndef CAPSTONE_DIET
8335  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8336 #endif
8337 },
8338 {
8339  Mips_SRL_D, MIPS_INS_SRL,
8340 #ifndef CAPSTONE_DIET
8341  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8342 #endif
8343 },
8344 {
8345  Mips_SRL_H, MIPS_INS_SRL,
8346 #ifndef CAPSTONE_DIET
8347  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8348 #endif
8349 },
8350 {
8351  Mips_SRL_MM, MIPS_INS_SRL,
8352 #ifndef CAPSTONE_DIET
8353  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8354 #endif
8355 },
8356 {
8357  Mips_SRL_W, MIPS_INS_SRL,
8358 #ifndef CAPSTONE_DIET
8359  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8360 #endif
8361 },
8362 {
8363  Mips_SSNOP, MIPS_INS_SSNOP,
8364 #ifndef CAPSTONE_DIET
8365  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8366 #endif
8367 },
8368 {
8369  Mips_SSNOP_MM, MIPS_INS_SSNOP,
8370 #ifndef CAPSTONE_DIET
8371  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8372 #endif
8373 },
8374 {
8375  Mips_ST_B, MIPS_INS_ST,
8376 #ifndef CAPSTONE_DIET
8377  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8378 #endif
8379 },
8380 {
8381  Mips_ST_D, MIPS_INS_ST,
8382 #ifndef CAPSTONE_DIET
8383  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8384 #endif
8385 },
8386 {
8387  Mips_ST_H, MIPS_INS_ST,
8388 #ifndef CAPSTONE_DIET
8389  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8390 #endif
8391 },
8392 {
8393  Mips_ST_W, MIPS_INS_ST,
8394 #ifndef CAPSTONE_DIET
8395  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8396 #endif
8397 },
8398 {
8399  Mips_SUB, MIPS_INS_SUB,
8400 #ifndef CAPSTONE_DIET
8401  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8402 #endif
8403 },
8404 {
8405  Mips_SUBQH_PH, MIPS_INS_SUBQH,
8406 #ifndef CAPSTONE_DIET
8407  { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
8408 #endif
8409 },
8410 {
8411  Mips_SUBQH_R_PH, MIPS_INS_SUBQH_R,
8412 #ifndef CAPSTONE_DIET
8413  { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
8414 #endif
8415 },
8416 {
8417  Mips_SUBQH_R_W, MIPS_INS_SUBQH_R,
8418 #ifndef CAPSTONE_DIET
8419  { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
8420 #endif
8421 },
8422 {
8423  Mips_SUBQH_W, MIPS_INS_SUBQH,
8424 #ifndef CAPSTONE_DIET
8425  { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
8426 #endif
8427 },
8428 {
8429  Mips_SUBQ_PH, MIPS_INS_SUBQ,
8430 #ifndef CAPSTONE_DIET
8431  { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
8432 #endif
8433 },
8434 {
8435  Mips_SUBQ_S_PH, MIPS_INS_SUBQ_S,
8436 #ifndef CAPSTONE_DIET
8437  { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
8438 #endif
8439 },
8440 {
8441  Mips_SUBQ_S_W, MIPS_INS_SUBQ_S,
8442 #ifndef CAPSTONE_DIET
8443  { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
8444 #endif
8445 },
8446 {
8447  Mips_SUBSUS_U_B, MIPS_INS_SUBSUS_U,
8448 #ifndef CAPSTONE_DIET
8449  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8450 #endif
8451 },
8452 {
8453  Mips_SUBSUS_U_D, MIPS_INS_SUBSUS_U,
8454 #ifndef CAPSTONE_DIET
8455  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8456 #endif
8457 },
8458 {
8459  Mips_SUBSUS_U_H, MIPS_INS_SUBSUS_U,
8460 #ifndef CAPSTONE_DIET
8461  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8462 #endif
8463 },
8464 {
8465  Mips_SUBSUS_U_W, MIPS_INS_SUBSUS_U,
8466 #ifndef CAPSTONE_DIET
8467  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8468 #endif
8469 },
8470 {
8471  Mips_SUBSUU_S_B, MIPS_INS_SUBSUU_S,
8472 #ifndef CAPSTONE_DIET
8473  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8474 #endif
8475 },
8476 {
8477  Mips_SUBSUU_S_D, MIPS_INS_SUBSUU_S,
8478 #ifndef CAPSTONE_DIET
8479  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8480 #endif
8481 },
8482 {
8483  Mips_SUBSUU_S_H, MIPS_INS_SUBSUU_S,
8484 #ifndef CAPSTONE_DIET
8485  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8486 #endif
8487 },
8488 {
8489  Mips_SUBSUU_S_W, MIPS_INS_SUBSUU_S,
8490 #ifndef CAPSTONE_DIET
8491  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8492 #endif
8493 },
8494 {
8495  Mips_SUBS_S_B, MIPS_INS_SUBS_S,
8496 #ifndef CAPSTONE_DIET
8497  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8498 #endif
8499 },
8500 {
8501  Mips_SUBS_S_D, MIPS_INS_SUBS_S,
8502 #ifndef CAPSTONE_DIET
8503  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8504 #endif
8505 },
8506 {
8507  Mips_SUBS_S_H, MIPS_INS_SUBS_S,
8508 #ifndef CAPSTONE_DIET
8509  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8510 #endif
8511 },
8512 {
8513  Mips_SUBS_S_W, MIPS_INS_SUBS_S,
8514 #ifndef CAPSTONE_DIET
8515  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8516 #endif
8517 },
8518 {
8519  Mips_SUBS_U_B, MIPS_INS_SUBS_U,
8520 #ifndef CAPSTONE_DIET
8521  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8522 #endif
8523 },
8524 {
8525  Mips_SUBS_U_D, MIPS_INS_SUBS_U,
8526 #ifndef CAPSTONE_DIET
8527  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8528 #endif
8529 },
8530 {
8531  Mips_SUBS_U_H, MIPS_INS_SUBS_U,
8532 #ifndef CAPSTONE_DIET
8533  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8534 #endif
8535 },
8536 {
8537  Mips_SUBS_U_W, MIPS_INS_SUBS_U,
8538 #ifndef CAPSTONE_DIET
8539  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8540 #endif
8541 },
8542 {
8543  Mips_SUBU16_MM, MIPS_INS_SUBU16,
8544 #ifndef CAPSTONE_DIET
8545  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8546 #endif
8547 },
8548 {
8549  Mips_SUBUH_QB, MIPS_INS_SUBUH,
8550 #ifndef CAPSTONE_DIET
8551  { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
8552 #endif
8553 },
8554 {
8555  Mips_SUBUH_R_QB, MIPS_INS_SUBUH_R,
8556 #ifndef CAPSTONE_DIET
8557  { 0 }, { 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
8558 #endif
8559 },
8560 {
8561  Mips_SUBU_PH, MIPS_INS_SUBU,
8562 #ifndef CAPSTONE_DIET
8563  { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
8564 #endif
8565 },
8566 {
8567  Mips_SUBU_QB, MIPS_INS_SUBU,
8568 #ifndef CAPSTONE_DIET
8569  { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
8570 #endif
8571 },
8572 {
8573  Mips_SUBU_S_PH, MIPS_INS_SUBU_S,
8574 #ifndef CAPSTONE_DIET
8575  { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSPR2, 0 }, 0, 0
8576 #endif
8577 },
8578 {
8579  Mips_SUBU_S_QB, MIPS_INS_SUBU_S,
8580 #ifndef CAPSTONE_DIET
8581  { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
8582 #endif
8583 },
8584 {
8585  Mips_SUBVI_B, MIPS_INS_SUBVI,
8586 #ifndef CAPSTONE_DIET
8587  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8588 #endif
8589 },
8590 {
8591  Mips_SUBVI_D, MIPS_INS_SUBVI,
8592 #ifndef CAPSTONE_DIET
8593  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8594 #endif
8595 },
8596 {
8597  Mips_SUBVI_H, MIPS_INS_SUBVI,
8598 #ifndef CAPSTONE_DIET
8599  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8600 #endif
8601 },
8602 {
8603  Mips_SUBVI_W, MIPS_INS_SUBVI,
8604 #ifndef CAPSTONE_DIET
8605  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8606 #endif
8607 },
8608 {
8609  Mips_SUBV_B, MIPS_INS_SUBV,
8610 #ifndef CAPSTONE_DIET
8611  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8612 #endif
8613 },
8614 {
8615  Mips_SUBV_D, MIPS_INS_SUBV,
8616 #ifndef CAPSTONE_DIET
8617  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8618 #endif
8619 },
8620 {
8621  Mips_SUBV_H, MIPS_INS_SUBV,
8622 #ifndef CAPSTONE_DIET
8623  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8624 #endif
8625 },
8626 {
8627  Mips_SUBV_W, MIPS_INS_SUBV,
8628 #ifndef CAPSTONE_DIET
8629  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
8630 #endif
8631 },
8632 {
8633  Mips_SUB_MM, MIPS_INS_SUB,
8634 #ifndef CAPSTONE_DIET
8635  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8636 #endif
8637 },
8638 {
8639  Mips_SUBu, MIPS_INS_SUBU,
8640 #ifndef CAPSTONE_DIET
8641  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8642 #endif
8643 },
8644 {
8645  Mips_SUBu_MM, MIPS_INS_SUBU,
8646 #ifndef CAPSTONE_DIET
8647  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8648 #endif
8649 },
8650 {
8651  Mips_SUXC1, MIPS_INS_SUXC1,
8652 #ifndef CAPSTONE_DIET
8653  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTFP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0
8654 #endif
8655 },
8656 {
8657  Mips_SUXC164, MIPS_INS_SUXC1,
8658 #ifndef CAPSTONE_DIET
8659  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, MIPS_GRP_MIPS5_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
8660 #endif
8661 },
8662 {
8663  Mips_SUXC1_MM, MIPS_INS_SUXC1,
8664 #ifndef CAPSTONE_DIET
8665  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8666 #endif
8667 },
8668 {
8669  Mips_SW, MIPS_INS_SW,
8670 #ifndef CAPSTONE_DIET
8671  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
8672 #endif
8673 },
8674 {
8675  Mips_SW16_MM, MIPS_INS_SW16,
8676 #ifndef CAPSTONE_DIET
8677  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8678 #endif
8679 },
8680 {
8681  Mips_SW64, MIPS_INS_SW,
8682 #ifndef CAPSTONE_DIET
8683  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8684 #endif
8685 },
8686 {
8687  Mips_SWC1, MIPS_INS_SWC1,
8688 #ifndef CAPSTONE_DIET
8689  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8690 #endif
8691 },
8692 {
8693  Mips_SWC1_MM, MIPS_INS_SWC1,
8694 #ifndef CAPSTONE_DIET
8695  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8696 #endif
8697 },
8698 {
8699  Mips_SWC2, MIPS_INS_SWC2,
8700 #ifndef CAPSTONE_DIET
8701  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
8702 #endif
8703 },
8704 {
8705  Mips_SWC2_R6, MIPS_INS_SWC2,
8706 #ifndef CAPSTONE_DIET
8707  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 0, 0
8708 #endif
8709 },
8710 {
8711  Mips_SWC3, MIPS_INS_SWC3,
8712 #ifndef CAPSTONE_DIET
8713  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
8714 #endif
8715 },
8716 {
8717  Mips_SWL, MIPS_INS_SWL,
8718 #ifndef CAPSTONE_DIET
8719  { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
8720 #endif
8721 },
8722 {
8723  Mips_SWL64, MIPS_INS_SWL,
8724 #ifndef CAPSTONE_DIET
8725  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8726 #endif
8727 },
8728 {
8729  Mips_SWL_MM, MIPS_INS_SWL,
8730 #ifndef CAPSTONE_DIET
8731  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8732 #endif
8733 },
8734 {
8735  Mips_SWM16_MM, MIPS_INS_SWM16,
8736 #ifndef CAPSTONE_DIET
8737  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8738 #endif
8739 },
8740 {
8741  Mips_SWM32_MM, MIPS_INS_SWM32,
8742 #ifndef CAPSTONE_DIET
8743  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8744 #endif
8745 },
8746 {
8747  Mips_SWP_MM, MIPS_INS_SWP,
8748 #ifndef CAPSTONE_DIET
8749  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8750 #endif
8751 },
8752 {
8753  Mips_SWR, MIPS_INS_SWR,
8754 #ifndef CAPSTONE_DIET
8755  { 0 }, { 0 }, { MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
8756 #endif
8757 },
8758 {
8759  Mips_SWR64, MIPS_INS_SWR,
8760 #ifndef CAPSTONE_DIET
8761  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
8762 #endif
8763 },
8764 {
8765  Mips_SWR_MM, MIPS_INS_SWR,
8766 #ifndef CAPSTONE_DIET
8767  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8768 #endif
8769 },
8770 {
8771  Mips_SWSP_MM, MIPS_INS_SW,
8772 #ifndef CAPSTONE_DIET
8773  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8774 #endif
8775 },
8776 {
8777  Mips_SWXC1, MIPS_INS_SWXC1,
8778 #ifndef CAPSTONE_DIET
8779  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS4_32R2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, MIPS_GRP_NOTNACL, 0 }, 0, 0
8780 #endif
8781 },
8782 {
8783  Mips_SWXC1_MM, MIPS_INS_SWXC1,
8784 #ifndef CAPSTONE_DIET
8785  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8786 #endif
8787 },
8788 {
8789  Mips_SW_MM, MIPS_INS_SW,
8790 #ifndef CAPSTONE_DIET
8791  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8792 #endif
8793 },
8794 {
8795  Mips_SYNC, MIPS_INS_SYNC,
8796 #ifndef CAPSTONE_DIET
8797  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32, 0 }, 0, 0
8798 #endif
8799 },
8800 {
8801  Mips_SYNCI, MIPS_INS_SYNCI,
8802 #ifndef CAPSTONE_DIET
8803  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
8804 #endif
8805 },
8806 {
8807  Mips_SYNC_MM, MIPS_INS_SYNC,
8808 #ifndef CAPSTONE_DIET
8809  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8810 #endif
8811 },
8812 {
8813  Mips_SYSCALL, MIPS_INS_SYSCALL,
8814 #ifndef CAPSTONE_DIET
8815  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_INT, 0 }, 0, 0
8816 #endif
8817 },
8818 {
8819  Mips_SYSCALL_MM, MIPS_INS_SYSCALL,
8820 #ifndef CAPSTONE_DIET
8821  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, MIPS_GRP_INT, 0 }, 0, 0
8822 #endif
8823 },
8824 {
8825  Mips_SbRxRyOffMemX16, MIPS_INS_SB,
8826 #ifndef CAPSTONE_DIET
8827  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8828 #endif
8829 },
8830 {
8831  Mips_SebRx16, MIPS_INS_SEB,
8832 #ifndef CAPSTONE_DIET
8833  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8834 #endif
8835 },
8836 {
8837  Mips_SehRx16, MIPS_INS_SEH,
8838 #ifndef CAPSTONE_DIET
8839  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8840 #endif
8841 },
8842 {
8843  Mips_ShRxRyOffMemX16, MIPS_INS_SH,
8844 #ifndef CAPSTONE_DIET
8845  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8846 #endif
8847 },
8848 {
8849  Mips_SllX16, MIPS_INS_SLL,
8850 #ifndef CAPSTONE_DIET
8851  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8852 #endif
8853 },
8854 {
8855  Mips_SllvRxRy16, MIPS_INS_SLLV,
8856 #ifndef CAPSTONE_DIET
8857  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8858 #endif
8859 },
8860 {
8861  Mips_SltRxRy16, MIPS_INS_SLT,
8862 #ifndef CAPSTONE_DIET
8863  { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8864 #endif
8865 },
8866 {
8867  Mips_SltiRxImm16, MIPS_INS_SLTI,
8868 #ifndef CAPSTONE_DIET
8869  { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8870 #endif
8871 },
8872 {
8873  Mips_SltiRxImmX16, MIPS_INS_SLTI,
8874 #ifndef CAPSTONE_DIET
8875  { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8876 #endif
8877 },
8878 {
8879  Mips_SltiuRxImm16, MIPS_INS_SLTIU,
8880 #ifndef CAPSTONE_DIET
8881  { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8882 #endif
8883 },
8884 {
8885  Mips_SltiuRxImmX16, MIPS_INS_SLTIU,
8886 #ifndef CAPSTONE_DIET
8887  { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8888 #endif
8889 },
8890 {
8891  Mips_SltuRxRy16, MIPS_INS_SLTU,
8892 #ifndef CAPSTONE_DIET
8893  { 0 }, { MIPS_REG_T8, 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8894 #endif
8895 },
8896 {
8897  Mips_SraX16, MIPS_INS_SRA,
8898 #ifndef CAPSTONE_DIET
8899  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8900 #endif
8901 },
8902 {
8903  Mips_SravRxRy16, MIPS_INS_SRAV,
8904 #ifndef CAPSTONE_DIET
8905  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8906 #endif
8907 },
8908 {
8909  Mips_SrlX16, MIPS_INS_SRL,
8910 #ifndef CAPSTONE_DIET
8911  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8912 #endif
8913 },
8914 {
8915  Mips_SrlvRxRy16, MIPS_INS_SRLV,
8916 #ifndef CAPSTONE_DIET
8917  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8918 #endif
8919 },
8920 {
8921  Mips_SubuRxRyRz16, MIPS_INS_SUBU,
8922 #ifndef CAPSTONE_DIET
8923  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8924 #endif
8925 },
8926 {
8927  Mips_SwRxRyOffMemX16, MIPS_INS_SW,
8928 #ifndef CAPSTONE_DIET
8929  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8930 #endif
8931 },
8932 {
8933  Mips_SwRxSpImmX16, MIPS_INS_SW,
8934 #ifndef CAPSTONE_DIET
8935  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
8936 #endif
8937 },
8938 {
8939  Mips_TEQ, MIPS_INS_TEQ,
8940 #ifndef CAPSTONE_DIET
8941  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
8942 #endif
8943 },
8944 {
8945  Mips_TEQI, MIPS_INS_TEQI,
8946 #ifndef CAPSTONE_DIET
8947  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
8948 #endif
8949 },
8950 {
8951  Mips_TEQI_MM, MIPS_INS_TEQI,
8952 #ifndef CAPSTONE_DIET
8953  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8954 #endif
8955 },
8956 {
8957  Mips_TEQ_MM, MIPS_INS_TEQ,
8958 #ifndef CAPSTONE_DIET
8959  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8960 #endif
8961 },
8962 {
8963  Mips_TGE, MIPS_INS_TGE,
8964 #ifndef CAPSTONE_DIET
8965  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
8966 #endif
8967 },
8968 {
8969  Mips_TGEI, MIPS_INS_TGEI,
8970 #ifndef CAPSTONE_DIET
8971  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
8972 #endif
8973 },
8974 {
8975  Mips_TGEIU, MIPS_INS_TGEIU,
8976 #ifndef CAPSTONE_DIET
8977  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
8978 #endif
8979 },
8980 {
8981  Mips_TGEIU_MM, MIPS_INS_TGEIU,
8982 #ifndef CAPSTONE_DIET
8983  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8984 #endif
8985 },
8986 {
8987  Mips_TGEI_MM, MIPS_INS_TGEI,
8988 #ifndef CAPSTONE_DIET
8989  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
8990 #endif
8991 },
8992 {
8993  Mips_TGEU, MIPS_INS_TGEU,
8994 #ifndef CAPSTONE_DIET
8995  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
8996 #endif
8997 },
8998 {
8999  Mips_TGEU_MM, MIPS_INS_TGEU,
9000 #ifndef CAPSTONE_DIET
9001  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
9002 #endif
9003 },
9004 {
9005  Mips_TGE_MM, MIPS_INS_TGE,
9006 #ifndef CAPSTONE_DIET
9007  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
9008 #endif
9009 },
9010 {
9011  Mips_TLBP, MIPS_INS_TLBP,
9012 #ifndef CAPSTONE_DIET
9013  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
9014 #endif
9015 },
9016 {
9017  Mips_TLBP_MM, MIPS_INS_TLBP,
9018 #ifndef CAPSTONE_DIET
9019  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
9020 #endif
9021 },
9022 {
9023  Mips_TLBR, MIPS_INS_TLBR,
9024 #ifndef CAPSTONE_DIET
9025  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
9026 #endif
9027 },
9028 {
9029  Mips_TLBR_MM, MIPS_INS_TLBR,
9030 #ifndef CAPSTONE_DIET
9031  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
9032 #endif
9033 },
9034 {
9035  Mips_TLBWI, MIPS_INS_TLBWI,
9036 #ifndef CAPSTONE_DIET
9037  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
9038 #endif
9039 },
9040 {
9041  Mips_TLBWI_MM, MIPS_INS_TLBWI,
9042 #ifndef CAPSTONE_DIET
9043  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
9044 #endif
9045 },
9046 {
9047  Mips_TLBWR, MIPS_INS_TLBWR,
9048 #ifndef CAPSTONE_DIET
9049  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
9050 #endif
9051 },
9052 {
9053  Mips_TLBWR_MM, MIPS_INS_TLBWR,
9054 #ifndef CAPSTONE_DIET
9055  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
9056 #endif
9057 },
9058 {
9059  Mips_TLT, MIPS_INS_TLT,
9060 #ifndef CAPSTONE_DIET
9061  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
9062 #endif
9063 },
9064 {
9065  Mips_TLTI, MIPS_INS_TLTI,
9066 #ifndef CAPSTONE_DIET
9067  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
9068 #endif
9069 },
9070 {
9071  Mips_TLTIU_MM, MIPS_INS_TLTIU,
9072 #ifndef CAPSTONE_DIET
9073  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
9074 #endif
9075 },
9076 {
9077  Mips_TLTI_MM, MIPS_INS_TLTI,
9078 #ifndef CAPSTONE_DIET
9079  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
9080 #endif
9081 },
9082 {
9083  Mips_TLTU, MIPS_INS_TLTU,
9084 #ifndef CAPSTONE_DIET
9085  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
9086 #endif
9087 },
9088 {
9089  Mips_TLTU_MM, MIPS_INS_TLTU,
9090 #ifndef CAPSTONE_DIET
9091  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
9092 #endif
9093 },
9094 {
9095  Mips_TLT_MM, MIPS_INS_TLT,
9096 #ifndef CAPSTONE_DIET
9097  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
9098 #endif
9099 },
9100 {
9101  Mips_TNE, MIPS_INS_TNE,
9102 #ifndef CAPSTONE_DIET
9103  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
9104 #endif
9105 },
9106 {
9107  Mips_TNEI, MIPS_INS_TNEI,
9108 #ifndef CAPSTONE_DIET
9109  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
9110 #endif
9111 },
9112 {
9113  Mips_TNEI_MM, MIPS_INS_TNEI,
9114 #ifndef CAPSTONE_DIET
9115  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
9116 #endif
9117 },
9118 {
9119  Mips_TNE_MM, MIPS_INS_TNE,
9120 #ifndef CAPSTONE_DIET
9121  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
9122 #endif
9123 },
9124 {
9125  Mips_TRUNC_L_D64, MIPS_INS_TRUNC,
9126 #ifndef CAPSTONE_DIET
9127  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
9128 #endif
9129 },
9130 {
9131  Mips_TRUNC_L_S, MIPS_INS_TRUNC,
9132 #ifndef CAPSTONE_DIET
9133  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_FP64BIT, 0 }, 0, 0
9134 #endif
9135 },
9136 {
9137  Mips_TRUNC_W_D32, MIPS_INS_TRUNC,
9138 #ifndef CAPSTONE_DIET
9139  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTFP64BIT, 0 }, 0, 0
9140 #endif
9141 },
9142 {
9143  Mips_TRUNC_W_D64, MIPS_INS_TRUNC,
9144 #ifndef CAPSTONE_DIET
9145  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_FP64BIT, 0 }, 0, 0
9146 #endif
9147 },
9148 {
9149  Mips_TRUNC_W_MM, MIPS_INS_TRUNC,
9150 #ifndef CAPSTONE_DIET
9151  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
9152 #endif
9153 },
9154 {
9155  Mips_TRUNC_W_S, MIPS_INS_TRUNC,
9156 #ifndef CAPSTONE_DIET
9157  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, 0 }, 0, 0
9158 #endif
9159 },
9160 {
9161  Mips_TRUNC_W_S_MM, MIPS_INS_TRUNC,
9162 #ifndef CAPSTONE_DIET
9163  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
9164 #endif
9165 },
9166 {
9167  Mips_TTLTIU, MIPS_INS_TLTIU,
9168 #ifndef CAPSTONE_DIET
9169  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
9170 #endif
9171 },
9172 {
9173  Mips_UDIV, MIPS_INS_DIVU,
9174 #ifndef CAPSTONE_DIET
9175  { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
9176 #endif
9177 },
9178 {
9179  Mips_UDIV_MM, MIPS_INS_DIVU,
9180 #ifndef CAPSTONE_DIET
9181  { 0 }, { MIPS_REG_HI0, MIPS_REG_LO0, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
9182 #endif
9183 },
9184 {
9185  Mips_V3MULU, MIPS_INS_V3MULU,
9186 #ifndef CAPSTONE_DIET
9187  { 0 }, { MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
9188 #endif
9189 },
9190 {
9191  Mips_VMM0, MIPS_INS_VMM0,
9192 #ifndef CAPSTONE_DIET
9193  { 0 }, { MIPS_REG_MPL0, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
9194 #endif
9195 },
9196 {
9197  Mips_VMULU, MIPS_INS_VMULU,
9198 #ifndef CAPSTONE_DIET
9199  { 0 }, { MIPS_REG_MPL1, MIPS_REG_MPL2, MIPS_REG_P0, MIPS_REG_P1, MIPS_REG_P2, 0 }, { MIPS_GRP_CNMIPS, 0 }, 0, 0
9200 #endif
9201 },
9202 {
9203  Mips_VSHF_B, MIPS_INS_VSHF,
9204 #ifndef CAPSTONE_DIET
9205  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
9206 #endif
9207 },
9208 {
9209  Mips_VSHF_D, MIPS_INS_VSHF,
9210 #ifndef CAPSTONE_DIET
9211  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
9212 #endif
9213 },
9214 {
9215  Mips_VSHF_H, MIPS_INS_VSHF,
9216 #ifndef CAPSTONE_DIET
9217  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
9218 #endif
9219 },
9220 {
9221  Mips_VSHF_W, MIPS_INS_VSHF,
9222 #ifndef CAPSTONE_DIET
9223  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
9224 #endif
9225 },
9226 {
9227  Mips_WAIT, MIPS_INS_WAIT,
9228 #ifndef CAPSTONE_DIET
9229  { 0 }, { 0 }, { MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
9230 #endif
9231 },
9232 {
9233  Mips_WAIT_MM, MIPS_INS_WAIT,
9234 #ifndef CAPSTONE_DIET
9235  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
9236 #endif
9237 },
9238 {
9239  Mips_WRDSP, MIPS_INS_WRDSP,
9240 #ifndef CAPSTONE_DIET
9241  { 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
9242 #endif
9243 },
9244 {
9245  Mips_WSBH, MIPS_INS_WSBH,
9246 #ifndef CAPSTONE_DIET
9247  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R2, 0 }, 0, 0
9248 #endif
9249 },
9250 {
9251  Mips_WSBH_MM, MIPS_INS_WSBH,
9252 #ifndef CAPSTONE_DIET
9253  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
9254 #endif
9255 },
9256 {
9257  Mips_XOR, MIPS_INS_XOR,
9258 #ifndef CAPSTONE_DIET
9259  { 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTINMICROMIPS, 0 }, 0, 0
9260 #endif
9261 },
9262 {
9263  Mips_XOR16_MM, MIPS_INS_XOR16,
9264 #ifndef CAPSTONE_DIET
9265  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
9266 #endif
9267 },
9268 {
9269  Mips_XOR64, MIPS_INS_XOR,
9270 #ifndef CAPSTONE_DIET
9271  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
9272 #endif
9273 },
9274 {
9275  Mips_XORI_B, MIPS_INS_XORI,
9276 #ifndef CAPSTONE_DIET
9277  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
9278 #endif
9279 },
9280 {
9281  Mips_XOR_MM, MIPS_INS_XOR,
9282 #ifndef CAPSTONE_DIET
9283  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
9284 #endif
9285 },
9286 {
9287  Mips_XOR_V, MIPS_INS_XOR,
9288 #ifndef CAPSTONE_DIET
9289  { 0 }, { 0 }, { MIPS_GRP_MSA, 0 }, 0, 0
9290 #endif
9291 },
9292 {
9293  Mips_XORi, MIPS_INS_XORI,
9294 #ifndef CAPSTONE_DIET
9295  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
9296 #endif
9297 },
9298 {
9299  Mips_XORi64, MIPS_INS_XORI,
9300 #ifndef CAPSTONE_DIET
9301  { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0
9302 #endif
9303 },
9304 {
9305  Mips_XORi_MM, MIPS_INS_XORI,
9306 #ifndef CAPSTONE_DIET
9307  { 0 }, { 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
9308 #endif
9309 },
9310 {
9311  Mips_XorRxRxRy16, MIPS_INS_XOR,
9312 #ifndef CAPSTONE_DIET
9313  { 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
9314 #endif
9315 },
MIPS_INS_MTP0
@ MIPS_INS_MTP0
Definition: analysis_mips_gnu.c:507
MIPS_INS_HSUB_S
@ MIPS_INS_HSUB_S
Definition: analysis_mips_gnu.c:388
MIPS_INS_PRECR_SRA
@ MIPS_INS_PRECR_SRA
Definition: analysis_mips_gnu.c:550
MIPS_INS_EXTPDPV
@ MIPS_INS_EXTPDPV
Definition: analysis_mips_gnu.c:315
MIPS_INS_ABSQ_S
@ MIPS_INS_ABSQ_S
Definition: analysis_mips_gnu.c:63
MIPS_INS_JRADDIUSP
@ MIPS_INS_JRADDIUSP
Definition: analysis_mips_gnu.c:409
MIPS_INS_DDIVU
@ MIPS_INS_DDIVU
Definition: analysis_mips_gnu.c:244
MIPS_INS_EXTPDP
@ MIPS_INS_EXTPDP
Definition: analysis_mips_gnu.c:314
MIPS_INS_PRECEU
@ MIPS_INS_PRECEU
Definition: analysis_mips_gnu.c:545
MIPS_INS_SHLL
@ MIPS_INS_SHLL
Definition: analysis_mips_gnu.c:592
MIPS_INS_MTHLIP
@ MIPS_INS_MTHLIP
Definition: analysis_mips_gnu.c:502
MIPS_INS_ADDS_A
@ MIPS_INS_ADDS_A
Definition: analysis_mips_gnu.c:75
MIPS_INS_SELEQZ
@ MIPS_INS_SELEQZ
Definition: analysis_mips_gnu.c:580
MIPS_INS_DMUH
@ MIPS_INS_DMUH
Definition: analysis_mips_gnu.c:266
MIPS_INS_ILVL
@ MIPS_INS_ILVL
Definition: analysis_mips_gnu.c:391
MIPS_INS_BINSR
@ MIPS_INS_BINSR
Definition: analysis_mips_gnu.c:158
MIPS_INS_DPAQX_S
@ MIPS_INS_DPAQX_S
Definition: analysis_mips_gnu.c:277
MIPS_INS_TLBP
@ MIPS_INS_TLBP
Definition: analysis_mips_gnu.c:663
MIPS_INS_FFQR
@ MIPS_INS_FFQR
Definition: analysis_mips_gnu.c:349
MIPS_INS_AUIPC
@ MIPS_INS_AUIPC
Definition: analysis_mips_gnu.c:99
MIPS_INS_BEQZC
@ MIPS_INS_BEQZC
Definition: analysis_mips_gnu.c:141
MIPS_INS_CMPU
@ MIPS_INS_CMPU
Definition: analysis_mips_gnu.c:223
MIPS_INS_BGEZL
@ MIPS_INS_BGEZL
Definition: analysis_mips_gnu.c:150
MIPS_INS_XORI
@ MIPS_INS_XORI
Definition: analysis_mips_gnu.c:683
MIPS_INS_DPSQX_S
@ MIPS_INS_DPSQX_S
Definition: analysis_mips_gnu.c:285
MIPS_INS_MSUB
@ MIPS_INS_MSUB
Definition: analysis_mips_gnu.c:491
MIPS_INS_ADDV
@ MIPS_INS_ADDV
Definition: analysis_mips_gnu.c:84
MIPS_INS_MIN_U
@ MIPS_INS_MIN_U
Definition: analysis_mips_gnu.c:479
MIPS_INS_AUI
@ MIPS_INS_AUI
Definition: analysis_mips_gnu.c:98
MIPS_INS_FLOG2
@ MIPS_INS_FLOG2
Definition: analysis_mips_gnu.c:351
MIPS_INS_TGEIU
@ MIPS_INS_TGEIU
Definition: analysis_mips_gnu.c:661
MIPS_INS_BLTZ
@ MIPS_INS_BLTZ
Definition: analysis_mips_gnu.c:167
MIPS_INS_FMSUB
@ MIPS_INS_FMSUB
Definition: analysis_mips_gnu.c:359
MIPS_INS_DPADD_U
@ MIPS_INS_DPADD_U
Definition: analysis_mips_gnu.c:275
MIPS_INS_FFINT_U
@ MIPS_INS_FFINT_U
Definition: analysis_mips_gnu.c:347
MIPS_INS_ADDU_S
@ MIPS_INS_ADDU_S
Definition: analysis_mips_gnu.c:82
MIPS_INS_LDC1
@ MIPS_INS_LDC1
Definition: analysis_mips_gnu.c:417
MIPS_INS_DPA
@ MIPS_INS_DPA
Definition: analysis_mips_gnu.c:282
MIPS_INS_HADD_S
@ MIPS_INS_HADD_S
Definition: analysis_mips_gnu.c:386
MIPS_INS_FRCP
@ MIPS_INS_FRCP
Definition: analysis_mips_gnu.c:363
MIPS_INS_SEH
@ MIPS_INS_SEH
Definition: analysis_mips_gnu.c:579
MIPS_INS_BNEC
@ MIPS_INS_BNEC
Definition: analysis_mips_gnu.c:179
MIPS_INS_FSLT
@ MIPS_INS_FSLT
Definition: analysis_mips_gnu.c:369
MIPS_INS_DMUL
@ MIPS_INS_DMUL
Definition: analysis_mips_gnu.c:268
MIPS_INS_DSRL32
@ MIPS_INS_DSRL32
Definition: analysis_mips_gnu.c:305
MIPS_INS_LDPC
@ MIPS_INS_LDPC
Definition: analysis_mips_gnu.c:422
MIPS_INS_SNE
@ MIPS_INS_SNE
Definition: analysis_mips_gnu.c:610
MIPS_INS_FSOR
@ MIPS_INS_FSOR
Definition: analysis_mips_gnu.c:371
MIPS_INS_SHRA
@ MIPS_INS_SHRA
Definition: analysis_mips_gnu.c:596
MIPS_INS_BGTZ
@ MIPS_INS_BGTZ
Definition: analysis_mips_gnu.c:151
MIPS_INS_INSERT
@ MIPS_INS_INSERT
Definition: analysis_mips_gnu.c:395
MIPS_INS_BBIT032
@ MIPS_INS_BBIT032
Definition: analysis_mips_gnu.c:110
MIPS_INS_DMULT
@ MIPS_INS_DMULT
Definition: analysis_mips_gnu.c:269
MIPS_INS_FCULT
@ MIPS_INS_FCULT
Definition: analysis_mips_gnu.c:338
MIPS_INS_FTRUNC_S
@ MIPS_INS_FTRUNC_S
Definition: analysis_mips_gnu.c:384
MIPS_INS_SYNCI
@ MIPS_INS_SYNCI
Definition: analysis_mips_gnu.c:655
MIPS_INS_DMFC1
@ MIPS_INS_DMFC1
Definition: analysis_mips_gnu.c:259
MIPS_INS_EXTP
@ MIPS_INS_EXTP
Definition: analysis_mips_gnu.c:313
MIPS_INS_MOV
@ MIPS_INS_MOV
Definition: analysis_mips_gnu.c:358
MIPS_INS_TEQ
@ MIPS_INS_TEQ
Definition: analysis_mips_gnu.c:657
MIPS_INS_DMTC1
@ MIPS_INS_DMTC1
Definition: analysis_mips_gnu.c:264
MIPS_INS_BC3T
@ MIPS_INS_BC3T
Definition: analysis_mips_gnu.c:132
MIPS_INS_BLTZALC
@ MIPS_INS_BLTZALC
Definition: analysis_mips_gnu.c:169
MIPS_INS_SAT_S
@ MIPS_INS_SAT_S
Definition: analysis_mips_gnu.c:563
MIPS_INS_BLTUC
@ MIPS_INS_BLTUC
Definition: analysis_mips_gnu.c:166
MIPS_INS_SUBQH
@ MIPS_INS_SUBQH
Definition: analysis_mips_gnu.c:627
MIPS_INS_LI
@ MIPS_INS_LI
Definition: analysis_mips_gnu.c:451
MIPS_INS_SWP
@ MIPS_INS_SWP
Definition: analysis_mips_gnu.c:651
MIPS_INS_ALUIPC
@ MIPS_INS_ALUIPC
Definition: analysis_mips_gnu.c:90
MIPS_INS_FCLT
@ MIPS_INS_FCLT
Definition: analysis_mips_gnu.c:333
MIPS_INS_SELNEZ
@ MIPS_INS_SELNEZ
Definition: analysis_mips_gnu.c:581
MIPS_INS_FSEQ
@ MIPS_INS_FSEQ
Definition: analysis_mips_gnu.c:367
MIPS_INS_CEQI
@ MIPS_INS_CEQI
Definition: analysis_mips_gnu.c:204
MIPS_INS_DROTR
@ MIPS_INS_DROTR
Definition: analysis_mips_gnu.c:293
MIPS_INS_ST
@ MIPS_INS_ST
Definition: analysis_mips_gnu.c:626
MIPS_INS_WAIT
@ MIPS_INS_WAIT
Definition: analysis_mips_gnu.c:678
MIPS_INS_FSUN
@ MIPS_INS_FSUN
Definition: analysis_mips_gnu.c:380
MIPS_INS_CMPGDU
@ MIPS_INS_CMPGDU
Definition: analysis_mips_gnu.c:221
MIPS_INS_MSUBU
@ MIPS_INS_MSUBU
Definition: analysis_mips_gnu.c:494
MIPS_INS_BLTZALL
@ MIPS_INS_BLTZALL
Definition: analysis_mips_gnu.c:170
MIPS_INS_ADDUH_R
@ MIPS_INS_ADDUH_R
Definition: analysis_mips_gnu.c:80
MIPS_INS_BC1T
@ MIPS_INS_BC1T
Definition: analysis_mips_gnu.c:122
MIPS_INS_SWL
@ MIPS_INS_SWL
Definition: analysis_mips_gnu.c:648
MIPS_INS_BC1EQZ
@ MIPS_INS_BC1EQZ
Definition: analysis_mips_gnu.c:118
MIPS_INS_SLT
@ MIPS_INS_SLT
Definition: analysis_mips_gnu.c:606
MIPS_INS_PREF
@ MIPS_INS_PREF
Definition: analysis_mips_gnu.c:552
MIPS_INS_ILVEV
@ MIPS_INS_ILVEV
Definition: analysis_mips_gnu.c:390
MIPS_INS_DPS
@ MIPS_INS_DPS
Definition: analysis_mips_gnu.c:292
MIPS_INS_SWC1
@ MIPS_INS_SWC1
Definition: analysis_mips_gnu.c:645
MIPS_INS_BMZI
@ MIPS_INS_BMZI
Definition: analysis_mips_gnu.c:176
MIPS_INS_SUBU16
@ MIPS_INS_SUBU16
Definition: analysis_mips_gnu.c:635
MIPS_INS_MOVN
@ MIPS_INS_MOVN
Definition: analysis_mips_gnu.c:488
MIPS_INS_BNE
@ MIPS_INS_BNE
Definition: analysis_mips_gnu.c:178
MIPS_INS_MSUBF
@ MIPS_INS_MSUBF
Definition: analysis_mips_gnu.c:492
MIPS_INS_DPAQ_SA
@ MIPS_INS_DPAQ_SA
Definition: analysis_mips_gnu.c:278
MIPS_INS_SPLAT
@ MIPS_INS_SPLAT
Definition: analysis_mips_gnu.c:613
MIPS_INS_BMNZI
@ MIPS_INS_BMNZI
Definition: analysis_mips_gnu.c:174
MIPS_INS_DSRA
@ MIPS_INS_DSRA
Definition: analysis_mips_gnu.c:301
MIPS_INS_BGTZC
@ MIPS_INS_BGTZC
Definition: analysis_mips_gnu.c:153
MIPS_INS_MOVF
@ MIPS_INS_MOVF
Definition: analysis_mips_gnu.c:487
MIPS_INS_DINS
@ MIPS_INS_DINS
Definition: analysis_mips_gnu.c:250
MIPS_INS_INS
@ MIPS_INS_INS
Definition: analysis_mips_gnu.c:394
MIPS_INS_FTINT_U
@ MIPS_INS_FTINT_U
Definition: analysis_mips_gnu.c:382
MIPS_INS_BREAK
@ MIPS_INS_BREAK
Definition: analysis_mips_gnu.c:190
MIPS_INS_CLO
@ MIPS_INS_CLO
Definition: analysis_mips_gnu.c:215
MIPS_INS_LDC2
@ MIPS_INS_LDC2
Definition: analysis_mips_gnu.c:418
MIPS_INS_EXTR_S
@ MIPS_INS_EXTR_S
Definition: analysis_mips_gnu.c:323
MIPS_INS_VSHF
@ MIPS_INS_VSHF
Definition: analysis_mips_gnu.c:677
MIPS_INS_FEXUPL
@ MIPS_INS_FEXUPL
Definition: analysis_mips_gnu.c:344
MIPS_INS_LWM16
@ MIPS_INS_LWM16
Definition: analysis_mips_gnu.c:441
MIPS_INS_SDC2
@ MIPS_INS_SDC2
Definition: analysis_mips_gnu.c:573
MIPS_INS_SHLL_S
@ MIPS_INS_SHLL_S
Definition: analysis_mips_gnu.c:593
MIPS_INS_FSLE
@ MIPS_INS_FSLE
Definition: analysis_mips_gnu.c:368
MIPS_INS_LDL
@ MIPS_INS_LDL
Definition: analysis_mips_gnu.c:421
MIPS_INS_DPOP
@ MIPS_INS_DPOP
Definition: analysis_mips_gnu.c:283
MIPS_INS_SHILOV
@ MIPS_INS_SHILOV
Definition: analysis_mips_gnu.c:589
MIPS_INS_EI
@ MIPS_INS_EI
Definition: analysis_mips_gnu.c:310
MIPS_INS_SYNC
@ MIPS_INS_SYNC
Definition: analysis_mips_gnu.c:654
MIPS_INS_LWUPC
@ MIPS_INS_LWUPC
Definition: analysis_mips_gnu.c:446
MIPS_INS_ADDVI
@ MIPS_INS_ADDVI
Definition: analysis_mips_gnu.c:83
MIPS_INS_ILVR
@ MIPS_INS_ILVR
Definition: analysis_mips_gnu.c:393
MIPS_INS_FCUN
@ MIPS_INS_FCUN
Definition: analysis_mips_gnu.c:340
MIPS_INS_BITREV
@ MIPS_INS_BITREV
Definition: analysis_mips_gnu.c:159
MIPS_INS_SWC3
@ MIPS_INS_SWC3
Definition: analysis_mips_gnu.c:647
MIPS_INS_SDXC1
@ MIPS_INS_SDXC1
Definition: analysis_mips_gnu.c:577
MIPS_INS_SW
@ MIPS_INS_SW
Definition: analysis_mips_gnu.c:643
MIPS_INS_BC2F
@ MIPS_INS_BC2F
Definition: analysis_mips_gnu.c:125
MIPS_INS_DINSM
@ MIPS_INS_DINSM
Definition: analysis_mips_gnu.c:251
MIPS_INS_BNZ
@ MIPS_INS_BNZ
Definition: analysis_mips_gnu.c:187
MIPS_INS_C
@ MIPS_INS_C
Definition: analysis_mips_gnu.c:230
MIPS_INS_JIALC
@ MIPS_INS_JIALC
Definition: analysis_mips_gnu.c:405
MIPS_INS_DPSQ_S
@ MIPS_INS_DPSQ_S
Definition: analysis_mips_gnu.c:287
MIPS_INS_BSETI
@ MIPS_INS_BSETI
Definition: analysis_mips_gnu.c:194
MIPS_INS_NMADD
@ MIPS_INS_NMADD
Definition: analysis_mips_gnu.c:527
MIPS_INS_EXTPV
@ MIPS_INS_EXTPV
Definition: analysis_mips_gnu.c:316
MIPS_INS_LDC3
@ MIPS_INS_LDC3
Definition: analysis_mips_gnu.c:419
MIPS_INS_LW16
@ MIPS_INS_LW16
Definition: analysis_mips_gnu.c:436
MIPS_INS_NLOC
@ MIPS_INS_NLOC
Definition: analysis_mips_gnu.c:525
MIPS_INS_LWP
@ MIPS_INS_LWP
Definition: analysis_mips_gnu.c:444
MIPS_INS_EXTS32
@ MIPS_INS_EXTS32
Definition: analysis_mips_gnu.c:326
MIPS_INS_SWM16
@ MIPS_INS_SWM16
Definition: analysis_mips_gnu.c:649
MIPS_INS_CLTI_U
@ MIPS_INS_CLTI_U
Definition: analysis_mips_gnu.c:217
MIPS_INS_SRLI
@ MIPS_INS_SRLI
Definition: analysis_mips_gnu.c:621
MIPS_INS_PCKEV
@ MIPS_INS_PCKEV
Definition: analysis_mips_gnu.c:538
MIPS_INS_FFQL
@ MIPS_INS_FFQL
Definition: analysis_mips_gnu.c:348
MIPS_INS_DCLZ
@ MIPS_INS_DCLZ
Definition: analysis_mips_gnu.c:242
MIPS_INS_MFHC1
@ MIPS_INS_MFHC1
Definition: analysis_mips_gnu.c:470
MIPS_INS_FCUNE
@ MIPS_INS_FCUNE
Definition: analysis_mips_gnu.c:339
MIPS_INS_ADDUH
@ MIPS_INS_ADDUH
Definition: analysis_mips_gnu.c:79
MIPS_INS_MOVEP
@ MIPS_INS_MOVEP
Definition: analysis_mips_gnu.c:486
MIPS_INS_ORI
@ MIPS_INS_ORI
Definition: analysis_mips_gnu.c:535
MIPS_INS_LUI
@ MIPS_INS_LUI
Definition: analysis_mips_gnu.c:434
MIPS_INS_BLTZALS
@ MIPS_INS_BLTZALS
Definition: analysis_mips_gnu.c:171
MIPS_INS_DIV_S
@ MIPS_INS_DIV_S
Definition: analysis_mips_gnu.c:255
MIPS_INS_BBIT0
@ MIPS_INS_BBIT0
Definition: analysis_mips_gnu.c:109
MIPS_INS_CMPGU
@ MIPS_INS_CMPGU
Definition: analysis_mips_gnu.c:222
MIPS_INS_TGEU
@ MIPS_INS_TGEU
Definition: analysis_mips_gnu.c:662
MIPS_INS_SH16
@ MIPS_INS_SH16
Definition: analysis_mips_gnu.c:586
MIPS_INS_BEQL
@ MIPS_INS_BEQL
Definition: analysis_mips_gnu.c:138
MIPS_INS_BC0F
@ MIPS_INS_BC0F
Definition: analysis_mips_gnu.c:114
MIPS_INS_BGEZALC
@ MIPS_INS_BGEZALC
Definition: analysis_mips_gnu.c:146
MIPS_INS_REPLV
@ MIPS_INS_REPLV
Definition: analysis_mips_gnu.c:557
MIPS_INS_BLEZALC
@ MIPS_INS_BLEZALC
Definition: analysis_mips_gnu.c:162
MIPS_INS_JALRS
@ MIPS_INS_JALRS
Definition: analysis_mips_gnu.c:402
MIPS_INS_MAX_A
@ MIPS_INS_MAX_A
Definition: analysis_mips_gnu.c:463
MIPS_INS_SC
@ MIPS_INS_SC
Definition: analysis_mips_gnu.c:567
MIPS_INS_ROTR
@ MIPS_INS_ROTR
Definition: analysis_mips_gnu.c:560
MIPS_INS_FSAF
@ MIPS_INS_FSAF
Definition: analysis_mips_gnu.c:366
MIPS_INS_BPOSGE32
@ MIPS_INS_BPOSGE32
Definition: analysis_mips_gnu.c:189
MIPS_INS_FTRUNC_U
@ MIPS_INS_FTRUNC_U
Definition: analysis_mips_gnu.c:385
MIPS_INS_CLT_S
@ MIPS_INS_CLT_S
Definition: analysis_mips_gnu.c:218
MIPS_INS_DSUBU
@ MIPS_INS_DSUBU
Definition: analysis_mips_gnu.c:308
MIPS_INS_LWL
@ MIPS_INS_LWL
Definition: analysis_mips_gnu.c:440
MIPS_INS_FCUEQ
@ MIPS_INS_FCUEQ
Definition: analysis_mips_gnu.c:336
MIPS_INS_SWXC1
@ MIPS_INS_SWXC1
Definition: analysis_mips_gnu.c:653
MIPS_INS_FMAX_A
@ MIPS_INS_FMAX_A
Definition: analysis_mips_gnu.c:354
MIPS_INS_LI16
@ MIPS_INS_LI16
Definition: analysis_mips_gnu.c:429
MIPS_INS_FMUL
@ MIPS_INS_FMUL
Definition: analysis_mips_gnu.c:360
MIPS_INS_CLASS
@ MIPS_INS_CLASS
Definition: analysis_mips_gnu.c:210
MIPS_INS_INSVE
@ MIPS_INS_INSVE
Definition: analysis_mips_gnu.c:397
MIPS_INS_BOVC
@ MIPS_INS_BOVC
Definition: analysis_mips_gnu.c:188
MIPS_INS_SUBUH
@ MIPS_INS_SUBUH
Definition: analysis_mips_gnu.c:636
MIPS_INS_DPSQ_SA
@ MIPS_INS_DPSQ_SA
Definition: analysis_mips_gnu.c:286
MIPS_INS_ADDS_U
@ MIPS_INS_ADDS_U
Definition: analysis_mips_gnu.c:77
MIPS_INS_MUL
@ MIPS_INS_MUL
Definition: analysis_mips_gnu.c:361
MIPS_INS_CFCMSA
@ MIPS_INS_CFCMSA
Definition: analysis_mips_gnu.c:207
MIPS_INS_BNEG
@ MIPS_INS_BNEG
Definition: analysis_mips_gnu.c:181
MIPS_INS_DIV_U
@ MIPS_INS_DIV_U
Definition: analysis_mips_gnu.c:256
MIPS_INS_MADD
@ MIPS_INS_MADD
Definition: analysis_mips_gnu.c:452
MIPS_INS_PRECR
@ MIPS_INS_PRECR
Definition: analysis_mips_gnu.c:549
MIPS_INS_SUBQ_S
@ MIPS_INS_SUBQ_S
Definition: analysis_mips_gnu.c:630
MIPS_INS_MSUBR_Q
@ MIPS_INS_MSUBR_Q
Definition: analysis_mips_gnu.c:493
MIPS_INS_MADDV
@ MIPS_INS_MADDV
Definition: analysis_mips_gnu.c:456
MIPS_INS_FCAF
@ MIPS_INS_FCAF
Definition: analysis_mips_gnu.c:329
MIPS_INS_SDL
@ MIPS_INS_SDL
Definition: analysis_mips_gnu.c:575
MIPS_INS_MIN_S
@ MIPS_INS_MIN_S
Definition: analysis_mips_gnu.c:478
MIPS_INS_AND16
@ MIPS_INS_AND16
Definition: analysis_mips_gnu.c:92
MIPS_INS_FLOOR
@ MIPS_INS_FLOOR
Definition: analysis_mips_gnu.c:352
MIPS_INS_MAXA
@ MIPS_INS_MAXA
Definition: analysis_mips_gnu.c:460
MIPS_INS_SH
@ MIPS_INS_SH
Definition: analysis_mips_gnu.c:585
MIPS_INS_MTHI
@ MIPS_INS_MTHI
Definition: analysis_mips_gnu.c:501
MIPS_INS_BNEZALC
@ MIPS_INS_BNEZALC
Definition: analysis_mips_gnu.c:184
MIPS_INS_HSUB_U
@ MIPS_INS_HSUB_U
Definition: analysis_mips_gnu.c:389
MIPS_INS_BNEGI
@ MIPS_INS_BNEGI
Definition: analysis_mips_gnu.c:180
MIPS_INS_SHRLV
@ MIPS_INS_SHRLV
Definition: analysis_mips_gnu.c:598
MIPS_INS_CVT
@ MIPS_INS_CVT
Definition: analysis_mips_gnu.c:229
MIPS_INS_SUXC1
@ MIPS_INS_SUXC1
Definition: analysis_mips_gnu.c:642
MIPS_INS_SQRT
@ MIPS_INS_SQRT
Definition: analysis_mips_gnu.c:373
MIPS_INS_BEQ
@ MIPS_INS_BEQ
Definition: analysis_mips_gnu.c:136
MIPS_INS_JAL
@ MIPS_INS_JAL
Definition: analysis_mips_gnu.c:399
MIPS_INS_SWR
@ MIPS_INS_SWR
Definition: analysis_mips_gnu.c:652
MIPS_INS_RDDSP
@ MIPS_INS_RDDSP
Definition: analysis_mips_gnu.c:555
MIPS_INS_TRUNC
@ MIPS_INS_TRUNC
Definition: analysis_mips_gnu.c:673
MIPS_INS_RINT
@ MIPS_INS_RINT
Definition: analysis_mips_gnu.c:559
MIPS_INS_BC2NEZ
@ MIPS_INS_BC2NEZ
Definition: analysis_mips_gnu.c:127
MIPS_INS_LWR
@ MIPS_INS_LWR
Definition: analysis_mips_gnu.c:445
MIPS_INS_LWM32
@ MIPS_INS_LWM32
Definition: analysis_mips_gnu.c:442
MIPS_INS_JALRS16
@ MIPS_INS_JALRS16
Definition: analysis_mips_gnu.c:401
MIPS_INS_JIC
@ MIPS_INS_JIC
Definition: analysis_mips_gnu.c:406
MIPS_INS_COPY_S
@ MIPS_INS_COPY_S
Definition: analysis_mips_gnu.c:225
MIPS_INS_MULQ_RS
@ MIPS_INS_MULQ_RS
Definition: analysis_mips_gnu.c:514
MIPS_INS_SHRAV_R
@ MIPS_INS_SHRAV_R
Definition: analysis_mips_gnu.c:595
MIPS_INS_LHX
@ MIPS_INS_LHX
Definition: analysis_mips_gnu.c:427
MIPS_INS_BCLR
@ MIPS_INS_BCLR
Definition: analysis_mips_gnu.c:135
MIPS_INS_JALS
@ MIPS_INS_JALS
Definition: analysis_mips_gnu.c:403
MIPS_INS_LUXC1
@ MIPS_INS_LUXC1
Definition: analysis_mips_gnu.c:433
MIPS_INS_MTM2
@ MIPS_INS_MTM2
Definition: analysis_mips_gnu.c:506
MIPS_INS_LD
@ MIPS_INS_LD
Definition: analysis_mips_gnu.c:416
MIPS_INS_MULSAQ_S
@ MIPS_INS_MULSAQ_S
Definition: analysis_mips_gnu.c:517
MIPS_INS_DPSX
@ MIPS_INS_DPSX
Definition: analysis_mips_gnu.c:291
MIPS_INS_BEQZ16
@ MIPS_INS_BEQZ16
Definition: analysis_mips_gnu.c:139
MIPS_INS_MAXI_S
@ MIPS_INS_MAXI_S
Definition: analysis_mips_gnu.c:461
MIPS_INS_LH
@ MIPS_INS_LH
Definition: analysis_mips_gnu.c:425
MIPS_INS_LDXC1
@ MIPS_INS_LDXC1
Definition: analysis_mips_gnu.c:424
MIPS_INS_ADDIUSP
@ MIPS_INS_ADDIUSP
Definition: analysis_mips_gnu.c:69
MIPS_INS_MULR_Q
@ MIPS_INS_MULR_Q
Definition: analysis_mips_gnu.c:516
MIPS_INS_LWXS
@ MIPS_INS_LWXS
Definition: analysis_mips_gnu.c:450
MIPS_INS_BSEL
@ MIPS_INS_BSEL
Definition: analysis_mips_gnu.c:193
MIPS_INS_SHRA_R
@ MIPS_INS_SHRA_R
Definition: analysis_mips_gnu.c:597
MIPS_INS_SLDI
@ MIPS_INS_SLDI
Definition: analysis_mips_gnu.c:600
MIPS_INS_LW
@ MIPS_INS_LW
Definition: analysis_mips_gnu.c:435
MIPS_INS_MTP2
@ MIPS_INS_MTP2
Definition: analysis_mips_gnu.c:509
MIPS_INS_DMFC2
@ MIPS_INS_DMFC2
Definition: analysis_mips_gnu.c:260
MIPS_INS_MAX_U
@ MIPS_INS_MAX_U
Definition: analysis_mips_gnu.c:466
MIPS_INS_LSA
@ MIPS_INS_LSA
Definition: analysis_mips_gnu.c:432
MIPS_INS_SRLV
@ MIPS_INS_SRLV
Definition: analysis_mips_gnu.c:624
MIPS_INS_ABS
@ MIPS_INS_ABS
Definition: analysis_mips_gnu.c:327
MIPS_INS_SRL
@ MIPS_INS_SRL
Definition: analysis_mips_gnu.c:619
MIPS_INS_ADDS_S
@ MIPS_INS_ADDS_S
Definition: analysis_mips_gnu.c:76
MIPS_INS_ADD
@ MIPS_INS_ADD
Definition: analysis_mips_gnu.c:64
MIPS_INS_MTC2
@ MIPS_INS_MTC2
Definition: analysis_mips_gnu.c:499
MIPS_INS_BBIT132
@ MIPS_INS_BBIT132
Definition: analysis_mips_gnu.c:112
MIPS_INS_EXTR
@ MIPS_INS_EXTR
Definition: analysis_mips_gnu.c:324
MIPS_INS_DEXT
@ MIPS_INS_DEXT
Definition: analysis_mips_gnu.c:246
MIPS_INS_SUBS_U
@ MIPS_INS_SUBS_U
Definition: analysis_mips_gnu.c:634
MIPS_INS_MFLO
@ MIPS_INS_MFLO
Definition: analysis_mips_gnu.c:472
MIPS_INS_DPAQ_S
@ MIPS_INS_DPAQ_S
Definition: analysis_mips_gnu.c:279
MIPS_INS_B16
@ MIPS_INS_B16
Definition: analysis_mips_gnu.c:104
MIPS_INS_DPSUB_U
@ MIPS_INS_DPSUB_U
Definition: analysis_mips_gnu.c:289
MIPS_INS_PCNT
@ MIPS_INS_PCNT
Definition: analysis_mips_gnu.c:540
MIPS_INS_V3MULU
@ MIPS_INS_V3MULU
Definition: analysis_mips_gnu.c:674
MIPS_INS_NOR
@ MIPS_INS_NOR
Definition: analysis_mips_gnu.c:529
MIPS_INS_LWX
@ MIPS_INS_LWX
Definition: analysis_mips_gnu.c:448
MIPS_INS_TLT
@ MIPS_INS_TLT
Definition: analysis_mips_gnu.c:667
MIPS_INS_MULEU_S
@ MIPS_INS_MULEU_S
Definition: analysis_mips_gnu.c:513
MIPS_INS_MINA
@ MIPS_INS_MINA
Definition: analysis_mips_gnu.c:473
MIPS_INS_TGE
@ MIPS_INS_TGE
Definition: analysis_mips_gnu.c:659
MIPS_INS_BMZ
@ MIPS_INS_BMZ
Definition: analysis_mips_gnu.c:177
MIPS_INS_MULSA
@ MIPS_INS_MULSA
Definition: analysis_mips_gnu.c:518
MIPS_INS_DSHD
@ MIPS_INS_DSHD
Definition: analysis_mips_gnu.c:297
MIPS_INS_SUBSUS_U
@ MIPS_INS_SUBSUS_U
Definition: analysis_mips_gnu.c:631
MIPS_INS_EXTRV
@ MIPS_INS_EXTRV
Definition: analysis_mips_gnu.c:320
MIPS_INS_ADDSC
@ MIPS_INS_ADDSC
Definition: analysis_mips_gnu.c:74
MIPS_INS_JR_HB
@ MIPS_INS_JR_HB
Definition: analysis_mips_gnu.c:691
MIPS_INS_SDR
@ MIPS_INS_SDR
Definition: analysis_mips_gnu.c:576
MIPS_INS_SUBU_S
@ MIPS_INS_SUBU_S
Definition: analysis_mips_gnu.c:639
MIPS_INS_LDR
@ MIPS_INS_LDR
Definition: analysis_mips_gnu.c:423
MIPS_INS_BC2T
@ MIPS_INS_BC2T
Definition: analysis_mips_gnu.c:128
MIPS_INS_DPSQX_SA
@ MIPS_INS_DPSQX_SA
Definition: analysis_mips_gnu.c:284
MIPS_INS_MTM0
@ MIPS_INS_MTM0
Definition: analysis_mips_gnu.c:504
MIPS_INS_SRLR
@ MIPS_INS_SRLR
Definition: analysis_mips_gnu.c:623
MIPS_INS_BGTZL
@ MIPS_INS_BGTZL
Definition: analysis_mips_gnu.c:154
MIPS_INS_EXTR_R
@ MIPS_INS_EXTR_R
Definition: analysis_mips_gnu.c:322
MIPS_INS_SUBQH_R
@ MIPS_INS_SUBQH_R
Definition: analysis_mips_gnu.c:628
MIPS_INS_NOT
@ MIPS_INS_NOT
Definition: analysis_mips_gnu.c:532
MIPS_INS_DATI
@ MIPS_INS_DATI
Definition: analysis_mips_gnu.c:238
MIPS_INS_MAXI_U
@ MIPS_INS_MAXI_U
Definition: analysis_mips_gnu.c:462
MIPS_INS_MUH
@ MIPS_INS_MUH
Definition: analysis_mips_gnu.c:510
MIPS_INS_MULU
@ MIPS_INS_MULU
Definition: analysis_mips_gnu.c:521
MIPS_INS_BLEZL
@ MIPS_INS_BLEZL
Definition: analysis_mips_gnu.c:164
MIPS_INS_MAQ_SA
@ MIPS_INS_MAQ_SA
Definition: analysis_mips_gnu.c:458
MIPS_INS_MIN_A
@ MIPS_INS_MIN_A
Definition: analysis_mips_gnu.c:476
MIPS_INS_ADDU
@ MIPS_INS_ADDU
Definition: analysis_mips_gnu.c:81
MIPS_INS_HADD_U
@ MIPS_INS_HADD_U
Definition: analysis_mips_gnu.c:387
MIPS_INS_SUB
@ MIPS_INS_SUB
Definition: analysis_mips_gnu.c:375
MIPS_INS_MAX
@ MIPS_INS_MAX
Definition: analysis_mips_gnu.c:464
MIPS_INS_SAT_U
@ MIPS_INS_SAT_U
Definition: analysis_mips_gnu.c:564
MIPS_INS_LHU16
@ MIPS_INS_LHU16
Definition: analysis_mips_gnu.c:426
MIPS_INS_SEB
@ MIPS_INS_SEB
Definition: analysis_mips_gnu.c:578
MIPS_INS_FRINT
@ MIPS_INS_FRINT
Definition: analysis_mips_gnu.c:364
MIPS_INS_DSRA32
@ MIPS_INS_DSRA32
Definition: analysis_mips_gnu.c:302
MIPS_INS_EXT
@ MIPS_INS_EXT
Definition: analysis_mips_gnu.c:312
MIPS_INS_SB16
@ MIPS_INS_SB16
Definition: analysis_mips_gnu.c:566
MIPS_INS_BGTZALC
@ MIPS_INS_BGTZALC
Definition: analysis_mips_gnu.c:152
MIPS_INS_APPEND
@ MIPS_INS_APPEND
Definition: analysis_mips_gnu.c:95
MIPS_INS_TLBR
@ MIPS_INS_TLBR
Definition: analysis_mips_gnu.c:664
MIPS_INS_SLTIU
@ MIPS_INS_SLTIU
Definition: analysis_mips_gnu.c:608
MIPS_INS_DAUI
@ MIPS_INS_DAUI
Definition: analysis_mips_gnu.c:239
MIPS_INS_SRA
@ MIPS_INS_SRA
Definition: analysis_mips_gnu.c:614
MIPS_INS_PRECEQ
@ MIPS_INS_PRECEQ
Definition: analysis_mips_gnu.c:544
MIPS_INS_ERET
@ MIPS_INS_ERET
Definition: analysis_mips_gnu.c:311
MIPS_INS_BC1TL
@ MIPS_INS_BC1TL
Definition: analysis_mips_gnu.c:123
MIPS_INS_BEQC
@ MIPS_INS_BEQC
Definition: analysis_mips_gnu.c:137
MIPS_INS_LL
@ MIPS_INS_LL
Definition: analysis_mips_gnu.c:430
MIPS_INS_BLEZC
@ MIPS_INS_BLEZC
Definition: analysis_mips_gnu.c:163
MIPS_INS_JALX
@ MIPS_INS_JALX
Definition: analysis_mips_gnu.c:404
MIPS_INS_DSRAV
@ MIPS_INS_DSRAV
Definition: analysis_mips_gnu.c:303
MIPS_INS_DMOD
@ MIPS_INS_DMOD
Definition: analysis_mips_gnu.c:261
MIPS_INS_SSNOP
@ MIPS_INS_SSNOP
Definition: analysis_mips_gnu.c:625
MIPS_INS_CEQ
@ MIPS_INS_CEQ
Definition: analysis_mips_gnu.c:205
MIPS_INS_PRECRQ
@ MIPS_INS_PRECRQ
Definition: analysis_mips_gnu.c:547
MIPS_INS_SRAR
@ MIPS_INS_SRAR
Definition: analysis_mips_gnu.c:617
MIPS_INS_DPAQX_SA
@ MIPS_INS_DPAQX_SA
Definition: analysis_mips_gnu.c:276
MIPS_INS_MFHI
@ MIPS_INS_MFHI
Definition: analysis_mips_gnu.c:471
MIPS_INS_DPAX
@ MIPS_INS_DPAX
Definition: analysis_mips_gnu.c:281
MIPS_INS_BNEZ
@ MIPS_INS_BNEZ
Definition: analysis_mips_gnu.c:199
MIPS_INS_CACHE
@ MIPS_INS_CACHE
Definition: analysis_mips_gnu.c:202
MIPS_INS_PREPEND
@ MIPS_INS_PREPEND
Definition: analysis_mips_gnu.c:553
MIPS_INS_EXTRV_RS
@ MIPS_INS_EXTRV_RS
Definition: analysis_mips_gnu.c:317
MIPS_INS_LHU
@ MIPS_INS_LHU
Definition: analysis_mips_gnu.c:428
MIPS_INS_BSELI
@ MIPS_INS_BSELI
Definition: analysis_mips_gnu.c:192
MIPS_INS_BC1FL
@ MIPS_INS_BC1FL
Definition: analysis_mips_gnu.c:120
MIPS_INS_BITSWAP
@ MIPS_INS_BITSWAP
Definition: analysis_mips_gnu.c:160
MIPS_INS_DINSU
@ MIPS_INS_DINSU
Definition: analysis_mips_gnu.c:252
MIPS_INS_NEG
@ MIPS_INS_NEG
Definition: analysis_mips_gnu.c:362
MIPS_INS_MADDR_Q
@ MIPS_INS_MADDR_Q
Definition: analysis_mips_gnu.c:454
MIPS_INS_ADDWC
@ MIPS_INS_ADDWC
Definition: analysis_mips_gnu.c:85
MIPS_INS_CLEI_S
@ MIPS_INS_CLEI_S
Definition: analysis_mips_gnu.c:211
MIPS_INS_BGEZ
@ MIPS_INS_BGEZ
Definition: analysis_mips_gnu.c:144
MIPS_INS_BAL
@ MIPS_INS_BAL
Definition: analysis_mips_gnu.c:106
MIPS_INS_TLBWR
@ MIPS_INS_TLBWR
Definition: analysis_mips_gnu.c:666
MIPS_INS_DPADD_S
@ MIPS_INS_DPADD_S
Definition: analysis_mips_gnu.c:274
MIPS_INS_PRECRQ_RS
@ MIPS_INS_PRECRQ_RS
Definition: analysis_mips_gnu.c:548
MIPS_INS_DCLO
@ MIPS_INS_DCLO
Definition: analysis_mips_gnu.c:241
MIPS_INS_NORI
@ MIPS_INS_NORI
Definition: analysis_mips_gnu.c:530
MIPS_INS_BNVC
@ MIPS_INS_BNVC
Definition: analysis_mips_gnu.c:186
MIPS_INS_DSRLV
@ MIPS_INS_DSRLV
Definition: analysis_mips_gnu.c:306
MIPS_INS_BC0TL
@ MIPS_INS_BC0TL
Definition: analysis_mips_gnu.c:117
MIPS_INS_BINSRI
@ MIPS_INS_BINSRI
Definition: analysis_mips_gnu.c:157
MIPS_INS_ADDI
@ MIPS_INS_ADDI
Definition: analysis_mips_gnu.c:87
MIPS_INS_EXTRV_R
@ MIPS_INS_EXTRV_R
Definition: analysis_mips_gnu.c:318
MIPS_INS_FEXP2
@ MIPS_INS_FEXP2
Definition: analysis_mips_gnu.c:343
MIPS_INS_SUBS_S
@ MIPS_INS_SUBS_S
Definition: analysis_mips_gnu.c:633
MIPS_INS_FCOR
@ MIPS_INS_FCOR
Definition: analysis_mips_gnu.c:335
MIPS_INS_DADD
@ MIPS_INS_DADD
Definition: analysis_mips_gnu.c:232
MIPS_INS_MADD_Q
@ MIPS_INS_MADD_Q
Definition: analysis_mips_gnu.c:457
MIPS_INS_BC1F
@ MIPS_INS_BC1F
Definition: analysis_mips_gnu.c:119
MIPS_INS_SDC3
@ MIPS_INS_SDC3
Definition: analysis_mips_gnu.c:574
MIPS_INS_ADDQH_R
@ MIPS_INS_ADDQH_R
Definition: analysis_mips_gnu.c:71
MIPS_INS_SLTU
@ MIPS_INS_SLTU
Definition: analysis_mips_gnu.c:609
MIPS_INS_SDC1
@ MIPS_INS_SDC1
Definition: analysis_mips_gnu.c:572
MIPS_INS_MOVT
@ MIPS_INS_MOVT
Definition: analysis_mips_gnu.c:489
MIPS_INS_DMULTU
@ MIPS_INS_DMULTU
Definition: analysis_mips_gnu.c:270
MIPS_INS_DSUB
@ MIPS_INS_DSUB
Definition: analysis_mips_gnu.c:307
MIPS_INS_DSRL
@ MIPS_INS_DSRL
Definition: analysis_mips_gnu.c:304
MIPS_INS_MOD
@ MIPS_INS_MOD
Definition: analysis_mips_gnu.c:480
MIPS_INS_EHB
@ MIPS_INS_EHB
Definition: analysis_mips_gnu.c:309
MIPS_INS_BC2FL
@ MIPS_INS_BC2FL
Definition: analysis_mips_gnu.c:126
MIPS_INS_FDIV
@ MIPS_INS_FDIV
Definition: analysis_mips_gnu.c:341
MIPS_INS_BREAK16
@ MIPS_INS_BREAK16
Definition: analysis_mips_gnu.c:191
MIPS_INS_SNEI
@ MIPS_INS_SNEI
Definition: analysis_mips_gnu.c:611
MIPS_INS_AND
@ MIPS_INS_AND
Definition: analysis_mips_gnu.c:91
MIPS_INS_JR16
@ MIPS_INS_JR16
Definition: analysis_mips_gnu.c:408
MIPS_INS_FMIN_A
@ MIPS_INS_FMIN_A
Definition: analysis_mips_gnu.c:356
MIPS_INS_FCEQ
@ MIPS_INS_FCEQ
Definition: analysis_mips_gnu.c:330
MIPS_INS_B
@ MIPS_INS_B
Definition: analysis_mips_gnu.c:198
MIPS_INS_FSUB
@ MIPS_INS_FSUB
Definition: analysis_mips_gnu.c:374
MIPS_INS_ADD_A
@ MIPS_INS_ADD_A
Definition: analysis_mips_gnu.c:86
MIPS_INS_DMODU
@ MIPS_INS_DMODU
Definition: analysis_mips_gnu.c:262
MIPS_INS_FSULT
@ MIPS_INS_FSULT
Definition: analysis_mips_gnu.c:378
MIPS_INS_SD
@ MIPS_INS_SD
Definition: analysis_mips_gnu.c:569
MIPS_INS_FMIN
@ MIPS_INS_FMIN
Definition: analysis_mips_gnu.c:357
MIPS_INS_POP
@ MIPS_INS_POP
Definition: analysis_mips_gnu.c:542
MIPS_INS_WSBH
@ MIPS_INS_WSBH
Definition: analysis_mips_gnu.c:680
MIPS_INS_LWPC
@ MIPS_INS_LWPC
Definition: analysis_mips_gnu.c:443
MIPS_INS_DALIGN
@ MIPS_INS_DALIGN
Definition: analysis_mips_gnu.c:237
MIPS_INS_AVER_S
@ MIPS_INS_AVER_S
Definition: analysis_mips_gnu.c:100
MIPS_INS_TLBWI
@ MIPS_INS_TLBWI
Definition: analysis_mips_gnu.c:665
MIPS_INS_BBIT1
@ MIPS_INS_BBIT1
Definition: analysis_mips_gnu.c:111
MIPS_INS_SLLI
@ MIPS_INS_SLLI
Definition: analysis_mips_gnu.c:604
MIPS_INS_DSLLV
@ MIPS_INS_DSLLV
Definition: analysis_mips_gnu.c:300
MIPS_INS_MOD_S
@ MIPS_INS_MOD_S
Definition: analysis_mips_gnu.c:483
MIPS_INS_SHILO
@ MIPS_INS_SHILO
Definition: analysis_mips_gnu.c:588
MIPS_INS_ALIGN
@ MIPS_INS_ALIGN
Definition: analysis_mips_gnu.c:89
MIPS_INS_SUBSUU_S
@ MIPS_INS_SUBSUU_S
Definition: analysis_mips_gnu.c:632
MIPS_INS_FEXDO
@ MIPS_INS_FEXDO
Definition: analysis_mips_gnu.c:342
MIPS_INS_SHRL
@ MIPS_INS_SHRL
Definition: analysis_mips_gnu.c:599
MIPS_INS_BLTC
@ MIPS_INS_BLTC
Definition: analysis_mips_gnu.c:165
MIPS_INS_XOR
@ MIPS_INS_XOR
Definition: analysis_mips_gnu.c:681
MIPS_INS_SLD
@ MIPS_INS_SLD
Definition: analysis_mips_gnu.c:601
MIPS_INS_BC0T
@ MIPS_INS_BC0T
Definition: analysis_mips_gnu.c:116
MIPS_INS_SRL16
@ MIPS_INS_SRL16
Definition: analysis_mips_gnu.c:620
MIPS_INS_MSUB_Q
@ MIPS_INS_MSUB_Q
Definition: analysis_mips_gnu.c:496
MIPS_INS_BNEZC
@ MIPS_INS_BNEZC
Definition: analysis_mips_gnu.c:185
MIPS_INS_DMTC2
@ MIPS_INS_DMTC2
Definition: analysis_mips_gnu.c:265
MIPS_INS_CINS32
@ MIPS_INS_CINS32
Definition: analysis_mips_gnu.c:209
MIPS_INS_MUL_Q
@ MIPS_INS_MUL_Q
Definition: analysis_mips_gnu.c:523
MIPS_INS_MODSUB
@ MIPS_INS_MODSUB
Definition: analysis_mips_gnu.c:481
MIPS_INS_MTP1
@ MIPS_INS_MTP1
Definition: analysis_mips_gnu.c:508
MIPS_INS_MOD_U
@ MIPS_INS_MOD_U
Definition: analysis_mips_gnu.c:484
MIPS_INS_DERET
@ MIPS_INS_DERET
Definition: analysis_mips_gnu.c:245
MIPS_INS_CTC1
@ MIPS_INS_CTC1
Definition: analysis_mips_gnu.c:227
MIPS_INS_PACKRL
@ MIPS_INS_PACKRL
Definition: analysis_mips_gnu.c:536
MIPS_INS_BC
@ MIPS_INS_BC
Definition: analysis_mips_gnu.c:113
MIPS_INS_FSULE
@ MIPS_INS_FSULE
Definition: analysis_mips_gnu.c:377
MIPS_INS_FCULE
@ MIPS_INS_FCULE
Definition: analysis_mips_gnu.c:337
MIPS_INS_LBU
@ MIPS_INS_LBU
Definition: analysis_mips_gnu.c:415
MIPS_INS_SEL
@ MIPS_INS_SEL
Definition: analysis_mips_gnu.c:582
MIPS_INS_SUBU
@ MIPS_INS_SUBU
Definition: analysis_mips_gnu.c:638
MIPS_INS_DIV
@ MIPS_INS_DIV
Definition: analysis_mips_gnu.c:253
MIPS_INS_LWC2
@ MIPS_INS_LWC2
Definition: analysis_mips_gnu.c:438
MIPS_INS_BLEZ
@ MIPS_INS_BLEZ
Definition: analysis_mips_gnu.c:161
MIPS_INS_LDI
@ MIPS_INS_LDI
Definition: analysis_mips_gnu.c:420
MIPS_INS_JALRC
@ MIPS_INS_JALRC
Definition: analysis_mips_gnu.c:411
MIPS_INS_ADDIUR1SP
@ MIPS_INS_ADDIUR1SP
Definition: analysis_mips_gnu.c:66
MIPS_INS_FEXUPR
@ MIPS_INS_FEXUPR
Definition: analysis_mips_gnu.c:345
MIPS_INS_DEXTU
@ MIPS_INS_DEXTU
Definition: analysis_mips_gnu.c:248
MIPS_INS_BEQZALC
@ MIPS_INS_BEQZALC
Definition: analysis_mips_gnu.c:140
MIPS_INS_ASUB_S
@ MIPS_INS_ASUB_S
Definition: analysis_mips_gnu.c:96
MIPS_INS_BGEZALS
@ MIPS_INS_BGEZALS
Definition: analysis_mips_gnu.c:148
MIPS_INS_SWC2
@ MIPS_INS_SWC2
Definition: analysis_mips_gnu.c:646
MIPS_INS_DEXTM
@ MIPS_INS_DEXTM
Definition: analysis_mips_gnu.c:247
MIPS_INS_FCNE
@ MIPS_INS_FCNE
Definition: analysis_mips_gnu.c:334
MIPS_INS_LLD
@ MIPS_INS_LLD
Definition: analysis_mips_gnu.c:431
MIPS_INS_MULQ_S
@ MIPS_INS_MULQ_S
Definition: analysis_mips_gnu.c:515
MIPS_INS_DMULU
@ MIPS_INS_DMULU
Definition: analysis_mips_gnu.c:271
MIPS_INS_ROTRV
@ MIPS_INS_ROTRV
Definition: analysis_mips_gnu.c:561
MIPS_INS_RDHWR
@ MIPS_INS_RDHWR
Definition: analysis_mips_gnu.c:556
MIPS_INS_J
@ MIPS_INS_J
Definition: analysis_mips_gnu.c:398
MIPS_INS_BSET
@ MIPS_INS_BSET
Definition: analysis_mips_gnu.c:195
MIPS_INS_LBUX
@ MIPS_INS_LBUX
Definition: analysis_mips_gnu.c:414
MIPS_INS_CTCMSA
@ MIPS_INS_CTCMSA
Definition: analysis_mips_gnu.c:228
MIPS_INS_BGEZALL
@ MIPS_INS_BGEZALL
Definition: analysis_mips_gnu.c:147
MIPS_INS_BGEUC
@ MIPS_INS_BGEUC
Definition: analysis_mips_gnu.c:143
MIPS_INS_TEQI
@ MIPS_INS_TEQI
Definition: analysis_mips_gnu.c:658
MIPS_INS_ADDU16
@ MIPS_INS_ADDU16
Definition: analysis_mips_gnu.c:78
MIPS_INS_SHF
@ MIPS_INS_SHF
Definition: analysis_mips_gnu.c:587
MIPS_INS_BC2TL
@ MIPS_INS_BC2TL
Definition: analysis_mips_gnu.c:129
MIPS_INS_CMPI
@ MIPS_INS_CMPI
Definition: analysis_mips_gnu.c:231
MIPS_INS_MADDU
@ MIPS_INS_MADDU
Definition: analysis_mips_gnu.c:455
MIPS_INS_SRLRI
@ MIPS_INS_SRLRI
Definition: analysis_mips_gnu.c:622
MIPS_INS_DSLL
@ MIPS_INS_DSLL
Definition: analysis_mips_gnu.c:298
MIPS_INS_BNEZ16
@ MIPS_INS_BNEZ16
Definition: analysis_mips_gnu.c:183
MIPS_INS_BTNEZ
@ MIPS_INS_BTNEZ
Definition: analysis_mips_gnu.c:201
MIPS_INS_CFC1
@ MIPS_INS_CFC1
Definition: analysis_mips_gnu.c:206
MIPS_INS_ADDIU
@ MIPS_INS_ADDIU
Definition: analysis_mips_gnu.c:88
MIPS_INS_SUBUH_R
@ MIPS_INS_SUBUH_R
Definition: analysis_mips_gnu.c:637
MIPS_INS_FADD
@ MIPS_INS_FADD
Definition: analysis_mips_gnu.c:328
MIPS_INS_CLT_U
@ MIPS_INS_CLT_U
Definition: analysis_mips_gnu.c:219
MIPS_INS_NLZC
@ MIPS_INS_NLZC
Definition: analysis_mips_gnu.c:526
MIPS_INS_MINI_U
@ MIPS_INS_MINI_U
Definition: analysis_mips_gnu.c:475
MIPS_INS_SUBVI
@ MIPS_INS_SUBVI
Definition: analysis_mips_gnu.c:640
MIPS_INS_ILVOD
@ MIPS_INS_ILVOD
Definition: analysis_mips_gnu.c:392
MIPS_INS_NOT16
@ MIPS_INS_NOT16
Definition: analysis_mips_gnu.c:531
MIPS_INS_BCLRI
@ MIPS_INS_BCLRI
Definition: analysis_mips_gnu.c:134
MIPS_INS_OR16
@ MIPS_INS_OR16
Definition: analysis_mips_gnu.c:534
MIPS_INS_BLTZL
@ MIPS_INS_BLTZL
Definition: analysis_mips_gnu.c:173
MIPS_INS_BGEC
@ MIPS_INS_BGEC
Definition: analysis_mips_gnu.c:142
MIPS_INS_CLEI_U
@ MIPS_INS_CLEI_U
Definition: analysis_mips_gnu.c:212
MIPS_INS_FTQ
@ MIPS_INS_FTQ
Definition: analysis_mips_gnu.c:383
MIPS_INS_MFC0
@ MIPS_INS_MFC0
Definition: analysis_mips_gnu.c:467
MIPS_INS_DPAU
@ MIPS_INS_DPAU
Definition: analysis_mips_gnu.c:280
MIPS_INS_BLTZC
@ MIPS_INS_BLTZC
Definition: analysis_mips_gnu.c:172
MIPS_INS_SEQ
@ MIPS_INS_SEQ
Definition: analysis_mips_gnu.c:583
MIPS_INS_ADDQH
@ MIPS_INS_ADDQH
Definition: analysis_mips_gnu.c:70
MIPS_INS_AVER_U
@ MIPS_INS_AVER_U
Definition: analysis_mips_gnu.c:101
MIPS_INS_FSNE
@ MIPS_INS_FSNE
Definition: analysis_mips_gnu.c:370
MIPS_INS_LWU
@ MIPS_INS_LWU
Definition: analysis_mips_gnu.c:447
MIPS_INS_ADDIUPC
@ MIPS_INS_ADDIUPC
Definition: analysis_mips_gnu.c:65
MIPS_INS_SRAI
@ MIPS_INS_SRAI
Definition: analysis_mips_gnu.c:615
MIPS_INS_FTINT_S
@ MIPS_INS_FTINT_S
Definition: analysis_mips_gnu.c:381
MIPS_INS_MULEQ_S
@ MIPS_INS_MULEQ_S
Definition: analysis_mips_gnu.c:512
MIPS_INS_MTC0
@ MIPS_INS_MTC0
Definition: analysis_mips_gnu.c:497
MIPS_INS_MULV
@ MIPS_INS_MULV
Definition: analysis_mips_gnu.c:522
MIPS_INS_DIVU
@ MIPS_INS_DIVU
Definition: analysis_mips_gnu.c:254
MIPS_INS_MAQ_S
@ MIPS_INS_MAQ_S
Definition: analysis_mips_gnu.c:459
MIPS_INS_SYSCALL
@ MIPS_INS_SYSCALL
Definition: analysis_mips_gnu.c:656
MIPS_INS_BTEQZ
@ MIPS_INS_BTEQZ
Definition: analysis_mips_gnu.c:200
MIPS_INS_SDBBP
@ MIPS_INS_SDBBP
Definition: analysis_mips_gnu.c:570
MIPS_INS_SHLLV
@ MIPS_INS_SHLLV
Definition: analysis_mips_gnu.c:590
MIPS_INS_DPSUB_S
@ MIPS_INS_DPSUB_S
Definition: analysis_mips_gnu.c:288
MIPS_INS_FILL
@ MIPS_INS_FILL
Definition: analysis_mips_gnu.c:350
MIPS_INS_MULTU
@ MIPS_INS_MULTU
Definition: analysis_mips_gnu.c:520
MIPS_INS_SW16
@ MIPS_INS_SW16
Definition: analysis_mips_gnu.c:644
MIPS_INS_DBITSWAP
@ MIPS_INS_DBITSWAP
Definition: analysis_mips_gnu.c:240
MIPS_INS_OR
@ MIPS_INS_OR
Definition: analysis_mips_gnu.c:533
MIPS_INS_ADDQ
@ MIPS_INS_ADDQ
Definition: analysis_mips_gnu.c:72
MIPS_INS_ADDIUS5
@ MIPS_INS_ADDIUS5
Definition: analysis_mips_gnu.c:68
MIPS_INS_WRDSP
@ MIPS_INS_WRDSP
Definition: analysis_mips_gnu.c:679
MIPS_INS_LBU16
@ MIPS_INS_LBU16
Definition: analysis_mips_gnu.c:413
MIPS_INS_TNE
@ MIPS_INS_TNE
Definition: analysis_mips_gnu.c:671
MIPS_INS_BC3F
@ MIPS_INS_BC3F
Definition: analysis_mips_gnu.c:130
MIPS_INS_VMM0
@ MIPS_INS_VMM0
Definition: analysis_mips_gnu.c:675
MIPS_INS_TLTIU
@ MIPS_INS_TLTIU
Definition: analysis_mips_gnu.c:669
MIPS_INS_MTHC1
@ MIPS_INS_MTHC1
Definition: analysis_mips_gnu.c:500
MIPS_INS_SCD
@ MIPS_INS_SCD
Definition: analysis_mips_gnu.c:568
MIPS_INS_JALR
@ MIPS_INS_JALR
Definition: analysis_mips_gnu.c:400
MIPS_INS_PRECEQU
@ MIPS_INS_PRECEQU
Definition: analysis_mips_gnu.c:543
MIPS_INS_ANDI
@ MIPS_INS_ANDI
Definition: analysis_mips_gnu.c:94
MIPS_INS_BALC
@ MIPS_INS_BALC
Definition: analysis_mips_gnu.c:107
MIPS_INS_DDIV
@ MIPS_INS_DDIV
Definition: analysis_mips_gnu.c:243
MIPS_INS_SWM32
@ MIPS_INS_SWM32
Definition: analysis_mips_gnu.c:650
MIPS_INS_COPY_U
@ MIPS_INS_COPY_U
Definition: analysis_mips_gnu.c:226
MIPS_INS_BEQZ
@ MIPS_INS_BEQZ
Definition: analysis_mips_gnu.c:197
MIPS_INS_MODU
@ MIPS_INS_MODU
Definition: analysis_mips_gnu.c:482
MIPS_INS_REPL
@ MIPS_INS_REPL
Definition: analysis_mips_gnu.c:558
MIPS_INS_SPLATI
@ MIPS_INS_SPLATI
Definition: analysis_mips_gnu.c:612
MIPS_INS_LB
@ MIPS_INS_LB
Definition: analysis_mips_gnu.c:412
MIPS_INS_DI
@ MIPS_INS_DI
Definition: analysis_mips_gnu.c:249
MIPS_INS_DLSA
@ MIPS_INS_DLSA
Definition: analysis_mips_gnu.c:257
MIPS_INS_MINI_S
@ MIPS_INS_MINI_S
Definition: analysis_mips_gnu.c:474
MIPS_INS_DOTP_S
@ MIPS_INS_DOTP_S
Definition: analysis_mips_gnu.c:272
MIPS_INS_DROTRV
@ MIPS_INS_DROTRV
Definition: analysis_mips_gnu.c:295
MIPS_INS_MTLO
@ MIPS_INS_MTLO
Definition: analysis_mips_gnu.c:503
MIPS_INS_SLL
@ MIPS_INS_SLL
Definition: analysis_mips_gnu.c:602
MIPS_INS_MADDF
@ MIPS_INS_MADDF
Definition: analysis_mips_gnu.c:453
MIPS_INS_SRARI
@ MIPS_INS_SRARI
Definition: analysis_mips_gnu.c:616
MIPS_INS_TLTU
@ MIPS_INS_TLTU
Definition: analysis_mips_gnu.c:670
MIPS_INS_PRECRQU_S
@ MIPS_INS_PRECRQU_S
Definition: analysis_mips_gnu.c:546
MIPS_INS_EXTR_RS
@ MIPS_INS_EXTR_RS
Definition: analysis_mips_gnu.c:321
MIPS_INS_BGEZAL
@ MIPS_INS_BGEZAL
Definition: analysis_mips_gnu.c:145
MIPS_INS_PRECR_SRA_R
@ MIPS_INS_PRECR_SRA_R
Definition: analysis_mips_gnu.c:551
MIPS_INS_CEIL
@ MIPS_INS_CEIL
Definition: analysis_mips_gnu.c:203
MIPS_INS_MIN
@ MIPS_INS_MIN
Definition: analysis_mips_gnu.c:477
MIPS_INS_NMSUB
@ MIPS_INS_NMSUB
Definition: analysis_mips_gnu.c:528
MIPS_INS_BC1NEZ
@ MIPS_INS_BC1NEZ
Definition: analysis_mips_gnu.c:121
MIPS_INS_SLL16
@ MIPS_INS_SLL16
Definition: analysis_mips_gnu.c:603
MIPS_INS_CLTI_S
@ MIPS_INS_CLTI_S
Definition: analysis_mips_gnu.c:216
MIPS_INS_BINSLI
@ MIPS_INS_BINSLI
Definition: analysis_mips_gnu.c:155
MIPS_INS_MTC1
@ MIPS_INS_MTC1
Definition: analysis_mips_gnu.c:498
MIPS_INS_DROTR32
@ MIPS_INS_DROTR32
Definition: analysis_mips_gnu.c:294
MIPS_INS_ASUB_U
@ MIPS_INS_ASUB_U
Definition: analysis_mips_gnu.c:97
MIPS_INS_PICK
@ MIPS_INS_PICK
Definition: analysis_mips_gnu.c:541
MIPS_INS_RADDU
@ MIPS_INS_RADDU
Definition: analysis_mips_gnu.c:554
MIPS_INS_CMP
@ MIPS_INS_CMP
Definition: analysis_mips_gnu.c:224
MIPS_INS_ROUND
@ MIPS_INS_ROUND
Definition: analysis_mips_gnu.c:562
MIPS_INS_MULT
@ MIPS_INS_MULT
Definition: analysis_mips_gnu.c:519
MIPS_INS_MAX_S
@ MIPS_INS_MAX_S
Definition: analysis_mips_gnu.c:465
MIPS_INS_EXTS
@ MIPS_INS_EXTS
Definition: analysis_mips_gnu.c:325
MIPS_INS_LWC1
@ MIPS_INS_LWC1
Definition: analysis_mips_gnu.c:437
MIPS_INS_BC0FL
@ MIPS_INS_BC0FL
Definition: analysis_mips_gnu.c:115
MIPS_INS_FSUEQ
@ MIPS_INS_FSUEQ
Definition: analysis_mips_gnu.c:376
MIPS_INS_DMFC0
@ MIPS_INS_DMFC0
Definition: analysis_mips_gnu.c:258
MIPS_INS_CLE_U
@ MIPS_INS_CLE_U
Definition: analysis_mips_gnu.c:214
MIPS_INS_MTM1
@ MIPS_INS_MTM1
Definition: analysis_mips_gnu.c:505
MIPS_INS_BMNZ
@ MIPS_INS_BMNZ
Definition: analysis_mips_gnu.c:175
MIPS_INS_MOVE
@ MIPS_INS_MOVE
Definition: analysis_mips_gnu.c:485
MIPS_INS_MOVZ
@ MIPS_INS_MOVZ
Definition: analysis_mips_gnu.c:490
MIPS_INS_SRAV
@ MIPS_INS_SRAV
Definition: analysis_mips_gnu.c:618
MIPS_INS_FRSQRT
@ MIPS_INS_FRSQRT
Definition: analysis_mips_gnu.c:365
MIPS_INS_LWXC1
@ MIPS_INS_LWXC1
Definition: analysis_mips_gnu.c:449
MIPS_INS_JRC
@ MIPS_INS_JRC
Definition: analysis_mips_gnu.c:410
MIPS_INS_BC2EQZ
@ MIPS_INS_BC2EQZ
Definition: analysis_mips_gnu.c:124
MIPS_INS_DSBH
@ MIPS_INS_DSBH
Definition: analysis_mips_gnu.c:296
MIPS_INS_SUBQ
@ MIPS_INS_SUBQ
Definition: analysis_mips_gnu.c:629
MIPS_INS_FSQRT
@ MIPS_INS_FSQRT
Definition: analysis_mips_gnu.c:372
MIPS_INS_FMAX
@ MIPS_INS_FMAX
Definition: analysis_mips_gnu.c:355
MIPS_INS_DADDIU
@ MIPS_INS_DADDIU
Definition: analysis_mips_gnu.c:234
MIPS_INS_PCKOD
@ MIPS_INS_PCKOD
Definition: analysis_mips_gnu.c:539
MIPS_INS_FFINT_S
@ MIPS_INS_FFINT_S
Definition: analysis_mips_gnu.c:346
MIPS_INS_AVE_S
@ MIPS_INS_AVE_S
Definition: analysis_mips_gnu.c:102
MIPS_INS_FMADD
@ MIPS_INS_FMADD
Definition: analysis_mips_gnu.c:353
MIPS_INS_AVE_U
@ MIPS_INS_AVE_U
Definition: analysis_mips_gnu.c:103
MIPS_INS_BGEZC
@ MIPS_INS_BGEZC
Definition: analysis_mips_gnu.c:149
MIPS_INS_FCLE
@ MIPS_INS_FCLE
Definition: analysis_mips_gnu.c:332
MIPS_INS_BZ
@ MIPS_INS_BZ
Definition: analysis_mips_gnu.c:196
MIPS_INS_SHRAV
@ MIPS_INS_SHRAV
Definition: analysis_mips_gnu.c:594
MIPS_INS_BINSL
@ MIPS_INS_BINSL
Definition: analysis_mips_gnu.c:156
MIPS_INS_DADDI
@ MIPS_INS_DADDI
Definition: analysis_mips_gnu.c:233
MIPS_INS_ANDI16
@ MIPS_INS_ANDI16
Definition: analysis_mips_gnu.c:93
MIPS_INS_SDBBP16
@ MIPS_INS_SDBBP16
Definition: analysis_mips_gnu.c:571
MIPS_INS_PAUSE
@ MIPS_INS_PAUSE
Definition: analysis_mips_gnu.c:537
MIPS_INS_BALIGN
@ MIPS_INS_BALIGN
Definition: analysis_mips_gnu.c:108
MIPS_INS_VMULU
@ MIPS_INS_VMULU
Definition: analysis_mips_gnu.c:676
MIPS_INS_BADDU
@ MIPS_INS_BADDU
Definition: analysis_mips_gnu.c:105
MIPS_INS_EXTRV_S
@ MIPS_INS_EXTRV_S
Definition: analysis_mips_gnu.c:319
MIPS_INS_INSV
@ MIPS_INS_INSV
Definition: analysis_mips_gnu.c:396
MIPS_INS_LWC3
@ MIPS_INS_LWC3
Definition: analysis_mips_gnu.c:439
MIPS_INS_DPSU
@ MIPS_INS_DPSU
Definition: analysis_mips_gnu.c:290
MIPS_INS_DOTP_U
@ MIPS_INS_DOTP_U
Definition: analysis_mips_gnu.c:273
MIPS_INS_BC3FL
@ MIPS_INS_BC3FL
Definition: analysis_mips_gnu.c:131
MIPS_INS_MSUBV
@ MIPS_INS_MSUBV
Definition: analysis_mips_gnu.c:495
MIPS_INS_SEQI
@ MIPS_INS_SEQI
Definition: analysis_mips_gnu.c:584
MIPS_INS_SLLV
@ MIPS_INS_SLLV
Definition: analysis_mips_gnu.c:605
MIPS_INS_TNEI
@ MIPS_INS_TNEI
Definition: analysis_mips_gnu.c:672
MIPS_INS_CLE_S
@ MIPS_INS_CLE_S
Definition: analysis_mips_gnu.c:213
MIPS_INS_JALR_HB
@ MIPS_INS_JALR_HB
Definition: analysis_mips_gnu.c:690
MIPS_INS_TLTI
@ MIPS_INS_TLTI
Definition: analysis_mips_gnu.c:668
MIPS_INS_SLTI
@ MIPS_INS_SLTI
Definition: analysis_mips_gnu.c:607
MIPS_INS_CINS
@ MIPS_INS_CINS
Definition: analysis_mips_gnu.c:208
MIPS_INS_DAHI
@ MIPS_INS_DAHI
Definition: analysis_mips_gnu.c:236
MIPS_INS_ADDQ_S
@ MIPS_INS_ADDQ_S
Definition: analysis_mips_gnu.c:73
MIPS_INS_CLZ
@ MIPS_INS_CLZ
Definition: analysis_mips_gnu.c:220
MIPS_INS_DMTC0
@ MIPS_INS_DMTC0
Definition: analysis_mips_gnu.c:263
MIPS_INS_FCLASS
@ MIPS_INS_FCLASS
Definition: analysis_mips_gnu.c:331
MIPS_INS_DMUHU
@ MIPS_INS_DMUHU
Definition: analysis_mips_gnu.c:267
MIPS_INS_JR
@ MIPS_INS_JR
Definition: analysis_mips_gnu.c:407
MIPS_INS_ADDIUR2
@ MIPS_INS_ADDIUR2
Definition: analysis_mips_gnu.c:67
MIPS_INS_SB
@ MIPS_INS_SB
Definition: analysis_mips_gnu.c:565
MIPS_INS_BC3TL
@ MIPS_INS_BC3TL
Definition: analysis_mips_gnu.c:133
MIPS_INS_TGEI
@ MIPS_INS_TGEI
Definition: analysis_mips_gnu.c:660
MIPS_INS_MFC1
@ MIPS_INS_MFC1
Definition: analysis_mips_gnu.c:468
MIPS_INS_FSUNE
@ MIPS_INS_FSUNE
Definition: analysis_mips_gnu.c:379
MIPS_INS_DSLL32
@ MIPS_INS_DSLL32
Definition: analysis_mips_gnu.c:299
MIPS_INS_SUBV
@ MIPS_INS_SUBV
Definition: analysis_mips_gnu.c:641
MIPS_INS_BNEL
@ MIPS_INS_BNEL
Definition: analysis_mips_gnu.c:182
MIPS_INS_DADDU
@ MIPS_INS_DADDU
Definition: analysis_mips_gnu.c:235
MIPS_INS_MUHU
@ MIPS_INS_MUHU
Definition: analysis_mips_gnu.c:511
MIPS_INS_SHLLV_S
@ MIPS_INS_SHLLV_S
Definition: analysis_mips_gnu.c:591
MIPS_INS_MFC2
@ MIPS_INS_MFC2
Definition: analysis_mips_gnu.c:469
MIPS_INS_MUL_S
@ MIPS_INS_MUL_S
Definition: analysis_mips_gnu.c:524
MIPS_INS_XOR16
@ MIPS_INS_XOR16
Definition: analysis_mips_gnu.c:682
MIPS_INS_BLTZAL
@ MIPS_INS_BLTZAL
Definition: analysis_mips_gnu.c:168
MIPS_GRP_MIPS3
@ MIPS_GRP_MIPS3
Definition: mips.h:940
MIPS_GRP_MIPS16MODE
@ MIPS_GRP_MIPS16MODE
Definition: mips.h:927
MIPS_GRP_MICROMIPS
@ MIPS_GRP_MICROMIPS
Definition: mips.h:926
MIPS_GRP_MIPS4_32R2
@ MIPS_GRP_MIPS4_32R2
Definition: mips.h:944
MIPS_GRP_DSP
@ MIPS_GRP_DSP
Definition: mips.h:916
MIPS_GRP_STDENC
@ MIPS_GRP_STDENC
Definition: mips.h:924
MIPS_GRP_MIPS5_32R2
@ MIPS_GRP_MIPS5_32R2
Definition: mips.h:945
MIPS_GRP_GP64BIT
@ MIPS_GRP_GP64BIT
Definition: mips.h:947
MIPS_GRP_INT
@ MIPS_GRP_INT
= CS_GRP_INT
Definition: mips.h:906
MIPS_GRP_MIPS64R2
@ MIPS_GRP_MIPS64R2
Definition: mips.h:922
MIPS_GRP_MIPS2
@ MIPS_GRP_MIPS2
Definition: mips.h:939
MIPS_GRP_MIPS4_32
@ MIPS_GRP_MIPS4_32
Definition: mips.h:943
MIPS_GRP_NOTMIPS64R6
@ MIPS_GRP_NOTMIPS64R6
Definition: mips.h:934
MIPS_GRP_MIPS64R6
@ MIPS_GRP_MIPS64R6
Definition: mips.h:938
MIPS_GRP_FP64BIT
@ MIPS_GRP_FP64BIT
Definition: mips.h:928
MIPS_GRP_MIPS3_32
@ MIPS_GRP_MIPS3_32
Definition: mips.h:941
MIPS_GRP_MIPS32R6
@ MIPS_GRP_MIPS32R6
Definition: mips.h:937
MIPS_GRP_CALL
@ MIPS_GRP_CALL
= CS_GRP_CALL
Definition: mips.h:902
MIPS_GRP_MIPS32R2
@ MIPS_GRP_MIPS32R2
Definition: mips.h:920
MIPS_GRP_NOTFP64BIT
@ MIPS_GRP_NOTFP64BIT
Definition: mips.h:930
MIPS_GRP_NOTNACL
@ MIPS_GRP_NOTNACL
Definition: mips.h:932
MIPS_GRP_NONANSFPMATH
@ MIPS_GRP_NONANSFPMATH
Definition: mips.h:929
MIPS_GRP_MSA
@ MIPS_GRP_MSA
Definition: mips.h:919
MIPS_GRP_MIPS3_32R2
@ MIPS_GRP_MIPS3_32R2
Definition: mips.h:942
MIPS_GRP_NOTINMICROMIPS
@ MIPS_GRP_NOTINMICROMIPS
Definition: mips.h:931
MIPS_GRP_GP32BIT
@ MIPS_GRP_GP32BIT
Definition: mips.h:946
MIPS_GRP_BRANCH_RELATIVE
@ MIPS_GRP_BRANCH_RELATIVE
= CS_GRP_BRANCH_RELATIVE
Definition: mips.h:912
MIPS_GRP_NOTMIPS32R6
@ MIPS_GRP_NOTMIPS32R6
Definition: mips.h:933
MIPS_GRP_DSPR2
@ MIPS_GRP_DSPR2
Definition: mips.h:917
MIPS_GRP_CNMIPS
@ MIPS_GRP_CNMIPS
Definition: mips.h:935
MIPS_GRP_MIPS32
@ MIPS_GRP_MIPS32
Definition: mips.h:936
MIPS_GRP_MIPS64
@ MIPS_GRP_MIPS64
Definition: mips.h:921
MIPS_REG_P2
@ MIPS_REG_P2
Definition: mips.h:179
MIPS_REG_MPL2
@ MIPS_REG_MPL2
Definition: mips.h:183
MIPS_REG_HI0
@ MIPS_REG_HI0
Definition: mips.h:221
MIPS_REG_DSPEFI
@ MIPS_REG_DSPEFI
Definition: mips.h:71
MIPS_REG_DSPOUTFLAG16_19
@ MIPS_REG_DSPOUTFLAG16_19
Definition: mips.h:73
MIPS_REG_DSPCCOND
@ MIPS_REG_DSPCCOND
Definition: mips.h:69
MIPS_REG_DSPSCOUNT
@ MIPS_REG_DSPSCOUNT
Definition: mips.h:79
MIPS_REG_DSPPOS
@ MIPS_REG_DSPPOS
Definition: mips.h:78
MIPS_REG_AT
@ MIPS_REG_AT
Definition: mips.h:189
MIPS_REG_DSPOUTFLAG22
@ MIPS_REG_DSPOUTFLAG22
Definition: mips.h:76
MIPS_REG_DSPCARRY
@ MIPS_REG_DSPCARRY
Definition: mips.h:70
MIPS_REG_DSPOUTFLAG23
@ MIPS_REG_DSPOUTFLAG23
Definition: mips.h:77
MIPS_REG_T8
@ MIPS_REG_T8
Definition: mips.h:212
MIPS_REG_DSPOUTFLAG20
@ MIPS_REG_DSPOUTFLAG20
Definition: mips.h:74
MIPS_REG_FCC0
@ MIPS_REG_FCC0
Definition: mips.h:131
MIPS_REG_P0
@ MIPS_REG_P0
Definition: mips.h:177
MIPS_REG_DSPOUTFLAG21
@ MIPS_REG_DSPOUTFLAG21
Definition: mips.h:75
MIPS_REG_RA
@ MIPS_REG_RA
Definition: mips.h:219
MIPS_REG_MPL0
@ MIPS_REG_MPL0
Definition: mips.h:181
MIPS_REG_LO0
@ MIPS_REG_LO0
Definition: mips.h:226
MIPS_REG_AC0
@ MIPS_REG_AC0
Definition: mips.h:82
MIPS_REG_P1
@ MIPS_REG_P1
Definition: mips.h:178
MIPS_REG_MPL1
@ MIPS_REG_MPL1
Definition: mips.h:182
MIPS_REG_SP
@ MIPS_REG_SP
Definition: mips.h:217