Rizin
unix-like reverse engineering framework and cli tools
ARMGenInstrInfo.inc
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1 /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2 |* *|
3 |*Target Instruction Enum Values *|
4 |* *|
5 |* Automatically generated file, do not edit! *|
6 |* *|
7 \*===----------------------------------------------------------------------===*/
8 
9 /* Capstone Disassembly Engine, http://www.capstone-engine.org */
10 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
11 
12 
13 #ifdef GET_INSTRINFO_ENUM
14 #undef GET_INSTRINFO_ENUM
15 
16 enum {
17  ARM_PHI = 0,
18  ARM_INLINEASM = 1,
19  ARM_CFI_INSTRUCTION = 2,
20  ARM_EH_LABEL = 3,
21  ARM_GC_LABEL = 4,
22  ARM_KILL = 5,
23  ARM_EXTRACT_SUBREG = 6,
24  ARM_INSERT_SUBREG = 7,
25  ARM_IMPLICIT_DEF = 8,
26  ARM_SUBREG_TO_REG = 9,
27  ARM_COPY_TO_REGCLASS = 10,
28  ARM_DBG_VALUE = 11,
29  ARM_REG_SEQUENCE = 12,
30  ARM_COPY = 13,
31  ARM_BUNDLE = 14,
32  ARM_LIFETIME_START = 15,
33  ARM_LIFETIME_END = 16,
34  ARM_STACKMAP = 17,
35  ARM_PATCHPOINT = 18,
36  ARM_LOAD_STACK_GUARD = 19,
37  ARM_STATEPOINT = 20,
38  ARM_FRAME_ALLOC = 21,
39  ARM_ABS = 22,
40  ARM_ADCri = 23,
41  ARM_ADCrr = 24,
42  ARM_ADCrsi = 25,
43  ARM_ADCrsr = 26,
44  ARM_ADDSri = 27,
45  ARM_ADDSrr = 28,
46  ARM_ADDSrsi = 29,
47  ARM_ADDSrsr = 30,
48  ARM_ADDri = 31,
49  ARM_ADDrr = 32,
50  ARM_ADDrsi = 33,
51  ARM_ADDrsr = 34,
52  ARM_ADJCALLSTACKDOWN = 35,
53  ARM_ADJCALLSTACKUP = 36,
54  ARM_ADR = 37,
55  ARM_AESD = 38,
56  ARM_AESE = 39,
57  ARM_AESIMC = 40,
58  ARM_AESMC = 41,
59  ARM_ANDri = 42,
60  ARM_ANDrr = 43,
61  ARM_ANDrsi = 44,
62  ARM_ANDrsr = 45,
63  ARM_ASRi = 46,
64  ARM_ASRr = 47,
65  ARM_B = 48,
66  ARM_BCCZi64 = 49,
67  ARM_BCCi64 = 50,
68  ARM_BFC = 51,
69  ARM_BFI = 52,
70  ARM_BICri = 53,
71  ARM_BICrr = 54,
72  ARM_BICrsi = 55,
73  ARM_BICrsr = 56,
74  ARM_BKPT = 57,
75  ARM_BL = 58,
76  ARM_BLX = 59,
77  ARM_BLX_pred = 60,
78  ARM_BLXi = 61,
79  ARM_BL_pred = 62,
80  ARM_BMOVPCB_CALL = 63,
81  ARM_BMOVPCRX_CALL = 64,
82  ARM_BR_JTadd = 65,
83  ARM_BR_JTm = 66,
84  ARM_BR_JTr = 67,
85  ARM_BX = 68,
86  ARM_BXJ = 69,
87  ARM_BX_CALL = 70,
88  ARM_BX_RET = 71,
89  ARM_BX_pred = 72,
90  ARM_Bcc = 73,
91  ARM_CDP = 74,
92  ARM_CDP2 = 75,
93  ARM_CLREX = 76,
94  ARM_CLZ = 77,
95  ARM_CMNri = 78,
96  ARM_CMNzrr = 79,
97  ARM_CMNzrsi = 80,
98  ARM_CMNzrsr = 81,
99  ARM_CMPri = 82,
100  ARM_CMPrr = 83,
101  ARM_CMPrsi = 84,
102  ARM_CMPrsr = 85,
103  ARM_CONSTPOOL_ENTRY = 86,
104  ARM_COPY_STRUCT_BYVAL_I32 = 87,
105  ARM_CPS1p = 88,
106  ARM_CPS2p = 89,
107  ARM_CPS3p = 90,
108  ARM_CRC32B = 91,
109  ARM_CRC32CB = 92,
110  ARM_CRC32CH = 93,
111  ARM_CRC32CW = 94,
112  ARM_CRC32H = 95,
113  ARM_CRC32W = 96,
114  ARM_DBG = 97,
115  ARM_DMB = 98,
116  ARM_DSB = 99,
117  ARM_EORri = 100,
118  ARM_EORrr = 101,
119  ARM_EORrsi = 102,
120  ARM_EORrsr = 103,
121  ARM_ERET = 104,
122  ARM_FCONSTD = 105,
123  ARM_FCONSTS = 106,
124  ARM_FLDMXDB_UPD = 107,
125  ARM_FLDMXIA = 108,
126  ARM_FLDMXIA_UPD = 109,
127  ARM_FMSTAT = 110,
128  ARM_FSTMXDB_UPD = 111,
129  ARM_FSTMXIA = 112,
130  ARM_FSTMXIA_UPD = 113,
131  ARM_HINT = 114,
132  ARM_HLT = 115,
133  ARM_HVC = 116,
134  ARM_ISB = 117,
135  ARM_ITasm = 118,
136  ARM_Int_eh_sjlj_dispatchsetup = 119,
137  ARM_Int_eh_sjlj_longjmp = 120,
138  ARM_Int_eh_sjlj_setjmp = 121,
139  ARM_Int_eh_sjlj_setjmp_nofp = 122,
140  ARM_LDA = 123,
141  ARM_LDAB = 124,
142  ARM_LDAEX = 125,
143  ARM_LDAEXB = 126,
144  ARM_LDAEXD = 127,
145  ARM_LDAEXH = 128,
146  ARM_LDAH = 129,
147  ARM_LDC2L_OFFSET = 130,
148  ARM_LDC2L_OPTION = 131,
149  ARM_LDC2L_POST = 132,
150  ARM_LDC2L_PRE = 133,
151  ARM_LDC2_OFFSET = 134,
152  ARM_LDC2_OPTION = 135,
153  ARM_LDC2_POST = 136,
154  ARM_LDC2_PRE = 137,
155  ARM_LDCL_OFFSET = 138,
156  ARM_LDCL_OPTION = 139,
157  ARM_LDCL_POST = 140,
158  ARM_LDCL_PRE = 141,
159  ARM_LDC_OFFSET = 142,
160  ARM_LDC_OPTION = 143,
161  ARM_LDC_POST = 144,
162  ARM_LDC_PRE = 145,
163  ARM_LDMDA = 146,
164  ARM_LDMDA_UPD = 147,
165  ARM_LDMDB = 148,
166  ARM_LDMDB_UPD = 149,
167  ARM_LDMIA = 150,
168  ARM_LDMIA_RET = 151,
169  ARM_LDMIA_UPD = 152,
170  ARM_LDMIB = 153,
171  ARM_LDMIB_UPD = 154,
172  ARM_LDRBT_POST = 155,
173  ARM_LDRBT_POST_IMM = 156,
174  ARM_LDRBT_POST_REG = 157,
175  ARM_LDRB_POST_IMM = 158,
176  ARM_LDRB_POST_REG = 159,
177  ARM_LDRB_PRE_IMM = 160,
178  ARM_LDRB_PRE_REG = 161,
179  ARM_LDRBi12 = 162,
180  ARM_LDRBrs = 163,
181  ARM_LDRD = 164,
182  ARM_LDRD_POST = 165,
183  ARM_LDRD_PRE = 166,
184  ARM_LDREX = 167,
185  ARM_LDREXB = 168,
186  ARM_LDREXD = 169,
187  ARM_LDREXH = 170,
188  ARM_LDRH = 171,
189  ARM_LDRHTi = 172,
190  ARM_LDRHTr = 173,
191  ARM_LDRH_POST = 174,
192  ARM_LDRH_PRE = 175,
193  ARM_LDRLIT_ga_abs = 176,
194  ARM_LDRLIT_ga_pcrel = 177,
195  ARM_LDRLIT_ga_pcrel_ldr = 178,
196  ARM_LDRSB = 179,
197  ARM_LDRSBTi = 180,
198  ARM_LDRSBTr = 181,
199  ARM_LDRSB_POST = 182,
200  ARM_LDRSB_PRE = 183,
201  ARM_LDRSH = 184,
202  ARM_LDRSHTi = 185,
203  ARM_LDRSHTr = 186,
204  ARM_LDRSH_POST = 187,
205  ARM_LDRSH_PRE = 188,
206  ARM_LDRT_POST = 189,
207  ARM_LDRT_POST_IMM = 190,
208  ARM_LDRT_POST_REG = 191,
209  ARM_LDR_POST_IMM = 192,
210  ARM_LDR_POST_REG = 193,
211  ARM_LDR_PRE_IMM = 194,
212  ARM_LDR_PRE_REG = 195,
213  ARM_LDRcp = 196,
214  ARM_LDRi12 = 197,
215  ARM_LDRrs = 198,
216  ARM_LEApcrel = 199,
217  ARM_LEApcrelJT = 200,
218  ARM_LSLi = 201,
219  ARM_LSLr = 202,
220  ARM_LSRi = 203,
221  ARM_LSRr = 204,
222  ARM_MCR = 205,
223  ARM_MCR2 = 206,
224  ARM_MCRR = 207,
225  ARM_MCRR2 = 208,
226  ARM_MLA = 209,
227  ARM_MLAv5 = 210,
228  ARM_MLS = 211,
229  ARM_MOVCCi = 212,
230  ARM_MOVCCi16 = 213,
231  ARM_MOVCCi32imm = 214,
232  ARM_MOVCCr = 215,
233  ARM_MOVCCsi = 216,
234  ARM_MOVCCsr = 217,
235  ARM_MOVPCLR = 218,
236  ARM_MOVPCRX = 219,
237  ARM_MOVTi16 = 220,
238  ARM_MOVTi16_ga_pcrel = 221,
239  ARM_MOV_ga_pcrel = 222,
240  ARM_MOV_ga_pcrel_ldr = 223,
241  ARM_MOVi = 224,
242  ARM_MOVi16 = 225,
243  ARM_MOVi16_ga_pcrel = 226,
244  ARM_MOVi32imm = 227,
245  ARM_MOVr = 228,
246  ARM_MOVr_TC = 229,
247  ARM_MOVsi = 230,
248  ARM_MOVsr = 231,
249  ARM_MOVsra_flag = 232,
250  ARM_MOVsrl_flag = 233,
251  ARM_MRC = 234,
252  ARM_MRC2 = 235,
253  ARM_MRRC = 236,
254  ARM_MRRC2 = 237,
255  ARM_MRS = 238,
256  ARM_MRSbanked = 239,
257  ARM_MRSsys = 240,
258  ARM_MSR = 241,
259  ARM_MSRbanked = 242,
260  ARM_MSRi = 243,
261  ARM_MUL = 244,
262  ARM_MULv5 = 245,
263  ARM_MVNCCi = 246,
264  ARM_MVNi = 247,
265  ARM_MVNr = 248,
266  ARM_MVNsi = 249,
267  ARM_MVNsr = 250,
268  ARM_ORRri = 251,
269  ARM_ORRrr = 252,
270  ARM_ORRrsi = 253,
271  ARM_ORRrsr = 254,
272  ARM_PICADD = 255,
273  ARM_PICLDR = 256,
274  ARM_PICLDRB = 257,
275  ARM_PICLDRH = 258,
276  ARM_PICLDRSB = 259,
277  ARM_PICLDRSH = 260,
278  ARM_PICSTR = 261,
279  ARM_PICSTRB = 262,
280  ARM_PICSTRH = 263,
281  ARM_PKHBT = 264,
282  ARM_PKHTB = 265,
283  ARM_PLDWi12 = 266,
284  ARM_PLDWrs = 267,
285  ARM_PLDi12 = 268,
286  ARM_PLDrs = 269,
287  ARM_PLIi12 = 270,
288  ARM_PLIrs = 271,
289  ARM_QADD = 272,
290  ARM_QADD16 = 273,
291  ARM_QADD8 = 274,
292  ARM_QASX = 275,
293  ARM_QDADD = 276,
294  ARM_QDSUB = 277,
295  ARM_QSAX = 278,
296  ARM_QSUB = 279,
297  ARM_QSUB16 = 280,
298  ARM_QSUB8 = 281,
299  ARM_RBIT = 282,
300  ARM_REV = 283,
301  ARM_REV16 = 284,
302  ARM_REVSH = 285,
303  ARM_RFEDA = 286,
304  ARM_RFEDA_UPD = 287,
305  ARM_RFEDB = 288,
306  ARM_RFEDB_UPD = 289,
307  ARM_RFEIA = 290,
308  ARM_RFEIA_UPD = 291,
309  ARM_RFEIB = 292,
310  ARM_RFEIB_UPD = 293,
311  ARM_RORi = 294,
312  ARM_RORr = 295,
313  ARM_RRX = 296,
314  ARM_RRXi = 297,
315  ARM_RSBSri = 298,
316  ARM_RSBSrsi = 299,
317  ARM_RSBSrsr = 300,
318  ARM_RSBri = 301,
319  ARM_RSBrr = 302,
320  ARM_RSBrsi = 303,
321  ARM_RSBrsr = 304,
322  ARM_RSCri = 305,
323  ARM_RSCrr = 306,
324  ARM_RSCrsi = 307,
325  ARM_RSCrsr = 308,
326  ARM_SADD16 = 309,
327  ARM_SADD8 = 310,
328  ARM_SASX = 311,
329  ARM_SBCri = 312,
330  ARM_SBCrr = 313,
331  ARM_SBCrsi = 314,
332  ARM_SBCrsr = 315,
333  ARM_SBFX = 316,
334  ARM_SDIV = 317,
335  ARM_SEL = 318,
336  ARM_SETEND = 319,
337  ARM_SHA1C = 320,
338  ARM_SHA1H = 321,
339  ARM_SHA1M = 322,
340  ARM_SHA1P = 323,
341  ARM_SHA1SU0 = 324,
342  ARM_SHA1SU1 = 325,
343  ARM_SHA256H = 326,
344  ARM_SHA256H2 = 327,
345  ARM_SHA256SU0 = 328,
346  ARM_SHA256SU1 = 329,
347  ARM_SHADD16 = 330,
348  ARM_SHADD8 = 331,
349  ARM_SHASX = 332,
350  ARM_SHSAX = 333,
351  ARM_SHSUB16 = 334,
352  ARM_SHSUB8 = 335,
353  ARM_SMC = 336,
354  ARM_SMLABB = 337,
355  ARM_SMLABT = 338,
356  ARM_SMLAD = 339,
357  ARM_SMLADX = 340,
358  ARM_SMLAL = 341,
359  ARM_SMLALBB = 342,
360  ARM_SMLALBT = 343,
361  ARM_SMLALD = 344,
362  ARM_SMLALDX = 345,
363  ARM_SMLALTB = 346,
364  ARM_SMLALTT = 347,
365  ARM_SMLALv5 = 348,
366  ARM_SMLATB = 349,
367  ARM_SMLATT = 350,
368  ARM_SMLAWB = 351,
369  ARM_SMLAWT = 352,
370  ARM_SMLSD = 353,
371  ARM_SMLSDX = 354,
372  ARM_SMLSLD = 355,
373  ARM_SMLSLDX = 356,
374  ARM_SMMLA = 357,
375  ARM_SMMLAR = 358,
376  ARM_SMMLS = 359,
377  ARM_SMMLSR = 360,
378  ARM_SMMUL = 361,
379  ARM_SMMULR = 362,
380  ARM_SMUAD = 363,
381  ARM_SMUADX = 364,
382  ARM_SMULBB = 365,
383  ARM_SMULBT = 366,
384  ARM_SMULL = 367,
385  ARM_SMULLv5 = 368,
386  ARM_SMULTB = 369,
387  ARM_SMULTT = 370,
388  ARM_SMULWB = 371,
389  ARM_SMULWT = 372,
390  ARM_SMUSD = 373,
391  ARM_SMUSDX = 374,
392  ARM_SPACE = 375,
393  ARM_SRSDA = 376,
394  ARM_SRSDA_UPD = 377,
395  ARM_SRSDB = 378,
396  ARM_SRSDB_UPD = 379,
397  ARM_SRSIA = 380,
398  ARM_SRSIA_UPD = 381,
399  ARM_SRSIB = 382,
400  ARM_SRSIB_UPD = 383,
401  ARM_SSAT = 384,
402  ARM_SSAT16 = 385,
403  ARM_SSAX = 386,
404  ARM_SSUB16 = 387,
405  ARM_SSUB8 = 388,
406  ARM_STC2L_OFFSET = 389,
407  ARM_STC2L_OPTION = 390,
408  ARM_STC2L_POST = 391,
409  ARM_STC2L_PRE = 392,
410  ARM_STC2_OFFSET = 393,
411  ARM_STC2_OPTION = 394,
412  ARM_STC2_POST = 395,
413  ARM_STC2_PRE = 396,
414  ARM_STCL_OFFSET = 397,
415  ARM_STCL_OPTION = 398,
416  ARM_STCL_POST = 399,
417  ARM_STCL_PRE = 400,
418  ARM_STC_OFFSET = 401,
419  ARM_STC_OPTION = 402,
420  ARM_STC_POST = 403,
421  ARM_STC_PRE = 404,
422  ARM_STL = 405,
423  ARM_STLB = 406,
424  ARM_STLEX = 407,
425  ARM_STLEXB = 408,
426  ARM_STLEXD = 409,
427  ARM_STLEXH = 410,
428  ARM_STLH = 411,
429  ARM_STMDA = 412,
430  ARM_STMDA_UPD = 413,
431  ARM_STMDB = 414,
432  ARM_STMDB_UPD = 415,
433  ARM_STMIA = 416,
434  ARM_STMIA_UPD = 417,
435  ARM_STMIB = 418,
436  ARM_STMIB_UPD = 419,
437  ARM_STRBT_POST = 420,
438  ARM_STRBT_POST_IMM = 421,
439  ARM_STRBT_POST_REG = 422,
440  ARM_STRB_POST_IMM = 423,
441  ARM_STRB_POST_REG = 424,
442  ARM_STRB_PRE_IMM = 425,
443  ARM_STRB_PRE_REG = 426,
444  ARM_STRBi12 = 427,
445  ARM_STRBi_preidx = 428,
446  ARM_STRBr_preidx = 429,
447  ARM_STRBrs = 430,
448  ARM_STRD = 431,
449  ARM_STRD_POST = 432,
450  ARM_STRD_PRE = 433,
451  ARM_STREX = 434,
452  ARM_STREXB = 435,
453  ARM_STREXD = 436,
454  ARM_STREXH = 437,
455  ARM_STRH = 438,
456  ARM_STRHTi = 439,
457  ARM_STRHTr = 440,
458  ARM_STRH_POST = 441,
459  ARM_STRH_PRE = 442,
460  ARM_STRH_preidx = 443,
461  ARM_STRT_POST = 444,
462  ARM_STRT_POST_IMM = 445,
463  ARM_STRT_POST_REG = 446,
464  ARM_STR_POST_IMM = 447,
465  ARM_STR_POST_REG = 448,
466  ARM_STR_PRE_IMM = 449,
467  ARM_STR_PRE_REG = 450,
468  ARM_STRi12 = 451,
469  ARM_STRi_preidx = 452,
470  ARM_STRr_preidx = 453,
471  ARM_STRrs = 454,
472  ARM_SUBS_PC_LR = 455,
473  ARM_SUBSri = 456,
474  ARM_SUBSrr = 457,
475  ARM_SUBSrsi = 458,
476  ARM_SUBSrsr = 459,
477  ARM_SUBri = 460,
478  ARM_SUBrr = 461,
479  ARM_SUBrsi = 462,
480  ARM_SUBrsr = 463,
481  ARM_SVC = 464,
482  ARM_SWP = 465,
483  ARM_SWPB = 466,
484  ARM_SXTAB = 467,
485  ARM_SXTAB16 = 468,
486  ARM_SXTAH = 469,
487  ARM_SXTB = 470,
488  ARM_SXTB16 = 471,
489  ARM_SXTH = 472,
490  ARM_TAILJMPd = 473,
491  ARM_TAILJMPr = 474,
492  ARM_TCRETURNdi = 475,
493  ARM_TCRETURNri = 476,
494  ARM_TEQri = 477,
495  ARM_TEQrr = 478,
496  ARM_TEQrsi = 479,
497  ARM_TEQrsr = 480,
498  ARM_TPsoft = 481,
499  ARM_TRAP = 482,
500  ARM_TRAPNaCl = 483,
501  ARM_TSTri = 484,
502  ARM_TSTrr = 485,
503  ARM_TSTrsi = 486,
504  ARM_TSTrsr = 487,
505  ARM_UADD16 = 488,
506  ARM_UADD8 = 489,
507  ARM_UASX = 490,
508  ARM_UBFX = 491,
509  ARM_UDF = 492,
510  ARM_UDIV = 493,
511  ARM_UHADD16 = 494,
512  ARM_UHADD8 = 495,
513  ARM_UHASX = 496,
514  ARM_UHSAX = 497,
515  ARM_UHSUB16 = 498,
516  ARM_UHSUB8 = 499,
517  ARM_UMAAL = 500,
518  ARM_UMLAL = 501,
519  ARM_UMLALv5 = 502,
520  ARM_UMULL = 503,
521  ARM_UMULLv5 = 504,
522  ARM_UQADD16 = 505,
523  ARM_UQADD8 = 506,
524  ARM_UQASX = 507,
525  ARM_UQSAX = 508,
526  ARM_UQSUB16 = 509,
527  ARM_UQSUB8 = 510,
528  ARM_USAD8 = 511,
529  ARM_USADA8 = 512,
530  ARM_USAT = 513,
531  ARM_USAT16 = 514,
532  ARM_USAX = 515,
533  ARM_USUB16 = 516,
534  ARM_USUB8 = 517,
535  ARM_UXTAB = 518,
536  ARM_UXTAB16 = 519,
537  ARM_UXTAH = 520,
538  ARM_UXTB = 521,
539  ARM_UXTB16 = 522,
540  ARM_UXTH = 523,
541  ARM_VABALsv2i64 = 524,
542  ARM_VABALsv4i32 = 525,
543  ARM_VABALsv8i16 = 526,
544  ARM_VABALuv2i64 = 527,
545  ARM_VABALuv4i32 = 528,
546  ARM_VABALuv8i16 = 529,
547  ARM_VABAsv16i8 = 530,
548  ARM_VABAsv2i32 = 531,
549  ARM_VABAsv4i16 = 532,
550  ARM_VABAsv4i32 = 533,
551  ARM_VABAsv8i16 = 534,
552  ARM_VABAsv8i8 = 535,
553  ARM_VABAuv16i8 = 536,
554  ARM_VABAuv2i32 = 537,
555  ARM_VABAuv4i16 = 538,
556  ARM_VABAuv4i32 = 539,
557  ARM_VABAuv8i16 = 540,
558  ARM_VABAuv8i8 = 541,
559  ARM_VABDLsv2i64 = 542,
560  ARM_VABDLsv4i32 = 543,
561  ARM_VABDLsv8i16 = 544,
562  ARM_VABDLuv2i64 = 545,
563  ARM_VABDLuv4i32 = 546,
564  ARM_VABDLuv8i16 = 547,
565  ARM_VABDfd = 548,
566  ARM_VABDfq = 549,
567  ARM_VABDsv16i8 = 550,
568  ARM_VABDsv2i32 = 551,
569  ARM_VABDsv4i16 = 552,
570  ARM_VABDsv4i32 = 553,
571  ARM_VABDsv8i16 = 554,
572  ARM_VABDsv8i8 = 555,
573  ARM_VABDuv16i8 = 556,
574  ARM_VABDuv2i32 = 557,
575  ARM_VABDuv4i16 = 558,
576  ARM_VABDuv4i32 = 559,
577  ARM_VABDuv8i16 = 560,
578  ARM_VABDuv8i8 = 561,
579  ARM_VABSD = 562,
580  ARM_VABSS = 563,
581  ARM_VABSfd = 564,
582  ARM_VABSfq = 565,
583  ARM_VABSv16i8 = 566,
584  ARM_VABSv2i32 = 567,
585  ARM_VABSv4i16 = 568,
586  ARM_VABSv4i32 = 569,
587  ARM_VABSv8i16 = 570,
588  ARM_VABSv8i8 = 571,
589  ARM_VACGEd = 572,
590  ARM_VACGEq = 573,
591  ARM_VACGTd = 574,
592  ARM_VACGTq = 575,
593  ARM_VADDD = 576,
594  ARM_VADDHNv2i32 = 577,
595  ARM_VADDHNv4i16 = 578,
596  ARM_VADDHNv8i8 = 579,
597  ARM_VADDLsv2i64 = 580,
598  ARM_VADDLsv4i32 = 581,
599  ARM_VADDLsv8i16 = 582,
600  ARM_VADDLuv2i64 = 583,
601  ARM_VADDLuv4i32 = 584,
602  ARM_VADDLuv8i16 = 585,
603  ARM_VADDS = 586,
604  ARM_VADDWsv2i64 = 587,
605  ARM_VADDWsv4i32 = 588,
606  ARM_VADDWsv8i16 = 589,
607  ARM_VADDWuv2i64 = 590,
608  ARM_VADDWuv4i32 = 591,
609  ARM_VADDWuv8i16 = 592,
610  ARM_VADDfd = 593,
611  ARM_VADDfq = 594,
612  ARM_VADDv16i8 = 595,
613  ARM_VADDv1i64 = 596,
614  ARM_VADDv2i32 = 597,
615  ARM_VADDv2i64 = 598,
616  ARM_VADDv4i16 = 599,
617  ARM_VADDv4i32 = 600,
618  ARM_VADDv8i16 = 601,
619  ARM_VADDv8i8 = 602,
620  ARM_VANDd = 603,
621  ARM_VANDq = 604,
622  ARM_VBICd = 605,
623  ARM_VBICiv2i32 = 606,
624  ARM_VBICiv4i16 = 607,
625  ARM_VBICiv4i32 = 608,
626  ARM_VBICiv8i16 = 609,
627  ARM_VBICq = 610,
628  ARM_VBIFd = 611,
629  ARM_VBIFq = 612,
630  ARM_VBITd = 613,
631  ARM_VBITq = 614,
632  ARM_VBSLd = 615,
633  ARM_VBSLq = 616,
634  ARM_VCEQfd = 617,
635  ARM_VCEQfq = 618,
636  ARM_VCEQv16i8 = 619,
637  ARM_VCEQv2i32 = 620,
638  ARM_VCEQv4i16 = 621,
639  ARM_VCEQv4i32 = 622,
640  ARM_VCEQv8i16 = 623,
641  ARM_VCEQv8i8 = 624,
642  ARM_VCEQzv16i8 = 625,
643  ARM_VCEQzv2f32 = 626,
644  ARM_VCEQzv2i32 = 627,
645  ARM_VCEQzv4f32 = 628,
646  ARM_VCEQzv4i16 = 629,
647  ARM_VCEQzv4i32 = 630,
648  ARM_VCEQzv8i16 = 631,
649  ARM_VCEQzv8i8 = 632,
650  ARM_VCGEfd = 633,
651  ARM_VCGEfq = 634,
652  ARM_VCGEsv16i8 = 635,
653  ARM_VCGEsv2i32 = 636,
654  ARM_VCGEsv4i16 = 637,
655  ARM_VCGEsv4i32 = 638,
656  ARM_VCGEsv8i16 = 639,
657  ARM_VCGEsv8i8 = 640,
658  ARM_VCGEuv16i8 = 641,
659  ARM_VCGEuv2i32 = 642,
660  ARM_VCGEuv4i16 = 643,
661  ARM_VCGEuv4i32 = 644,
662  ARM_VCGEuv8i16 = 645,
663  ARM_VCGEuv8i8 = 646,
664  ARM_VCGEzv16i8 = 647,
665  ARM_VCGEzv2f32 = 648,
666  ARM_VCGEzv2i32 = 649,
667  ARM_VCGEzv4f32 = 650,
668  ARM_VCGEzv4i16 = 651,
669  ARM_VCGEzv4i32 = 652,
670  ARM_VCGEzv8i16 = 653,
671  ARM_VCGEzv8i8 = 654,
672  ARM_VCGTfd = 655,
673  ARM_VCGTfq = 656,
674  ARM_VCGTsv16i8 = 657,
675  ARM_VCGTsv2i32 = 658,
676  ARM_VCGTsv4i16 = 659,
677  ARM_VCGTsv4i32 = 660,
678  ARM_VCGTsv8i16 = 661,
679  ARM_VCGTsv8i8 = 662,
680  ARM_VCGTuv16i8 = 663,
681  ARM_VCGTuv2i32 = 664,
682  ARM_VCGTuv4i16 = 665,
683  ARM_VCGTuv4i32 = 666,
684  ARM_VCGTuv8i16 = 667,
685  ARM_VCGTuv8i8 = 668,
686  ARM_VCGTzv16i8 = 669,
687  ARM_VCGTzv2f32 = 670,
688  ARM_VCGTzv2i32 = 671,
689  ARM_VCGTzv4f32 = 672,
690  ARM_VCGTzv4i16 = 673,
691  ARM_VCGTzv4i32 = 674,
692  ARM_VCGTzv8i16 = 675,
693  ARM_VCGTzv8i8 = 676,
694  ARM_VCLEzv16i8 = 677,
695  ARM_VCLEzv2f32 = 678,
696  ARM_VCLEzv2i32 = 679,
697  ARM_VCLEzv4f32 = 680,
698  ARM_VCLEzv4i16 = 681,
699  ARM_VCLEzv4i32 = 682,
700  ARM_VCLEzv8i16 = 683,
701  ARM_VCLEzv8i8 = 684,
702  ARM_VCLSv16i8 = 685,
703  ARM_VCLSv2i32 = 686,
704  ARM_VCLSv4i16 = 687,
705  ARM_VCLSv4i32 = 688,
706  ARM_VCLSv8i16 = 689,
707  ARM_VCLSv8i8 = 690,
708  ARM_VCLTzv16i8 = 691,
709  ARM_VCLTzv2f32 = 692,
710  ARM_VCLTzv2i32 = 693,
711  ARM_VCLTzv4f32 = 694,
712  ARM_VCLTzv4i16 = 695,
713  ARM_VCLTzv4i32 = 696,
714  ARM_VCLTzv8i16 = 697,
715  ARM_VCLTzv8i8 = 698,
716  ARM_VCLZv16i8 = 699,
717  ARM_VCLZv2i32 = 700,
718  ARM_VCLZv4i16 = 701,
719  ARM_VCLZv4i32 = 702,
720  ARM_VCLZv8i16 = 703,
721  ARM_VCLZv8i8 = 704,
722  ARM_VCMPD = 705,
723  ARM_VCMPED = 706,
724  ARM_VCMPES = 707,
725  ARM_VCMPEZD = 708,
726  ARM_VCMPEZS = 709,
727  ARM_VCMPS = 710,
728  ARM_VCMPZD = 711,
729  ARM_VCMPZS = 712,
730  ARM_VCNTd = 713,
731  ARM_VCNTq = 714,
732  ARM_VCVTANSD = 715,
733  ARM_VCVTANSQ = 716,
734  ARM_VCVTANUD = 717,
735  ARM_VCVTANUQ = 718,
736  ARM_VCVTASD = 719,
737  ARM_VCVTASS = 720,
738  ARM_VCVTAUD = 721,
739  ARM_VCVTAUS = 722,
740  ARM_VCVTBDH = 723,
741  ARM_VCVTBHD = 724,
742  ARM_VCVTBHS = 725,
743  ARM_VCVTBSH = 726,
744  ARM_VCVTDS = 727,
745  ARM_VCVTMNSD = 728,
746  ARM_VCVTMNSQ = 729,
747  ARM_VCVTMNUD = 730,
748  ARM_VCVTMNUQ = 731,
749  ARM_VCVTMSD = 732,
750  ARM_VCVTMSS = 733,
751  ARM_VCVTMUD = 734,
752  ARM_VCVTMUS = 735,
753  ARM_VCVTNNSD = 736,
754  ARM_VCVTNNSQ = 737,
755  ARM_VCVTNNUD = 738,
756  ARM_VCVTNNUQ = 739,
757  ARM_VCVTNSD = 740,
758  ARM_VCVTNSS = 741,
759  ARM_VCVTNUD = 742,
760  ARM_VCVTNUS = 743,
761  ARM_VCVTPNSD = 744,
762  ARM_VCVTPNSQ = 745,
763  ARM_VCVTPNUD = 746,
764  ARM_VCVTPNUQ = 747,
765  ARM_VCVTPSD = 748,
766  ARM_VCVTPSS = 749,
767  ARM_VCVTPUD = 750,
768  ARM_VCVTPUS = 751,
769  ARM_VCVTSD = 752,
770  ARM_VCVTTDH = 753,
771  ARM_VCVTTHD = 754,
772  ARM_VCVTTHS = 755,
773  ARM_VCVTTSH = 756,
774  ARM_VCVTf2h = 757,
775  ARM_VCVTf2sd = 758,
776  ARM_VCVTf2sq = 759,
777  ARM_VCVTf2ud = 760,
778  ARM_VCVTf2uq = 761,
779  ARM_VCVTf2xsd = 762,
780  ARM_VCVTf2xsq = 763,
781  ARM_VCVTf2xud = 764,
782  ARM_VCVTf2xuq = 765,
783  ARM_VCVTh2f = 766,
784  ARM_VCVTs2fd = 767,
785  ARM_VCVTs2fq = 768,
786  ARM_VCVTu2fd = 769,
787  ARM_VCVTu2fq = 770,
788  ARM_VCVTxs2fd = 771,
789  ARM_VCVTxs2fq = 772,
790  ARM_VCVTxu2fd = 773,
791  ARM_VCVTxu2fq = 774,
792  ARM_VDIVD = 775,
793  ARM_VDIVS = 776,
794  ARM_VDUP16d = 777,
795  ARM_VDUP16q = 778,
796  ARM_VDUP32d = 779,
797  ARM_VDUP32q = 780,
798  ARM_VDUP8d = 781,
799  ARM_VDUP8q = 782,
800  ARM_VDUPLN16d = 783,
801  ARM_VDUPLN16q = 784,
802  ARM_VDUPLN32d = 785,
803  ARM_VDUPLN32q = 786,
804  ARM_VDUPLN8d = 787,
805  ARM_VDUPLN8q = 788,
806  ARM_VEORd = 789,
807  ARM_VEORq = 790,
808  ARM_VEXTd16 = 791,
809  ARM_VEXTd32 = 792,
810  ARM_VEXTd8 = 793,
811  ARM_VEXTq16 = 794,
812  ARM_VEXTq32 = 795,
813  ARM_VEXTq64 = 796,
814  ARM_VEXTq8 = 797,
815  ARM_VFMAD = 798,
816  ARM_VFMAS = 799,
817  ARM_VFMAfd = 800,
818  ARM_VFMAfq = 801,
819  ARM_VFMSD = 802,
820  ARM_VFMSS = 803,
821  ARM_VFMSfd = 804,
822  ARM_VFMSfq = 805,
823  ARM_VFNMAD = 806,
824  ARM_VFNMAS = 807,
825  ARM_VFNMSD = 808,
826  ARM_VFNMSS = 809,
827  ARM_VGETLNi32 = 810,
828  ARM_VGETLNs16 = 811,
829  ARM_VGETLNs8 = 812,
830  ARM_VGETLNu16 = 813,
831  ARM_VGETLNu8 = 814,
832  ARM_VHADDsv16i8 = 815,
833  ARM_VHADDsv2i32 = 816,
834  ARM_VHADDsv4i16 = 817,
835  ARM_VHADDsv4i32 = 818,
836  ARM_VHADDsv8i16 = 819,
837  ARM_VHADDsv8i8 = 820,
838  ARM_VHADDuv16i8 = 821,
839  ARM_VHADDuv2i32 = 822,
840  ARM_VHADDuv4i16 = 823,
841  ARM_VHADDuv4i32 = 824,
842  ARM_VHADDuv8i16 = 825,
843  ARM_VHADDuv8i8 = 826,
844  ARM_VHSUBsv16i8 = 827,
845  ARM_VHSUBsv2i32 = 828,
846  ARM_VHSUBsv4i16 = 829,
847  ARM_VHSUBsv4i32 = 830,
848  ARM_VHSUBsv8i16 = 831,
849  ARM_VHSUBsv8i8 = 832,
850  ARM_VHSUBuv16i8 = 833,
851  ARM_VHSUBuv2i32 = 834,
852  ARM_VHSUBuv4i16 = 835,
853  ARM_VHSUBuv4i32 = 836,
854  ARM_VHSUBuv8i16 = 837,
855  ARM_VHSUBuv8i8 = 838,
856  ARM_VLD1DUPd16 = 839,
857  ARM_VLD1DUPd16wb_fixed = 840,
858  ARM_VLD1DUPd16wb_register = 841,
859  ARM_VLD1DUPd32 = 842,
860  ARM_VLD1DUPd32wb_fixed = 843,
861  ARM_VLD1DUPd32wb_register = 844,
862  ARM_VLD1DUPd8 = 845,
863  ARM_VLD1DUPd8wb_fixed = 846,
864  ARM_VLD1DUPd8wb_register = 847,
865  ARM_VLD1DUPq16 = 848,
866  ARM_VLD1DUPq16wb_fixed = 849,
867  ARM_VLD1DUPq16wb_register = 850,
868  ARM_VLD1DUPq32 = 851,
869  ARM_VLD1DUPq32wb_fixed = 852,
870  ARM_VLD1DUPq32wb_register = 853,
871  ARM_VLD1DUPq8 = 854,
872  ARM_VLD1DUPq8wb_fixed = 855,
873  ARM_VLD1DUPq8wb_register = 856,
874  ARM_VLD1LNd16 = 857,
875  ARM_VLD1LNd16_UPD = 858,
876  ARM_VLD1LNd32 = 859,
877  ARM_VLD1LNd32_UPD = 860,
878  ARM_VLD1LNd8 = 861,
879  ARM_VLD1LNd8_UPD = 862,
880  ARM_VLD1LNdAsm_16 = 863,
881  ARM_VLD1LNdAsm_32 = 864,
882  ARM_VLD1LNdAsm_8 = 865,
883  ARM_VLD1LNdWB_fixed_Asm_16 = 866,
884  ARM_VLD1LNdWB_fixed_Asm_32 = 867,
885  ARM_VLD1LNdWB_fixed_Asm_8 = 868,
886  ARM_VLD1LNdWB_register_Asm_16 = 869,
887  ARM_VLD1LNdWB_register_Asm_32 = 870,
888  ARM_VLD1LNdWB_register_Asm_8 = 871,
889  ARM_VLD1LNq16Pseudo = 872,
890  ARM_VLD1LNq16Pseudo_UPD = 873,
891  ARM_VLD1LNq32Pseudo = 874,
892  ARM_VLD1LNq32Pseudo_UPD = 875,
893  ARM_VLD1LNq8Pseudo = 876,
894  ARM_VLD1LNq8Pseudo_UPD = 877,
895  ARM_VLD1d16 = 878,
896  ARM_VLD1d16Q = 879,
897  ARM_VLD1d16Qwb_fixed = 880,
898  ARM_VLD1d16Qwb_register = 881,
899  ARM_VLD1d16T = 882,
900  ARM_VLD1d16Twb_fixed = 883,
901  ARM_VLD1d16Twb_register = 884,
902  ARM_VLD1d16wb_fixed = 885,
903  ARM_VLD1d16wb_register = 886,
904  ARM_VLD1d32 = 887,
905  ARM_VLD1d32Q = 888,
906  ARM_VLD1d32Qwb_fixed = 889,
907  ARM_VLD1d32Qwb_register = 890,
908  ARM_VLD1d32T = 891,
909  ARM_VLD1d32Twb_fixed = 892,
910  ARM_VLD1d32Twb_register = 893,
911  ARM_VLD1d32wb_fixed = 894,
912  ARM_VLD1d32wb_register = 895,
913  ARM_VLD1d64 = 896,
914  ARM_VLD1d64Q = 897,
915  ARM_VLD1d64QPseudo = 898,
916  ARM_VLD1d64QPseudoWB_fixed = 899,
917  ARM_VLD1d64QPseudoWB_register = 900,
918  ARM_VLD1d64Qwb_fixed = 901,
919  ARM_VLD1d64Qwb_register = 902,
920  ARM_VLD1d64T = 903,
921  ARM_VLD1d64TPseudo = 904,
922  ARM_VLD1d64TPseudoWB_fixed = 905,
923  ARM_VLD1d64TPseudoWB_register = 906,
924  ARM_VLD1d64Twb_fixed = 907,
925  ARM_VLD1d64Twb_register = 908,
926  ARM_VLD1d64wb_fixed = 909,
927  ARM_VLD1d64wb_register = 910,
928  ARM_VLD1d8 = 911,
929  ARM_VLD1d8Q = 912,
930  ARM_VLD1d8Qwb_fixed = 913,
931  ARM_VLD1d8Qwb_register = 914,
932  ARM_VLD1d8T = 915,
933  ARM_VLD1d8Twb_fixed = 916,
934  ARM_VLD1d8Twb_register = 917,
935  ARM_VLD1d8wb_fixed = 918,
936  ARM_VLD1d8wb_register = 919,
937  ARM_VLD1q16 = 920,
938  ARM_VLD1q16wb_fixed = 921,
939  ARM_VLD1q16wb_register = 922,
940  ARM_VLD1q32 = 923,
941  ARM_VLD1q32wb_fixed = 924,
942  ARM_VLD1q32wb_register = 925,
943  ARM_VLD1q64 = 926,
944  ARM_VLD1q64wb_fixed = 927,
945  ARM_VLD1q64wb_register = 928,
946  ARM_VLD1q8 = 929,
947  ARM_VLD1q8wb_fixed = 930,
948  ARM_VLD1q8wb_register = 931,
949  ARM_VLD2DUPd16 = 932,
950  ARM_VLD2DUPd16wb_fixed = 933,
951  ARM_VLD2DUPd16wb_register = 934,
952  ARM_VLD2DUPd16x2 = 935,
953  ARM_VLD2DUPd16x2wb_fixed = 936,
954  ARM_VLD2DUPd16x2wb_register = 937,
955  ARM_VLD2DUPd32 = 938,
956  ARM_VLD2DUPd32wb_fixed = 939,
957  ARM_VLD2DUPd32wb_register = 940,
958  ARM_VLD2DUPd32x2 = 941,
959  ARM_VLD2DUPd32x2wb_fixed = 942,
960  ARM_VLD2DUPd32x2wb_register = 943,
961  ARM_VLD2DUPd8 = 944,
962  ARM_VLD2DUPd8wb_fixed = 945,
963  ARM_VLD2DUPd8wb_register = 946,
964  ARM_VLD2DUPd8x2 = 947,
965  ARM_VLD2DUPd8x2wb_fixed = 948,
966  ARM_VLD2DUPd8x2wb_register = 949,
967  ARM_VLD2LNd16 = 950,
968  ARM_VLD2LNd16Pseudo = 951,
969  ARM_VLD2LNd16Pseudo_UPD = 952,
970  ARM_VLD2LNd16_UPD = 953,
971  ARM_VLD2LNd32 = 954,
972  ARM_VLD2LNd32Pseudo = 955,
973  ARM_VLD2LNd32Pseudo_UPD = 956,
974  ARM_VLD2LNd32_UPD = 957,
975  ARM_VLD2LNd8 = 958,
976  ARM_VLD2LNd8Pseudo = 959,
977  ARM_VLD2LNd8Pseudo_UPD = 960,
978  ARM_VLD2LNd8_UPD = 961,
979  ARM_VLD2LNdAsm_16 = 962,
980  ARM_VLD2LNdAsm_32 = 963,
981  ARM_VLD2LNdAsm_8 = 964,
982  ARM_VLD2LNdWB_fixed_Asm_16 = 965,
983  ARM_VLD2LNdWB_fixed_Asm_32 = 966,
984  ARM_VLD2LNdWB_fixed_Asm_8 = 967,
985  ARM_VLD2LNdWB_register_Asm_16 = 968,
986  ARM_VLD2LNdWB_register_Asm_32 = 969,
987  ARM_VLD2LNdWB_register_Asm_8 = 970,
988  ARM_VLD2LNq16 = 971,
989  ARM_VLD2LNq16Pseudo = 972,
990  ARM_VLD2LNq16Pseudo_UPD = 973,
991  ARM_VLD2LNq16_UPD = 974,
992  ARM_VLD2LNq32 = 975,
993  ARM_VLD2LNq32Pseudo = 976,
994  ARM_VLD2LNq32Pseudo_UPD = 977,
995  ARM_VLD2LNq32_UPD = 978,
996  ARM_VLD2LNqAsm_16 = 979,
997  ARM_VLD2LNqAsm_32 = 980,
998  ARM_VLD2LNqWB_fixed_Asm_16 = 981,
999  ARM_VLD2LNqWB_fixed_Asm_32 = 982,
1000  ARM_VLD2LNqWB_register_Asm_16 = 983,
1001  ARM_VLD2LNqWB_register_Asm_32 = 984,
1002  ARM_VLD2b16 = 985,
1003  ARM_VLD2b16wb_fixed = 986,
1004  ARM_VLD2b16wb_register = 987,
1005  ARM_VLD2b32 = 988,
1006  ARM_VLD2b32wb_fixed = 989,
1007  ARM_VLD2b32wb_register = 990,
1008  ARM_VLD2b8 = 991,
1009  ARM_VLD2b8wb_fixed = 992,
1010  ARM_VLD2b8wb_register = 993,
1011  ARM_VLD2d16 = 994,
1012  ARM_VLD2d16wb_fixed = 995,
1013  ARM_VLD2d16wb_register = 996,
1014  ARM_VLD2d32 = 997,
1015  ARM_VLD2d32wb_fixed = 998,
1016  ARM_VLD2d32wb_register = 999,
1017  ARM_VLD2d8 = 1000,
1018  ARM_VLD2d8wb_fixed = 1001,
1019  ARM_VLD2d8wb_register = 1002,
1020  ARM_VLD2q16 = 1003,
1021  ARM_VLD2q16Pseudo = 1004,
1022  ARM_VLD2q16PseudoWB_fixed = 1005,
1023  ARM_VLD2q16PseudoWB_register = 1006,
1024  ARM_VLD2q16wb_fixed = 1007,
1025  ARM_VLD2q16wb_register = 1008,
1026  ARM_VLD2q32 = 1009,
1027  ARM_VLD2q32Pseudo = 1010,
1028  ARM_VLD2q32PseudoWB_fixed = 1011,
1029  ARM_VLD2q32PseudoWB_register = 1012,
1030  ARM_VLD2q32wb_fixed = 1013,
1031  ARM_VLD2q32wb_register = 1014,
1032  ARM_VLD2q8 = 1015,
1033  ARM_VLD2q8Pseudo = 1016,
1034  ARM_VLD2q8PseudoWB_fixed = 1017,
1035  ARM_VLD2q8PseudoWB_register = 1018,
1036  ARM_VLD2q8wb_fixed = 1019,
1037  ARM_VLD2q8wb_register = 1020,
1038  ARM_VLD3DUPd16 = 1021,
1039  ARM_VLD3DUPd16Pseudo = 1022,
1040  ARM_VLD3DUPd16Pseudo_UPD = 1023,
1041  ARM_VLD3DUPd16_UPD = 1024,
1042  ARM_VLD3DUPd32 = 1025,
1043  ARM_VLD3DUPd32Pseudo = 1026,
1044  ARM_VLD3DUPd32Pseudo_UPD = 1027,
1045  ARM_VLD3DUPd32_UPD = 1028,
1046  ARM_VLD3DUPd8 = 1029,
1047  ARM_VLD3DUPd8Pseudo = 1030,
1048  ARM_VLD3DUPd8Pseudo_UPD = 1031,
1049  ARM_VLD3DUPd8_UPD = 1032,
1050  ARM_VLD3DUPdAsm_16 = 1033,
1051  ARM_VLD3DUPdAsm_32 = 1034,
1052  ARM_VLD3DUPdAsm_8 = 1035,
1053  ARM_VLD3DUPdWB_fixed_Asm_16 = 1036,
1054  ARM_VLD3DUPdWB_fixed_Asm_32 = 1037,
1055  ARM_VLD3DUPdWB_fixed_Asm_8 = 1038,
1056  ARM_VLD3DUPdWB_register_Asm_16 = 1039,
1057  ARM_VLD3DUPdWB_register_Asm_32 = 1040,
1058  ARM_VLD3DUPdWB_register_Asm_8 = 1041,
1059  ARM_VLD3DUPq16 = 1042,
1060  ARM_VLD3DUPq16_UPD = 1043,
1061  ARM_VLD3DUPq32 = 1044,
1062  ARM_VLD3DUPq32_UPD = 1045,
1063  ARM_VLD3DUPq8 = 1046,
1064  ARM_VLD3DUPq8_UPD = 1047,
1065  ARM_VLD3DUPqAsm_16 = 1048,
1066  ARM_VLD3DUPqAsm_32 = 1049,
1067  ARM_VLD3DUPqAsm_8 = 1050,
1068  ARM_VLD3DUPqWB_fixed_Asm_16 = 1051,
1069  ARM_VLD3DUPqWB_fixed_Asm_32 = 1052,
1070  ARM_VLD3DUPqWB_fixed_Asm_8 = 1053,
1071  ARM_VLD3DUPqWB_register_Asm_16 = 1054,
1072  ARM_VLD3DUPqWB_register_Asm_32 = 1055,
1073  ARM_VLD3DUPqWB_register_Asm_8 = 1056,
1074  ARM_VLD3LNd16 = 1057,
1075  ARM_VLD3LNd16Pseudo = 1058,
1076  ARM_VLD3LNd16Pseudo_UPD = 1059,
1077  ARM_VLD3LNd16_UPD = 1060,
1078  ARM_VLD3LNd32 = 1061,
1079  ARM_VLD3LNd32Pseudo = 1062,
1080  ARM_VLD3LNd32Pseudo_UPD = 1063,
1081  ARM_VLD3LNd32_UPD = 1064,
1082  ARM_VLD3LNd8 = 1065,
1083  ARM_VLD3LNd8Pseudo = 1066,
1084  ARM_VLD3LNd8Pseudo_UPD = 1067,
1085  ARM_VLD3LNd8_UPD = 1068,
1086  ARM_VLD3LNdAsm_16 = 1069,
1087  ARM_VLD3LNdAsm_32 = 1070,
1088  ARM_VLD3LNdAsm_8 = 1071,
1089  ARM_VLD3LNdWB_fixed_Asm_16 = 1072,
1090  ARM_VLD3LNdWB_fixed_Asm_32 = 1073,
1091  ARM_VLD3LNdWB_fixed_Asm_8 = 1074,
1092  ARM_VLD3LNdWB_register_Asm_16 = 1075,
1093  ARM_VLD3LNdWB_register_Asm_32 = 1076,
1094  ARM_VLD3LNdWB_register_Asm_8 = 1077,
1095  ARM_VLD3LNq16 = 1078,
1096  ARM_VLD3LNq16Pseudo = 1079,
1097  ARM_VLD3LNq16Pseudo_UPD = 1080,
1098  ARM_VLD3LNq16_UPD = 1081,
1099  ARM_VLD3LNq32 = 1082,
1100  ARM_VLD3LNq32Pseudo = 1083,
1101  ARM_VLD3LNq32Pseudo_UPD = 1084,
1102  ARM_VLD3LNq32_UPD = 1085,
1103  ARM_VLD3LNqAsm_16 = 1086,
1104  ARM_VLD3LNqAsm_32 = 1087,
1105  ARM_VLD3LNqWB_fixed_Asm_16 = 1088,
1106  ARM_VLD3LNqWB_fixed_Asm_32 = 1089,
1107  ARM_VLD3LNqWB_register_Asm_16 = 1090,
1108  ARM_VLD3LNqWB_register_Asm_32 = 1091,
1109  ARM_VLD3d16 = 1092,
1110  ARM_VLD3d16Pseudo = 1093,
1111  ARM_VLD3d16Pseudo_UPD = 1094,
1112  ARM_VLD3d16_UPD = 1095,
1113  ARM_VLD3d32 = 1096,
1114  ARM_VLD3d32Pseudo = 1097,
1115  ARM_VLD3d32Pseudo_UPD = 1098,
1116  ARM_VLD3d32_UPD = 1099,
1117  ARM_VLD3d8 = 1100,
1118  ARM_VLD3d8Pseudo = 1101,
1119  ARM_VLD3d8Pseudo_UPD = 1102,
1120  ARM_VLD3d8_UPD = 1103,
1121  ARM_VLD3dAsm_16 = 1104,
1122  ARM_VLD3dAsm_32 = 1105,
1123  ARM_VLD3dAsm_8 = 1106,
1124  ARM_VLD3dWB_fixed_Asm_16 = 1107,
1125  ARM_VLD3dWB_fixed_Asm_32 = 1108,
1126  ARM_VLD3dWB_fixed_Asm_8 = 1109,
1127  ARM_VLD3dWB_register_Asm_16 = 1110,
1128  ARM_VLD3dWB_register_Asm_32 = 1111,
1129  ARM_VLD3dWB_register_Asm_8 = 1112,
1130  ARM_VLD3q16 = 1113,
1131  ARM_VLD3q16Pseudo_UPD = 1114,
1132  ARM_VLD3q16_UPD = 1115,
1133  ARM_VLD3q16oddPseudo = 1116,
1134  ARM_VLD3q16oddPseudo_UPD = 1117,
1135  ARM_VLD3q32 = 1118,
1136  ARM_VLD3q32Pseudo_UPD = 1119,
1137  ARM_VLD3q32_UPD = 1120,
1138  ARM_VLD3q32oddPseudo = 1121,
1139  ARM_VLD3q32oddPseudo_UPD = 1122,
1140  ARM_VLD3q8 = 1123,
1141  ARM_VLD3q8Pseudo_UPD = 1124,
1142  ARM_VLD3q8_UPD = 1125,
1143  ARM_VLD3q8oddPseudo = 1126,
1144  ARM_VLD3q8oddPseudo_UPD = 1127,
1145  ARM_VLD3qAsm_16 = 1128,
1146  ARM_VLD3qAsm_32 = 1129,
1147  ARM_VLD3qAsm_8 = 1130,
1148  ARM_VLD3qWB_fixed_Asm_16 = 1131,
1149  ARM_VLD3qWB_fixed_Asm_32 = 1132,
1150  ARM_VLD3qWB_fixed_Asm_8 = 1133,
1151  ARM_VLD3qWB_register_Asm_16 = 1134,
1152  ARM_VLD3qWB_register_Asm_32 = 1135,
1153  ARM_VLD3qWB_register_Asm_8 = 1136,
1154  ARM_VLD4DUPd16 = 1137,
1155  ARM_VLD4DUPd16Pseudo = 1138,
1156  ARM_VLD4DUPd16Pseudo_UPD = 1139,
1157  ARM_VLD4DUPd16_UPD = 1140,
1158  ARM_VLD4DUPd32 = 1141,
1159  ARM_VLD4DUPd32Pseudo = 1142,
1160  ARM_VLD4DUPd32Pseudo_UPD = 1143,
1161  ARM_VLD4DUPd32_UPD = 1144,
1162  ARM_VLD4DUPd8 = 1145,
1163  ARM_VLD4DUPd8Pseudo = 1146,
1164  ARM_VLD4DUPd8Pseudo_UPD = 1147,
1165  ARM_VLD4DUPd8_UPD = 1148,
1166  ARM_VLD4DUPdAsm_16 = 1149,
1167  ARM_VLD4DUPdAsm_32 = 1150,
1168  ARM_VLD4DUPdAsm_8 = 1151,
1169  ARM_VLD4DUPdWB_fixed_Asm_16 = 1152,
1170  ARM_VLD4DUPdWB_fixed_Asm_32 = 1153,
1171  ARM_VLD4DUPdWB_fixed_Asm_8 = 1154,
1172  ARM_VLD4DUPdWB_register_Asm_16 = 1155,
1173  ARM_VLD4DUPdWB_register_Asm_32 = 1156,
1174  ARM_VLD4DUPdWB_register_Asm_8 = 1157,
1175  ARM_VLD4DUPq16 = 1158,
1176  ARM_VLD4DUPq16_UPD = 1159,
1177  ARM_VLD4DUPq32 = 1160,
1178  ARM_VLD4DUPq32_UPD = 1161,
1179  ARM_VLD4DUPq8 = 1162,
1180  ARM_VLD4DUPq8_UPD = 1163,
1181  ARM_VLD4DUPqAsm_16 = 1164,
1182  ARM_VLD4DUPqAsm_32 = 1165,
1183  ARM_VLD4DUPqAsm_8 = 1166,
1184  ARM_VLD4DUPqWB_fixed_Asm_16 = 1167,
1185  ARM_VLD4DUPqWB_fixed_Asm_32 = 1168,
1186  ARM_VLD4DUPqWB_fixed_Asm_8 = 1169,
1187  ARM_VLD4DUPqWB_register_Asm_16 = 1170,
1188  ARM_VLD4DUPqWB_register_Asm_32 = 1171,
1189  ARM_VLD4DUPqWB_register_Asm_8 = 1172,
1190  ARM_VLD4LNd16 = 1173,
1191  ARM_VLD4LNd16Pseudo = 1174,
1192  ARM_VLD4LNd16Pseudo_UPD = 1175,
1193  ARM_VLD4LNd16_UPD = 1176,
1194  ARM_VLD4LNd32 = 1177,
1195  ARM_VLD4LNd32Pseudo = 1178,
1196  ARM_VLD4LNd32Pseudo_UPD = 1179,
1197  ARM_VLD4LNd32_UPD = 1180,
1198  ARM_VLD4LNd8 = 1181,
1199  ARM_VLD4LNd8Pseudo = 1182,
1200  ARM_VLD4LNd8Pseudo_UPD = 1183,
1201  ARM_VLD4LNd8_UPD = 1184,
1202  ARM_VLD4LNdAsm_16 = 1185,
1203  ARM_VLD4LNdAsm_32 = 1186,
1204  ARM_VLD4LNdAsm_8 = 1187,
1205  ARM_VLD4LNdWB_fixed_Asm_16 = 1188,
1206  ARM_VLD4LNdWB_fixed_Asm_32 = 1189,
1207  ARM_VLD4LNdWB_fixed_Asm_8 = 1190,
1208  ARM_VLD4LNdWB_register_Asm_16 = 1191,
1209  ARM_VLD4LNdWB_register_Asm_32 = 1192,
1210  ARM_VLD4LNdWB_register_Asm_8 = 1193,
1211  ARM_VLD4LNq16 = 1194,
1212  ARM_VLD4LNq16Pseudo = 1195,
1213  ARM_VLD4LNq16Pseudo_UPD = 1196,
1214  ARM_VLD4LNq16_UPD = 1197,
1215  ARM_VLD4LNq32 = 1198,
1216  ARM_VLD4LNq32Pseudo = 1199,
1217  ARM_VLD4LNq32Pseudo_UPD = 1200,
1218  ARM_VLD4LNq32_UPD = 1201,
1219  ARM_VLD4LNqAsm_16 = 1202,
1220  ARM_VLD4LNqAsm_32 = 1203,
1221  ARM_VLD4LNqWB_fixed_Asm_16 = 1204,
1222  ARM_VLD4LNqWB_fixed_Asm_32 = 1205,
1223  ARM_VLD4LNqWB_register_Asm_16 = 1206,
1224  ARM_VLD4LNqWB_register_Asm_32 = 1207,
1225  ARM_VLD4d16 = 1208,
1226  ARM_VLD4d16Pseudo = 1209,
1227  ARM_VLD4d16Pseudo_UPD = 1210,
1228  ARM_VLD4d16_UPD = 1211,
1229  ARM_VLD4d32 = 1212,
1230  ARM_VLD4d32Pseudo = 1213,
1231  ARM_VLD4d32Pseudo_UPD = 1214,
1232  ARM_VLD4d32_UPD = 1215,
1233  ARM_VLD4d8 = 1216,
1234  ARM_VLD4d8Pseudo = 1217,
1235  ARM_VLD4d8Pseudo_UPD = 1218,
1236  ARM_VLD4d8_UPD = 1219,
1237  ARM_VLD4dAsm_16 = 1220,
1238  ARM_VLD4dAsm_32 = 1221,
1239  ARM_VLD4dAsm_8 = 1222,
1240  ARM_VLD4dWB_fixed_Asm_16 = 1223,
1241  ARM_VLD4dWB_fixed_Asm_32 = 1224,
1242  ARM_VLD4dWB_fixed_Asm_8 = 1225,
1243  ARM_VLD4dWB_register_Asm_16 = 1226,
1244  ARM_VLD4dWB_register_Asm_32 = 1227,
1245  ARM_VLD4dWB_register_Asm_8 = 1228,
1246  ARM_VLD4q16 = 1229,
1247  ARM_VLD4q16Pseudo_UPD = 1230,
1248  ARM_VLD4q16_UPD = 1231,
1249  ARM_VLD4q16oddPseudo = 1232,
1250  ARM_VLD4q16oddPseudo_UPD = 1233,
1251  ARM_VLD4q32 = 1234,
1252  ARM_VLD4q32Pseudo_UPD = 1235,
1253  ARM_VLD4q32_UPD = 1236,
1254  ARM_VLD4q32oddPseudo = 1237,
1255  ARM_VLD4q32oddPseudo_UPD = 1238,
1256  ARM_VLD4q8 = 1239,
1257  ARM_VLD4q8Pseudo_UPD = 1240,
1258  ARM_VLD4q8_UPD = 1241,
1259  ARM_VLD4q8oddPseudo = 1242,
1260  ARM_VLD4q8oddPseudo_UPD = 1243,
1261  ARM_VLD4qAsm_16 = 1244,
1262  ARM_VLD4qAsm_32 = 1245,
1263  ARM_VLD4qAsm_8 = 1246,
1264  ARM_VLD4qWB_fixed_Asm_16 = 1247,
1265  ARM_VLD4qWB_fixed_Asm_32 = 1248,
1266  ARM_VLD4qWB_fixed_Asm_8 = 1249,
1267  ARM_VLD4qWB_register_Asm_16 = 1250,
1268  ARM_VLD4qWB_register_Asm_32 = 1251,
1269  ARM_VLD4qWB_register_Asm_8 = 1252,
1270  ARM_VLDMDDB_UPD = 1253,
1271  ARM_VLDMDIA = 1254,
1272  ARM_VLDMDIA_UPD = 1255,
1273  ARM_VLDMQIA = 1256,
1274  ARM_VLDMSDB_UPD = 1257,
1275  ARM_VLDMSIA = 1258,
1276  ARM_VLDMSIA_UPD = 1259,
1277  ARM_VLDRD = 1260,
1278  ARM_VLDRS = 1261,
1279  ARM_VMAXNMD = 1262,
1280  ARM_VMAXNMND = 1263,
1281  ARM_VMAXNMNQ = 1264,
1282  ARM_VMAXNMS = 1265,
1283  ARM_VMAXfd = 1266,
1284  ARM_VMAXfq = 1267,
1285  ARM_VMAXsv16i8 = 1268,
1286  ARM_VMAXsv2i32 = 1269,
1287  ARM_VMAXsv4i16 = 1270,
1288  ARM_VMAXsv4i32 = 1271,
1289  ARM_VMAXsv8i16 = 1272,
1290  ARM_VMAXsv8i8 = 1273,
1291  ARM_VMAXuv16i8 = 1274,
1292  ARM_VMAXuv2i32 = 1275,
1293  ARM_VMAXuv4i16 = 1276,
1294  ARM_VMAXuv4i32 = 1277,
1295  ARM_VMAXuv8i16 = 1278,
1296  ARM_VMAXuv8i8 = 1279,
1297  ARM_VMINNMD = 1280,
1298  ARM_VMINNMND = 1281,
1299  ARM_VMINNMNQ = 1282,
1300  ARM_VMINNMS = 1283,
1301  ARM_VMINfd = 1284,
1302  ARM_VMINfq = 1285,
1303  ARM_VMINsv16i8 = 1286,
1304  ARM_VMINsv2i32 = 1287,
1305  ARM_VMINsv4i16 = 1288,
1306  ARM_VMINsv4i32 = 1289,
1307  ARM_VMINsv8i16 = 1290,
1308  ARM_VMINsv8i8 = 1291,
1309  ARM_VMINuv16i8 = 1292,
1310  ARM_VMINuv2i32 = 1293,
1311  ARM_VMINuv4i16 = 1294,
1312  ARM_VMINuv4i32 = 1295,
1313  ARM_VMINuv8i16 = 1296,
1314  ARM_VMINuv8i8 = 1297,
1315  ARM_VMLAD = 1298,
1316  ARM_VMLALslsv2i32 = 1299,
1317  ARM_VMLALslsv4i16 = 1300,
1318  ARM_VMLALsluv2i32 = 1301,
1319  ARM_VMLALsluv4i16 = 1302,
1320  ARM_VMLALsv2i64 = 1303,
1321  ARM_VMLALsv4i32 = 1304,
1322  ARM_VMLALsv8i16 = 1305,
1323  ARM_VMLALuv2i64 = 1306,
1324  ARM_VMLALuv4i32 = 1307,
1325  ARM_VMLALuv8i16 = 1308,
1326  ARM_VMLAS = 1309,
1327  ARM_VMLAfd = 1310,
1328  ARM_VMLAfq = 1311,
1329  ARM_VMLAslfd = 1312,
1330  ARM_VMLAslfq = 1313,
1331  ARM_VMLAslv2i32 = 1314,
1332  ARM_VMLAslv4i16 = 1315,
1333  ARM_VMLAslv4i32 = 1316,
1334  ARM_VMLAslv8i16 = 1317,
1335  ARM_VMLAv16i8 = 1318,
1336  ARM_VMLAv2i32 = 1319,
1337  ARM_VMLAv4i16 = 1320,
1338  ARM_VMLAv4i32 = 1321,
1339  ARM_VMLAv8i16 = 1322,
1340  ARM_VMLAv8i8 = 1323,
1341  ARM_VMLSD = 1324,
1342  ARM_VMLSLslsv2i32 = 1325,
1343  ARM_VMLSLslsv4i16 = 1326,
1344  ARM_VMLSLsluv2i32 = 1327,
1345  ARM_VMLSLsluv4i16 = 1328,
1346  ARM_VMLSLsv2i64 = 1329,
1347  ARM_VMLSLsv4i32 = 1330,
1348  ARM_VMLSLsv8i16 = 1331,
1349  ARM_VMLSLuv2i64 = 1332,
1350  ARM_VMLSLuv4i32 = 1333,
1351  ARM_VMLSLuv8i16 = 1334,
1352  ARM_VMLSS = 1335,
1353  ARM_VMLSfd = 1336,
1354  ARM_VMLSfq = 1337,
1355  ARM_VMLSslfd = 1338,
1356  ARM_VMLSslfq = 1339,
1357  ARM_VMLSslv2i32 = 1340,
1358  ARM_VMLSslv4i16 = 1341,
1359  ARM_VMLSslv4i32 = 1342,
1360  ARM_VMLSslv8i16 = 1343,
1361  ARM_VMLSv16i8 = 1344,
1362  ARM_VMLSv2i32 = 1345,
1363  ARM_VMLSv4i16 = 1346,
1364  ARM_VMLSv4i32 = 1347,
1365  ARM_VMLSv8i16 = 1348,
1366  ARM_VMLSv8i8 = 1349,
1367  ARM_VMOVD = 1350,
1368  ARM_VMOVD0 = 1351,
1369  ARM_VMOVDRR = 1352,
1370  ARM_VMOVDcc = 1353,
1371  ARM_VMOVLsv2i64 = 1354,
1372  ARM_VMOVLsv4i32 = 1355,
1373  ARM_VMOVLsv8i16 = 1356,
1374  ARM_VMOVLuv2i64 = 1357,
1375  ARM_VMOVLuv4i32 = 1358,
1376  ARM_VMOVLuv8i16 = 1359,
1377  ARM_VMOVNv2i32 = 1360,
1378  ARM_VMOVNv4i16 = 1361,
1379  ARM_VMOVNv8i8 = 1362,
1380  ARM_VMOVQ0 = 1363,
1381  ARM_VMOVRRD = 1364,
1382  ARM_VMOVRRS = 1365,
1383  ARM_VMOVRS = 1366,
1384  ARM_VMOVS = 1367,
1385  ARM_VMOVSR = 1368,
1386  ARM_VMOVSRR = 1369,
1387  ARM_VMOVScc = 1370,
1388  ARM_VMOVv16i8 = 1371,
1389  ARM_VMOVv1i64 = 1372,
1390  ARM_VMOVv2f32 = 1373,
1391  ARM_VMOVv2i32 = 1374,
1392  ARM_VMOVv2i64 = 1375,
1393  ARM_VMOVv4f32 = 1376,
1394  ARM_VMOVv4i16 = 1377,
1395  ARM_VMOVv4i32 = 1378,
1396  ARM_VMOVv8i16 = 1379,
1397  ARM_VMOVv8i8 = 1380,
1398  ARM_VMRS = 1381,
1399  ARM_VMRS_FPEXC = 1382,
1400  ARM_VMRS_FPINST = 1383,
1401  ARM_VMRS_FPINST2 = 1384,
1402  ARM_VMRS_FPSID = 1385,
1403  ARM_VMRS_MVFR0 = 1386,
1404  ARM_VMRS_MVFR1 = 1387,
1405  ARM_VMRS_MVFR2 = 1388,
1406  ARM_VMSR = 1389,
1407  ARM_VMSR_FPEXC = 1390,
1408  ARM_VMSR_FPINST = 1391,
1409  ARM_VMSR_FPINST2 = 1392,
1410  ARM_VMSR_FPSID = 1393,
1411  ARM_VMULD = 1394,
1412  ARM_VMULLp64 = 1395,
1413  ARM_VMULLp8 = 1396,
1414  ARM_VMULLslsv2i32 = 1397,
1415  ARM_VMULLslsv4i16 = 1398,
1416  ARM_VMULLsluv2i32 = 1399,
1417  ARM_VMULLsluv4i16 = 1400,
1418  ARM_VMULLsv2i64 = 1401,
1419  ARM_VMULLsv4i32 = 1402,
1420  ARM_VMULLsv8i16 = 1403,
1421  ARM_VMULLuv2i64 = 1404,
1422  ARM_VMULLuv4i32 = 1405,
1423  ARM_VMULLuv8i16 = 1406,
1424  ARM_VMULS = 1407,
1425  ARM_VMULfd = 1408,
1426  ARM_VMULfq = 1409,
1427  ARM_VMULpd = 1410,
1428  ARM_VMULpq = 1411,
1429  ARM_VMULslfd = 1412,
1430  ARM_VMULslfq = 1413,
1431  ARM_VMULslv2i32 = 1414,
1432  ARM_VMULslv4i16 = 1415,
1433  ARM_VMULslv4i32 = 1416,
1434  ARM_VMULslv8i16 = 1417,
1435  ARM_VMULv16i8 = 1418,
1436  ARM_VMULv2i32 = 1419,
1437  ARM_VMULv4i16 = 1420,
1438  ARM_VMULv4i32 = 1421,
1439  ARM_VMULv8i16 = 1422,
1440  ARM_VMULv8i8 = 1423,
1441  ARM_VMVNd = 1424,
1442  ARM_VMVNq = 1425,
1443  ARM_VMVNv2i32 = 1426,
1444  ARM_VMVNv4i16 = 1427,
1445  ARM_VMVNv4i32 = 1428,
1446  ARM_VMVNv8i16 = 1429,
1447  ARM_VNEGD = 1430,
1448  ARM_VNEGS = 1431,
1449  ARM_VNEGf32q = 1432,
1450  ARM_VNEGfd = 1433,
1451  ARM_VNEGs16d = 1434,
1452  ARM_VNEGs16q = 1435,
1453  ARM_VNEGs32d = 1436,
1454  ARM_VNEGs32q = 1437,
1455  ARM_VNEGs8d = 1438,
1456  ARM_VNEGs8q = 1439,
1457  ARM_VNMLAD = 1440,
1458  ARM_VNMLAS = 1441,
1459  ARM_VNMLSD = 1442,
1460  ARM_VNMLSS = 1443,
1461  ARM_VNMULD = 1444,
1462  ARM_VNMULS = 1445,
1463  ARM_VORNd = 1446,
1464  ARM_VORNq = 1447,
1465  ARM_VORRd = 1448,
1466  ARM_VORRiv2i32 = 1449,
1467  ARM_VORRiv4i16 = 1450,
1468  ARM_VORRiv4i32 = 1451,
1469  ARM_VORRiv8i16 = 1452,
1470  ARM_VORRq = 1453,
1471  ARM_VPADALsv16i8 = 1454,
1472  ARM_VPADALsv2i32 = 1455,
1473  ARM_VPADALsv4i16 = 1456,
1474  ARM_VPADALsv4i32 = 1457,
1475  ARM_VPADALsv8i16 = 1458,
1476  ARM_VPADALsv8i8 = 1459,
1477  ARM_VPADALuv16i8 = 1460,
1478  ARM_VPADALuv2i32 = 1461,
1479  ARM_VPADALuv4i16 = 1462,
1480  ARM_VPADALuv4i32 = 1463,
1481  ARM_VPADALuv8i16 = 1464,
1482  ARM_VPADALuv8i8 = 1465,
1483  ARM_VPADDLsv16i8 = 1466,
1484  ARM_VPADDLsv2i32 = 1467,
1485  ARM_VPADDLsv4i16 = 1468,
1486  ARM_VPADDLsv4i32 = 1469,
1487  ARM_VPADDLsv8i16 = 1470,
1488  ARM_VPADDLsv8i8 = 1471,
1489  ARM_VPADDLuv16i8 = 1472,
1490  ARM_VPADDLuv2i32 = 1473,
1491  ARM_VPADDLuv4i16 = 1474,
1492  ARM_VPADDLuv4i32 = 1475,
1493  ARM_VPADDLuv8i16 = 1476,
1494  ARM_VPADDLuv8i8 = 1477,
1495  ARM_VPADDf = 1478,
1496  ARM_VPADDi16 = 1479,
1497  ARM_VPADDi32 = 1480,
1498  ARM_VPADDi8 = 1481,
1499  ARM_VPMAXf = 1482,
1500  ARM_VPMAXs16 = 1483,
1501  ARM_VPMAXs32 = 1484,
1502  ARM_VPMAXs8 = 1485,
1503  ARM_VPMAXu16 = 1486,
1504  ARM_VPMAXu32 = 1487,
1505  ARM_VPMAXu8 = 1488,
1506  ARM_VPMINf = 1489,
1507  ARM_VPMINs16 = 1490,
1508  ARM_VPMINs32 = 1491,
1509  ARM_VPMINs8 = 1492,
1510  ARM_VPMINu16 = 1493,
1511  ARM_VPMINu32 = 1494,
1512  ARM_VPMINu8 = 1495,
1513  ARM_VQABSv16i8 = 1496,
1514  ARM_VQABSv2i32 = 1497,
1515  ARM_VQABSv4i16 = 1498,
1516  ARM_VQABSv4i32 = 1499,
1517  ARM_VQABSv8i16 = 1500,
1518  ARM_VQABSv8i8 = 1501,
1519  ARM_VQADDsv16i8 = 1502,
1520  ARM_VQADDsv1i64 = 1503,
1521  ARM_VQADDsv2i32 = 1504,
1522  ARM_VQADDsv2i64 = 1505,
1523  ARM_VQADDsv4i16 = 1506,
1524  ARM_VQADDsv4i32 = 1507,
1525  ARM_VQADDsv8i16 = 1508,
1526  ARM_VQADDsv8i8 = 1509,
1527  ARM_VQADDuv16i8 = 1510,
1528  ARM_VQADDuv1i64 = 1511,
1529  ARM_VQADDuv2i32 = 1512,
1530  ARM_VQADDuv2i64 = 1513,
1531  ARM_VQADDuv4i16 = 1514,
1532  ARM_VQADDuv4i32 = 1515,
1533  ARM_VQADDuv8i16 = 1516,
1534  ARM_VQADDuv8i8 = 1517,
1535  ARM_VQDMLALslv2i32 = 1518,
1536  ARM_VQDMLALslv4i16 = 1519,
1537  ARM_VQDMLALv2i64 = 1520,
1538  ARM_VQDMLALv4i32 = 1521,
1539  ARM_VQDMLSLslv2i32 = 1522,
1540  ARM_VQDMLSLslv4i16 = 1523,
1541  ARM_VQDMLSLv2i64 = 1524,
1542  ARM_VQDMLSLv4i32 = 1525,
1543  ARM_VQDMULHslv2i32 = 1526,
1544  ARM_VQDMULHslv4i16 = 1527,
1545  ARM_VQDMULHslv4i32 = 1528,
1546  ARM_VQDMULHslv8i16 = 1529,
1547  ARM_VQDMULHv2i32 = 1530,
1548  ARM_VQDMULHv4i16 = 1531,
1549  ARM_VQDMULHv4i32 = 1532,
1550  ARM_VQDMULHv8i16 = 1533,
1551  ARM_VQDMULLslv2i32 = 1534,
1552  ARM_VQDMULLslv4i16 = 1535,
1553  ARM_VQDMULLv2i64 = 1536,
1554  ARM_VQDMULLv4i32 = 1537,
1555  ARM_VQMOVNsuv2i32 = 1538,
1556  ARM_VQMOVNsuv4i16 = 1539,
1557  ARM_VQMOVNsuv8i8 = 1540,
1558  ARM_VQMOVNsv2i32 = 1541,
1559  ARM_VQMOVNsv4i16 = 1542,
1560  ARM_VQMOVNsv8i8 = 1543,
1561  ARM_VQMOVNuv2i32 = 1544,
1562  ARM_VQMOVNuv4i16 = 1545,
1563  ARM_VQMOVNuv8i8 = 1546,
1564  ARM_VQNEGv16i8 = 1547,
1565  ARM_VQNEGv2i32 = 1548,
1566  ARM_VQNEGv4i16 = 1549,
1567  ARM_VQNEGv4i32 = 1550,
1568  ARM_VQNEGv8i16 = 1551,
1569  ARM_VQNEGv8i8 = 1552,
1570  ARM_VQRDMULHslv2i32 = 1553,
1571  ARM_VQRDMULHslv4i16 = 1554,
1572  ARM_VQRDMULHslv4i32 = 1555,
1573  ARM_VQRDMULHslv8i16 = 1556,
1574  ARM_VQRDMULHv2i32 = 1557,
1575  ARM_VQRDMULHv4i16 = 1558,
1576  ARM_VQRDMULHv4i32 = 1559,
1577  ARM_VQRDMULHv8i16 = 1560,
1578  ARM_VQRSHLsv16i8 = 1561,
1579  ARM_VQRSHLsv1i64 = 1562,
1580  ARM_VQRSHLsv2i32 = 1563,
1581  ARM_VQRSHLsv2i64 = 1564,
1582  ARM_VQRSHLsv4i16 = 1565,
1583  ARM_VQRSHLsv4i32 = 1566,
1584  ARM_VQRSHLsv8i16 = 1567,
1585  ARM_VQRSHLsv8i8 = 1568,
1586  ARM_VQRSHLuv16i8 = 1569,
1587  ARM_VQRSHLuv1i64 = 1570,
1588  ARM_VQRSHLuv2i32 = 1571,
1589  ARM_VQRSHLuv2i64 = 1572,
1590  ARM_VQRSHLuv4i16 = 1573,
1591  ARM_VQRSHLuv4i32 = 1574,
1592  ARM_VQRSHLuv8i16 = 1575,
1593  ARM_VQRSHLuv8i8 = 1576,
1594  ARM_VQRSHRNsv2i32 = 1577,
1595  ARM_VQRSHRNsv4i16 = 1578,
1596  ARM_VQRSHRNsv8i8 = 1579,
1597  ARM_VQRSHRNuv2i32 = 1580,
1598  ARM_VQRSHRNuv4i16 = 1581,
1599  ARM_VQRSHRNuv8i8 = 1582,
1600  ARM_VQRSHRUNv2i32 = 1583,
1601  ARM_VQRSHRUNv4i16 = 1584,
1602  ARM_VQRSHRUNv8i8 = 1585,
1603  ARM_VQSHLsiv16i8 = 1586,
1604  ARM_VQSHLsiv1i64 = 1587,
1605  ARM_VQSHLsiv2i32 = 1588,
1606  ARM_VQSHLsiv2i64 = 1589,
1607  ARM_VQSHLsiv4i16 = 1590,
1608  ARM_VQSHLsiv4i32 = 1591,
1609  ARM_VQSHLsiv8i16 = 1592,
1610  ARM_VQSHLsiv8i8 = 1593,
1611  ARM_VQSHLsuv16i8 = 1594,
1612  ARM_VQSHLsuv1i64 = 1595,
1613  ARM_VQSHLsuv2i32 = 1596,
1614  ARM_VQSHLsuv2i64 = 1597,
1615  ARM_VQSHLsuv4i16 = 1598,
1616  ARM_VQSHLsuv4i32 = 1599,
1617  ARM_VQSHLsuv8i16 = 1600,
1618  ARM_VQSHLsuv8i8 = 1601,
1619  ARM_VQSHLsv16i8 = 1602,
1620  ARM_VQSHLsv1i64 = 1603,
1621  ARM_VQSHLsv2i32 = 1604,
1622  ARM_VQSHLsv2i64 = 1605,
1623  ARM_VQSHLsv4i16 = 1606,
1624  ARM_VQSHLsv4i32 = 1607,
1625  ARM_VQSHLsv8i16 = 1608,
1626  ARM_VQSHLsv8i8 = 1609,
1627  ARM_VQSHLuiv16i8 = 1610,
1628  ARM_VQSHLuiv1i64 = 1611,
1629  ARM_VQSHLuiv2i32 = 1612,
1630  ARM_VQSHLuiv2i64 = 1613,
1631  ARM_VQSHLuiv4i16 = 1614,
1632  ARM_VQSHLuiv4i32 = 1615,
1633  ARM_VQSHLuiv8i16 = 1616,
1634  ARM_VQSHLuiv8i8 = 1617,
1635  ARM_VQSHLuv16i8 = 1618,
1636  ARM_VQSHLuv1i64 = 1619,
1637  ARM_VQSHLuv2i32 = 1620,
1638  ARM_VQSHLuv2i64 = 1621,
1639  ARM_VQSHLuv4i16 = 1622,
1640  ARM_VQSHLuv4i32 = 1623,
1641  ARM_VQSHLuv8i16 = 1624,
1642  ARM_VQSHLuv8i8 = 1625,
1643  ARM_VQSHRNsv2i32 = 1626,
1644  ARM_VQSHRNsv4i16 = 1627,
1645  ARM_VQSHRNsv8i8 = 1628,
1646  ARM_VQSHRNuv2i32 = 1629,
1647  ARM_VQSHRNuv4i16 = 1630,
1648  ARM_VQSHRNuv8i8 = 1631,
1649  ARM_VQSHRUNv2i32 = 1632,
1650  ARM_VQSHRUNv4i16 = 1633,
1651  ARM_VQSHRUNv8i8 = 1634,
1652  ARM_VQSUBsv16i8 = 1635,
1653  ARM_VQSUBsv1i64 = 1636,
1654  ARM_VQSUBsv2i32 = 1637,
1655  ARM_VQSUBsv2i64 = 1638,
1656  ARM_VQSUBsv4i16 = 1639,
1657  ARM_VQSUBsv4i32 = 1640,
1658  ARM_VQSUBsv8i16 = 1641,
1659  ARM_VQSUBsv8i8 = 1642,
1660  ARM_VQSUBuv16i8 = 1643,
1661  ARM_VQSUBuv1i64 = 1644,
1662  ARM_VQSUBuv2i32 = 1645,
1663  ARM_VQSUBuv2i64 = 1646,
1664  ARM_VQSUBuv4i16 = 1647,
1665  ARM_VQSUBuv4i32 = 1648,
1666  ARM_VQSUBuv8i16 = 1649,
1667  ARM_VQSUBuv8i8 = 1650,
1668  ARM_VRADDHNv2i32 = 1651,
1669  ARM_VRADDHNv4i16 = 1652,
1670  ARM_VRADDHNv8i8 = 1653,
1671  ARM_VRECPEd = 1654,
1672  ARM_VRECPEfd = 1655,
1673  ARM_VRECPEfq = 1656,
1674  ARM_VRECPEq = 1657,
1675  ARM_VRECPSfd = 1658,
1676  ARM_VRECPSfq = 1659,
1677  ARM_VREV16d8 = 1660,
1678  ARM_VREV16q8 = 1661,
1679  ARM_VREV32d16 = 1662,
1680  ARM_VREV32d8 = 1663,
1681  ARM_VREV32q16 = 1664,
1682  ARM_VREV32q8 = 1665,
1683  ARM_VREV64d16 = 1666,
1684  ARM_VREV64d32 = 1667,
1685  ARM_VREV64d8 = 1668,
1686  ARM_VREV64q16 = 1669,
1687  ARM_VREV64q32 = 1670,
1688  ARM_VREV64q8 = 1671,
1689  ARM_VRHADDsv16i8 = 1672,
1690  ARM_VRHADDsv2i32 = 1673,
1691  ARM_VRHADDsv4i16 = 1674,
1692  ARM_VRHADDsv4i32 = 1675,
1693  ARM_VRHADDsv8i16 = 1676,
1694  ARM_VRHADDsv8i8 = 1677,
1695  ARM_VRHADDuv16i8 = 1678,
1696  ARM_VRHADDuv2i32 = 1679,
1697  ARM_VRHADDuv4i16 = 1680,
1698  ARM_VRHADDuv4i32 = 1681,
1699  ARM_VRHADDuv8i16 = 1682,
1700  ARM_VRHADDuv8i8 = 1683,
1701  ARM_VRINTAD = 1684,
1702  ARM_VRINTAND = 1685,
1703  ARM_VRINTANQ = 1686,
1704  ARM_VRINTAS = 1687,
1705  ARM_VRINTMD = 1688,
1706  ARM_VRINTMND = 1689,
1707  ARM_VRINTMNQ = 1690,
1708  ARM_VRINTMS = 1691,
1709  ARM_VRINTND = 1692,
1710  ARM_VRINTNND = 1693,
1711  ARM_VRINTNNQ = 1694,
1712  ARM_VRINTNS = 1695,
1713  ARM_VRINTPD = 1696,
1714  ARM_VRINTPND = 1697,
1715  ARM_VRINTPNQ = 1698,
1716  ARM_VRINTPS = 1699,
1717  ARM_VRINTRD = 1700,
1718  ARM_VRINTRS = 1701,
1719  ARM_VRINTXD = 1702,
1720  ARM_VRINTXND = 1703,
1721  ARM_VRINTXNQ = 1704,
1722  ARM_VRINTXS = 1705,
1723  ARM_VRINTZD = 1706,
1724  ARM_VRINTZND = 1707,
1725  ARM_VRINTZNQ = 1708,
1726  ARM_VRINTZS = 1709,
1727  ARM_VRSHLsv16i8 = 1710,
1728  ARM_VRSHLsv1i64 = 1711,
1729  ARM_VRSHLsv2i32 = 1712,
1730  ARM_VRSHLsv2i64 = 1713,
1731  ARM_VRSHLsv4i16 = 1714,
1732  ARM_VRSHLsv4i32 = 1715,
1733  ARM_VRSHLsv8i16 = 1716,
1734  ARM_VRSHLsv8i8 = 1717,
1735  ARM_VRSHLuv16i8 = 1718,
1736  ARM_VRSHLuv1i64 = 1719,
1737  ARM_VRSHLuv2i32 = 1720,
1738  ARM_VRSHLuv2i64 = 1721,
1739  ARM_VRSHLuv4i16 = 1722,
1740  ARM_VRSHLuv4i32 = 1723,
1741  ARM_VRSHLuv8i16 = 1724,
1742  ARM_VRSHLuv8i8 = 1725,
1743  ARM_VRSHRNv2i32 = 1726,
1744  ARM_VRSHRNv4i16 = 1727,
1745  ARM_VRSHRNv8i8 = 1728,
1746  ARM_VRSHRsv16i8 = 1729,
1747  ARM_VRSHRsv1i64 = 1730,
1748  ARM_VRSHRsv2i32 = 1731,
1749  ARM_VRSHRsv2i64 = 1732,
1750  ARM_VRSHRsv4i16 = 1733,
1751  ARM_VRSHRsv4i32 = 1734,
1752  ARM_VRSHRsv8i16 = 1735,
1753  ARM_VRSHRsv8i8 = 1736,
1754  ARM_VRSHRuv16i8 = 1737,
1755  ARM_VRSHRuv1i64 = 1738,
1756  ARM_VRSHRuv2i32 = 1739,
1757  ARM_VRSHRuv2i64 = 1740,
1758  ARM_VRSHRuv4i16 = 1741,
1759  ARM_VRSHRuv4i32 = 1742,
1760  ARM_VRSHRuv8i16 = 1743,
1761  ARM_VRSHRuv8i8 = 1744,
1762  ARM_VRSQRTEd = 1745,
1763  ARM_VRSQRTEfd = 1746,
1764  ARM_VRSQRTEfq = 1747,
1765  ARM_VRSQRTEq = 1748,
1766  ARM_VRSQRTSfd = 1749,
1767  ARM_VRSQRTSfq = 1750,
1768  ARM_VRSRAsv16i8 = 1751,
1769  ARM_VRSRAsv1i64 = 1752,
1770  ARM_VRSRAsv2i32 = 1753,
1771  ARM_VRSRAsv2i64 = 1754,
1772  ARM_VRSRAsv4i16 = 1755,
1773  ARM_VRSRAsv4i32 = 1756,
1774  ARM_VRSRAsv8i16 = 1757,
1775  ARM_VRSRAsv8i8 = 1758,
1776  ARM_VRSRAuv16i8 = 1759,
1777  ARM_VRSRAuv1i64 = 1760,
1778  ARM_VRSRAuv2i32 = 1761,
1779  ARM_VRSRAuv2i64 = 1762,
1780  ARM_VRSRAuv4i16 = 1763,
1781  ARM_VRSRAuv4i32 = 1764,
1782  ARM_VRSRAuv8i16 = 1765,
1783  ARM_VRSRAuv8i8 = 1766,
1784  ARM_VRSUBHNv2i32 = 1767,
1785  ARM_VRSUBHNv4i16 = 1768,
1786  ARM_VRSUBHNv8i8 = 1769,
1787  ARM_VSELEQD = 1770,
1788  ARM_VSELEQS = 1771,
1789  ARM_VSELGED = 1772,
1790  ARM_VSELGES = 1773,
1791  ARM_VSELGTD = 1774,
1792  ARM_VSELGTS = 1775,
1793  ARM_VSELVSD = 1776,
1794  ARM_VSELVSS = 1777,
1795  ARM_VSETLNi16 = 1778,
1796  ARM_VSETLNi32 = 1779,
1797  ARM_VSETLNi8 = 1780,
1798  ARM_VSHLLi16 = 1781,
1799  ARM_VSHLLi32 = 1782,
1800  ARM_VSHLLi8 = 1783,
1801  ARM_VSHLLsv2i64 = 1784,
1802  ARM_VSHLLsv4i32 = 1785,
1803  ARM_VSHLLsv8i16 = 1786,
1804  ARM_VSHLLuv2i64 = 1787,
1805  ARM_VSHLLuv4i32 = 1788,
1806  ARM_VSHLLuv8i16 = 1789,
1807  ARM_VSHLiv16i8 = 1790,
1808  ARM_VSHLiv1i64 = 1791,
1809  ARM_VSHLiv2i32 = 1792,
1810  ARM_VSHLiv2i64 = 1793,
1811  ARM_VSHLiv4i16 = 1794,
1812  ARM_VSHLiv4i32 = 1795,
1813  ARM_VSHLiv8i16 = 1796,
1814  ARM_VSHLiv8i8 = 1797,
1815  ARM_VSHLsv16i8 = 1798,
1816  ARM_VSHLsv1i64 = 1799,
1817  ARM_VSHLsv2i32 = 1800,
1818  ARM_VSHLsv2i64 = 1801,
1819  ARM_VSHLsv4i16 = 1802,
1820  ARM_VSHLsv4i32 = 1803,
1821  ARM_VSHLsv8i16 = 1804,
1822  ARM_VSHLsv8i8 = 1805,
1823  ARM_VSHLuv16i8 = 1806,
1824  ARM_VSHLuv1i64 = 1807,
1825  ARM_VSHLuv2i32 = 1808,
1826  ARM_VSHLuv2i64 = 1809,
1827  ARM_VSHLuv4i16 = 1810,
1828  ARM_VSHLuv4i32 = 1811,
1829  ARM_VSHLuv8i16 = 1812,
1830  ARM_VSHLuv8i8 = 1813,
1831  ARM_VSHRNv2i32 = 1814,
1832  ARM_VSHRNv4i16 = 1815,
1833  ARM_VSHRNv8i8 = 1816,
1834  ARM_VSHRsv16i8 = 1817,
1835  ARM_VSHRsv1i64 = 1818,
1836  ARM_VSHRsv2i32 = 1819,
1837  ARM_VSHRsv2i64 = 1820,
1838  ARM_VSHRsv4i16 = 1821,
1839  ARM_VSHRsv4i32 = 1822,
1840  ARM_VSHRsv8i16 = 1823,
1841  ARM_VSHRsv8i8 = 1824,
1842  ARM_VSHRuv16i8 = 1825,
1843  ARM_VSHRuv1i64 = 1826,
1844  ARM_VSHRuv2i32 = 1827,
1845  ARM_VSHRuv2i64 = 1828,
1846  ARM_VSHRuv4i16 = 1829,
1847  ARM_VSHRuv4i32 = 1830,
1848  ARM_VSHRuv8i16 = 1831,
1849  ARM_VSHRuv8i8 = 1832,
1850  ARM_VSHTOD = 1833,
1851  ARM_VSHTOS = 1834,
1852  ARM_VSITOD = 1835,
1853  ARM_VSITOS = 1836,
1854  ARM_VSLIv16i8 = 1837,
1855  ARM_VSLIv1i64 = 1838,
1856  ARM_VSLIv2i32 = 1839,
1857  ARM_VSLIv2i64 = 1840,
1858  ARM_VSLIv4i16 = 1841,
1859  ARM_VSLIv4i32 = 1842,
1860  ARM_VSLIv8i16 = 1843,
1861  ARM_VSLIv8i8 = 1844,
1862  ARM_VSLTOD = 1845,
1863  ARM_VSLTOS = 1846,
1864  ARM_VSQRTD = 1847,
1865  ARM_VSQRTS = 1848,
1866  ARM_VSRAsv16i8 = 1849,
1867  ARM_VSRAsv1i64 = 1850,
1868  ARM_VSRAsv2i32 = 1851,
1869  ARM_VSRAsv2i64 = 1852,
1870  ARM_VSRAsv4i16 = 1853,
1871  ARM_VSRAsv4i32 = 1854,
1872  ARM_VSRAsv8i16 = 1855,
1873  ARM_VSRAsv8i8 = 1856,
1874  ARM_VSRAuv16i8 = 1857,
1875  ARM_VSRAuv1i64 = 1858,
1876  ARM_VSRAuv2i32 = 1859,
1877  ARM_VSRAuv2i64 = 1860,
1878  ARM_VSRAuv4i16 = 1861,
1879  ARM_VSRAuv4i32 = 1862,
1880  ARM_VSRAuv8i16 = 1863,
1881  ARM_VSRAuv8i8 = 1864,
1882  ARM_VSRIv16i8 = 1865,
1883  ARM_VSRIv1i64 = 1866,
1884  ARM_VSRIv2i32 = 1867,
1885  ARM_VSRIv2i64 = 1868,
1886  ARM_VSRIv4i16 = 1869,
1887  ARM_VSRIv4i32 = 1870,
1888  ARM_VSRIv8i16 = 1871,
1889  ARM_VSRIv8i8 = 1872,
1890  ARM_VST1LNd16 = 1873,
1891  ARM_VST1LNd16_UPD = 1874,
1892  ARM_VST1LNd32 = 1875,
1893  ARM_VST1LNd32_UPD = 1876,
1894  ARM_VST1LNd8 = 1877,
1895  ARM_VST1LNd8_UPD = 1878,
1896  ARM_VST1LNdAsm_16 = 1879,
1897  ARM_VST1LNdAsm_32 = 1880,
1898  ARM_VST1LNdAsm_8 = 1881,
1899  ARM_VST1LNdWB_fixed_Asm_16 = 1882,
1900  ARM_VST1LNdWB_fixed_Asm_32 = 1883,
1901  ARM_VST1LNdWB_fixed_Asm_8 = 1884,
1902  ARM_VST1LNdWB_register_Asm_16 = 1885,
1903  ARM_VST1LNdWB_register_Asm_32 = 1886,
1904  ARM_VST1LNdWB_register_Asm_8 = 1887,
1905  ARM_VST1LNq16Pseudo = 1888,
1906  ARM_VST1LNq16Pseudo_UPD = 1889,
1907  ARM_VST1LNq32Pseudo = 1890,
1908  ARM_VST1LNq32Pseudo_UPD = 1891,
1909  ARM_VST1LNq8Pseudo = 1892,
1910  ARM_VST1LNq8Pseudo_UPD = 1893,
1911  ARM_VST1d16 = 1894,
1912  ARM_VST1d16Q = 1895,
1913  ARM_VST1d16Qwb_fixed = 1896,
1914  ARM_VST1d16Qwb_register = 1897,
1915  ARM_VST1d16T = 1898,
1916  ARM_VST1d16Twb_fixed = 1899,
1917  ARM_VST1d16Twb_register = 1900,
1918  ARM_VST1d16wb_fixed = 1901,
1919  ARM_VST1d16wb_register = 1902,
1920  ARM_VST1d32 = 1903,
1921  ARM_VST1d32Q = 1904,
1922  ARM_VST1d32Qwb_fixed = 1905,
1923  ARM_VST1d32Qwb_register = 1906,
1924  ARM_VST1d32T = 1907,
1925  ARM_VST1d32Twb_fixed = 1908,
1926  ARM_VST1d32Twb_register = 1909,
1927  ARM_VST1d32wb_fixed = 1910,
1928  ARM_VST1d32wb_register = 1911,
1929  ARM_VST1d64 = 1912,
1930  ARM_VST1d64Q = 1913,
1931  ARM_VST1d64QPseudo = 1914,
1932  ARM_VST1d64QPseudoWB_fixed = 1915,
1933  ARM_VST1d64QPseudoWB_register = 1916,
1934  ARM_VST1d64Qwb_fixed = 1917,
1935  ARM_VST1d64Qwb_register = 1918,
1936  ARM_VST1d64T = 1919,
1937  ARM_VST1d64TPseudo = 1920,
1938  ARM_VST1d64TPseudoWB_fixed = 1921,
1939  ARM_VST1d64TPseudoWB_register = 1922,
1940  ARM_VST1d64Twb_fixed = 1923,
1941  ARM_VST1d64Twb_register = 1924,
1942  ARM_VST1d64wb_fixed = 1925,
1943  ARM_VST1d64wb_register = 1926,
1944  ARM_VST1d8 = 1927,
1945  ARM_VST1d8Q = 1928,
1946  ARM_VST1d8Qwb_fixed = 1929,
1947  ARM_VST1d8Qwb_register = 1930,
1948  ARM_VST1d8T = 1931,
1949  ARM_VST1d8Twb_fixed = 1932,
1950  ARM_VST1d8Twb_register = 1933,
1951  ARM_VST1d8wb_fixed = 1934,
1952  ARM_VST1d8wb_register = 1935,
1953  ARM_VST1q16 = 1936,
1954  ARM_VST1q16wb_fixed = 1937,
1955  ARM_VST1q16wb_register = 1938,
1956  ARM_VST1q32 = 1939,
1957  ARM_VST1q32wb_fixed = 1940,
1958  ARM_VST1q32wb_register = 1941,
1959  ARM_VST1q64 = 1942,
1960  ARM_VST1q64wb_fixed = 1943,
1961  ARM_VST1q64wb_register = 1944,
1962  ARM_VST1q8 = 1945,
1963  ARM_VST1q8wb_fixed = 1946,
1964  ARM_VST1q8wb_register = 1947,
1965  ARM_VST2LNd16 = 1948,
1966  ARM_VST2LNd16Pseudo = 1949,
1967  ARM_VST2LNd16Pseudo_UPD = 1950,
1968  ARM_VST2LNd16_UPD = 1951,
1969  ARM_VST2LNd32 = 1952,
1970  ARM_VST2LNd32Pseudo = 1953,
1971  ARM_VST2LNd32Pseudo_UPD = 1954,
1972  ARM_VST2LNd32_UPD = 1955,
1973  ARM_VST2LNd8 = 1956,
1974  ARM_VST2LNd8Pseudo = 1957,
1975  ARM_VST2LNd8Pseudo_UPD = 1958,
1976  ARM_VST2LNd8_UPD = 1959,
1977  ARM_VST2LNdAsm_16 = 1960,
1978  ARM_VST2LNdAsm_32 = 1961,
1979  ARM_VST2LNdAsm_8 = 1962,
1980  ARM_VST2LNdWB_fixed_Asm_16 = 1963,
1981  ARM_VST2LNdWB_fixed_Asm_32 = 1964,
1982  ARM_VST2LNdWB_fixed_Asm_8 = 1965,
1983  ARM_VST2LNdWB_register_Asm_16 = 1966,
1984  ARM_VST2LNdWB_register_Asm_32 = 1967,
1985  ARM_VST2LNdWB_register_Asm_8 = 1968,
1986  ARM_VST2LNq16 = 1969,
1987  ARM_VST2LNq16Pseudo = 1970,
1988  ARM_VST2LNq16Pseudo_UPD = 1971,
1989  ARM_VST2LNq16_UPD = 1972,
1990  ARM_VST2LNq32 = 1973,
1991  ARM_VST2LNq32Pseudo = 1974,
1992  ARM_VST2LNq32Pseudo_UPD = 1975,
1993  ARM_VST2LNq32_UPD = 1976,
1994  ARM_VST2LNqAsm_16 = 1977,
1995  ARM_VST2LNqAsm_32 = 1978,
1996  ARM_VST2LNqWB_fixed_Asm_16 = 1979,
1997  ARM_VST2LNqWB_fixed_Asm_32 = 1980,
1998  ARM_VST2LNqWB_register_Asm_16 = 1981,
1999  ARM_VST2LNqWB_register_Asm_32 = 1982,
2000  ARM_VST2b16 = 1983,
2001  ARM_VST2b16wb_fixed = 1984,
2002  ARM_VST2b16wb_register = 1985,
2003  ARM_VST2b32 = 1986,
2004  ARM_VST2b32wb_fixed = 1987,
2005  ARM_VST2b32wb_register = 1988,
2006  ARM_VST2b8 = 1989,
2007  ARM_VST2b8wb_fixed = 1990,
2008  ARM_VST2b8wb_register = 1991,
2009  ARM_VST2d16 = 1992,
2010  ARM_VST2d16wb_fixed = 1993,
2011  ARM_VST2d16wb_register = 1994,
2012  ARM_VST2d32 = 1995,
2013  ARM_VST2d32wb_fixed = 1996,
2014  ARM_VST2d32wb_register = 1997,
2015  ARM_VST2d8 = 1998,
2016  ARM_VST2d8wb_fixed = 1999,
2017  ARM_VST2d8wb_register = 2000,
2018  ARM_VST2q16 = 2001,
2019  ARM_VST2q16Pseudo = 2002,
2020  ARM_VST2q16PseudoWB_fixed = 2003,
2021  ARM_VST2q16PseudoWB_register = 2004,
2022  ARM_VST2q16wb_fixed = 2005,
2023  ARM_VST2q16wb_register = 2006,
2024  ARM_VST2q32 = 2007,
2025  ARM_VST2q32Pseudo = 2008,
2026  ARM_VST2q32PseudoWB_fixed = 2009,
2027  ARM_VST2q32PseudoWB_register = 2010,
2028  ARM_VST2q32wb_fixed = 2011,
2029  ARM_VST2q32wb_register = 2012,
2030  ARM_VST2q8 = 2013,
2031  ARM_VST2q8Pseudo = 2014,
2032  ARM_VST2q8PseudoWB_fixed = 2015,
2033  ARM_VST2q8PseudoWB_register = 2016,
2034  ARM_VST2q8wb_fixed = 2017,
2035  ARM_VST2q8wb_register = 2018,
2036  ARM_VST3LNd16 = 2019,
2037  ARM_VST3LNd16Pseudo = 2020,
2038  ARM_VST3LNd16Pseudo_UPD = 2021,
2039  ARM_VST3LNd16_UPD = 2022,
2040  ARM_VST3LNd32 = 2023,
2041  ARM_VST3LNd32Pseudo = 2024,
2042  ARM_VST3LNd32Pseudo_UPD = 2025,
2043  ARM_VST3LNd32_UPD = 2026,
2044  ARM_VST3LNd8 = 2027,
2045  ARM_VST3LNd8Pseudo = 2028,
2046  ARM_VST3LNd8Pseudo_UPD = 2029,
2047  ARM_VST3LNd8_UPD = 2030,
2048  ARM_VST3LNdAsm_16 = 2031,
2049  ARM_VST3LNdAsm_32 = 2032,
2050  ARM_VST3LNdAsm_8 = 2033,
2051  ARM_VST3LNdWB_fixed_Asm_16 = 2034,
2052  ARM_VST3LNdWB_fixed_Asm_32 = 2035,
2053  ARM_VST3LNdWB_fixed_Asm_8 = 2036,
2054  ARM_VST3LNdWB_register_Asm_16 = 2037,
2055  ARM_VST3LNdWB_register_Asm_32 = 2038,
2056  ARM_VST3LNdWB_register_Asm_8 = 2039,
2057  ARM_VST3LNq16 = 2040,
2058  ARM_VST3LNq16Pseudo = 2041,
2059  ARM_VST3LNq16Pseudo_UPD = 2042,
2060  ARM_VST3LNq16_UPD = 2043,
2061  ARM_VST3LNq32 = 2044,
2062  ARM_VST3LNq32Pseudo = 2045,
2063  ARM_VST3LNq32Pseudo_UPD = 2046,
2064  ARM_VST3LNq32_UPD = 2047,
2065  ARM_VST3LNqAsm_16 = 2048,
2066  ARM_VST3LNqAsm_32 = 2049,
2067  ARM_VST3LNqWB_fixed_Asm_16 = 2050,
2068  ARM_VST3LNqWB_fixed_Asm_32 = 2051,
2069  ARM_VST3LNqWB_register_Asm_16 = 2052,
2070  ARM_VST3LNqWB_register_Asm_32 = 2053,
2071  ARM_VST3d16 = 2054,
2072  ARM_VST3d16Pseudo = 2055,
2073  ARM_VST3d16Pseudo_UPD = 2056,
2074  ARM_VST3d16_UPD = 2057,
2075  ARM_VST3d32 = 2058,
2076  ARM_VST3d32Pseudo = 2059,
2077  ARM_VST3d32Pseudo_UPD = 2060,
2078  ARM_VST3d32_UPD = 2061,
2079  ARM_VST3d8 = 2062,
2080  ARM_VST3d8Pseudo = 2063,
2081  ARM_VST3d8Pseudo_UPD = 2064,
2082  ARM_VST3d8_UPD = 2065,
2083  ARM_VST3dAsm_16 = 2066,
2084  ARM_VST3dAsm_32 = 2067,
2085  ARM_VST3dAsm_8 = 2068,
2086  ARM_VST3dWB_fixed_Asm_16 = 2069,
2087  ARM_VST3dWB_fixed_Asm_32 = 2070,
2088  ARM_VST3dWB_fixed_Asm_8 = 2071,
2089  ARM_VST3dWB_register_Asm_16 = 2072,
2090  ARM_VST3dWB_register_Asm_32 = 2073,
2091  ARM_VST3dWB_register_Asm_8 = 2074,
2092  ARM_VST3q16 = 2075,
2093  ARM_VST3q16Pseudo_UPD = 2076,
2094  ARM_VST3q16_UPD = 2077,
2095  ARM_VST3q16oddPseudo = 2078,
2096  ARM_VST3q16oddPseudo_UPD = 2079,
2097  ARM_VST3q32 = 2080,
2098  ARM_VST3q32Pseudo_UPD = 2081,
2099  ARM_VST3q32_UPD = 2082,
2100  ARM_VST3q32oddPseudo = 2083,
2101  ARM_VST3q32oddPseudo_UPD = 2084,
2102  ARM_VST3q8 = 2085,
2103  ARM_VST3q8Pseudo_UPD = 2086,
2104  ARM_VST3q8_UPD = 2087,
2105  ARM_VST3q8oddPseudo = 2088,
2106  ARM_VST3q8oddPseudo_UPD = 2089,
2107  ARM_VST3qAsm_16 = 2090,
2108  ARM_VST3qAsm_32 = 2091,
2109  ARM_VST3qAsm_8 = 2092,
2110  ARM_VST3qWB_fixed_Asm_16 = 2093,
2111  ARM_VST3qWB_fixed_Asm_32 = 2094,
2112  ARM_VST3qWB_fixed_Asm_8 = 2095,
2113  ARM_VST3qWB_register_Asm_16 = 2096,
2114  ARM_VST3qWB_register_Asm_32 = 2097,
2115  ARM_VST3qWB_register_Asm_8 = 2098,
2116  ARM_VST4LNd16 = 2099,
2117  ARM_VST4LNd16Pseudo = 2100,
2118  ARM_VST4LNd16Pseudo_UPD = 2101,
2119  ARM_VST4LNd16_UPD = 2102,
2120  ARM_VST4LNd32 = 2103,
2121  ARM_VST4LNd32Pseudo = 2104,
2122  ARM_VST4LNd32Pseudo_UPD = 2105,
2123  ARM_VST4LNd32_UPD = 2106,
2124  ARM_VST4LNd8 = 2107,
2125  ARM_VST4LNd8Pseudo = 2108,
2126  ARM_VST4LNd8Pseudo_UPD = 2109,
2127  ARM_VST4LNd8_UPD = 2110,
2128  ARM_VST4LNdAsm_16 = 2111,
2129  ARM_VST4LNdAsm_32 = 2112,
2130  ARM_VST4LNdAsm_8 = 2113,
2131  ARM_VST4LNdWB_fixed_Asm_16 = 2114,
2132  ARM_VST4LNdWB_fixed_Asm_32 = 2115,
2133  ARM_VST4LNdWB_fixed_Asm_8 = 2116,
2134  ARM_VST4LNdWB_register_Asm_16 = 2117,
2135  ARM_VST4LNdWB_register_Asm_32 = 2118,
2136  ARM_VST4LNdWB_register_Asm_8 = 2119,
2137  ARM_VST4LNq16 = 2120,
2138  ARM_VST4LNq16Pseudo = 2121,
2139  ARM_VST4LNq16Pseudo_UPD = 2122,
2140  ARM_VST4LNq16_UPD = 2123,
2141  ARM_VST4LNq32 = 2124,
2142  ARM_VST4LNq32Pseudo = 2125,
2143  ARM_VST4LNq32Pseudo_UPD = 2126,
2144  ARM_VST4LNq32_UPD = 2127,
2145  ARM_VST4LNqAsm_16 = 2128,
2146  ARM_VST4LNqAsm_32 = 2129,
2147  ARM_VST4LNqWB_fixed_Asm_16 = 2130,
2148  ARM_VST4LNqWB_fixed_Asm_32 = 2131,
2149  ARM_VST4LNqWB_register_Asm_16 = 2132,
2150  ARM_VST4LNqWB_register_Asm_32 = 2133,
2151  ARM_VST4d16 = 2134,
2152  ARM_VST4d16Pseudo = 2135,
2153  ARM_VST4d16Pseudo_UPD = 2136,
2154  ARM_VST4d16_UPD = 2137,
2155  ARM_VST4d32 = 2138,
2156  ARM_VST4d32Pseudo = 2139,
2157  ARM_VST4d32Pseudo_UPD = 2140,
2158  ARM_VST4d32_UPD = 2141,
2159  ARM_VST4d8 = 2142,
2160  ARM_VST4d8Pseudo = 2143,
2161  ARM_VST4d8Pseudo_UPD = 2144,
2162  ARM_VST4d8_UPD = 2145,
2163  ARM_VST4dAsm_16 = 2146,
2164  ARM_VST4dAsm_32 = 2147,
2165  ARM_VST4dAsm_8 = 2148,
2166  ARM_VST4dWB_fixed_Asm_16 = 2149,
2167  ARM_VST4dWB_fixed_Asm_32 = 2150,
2168  ARM_VST4dWB_fixed_Asm_8 = 2151,
2169  ARM_VST4dWB_register_Asm_16 = 2152,
2170  ARM_VST4dWB_register_Asm_32 = 2153,
2171  ARM_VST4dWB_register_Asm_8 = 2154,
2172  ARM_VST4q16 = 2155,
2173  ARM_VST4q16Pseudo_UPD = 2156,
2174  ARM_VST4q16_UPD = 2157,
2175  ARM_VST4q16oddPseudo = 2158,
2176  ARM_VST4q16oddPseudo_UPD = 2159,
2177  ARM_VST4q32 = 2160,
2178  ARM_VST4q32Pseudo_UPD = 2161,
2179  ARM_VST4q32_UPD = 2162,
2180  ARM_VST4q32oddPseudo = 2163,
2181  ARM_VST4q32oddPseudo_UPD = 2164,
2182  ARM_VST4q8 = 2165,
2183  ARM_VST4q8Pseudo_UPD = 2166,
2184  ARM_VST4q8_UPD = 2167,
2185  ARM_VST4q8oddPseudo = 2168,
2186  ARM_VST4q8oddPseudo_UPD = 2169,
2187  ARM_VST4qAsm_16 = 2170,
2188  ARM_VST4qAsm_32 = 2171,
2189  ARM_VST4qAsm_8 = 2172,
2190  ARM_VST4qWB_fixed_Asm_16 = 2173,
2191  ARM_VST4qWB_fixed_Asm_32 = 2174,
2192  ARM_VST4qWB_fixed_Asm_8 = 2175,
2193  ARM_VST4qWB_register_Asm_16 = 2176,
2194  ARM_VST4qWB_register_Asm_32 = 2177,
2195  ARM_VST4qWB_register_Asm_8 = 2178,
2196  ARM_VSTMDDB_UPD = 2179,
2197  ARM_VSTMDIA = 2180,
2198  ARM_VSTMDIA_UPD = 2181,
2199  ARM_VSTMQIA = 2182,
2200  ARM_VSTMSDB_UPD = 2183,
2201  ARM_VSTMSIA = 2184,
2202  ARM_VSTMSIA_UPD = 2185,
2203  ARM_VSTRD = 2186,
2204  ARM_VSTRS = 2187,
2205  ARM_VSUBD = 2188,
2206  ARM_VSUBHNv2i32 = 2189,
2207  ARM_VSUBHNv4i16 = 2190,
2208  ARM_VSUBHNv8i8 = 2191,
2209  ARM_VSUBLsv2i64 = 2192,
2210  ARM_VSUBLsv4i32 = 2193,
2211  ARM_VSUBLsv8i16 = 2194,
2212  ARM_VSUBLuv2i64 = 2195,
2213  ARM_VSUBLuv4i32 = 2196,
2214  ARM_VSUBLuv8i16 = 2197,
2215  ARM_VSUBS = 2198,
2216  ARM_VSUBWsv2i64 = 2199,
2217  ARM_VSUBWsv4i32 = 2200,
2218  ARM_VSUBWsv8i16 = 2201,
2219  ARM_VSUBWuv2i64 = 2202,
2220  ARM_VSUBWuv4i32 = 2203,
2221  ARM_VSUBWuv8i16 = 2204,
2222  ARM_VSUBfd = 2205,
2223  ARM_VSUBfq = 2206,
2224  ARM_VSUBv16i8 = 2207,
2225  ARM_VSUBv1i64 = 2208,
2226  ARM_VSUBv2i32 = 2209,
2227  ARM_VSUBv2i64 = 2210,
2228  ARM_VSUBv4i16 = 2211,
2229  ARM_VSUBv4i32 = 2212,
2230  ARM_VSUBv8i16 = 2213,
2231  ARM_VSUBv8i8 = 2214,
2232  ARM_VSWPd = 2215,
2233  ARM_VSWPq = 2216,
2234  ARM_VTBL1 = 2217,
2235  ARM_VTBL2 = 2218,
2236  ARM_VTBL3 = 2219,
2237  ARM_VTBL3Pseudo = 2220,
2238  ARM_VTBL4 = 2221,
2239  ARM_VTBL4Pseudo = 2222,
2240  ARM_VTBX1 = 2223,
2241  ARM_VTBX2 = 2224,
2242  ARM_VTBX3 = 2225,
2243  ARM_VTBX3Pseudo = 2226,
2244  ARM_VTBX4 = 2227,
2245  ARM_VTBX4Pseudo = 2228,
2246  ARM_VTOSHD = 2229,
2247  ARM_VTOSHS = 2230,
2248  ARM_VTOSIRD = 2231,
2249  ARM_VTOSIRS = 2232,
2250  ARM_VTOSIZD = 2233,
2251  ARM_VTOSIZS = 2234,
2252  ARM_VTOSLD = 2235,
2253  ARM_VTOSLS = 2236,
2254  ARM_VTOUHD = 2237,
2255  ARM_VTOUHS = 2238,
2256  ARM_VTOUIRD = 2239,
2257  ARM_VTOUIRS = 2240,
2258  ARM_VTOUIZD = 2241,
2259  ARM_VTOUIZS = 2242,
2260  ARM_VTOULD = 2243,
2261  ARM_VTOULS = 2244,
2262  ARM_VTRNd16 = 2245,
2263  ARM_VTRNd32 = 2246,
2264  ARM_VTRNd8 = 2247,
2265  ARM_VTRNq16 = 2248,
2266  ARM_VTRNq32 = 2249,
2267  ARM_VTRNq8 = 2250,
2268  ARM_VTSTv16i8 = 2251,
2269  ARM_VTSTv2i32 = 2252,
2270  ARM_VTSTv4i16 = 2253,
2271  ARM_VTSTv4i32 = 2254,
2272  ARM_VTSTv8i16 = 2255,
2273  ARM_VTSTv8i8 = 2256,
2274  ARM_VUHTOD = 2257,
2275  ARM_VUHTOS = 2258,
2276  ARM_VUITOD = 2259,
2277  ARM_VUITOS = 2260,
2278  ARM_VULTOD = 2261,
2279  ARM_VULTOS = 2262,
2280  ARM_VUZPd16 = 2263,
2281  ARM_VUZPd8 = 2264,
2282  ARM_VUZPq16 = 2265,
2283  ARM_VUZPq32 = 2266,
2284  ARM_VUZPq8 = 2267,
2285  ARM_VZIPd16 = 2268,
2286  ARM_VZIPd8 = 2269,
2287  ARM_VZIPq16 = 2270,
2288  ARM_VZIPq32 = 2271,
2289  ARM_VZIPq8 = 2272,
2290  ARM_WIN__CHKSTK = 2273,
2291  ARM_sysLDMDA = 2274,
2292  ARM_sysLDMDA_UPD = 2275,
2293  ARM_sysLDMDB = 2276,
2294  ARM_sysLDMDB_UPD = 2277,
2295  ARM_sysLDMIA = 2278,
2296  ARM_sysLDMIA_UPD = 2279,
2297  ARM_sysLDMIB = 2280,
2298  ARM_sysLDMIB_UPD = 2281,
2299  ARM_sysSTMDA = 2282,
2300  ARM_sysSTMDA_UPD = 2283,
2301  ARM_sysSTMDB = 2284,
2302  ARM_sysSTMDB_UPD = 2285,
2303  ARM_sysSTMIA = 2286,
2304  ARM_sysSTMIA_UPD = 2287,
2305  ARM_sysSTMIB = 2288,
2306  ARM_sysSTMIB_UPD = 2289,
2307  ARM_t2ABS = 2290,
2308  ARM_t2ADCri = 2291,
2309  ARM_t2ADCrr = 2292,
2310  ARM_t2ADCrs = 2293,
2311  ARM_t2ADDSri = 2294,
2312  ARM_t2ADDSrr = 2295,
2313  ARM_t2ADDSrs = 2296,
2314  ARM_t2ADDri = 2297,
2315  ARM_t2ADDri12 = 2298,
2316  ARM_t2ADDrr = 2299,
2317  ARM_t2ADDrs = 2300,
2318  ARM_t2ADR = 2301,
2319  ARM_t2ANDri = 2302,
2320  ARM_t2ANDrr = 2303,
2321  ARM_t2ANDrs = 2304,
2322  ARM_t2ASRri = 2305,
2323  ARM_t2ASRrr = 2306,
2324  ARM_t2B = 2307,
2325  ARM_t2BFC = 2308,
2326  ARM_t2BFI = 2309,
2327  ARM_t2BICri = 2310,
2328  ARM_t2BICrr = 2311,
2329  ARM_t2BICrs = 2312,
2330  ARM_t2BR_JT = 2313,
2331  ARM_t2BXJ = 2314,
2332  ARM_t2Bcc = 2315,
2333  ARM_t2CDP = 2316,
2334  ARM_t2CDP2 = 2317,
2335  ARM_t2CLREX = 2318,
2336  ARM_t2CLZ = 2319,
2337  ARM_t2CMNri = 2320,
2338  ARM_t2CMNzrr = 2321,
2339  ARM_t2CMNzrs = 2322,
2340  ARM_t2CMPri = 2323,
2341  ARM_t2CMPrr = 2324,
2342  ARM_t2CMPrs = 2325,
2343  ARM_t2CPS1p = 2326,
2344  ARM_t2CPS2p = 2327,
2345  ARM_t2CPS3p = 2328,
2346  ARM_t2CRC32B = 2329,
2347  ARM_t2CRC32CB = 2330,
2348  ARM_t2CRC32CH = 2331,
2349  ARM_t2CRC32CW = 2332,
2350  ARM_t2CRC32H = 2333,
2351  ARM_t2CRC32W = 2334,
2352  ARM_t2DBG = 2335,
2353  ARM_t2DCPS1 = 2336,
2354  ARM_t2DCPS2 = 2337,
2355  ARM_t2DCPS3 = 2338,
2356  ARM_t2DMB = 2339,
2357  ARM_t2DSB = 2340,
2358  ARM_t2EORri = 2341,
2359  ARM_t2EORrr = 2342,
2360  ARM_t2EORrs = 2343,
2361  ARM_t2HINT = 2344,
2362  ARM_t2HVC = 2345,
2363  ARM_t2ISB = 2346,
2364  ARM_t2IT = 2347,
2365  ARM_t2Int_eh_sjlj_setjmp = 2348,
2366  ARM_t2Int_eh_sjlj_setjmp_nofp = 2349,
2367  ARM_t2LDA = 2350,
2368  ARM_t2LDAB = 2351,
2369  ARM_t2LDAEX = 2352,
2370  ARM_t2LDAEXB = 2353,
2371  ARM_t2LDAEXD = 2354,
2372  ARM_t2LDAEXH = 2355,
2373  ARM_t2LDAH = 2356,
2374  ARM_t2LDC2L_OFFSET = 2357,
2375  ARM_t2LDC2L_OPTION = 2358,
2376  ARM_t2LDC2L_POST = 2359,
2377  ARM_t2LDC2L_PRE = 2360,
2378  ARM_t2LDC2_OFFSET = 2361,
2379  ARM_t2LDC2_OPTION = 2362,
2380  ARM_t2LDC2_POST = 2363,
2381  ARM_t2LDC2_PRE = 2364,
2382  ARM_t2LDCL_OFFSET = 2365,
2383  ARM_t2LDCL_OPTION = 2366,
2384  ARM_t2LDCL_POST = 2367,
2385  ARM_t2LDCL_PRE = 2368,
2386  ARM_t2LDC_OFFSET = 2369,
2387  ARM_t2LDC_OPTION = 2370,
2388  ARM_t2LDC_POST = 2371,
2389  ARM_t2LDC_PRE = 2372,
2390  ARM_t2LDMDB = 2373,
2391  ARM_t2LDMDB_UPD = 2374,
2392  ARM_t2LDMIA = 2375,
2393  ARM_t2LDMIA_RET = 2376,
2394  ARM_t2LDMIA_UPD = 2377,
2395  ARM_t2LDRBT = 2378,
2396  ARM_t2LDRB_POST = 2379,
2397  ARM_t2LDRB_PRE = 2380,
2398  ARM_t2LDRBi12 = 2381,
2399  ARM_t2LDRBi8 = 2382,
2400  ARM_t2LDRBpci = 2383,
2401  ARM_t2LDRBpcrel = 2384,
2402  ARM_t2LDRBs = 2385,
2403  ARM_t2LDRD_POST = 2386,
2404  ARM_t2LDRD_PRE = 2387,
2405  ARM_t2LDRDi8 = 2388,
2406  ARM_t2LDREX = 2389,
2407  ARM_t2LDREXB = 2390,
2408  ARM_t2LDREXD = 2391,
2409  ARM_t2LDREXH = 2392,
2410  ARM_t2LDRHT = 2393,
2411  ARM_t2LDRH_POST = 2394,
2412  ARM_t2LDRH_PRE = 2395,
2413  ARM_t2LDRHi12 = 2396,
2414  ARM_t2LDRHi8 = 2397,
2415  ARM_t2LDRHpci = 2398,
2416  ARM_t2LDRHpcrel = 2399,
2417  ARM_t2LDRHs = 2400,
2418  ARM_t2LDRSBT = 2401,
2419  ARM_t2LDRSB_POST = 2402,
2420  ARM_t2LDRSB_PRE = 2403,
2421  ARM_t2LDRSBi12 = 2404,
2422  ARM_t2LDRSBi8 = 2405,
2423  ARM_t2LDRSBpci = 2406,
2424  ARM_t2LDRSBpcrel = 2407,
2425  ARM_t2LDRSBs = 2408,
2426  ARM_t2LDRSHT = 2409,
2427  ARM_t2LDRSH_POST = 2410,
2428  ARM_t2LDRSH_PRE = 2411,
2429  ARM_t2LDRSHi12 = 2412,
2430  ARM_t2LDRSHi8 = 2413,
2431  ARM_t2LDRSHpci = 2414,
2432  ARM_t2LDRSHpcrel = 2415,
2433  ARM_t2LDRSHs = 2416,
2434  ARM_t2LDRT = 2417,
2435  ARM_t2LDR_POST = 2418,
2436  ARM_t2LDR_PRE = 2419,
2437  ARM_t2LDRi12 = 2420,
2438  ARM_t2LDRi8 = 2421,
2439  ARM_t2LDRpci = 2422,
2440  ARM_t2LDRpci_pic = 2423,
2441  ARM_t2LDRpcrel = 2424,
2442  ARM_t2LDRs = 2425,
2443  ARM_t2LEApcrel = 2426,
2444  ARM_t2LEApcrelJT = 2427,
2445  ARM_t2LSLri = 2428,
2446  ARM_t2LSLrr = 2429,
2447  ARM_t2LSRri = 2430,
2448  ARM_t2LSRrr = 2431,
2449  ARM_t2MCR = 2432,
2450  ARM_t2MCR2 = 2433,
2451  ARM_t2MCRR = 2434,
2452  ARM_t2MCRR2 = 2435,
2453  ARM_t2MLA = 2436,
2454  ARM_t2MLS = 2437,
2455  ARM_t2MOVCCasr = 2438,
2456  ARM_t2MOVCCi = 2439,
2457  ARM_t2MOVCCi16 = 2440,
2458  ARM_t2MOVCCi32imm = 2441,
2459  ARM_t2MOVCClsl = 2442,
2460  ARM_t2MOVCClsr = 2443,
2461  ARM_t2MOVCCr = 2444,
2462  ARM_t2MOVCCror = 2445,
2463  ARM_t2MOVSsi = 2446,
2464  ARM_t2MOVSsr = 2447,
2465  ARM_t2MOVTi16 = 2448,
2466  ARM_t2MOVTi16_ga_pcrel = 2449,
2467  ARM_t2MOV_ga_pcrel = 2450,
2468  ARM_t2MOVi = 2451,
2469  ARM_t2MOVi16 = 2452,
2470  ARM_t2MOVi16_ga_pcrel = 2453,
2471  ARM_t2MOVi32imm = 2454,
2472  ARM_t2MOVr = 2455,
2473  ARM_t2MOVsi = 2456,
2474  ARM_t2MOVsr = 2457,
2475  ARM_t2MOVsra_flag = 2458,
2476  ARM_t2MOVsrl_flag = 2459,
2477  ARM_t2MRC = 2460,
2478  ARM_t2MRC2 = 2461,
2479  ARM_t2MRRC = 2462,
2480  ARM_t2MRRC2 = 2463,
2481  ARM_t2MRS_AR = 2464,
2482  ARM_t2MRS_M = 2465,
2483  ARM_t2MRSbanked = 2466,
2484  ARM_t2MRSsys_AR = 2467,
2485  ARM_t2MSR_AR = 2468,
2486  ARM_t2MSR_M = 2469,
2487  ARM_t2MSRbanked = 2470,
2488  ARM_t2MUL = 2471,
2489  ARM_t2MVNCCi = 2472,
2490  ARM_t2MVNi = 2473,
2491  ARM_t2MVNr = 2474,
2492  ARM_t2MVNs = 2475,
2493  ARM_t2ORNri = 2476,
2494  ARM_t2ORNrr = 2477,
2495  ARM_t2ORNrs = 2478,
2496  ARM_t2ORRri = 2479,
2497  ARM_t2ORRrr = 2480,
2498  ARM_t2ORRrs = 2481,
2499  ARM_t2PKHBT = 2482,
2500  ARM_t2PKHTB = 2483,
2501  ARM_t2PLDWi12 = 2484,
2502  ARM_t2PLDWi8 = 2485,
2503  ARM_t2PLDWs = 2486,
2504  ARM_t2PLDi12 = 2487,
2505  ARM_t2PLDi8 = 2488,
2506  ARM_t2PLDpci = 2489,
2507  ARM_t2PLDs = 2490,
2508  ARM_t2PLIi12 = 2491,
2509  ARM_t2PLIi8 = 2492,
2510  ARM_t2PLIpci = 2493,
2511  ARM_t2PLIs = 2494,
2512  ARM_t2QADD = 2495,
2513  ARM_t2QADD16 = 2496,
2514  ARM_t2QADD8 = 2497,
2515  ARM_t2QASX = 2498,
2516  ARM_t2QDADD = 2499,
2517  ARM_t2QDSUB = 2500,
2518  ARM_t2QSAX = 2501,
2519  ARM_t2QSUB = 2502,
2520  ARM_t2QSUB16 = 2503,
2521  ARM_t2QSUB8 = 2504,
2522  ARM_t2RBIT = 2505,
2523  ARM_t2REV = 2506,
2524  ARM_t2REV16 = 2507,
2525  ARM_t2REVSH = 2508,
2526  ARM_t2RFEDB = 2509,
2527  ARM_t2RFEDBW = 2510,
2528  ARM_t2RFEIA = 2511,
2529  ARM_t2RFEIAW = 2512,
2530  ARM_t2RORri = 2513,
2531  ARM_t2RORrr = 2514,
2532  ARM_t2RRX = 2515,
2533  ARM_t2RSBSri = 2516,
2534  ARM_t2RSBSrs = 2517,
2535  ARM_t2RSBri = 2518,
2536  ARM_t2RSBrr = 2519,
2537  ARM_t2RSBrs = 2520,
2538  ARM_t2SADD16 = 2521,
2539  ARM_t2SADD8 = 2522,
2540  ARM_t2SASX = 2523,
2541  ARM_t2SBCri = 2524,
2542  ARM_t2SBCrr = 2525,
2543  ARM_t2SBCrs = 2526,
2544  ARM_t2SBFX = 2527,
2545  ARM_t2SDIV = 2528,
2546  ARM_t2SEL = 2529,
2547  ARM_t2SHADD16 = 2530,
2548  ARM_t2SHADD8 = 2531,
2549  ARM_t2SHASX = 2532,
2550  ARM_t2SHSAX = 2533,
2551  ARM_t2SHSUB16 = 2534,
2552  ARM_t2SHSUB8 = 2535,
2553  ARM_t2SMC = 2536,
2554  ARM_t2SMLABB = 2537,
2555  ARM_t2SMLABT = 2538,
2556  ARM_t2SMLAD = 2539,
2557  ARM_t2SMLADX = 2540,
2558  ARM_t2SMLAL = 2541,
2559  ARM_t2SMLALBB = 2542,
2560  ARM_t2SMLALBT = 2543,
2561  ARM_t2SMLALD = 2544,
2562  ARM_t2SMLALDX = 2545,
2563  ARM_t2SMLALTB = 2546,
2564  ARM_t2SMLALTT = 2547,
2565  ARM_t2SMLATB = 2548,
2566  ARM_t2SMLATT = 2549,
2567  ARM_t2SMLAWB = 2550,
2568  ARM_t2SMLAWT = 2551,
2569  ARM_t2SMLSD = 2552,
2570  ARM_t2SMLSDX = 2553,
2571  ARM_t2SMLSLD = 2554,
2572  ARM_t2SMLSLDX = 2555,
2573  ARM_t2SMMLA = 2556,
2574  ARM_t2SMMLAR = 2557,
2575  ARM_t2SMMLS = 2558,
2576  ARM_t2SMMLSR = 2559,
2577  ARM_t2SMMUL = 2560,
2578  ARM_t2SMMULR = 2561,
2579  ARM_t2SMUAD = 2562,
2580  ARM_t2SMUADX = 2563,
2581  ARM_t2SMULBB = 2564,
2582  ARM_t2SMULBT = 2565,
2583  ARM_t2SMULL = 2566,
2584  ARM_t2SMULTB = 2567,
2585  ARM_t2SMULTT = 2568,
2586  ARM_t2SMULWB = 2569,
2587  ARM_t2SMULWT = 2570,
2588  ARM_t2SMUSD = 2571,
2589  ARM_t2SMUSDX = 2572,
2590  ARM_t2SRSDB = 2573,
2591  ARM_t2SRSDB_UPD = 2574,
2592  ARM_t2SRSIA = 2575,
2593  ARM_t2SRSIA_UPD = 2576,
2594  ARM_t2SSAT = 2577,
2595  ARM_t2SSAT16 = 2578,
2596  ARM_t2SSAX = 2579,
2597  ARM_t2SSUB16 = 2580,
2598  ARM_t2SSUB8 = 2581,
2599  ARM_t2STC2L_OFFSET = 2582,
2600  ARM_t2STC2L_OPTION = 2583,
2601  ARM_t2STC2L_POST = 2584,
2602  ARM_t2STC2L_PRE = 2585,
2603  ARM_t2STC2_OFFSET = 2586,
2604  ARM_t2STC2_OPTION = 2587,
2605  ARM_t2STC2_POST = 2588,
2606  ARM_t2STC2_PRE = 2589,
2607  ARM_t2STCL_OFFSET = 2590,
2608  ARM_t2STCL_OPTION = 2591,
2609  ARM_t2STCL_POST = 2592,
2610  ARM_t2STCL_PRE = 2593,
2611  ARM_t2STC_OFFSET = 2594,
2612  ARM_t2STC_OPTION = 2595,
2613  ARM_t2STC_POST = 2596,
2614  ARM_t2STC_PRE = 2597,
2615  ARM_t2STL = 2598,
2616  ARM_t2STLB = 2599,
2617  ARM_t2STLEX = 2600,
2618  ARM_t2STLEXB = 2601,
2619  ARM_t2STLEXD = 2602,
2620  ARM_t2STLEXH = 2603,
2621  ARM_t2STLH = 2604,
2622  ARM_t2STMDB = 2605,
2623  ARM_t2STMDB_UPD = 2606,
2624  ARM_t2STMIA = 2607,
2625  ARM_t2STMIA_UPD = 2608,
2626  ARM_t2STRBT = 2609,
2627  ARM_t2STRB_POST = 2610,
2628  ARM_t2STRB_PRE = 2611,
2629  ARM_t2STRB_preidx = 2612,
2630  ARM_t2STRBi12 = 2613,
2631  ARM_t2STRBi8 = 2614,
2632  ARM_t2STRBs = 2615,
2633  ARM_t2STRD_POST = 2616,
2634  ARM_t2STRD_PRE = 2617,
2635  ARM_t2STRDi8 = 2618,
2636  ARM_t2STREX = 2619,
2637  ARM_t2STREXB = 2620,
2638  ARM_t2STREXD = 2621,
2639  ARM_t2STREXH = 2622,
2640  ARM_t2STRHT = 2623,
2641  ARM_t2STRH_POST = 2624,
2642  ARM_t2STRH_PRE = 2625,
2643  ARM_t2STRH_preidx = 2626,
2644  ARM_t2STRHi12 = 2627,
2645  ARM_t2STRHi8 = 2628,
2646  ARM_t2STRHs = 2629,
2647  ARM_t2STRT = 2630,
2648  ARM_t2STR_POST = 2631,
2649  ARM_t2STR_PRE = 2632,
2650  ARM_t2STR_preidx = 2633,
2651  ARM_t2STRi12 = 2634,
2652  ARM_t2STRi8 = 2635,
2653  ARM_t2STRs = 2636,
2654  ARM_t2SUBS_PC_LR = 2637,
2655  ARM_t2SUBSri = 2638,
2656  ARM_t2SUBSrr = 2639,
2657  ARM_t2SUBSrs = 2640,
2658  ARM_t2SUBri = 2641,
2659  ARM_t2SUBri12 = 2642,
2660  ARM_t2SUBrr = 2643,
2661  ARM_t2SUBrs = 2644,
2662  ARM_t2SXTAB = 2645,
2663  ARM_t2SXTAB16 = 2646,
2664  ARM_t2SXTAH = 2647,
2665  ARM_t2SXTB = 2648,
2666  ARM_t2SXTB16 = 2649,
2667  ARM_t2SXTH = 2650,
2668  ARM_t2TBB = 2651,
2669  ARM_t2TBB_JT = 2652,
2670  ARM_t2TBH = 2653,
2671  ARM_t2TBH_JT = 2654,
2672  ARM_t2TEQri = 2655,
2673  ARM_t2TEQrr = 2656,
2674  ARM_t2TEQrs = 2657,
2675  ARM_t2TSTri = 2658,
2676  ARM_t2TSTrr = 2659,
2677  ARM_t2TSTrs = 2660,
2678  ARM_t2UADD16 = 2661,
2679  ARM_t2UADD8 = 2662,
2680  ARM_t2UASX = 2663,
2681  ARM_t2UBFX = 2664,
2682  ARM_t2UDF = 2665,
2683  ARM_t2UDIV = 2666,
2684  ARM_t2UHADD16 = 2667,
2685  ARM_t2UHADD8 = 2668,
2686  ARM_t2UHASX = 2669,
2687  ARM_t2UHSAX = 2670,
2688  ARM_t2UHSUB16 = 2671,
2689  ARM_t2UHSUB8 = 2672,
2690  ARM_t2UMAAL = 2673,
2691  ARM_t2UMLAL = 2674,
2692  ARM_t2UMULL = 2675,
2693  ARM_t2UQADD16 = 2676,
2694  ARM_t2UQADD8 = 2677,
2695  ARM_t2UQASX = 2678,
2696  ARM_t2UQSAX = 2679,
2697  ARM_t2UQSUB16 = 2680,
2698  ARM_t2UQSUB8 = 2681,
2699  ARM_t2USAD8 = 2682,
2700  ARM_t2USADA8 = 2683,
2701  ARM_t2USAT = 2684,
2702  ARM_t2USAT16 = 2685,
2703  ARM_t2USAX = 2686,
2704  ARM_t2USUB16 = 2687,
2705  ARM_t2USUB8 = 2688,
2706  ARM_t2UXTAB = 2689,
2707  ARM_t2UXTAB16 = 2690,
2708  ARM_t2UXTAH = 2691,
2709  ARM_t2UXTB = 2692,
2710  ARM_t2UXTB16 = 2693,
2711  ARM_t2UXTH = 2694,
2712  ARM_tADC = 2695,
2713  ARM_tADDframe = 2696,
2714  ARM_tADDhirr = 2697,
2715  ARM_tADDi3 = 2698,
2716  ARM_tADDi8 = 2699,
2717  ARM_tADDrSP = 2700,
2718  ARM_tADDrSPi = 2701,
2719  ARM_tADDrr = 2702,
2720  ARM_tADDspi = 2703,
2721  ARM_tADDspr = 2704,
2722  ARM_tADJCALLSTACKDOWN = 2705,
2723  ARM_tADJCALLSTACKUP = 2706,
2724  ARM_tADR = 2707,
2725  ARM_tAND = 2708,
2726  ARM_tASRri = 2709,
2727  ARM_tASRrr = 2710,
2728  ARM_tB = 2711,
2729  ARM_tBIC = 2712,
2730  ARM_tBKPT = 2713,
2731  ARM_tBL = 2714,
2732  ARM_tBLXi = 2715,
2733  ARM_tBLXr = 2716,
2734  ARM_tBRIND = 2717,
2735  ARM_tBR_JTr = 2718,
2736  ARM_tBX = 2719,
2737  ARM_tBX_CALL = 2720,
2738  ARM_tBX_RET = 2721,
2739  ARM_tBX_RET_vararg = 2722,
2740  ARM_tBcc = 2723,
2741  ARM_tBfar = 2724,
2742  ARM_tCBNZ = 2725,
2743  ARM_tCBZ = 2726,
2744  ARM_tCMNz = 2727,
2745  ARM_tCMPhir = 2728,
2746  ARM_tCMPi8 = 2729,
2747  ARM_tCMPr = 2730,
2748  ARM_tCPS = 2731,
2749  ARM_tEOR = 2732,
2750  ARM_tHINT = 2733,
2751  ARM_tHLT = 2734,
2752  ARM_tInt_eh_sjlj_longjmp = 2735,
2753  ARM_tInt_eh_sjlj_setjmp = 2736,
2754  ARM_tLDMIA = 2737,
2755  ARM_tLDMIA_UPD = 2738,
2756  ARM_tLDRBi = 2739,
2757  ARM_tLDRBr = 2740,
2758  ARM_tLDRHi = 2741,
2759  ARM_tLDRHr = 2742,
2760  ARM_tLDRLIT_ga_abs = 2743,
2761  ARM_tLDRLIT_ga_pcrel = 2744,
2762  ARM_tLDRSB = 2745,
2763  ARM_tLDRSH = 2746,
2764  ARM_tLDRi = 2747,
2765  ARM_tLDRpci = 2748,
2766  ARM_tLDRpci_pic = 2749,
2767  ARM_tLDRr = 2750,
2768  ARM_tLDRspi = 2751,
2769  ARM_tLEApcrel = 2752,
2770  ARM_tLEApcrelJT = 2753,
2771  ARM_tLSLri = 2754,
2772  ARM_tLSLrr = 2755,
2773  ARM_tLSRri = 2756,
2774  ARM_tLSRrr = 2757,
2775  ARM_tMOVCCr_pseudo = 2758,
2776  ARM_tMOVSr = 2759,
2777  ARM_tMOVi8 = 2760,
2778  ARM_tMOVr = 2761,
2779  ARM_tMUL = 2762,
2780  ARM_tMVN = 2763,
2781  ARM_tORR = 2764,
2782  ARM_tPICADD = 2765,
2783  ARM_tPOP = 2766,
2784  ARM_tPOP_RET = 2767,
2785  ARM_tPUSH = 2768,
2786  ARM_tREV = 2769,
2787  ARM_tREV16 = 2770,
2788  ARM_tREVSH = 2771,
2789  ARM_tROR = 2772,
2790  ARM_tRSB = 2773,
2791  ARM_tSBC = 2774,
2792  ARM_tSETEND = 2775,
2793  ARM_tSTMIA_UPD = 2776,
2794  ARM_tSTRBi = 2777,
2795  ARM_tSTRBr = 2778,
2796  ARM_tSTRHi = 2779,
2797  ARM_tSTRHr = 2780,
2798  ARM_tSTRi = 2781,
2799  ARM_tSTRr = 2782,
2800  ARM_tSTRspi = 2783,
2801  ARM_tSUBi3 = 2784,
2802  ARM_tSUBi8 = 2785,
2803  ARM_tSUBrr = 2786,
2804  ARM_tSUBspi = 2787,
2805  ARM_tSVC = 2788,
2806  ARM_tSXTB = 2789,
2807  ARM_tSXTH = 2790,
2808  ARM_tTAILJMPd = 2791,
2809  ARM_tTAILJMPdND = 2792,
2810  ARM_tTAILJMPr = 2793,
2811  ARM_tTPsoft = 2794,
2812  ARM_tTRAP = 2795,
2813  ARM_tTST = 2796,
2814  ARM_tUDF = 2797,
2815  ARM_tUXTB = 2798,
2816  ARM_tUXTH = 2799,
2817  ARM_INSTRUCTION_LIST_END = 2800
2818 };
2819 
2820 #endif // GET_INSTRINFO_ENUM
2821 
2822 
2823 #ifdef GET_INSTRINFO_MC_DESC
2824 #undef GET_INSTRINFO_MC_DESC
2825 
2826 #define nullptr 0
2827 
2828 #define ImplicitList1 0
2829 #define ImplicitList2 0
2830 #define ImplicitList3 0
2831 #define ImplicitList4 0
2832 #define ImplicitList5 0
2833 #define ImplicitList6 0
2834 #define ImplicitList7 0
2835 #define ImplicitList8 0
2836 #define ImplicitList9 0
2837 #define ImplicitList10 0
2838 #define ImplicitList11 0
2839 #define ImplicitList12 0
2840 #define ImplicitList13 0
2841 #define ImplicitList14 0
2842 #define ImplicitList15 0
2843 
2844 
2845 static MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
2846 static MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
2847 static MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
2848 static MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
2849 static MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
2850 static MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
2851 static MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
2852 static MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
2853 static MCOperandInfo OperandInfo10[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, };
2854 static MCOperandInfo OperandInfo11[] = { { 0, 0|(1<<MCOI_LookupPtrRegClass), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
2855 static MCOperandInfo OperandInfo12[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
2856 static MCOperandInfo OperandInfo13[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
2857 static MCOperandInfo OperandInfo14[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
2858 static MCOperandInfo OperandInfo15[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
2859 static MCOperandInfo OperandInfo16[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
2860 static MCOperandInfo OperandInfo17[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2861 static MCOperandInfo OperandInfo18[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2862 static MCOperandInfo OperandInfo19[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2863 static MCOperandInfo OperandInfo20[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2864 static MCOperandInfo OperandInfo21[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
2865 static MCOperandInfo OperandInfo22[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2866 static MCOperandInfo OperandInfo23[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2867 static MCOperandInfo OperandInfo24[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2868 static MCOperandInfo OperandInfo25[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
2869 static MCOperandInfo OperandInfo26[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
2870 static MCOperandInfo OperandInfo27[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
2871 static MCOperandInfo OperandInfo28[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
2872 static MCOperandInfo OperandInfo29[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
2873 static MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
2874 static MCOperandInfo OperandInfo31[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2875 static MCOperandInfo OperandInfo32[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2876 static MCOperandInfo OperandInfo33[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
2877 static MCOperandInfo OperandInfo34[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2878 static MCOperandInfo OperandInfo35[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2879 static MCOperandInfo OperandInfo36[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
2880 static MCOperandInfo OperandInfo37[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
2881 static MCOperandInfo OperandInfo38[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
2882 static MCOperandInfo OperandInfo39[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
2883 static MCOperandInfo OperandInfo40[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2884 static MCOperandInfo OperandInfo41[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2885 static MCOperandInfo OperandInfo42[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
2886 static MCOperandInfo OperandInfo43[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2887 static MCOperandInfo OperandInfo44[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2888 static MCOperandInfo OperandInfo45[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2889 static MCOperandInfo OperandInfo46[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
2890 static MCOperandInfo OperandInfo47[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
2891 static MCOperandInfo OperandInfo48[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2892 static MCOperandInfo OperandInfo49[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2893 static MCOperandInfo OperandInfo50[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2894 static MCOperandInfo OperandInfo51[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
2895 static MCOperandInfo OperandInfo52[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
2896 static MCOperandInfo OperandInfo53[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2897 static MCOperandInfo OperandInfo54[] = { { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2898 static MCOperandInfo OperandInfo55[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
2899 static MCOperandInfo OperandInfo56[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2900 static MCOperandInfo OperandInfo57[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2901 static MCOperandInfo OperandInfo58[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2902 static MCOperandInfo OperandInfo59[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2903 static MCOperandInfo OperandInfo60[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2904 static MCOperandInfo OperandInfo61[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2905 static MCOperandInfo OperandInfo62[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2906 static MCOperandInfo OperandInfo63[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2907 static MCOperandInfo OperandInfo64[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2908 static MCOperandInfo OperandInfo65[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2909 static MCOperandInfo OperandInfo66[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
2910 static MCOperandInfo OperandInfo67[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2911 static MCOperandInfo OperandInfo68[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2912 static MCOperandInfo OperandInfo69[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2913 static MCOperandInfo OperandInfo70[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2914 static MCOperandInfo OperandInfo71[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
2915 static MCOperandInfo OperandInfo72[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2916 static MCOperandInfo OperandInfo73[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
2917 static MCOperandInfo OperandInfo74[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
2918 static MCOperandInfo OperandInfo75[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
2919 static MCOperandInfo OperandInfo76[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2920 static MCOperandInfo OperandInfo77[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2921 static MCOperandInfo OperandInfo78[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2922 static MCOperandInfo OperandInfo79[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2923 static MCOperandInfo OperandInfo80[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2924 static MCOperandInfo OperandInfo81[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2925 static MCOperandInfo OperandInfo82[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
2926 static MCOperandInfo OperandInfo83[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
2927 static MCOperandInfo OperandInfo84[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
2928 static MCOperandInfo OperandInfo85[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
2929 static MCOperandInfo OperandInfo86[] = { { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
2930 static MCOperandInfo OperandInfo87[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
2931 static MCOperandInfo OperandInfo88[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
2932 static MCOperandInfo OperandInfo89[] = { { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2933 static MCOperandInfo OperandInfo90[] = { { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
2934 static MCOperandInfo OperandInfo91[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2935 static MCOperandInfo OperandInfo92[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2936 static MCOperandInfo OperandInfo93[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2937 static MCOperandInfo OperandInfo94[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2938 static MCOperandInfo OperandInfo95[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2939 static MCOperandInfo OperandInfo96[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
2940 static MCOperandInfo OperandInfo97[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
2941 static MCOperandInfo OperandInfo98[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2942 static MCOperandInfo OperandInfo99[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
2943 static MCOperandInfo OperandInfo100[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
2944 static MCOperandInfo OperandInfo101[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2945 static MCOperandInfo OperandInfo102[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2946 static MCOperandInfo OperandInfo103[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
2947 static MCOperandInfo OperandInfo104[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2948 static MCOperandInfo OperandInfo105[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
2949 static MCOperandInfo OperandInfo106[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2950 static MCOperandInfo OperandInfo107[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
2951 static MCOperandInfo OperandInfo108[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
2952 static MCOperandInfo OperandInfo109[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
2953 static MCOperandInfo OperandInfo110[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
2954 static MCOperandInfo OperandInfo111[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2955 static MCOperandInfo OperandInfo112[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2956 static MCOperandInfo OperandInfo113[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2957 static MCOperandInfo OperandInfo114[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2958 static MCOperandInfo OperandInfo115[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2959 static MCOperandInfo OperandInfo116[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2960 static MCOperandInfo OperandInfo117[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2961 static MCOperandInfo OperandInfo118[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2962 static MCOperandInfo OperandInfo119[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2963 static MCOperandInfo OperandInfo120[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2964 static MCOperandInfo OperandInfo121[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2965 static MCOperandInfo OperandInfo122[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2966 static MCOperandInfo OperandInfo123[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2967 static MCOperandInfo OperandInfo124[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2968 static MCOperandInfo OperandInfo125[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2969 static MCOperandInfo OperandInfo126[] = { { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
2970 static MCOperandInfo OperandInfo127[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2971 static MCOperandInfo OperandInfo128[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2972 static MCOperandInfo OperandInfo129[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2973 static MCOperandInfo OperandInfo130[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2974 static MCOperandInfo OperandInfo131[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2975 static MCOperandInfo OperandInfo132[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2976 static MCOperandInfo OperandInfo133[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2977 static MCOperandInfo OperandInfo134[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2978 static MCOperandInfo OperandInfo135[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2979 static MCOperandInfo OperandInfo136[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2980 static MCOperandInfo OperandInfo137[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2981 static MCOperandInfo OperandInfo138[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2982 static MCOperandInfo OperandInfo139[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2983 static MCOperandInfo OperandInfo140[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2984 static MCOperandInfo OperandInfo141[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2985 static MCOperandInfo OperandInfo142[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2986 static MCOperandInfo OperandInfo143[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
2987 static MCOperandInfo OperandInfo144[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
2988 static MCOperandInfo OperandInfo145[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
2989 static MCOperandInfo OperandInfo146[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2990 static MCOperandInfo OperandInfo147[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2991 static MCOperandInfo OperandInfo148[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2992 static MCOperandInfo OperandInfo149[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2993 static MCOperandInfo OperandInfo150[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2994 static MCOperandInfo OperandInfo151[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2995 static MCOperandInfo OperandInfo152[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2996 static MCOperandInfo OperandInfo153[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2997 static MCOperandInfo OperandInfo154[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2998 static MCOperandInfo OperandInfo155[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
2999 static MCOperandInfo OperandInfo156[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3000 static MCOperandInfo OperandInfo157[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3001 static MCOperandInfo OperandInfo158[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3002 static MCOperandInfo OperandInfo159[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3003 static MCOperandInfo OperandInfo160[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3004 static MCOperandInfo OperandInfo161[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3005 static MCOperandInfo OperandInfo162[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3006 static MCOperandInfo OperandInfo163[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3007 static MCOperandInfo OperandInfo164[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3008 static MCOperandInfo OperandInfo165[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3009 static MCOperandInfo OperandInfo166[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3010 static MCOperandInfo OperandInfo167[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3011 static MCOperandInfo OperandInfo168[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3012 static MCOperandInfo OperandInfo169[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3013 static MCOperandInfo OperandInfo170[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3014 static MCOperandInfo OperandInfo171[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3015 static MCOperandInfo OperandInfo172[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3016 static MCOperandInfo OperandInfo173[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3017 static MCOperandInfo OperandInfo174[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3018 static MCOperandInfo OperandInfo175[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3019 static MCOperandInfo OperandInfo176[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3020 static MCOperandInfo OperandInfo177[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3021 static MCOperandInfo OperandInfo178[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3022 static MCOperandInfo OperandInfo179[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3023 static MCOperandInfo OperandInfo180[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3024 static MCOperandInfo OperandInfo181[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3025 static MCOperandInfo OperandInfo182[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3026 static MCOperandInfo OperandInfo183[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3027 static MCOperandInfo OperandInfo184[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3028 static MCOperandInfo OperandInfo185[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3029 static MCOperandInfo OperandInfo186[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3030 static MCOperandInfo OperandInfo187[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3031 static MCOperandInfo OperandInfo188[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3032 static MCOperandInfo OperandInfo189[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((4 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3033 static MCOperandInfo OperandInfo190[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3034 static MCOperandInfo OperandInfo191[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((4 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3035 static MCOperandInfo OperandInfo192[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3036 static MCOperandInfo OperandInfo193[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3037 static MCOperandInfo OperandInfo194[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3038 static MCOperandInfo OperandInfo195[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3039 static MCOperandInfo OperandInfo196[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3040 static MCOperandInfo OperandInfo197[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3041 static MCOperandInfo OperandInfo198[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3042 static MCOperandInfo OperandInfo199[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3043 static MCOperandInfo OperandInfo200[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3044 static MCOperandInfo OperandInfo201[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3045 static MCOperandInfo OperandInfo202[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3046 static MCOperandInfo OperandInfo203[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3047 static MCOperandInfo OperandInfo204[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3048 static MCOperandInfo OperandInfo205[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3049 static MCOperandInfo OperandInfo206[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3050 static MCOperandInfo OperandInfo207[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3051 static MCOperandInfo OperandInfo208[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3052 static MCOperandInfo OperandInfo209[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3053 static MCOperandInfo OperandInfo210[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3054 static MCOperandInfo OperandInfo211[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3055 static MCOperandInfo OperandInfo212[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3056 static MCOperandInfo OperandInfo213[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3057 static MCOperandInfo OperandInfo214[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3058 static MCOperandInfo OperandInfo215[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3059 static MCOperandInfo OperandInfo216[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3060 static MCOperandInfo OperandInfo217[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3061 static MCOperandInfo OperandInfo218[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3062 static MCOperandInfo OperandInfo219[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3063 static MCOperandInfo OperandInfo220[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3064 static MCOperandInfo OperandInfo221[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3065 static MCOperandInfo OperandInfo222[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3066 static MCOperandInfo OperandInfo223[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3067 static MCOperandInfo OperandInfo224[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3068 static MCOperandInfo OperandInfo225[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3069 static MCOperandInfo OperandInfo226[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3070 static MCOperandInfo OperandInfo227[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3071 static MCOperandInfo OperandInfo228[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3072 static MCOperandInfo OperandInfo229[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3073 static MCOperandInfo OperandInfo230[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3074 static MCOperandInfo OperandInfo231[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3075 static MCOperandInfo OperandInfo232[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3076 static MCOperandInfo OperandInfo233[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3077 static MCOperandInfo OperandInfo234[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3078 static MCOperandInfo OperandInfo235[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3079 static MCOperandInfo OperandInfo236[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3080 static MCOperandInfo OperandInfo237[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3081 static MCOperandInfo OperandInfo238[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3082 static MCOperandInfo OperandInfo239[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3083 static MCOperandInfo OperandInfo240[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3084 static MCOperandInfo OperandInfo241[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3085 static MCOperandInfo OperandInfo242[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3086 static MCOperandInfo OperandInfo243[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3087 static MCOperandInfo OperandInfo244[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3088 static MCOperandInfo OperandInfo245[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3089 static MCOperandInfo OperandInfo246[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3090 static MCOperandInfo OperandInfo247[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3091 static MCOperandInfo OperandInfo248[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3092 static MCOperandInfo OperandInfo249[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3093 static MCOperandInfo OperandInfo250[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3094 static MCOperandInfo OperandInfo251[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3095 static MCOperandInfo OperandInfo252[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3096 static MCOperandInfo OperandInfo253[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3097 static MCOperandInfo OperandInfo254[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3098 static MCOperandInfo OperandInfo255[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3099 static MCOperandInfo OperandInfo256[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3100 static MCOperandInfo OperandInfo257[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3101 static MCOperandInfo OperandInfo258[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3102 static MCOperandInfo OperandInfo259[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3103 static MCOperandInfo OperandInfo260[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3104 static MCOperandInfo OperandInfo261[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3105 static MCOperandInfo OperandInfo262[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3106 static MCOperandInfo OperandInfo263[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3107 static MCOperandInfo OperandInfo264[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3108 static MCOperandInfo OperandInfo265[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3109 static MCOperandInfo OperandInfo266[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3110 static MCOperandInfo OperandInfo267[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3111 static MCOperandInfo OperandInfo268[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3112 static MCOperandInfo OperandInfo269[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3113 static MCOperandInfo OperandInfo270[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3114 static MCOperandInfo OperandInfo271[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3115 static MCOperandInfo OperandInfo272[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3116 static MCOperandInfo OperandInfo273[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3117 static MCOperandInfo OperandInfo274[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3118 static MCOperandInfo OperandInfo275[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3119 static MCOperandInfo OperandInfo276[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3120 static MCOperandInfo OperandInfo277[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3121 static MCOperandInfo OperandInfo278[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3122 static MCOperandInfo OperandInfo279[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3123 static MCOperandInfo OperandInfo280[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3124 static MCOperandInfo OperandInfo281[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3125 static MCOperandInfo OperandInfo282[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3126 static MCOperandInfo OperandInfo283[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3127 static MCOperandInfo OperandInfo284[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3128 static MCOperandInfo OperandInfo285[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3129 static MCOperandInfo OperandInfo286[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3130 static MCOperandInfo OperandInfo287[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3131 static MCOperandInfo OperandInfo288[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3132 static MCOperandInfo OperandInfo289[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3133 static MCOperandInfo OperandInfo290[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3134 static MCOperandInfo OperandInfo291[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3135 static MCOperandInfo OperandInfo292[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3136 static MCOperandInfo OperandInfo293[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3137 static MCOperandInfo OperandInfo294[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3138 static MCOperandInfo OperandInfo295[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3139 static MCOperandInfo OperandInfo296[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3140 static MCOperandInfo OperandInfo297[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3141 static MCOperandInfo OperandInfo298[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3142 static MCOperandInfo OperandInfo299[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3143 static MCOperandInfo OperandInfo300[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3144 static MCOperandInfo OperandInfo301[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3145 static MCOperandInfo OperandInfo302[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3146 static MCOperandInfo OperandInfo303[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3147 static MCOperandInfo OperandInfo304[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3148 static MCOperandInfo OperandInfo305[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3149 static MCOperandInfo OperandInfo306[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3150 static MCOperandInfo OperandInfo307[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
3151 static MCOperandInfo OperandInfo308[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3152 static MCOperandInfo OperandInfo309[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3153 static MCOperandInfo OperandInfo310[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3154 static MCOperandInfo OperandInfo311[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3155 static MCOperandInfo OperandInfo312[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3156 static MCOperandInfo OperandInfo313[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
3157 static MCOperandInfo OperandInfo314[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3158 static MCOperandInfo OperandInfo315[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3159 static MCOperandInfo OperandInfo316[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3160 static MCOperandInfo OperandInfo317[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3161 static MCOperandInfo OperandInfo318[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3162 static MCOperandInfo OperandInfo319[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3163 static MCOperandInfo OperandInfo320[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3164 static MCOperandInfo OperandInfo321[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3165 static MCOperandInfo OperandInfo322[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3166 static MCOperandInfo OperandInfo323[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3167 static MCOperandInfo OperandInfo324[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3168 static MCOperandInfo OperandInfo325[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3169 static MCOperandInfo OperandInfo326[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3170 static MCOperandInfo OperandInfo327[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3171 static MCOperandInfo OperandInfo328[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3172 static MCOperandInfo OperandInfo329[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3173 static MCOperandInfo OperandInfo330[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3174 static MCOperandInfo OperandInfo331[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3175 static MCOperandInfo OperandInfo332[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3176 static MCOperandInfo OperandInfo333[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
3177 static MCOperandInfo OperandInfo334[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3178 static MCOperandInfo OperandInfo335[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3179 static MCOperandInfo OperandInfo336[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3180 static MCOperandInfo OperandInfo337[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3181 static MCOperandInfo OperandInfo338[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3182 static MCOperandInfo OperandInfo339[] = { { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3183 static MCOperandInfo OperandInfo340[] = { { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3184 static MCOperandInfo OperandInfo341[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3185 static MCOperandInfo OperandInfo342[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
3186 static MCOperandInfo OperandInfo343[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
3187 static MCOperandInfo OperandInfo344[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3188 static MCOperandInfo OperandInfo345[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
3189 static MCOperandInfo OperandInfo346[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3190 static MCOperandInfo OperandInfo347[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3191 static MCOperandInfo OperandInfo348[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3192 static MCOperandInfo OperandInfo349[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3193 static MCOperandInfo OperandInfo350[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3194 static MCOperandInfo OperandInfo351[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
3195 static MCOperandInfo OperandInfo352[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3196 static MCOperandInfo OperandInfo353[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3197 static MCOperandInfo OperandInfo354[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3198 static MCOperandInfo OperandInfo355[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3199 static MCOperandInfo OperandInfo356[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3200 static MCOperandInfo OperandInfo357[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3201 static MCOperandInfo OperandInfo358[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
3202 static MCOperandInfo OperandInfo359[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3203 static MCOperandInfo OperandInfo360[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3204 static MCOperandInfo OperandInfo361[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
3205 
3206 
3207 static const MCInstrDesc ARMInsts[] = {
3208  { 0, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #0 = PHI
3209  { 1, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Variadic), 0x0ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #1 = INLINEASM
3210  { 2, 1, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2,0,nullptr }, // Inst #2 = CFI_INSTRUCTION
3211  { 3, 1, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2,0,nullptr }, // Inst #3 = EH_LABEL
3212  { 4, 1, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2,0,nullptr }, // Inst #4 = GC_LABEL
3213  { 5, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Variadic), 0x0ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #5 = KILL
3214  { 6, 3, 1, 0, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo3,0,nullptr }, // Inst #6 = EXTRACT_SUBREG
3215  { 7, 4, 1, 0, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4,0,nullptr }, // Inst #7 = INSERT_SUBREG
3216  { 8, 1, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Rematerializable)|(1<<MCID_CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #8 = IMPLICIT_DEF
3217  { 9, 4, 1, 0, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo6,0,nullptr }, // Inst #9 = SUBREG_TO_REG
3218  { 10, 3, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo3,0,nullptr }, // Inst #10 = COPY_TO_REGCLASS
3219  { 11, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Variadic), 0x0ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #11 = DBG_VALUE
3220  { 12, 2, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Variadic)|(1<<MCID_CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7,0,nullptr }, // Inst #12 = REG_SEQUENCE
3221  { 13, 2, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo7,0,nullptr }, // Inst #13 = COPY
3222  { 14, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #14 = BUNDLE
3223  { 15, 1, 0, 0, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2,0,nullptr }, // Inst #15 = LIFETIME_START
3224  { 16, 1, 0, 0, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo2,0,nullptr }, // Inst #16 = LIFETIME_END
3225  { 17, 2, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Call)|(1<<MCID_MayLoad)|(1<<MCID_UsesCustomInserter)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo8,0,nullptr }, // Inst #17 = STACKMAP
3226  { 18, 6, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Call)|(1<<MCID_MayLoad)|(1<<MCID_UsesCustomInserter)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo9,0,nullptr }, // Inst #18 = PATCHPOINT
3227  { 19, 1, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo10,0,nullptr }, // Inst #19 = LOAD_STACK_GUARD
3228  { 20, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Call)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #20 = STATEPOINT
3229  { 21, 2, 0, 0, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo11,0,nullptr }, // Inst #21 = FRAME_ALLOC
3230  { 22, 2, 1, 590, 8, 0|(1<<MCID_Pseudo)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo12,0,nullptr }, // Inst #22 = ABS
3231  { 23, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo13,0,nullptr }, // Inst #23 = ADCri
3232  { 24, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo14,0,nullptr }, // Inst #24 = ADCrr
3233  { 25, 7, 1, 3, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo15,0,nullptr }, // Inst #25 = ADCrsi
3234  { 26, 8, 1, 4, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo16,0,nullptr }, // Inst #26 = ADCrsr
3235  { 27, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo17,0,nullptr }, // Inst #27 = ADDSri
3236  { 28, 5, 1, 2, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo18,0,nullptr }, // Inst #28 = ADDSrr
3237  { 29, 6, 1, 3, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo19,0,nullptr }, // Inst #29 = ADDSrsi
3238  { 30, 7, 1, 5, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo20,0,nullptr }, // Inst #30 = ADDSrsr
3239  { 31, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #31 = ADDri
3240  { 32, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #32 = ADDrr
3241  { 33, 7, 1, 3, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo15,0,nullptr }, // Inst #33 = ADDrsi
3242  { 34, 8, 1, 4, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo21,0,nullptr }, // Inst #34 = ADDrsr
3243  { 35, 3, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo22,0,nullptr }, // Inst #35 = ADJCALLSTACKDOWN
3244  { 36, 4, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo23,0,nullptr }, // Inst #36 = ADJCALLSTACKUP
3245  { 37, 4, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xd01ULL, nullptr, nullptr, OperandInfo24,0,nullptr }, // Inst #37 = ADR
3246  { 38, 3, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #38 = AESD
3247  { 39, 3, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #39 = AESE
3248  { 40, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #40 = AESIMC
3249  { 41, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #41 = AESMC
3250  { 42, 6, 1, 264, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #42 = ANDri
3251  { 43, 6, 1, 265, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #43 = ANDrr
3252  { 44, 7, 1, 266, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo15,0,nullptr }, // Inst #44 = ANDrsi
3253  { 45, 8, 1, 267, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo21,0,nullptr }, // Inst #45 = ANDrsr
3254  { 46, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #46 = ASRi
3255  { 47, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo27,0,nullptr }, // Inst #47 = ASRr
3256  { 48, 1, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x0ULL, nullptr, nullptr, OperandInfo28,0,nullptr }, // Inst #48 = B
3257  { 49, 4, 0, 10, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_Terminator)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo29,0,nullptr }, // Inst #49 = BCCZi64
3258  { 50, 6, 0, 10, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_Terminator)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, ImplicitList1, OperandInfo30,0,nullptr }, // Inst #50 = BCCi64
3259  { 51, 5, 1, 278, 4, 0|(1<<MCID_Predicable), 0x201ULL, nullptr, nullptr, OperandInfo31,0,nullptr }, // Inst #51 = BFC
3260  { 52, 6, 1, 278, 4, 0|(1<<MCID_Predicable), 0x201ULL, nullptr, nullptr, OperandInfo32,0,nullptr }, // Inst #52 = BFI
3261  { 53, 6, 1, 264, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #53 = BICri
3262  { 54, 6, 1, 265, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #54 = BICrr
3263  { 55, 7, 1, 266, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo15,0,nullptr }, // Inst #55 = BICrsi
3264  { 56, 8, 1, 267, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo21,0,nullptr }, // Inst #56 = BICrsr
3265  { 57, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #57 = BKPT
3266  { 58, 1, 0, 12, 4, 0|(1<<MCID_Call), 0x100ULL, ImplicitList2, ImplicitList3, OperandInfo28,0,nullptr }, // Inst #58 = BL
3267  { 59, 1, 0, 12, 4, 0|(1<<MCID_Call), 0x180ULL, ImplicitList2, ImplicitList3, OperandInfo33,0,nullptr }, // Inst #59 = BLX
3268  { 60, 3, 0, 12, 4, 0|(1<<MCID_Call)|(1<<MCID_Predicable), 0x180ULL, ImplicitList2, ImplicitList3, OperandInfo34,0,nullptr }, // Inst #60 = BLX_pred
3269  { 61, 1, 0, 13, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x180ULL, nullptr, nullptr, OperandInfo28,0,nullptr }, // Inst #61 = BLXi
3270  { 62, 3, 0, 12, 4, 0|(1<<MCID_Call)|(1<<MCID_Predicable), 0x100ULL, ImplicitList2, ImplicitList3, OperandInfo35,0,nullptr }, // Inst #62 = BL_pred
3271  { 63, 1, 0, 10, 8, 0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo28,0,nullptr }, // Inst #63 = BMOVPCB_CALL
3272  { 64, 1, 0, 10, 8, 0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo36,0,nullptr }, // Inst #64 = BMOVPCRX_CALL
3273  { 65, 4, 0, 14, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo37,0,nullptr }, // Inst #65 = BR_JTadd
3274  { 66, 5, 0, 14, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_MayLoad)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo38,0,nullptr }, // Inst #66 = BR_JTm
3275  { 67, 3, 0, 10, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo39,0,nullptr }, // Inst #67 = BR_JTr
3276  { 68, 1, 0, 10, 4, 0|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator), 0x180ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #68 = BX
3277  { 69, 3, 0, 15, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo34,0,nullptr }, // Inst #69 = BXJ
3278  { 70, 1, 0, 10, 8, 0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo36,0,nullptr }, // Inst #70 = BX_CALL
3279  { 71, 2, 0, 10, 4, 0|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x180ULL, nullptr, nullptr, OperandInfo40,0,nullptr }, // Inst #71 = BX_RET
3280  { 72, 3, 0, 10, 4, 0|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x180ULL, nullptr, nullptr, OperandInfo34,0,nullptr }, // Inst #72 = BX_pred
3281  { 73, 3, 0, 10, 4, 0|(1<<MCID_Branch)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo35,0,nullptr }, // Inst #73 = Bcc
3282  { 74, 8, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo41,0,nullptr }, // Inst #74 = CDP
3283  { 75, 6, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo42,0,nullptr }, // Inst #75 = CDP2
3284  { 76, 0, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #76 = CLREX
3285  { 77, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #77 = CLZ
3286  { 78, 4, 0, 17, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo24,0,nullptr }, // Inst #78 = CMNri
3287  { 79, 4, 0, 18, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x201ULL, nullptr, ImplicitList1, OperandInfo43,0,nullptr }, // Inst #79 = CMNzrr
3288  { 80, 5, 0, 19, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x1501ULL, nullptr, ImplicitList1, OperandInfo44,0,nullptr }, // Inst #80 = CMNzrsi
3289  { 81, 6, 0, 20, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x281ULL, nullptr, ImplicitList1, OperandInfo45,0,nullptr }, // Inst #81 = CMNzrsr
3290  { 82, 4, 0, 17, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo24,0,nullptr }, // Inst #82 = CMPri
3291  { 83, 4, 0, 18, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo43,0,nullptr }, // Inst #83 = CMPrr
3292  { 84, 5, 0, 19, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x1501ULL, nullptr, ImplicitList1, OperandInfo44,0,nullptr }, // Inst #84 = CMPrsi
3293  { 85, 6, 0, 20, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x281ULL, nullptr, ImplicitList1, OperandInfo45,0,nullptr }, // Inst #85 = CMPrsr
3294  { 86, 3, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo3,0,nullptr }, // Inst #86 = CONSTPOOL_ENTRY
3295  { 87, 4, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo37,0,nullptr }, // Inst #87 = COPY_STRUCT_BYVAL_I32
3296  { 88, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #88 = CPS1p
3297  { 89, 2, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo7,0,nullptr }, // Inst #89 = CPS2p
3298  { 90, 3, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo46,0,nullptr }, // Inst #90 = CPS3p
3299  { 91, 3, 1, 0, 4, 0, 0xd00ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #91 = CRC32B
3300  { 92, 3, 1, 0, 4, 0, 0xd00ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #92 = CRC32CB
3301  { 93, 3, 1, 0, 4, 0, 0xd00ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #93 = CRC32CH
3302  { 94, 3, 1, 0, 4, 0, 0xd00ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #94 = CRC32CW
3303  { 95, 3, 1, 0, 4, 0, 0xd00ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #95 = CRC32H
3304  { 96, 3, 1, 0, 4, 0, 0xd00ULL, nullptr, nullptr, OperandInfo47,0,nullptr }, // Inst #96 = CRC32W
3305  { 97, 3, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #97 = DBG
3306  { 98, 1, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #98 = DMB
3307  { 99, 1, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #99 = DSB
3308  { 100, 6, 1, 264, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #100 = EORri
3309  { 101, 6, 1, 265, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #101 = EORrr
3310  { 102, 7, 1, 266, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo15,0,nullptr }, // Inst #102 = EORrsi
3311  { 103, 8, 1, 267, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo21,0,nullptr }, // Inst #103 = EORrsr
3312  { 104, 2, 0, 0, 4, 0|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, ImplicitList4, OperandInfo40,0,nullptr }, // Inst #104 = ERET
3313  { 105, 4, 1, 487, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x8c00ULL, nullptr, nullptr, OperandInfo49,0,nullptr }, // Inst #105 = FCONSTD
3314  { 106, 4, 1, 488, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x8c00ULL, nullptr, nullptr, OperandInfo50,0,nullptr }, // Inst #106 = FCONSTS
3315  { 107, 5, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b64ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #107 = FLDMXDB_UPD
3316  { 108, 4, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b04ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #108 = FLDMXIA
3317  { 109, 5, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b64ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #109 = FLDMXIA_UPD
3318  { 110, 2, 0, 507, 4, 0|(1<<MCID_Predicable), 0x8c00ULL, ImplicitList5, ImplicitList1, OperandInfo40,0,nullptr }, // Inst #110 = FMSTAT
3319  { 111, 5, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b64ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #111 = FSTMXDB_UPD
3320  { 112, 4, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b04ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #112 = FSTMXIA
3321  { 113, 5, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b64ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #113 = FSTMXIA_UPD
3322  { 114, 3, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #114 = HINT
3323  { 115, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #115 = HLT
3324  { 116, 1, 0, 0, 4, 0|(1<<MCID_Call)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #116 = HVC
3325  { 117, 1, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #117 = ISB
3326  { 118, 2, 0, 377, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo7,0,0 }, // Inst #118 = ITasm
3327  { 119, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Barrier)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #119 = Int_eh_sjlj_dispatchsetup
3328  { 120, 2, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList6, OperandInfo12,0,nullptr }, // Inst #120 = Int_eh_sjlj_longjmp
3329  { 121, 2, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Barrier)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList7, OperandInfo12,0,nullptr }, // Inst #121 = Int_eh_sjlj_setjmp
3330  { 122, 2, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Barrier)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList8, OperandInfo12,0,nullptr }, // Inst #122 = Int_eh_sjlj_setjmp_nofp
3331  { 123, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x580ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #123 = LDA
3332  { 124, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x580ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #124 = LDAB
3333  { 125, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #125 = LDAEX
3334  { 126, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #126 = LDAEXB
3335  { 127, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x580ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #127 = LDAEXD
3336  { 128, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #128 = LDAEXH
3337  { 129, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x580ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #129 = LDAH
3338  { 130, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #130 = LDC2L_OFFSET
3339  { 131, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #131 = LDC2L_OPTION
3340  { 132, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #132 = LDC2L_POST
3341  { 133, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #133 = LDC2L_PRE
3342  { 134, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #134 = LDC2_OFFSET
3343  { 135, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #135 = LDC2_OPTION
3344  { 136, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #136 = LDC2_POST
3345  { 137, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #137 = LDC2_PRE
3346  { 138, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #138 = LDCL_OFFSET
3347  { 139, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #139 = LDCL_OPTION
3348  { 140, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #140 = LDCL_POST
3349  { 141, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #141 = LDCL_PRE
3350  { 142, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #142 = LDC_OFFSET
3351  { 143, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #143 = LDC_OPTION
3352  { 144, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #144 = LDC_POST
3353  { 145, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #145 = LDC_PRE
3354  { 146, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #146 = LDMDA
3355  { 147, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #147 = LDMDA_UPD
3356  { 148, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #148 = LDMDB
3357  { 149, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #149 = LDMDB_UPD
3358  { 150, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #150 = LDMIA
3359  { 151, 5, 1, 355, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #151 = LDMIA_RET
3360  { 152, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #152 = LDMIA_UPD
3361  { 153, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #153 = LDMIB
3362  { 154, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #154 = LDMIB_UPD
3363  { 155, 4, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #155 = LDRBT_POST
3364  { 156, 7, 2, 341, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #156 = LDRBT_POST_IMM
3365  { 157, 7, 2, 341, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #157 = LDRBT_POST_REG
3366  { 158, 7, 2, 342, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #158 = LDRB_POST_IMM
3367  { 159, 7, 2, 341, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #159 = LDRB_POST_REG
3368  { 160, 6, 2, 342, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x322ULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #160 = LDRB_PRE_IMM
3369  { 161, 7, 2, 341, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x322ULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #161 = LDRB_PRE_REG
3370  { 162, 5, 1, 325, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x310ULL, nullptr, nullptr, OperandInfo59,0,nullptr }, // Inst #162 = LDRBi12
3371  { 163, 6, 1, 326, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x300ULL, nullptr, nullptr, OperandInfo60,0,nullptr }, // Inst #163 = LDRBrs
3372  { 164, 7, 2, 350, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x403ULL, nullptr, nullptr, OperandInfo61,0,nullptr }, // Inst #164 = LDRD
3373  { 165, 8, 3, 352, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x443ULL, nullptr, nullptr, OperandInfo62,0,nullptr }, // Inst #165 = LDRD_POST
3374  { 166, 8, 3, 352, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x423ULL, nullptr, nullptr, OperandInfo62,0,nullptr }, // Inst #166 = LDRD_PRE
3375  { 167, 4, 1, 327, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #167 = LDREX
3376  { 168, 4, 1, 327, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #168 = LDREXB
3377  { 169, 4, 1, 327, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x580ULL, nullptr, nullptr, OperandInfo54,0,nullptr }, // Inst #169 = LDREXD
3378  { 170, 4, 1, 327, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #170 = LDREXH
3379  { 171, 6, 1, 335, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x403ULL, nullptr, nullptr, OperandInfo63,0,nullptr }, // Inst #171 = LDRH
3380  { 172, 6, 2, 343, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #172 = LDRHTi
3381  { 173, 7, 2, 343, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo64,0,nullptr }, // Inst #173 = LDRHTr
3382  { 174, 7, 2, 343, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo65,0,nullptr }, // Inst #174 = LDRH_POST
3383  { 175, 7, 2, 343, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x423ULL, nullptr, nullptr, OperandInfo65,0,nullptr }, // Inst #175 = LDRH_PRE
3384  { 176, 2, 1, 33, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo66,0,nullptr }, // Inst #176 = LDRLIT_ga_abs
3385  { 177, 2, 1, 34, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo66,0,nullptr }, // Inst #177 = LDRLIT_ga_pcrel
3386  { 178, 2, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo66,0,nullptr }, // Inst #178 = LDRLIT_ga_pcrel_ldr
3387  { 179, 6, 1, 288, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x403ULL, nullptr, nullptr, OperandInfo63,0,nullptr }, // Inst #179 = LDRSB
3388  { 180, 6, 2, 289, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #180 = LDRSBTi
3389  { 181, 7, 2, 289, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo64,0,nullptr }, // Inst #181 = LDRSBTr
3390  { 182, 7, 2, 289, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo65,0,nullptr }, // Inst #182 = LDRSB_POST
3391  { 183, 7, 2, 289, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x423ULL, nullptr, nullptr, OperandInfo65,0,nullptr }, // Inst #183 = LDRSB_PRE
3392  { 184, 6, 1, 288, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x403ULL, nullptr, nullptr, OperandInfo63,0,nullptr }, // Inst #184 = LDRSH
3393  { 185, 6, 2, 289, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #185 = LDRSHTi
3394  { 186, 7, 2, 289, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo64,0,nullptr }, // Inst #186 = LDRSHTr
3395  { 187, 7, 2, 289, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, nullptr, nullptr, OperandInfo65,0,nullptr }, // Inst #187 = LDRSH_POST
3396  { 188, 7, 2, 289, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x423ULL, nullptr, nullptr, OperandInfo65,0,nullptr }, // Inst #188 = LDRSH_PRE
3397  { 189, 4, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #189 = LDRT_POST
3398  { 190, 7, 2, 344, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #190 = LDRT_POST_IMM
3399  { 191, 7, 2, 344, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #191 = LDRT_POST_REG
3400  { 192, 7, 2, 345, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #192 = LDR_POST_IMM
3401  { 193, 7, 2, 344, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #193 = LDR_POST_REG
3402  { 194, 6, 2, 345, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x322ULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #194 = LDR_PRE_IMM
3403  { 195, 7, 2, 344, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x322ULL, nullptr, nullptr, OperandInfo57,0,nullptr }, // Inst #195 = LDR_PRE_REG
3404  { 196, 5, 1, 336, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x310ULL, nullptr, nullptr, OperandInfo44,0,nullptr }, // Inst #196 = LDRcp
3405  { 197, 5, 1, 328, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x310ULL, nullptr, nullptr, OperandInfo44,0,nullptr }, // Inst #197 = LDRi12
3406  { 198, 6, 1, 287, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x300ULL, nullptr, nullptr, OperandInfo67,0,nullptr }, // Inst #198 = LDRrs
3407  { 199, 4, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo68,0,nullptr }, // Inst #199 = LEApcrel
3408  { 200, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo69,0,nullptr }, // Inst #200 = LEApcrelJT
3409  { 201, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #201 = LSLi
3410  { 202, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo27,0,nullptr }, // Inst #202 = LSLr
3411  { 203, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #203 = LSRi
3412  { 204, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo27,0,nullptr }, // Inst #204 = LSRr
3413  { 205, 8, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo70,0,0 }, // Inst #205 = MCR
3414  { 206, 6, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo71,0,nullptr }, // Inst #206 = MCR2
3415  { 207, 7, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo72,0,nullptr }, // Inst #207 = MCRR
3416  { 208, 5, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo73,0,nullptr }, // Inst #208 = MCRR2
3417  { 209, 7, 1, 279, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo74,0,nullptr }, // Inst #209 = MLA
3418  { 210, 7, 1, 279, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo75,0,nullptr }, // Inst #210 = MLAv5
3419  { 211, 6, 1, 279, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo76,0,nullptr }, // Inst #211 = MLS
3420  { 212, 5, 1, 40, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo31,0,nullptr }, // Inst #212 = MOVCCi
3421  { 213, 5, 1, 41, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo31,0,nullptr }, // Inst #213 = MOVCCi16
3422  { 214, 5, 1, 273, 8, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo77,0,nullptr }, // Inst #214 = MOVCCi32imm
3423  { 215, 5, 1, 43, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Select)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x0ULL, nullptr, nullptr, OperandInfo78,0,nullptr }, // Inst #215 = MOVCCr
3424  { 216, 6, 1, 268, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo79,0,nullptr }, // Inst #216 = MOVCCsi
3425  { 217, 7, 1, 268, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo80,0,nullptr }, // Inst #217 = MOVCCsr
3426  { 218, 2, 0, 10, 4, 0|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x180ULL, nullptr, nullptr, OperandInfo40,0,nullptr }, // Inst #218 = MOVPCLR
3427  { 219, 1, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator), 0x0ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #219 = MOVPCRX
3428  { 220, 5, 1, 41, 4, 0|(1<<MCID_Predicable), 0x2201ULL, nullptr, nullptr, OperandInfo81,0,nullptr }, // Inst #220 = MOVTi16
3429  { 221, 4, 1, 41, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo82,0,nullptr }, // Inst #221 = MOVTi16_ga_pcrel
3430  { 222, 2, 1, 275, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo66,0,nullptr }, // Inst #222 = MOV_ga_pcrel
3431  { 223, 2, 1, 276, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo66,0,nullptr }, // Inst #223 = MOV_ga_pcrel_ldr
3432  { 224, 5, 1, 41, 4, 0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef)|(1<<MCID_CheapAsAMove), 0x2201ULL, nullptr, nullptr, OperandInfo83,0,nullptr }, // Inst #224 = MOVi
3433  { 225, 4, 1, 41, 4, 0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_CheapAsAMove), 0x2201ULL, nullptr, nullptr, OperandInfo24,0,nullptr }, // Inst #225 = MOVi16
3434  { 226, 3, 1, 41, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo84,0,nullptr }, // Inst #226 = MOVi16_ga_pcrel
3435  { 227, 2, 1, 274, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo66,0,nullptr }, // Inst #227 = MOVi32imm
3436  { 228, 5, 1, 48, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2201ULL, nullptr, nullptr, OperandInfo85,0,nullptr }, // Inst #228 = MOVr
3437  { 229, 5, 1, 48, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2201ULL, nullptr, nullptr, OperandInfo86,0,nullptr }, // Inst #229 = MOVr_TC
3438  { 230, 6, 1, 269, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x3501ULL, nullptr, nullptr, OperandInfo87,0,nullptr }, // Inst #230 = MOVsi
3439  { 231, 7, 1, 269, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2281ULL, nullptr, nullptr, OperandInfo88,0,nullptr }, // Inst #231 = MOVsr
3440  { 232, 2, 1, 270, 0, 0|(1<<MCID_Pseudo), 0x2000ULL, nullptr, ImplicitList1, OperandInfo12,0,nullptr }, // Inst #232 = MOVsra_flag
3441  { 233, 2, 1, 270, 0, 0|(1<<MCID_Pseudo), 0x2000ULL, nullptr, ImplicitList1, OperandInfo12,0,nullptr }, // Inst #233 = MOVsrl_flag
3442  { 234, 8, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo89,0,nullptr }, // Inst #234 = MRC
3443  { 235, 6, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo90,0,nullptr }, // Inst #235 = MRC2
3444  { 236, 7, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo72,0,nullptr }, // Inst #236 = MRRC
3445  { 237, 5, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo73,0,nullptr }, // Inst #237 = MRRC2
3446  { 238, 3, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo91,0,nullptr }, // Inst #238 = MRS
3447  { 239, 4, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo92,0,nullptr }, // Inst #239 = MRSbanked
3448  { 240, 3, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo91,0,nullptr }, // Inst #240 = MRSsys
3449  { 241, 4, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo93,0,nullptr }, // Inst #241 = MSR
3450  { 242, 4, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo94,0,nullptr }, // Inst #242 = MSRbanked
3451  { 243, 4, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo95,0,nullptr }, // Inst #243 = MSRi
3452  { 244, 6, 1, 280, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo27,0,nullptr }, // Inst #244 = MUL
3453  { 245, 6, 1, 280, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo96,0,nullptr }, // Inst #245 = MULv5
3454  { 246, 5, 1, 40, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo31,0,nullptr }, // Inst #246 = MVNCCi
3455  { 247, 5, 1, 52, 4, 0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef)|(1<<MCID_CheapAsAMove), 0x2201ULL, nullptr, nullptr, OperandInfo83,0,nullptr }, // Inst #247 = MVNi
3456  { 248, 5, 1, 272, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2201ULL, nullptr, nullptr, OperandInfo85,0,nullptr }, // Inst #248 = MVNr
3457  { 249, 6, 1, 54, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x3501ULL, nullptr, nullptr, OperandInfo87,0,nullptr }, // Inst #249 = MVNsi
3458  { 250, 7, 1, 271, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2281ULL, nullptr, nullptr, OperandInfo97,0,nullptr }, // Inst #250 = MVNsr
3459  { 251, 6, 1, 264, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #251 = ORRri
3460  { 252, 6, 1, 265, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #252 = ORRrr
3461  { 253, 7, 1, 266, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo15,0,nullptr }, // Inst #253 = ORRrsi
3462  { 254, 8, 1, 267, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo21,0,nullptr }, // Inst #254 = ORRrsr
3463  { 255, 5, 1, 55, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo17,0,nullptr }, // Inst #255 = PICADD
3464  { 256, 5, 1, 286, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo44,0,nullptr }, // Inst #256 = PICLDR
3465  { 257, 5, 1, 335, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo44,0,nullptr }, // Inst #257 = PICLDRB
3466  { 258, 5, 1, 335, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo44,0,nullptr }, // Inst #258 = PICLDRH
3467  { 259, 5, 1, 288, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo44,0,nullptr }, // Inst #259 = PICLDRSB
3468  { 260, 5, 1, 288, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo44,0,nullptr }, // Inst #260 = PICLDRSH
3469  { 261, 5, 0, 358, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo44,0,nullptr }, // Inst #261 = PICSTR
3470  { 262, 5, 0, 359, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo44,0,nullptr }, // Inst #262 = PICSTRB
3471  { 263, 5, 0, 359, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo44,0,nullptr }, // Inst #263 = PICSTRH
3472  { 264, 6, 1, 58, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #264 = PKHBT
3473  { 265, 6, 1, 59, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo98,0,nullptr }, // Inst #265 = PKHTB
3474  { 266, 2, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd10ULL, nullptr, nullptr, OperandInfo99,0,nullptr }, // Inst #266 = PLDWi12
3475  { 267, 3, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd00ULL, nullptr, nullptr, OperandInfo100,0,nullptr }, // Inst #267 = PLDWrs
3476  { 268, 2, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd10ULL, nullptr, nullptr, OperandInfo99,0,nullptr }, // Inst #268 = PLDi12
3477  { 269, 3, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd00ULL, nullptr, nullptr, OperandInfo100,0,nullptr }, // Inst #269 = PLDrs
3478  { 270, 2, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd10ULL, nullptr, nullptr, OperandInfo99,0,nullptr }, // Inst #270 = PLIi12
3479  { 271, 3, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd00ULL, nullptr, nullptr, OperandInfo100,0,nullptr }, // Inst #271 = PLIrs
3480  { 272, 5, 1, 299, 4, 0|(1<<MCID_Predicable), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #272 = QADD
3481  { 273, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #273 = QADD16
3482  { 274, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #274 = QADD8
3483  { 275, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #275 = QASX
3484  { 276, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #276 = QDADD
3485  { 277, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #277 = QDSUB
3486  { 278, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #278 = QSAX
3487  { 279, 5, 1, 299, 4, 0|(1<<MCID_Predicable), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #279 = QSUB
3488  { 280, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #280 = QSUB16
3489  { 281, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #281 = QSUB8
3490  { 282, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #282 = RBIT
3491  { 283, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #283 = REV
3492  { 284, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #284 = REV16
3493  { 285, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #285 = REVSH
3494  { 286, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #286 = RFEDA
3495  { 287, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #287 = RFEDA_UPD
3496  { 288, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #288 = RFEDB
3497  { 289, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #289 = RFEDB_UPD
3498  { 290, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #290 = RFEIA
3499  { 291, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #291 = RFEIA_UPD
3500  { 292, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #292 = RFEIB
3501  { 293, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo33,0,nullptr }, // Inst #293 = RFEIB_UPD
3502  { 294, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #294 = RORi
3503  { 295, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo27,0,nullptr }, // Inst #295 = RORr
3504  { 296, 2, 1, 50, 0, 0|(1<<MCID_Pseudo), 0x2000ULL, ImplicitList1, nullptr, OperandInfo12,0,nullptr }, // Inst #296 = RRX
3505  { 297, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo85,0,nullptr }, // Inst #297 = RRXi
3506  { 298, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo17,0,nullptr }, // Inst #298 = RSBSri
3507  { 299, 6, 1, 3, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo19,0,nullptr }, // Inst #299 = RSBSrsi
3508  { 300, 7, 1, 5, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo20,0,nullptr }, // Inst #300 = RSBSrsr
3509  { 301, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #301 = RSBri
3510  { 302, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x201ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #302 = RSBrr
3511  { 303, 7, 1, 3, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo15,0,nullptr }, // Inst #303 = RSBrsi
3512  { 304, 8, 1, 4, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo21,0,nullptr }, // Inst #304 = RSBrsr
3513  { 305, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo13,0,nullptr }, // Inst #305 = RSCri
3514  { 306, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook)|(1<<MCID_UnmodeledSideEffects), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo14,0,nullptr }, // Inst #306 = RSCrr
3515  { 307, 7, 1, 3, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo15,0,nullptr }, // Inst #307 = RSCrsi
3516  { 308, 8, 1, 4, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo21,0,nullptr }, // Inst #308 = RSCrsr
3517  { 309, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #309 = SADD16
3518  { 310, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #310 = SADD8
3519  { 311, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #311 = SASX
3520  { 312, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo13,0,nullptr }, // Inst #312 = SBCri
3521  { 313, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo14,0,nullptr }, // Inst #313 = SBCrr
3522  { 314, 7, 1, 3, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo15,0,nullptr }, // Inst #314 = SBCrsi
3523  { 315, 8, 1, 4, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo16,0,nullptr }, // Inst #315 = SBCrsr
3524  { 316, 6, 1, 278, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x201ULL, nullptr, nullptr, OperandInfo102,0,nullptr }, // Inst #316 = SBFX
3525  { 317, 5, 1, 324, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo18,0,nullptr }, // Inst #317 = SDIV
3526  { 318, 5, 1, 277, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo18,0,nullptr }, // Inst #318 = SEL
3527  { 319, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5,ARM_HasV8Ops,nullptr }, // Inst #319 = SETEND
3528  { 320, 4, 1, 0, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo103,0,nullptr }, // Inst #320 = SHA1C
3529  { 321, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #321 = SHA1H
3530  { 322, 4, 1, 0, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo103,0,nullptr }, // Inst #322 = SHA1M
3531  { 323, 4, 1, 0, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo103,0,nullptr }, // Inst #323 = SHA1P
3532  { 324, 4, 1, 0, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo103,0,nullptr }, // Inst #324 = SHA1SU0
3533  { 325, 3, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #325 = SHA1SU1
3534  { 326, 4, 1, 0, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo103,0,nullptr }, // Inst #326 = SHA256H
3535  { 327, 4, 1, 0, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo103,0,nullptr }, // Inst #327 = SHA256H2
3536  { 328, 3, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo25,0,nullptr }, // Inst #328 = SHA256SU0
3537  { 329, 4, 1, 0, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo103,0,nullptr }, // Inst #329 = SHA256SU1
3538  { 330, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #330 = SHADD16
3539  { 331, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #331 = SHADD8
3540  { 332, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #332 = SHASX
3541  { 333, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #333 = SHSAX
3542  { 334, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #334 = SHSUB16
3543  { 335, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #335 = SHSUB8
3544  { 336, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #336 = SMC
3545  { 337, 6, 1, 285, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo104,0,nullptr }, // Inst #337 = SMLABB
3546  { 338, 6, 1, 285, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo104,0,nullptr }, // Inst #338 = SMLABT
3547  { 339, 6, 1, 319, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo104,0,nullptr }, // Inst #339 = SMLAD
3548  { 340, 6, 1, 319, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo104,0,nullptr }, // Inst #340 = SMLADX
3549  { 341, 9, 2, 281, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo105,0,nullptr }, // Inst #341 = SMLAL
3550  { 342, 6, 2, 281, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo106,0,nullptr }, // Inst #342 = SMLALBB
3551  { 343, 6, 2, 281, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo106,0,nullptr }, // Inst #343 = SMLALBT
3552  { 344, 6, 2, 283, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo106,0,nullptr }, // Inst #344 = SMLALD
3553  { 345, 6, 2, 283, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo106,0,nullptr }, // Inst #345 = SMLALDX
3554  { 346, 6, 2, 281, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo106,0,nullptr }, // Inst #346 = SMLALTB
3555  { 347, 6, 2, 281, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo106,0,nullptr }, // Inst #347 = SMLALTT
3556  { 348, 9, 2, 281, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo107,0,nullptr }, // Inst #348 = SMLALv5
3557  { 349, 6, 1, 285, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo104,0,nullptr }, // Inst #349 = SMLATB
3558  { 350, 6, 1, 285, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo104,0,nullptr }, // Inst #350 = SMLATT
3559  { 351, 6, 1, 285, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo104,0,nullptr }, // Inst #351 = SMLAWB
3560  { 352, 6, 1, 285, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo104,0,nullptr }, // Inst #352 = SMLAWT
3561  { 353, 6, 1, 316, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo104,0,nullptr }, // Inst #353 = SMLSD
3562  { 354, 6, 1, 316, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo104,0,nullptr }, // Inst #354 = SMLSDX
3563  { 355, 6, 2, 283, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo106,0,nullptr }, // Inst #355 = SMLSLD
3564  { 356, 6, 2, 283, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo106,0,nullptr }, // Inst #356 = SMLSLDX
3565  { 357, 6, 1, 279, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo76,0,nullptr }, // Inst #357 = SMMLA
3566  { 358, 6, 1, 279, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo76,0,nullptr }, // Inst #358 = SMMLAR
3567  { 359, 6, 1, 279, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo76,0,nullptr }, // Inst #359 = SMMLS
3568  { 360, 6, 1, 279, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo76,0,nullptr }, // Inst #360 = SMMLSR
3569  { 361, 5, 1, 280, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo18,0,nullptr }, // Inst #361 = SMMUL
3570  { 362, 5, 1, 280, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo18,0,nullptr }, // Inst #362 = SMMULR
3571  { 363, 5, 1, 314, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #363 = SMUAD
3572  { 364, 5, 1, 314, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #364 = SMUADX
3573  { 365, 5, 1, 284, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo18,0,nullptr }, // Inst #365 = SMULBB
3574  { 366, 5, 1, 284, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo18,0,nullptr }, // Inst #366 = SMULBT
3575  { 367, 7, 2, 321, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo108,0,nullptr }, // Inst #367 = SMULL
3576  { 368, 7, 2, 282, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo109,0,nullptr }, // Inst #368 = SMULLv5
3577  { 369, 5, 1, 284, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo18,0,nullptr }, // Inst #369 = SMULTB
3578  { 370, 5, 1, 284, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo18,0,nullptr }, // Inst #370 = SMULTT
3579  { 371, 5, 1, 284, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo18,0,nullptr }, // Inst #371 = SMULWB
3580  { 372, 5, 1, 284, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo18,0,nullptr }, // Inst #372 = SMULWT
3581  { 373, 5, 1, 309, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #373 = SMUSD
3582  { 374, 5, 1, 309, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #374 = SMUSDX
3583  { 375, 3, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo110,0,nullptr }, // Inst #375 = SPACE
3584  { 376, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #376 = SRSDA
3585  { 377, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #377 = SRSDA_UPD
3586  { 378, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #378 = SRSDB
3587  { 379, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #379 = SRSDB_UPD
3588  { 380, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #380 = SRSIA
3589  { 381, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #381 = SRSIA_UPD
3590  { 382, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #382 = SRSIB
3591  { 383, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #383 = SRSIB_UPD
3592  { 384, 6, 1, 300, 4, 0|(1<<MCID_Predicable), 0x680ULL, nullptr, nullptr, OperandInfo111,0,nullptr }, // Inst #384 = SSAT
3593  { 385, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x680ULL, nullptr, nullptr, OperandInfo112,0,nullptr }, // Inst #385 = SSAT16
3594  { 386, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #386 = SSAX
3595  { 387, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #387 = SSUB16
3596  { 388, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #388 = SSUB8
3597  { 389, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #389 = STC2L_OFFSET
3598  { 390, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #390 = STC2L_OPTION
3599  { 391, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #391 = STC2L_POST
3600  { 392, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #392 = STC2L_PRE
3601  { 393, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #393 = STC2_OFFSET
3602  { 394, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #394 = STC2_OPTION
3603  { 395, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #395 = STC2_POST
3604  { 396, 4, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo55,0,nullptr }, // Inst #396 = STC2_PRE
3605  { 397, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #397 = STCL_OFFSET
3606  { 398, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #398 = STCL_OPTION
3607  { 399, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #399 = STCL_POST
3608  { 400, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #400 = STCL_PRE
3609  { 401, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #401 = STC_OFFSET
3610  { 402, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #402 = STC_OPTION
3611  { 403, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x140ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #403 = STC_POST
3612  { 404, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x120ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #404 = STC_PRE
3613  { 405, 4, 0, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x580ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #405 = STL
3614  { 406, 4, 0, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x580ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #406 = STLB
3615  { 407, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo113,0,nullptr }, // Inst #407 = STLEX
3616  { 408, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo113,0,nullptr }, // Inst #408 = STLEXB
3617  { 409, 5, 1, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x580ULL, nullptr, nullptr, OperandInfo114,0,nullptr }, // Inst #409 = STLEXD
3618  { 410, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo113,0,nullptr }, // Inst #410 = STLEXH
3619  { 411, 4, 0, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x580ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #411 = STLH
3620  { 412, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #412 = STMDA
3621  { 413, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #413 = STMDA_UPD
3622  { 414, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #414 = STMDB
3623  { 415, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #415 = STMDB_UPD
3624  { 416, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #416 = STMIA
3625  { 417, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #417 = STMIA_UPD
3626  { 418, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #418 = STMIB
3627  { 419, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #419 = STMIB_UPD
3628  { 420, 4, 0, 365, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #420 = STRBT_POST
3629  { 421, 7, 1, 366, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x3c2ULL, nullptr, nullptr, OperandInfo115,0,nullptr }, // Inst #421 = STRBT_POST_IMM
3630  { 422, 7, 1, 366, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x3c2ULL, nullptr, nullptr, OperandInfo115,0,nullptr }, // Inst #422 = STRBT_POST_REG
3631  { 423, 7, 1, 367, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo116,0,nullptr }, // Inst #423 = STRB_POST_IMM
3632  { 424, 7, 1, 366, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo116,0,nullptr }, // Inst #424 = STRB_POST_REG
3633  { 425, 6, 1, 367, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3a2ULL, nullptr, nullptr, OperandInfo117,0,nullptr }, // Inst #425 = STRB_PRE_IMM
3634  { 426, 7, 1, 366, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3a2ULL, nullptr, nullptr, OperandInfo116,0,nullptr }, // Inst #426 = STRB_PRE_REG
3635  { 427, 5, 0, 359, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x390ULL, nullptr, nullptr, OperandInfo59,0,nullptr }, // Inst #427 = STRBi12
3636  { 428, 7, 1, 368, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo118,0,nullptr }, // Inst #428 = STRBi_preidx
3637  { 429, 7, 1, 368, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo118,0,nullptr }, // Inst #429 = STRBr_preidx
3638  { 430, 6, 0, 360, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x380ULL, nullptr, nullptr, OperandInfo60,0,nullptr }, // Inst #430 = STRBrs
3639  { 431, 7, 0, 372, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x483ULL, nullptr, nullptr, OperandInfo61,0,nullptr }, // Inst #431 = STRD
3640  { 432, 8, 1, 373, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x4c3ULL, nullptr, nullptr, OperandInfo119,0,nullptr }, // Inst #432 = STRD_POST
3641  { 433, 8, 1, 373, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x4a3ULL, nullptr, nullptr, OperandInfo119,0,nullptr }, // Inst #433 = STRD_PRE
3642  { 434, 5, 1, 361, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo113,0,nullptr }, // Inst #434 = STREX
3643  { 435, 5, 1, 361, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo113,0,nullptr }, // Inst #435 = STREXB
3644  { 436, 5, 1, 361, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x580ULL, nullptr, nullptr, OperandInfo114,0,nullptr }, // Inst #436 = STREXD
3645  { 437, 5, 1, 361, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, nullptr, nullptr, OperandInfo113,0,nullptr }, // Inst #437 = STREXH
3646  { 438, 6, 0, 359, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x483ULL, nullptr, nullptr, OperandInfo63,0,nullptr }, // Inst #438 = STRH
3647  { 439, 6, 1, 366, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x4c3ULL, nullptr, nullptr, OperandInfo120,0,nullptr }, // Inst #439 = STRHTi
3648  { 440, 7, 1, 366, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x4c3ULL, nullptr, nullptr, OperandInfo115,0,nullptr }, // Inst #440 = STRHTr
3649  { 441, 7, 1, 366, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x4c3ULL, nullptr, nullptr, OperandInfo121,0,nullptr }, // Inst #441 = STRH_POST
3650  { 442, 7, 1, 366, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x4a3ULL, nullptr, nullptr, OperandInfo121,0,nullptr }, // Inst #442 = STRH_PRE
3651  { 443, 7, 1, 368, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo122,0,nullptr }, // Inst #443 = STRH_preidx
3652  { 444, 4, 0, 365, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo53,0,nullptr }, // Inst #444 = STRT_POST
3653  { 445, 7, 1, 368, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo115,0,nullptr }, // Inst #445 = STRT_POST_IMM
3654  { 446, 7, 1, 368, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo115,0,nullptr }, // Inst #446 = STRT_POST_REG
3655  { 447, 7, 1, 369, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo116,0,nullptr }, // Inst #447 = STR_POST_IMM
3656  { 448, 7, 1, 368, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, nullptr, nullptr, OperandInfo116,0,nullptr }, // Inst #448 = STR_POST_REG
3657  { 449, 6, 1, 369, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3a2ULL, nullptr, nullptr, OperandInfo117,0,nullptr }, // Inst #449 = STR_PRE_IMM
3658  { 450, 7, 1, 368, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3a2ULL, nullptr, nullptr, OperandInfo116,0,nullptr }, // Inst #450 = STR_PRE_REG
3659  { 451, 5, 0, 358, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x390ULL, nullptr, nullptr, OperandInfo44,0,nullptr }, // Inst #451 = STRi12
3660  { 452, 7, 1, 368, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo118,0,nullptr }, // Inst #452 = STRi_preidx
3661  { 453, 7, 1, 368, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo118,0,nullptr }, // Inst #453 = STRr_preidx
3662  { 454, 6, 0, 362, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x380ULL, nullptr, nullptr, OperandInfo67,0,nullptr }, // Inst #454 = STRrs
3663  { 455, 3, 0, 76, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x0ULL, nullptr, nullptr, OperandInfo22,0,nullptr }, // Inst #455 = SUBS_PC_LR
3664  { 456, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo17,0,nullptr }, // Inst #456 = SUBSri
3665  { 457, 5, 1, 2, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo18,0,nullptr }, // Inst #457 = SUBSrr
3666  { 458, 6, 1, 3, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo19,0,nullptr }, // Inst #458 = SUBSrsi
3667  { 459, 7, 1, 5, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo20,0,nullptr }, // Inst #459 = SUBSrsr
3668  { 460, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo13,0,nullptr }, // Inst #460 = SUBri
3669  { 461, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo14,0,nullptr }, // Inst #461 = SUBrr
3670  { 462, 7, 1, 3, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo15,0,nullptr }, // Inst #462 = SUBrsi
3671  { 463, 8, 1, 4, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo21,0,nullptr }, // Inst #463 = SUBrsr
3672  { 464, 3, 0, 10, 4, 0|(1<<MCID_Call)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, ImplicitList2, nullptr, OperandInfo48,0,nullptr }, // Inst #464 = SVC
3673  { 465, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #465 = SWP
3674  { 466, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo123,0,nullptr }, // Inst #466 = SWPB
3675  { 467, 6, 1, 304, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #467 = SXTAB
3676  { 468, 6, 1, 304, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x700ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #468 = SXTAB16
3677  { 469, 6, 1, 304, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #469 = SXTAH
3678  { 470, 5, 1, 290, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #470 = SXTB
3679  { 471, 5, 1, 290, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x700ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #471 = SXTB16
3680  { 472, 5, 1, 290, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #472 = SXTH
3681  { 473, 1, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo28,0,nullptr }, // Inst #473 = TAILJMPd
3682  { 474, 1, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo126,0,nullptr }, // Inst #474 = TAILJMPr
3683  { 475, 1, 0, 10, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo2,0,nullptr }, // Inst #475 = TCRETURNdi
3684  { 476, 1, 0, 10, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Terminator), 0x0ULL, ImplicitList2, nullptr, OperandInfo126,0,nullptr }, // Inst #476 = TCRETURNri
3685  { 477, 4, 0, 79, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo24,0,nullptr }, // Inst #477 = TEQri
3686  { 478, 4, 0, 80, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x201ULL, nullptr, ImplicitList1, OperandInfo43,0,nullptr }, // Inst #478 = TEQrr
3687  { 479, 5, 0, 81, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x1501ULL, nullptr, ImplicitList1, OperandInfo44,0,nullptr }, // Inst #479 = TEQrsi
3688  { 480, 6, 0, 82, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x281ULL, nullptr, ImplicitList1, OperandInfo45,0,nullptr }, // Inst #480 = TEQrsr
3689  { 481, 0, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList9, nullptr,0,nullptr }, // Inst #481 = TPsoft
3690  { 482, 0, 0, 0, 4, 0|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #482 = TRAP
3691  { 483, 0, 0, 0, 4, 0|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #483 = TRAPNaCl
3692  { 484, 4, 0, 79, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x201ULL, nullptr, ImplicitList1, OperandInfo24,0,nullptr }, // Inst #484 = TSTri
3693  { 485, 4, 0, 80, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x201ULL, nullptr, ImplicitList1, OperandInfo43,0,nullptr }, // Inst #485 = TSTrr
3694  { 486, 5, 0, 81, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x1501ULL, nullptr, ImplicitList1, OperandInfo44,0,nullptr }, // Inst #486 = TSTrsi
3695  { 487, 6, 0, 82, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x281ULL, nullptr, ImplicitList1, OperandInfo45,0,nullptr }, // Inst #487 = TSTrsr
3696  { 488, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #488 = UADD16
3697  { 489, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #489 = UADD8
3698  { 490, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #490 = UASX
3699  { 491, 6, 1, 278, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x201ULL, nullptr, nullptr, OperandInfo102,0,nullptr }, // Inst #491 = UBFX
3700  { 492, 1, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #492 = UDF
3701  { 493, 5, 1, 324, 4, 0|(1<<MCID_Predicable), 0x600ULL, nullptr, nullptr, OperandInfo18,0,nullptr }, // Inst #493 = UDIV
3702  { 494, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #494 = UHADD16
3703  { 495, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #495 = UHADD8
3704  { 496, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #496 = UHASX
3705  { 497, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #497 = UHSAX
3706  { 498, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #498 = UHSUB16
3707  { 499, 5, 1, 303, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #499 = UHSUB8
3708  { 500, 6, 2, 281, 4, 0|(1<<MCID_Predicable), 0x80ULL, nullptr, nullptr, OperandInfo76,0,nullptr }, // Inst #500 = UMAAL
3709  { 501, 9, 2, 281, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo105,0,nullptr }, // Inst #501 = UMLAL
3710  { 502, 9, 2, 281, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo107,0,nullptr }, // Inst #502 = UMLALv5
3711  { 503, 7, 2, 321, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo108,0,nullptr }, // Inst #503 = UMULL
3712  { 504, 7, 2, 282, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo109,0,nullptr }, // Inst #504 = UMULLv5
3713  { 505, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #505 = UQADD16
3714  { 506, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #506 = UQADD8
3715  { 507, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #507 = UQASX
3716  { 508, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #508 = UQSAX
3717  { 509, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #509 = UQSUB16
3718  { 510, 5, 1, 299, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #510 = UQSUB8
3719  { 511, 5, 1, 307, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo18,0,nullptr }, // Inst #511 = USAD8
3720  { 512, 6, 1, 308, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, nullptr, nullptr, OperandInfo76,0,nullptr }, // Inst #512 = USADA8
3721  { 513, 6, 1, 300, 4, 0|(1<<MCID_Predicable), 0x680ULL, nullptr, nullptr, OperandInfo111,0,nullptr }, // Inst #513 = USAT
3722  { 514, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x680ULL, nullptr, nullptr, OperandInfo112,0,nullptr }, // Inst #514 = USAT16
3723  { 515, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #515 = USAX
3724  { 516, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #516 = USUB16
3725  { 517, 5, 1, 301, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, nullptr, nullptr, OperandInfo101,0,nullptr }, // Inst #517 = USUB8
3726  { 518, 6, 1, 304, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #518 = UXTAB
3727  { 519, 6, 1, 304, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x700ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #519 = UXTAB16
3728  { 520, 6, 1, 304, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo124,0,nullptr }, // Inst #520 = UXTAH
3729  { 521, 5, 1, 290, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #521 = UXTB
3730  { 522, 5, 1, 290, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #522 = UXTB16
3731  { 523, 5, 1, 290, 4, 0|(1<<MCID_Predicable), 0x700ULL, nullptr, nullptr, OperandInfo125,0,nullptr }, // Inst #523 = UXTH
3732  { 524, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #524 = VABALsv2i64
3733  { 525, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #525 = VABALsv4i32
3734  { 526, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #526 = VABALsv8i16
3735  { 527, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #527 = VABALuv2i64
3736  { 528, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #528 = VABALuv4i32
3737  { 529, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #529 = VABALuv8i16
3738  { 530, 6, 1, 401, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #530 = VABAsv16i8
3739  { 531, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #531 = VABAsv2i32
3740  { 532, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #532 = VABAsv4i16
3741  { 533, 6, 1, 401, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #533 = VABAsv4i32
3742  { 534, 6, 1, 401, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #534 = VABAsv8i16
3743  { 535, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #535 = VABAsv8i8
3744  { 536, 6, 1, 401, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #536 = VABAuv16i8
3745  { 537, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #537 = VABAuv2i32
3746  { 538, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #538 = VABAuv4i16
3747  { 539, 6, 1, 401, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #539 = VABAuv4i32
3748  { 540, 6, 1, 401, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #540 = VABAuv8i16
3749  { 541, 6, 1, 400, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #541 = VABAuv8i8
3750  { 542, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #542 = VABDLsv2i64
3751  { 543, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #543 = VABDLsv4i32
3752  { 544, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #544 = VABDLsv8i16
3753  { 545, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #545 = VABDLuv2i64
3754  { 546, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #546 = VABDLuv4i32
3755  { 547, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #547 = VABDLuv8i16
3756  { 548, 5, 1, 442, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #548 = VABDfd
3757  { 549, 5, 1, 443, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #549 = VABDfq
3758  { 550, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #550 = VABDsv16i8
3759  { 551, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #551 = VABDsv2i32
3760  { 552, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #552 = VABDsv4i16
3761  { 553, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #553 = VABDsv4i32
3762  { 554, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #554 = VABDsv8i16
3763  { 555, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #555 = VABDsv8i8
3764  { 556, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #556 = VABDuv16i8
3765  { 557, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #557 = VABDuv2i32
3766  { 558, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #558 = VABDuv4i16
3767  { 559, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #559 = VABDuv4i32
3768  { 560, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #560 = VABDuv8i16
3769  { 561, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #561 = VABDuv8i8
3770  { 562, 4, 1, 437, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #562 = VABSD
3771  { 563, 4, 1, 438, 4, 0|(1<<MCID_Predicable), 0x28780ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #563 = VABSS
3772  { 564, 4, 1, 402, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #564 = VABSfd
3773  { 565, 4, 1, 403, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #565 = VABSfq
3774  { 566, 4, 1, 404, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #566 = VABSv16i8
3775  { 567, 4, 1, 405, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #567 = VABSv2i32
3776  { 568, 4, 1, 405, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #568 = VABSv4i16
3777  { 569, 4, 1, 404, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #569 = VABSv4i32
3778  { 570, 4, 1, 404, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #570 = VABSv8i16
3779  { 571, 4, 1, 405, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #571 = VABSv8i8
3780  { 572, 5, 1, 406, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #572 = VACGEd
3781  { 573, 5, 1, 407, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #573 = VACGEq
3782  { 574, 5, 1, 406, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #574 = VACGTd
3783  { 575, 5, 1, 407, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #575 = VACGTq
3784  { 576, 5, 1, 448, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #576 = VADDD
3785  { 577, 5, 1, 421, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136,0,nullptr }, // Inst #577 = VADDHNv2i32
3786  { 578, 5, 1, 421, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136,0,nullptr }, // Inst #578 = VADDHNv4i16
3787  { 579, 5, 1, 421, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136,0,nullptr }, // Inst #579 = VADDHNv8i8
3788  { 580, 5, 1, 379, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #580 = VADDLsv2i64
3789  { 581, 5, 1, 379, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #581 = VADDLsv4i32
3790  { 582, 5, 1, 379, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #582 = VADDLsv8i16
3791  { 583, 5, 1, 379, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #583 = VADDLuv2i64
3792  { 584, 5, 1, 379, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #584 = VADDLuv4i32
3793  { 585, 5, 1, 379, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #585 = VADDLuv8i16
3794  { 586, 5, 1, 445, 4, 0|(1<<MCID_Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo137,0,nullptr }, // Inst #586 = VADDS
3795  { 587, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo138,0,nullptr }, // Inst #587 = VADDWsv2i64
3796  { 588, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo138,0,nullptr }, // Inst #588 = VADDWsv4i32
3797  { 589, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo138,0,nullptr }, // Inst #589 = VADDWsv8i16
3798  { 590, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo138,0,nullptr }, // Inst #590 = VADDWuv2i64
3799  { 591, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo138,0,nullptr }, // Inst #591 = VADDWuv4i32
3800  { 592, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo138,0,nullptr }, // Inst #592 = VADDWuv8i16
3801  { 593, 5, 1, 442, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #593 = VADDfd
3802  { 594, 5, 1, 443, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #594 = VADDfq
3803  { 595, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #595 = VADDv16i8
3804  { 596, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #596 = VADDv1i64
3805  { 597, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #597 = VADDv2i32
3806  { 598, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #598 = VADDv2i64
3807  { 599, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #599 = VADDv4i16
3808  { 600, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #600 = VADDv4i32
3809  { 601, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #601 = VADDv8i16
3810  { 602, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #602 = VADDv8i8
3811  { 603, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #603 = VANDd
3812  { 604, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #604 = VANDq
3813  { 605, 5, 1, 382, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #605 = VBICd
3814  { 606, 5, 1, 383, 4, 0|(1<<MCID_Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #606 = VBICiv2i32
3815  { 607, 5, 1, 383, 4, 0|(1<<MCID_Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #607 = VBICiv4i16
3816  { 608, 5, 1, 383, 4, 0|(1<<MCID_Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo140,0,nullptr }, // Inst #608 = VBICiv4i32
3817  { 609, 5, 1, 383, 4, 0|(1<<MCID_Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo140,0,nullptr }, // Inst #609 = VBICiv8i16
3818  { 610, 5, 1, 381, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #610 = VBICq
3819  { 611, 6, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #611 = VBIFd
3820  { 612, 6, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #612 = VBIFq
3821  { 613, 6, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #613 = VBITd
3822  { 614, 6, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #614 = VBITq
3823  { 615, 6, 1, 384, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #615 = VBSLd
3824  { 616, 6, 1, 385, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #616 = VBSLq
3825  { 617, 5, 1, 406, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #617 = VCEQfd
3826  { 618, 5, 1, 407, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #618 = VCEQfq
3827  { 619, 5, 1, 408, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #619 = VCEQv16i8
3828  { 620, 5, 1, 409, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #620 = VCEQv2i32
3829  { 621, 5, 1, 409, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #621 = VCEQv4i16
3830  { 622, 5, 1, 408, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #622 = VCEQv4i32
3831  { 623, 5, 1, 408, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #623 = VCEQv8i16
3832  { 624, 5, 1, 409, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #624 = VCEQv8i8
3833  { 625, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #625 = VCEQzv16i8
3834  { 626, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #626 = VCEQzv2f32
3835  { 627, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #627 = VCEQzv2i32
3836  { 628, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #628 = VCEQzv4f32
3837  { 629, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #629 = VCEQzv4i16
3838  { 630, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #630 = VCEQzv4i32
3839  { 631, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #631 = VCEQzv8i16
3840  { 632, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #632 = VCEQzv8i8
3841  { 633, 5, 1, 406, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #633 = VCGEfd
3842  { 634, 5, 1, 407, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #634 = VCGEfq
3843  { 635, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #635 = VCGEsv16i8
3844  { 636, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #636 = VCGEsv2i32
3845  { 637, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #637 = VCGEsv4i16
3846  { 638, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #638 = VCGEsv4i32
3847  { 639, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #639 = VCGEsv8i16
3848  { 640, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #640 = VCGEsv8i8
3849  { 641, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #641 = VCGEuv16i8
3850  { 642, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #642 = VCGEuv2i32
3851  { 643, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #643 = VCGEuv4i16
3852  { 644, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #644 = VCGEuv4i32
3853  { 645, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #645 = VCGEuv8i16
3854  { 646, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #646 = VCGEuv8i8
3855  { 647, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #647 = VCGEzv16i8
3856  { 648, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #648 = VCGEzv2f32
3857  { 649, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #649 = VCGEzv2i32
3858  { 650, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #650 = VCGEzv4f32
3859  { 651, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #651 = VCGEzv4i16
3860  { 652, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #652 = VCGEzv4i32
3861  { 653, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #653 = VCGEzv8i16
3862  { 654, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #654 = VCGEzv8i8
3863  { 655, 5, 1, 406, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #655 = VCGTfd
3864  { 656, 5, 1, 407, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #656 = VCGTfq
3865  { 657, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #657 = VCGTsv16i8
3866  { 658, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #658 = VCGTsv2i32
3867  { 659, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #659 = VCGTsv4i16
3868  { 660, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #660 = VCGTsv4i32
3869  { 661, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #661 = VCGTsv8i16
3870  { 662, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #662 = VCGTsv8i8
3871  { 663, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #663 = VCGTuv16i8
3872  { 664, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #664 = VCGTuv2i32
3873  { 665, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #665 = VCGTuv4i16
3874  { 666, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #666 = VCGTuv4i32
3875  { 667, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #667 = VCGTuv8i16
3876  { 668, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #668 = VCGTuv8i8
3877  { 669, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #669 = VCGTzv16i8
3878  { 670, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #670 = VCGTzv2f32
3879  { 671, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #671 = VCGTzv2i32
3880  { 672, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #672 = VCGTzv4f32
3881  { 673, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #673 = VCGTzv4i16
3882  { 674, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #674 = VCGTzv4i32
3883  { 675, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #675 = VCGTzv8i16
3884  { 676, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #676 = VCGTzv8i8
3885  { 677, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #677 = VCLEzv16i8
3886  { 678, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #678 = VCLEzv2f32
3887  { 679, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #679 = VCLEzv2i32
3888  { 680, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #680 = VCLEzv4f32
3889  { 681, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #681 = VCLEzv4i16
3890  { 682, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #682 = VCLEzv4i32
3891  { 683, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #683 = VCLEzv8i16
3892  { 684, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #684 = VCLEzv8i8
3893  { 685, 4, 1, 385, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #685 = VCLSv16i8
3894  { 686, 4, 1, 384, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #686 = VCLSv2i32
3895  { 687, 4, 1, 384, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #687 = VCLSv4i16
3896  { 688, 4, 1, 385, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #688 = VCLSv4i32
3897  { 689, 4, 1, 385, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #689 = VCLSv8i16
3898  { 690, 4, 1, 384, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #690 = VCLSv8i8
3899  { 691, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #691 = VCLTzv16i8
3900  { 692, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #692 = VCLTzv2f32
3901  { 693, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #693 = VCLTzv2i32
3902  { 694, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #694 = VCLTzv4f32
3903  { 695, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #695 = VCLTzv4i16
3904  { 696, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #696 = VCLTzv4i32
3905  { 697, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #697 = VCLTzv8i16
3906  { 698, 4, 1, 410, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #698 = VCLTzv8i8
3907  { 699, 4, 1, 385, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #699 = VCLZv16i8
3908  { 700, 4, 1, 384, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #700 = VCLZv2i32
3909  { 701, 4, 1, 384, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #701 = VCLZv4i16
3910  { 702, 4, 1, 385, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #702 = VCLZv4i32
3911  { 703, 4, 1, 385, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #703 = VCLZv8i16
3912  { 704, 4, 1, 384, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #704 = VCLZv8i8
3913  { 705, 4, 0, 439, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, ImplicitList5, OperandInfo133,0,nullptr }, // Inst #705 = VCMPD
3914  { 706, 4, 0, 439, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, ImplicitList5, OperandInfo133,0,nullptr }, // Inst #706 = VCMPED
3915  { 707, 4, 0, 440, 4, 0|(1<<MCID_Predicable), 0x28780ULL, nullptr, ImplicitList5, OperandInfo134,0,nullptr }, // Inst #707 = VCMPES
3916  { 708, 3, 0, 439, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, ImplicitList5, OperandInfo141,0,nullptr }, // Inst #708 = VCMPEZD
3917  { 709, 3, 0, 440, 4, 0|(1<<MCID_Predicable), 0x28780ULL, nullptr, ImplicitList5, OperandInfo142,0,nullptr }, // Inst #709 = VCMPEZS
3918  { 710, 4, 0, 440, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28780ULL, nullptr, ImplicitList5, OperandInfo134,0,nullptr }, // Inst #710 = VCMPS
3919  { 711, 3, 0, 439, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, ImplicitList5, OperandInfo141,0,nullptr }, // Inst #711 = VCMPZD
3920  { 712, 3, 0, 440, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28780ULL, nullptr, ImplicitList5, OperandInfo142,0,nullptr }, // Inst #712 = VCMPZS
3921  { 713, 4, 1, 384, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #713 = VCNTd
3922  { 714, 4, 1, 385, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #714 = VCNTq
3923  { 715, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #715 = VCVTANSD
3924  { 716, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #716 = VCVTANSQ
3925  { 717, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #717 = VCVTANUD
3926  { 718, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #718 = VCVTANUQ
3927  { 719, 2, 1, 474, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #719 = VCVTASD
3928  { 720, 2, 1, 474, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #720 = VCVTASS
3929  { 721, 2, 1, 474, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #721 = VCVTAUD
3930  { 722, 2, 1, 474, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #722 = VCVTAUS
3931  { 723, 4, 1, 474, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #723 = VCVTBDH
3932  { 724, 4, 1, 474, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo147,0,nullptr }, // Inst #724 = VCVTBHD
3933  { 725, 4, 1, 475, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #725 = VCVTBHS
3934  { 726, 4, 1, 476, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #726 = VCVTBSH
3935  { 727, 4, 1, 477, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo147,0,nullptr }, // Inst #727 = VCVTDS
3936  { 728, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #728 = VCVTMNSD
3937  { 729, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #729 = VCVTMNSQ
3938  { 730, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #730 = VCVTMNUD
3939  { 731, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #731 = VCVTMNUQ
3940  { 732, 2, 1, 474, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #732 = VCVTMSD
3941  { 733, 2, 1, 474, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #733 = VCVTMSS
3942  { 734, 2, 1, 474, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #734 = VCVTMUD
3943  { 735, 2, 1, 474, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #735 = VCVTMUS
3944  { 736, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #736 = VCVTNNSD
3945  { 737, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #737 = VCVTNNSQ
3946  { 738, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #738 = VCVTNNUD
3947  { 739, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #739 = VCVTNNUQ
3948  { 740, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #740 = VCVTNSD
3949  { 741, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #741 = VCVTNSS
3950  { 742, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #742 = VCVTNUD
3951  { 743, 2, 1, 474, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #743 = VCVTNUS
3952  { 744, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #744 = VCVTPNSD
3953  { 745, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #745 = VCVTPNSQ
3954  { 746, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #746 = VCVTPNUD
3955  { 747, 2, 1, 474, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #747 = VCVTPNUQ
3956  { 748, 2, 1, 474, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #748 = VCVTPSD
3957  { 749, 2, 1, 474, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #749 = VCVTPSS
3958  { 750, 2, 1, 474, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo144,0,nullptr }, // Inst #750 = VCVTPUD
3959  { 751, 2, 1, 474, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #751 = VCVTPUS
3960  { 752, 4, 1, 478, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #752 = VCVTSD
3961  { 753, 4, 1, 474, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #753 = VCVTTDH
3962  { 754, 4, 1, 474, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo147,0,nullptr }, // Inst #754 = VCVTTHD
3963  { 755, 4, 1, 475, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #755 = VCVTTHS
3964  { 756, 4, 1, 476, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #756 = VCVTTSH
3965  { 757, 4, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo148,0,nullptr }, // Inst #757 = VCVTf2h
3966  { 758, 4, 1, 480, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #758 = VCVTf2sd
3967  { 759, 4, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #759 = VCVTf2sq
3968  { 760, 4, 1, 480, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #760 = VCVTf2ud
3969  { 761, 4, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #761 = VCVTf2uq
3970  { 762, 5, 1, 480, 4, 0|(1<<MCID_Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #762 = VCVTf2xsd
3971  { 763, 5, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #763 = VCVTf2xsq
3972  { 764, 5, 1, 480, 4, 0|(1<<MCID_Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #764 = VCVTf2xud
3973  { 765, 5, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #765 = VCVTf2xuq
3974  { 766, 4, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo151,0,nullptr }, // Inst #766 = VCVTh2f
3975  { 767, 4, 1, 480, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #767 = VCVTs2fd
3976  { 768, 4, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #768 = VCVTs2fq
3977  { 769, 4, 1, 480, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #769 = VCVTu2fd
3978  { 770, 4, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #770 = VCVTu2fq
3979  { 771, 5, 1, 480, 4, 0|(1<<MCID_Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #771 = VCVTxs2fd
3980  { 772, 5, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #772 = VCVTxs2fq
3981  { 773, 5, 1, 480, 4, 0|(1<<MCID_Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #773 = VCVTxu2fd
3982  { 774, 5, 1, 479, 4, 0|(1<<MCID_Predicable), 0x11080ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #774 = VCVTxu2fq
3983  { 775, 5, 1, 588, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #775 = VDIVD
3984  { 776, 5, 1, 586, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo137,0,nullptr }, // Inst #776 = VDIVS
3985  { 777, 4, 1, 496, 4, 0|(1<<MCID_Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo152,0,nullptr }, // Inst #777 = VDUP16d
3986  { 778, 4, 1, 496, 4, 0|(1<<MCID_Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo153,0,nullptr }, // Inst #778 = VDUP16q
3987  { 779, 4, 1, 496, 4, 0|(1<<MCID_Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo152,0,nullptr }, // Inst #779 = VDUP32d
3988  { 780, 4, 1, 496, 4, 0|(1<<MCID_Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo153,0,nullptr }, // Inst #780 = VDUP32q
3989  { 781, 4, 1, 496, 4, 0|(1<<MCID_Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo152,0,nullptr }, // Inst #781 = VDUP8d
3990  { 782, 4, 1, 496, 4, 0|(1<<MCID_Predicable), 0x10e80ULL, nullptr, nullptr, OperandInfo153,0,nullptr }, // Inst #782 = VDUP8q
3991  { 783, 5, 1, 494, 4, 0|(1<<MCID_Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #783 = VDUPLN16d
3992  { 784, 5, 1, 495, 4, 0|(1<<MCID_Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #784 = VDUPLN16q
3993  { 785, 5, 1, 494, 4, 0|(1<<MCID_Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #785 = VDUPLN32d
3994  { 786, 5, 1, 495, 4, 0|(1<<MCID_Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #786 = VDUPLN32q
3995  { 787, 5, 1, 494, 4, 0|(1<<MCID_Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #787 = VDUPLN8d
3996  { 788, 5, 1, 495, 4, 0|(1<<MCID_Predicable), 0x11100ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #788 = VDUPLN8q
3997  { 789, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #789 = VEORd
3998  { 790, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #790 = VEORq
3999  { 791, 6, 1, 396, 4, 0|(1<<MCID_Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #791 = VEXTd16
4000  { 792, 6, 1, 396, 4, 0|(1<<MCID_Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #792 = VEXTd32
4001  { 793, 6, 1, 396, 4, 0|(1<<MCID_Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo155,0,nullptr }, // Inst #793 = VEXTd8
4002  { 794, 6, 1, 397, 4, 0|(1<<MCID_Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #794 = VEXTq16
4003  { 795, 6, 1, 397, 4, 0|(1<<MCID_Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #795 = VEXTq32
4004  { 796, 6, 1, 397, 4, 0|(1<<MCID_Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #796 = VEXTq64
4005  { 797, 6, 1, 397, 4, 0|(1<<MCID_Predicable), 0x11380ULL, nullptr, nullptr, OperandInfo156,0,nullptr }, // Inst #797 = VEXTq8
4006  { 798, 6, 1, 462, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #798 = VFMAD
4007  { 799, 6, 1, 463, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #799 = VFMAS
4008  { 800, 6, 1, 472, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #800 = VFMAfd
4009  { 801, 6, 1, 473, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #801 = VFMAfq
4010  { 802, 6, 1, 462, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #802 = VFMSD
4011  { 803, 6, 1, 463, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #803 = VFMSS
4012  { 804, 6, 1, 472, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #804 = VFMSfd
4013  { 805, 6, 1, 473, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #805 = VFMSfq
4014  { 806, 6, 1, 462, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #806 = VFNMAD
4015  { 807, 6, 1, 463, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #807 = VFNMAS
4016  { 808, 6, 1, 462, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #808 = VFNMSD
4017  { 809, 6, 1, 463, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #809 = VFNMSS
4018  { 810, 5, 1, 503, 4, 0|(1<<MCID_Predicable), 0x10d80ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #810 = VGETLNi32
4019  { 811, 5, 1, 504, 4, 0|(1<<MCID_Predicable), 0x10d80ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #811 = VGETLNs16
4020  { 812, 5, 1, 504, 4, 0|(1<<MCID_Predicable), 0x10d80ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #812 = VGETLNs8
4021  { 813, 5, 1, 503, 4, 0|(1<<MCID_Predicable), 0x10d80ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #813 = VGETLNu16
4022  { 814, 5, 1, 503, 4, 0|(1<<MCID_Predicable), 0x10d80ULL, nullptr, nullptr, OperandInfo158,0,nullptr }, // Inst #814 = VGETLNu8
4023  { 815, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #815 = VHADDsv16i8
4024  { 816, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #816 = VHADDsv2i32
4025  { 817, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #817 = VHADDsv4i16
4026  { 818, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #818 = VHADDsv4i32
4027  { 819, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #819 = VHADDsv8i16
4028  { 820, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #820 = VHADDsv8i8
4029  { 821, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #821 = VHADDuv16i8
4030  { 822, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #822 = VHADDuv2i32
4031  { 823, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #823 = VHADDuv4i16
4032  { 824, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #824 = VHADDuv4i32
4033  { 825, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #825 = VHADDuv8i16
4034  { 826, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #826 = VHADDuv8i8
4035  { 827, 5, 1, 388, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #827 = VHSUBsv16i8
4036  { 828, 5, 1, 389, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #828 = VHSUBsv2i32
4037  { 829, 5, 1, 389, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #829 = VHSUBsv4i16
4038  { 830, 5, 1, 388, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #830 = VHSUBsv4i32
4039  { 831, 5, 1, 388, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #831 = VHSUBsv8i16
4040  { 832, 5, 1, 389, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #832 = VHSUBsv8i8
4041  { 833, 5, 1, 388, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #833 = VHSUBuv16i8
4042  { 834, 5, 1, 389, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #834 = VHSUBuv2i32
4043  { 835, 5, 1, 389, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #835 = VHSUBuv4i16
4044  { 836, 5, 1, 388, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #836 = VHSUBuv4i32
4045  { 837, 5, 1, 388, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #837 = VHSUBuv8i16
4046  { 838, 5, 1, 389, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #838 = VHSUBuv8i8
4047  { 839, 5, 1, 538, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #839 = VLD1DUPd16
4048  { 840, 6, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #840 = VLD1DUPd16wb_fixed
4049  { 841, 7, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #841 = VLD1DUPd16wb_register
4050  { 842, 5, 1, 538, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #842 = VLD1DUPd32
4051  { 843, 6, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #843 = VLD1DUPd32wb_fixed
4052  { 844, 7, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #844 = VLD1DUPd32wb_register
4053  { 845, 5, 1, 538, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #845 = VLD1DUPd8
4054  { 846, 6, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #846 = VLD1DUPd8wb_fixed
4055  { 847, 7, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #847 = VLD1DUPd8wb_register
4056  { 848, 5, 1, 538, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #848 = VLD1DUPq16
4057  { 849, 6, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #849 = VLD1DUPq16wb_fixed
4058  { 850, 7, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #850 = VLD1DUPq16wb_register
4059  { 851, 5, 1, 538, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #851 = VLD1DUPq32
4060  { 852, 6, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #852 = VLD1DUPq32wb_fixed
4061  { 853, 7, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #853 = VLD1DUPq32wb_register
4062  { 854, 5, 1, 538, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #854 = VLD1DUPq8
4063  { 855, 6, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #855 = VLD1DUPq8wb_fixed
4064  { 856, 7, 2, 540, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #856 = VLD1DUPq8wb_register
4065  { 857, 7, 1, 539, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo165,0,nullptr }, // Inst #857 = VLD1LNd16
4066  { 858, 9, 2, 541, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166,0,nullptr }, // Inst #858 = VLD1LNd16_UPD
4067  { 859, 7, 1, 539, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo165,0,nullptr }, // Inst #859 = VLD1LNd32
4068  { 860, 9, 2, 541, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166,0,nullptr }, // Inst #860 = VLD1LNd32_UPD
4069  { 861, 7, 1, 539, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo165,0,nullptr }, // Inst #861 = VLD1LNd8
4070  { 862, 9, 2, 541, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo166,0,nullptr }, // Inst #862 = VLD1LNd8_UPD
4071  { 863, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #863 = VLD1LNdAsm_16
4072  { 864, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #864 = VLD1LNdAsm_32
4073  { 865, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #865 = VLD1LNdAsm_8
4074  { 866, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #866 = VLD1LNdWB_fixed_Asm_16
4075  { 867, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #867 = VLD1LNdWB_fixed_Asm_32
4076  { 868, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #868 = VLD1LNdWB_fixed_Asm_8
4077  { 869, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #869 = VLD1LNdWB_register_Asm_16
4078  { 870, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #870 = VLD1LNdWB_register_Asm_32
4079  { 871, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #871 = VLD1LNdWB_register_Asm_8
4080  { 872, 7, 1, 539, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo169,0,nullptr }, // Inst #872 = VLD1LNq16Pseudo
4081  { 873, 9, 2, 541, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo170,0,nullptr }, // Inst #873 = VLD1LNq16Pseudo_UPD
4082  { 874, 7, 1, 539, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo169,0,nullptr }, // Inst #874 = VLD1LNq32Pseudo
4083  { 875, 9, 2, 541, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo170,0,nullptr }, // Inst #875 = VLD1LNq32Pseudo_UPD
4084  { 876, 7, 1, 539, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo169,0,nullptr }, // Inst #876 = VLD1LNq8Pseudo
4085  { 877, 9, 2, 541, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo170,0,nullptr }, // Inst #877 = VLD1LNq8Pseudo_UPD
4086  { 878, 5, 1, 518, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #878 = VLD1d16
4087  { 879, 5, 1, 524, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #879 = VLD1d16Q
4088  { 880, 6, 2, 525, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #880 = VLD1d16Qwb_fixed
4089  { 881, 7, 2, 525, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #881 = VLD1d16Qwb_register
4090  { 882, 5, 1, 522, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #882 = VLD1d16T
4091  { 883, 6, 2, 523, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #883 = VLD1d16Twb_fixed
4092  { 884, 7, 2, 523, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #884 = VLD1d16Twb_register
4093  { 885, 6, 2, 520, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #885 = VLD1d16wb_fixed
4094  { 886, 7, 2, 520, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #886 = VLD1d16wb_register
4095  { 887, 5, 1, 518, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #887 = VLD1d32
4096  { 888, 5, 1, 524, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #888 = VLD1d32Q
4097  { 889, 6, 2, 525, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #889 = VLD1d32Qwb_fixed
4098  { 890, 7, 2, 525, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #890 = VLD1d32Qwb_register
4099  { 891, 5, 1, 522, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #891 = VLD1d32T
4100  { 892, 6, 2, 523, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #892 = VLD1d32Twb_fixed
4101  { 893, 7, 2, 523, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #893 = VLD1d32Twb_register
4102  { 894, 6, 2, 520, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #894 = VLD1d32wb_fixed
4103  { 895, 7, 2, 520, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #895 = VLD1d32wb_register
4104  { 896, 5, 1, 518, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #896 = VLD1d64
4105  { 897, 5, 1, 524, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #897 = VLD1d64Q
4106  { 898, 5, 1, 524, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #898 = VLD1d64QPseudo
4107  { 899, 6, 2, 524, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo172,0,nullptr }, // Inst #899 = VLD1d64QPseudoWB_fixed
4108  { 900, 7, 2, 524, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo173,0,nullptr }, // Inst #900 = VLD1d64QPseudoWB_register
4109  { 901, 6, 2, 525, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #901 = VLD1d64Qwb_fixed
4110  { 902, 7, 2, 525, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #902 = VLD1d64Qwb_register
4111  { 903, 5, 1, 522, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #903 = VLD1d64T
4112  { 904, 5, 1, 522, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #904 = VLD1d64TPseudo
4113  { 905, 6, 2, 522, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo172,0,nullptr }, // Inst #905 = VLD1d64TPseudoWB_fixed
4114  { 906, 7, 2, 522, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo173,0,nullptr }, // Inst #906 = VLD1d64TPseudoWB_register
4115  { 907, 6, 2, 523, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #907 = VLD1d64Twb_fixed
4116  { 908, 7, 2, 523, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #908 = VLD1d64Twb_register
4117  { 909, 6, 2, 520, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #909 = VLD1d64wb_fixed
4118  { 910, 7, 2, 520, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #910 = VLD1d64wb_register
4119  { 911, 5, 1, 518, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #911 = VLD1d8
4120  { 912, 5, 1, 524, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #912 = VLD1d8Q
4121  { 913, 6, 2, 525, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #913 = VLD1d8Qwb_fixed
4122  { 914, 7, 2, 525, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #914 = VLD1d8Qwb_register
4123  { 915, 5, 1, 522, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #915 = VLD1d8T
4124  { 916, 6, 2, 523, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #916 = VLD1d8Twb_fixed
4125  { 917, 7, 2, 523, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #917 = VLD1d8Twb_register
4126  { 918, 6, 2, 520, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #918 = VLD1d8wb_fixed
4127  { 919, 7, 2, 520, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #919 = VLD1d8wb_register
4128  { 920, 5, 1, 519, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #920 = VLD1q16
4129  { 921, 6, 2, 521, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #921 = VLD1q16wb_fixed
4130  { 922, 7, 2, 521, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #922 = VLD1q16wb_register
4131  { 923, 5, 1, 519, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #923 = VLD1q32
4132  { 924, 6, 2, 521, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #924 = VLD1q32wb_fixed
4133  { 925, 7, 2, 521, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #925 = VLD1q32wb_register
4134  { 926, 5, 1, 519, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #926 = VLD1q64
4135  { 927, 6, 2, 521, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #927 = VLD1q64wb_fixed
4136  { 928, 7, 2, 521, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #928 = VLD1q64wb_register
4137  { 929, 5, 1, 519, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #929 = VLD1q8
4138  { 930, 6, 2, 521, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #930 = VLD1q8wb_fixed
4139  { 931, 7, 2, 521, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #931 = VLD1q8wb_register
4140  { 932, 5, 1, 542, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #932 = VLD2DUPd16
4141  { 933, 6, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #933 = VLD2DUPd16wb_fixed
4142  { 934, 7, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #934 = VLD2DUPd16wb_register
4143  { 935, 5, 1, 542, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #935 = VLD2DUPd16x2
4144  { 936, 6, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #936 = VLD2DUPd16x2wb_fixed
4145  { 937, 7, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #937 = VLD2DUPd16x2wb_register
4146  { 938, 5, 1, 542, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #938 = VLD2DUPd32
4147  { 939, 6, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #939 = VLD2DUPd32wb_fixed
4148  { 940, 7, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #940 = VLD2DUPd32wb_register
4149  { 941, 5, 1, 542, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #941 = VLD2DUPd32x2
4150  { 942, 6, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #942 = VLD2DUPd32x2wb_fixed
4151  { 943, 7, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #943 = VLD2DUPd32x2wb_register
4152  { 944, 5, 1, 542, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #944 = VLD2DUPd8
4153  { 945, 6, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #945 = VLD2DUPd8wb_fixed
4154  { 946, 7, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #946 = VLD2DUPd8wb_register
4155  { 947, 5, 1, 542, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #947 = VLD2DUPd8x2
4156  { 948, 6, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #948 = VLD2DUPd8x2wb_fixed
4157  { 949, 7, 2, 545, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #949 = VLD2DUPd8x2wb_register
4158  { 950, 9, 2, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #950 = VLD2LNd16
4159  { 951, 7, 1, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo169,0,nullptr }, // Inst #951 = VLD2LNd16Pseudo
4160  { 952, 9, 2, 546, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo170,0,nullptr }, // Inst #952 = VLD2LNd16Pseudo_UPD
4161  { 953, 11, 3, 544, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #953 = VLD2LNd16_UPD
4162  { 954, 9, 2, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #954 = VLD2LNd32
4163  { 955, 7, 1, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo169,0,nullptr }, // Inst #955 = VLD2LNd32Pseudo
4164  { 956, 9, 2, 546, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo170,0,nullptr }, // Inst #956 = VLD2LNd32Pseudo_UPD
4165  { 957, 11, 3, 544, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #957 = VLD2LNd32_UPD
4166  { 958, 9, 2, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #958 = VLD2LNd8
4167  { 959, 7, 1, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo169,0,nullptr }, // Inst #959 = VLD2LNd8Pseudo
4168  { 960, 9, 2, 546, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo170,0,nullptr }, // Inst #960 = VLD2LNd8Pseudo_UPD
4169  { 961, 11, 3, 544, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #961 = VLD2LNd8_UPD
4170  { 962, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #962 = VLD2LNdAsm_16
4171  { 963, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #963 = VLD2LNdAsm_32
4172  { 964, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #964 = VLD2LNdAsm_8
4173  { 965, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #965 = VLD2LNdWB_fixed_Asm_16
4174  { 966, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #966 = VLD2LNdWB_fixed_Asm_32
4175  { 967, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #967 = VLD2LNdWB_fixed_Asm_8
4176  { 968, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #968 = VLD2LNdWB_register_Asm_16
4177  { 969, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #969 = VLD2LNdWB_register_Asm_32
4178  { 970, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #970 = VLD2LNdWB_register_Asm_8
4179  { 971, 9, 2, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #971 = VLD2LNq16
4180  { 972, 7, 1, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #972 = VLD2LNq16Pseudo
4181  { 973, 9, 2, 546, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #973 = VLD2LNq16Pseudo_UPD
4182  { 974, 11, 3, 544, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #974 = VLD2LNq16_UPD
4183  { 975, 9, 2, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo174,0,nullptr }, // Inst #975 = VLD2LNq32
4184  { 976, 7, 1, 543, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #976 = VLD2LNq32Pseudo
4185  { 977, 9, 2, 546, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #977 = VLD2LNq32Pseudo_UPD
4186  { 978, 11, 3, 544, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo175,0,nullptr }, // Inst #978 = VLD2LNq32_UPD
4187  { 979, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #979 = VLD2LNqAsm_16
4188  { 980, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #980 = VLD2LNqAsm_32
4189  { 981, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #981 = VLD2LNqWB_fixed_Asm_16
4190  { 982, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #982 = VLD2LNqWB_fixed_Asm_32
4191  { 983, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #983 = VLD2LNqWB_register_Asm_16
4192  { 984, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #984 = VLD2LNqWB_register_Asm_32
4193  { 985, 5, 1, 526, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #985 = VLD2b16
4194  { 986, 6, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #986 = VLD2b16wb_fixed
4195  { 987, 7, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #987 = VLD2b16wb_register
4196  { 988, 5, 1, 526, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #988 = VLD2b32
4197  { 989, 6, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #989 = VLD2b32wb_fixed
4198  { 990, 7, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #990 = VLD2b32wb_register
4199  { 991, 5, 1, 526, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #991 = VLD2b8
4200  { 992, 6, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #992 = VLD2b8wb_fixed
4201  { 993, 7, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #993 = VLD2b8wb_register
4202  { 994, 5, 1, 526, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #994 = VLD2d16
4203  { 995, 6, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #995 = VLD2d16wb_fixed
4204  { 996, 7, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #996 = VLD2d16wb_register
4205  { 997, 5, 1, 526, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #997 = VLD2d32
4206  { 998, 6, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #998 = VLD2d32wb_fixed
4207  { 999, 7, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #999 = VLD2d32wb_register
4208  { 1000, 5, 1, 526, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo162,0,nullptr }, // Inst #1000 = VLD2d8
4209  { 1001, 6, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo163,0,nullptr }, // Inst #1001 = VLD2d8wb_fixed
4210  { 1002, 7, 2, 528, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo164,0,nullptr }, // Inst #1002 = VLD2d8wb_register
4211  { 1003, 5, 1, 527, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1003 = VLD2q16
4212  { 1004, 5, 1, 527, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #1004 = VLD2q16Pseudo
4213  { 1005, 6, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo172,0,nullptr }, // Inst #1005 = VLD2q16PseudoWB_fixed
4214  { 1006, 7, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo173,0,nullptr }, // Inst #1006 = VLD2q16PseudoWB_register
4215  { 1007, 6, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #1007 = VLD2q16wb_fixed
4216  { 1008, 7, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #1008 = VLD2q16wb_register
4217  { 1009, 5, 1, 527, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1009 = VLD2q32
4218  { 1010, 5, 1, 527, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #1010 = VLD2q32Pseudo
4219  { 1011, 6, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo172,0,nullptr }, // Inst #1011 = VLD2q32PseudoWB_fixed
4220  { 1012, 7, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo173,0,nullptr }, // Inst #1012 = VLD2q32PseudoWB_register
4221  { 1013, 6, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #1013 = VLD2q32wb_fixed
4222  { 1014, 7, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #1014 = VLD2q32wb_register
4223  { 1015, 5, 1, 527, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1015 = VLD2q8
4224  { 1016, 5, 1, 527, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #1016 = VLD2q8Pseudo
4225  { 1017, 6, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo172,0,nullptr }, // Inst #1017 = VLD2q8PseudoWB_fixed
4226  { 1018, 7, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo173,0,nullptr }, // Inst #1018 = VLD2q8PseudoWB_register
4227  { 1019, 6, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo160,0,nullptr }, // Inst #1019 = VLD2q8wb_fixed
4228  { 1020, 7, 2, 529, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo161,0,nullptr }, // Inst #1020 = VLD2q8wb_register
4229  { 1021, 7, 3, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1021 = VLD3DUPd16
4230  { 1022, 5, 1, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #1022 = VLD3DUPd16Pseudo
4231  { 1023, 7, 2, 551, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1023 = VLD3DUPd16Pseudo_UPD
4232  { 1024, 9, 4, 549, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo180,0,nullptr }, // Inst #1024 = VLD3DUPd16_UPD
4233  { 1025, 7, 3, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1025 = VLD3DUPd32
4234  { 1026, 5, 1, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #1026 = VLD3DUPd32Pseudo
4235  { 1027, 7, 2, 551, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1027 = VLD3DUPd32Pseudo_UPD
4236  { 1028, 9, 4, 549, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo180,0,nullptr }, // Inst #1028 = VLD3DUPd32_UPD
4237  { 1029, 7, 3, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1029 = VLD3DUPd8
4238  { 1030, 5, 1, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #1030 = VLD3DUPd8Pseudo
4239  { 1031, 7, 2, 551, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1031 = VLD3DUPd8Pseudo_UPD
4240  { 1032, 9, 4, 549, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo180,0,nullptr }, // Inst #1032 = VLD3DUPd8_UPD
4241  { 1033, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1033 = VLD3DUPdAsm_16
4242  { 1034, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1034 = VLD3DUPdAsm_32
4243  { 1035, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1035 = VLD3DUPdAsm_8
4244  { 1036, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1036 = VLD3DUPdWB_fixed_Asm_16
4245  { 1037, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1037 = VLD3DUPdWB_fixed_Asm_32
4246  { 1038, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1038 = VLD3DUPdWB_fixed_Asm_8
4247  { 1039, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1039 = VLD3DUPdWB_register_Asm_16
4248  { 1040, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1040 = VLD3DUPdWB_register_Asm_32
4249  { 1041, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1041 = VLD3DUPdWB_register_Asm_8
4250  { 1042, 7, 3, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1042 = VLD3DUPq16
4251  { 1043, 9, 4, 549, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo180,0,nullptr }, // Inst #1043 = VLD3DUPq16_UPD
4252  { 1044, 7, 3, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1044 = VLD3DUPq32
4253  { 1045, 9, 4, 549, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo180,0,nullptr }, // Inst #1045 = VLD3DUPq32_UPD
4254  { 1046, 7, 3, 547, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1046 = VLD3DUPq8
4255  { 1047, 9, 4, 549, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo180,0,nullptr }, // Inst #1047 = VLD3DUPq8_UPD
4256  { 1048, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1048 = VLD3DUPqAsm_16
4257  { 1049, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1049 = VLD3DUPqAsm_32
4258  { 1050, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1050 = VLD3DUPqAsm_8
4259  { 1051, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1051 = VLD3DUPqWB_fixed_Asm_16
4260  { 1052, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1052 = VLD3DUPqWB_fixed_Asm_32
4261  { 1053, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1053 = VLD3DUPqWB_fixed_Asm_8
4262  { 1054, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1054 = VLD3DUPqWB_register_Asm_16
4263  { 1055, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1055 = VLD3DUPqWB_register_Asm_32
4264  { 1056, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1056 = VLD3DUPqWB_register_Asm_8
4265  { 1057, 11, 3, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1057 = VLD3LNd16
4266  { 1058, 7, 1, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1058 = VLD3LNd16Pseudo
4267  { 1059, 9, 2, 552, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1059 = VLD3LNd16Pseudo_UPD
4268  { 1060, 13, 4, 550, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo183,0,nullptr }, // Inst #1060 = VLD3LNd16_UPD
4269  { 1061, 11, 3, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1061 = VLD3LNd32
4270  { 1062, 7, 1, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1062 = VLD3LNd32Pseudo
4271  { 1063, 9, 2, 552, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1063 = VLD3LNd32Pseudo_UPD
4272  { 1064, 13, 4, 550, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo183,0,nullptr }, // Inst #1064 = VLD3LNd32_UPD
4273  { 1065, 11, 3, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1065 = VLD3LNd8
4274  { 1066, 7, 1, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1066 = VLD3LNd8Pseudo
4275  { 1067, 9, 2, 552, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1067 = VLD3LNd8Pseudo_UPD
4276  { 1068, 13, 4, 550, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo183,0,nullptr }, // Inst #1068 = VLD3LNd8_UPD
4277  { 1069, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1069 = VLD3LNdAsm_16
4278  { 1070, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1070 = VLD3LNdAsm_32
4279  { 1071, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1071 = VLD3LNdAsm_8
4280  { 1072, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1072 = VLD3LNdWB_fixed_Asm_16
4281  { 1073, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1073 = VLD3LNdWB_fixed_Asm_32
4282  { 1074, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1074 = VLD3LNdWB_fixed_Asm_8
4283  { 1075, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1075 = VLD3LNdWB_register_Asm_16
4284  { 1076, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1076 = VLD3LNdWB_register_Asm_32
4285  { 1077, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1077 = VLD3LNdWB_register_Asm_8
4286  { 1078, 11, 3, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1078 = VLD3LNq16
4287  { 1079, 7, 1, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo184,0,nullptr }, // Inst #1079 = VLD3LNq16Pseudo
4288  { 1080, 9, 2, 552, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo185,0,nullptr }, // Inst #1080 = VLD3LNq16Pseudo_UPD
4289  { 1081, 13, 4, 550, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo183,0,nullptr }, // Inst #1081 = VLD3LNq16_UPD
4290  { 1082, 11, 3, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo182,0,nullptr }, // Inst #1082 = VLD3LNq32
4291  { 1083, 7, 1, 548, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo184,0,nullptr }, // Inst #1083 = VLD3LNq32Pseudo
4292  { 1084, 9, 2, 552, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo185,0,nullptr }, // Inst #1084 = VLD3LNq32Pseudo_UPD
4293  { 1085, 13, 4, 550, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo183,0,nullptr }, // Inst #1085 = VLD3LNq32_UPD
4294  { 1086, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1086 = VLD3LNqAsm_16
4295  { 1087, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1087 = VLD3LNqAsm_32
4296  { 1088, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1088 = VLD3LNqWB_fixed_Asm_16
4297  { 1089, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1089 = VLD3LNqWB_fixed_Asm_32
4298  { 1090, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1090 = VLD3LNqWB_register_Asm_16
4299  { 1091, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1091 = VLD3LNqWB_register_Asm_32
4300  { 1092, 7, 3, 530, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1092 = VLD3d16
4301  { 1093, 5, 1, 531, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #1093 = VLD3d16Pseudo
4302  { 1094, 7, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1094 = VLD3d16Pseudo_UPD
4303  { 1095, 9, 4, 532, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo180,0,nullptr }, // Inst #1095 = VLD3d16_UPD
4304  { 1096, 7, 3, 530, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1096 = VLD3d32
4305  { 1097, 5, 1, 531, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #1097 = VLD3d32Pseudo
4306  { 1098, 7, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1098 = VLD3d32Pseudo_UPD
4307  { 1099, 9, 4, 532, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo180,0,nullptr }, // Inst #1099 = VLD3d32_UPD
4308  { 1100, 7, 3, 530, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1100 = VLD3d8
4309  { 1101, 5, 1, 531, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #1101 = VLD3d8Pseudo
4310  { 1102, 7, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1102 = VLD3d8Pseudo_UPD
4311  { 1103, 9, 4, 532, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo180,0,nullptr }, // Inst #1103 = VLD3d8_UPD
4312  { 1104, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1104 = VLD3dAsm_16
4313  { 1105, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1105 = VLD3dAsm_32
4314  { 1106, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1106 = VLD3dAsm_8
4315  { 1107, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1107 = VLD3dWB_fixed_Asm_16
4316  { 1108, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1108 = VLD3dWB_fixed_Asm_32
4317  { 1109, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1109 = VLD3dWB_fixed_Asm_8
4318  { 1110, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1110 = VLD3dWB_register_Asm_16
4319  { 1111, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1111 = VLD3dWB_register_Asm_32
4320  { 1112, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1112 = VLD3dWB_register_Asm_8
4321  { 1113, 7, 3, 530, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1113 = VLD3q16
4322  { 1114, 8, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1114 = VLD3q16Pseudo_UPD
4323  { 1115, 9, 4, 532, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo180,0,nullptr }, // Inst #1115 = VLD3q16_UPD
4324  { 1116, 6, 1, 531, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo187,0,nullptr }, // Inst #1116 = VLD3q16oddPseudo
4325  { 1117, 8, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1117 = VLD3q16oddPseudo_UPD
4326  { 1118, 7, 3, 530, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1118 = VLD3q32
4327  { 1119, 8, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1119 = VLD3q32Pseudo_UPD
4328  { 1120, 9, 4, 532, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo180,0,nullptr }, // Inst #1120 = VLD3q32_UPD
4329  { 1121, 6, 1, 531, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo187,0,nullptr }, // Inst #1121 = VLD3q32oddPseudo
4330  { 1122, 8, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1122 = VLD3q32oddPseudo_UPD
4331  { 1123, 7, 3, 530, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo178,0,nullptr }, // Inst #1123 = VLD3q8
4332  { 1124, 8, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1124 = VLD3q8Pseudo_UPD
4333  { 1125, 9, 4, 532, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo180,0,nullptr }, // Inst #1125 = VLD3q8_UPD
4334  { 1126, 6, 1, 531, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo187,0,nullptr }, // Inst #1126 = VLD3q8oddPseudo
4335  { 1127, 8, 2, 533, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1127 = VLD3q8oddPseudo_UPD
4336  { 1128, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1128 = VLD3qAsm_16
4337  { 1129, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1129 = VLD3qAsm_32
4338  { 1130, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1130 = VLD3qAsm_8
4339  { 1131, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1131 = VLD3qWB_fixed_Asm_16
4340  { 1132, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1132 = VLD3qWB_fixed_Asm_32
4341  { 1133, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1133 = VLD3qWB_fixed_Asm_8
4342  { 1134, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1134 = VLD3qWB_register_Asm_16
4343  { 1135, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1135 = VLD3qWB_register_Asm_32
4344  { 1136, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1136 = VLD3qWB_register_Asm_8
4345  { 1137, 8, 4, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo188,0,nullptr }, // Inst #1137 = VLD4DUPd16
4346  { 1138, 5, 1, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #1138 = VLD4DUPd16Pseudo
4347  { 1139, 7, 2, 557, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1139 = VLD4DUPd16Pseudo_UPD
4348  { 1140, 10, 5, 555, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo189,0,nullptr }, // Inst #1140 = VLD4DUPd16_UPD
4349  { 1141, 8, 4, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo188,0,nullptr }, // Inst #1141 = VLD4DUPd32
4350  { 1142, 5, 1, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #1142 = VLD4DUPd32Pseudo
4351  { 1143, 7, 2, 557, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1143 = VLD4DUPd32Pseudo_UPD
4352  { 1144, 10, 5, 555, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo189,0,nullptr }, // Inst #1144 = VLD4DUPd32_UPD
4353  { 1145, 8, 4, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo188,0,nullptr }, // Inst #1145 = VLD4DUPd8
4354  { 1146, 5, 1, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #1146 = VLD4DUPd8Pseudo
4355  { 1147, 7, 2, 557, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1147 = VLD4DUPd8Pseudo_UPD
4356  { 1148, 10, 5, 555, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo189,0,nullptr }, // Inst #1148 = VLD4DUPd8_UPD
4357  { 1149, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1149 = VLD4DUPdAsm_16
4358  { 1150, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1150 = VLD4DUPdAsm_32
4359  { 1151, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1151 = VLD4DUPdAsm_8
4360  { 1152, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1152 = VLD4DUPdWB_fixed_Asm_16
4361  { 1153, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1153 = VLD4DUPdWB_fixed_Asm_32
4362  { 1154, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1154 = VLD4DUPdWB_fixed_Asm_8
4363  { 1155, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1155 = VLD4DUPdWB_register_Asm_16
4364  { 1156, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1156 = VLD4DUPdWB_register_Asm_32
4365  { 1157, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1157 = VLD4DUPdWB_register_Asm_8
4366  { 1158, 8, 4, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo188,0,nullptr }, // Inst #1158 = VLD4DUPq16
4367  { 1159, 10, 5, 555, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo189,0,nullptr }, // Inst #1159 = VLD4DUPq16_UPD
4368  { 1160, 8, 4, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo188,0,nullptr }, // Inst #1160 = VLD4DUPq32
4369  { 1161, 10, 5, 555, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo189,0,nullptr }, // Inst #1161 = VLD4DUPq32_UPD
4370  { 1162, 8, 4, 553, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo188,0,nullptr }, // Inst #1162 = VLD4DUPq8
4371  { 1163, 10, 5, 555, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo189,0,nullptr }, // Inst #1163 = VLD4DUPq8_UPD
4372  { 1164, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1164 = VLD4DUPqAsm_16
4373  { 1165, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1165 = VLD4DUPqAsm_32
4374  { 1166, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1166 = VLD4DUPqAsm_8
4375  { 1167, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1167 = VLD4DUPqWB_fixed_Asm_16
4376  { 1168, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1168 = VLD4DUPqWB_fixed_Asm_32
4377  { 1169, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1169 = VLD4DUPqWB_fixed_Asm_8
4378  { 1170, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1170 = VLD4DUPqWB_register_Asm_16
4379  { 1171, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1171 = VLD4DUPqWB_register_Asm_32
4380  { 1172, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1172 = VLD4DUPqWB_register_Asm_8
4381  { 1173, 13, 4, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo190,0,nullptr }, // Inst #1173 = VLD4LNd16
4382  { 1174, 7, 1, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1174 = VLD4LNd16Pseudo
4383  { 1175, 9, 2, 558, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1175 = VLD4LNd16Pseudo_UPD
4384  { 1176, 15, 5, 556, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo191,0,nullptr }, // Inst #1176 = VLD4LNd16_UPD
4385  { 1177, 13, 4, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo190,0,nullptr }, // Inst #1177 = VLD4LNd32
4386  { 1178, 7, 1, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1178 = VLD4LNd32Pseudo
4387  { 1179, 9, 2, 558, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1179 = VLD4LNd32Pseudo_UPD
4388  { 1180, 15, 5, 556, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo191,0,nullptr }, // Inst #1180 = VLD4LNd32_UPD
4389  { 1181, 13, 4, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo190,0,nullptr }, // Inst #1181 = VLD4LNd8
4390  { 1182, 7, 1, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo176,0,nullptr }, // Inst #1182 = VLD4LNd8Pseudo
4391  { 1183, 9, 2, 558, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo177,0,nullptr }, // Inst #1183 = VLD4LNd8Pseudo_UPD
4392  { 1184, 15, 5, 556, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo191,0,nullptr }, // Inst #1184 = VLD4LNd8_UPD
4393  { 1185, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1185 = VLD4LNdAsm_16
4394  { 1186, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1186 = VLD4LNdAsm_32
4395  { 1187, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1187 = VLD4LNdAsm_8
4396  { 1188, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1188 = VLD4LNdWB_fixed_Asm_16
4397  { 1189, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1189 = VLD4LNdWB_fixed_Asm_32
4398  { 1190, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1190 = VLD4LNdWB_fixed_Asm_8
4399  { 1191, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1191 = VLD4LNdWB_register_Asm_16
4400  { 1192, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1192 = VLD4LNdWB_register_Asm_32
4401  { 1193, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1193 = VLD4LNdWB_register_Asm_8
4402  { 1194, 13, 4, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo190,0,nullptr }, // Inst #1194 = VLD4LNq16
4403  { 1195, 7, 1, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo184,0,nullptr }, // Inst #1195 = VLD4LNq16Pseudo
4404  { 1196, 9, 2, 558, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo185,0,nullptr }, // Inst #1196 = VLD4LNq16Pseudo_UPD
4405  { 1197, 15, 5, 556, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo191,0,nullptr }, // Inst #1197 = VLD4LNq16_UPD
4406  { 1198, 13, 4, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo190,0,nullptr }, // Inst #1198 = VLD4LNq32
4407  { 1199, 7, 1, 554, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo184,0,nullptr }, // Inst #1199 = VLD4LNq32Pseudo
4408  { 1200, 9, 2, 558, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo185,0,nullptr }, // Inst #1200 = VLD4LNq32Pseudo_UPD
4409  { 1201, 15, 5, 556, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo191,0,nullptr }, // Inst #1201 = VLD4LNq32_UPD
4410  { 1202, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1202 = VLD4LNqAsm_16
4411  { 1203, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1203 = VLD4LNqAsm_32
4412  { 1204, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1204 = VLD4LNqWB_fixed_Asm_16
4413  { 1205, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1205 = VLD4LNqWB_fixed_Asm_32
4414  { 1206, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1206 = VLD4LNqWB_register_Asm_16
4415  { 1207, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1207 = VLD4LNqWB_register_Asm_32
4416  { 1208, 8, 4, 534, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo188,0,nullptr }, // Inst #1208 = VLD4d16
4417  { 1209, 5, 1, 535, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #1209 = VLD4d16Pseudo
4418  { 1210, 7, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1210 = VLD4d16Pseudo_UPD
4419  { 1211, 10, 5, 536, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo189,0,nullptr }, // Inst #1211 = VLD4d16_UPD
4420  { 1212, 8, 4, 534, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo188,0,nullptr }, // Inst #1212 = VLD4d32
4421  { 1213, 5, 1, 535, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #1213 = VLD4d32Pseudo
4422  { 1214, 7, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1214 = VLD4d32Pseudo_UPD
4423  { 1215, 10, 5, 536, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo189,0,nullptr }, // Inst #1215 = VLD4d32_UPD
4424  { 1216, 8, 4, 534, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo188,0,nullptr }, // Inst #1216 = VLD4d8
4425  { 1217, 5, 1, 535, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo171,0,nullptr }, // Inst #1217 = VLD4d8Pseudo
4426  { 1218, 7, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo179,0,nullptr }, // Inst #1218 = VLD4d8Pseudo_UPD
4427  { 1219, 10, 5, 536, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo189,0,nullptr }, // Inst #1219 = VLD4d8_UPD
4428  { 1220, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1220 = VLD4dAsm_16
4429  { 1221, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1221 = VLD4dAsm_32
4430  { 1222, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1222 = VLD4dAsm_8
4431  { 1223, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1223 = VLD4dWB_fixed_Asm_16
4432  { 1224, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1224 = VLD4dWB_fixed_Asm_32
4433  { 1225, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1225 = VLD4dWB_fixed_Asm_8
4434  { 1226, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1226 = VLD4dWB_register_Asm_16
4435  { 1227, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1227 = VLD4dWB_register_Asm_32
4436  { 1228, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1228 = VLD4dWB_register_Asm_8
4437  { 1229, 8, 4, 534, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo188,0,nullptr }, // Inst #1229 = VLD4q16
4438  { 1230, 8, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1230 = VLD4q16Pseudo_UPD
4439  { 1231, 10, 5, 536, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo189,0,nullptr }, // Inst #1231 = VLD4q16_UPD
4440  { 1232, 6, 1, 535, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo187,0,nullptr }, // Inst #1232 = VLD4q16oddPseudo
4441  { 1233, 8, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1233 = VLD4q16oddPseudo_UPD
4442  { 1234, 8, 4, 534, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo188,0,nullptr }, // Inst #1234 = VLD4q32
4443  { 1235, 8, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1235 = VLD4q32Pseudo_UPD
4444  { 1236, 10, 5, 536, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo189,0,nullptr }, // Inst #1236 = VLD4q32_UPD
4445  { 1237, 6, 1, 535, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo187,0,nullptr }, // Inst #1237 = VLD4q32oddPseudo
4446  { 1238, 8, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1238 = VLD4q32oddPseudo_UPD
4447  { 1239, 8, 4, 534, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo188,0,nullptr }, // Inst #1239 = VLD4q8
4448  { 1240, 8, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1240 = VLD4q8Pseudo_UPD
4449  { 1241, 10, 5, 536, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo189,0,nullptr }, // Inst #1241 = VLD4q8_UPD
4450  { 1242, 6, 1, 535, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo187,0,nullptr }, // Inst #1242 = VLD4q8oddPseudo
4451  { 1243, 8, 2, 537, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo186,0,nullptr }, // Inst #1243 = VLD4q8oddPseudo_UPD
4452  { 1244, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1244 = VLD4qAsm_16
4453  { 1245, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1245 = VLD4qAsm_32
4454  { 1246, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1246 = VLD4qAsm_8
4455  { 1247, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1247 = VLD4qWB_fixed_Asm_16
4456  { 1248, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1248 = VLD4qWB_fixed_Asm_32
4457  { 1249, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1249 = VLD4qWB_fixed_Asm_8
4458  { 1250, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1250 = VLD4qWB_register_Asm_16
4459  { 1251, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1251 = VLD4qWB_register_Asm_32
4460  { 1252, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #1252 = VLD4qWB_register_Asm_8
4461  { 1253, 5, 1, 515, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x8be4ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #1253 = VLDMDDB_UPD
4462  { 1254, 4, 0, 514, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x8b84ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #1254 = VLDMDIA
4463  { 1255, 5, 1, 515, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x8be4ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #1255 = VLDMDIA_UPD
4464  { 1256, 4, 1, 512, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x18004ULL, nullptr, nullptr, OperandInfo192,0,nullptr }, // Inst #1256 = VLDMQIA
4465  { 1257, 5, 1, 515, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x18be4ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #1257 = VLDMSDB_UPD
4466  { 1258, 4, 0, 514, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x18b84ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #1258 = VLDMSIA
4467  { 1259, 5, 1, 515, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x18be4ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #1259 = VLDMSIA_UPD
4468  { 1260, 5, 1, 508, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x18b05ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #1260 = VLDRD
4469  { 1261, 5, 1, 509, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x18b05ULL, nullptr, nullptr, OperandInfo193,0,nullptr }, // Inst #1261 = VLDRS
4470  { 1262, 3, 1, 446, 4, 0, 0x8800ULL, nullptr, nullptr, OperandInfo194,0,nullptr }, // Inst #1262 = VMAXNMD
4471  { 1263, 3, 1, 446, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo194,0,nullptr }, // Inst #1263 = VMAXNMND
4472  { 1264, 3, 1, 446, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo195,0,nullptr }, // Inst #1264 = VMAXNMNQ
4473  { 1265, 3, 1, 446, 4, 0, 0x8800ULL, nullptr, nullptr, OperandInfo196,0,nullptr }, // Inst #1265 = VMAXNMS
4474  { 1266, 5, 1, 442, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1266 = VMAXfd
4475  { 1267, 5, 1, 443, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1267 = VMAXfq
4476  { 1268, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1268 = VMAXsv16i8
4477  { 1269, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1269 = VMAXsv2i32
4478  { 1270, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1270 = VMAXsv4i16
4479  { 1271, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1271 = VMAXsv4i32
4480  { 1272, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1272 = VMAXsv8i16
4481  { 1273, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1273 = VMAXsv8i8
4482  { 1274, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1274 = VMAXuv16i8
4483  { 1275, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1275 = VMAXuv2i32
4484  { 1276, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1276 = VMAXuv4i16
4485  { 1277, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1277 = VMAXuv4i32
4486  { 1278, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1278 = VMAXuv8i16
4487  { 1279, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1279 = VMAXuv8i8
4488  { 1280, 3, 1, 446, 4, 0, 0x8800ULL, nullptr, nullptr, OperandInfo194,0,nullptr }, // Inst #1280 = VMINNMD
4489  { 1281, 3, 1, 446, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo194,0,nullptr }, // Inst #1281 = VMINNMND
4490  { 1282, 3, 1, 446, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo195,0,nullptr }, // Inst #1282 = VMINNMNQ
4491  { 1283, 3, 1, 446, 4, 0, 0x8800ULL, nullptr, nullptr, OperandInfo196,0,nullptr }, // Inst #1283 = VMINNMS
4492  { 1284, 5, 1, 442, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1284 = VMINfd
4493  { 1285, 5, 1, 443, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1285 = VMINfq
4494  { 1286, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1286 = VMINsv16i8
4495  { 1287, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1287 = VMINsv2i32
4496  { 1288, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1288 = VMINsv4i16
4497  { 1289, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1289 = VMINsv4i32
4498  { 1290, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1290 = VMINsv8i16
4499  { 1291, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1291 = VMINsv8i8
4500  { 1292, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1292 = VMINuv16i8
4501  { 1293, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1293 = VMINuv2i32
4502  { 1294, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1294 = VMINuv4i16
4503  { 1295, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1295 = VMINuv4i32
4504  { 1296, 5, 1, 441, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1296 = VMINuv8i16
4505  { 1297, 5, 1, 444, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1297 = VMINuv8i8
4506  { 1298, 6, 1, 464, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1298 = VMLAD
4507  { 1299, 7, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo197,0,nullptr }, // Inst #1299 = VMLALslsv2i32
4508  { 1300, 7, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo198,0,nullptr }, // Inst #1300 = VMLALslsv4i16
4509  { 1301, 7, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo197,0,nullptr }, // Inst #1301 = VMLALsluv2i32
4510  { 1302, 7, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo198,0,nullptr }, // Inst #1302 = VMLALsluv4i16
4511  { 1303, 6, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1303 = VMLALsv2i64
4512  { 1304, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1304 = VMLALsv4i32
4513  { 1305, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1305 = VMLALsv8i16
4514  { 1306, 6, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1306 = VMLALuv2i64
4515  { 1307, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1307 = VMLALuv4i32
4516  { 1308, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1308 = VMLALuv8i16
4517  { 1309, 6, 1, 467, 4, 0|(1<<MCID_Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #1309 = VMLAS
4518  { 1310, 6, 1, 468, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1310 = VMLAfd
4519  { 1311, 6, 1, 469, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1311 = VMLAfq
4520  { 1312, 7, 1, 468, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo199,0,nullptr }, // Inst #1312 = VMLAslfd
4521  { 1313, 7, 1, 469, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo200,0,nullptr }, // Inst #1313 = VMLAslfq
4522  { 1314, 7, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo199,0,nullptr }, // Inst #1314 = VMLAslv2i32
4523  { 1315, 7, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo201,0,nullptr }, // Inst #1315 = VMLAslv4i16
4524  { 1316, 7, 1, 470, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo200,0,nullptr }, // Inst #1316 = VMLAslv4i32
4525  { 1317, 7, 1, 471, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo202,0,nullptr }, // Inst #1317 = VMLAslv8i16
4526  { 1318, 6, 1, 471, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1318 = VMLAv16i8
4527  { 1319, 6, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1319 = VMLAv2i32
4528  { 1320, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1320 = VMLAv4i16
4529  { 1321, 6, 1, 470, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1321 = VMLAv4i32
4530  { 1322, 6, 1, 471, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1322 = VMLAv8i16
4531  { 1323, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1323 = VMLAv8i8
4532  { 1324, 6, 1, 464, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1324 = VMLSD
4533  { 1325, 7, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo197,0,nullptr }, // Inst #1325 = VMLSLslsv2i32
4534  { 1326, 7, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo198,0,nullptr }, // Inst #1326 = VMLSLslsv4i16
4535  { 1327, 7, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo197,0,nullptr }, // Inst #1327 = VMLSLsluv2i32
4536  { 1328, 7, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo198,0,nullptr }, // Inst #1328 = VMLSLsluv4i16
4537  { 1329, 6, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1329 = VMLSLsv2i64
4538  { 1330, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1330 = VMLSLsv4i32
4539  { 1331, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1331 = VMLSLsv8i16
4540  { 1332, 6, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1332 = VMLSLuv2i64
4541  { 1333, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1333 = VMLSLuv4i32
4542  { 1334, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1334 = VMLSLuv8i16
4543  { 1335, 6, 1, 467, 4, 0|(1<<MCID_Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #1335 = VMLSS
4544  { 1336, 6, 1, 468, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1336 = VMLSfd
4545  { 1337, 6, 1, 469, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1337 = VMLSfq
4546  { 1338, 7, 1, 468, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo199,0,nullptr }, // Inst #1338 = VMLSslfd
4547  { 1339, 7, 1, 469, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo200,0,nullptr }, // Inst #1339 = VMLSslfq
4548  { 1340, 7, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo199,0,nullptr }, // Inst #1340 = VMLSslv2i32
4549  { 1341, 7, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo201,0,nullptr }, // Inst #1341 = VMLSslv4i16
4550  { 1342, 7, 1, 470, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo200,0,nullptr }, // Inst #1342 = VMLSslv4i32
4551  { 1343, 7, 1, 471, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo202,0,nullptr }, // Inst #1343 = VMLSslv8i16
4552  { 1344, 6, 1, 471, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1344 = VMLSv16i8
4553  { 1345, 6, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1345 = VMLSv2i32
4554  { 1346, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1346 = VMLSv4i16
4555  { 1347, 6, 1, 470, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1347 = VMLSv4i32
4556  { 1348, 6, 1, 471, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo128,0,nullptr }, // Inst #1348 = VMLSv8i16
4557  { 1349, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1349 = VMLSv8i8
4558  { 1350, 4, 1, 487, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1350 = VMOVD
4559  { 1351, 1, 1, 101, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Rematerializable)|(1<<MCID_CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo203,0,nullptr }, // Inst #1351 = VMOVD0
4560  { 1352, 5, 1, 501, 4, 0|(1<<MCID_Predicable)|(1<<MCID_RegSequence), 0x18a80ULL, nullptr, nullptr, OperandInfo204,0,nullptr }, // Inst #1352 = VMOVDRR
4561  { 1353, 5, 1, 487, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo205,0,nullptr }, // Inst #1353 = VMOVDcc
4562  { 1354, 4, 1, 491, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo151,0,nullptr }, // Inst #1354 = VMOVLsv2i64
4563  { 1355, 4, 1, 491, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo151,0,nullptr }, // Inst #1355 = VMOVLsv4i32
4564  { 1356, 4, 1, 491, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo151,0,nullptr }, // Inst #1356 = VMOVLsv8i16
4565  { 1357, 4, 1, 491, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo151,0,nullptr }, // Inst #1357 = VMOVLuv2i64
4566  { 1358, 4, 1, 491, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo151,0,nullptr }, // Inst #1358 = VMOVLuv4i32
4567  { 1359, 4, 1, 491, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo151,0,nullptr }, // Inst #1359 = VMOVLuv8i16
4568  { 1360, 4, 1, 492, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo148,0,nullptr }, // Inst #1360 = VMOVNv2i32
4569  { 1361, 4, 1, 492, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo148,0,nullptr }, // Inst #1361 = VMOVNv4i16
4570  { 1362, 4, 1, 492, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo148,0,nullptr }, // Inst #1362 = VMOVNv8i8
4571  { 1363, 1, 1, 101, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Rematerializable)|(1<<MCID_CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo206,0,nullptr }, // Inst #1363 = VMOVQ0
4572  { 1364, 5, 2, 500, 4, 0|(1<<MCID_Predicable)|(1<<MCID_ExtractSubreg), 0x18980ULL, nullptr, nullptr, OperandInfo207,0,nullptr }, // Inst #1364 = VMOVRRD
4573  { 1365, 6, 2, 500, 4, 0|(1<<MCID_Predicable), 0x18980ULL, nullptr, nullptr, OperandInfo208,0,nullptr }, // Inst #1365 = VMOVRRS
4574  { 1366, 4, 1, 497, 4, 0|(1<<MCID_Bitcast)|(1<<MCID_Predicable), 0x18900ULL, nullptr, nullptr, OperandInfo209,0,nullptr }, // Inst #1366 = VMOVRS
4575  { 1367, 4, 1, 488, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #1367 = VMOVS
4576  { 1368, 4, 1, 498, 4, 0|(1<<MCID_Bitcast)|(1<<MCID_Predicable), 0x18a00ULL, nullptr, nullptr, OperandInfo210,0,nullptr }, // Inst #1368 = VMOVSR
4577  { 1369, 6, 2, 502, 4, 0|(1<<MCID_Predicable), 0x18a80ULL, nullptr, nullptr, OperandInfo211,0,nullptr }, // Inst #1369 = VMOVSRR
4578  { 1370, 5, 1, 488, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo212,0,nullptr }, // Inst #1370 = VMOVScc
4579  { 1371, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo213,0,nullptr }, // Inst #1371 = VMOVv16i8
4580  { 1372, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo49,0,nullptr }, // Inst #1372 = VMOVv1i64
4581  { 1373, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo49,0,nullptr }, // Inst #1373 = VMOVv2f32
4582  { 1374, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo49,0,nullptr }, // Inst #1374 = VMOVv2i32
4583  { 1375, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo213,0,nullptr }, // Inst #1375 = VMOVv2i64
4584  { 1376, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo213,0,nullptr }, // Inst #1376 = VMOVv4f32
4585  { 1377, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo49,0,nullptr }, // Inst #1377 = VMOVv4i16
4586  { 1378, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo213,0,nullptr }, // Inst #1378 = VMOVv4i32
4587  { 1379, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo213,0,nullptr }, // Inst #1379 = VMOVv8i16
4588  { 1380, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo49,0,nullptr }, // Inst #1380 = VMOVv8i8
4589  { 1381, 3, 1, 505, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList10, nullptr, OperandInfo34,0,nullptr }, // Inst #1381 = VMRS
4590  { 1382, 3, 1, 505, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList10, nullptr, OperandInfo34,0,nullptr }, // Inst #1382 = VMRS_FPEXC
4591  { 1383, 3, 1, 505, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList10, nullptr, OperandInfo34,0,nullptr }, // Inst #1383 = VMRS_FPINST
4592  { 1384, 3, 1, 505, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList10, nullptr, OperandInfo34,0,nullptr }, // Inst #1384 = VMRS_FPINST2
4593  { 1385, 3, 1, 505, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList10, nullptr, OperandInfo34,0,nullptr }, // Inst #1385 = VMRS_FPSID
4594  { 1386, 3, 1, 505, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList10, nullptr, OperandInfo34,0,nullptr }, // Inst #1386 = VMRS_MVFR0
4595  { 1387, 3, 1, 505, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList10, nullptr, OperandInfo34,0,nullptr }, // Inst #1387 = VMRS_MVFR1
4596  { 1388, 3, 1, 505, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList10, nullptr, OperandInfo34,0,nullptr }, // Inst #1388 = VMRS_MVFR2
4597  { 1389, 3, 0, 506, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList10, OperandInfo34,0,nullptr }, // Inst #1389 = VMSR
4598  { 1390, 3, 0, 506, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList10, OperandInfo34,0,nullptr }, // Inst #1390 = VMSR_FPEXC
4599  { 1391, 3, 0, 506, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList10, OperandInfo34,0,nullptr }, // Inst #1391 = VMSR_FPINST
4600  { 1392, 3, 0, 506, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList10, OperandInfo34,0,nullptr }, // Inst #1392 = VMSR_FPINST2
4601  { 1393, 3, 0, 506, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, nullptr, ImplicitList10, OperandInfo34,0,nullptr }, // Inst #1393 = VMSR_FPSID
4602  { 1394, 5, 1, 461, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1394 = VMULD
4603  { 1395, 3, 1, 451, 4, 0, 0x11280ULL, nullptr, nullptr, OperandInfo214,0,nullptr }, // Inst #1395 = VMULLp64
4604  { 1396, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #1396 = VMULLp8
4605  { 1397, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo215,0,nullptr }, // Inst #1397 = VMULLslsv2i32
4606  { 1398, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo216,0,nullptr }, // Inst #1398 = VMULLslsv4i16
4607  { 1399, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo215,0,nullptr }, // Inst #1399 = VMULLsluv2i32
4608  { 1400, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo216,0,nullptr }, // Inst #1400 = VMULLsluv4i16
4609  { 1401, 5, 1, 453, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #1401 = VMULLsv2i64
4610  { 1402, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #1402 = VMULLsv4i32
4611  { 1403, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #1403 = VMULLsv8i16
4612  { 1404, 5, 1, 453, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #1404 = VMULLuv2i64
4613  { 1405, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #1405 = VMULLuv4i32
4614  { 1406, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #1406 = VMULLuv8i16
4615  { 1407, 5, 1, 454, 4, 0|(1<<MCID_Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo137,0,nullptr }, // Inst #1407 = VMULS
4616  { 1408, 5, 1, 455, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1408 = VMULfd
4617  { 1409, 5, 1, 456, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1409 = VMULfq
4618  { 1410, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1410 = VMULpd
4619  { 1411, 5, 1, 457, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1411 = VMULpq
4620  { 1412, 6, 1, 458, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo217,0,nullptr }, // Inst #1412 = VMULslfd
4621  { 1413, 6, 1, 459, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo218,0,nullptr }, // Inst #1413 = VMULslfq
4622  { 1414, 6, 1, 453, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo217,0,nullptr }, // Inst #1414 = VMULslv2i32
4623  { 1415, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1415 = VMULslv4i16
4624  { 1416, 6, 1, 460, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo218,0,nullptr }, // Inst #1416 = VMULslv4i32
4625  { 1417, 6, 1, 457, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1417 = VMULslv8i16
4626  { 1418, 5, 1, 457, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1418 = VMULv16i8
4627  { 1419, 5, 1, 453, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1419 = VMULv2i32
4628  { 1420, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1420 = VMULv4i16
4629  { 1421, 5, 1, 460, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1421 = VMULv4i32
4630  { 1422, 5, 1, 457, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1422 = VMULv8i16
4631  { 1423, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1423 = VMULv8i8
4632  { 1424, 4, 1, 490, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1424 = VMVNd
4633  { 1425, 4, 1, 490, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1425 = VMVNq
4634  { 1426, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo49,0,nullptr }, // Inst #1426 = VMVNv2i32
4635  { 1427, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo49,0,nullptr }, // Inst #1427 = VMVNv4i16
4636  { 1428, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo213,0,nullptr }, // Inst #1428 = VMVNv4i32
4637  { 1429, 4, 1, 489, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, nullptr, nullptr, OperandInfo213,0,nullptr }, // Inst #1429 = VMVNv8i16
4638  { 1430, 4, 1, 437, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1430 = VNEGD
4639  { 1431, 4, 1, 438, 4, 0|(1<<MCID_Predicable), 0x28780ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #1431 = VNEGS
4640  { 1432, 4, 1, 390, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1432 = VNEGf32q
4641  { 1433, 4, 1, 391, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1433 = VNEGfd
4642  { 1434, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1434 = VNEGs16d
4643  { 1435, 4, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1435 = VNEGs16q
4644  { 1436, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1436 = VNEGs32d
4645  { 1437, 4, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1437 = VNEGs32q
4646  { 1438, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1438 = VNEGs8d
4647  { 1439, 4, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1439 = VNEGs8q
4648  { 1440, 6, 1, 464, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1440 = VNMLAD
4649  { 1441, 6, 1, 467, 4, 0|(1<<MCID_Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #1441 = VNMLAS
4650  { 1442, 6, 1, 464, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #1442 = VNMLSD
4651  { 1443, 6, 1, 467, 4, 0|(1<<MCID_Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo157,0,nullptr }, // Inst #1443 = VNMLSS
4652  { 1444, 5, 1, 461, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1444 = VNMULD
4653  { 1445, 5, 1, 454, 4, 0|(1<<MCID_Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo137,0,nullptr }, // Inst #1445 = VNMULS
4654  { 1446, 5, 1, 382, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1446 = VORNd
4655  { 1447, 5, 1, 381, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1447 = VORNq
4656  { 1448, 5, 1, 382, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1448 = VORRd
4657  { 1449, 5, 1, 383, 4, 0|(1<<MCID_Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #1449 = VORRiv2i32
4658  { 1450, 5, 1, 383, 4, 0|(1<<MCID_Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo139,0,nullptr }, // Inst #1450 = VORRiv4i16
4659  { 1451, 5, 1, 383, 4, 0|(1<<MCID_Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo140,0,nullptr }, // Inst #1451 = VORRiv4i32
4660  { 1452, 5, 1, 383, 4, 0|(1<<MCID_Predicable), 0x10f80ULL, nullptr, nullptr, OperandInfo140,0,nullptr }, // Inst #1452 = VORRiv8i16
4661  { 1453, 5, 1, 381, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1453 = VORRq
4662  { 1454, 5, 1, 411, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1454 = VPADALsv16i8
4663  { 1455, 5, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo205,0,nullptr }, // Inst #1455 = VPADALsv2i32
4664  { 1456, 5, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo205,0,nullptr }, // Inst #1456 = VPADALsv4i16
4665  { 1457, 5, 1, 411, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1457 = VPADALsv4i32
4666  { 1458, 5, 1, 411, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1458 = VPADALsv8i16
4667  { 1459, 5, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo205,0,nullptr }, // Inst #1459 = VPADALsv8i8
4668  { 1460, 5, 1, 411, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1460 = VPADALuv16i8
4669  { 1461, 5, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo205,0,nullptr }, // Inst #1461 = VPADALuv2i32
4670  { 1462, 5, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo205,0,nullptr }, // Inst #1462 = VPADALuv4i16
4671  { 1463, 5, 1, 411, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1463 = VPADALuv4i32
4672  { 1464, 5, 1, 411, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo221,0,nullptr }, // Inst #1464 = VPADALuv8i16
4673  { 1465, 5, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo205,0,nullptr }, // Inst #1465 = VPADALuv8i8
4674  { 1466, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1466 = VPADDLsv16i8
4675  { 1467, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1467 = VPADDLsv2i32
4676  { 1468, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1468 = VPADDLsv4i16
4677  { 1469, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1469 = VPADDLsv4i32
4678  { 1470, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1470 = VPADDLsv8i16
4679  { 1471, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1471 = VPADDLsv8i8
4680  { 1472, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1472 = VPADDLuv16i8
4681  { 1473, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1473 = VPADDLuv2i32
4682  { 1474, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1474 = VPADDLuv4i16
4683  { 1475, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1475 = VPADDLuv4i32
4684  { 1476, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1476 = VPADDLuv8i16
4685  { 1477, 4, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1477 = VPADDLuv8i8
4686  { 1478, 5, 1, 447, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1478 = VPADDf
4687  { 1479, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1479 = VPADDi16
4688  { 1480, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1480 = VPADDi32
4689  { 1481, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1481 = VPADDi8
4690  { 1482, 5, 1, 447, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1482 = VPMAXf
4691  { 1483, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1483 = VPMAXs16
4692  { 1484, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1484 = VPMAXs32
4693  { 1485, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1485 = VPMAXs8
4694  { 1486, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1486 = VPMAXu16
4695  { 1487, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1487 = VPMAXu32
4696  { 1488, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1488 = VPMAXu8
4697  { 1489, 5, 1, 447, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1489 = VPMINf
4698  { 1490, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1490 = VPMINs16
4699  { 1491, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1491 = VPMINs32
4700  { 1492, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1492 = VPMINs8
4701  { 1493, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1493 = VPMINu16
4702  { 1494, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1494 = VPMINu32
4703  { 1495, 5, 1, 444, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1495 = VPMINu8
4704  { 1496, 4, 1, 413, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1496 = VQABSv16i8
4705  { 1497, 4, 1, 414, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1497 = VQABSv2i32
4706  { 1498, 4, 1, 414, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1498 = VQABSv4i16
4707  { 1499, 4, 1, 413, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1499 = VQABSv4i32
4708  { 1500, 4, 1, 413, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1500 = VQABSv8i16
4709  { 1501, 4, 1, 414, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1501 = VQABSv8i8
4710  { 1502, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1502 = VQADDsv16i8
4711  { 1503, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1503 = VQADDsv1i64
4712  { 1504, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1504 = VQADDsv2i32
4713  { 1505, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1505 = VQADDsv2i64
4714  { 1506, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1506 = VQADDsv4i16
4715  { 1507, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1507 = VQADDsv4i32
4716  { 1508, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1508 = VQADDsv8i16
4717  { 1509, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1509 = VQADDsv8i8
4718  { 1510, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1510 = VQADDuv16i8
4719  { 1511, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1511 = VQADDuv1i64
4720  { 1512, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1512 = VQADDuv2i32
4721  { 1513, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1513 = VQADDuv2i64
4722  { 1514, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1514 = VQADDuv4i16
4723  { 1515, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1515 = VQADDuv4i32
4724  { 1516, 5, 1, 415, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1516 = VQADDuv8i16
4725  { 1517, 5, 1, 416, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1517 = VQADDuv8i8
4726  { 1518, 7, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo197,0,nullptr }, // Inst #1518 = VQDMLALslv2i32
4727  { 1519, 7, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo198,0,nullptr }, // Inst #1519 = VQDMLALslv4i16
4728  { 1520, 6, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1520 = VQDMLALv2i64
4729  { 1521, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1521 = VQDMLALv4i32
4730  { 1522, 7, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo197,0,nullptr }, // Inst #1522 = VQDMLSLslv2i32
4731  { 1523, 7, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo198,0,nullptr }, // Inst #1523 = VQDMLSLslv4i16
4732  { 1524, 6, 1, 465, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1524 = VQDMLSLv2i64
4733  { 1525, 6, 1, 466, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo127,0,nullptr }, // Inst #1525 = VQDMLSLv4i32
4734  { 1526, 6, 1, 453, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo217,0,nullptr }, // Inst #1526 = VQDMULHslv2i32
4735  { 1527, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1527 = VQDMULHslv4i16
4736  { 1528, 6, 1, 460, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo218,0,nullptr }, // Inst #1528 = VQDMULHslv4i32
4737  { 1529, 6, 1, 457, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1529 = VQDMULHslv8i16
4738  { 1530, 5, 1, 453, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1530 = VQDMULHv2i32
4739  { 1531, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1531 = VQDMULHv4i16
4740  { 1532, 5, 1, 460, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1532 = VQDMULHv4i32
4741  { 1533, 5, 1, 457, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1533 = VQDMULHv8i16
4742  { 1534, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo215,0,nullptr }, // Inst #1534 = VQDMULLslv2i32
4743  { 1535, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo216,0,nullptr }, // Inst #1535 = VQDMULLslv4i16
4744  { 1536, 5, 1, 453, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #1536 = VQDMULLv2i64
4745  { 1537, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #1537 = VQDMULLv4i32
4746  { 1538, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo148,0,nullptr }, // Inst #1538 = VQMOVNsuv2i32
4747  { 1539, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo148,0,nullptr }, // Inst #1539 = VQMOVNsuv4i16
4748  { 1540, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo148,0,nullptr }, // Inst #1540 = VQMOVNsuv8i8
4749  { 1541, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo148,0,nullptr }, // Inst #1541 = VQMOVNsv2i32
4750  { 1542, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo148,0,nullptr }, // Inst #1542 = VQMOVNsv4i16
4751  { 1543, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo148,0,nullptr }, // Inst #1543 = VQMOVNsv8i8
4752  { 1544, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo148,0,nullptr }, // Inst #1544 = VQMOVNuv2i32
4753  { 1545, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo148,0,nullptr }, // Inst #1545 = VQMOVNuv4i16
4754  { 1546, 4, 1, 493, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo148,0,nullptr }, // Inst #1546 = VQMOVNuv8i8
4755  { 1547, 4, 1, 413, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1547 = VQNEGv16i8
4756  { 1548, 4, 1, 414, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1548 = VQNEGv2i32
4757  { 1549, 4, 1, 414, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1549 = VQNEGv4i16
4758  { 1550, 4, 1, 413, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1550 = VQNEGv4i32
4759  { 1551, 4, 1, 413, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1551 = VQNEGv8i16
4760  { 1552, 4, 1, 414, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1552 = VQNEGv8i8
4761  { 1553, 6, 1, 453, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo217,0,nullptr }, // Inst #1553 = VQRDMULHslv2i32
4762  { 1554, 6, 1, 452, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo219,0,nullptr }, // Inst #1554 = VQRDMULHslv4i16
4763  { 1555, 6, 1, 460, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo218,0,nullptr }, // Inst #1555 = VQRDMULHslv4i32
4764  { 1556, 6, 1, 457, 4, 0|(1<<MCID_Predicable), 0x11400ULL, nullptr, nullptr, OperandInfo220,0,nullptr }, // Inst #1556 = VQRDMULHslv8i16
4765  { 1557, 5, 1, 453, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1557 = VQRDMULHv2i32
4766  { 1558, 5, 1, 452, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1558 = VQRDMULHv4i16
4767  { 1559, 5, 1, 460, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1559 = VQRDMULHv4i32
4768  { 1560, 5, 1, 457, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1560 = VQRDMULHv8i16
4769  { 1561, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1561 = VQRSHLsv16i8
4770  { 1562, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1562 = VQRSHLsv1i64
4771  { 1563, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1563 = VQRSHLsv2i32
4772  { 1564, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1564 = VQRSHLsv2i64
4773  { 1565, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1565 = VQRSHLsv4i16
4774  { 1566, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1566 = VQRSHLsv4i32
4775  { 1567, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1567 = VQRSHLsv8i16
4776  { 1568, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1568 = VQRSHLsv8i8
4777  { 1569, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1569 = VQRSHLuv16i8
4778  { 1570, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1570 = VQRSHLuv1i64
4779  { 1571, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1571 = VQRSHLuv2i32
4780  { 1572, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1572 = VQRSHLuv2i64
4781  { 1573, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1573 = VQRSHLuv4i16
4782  { 1574, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1574 = VQRSHLuv4i32
4783  { 1575, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1575 = VQRSHLuv8i16
4784  { 1576, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1576 = VQRSHLuv8i8
4785  { 1577, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1577 = VQRSHRNsv2i32
4786  { 1578, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1578 = VQRSHRNsv4i16
4787  { 1579, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1579 = VQRSHRNsv8i8
4788  { 1580, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1580 = VQRSHRNuv2i32
4789  { 1581, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1581 = VQRSHRNuv4i16
4790  { 1582, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1582 = VQRSHRNuv8i8
4791  { 1583, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1583 = VQRSHRUNv2i32
4792  { 1584, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1584 = VQRSHRUNv4i16
4793  { 1585, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1585 = VQRSHRUNv8i8
4794  { 1586, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1586 = VQSHLsiv16i8
4795  { 1587, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1587 = VQSHLsiv1i64
4796  { 1588, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1588 = VQSHLsiv2i32
4797  { 1589, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1589 = VQSHLsiv2i64
4798  { 1590, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1590 = VQSHLsiv4i16
4799  { 1591, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1591 = VQSHLsiv4i32
4800  { 1592, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1592 = VQSHLsiv8i16
4801  { 1593, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1593 = VQSHLsiv8i8
4802  { 1594, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1594 = VQSHLsuv16i8
4803  { 1595, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1595 = VQSHLsuv1i64
4804  { 1596, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1596 = VQSHLsuv2i32
4805  { 1597, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1597 = VQSHLsuv2i64
4806  { 1598, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1598 = VQSHLsuv4i16
4807  { 1599, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1599 = VQSHLsuv4i32
4808  { 1600, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1600 = VQSHLsuv8i16
4809  { 1601, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1601 = VQSHLsuv8i8
4810  { 1602, 5, 1, 394, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1602 = VQSHLsv16i8
4811  { 1603, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1603 = VQSHLsv1i64
4812  { 1604, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1604 = VQSHLsv2i32
4813  { 1605, 5, 1, 394, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1605 = VQSHLsv2i64
4814  { 1606, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1606 = VQSHLsv4i16
4815  { 1607, 5, 1, 394, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1607 = VQSHLsv4i32
4816  { 1608, 5, 1, 394, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1608 = VQSHLsv8i16
4817  { 1609, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1609 = VQSHLsv8i8
4818  { 1610, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1610 = VQSHLuiv16i8
4819  { 1611, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1611 = VQSHLuiv1i64
4820  { 1612, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1612 = VQSHLuiv2i32
4821  { 1613, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1613 = VQSHLuiv2i64
4822  { 1614, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1614 = VQSHLuiv4i16
4823  { 1615, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1615 = VQSHLuiv4i32
4824  { 1616, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1616 = VQSHLuiv8i16
4825  { 1617, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1617 = VQSHLuiv8i8
4826  { 1618, 5, 1, 394, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1618 = VQSHLuv16i8
4827  { 1619, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1619 = VQSHLuv1i64
4828  { 1620, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1620 = VQSHLuv2i32
4829  { 1621, 5, 1, 394, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1621 = VQSHLuv2i64
4830  { 1622, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1622 = VQSHLuv4i16
4831  { 1623, 5, 1, 394, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1623 = VQSHLuv4i32
4832  { 1624, 5, 1, 394, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1624 = VQSHLuv8i16
4833  { 1625, 5, 1, 393, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1625 = VQSHLuv8i8
4834  { 1626, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1626 = VQSHRNsv2i32
4835  { 1627, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1627 = VQSHRNsv4i16
4836  { 1628, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1628 = VQSHRNsv8i8
4837  { 1629, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1629 = VQSHRNuv2i32
4838  { 1630, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1630 = VQSHRNuv4i16
4839  { 1631, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1631 = VQSHRNuv8i8
4840  { 1632, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1632 = VQSHRUNv2i32
4841  { 1633, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1633 = VQSHRUNv4i16
4842  { 1634, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1634 = VQSHRUNv8i8
4843  { 1635, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1635 = VQSUBsv16i8
4844  { 1636, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1636 = VQSUBsv1i64
4845  { 1637, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1637 = VQSUBsv2i32
4846  { 1638, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1638 = VQSUBsv2i64
4847  { 1639, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1639 = VQSUBsv4i16
4848  { 1640, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1640 = VQSUBsv4i32
4849  { 1641, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1641 = VQSUBsv8i16
4850  { 1642, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1642 = VQSUBsv8i8
4851  { 1643, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1643 = VQSUBuv16i8
4852  { 1644, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1644 = VQSUBuv1i64
4853  { 1645, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1645 = VQSUBuv2i32
4854  { 1646, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1646 = VQSUBuv2i64
4855  { 1647, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1647 = VQSUBuv4i16
4856  { 1648, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1648 = VQSUBuv4i32
4857  { 1649, 5, 1, 408, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1649 = VQSUBuv8i16
4858  { 1650, 5, 1, 409, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1650 = VQSUBuv8i8
4859  { 1651, 5, 1, 424, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136,0,nullptr }, // Inst #1651 = VRADDHNv2i32
4860  { 1652, 5, 1, 424, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136,0,nullptr }, // Inst #1652 = VRADDHNv4i16
4861  { 1653, 5, 1, 424, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo136,0,nullptr }, // Inst #1653 = VRADDHNv8i8
4862  { 1654, 4, 1, 419, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1654 = VRECPEd
4863  { 1655, 4, 1, 419, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1655 = VRECPEfd
4864  { 1656, 4, 1, 420, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1656 = VRECPEfq
4865  { 1657, 4, 1, 420, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1657 = VRECPEq
4866  { 1658, 5, 1, 449, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1658 = VRECPSfd
4867  { 1659, 5, 1, 450, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1659 = VRECPSfq
4868  { 1660, 4, 1, 398, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1660 = VREV16d8
4869  { 1661, 4, 1, 399, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1661 = VREV16q8
4870  { 1662, 4, 1, 398, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1662 = VREV32d16
4871  { 1663, 4, 1, 398, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1663 = VREV32d8
4872  { 1664, 4, 1, 399, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1664 = VREV32q16
4873  { 1665, 4, 1, 399, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1665 = VREV32q8
4874  { 1666, 4, 1, 398, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1666 = VREV64d16
4875  { 1667, 4, 1, 398, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1667 = VREV64d32
4876  { 1668, 4, 1, 398, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1668 = VREV64d8
4877  { 1669, 4, 1, 399, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1669 = VREV64q16
4878  { 1670, 4, 1, 399, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1670 = VREV64q32
4879  { 1671, 4, 1, 399, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1671 = VREV64q8
4880  { 1672, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1672 = VRHADDsv16i8
4881  { 1673, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1673 = VRHADDsv2i32
4882  { 1674, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1674 = VRHADDsv4i16
4883  { 1675, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1675 = VRHADDsv4i32
4884  { 1676, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1676 = VRHADDsv8i16
4885  { 1677, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1677 = VRHADDsv8i8
4886  { 1678, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1678 = VRHADDuv16i8
4887  { 1679, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1679 = VRHADDuv2i32
4888  { 1680, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1680 = VRHADDuv4i16
4889  { 1681, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1681 = VRHADDuv4i32
4890  { 1682, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1682 = VRHADDuv8i16
4891  { 1683, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1683 = VRHADDuv8i8
4892  { 1684, 2, 1, 0, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #1684 = VRINTAD
4893  { 1685, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #1685 = VRINTAND
4894  { 1686, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #1686 = VRINTANQ
4895  { 1687, 2, 1, 0, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1687 = VRINTAS
4896  { 1688, 2, 1, 0, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #1688 = VRINTMD
4897  { 1689, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #1689 = VRINTMND
4898  { 1690, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #1690 = VRINTMNQ
4899  { 1691, 2, 1, 0, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1691 = VRINTMS
4900  { 1692, 2, 1, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #1692 = VRINTND
4901  { 1693, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #1693 = VRINTNND
4902  { 1694, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #1694 = VRINTNNQ
4903  { 1695, 2, 1, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1695 = VRINTNS
4904  { 1696, 2, 1, 0, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #1696 = VRINTPD
4905  { 1697, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #1697 = VRINTPND
4906  { 1698, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #1698 = VRINTPNQ
4907  { 1699, 2, 1, 0, 4, 0, 0x8780ULL, nullptr, nullptr, OperandInfo145,0,nullptr }, // Inst #1699 = VRINTPS
4908  { 1700, 4, 1, 0, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1700 = VRINTRD
4909  { 1701, 4, 1, 0, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #1701 = VRINTRS
4910  { 1702, 4, 1, 0, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1702 = VRINTXD
4911  { 1703, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #1703 = VRINTXND
4912  { 1704, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #1704 = VRINTXNQ
4913  { 1705, 4, 1, 0, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #1705 = VRINTXS
4914  { 1706, 4, 1, 0, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1706 = VRINTZD
4915  { 1707, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo143,0,nullptr }, // Inst #1707 = VRINTZND
4916  { 1708, 2, 1, 0, 4, 0, 0x11000ULL, nullptr, nullptr, OperandInfo26,0,nullptr }, // Inst #1708 = VRINTZNQ
4917  { 1709, 4, 1, 0, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #1709 = VRINTZS
4918  { 1710, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1710 = VRSHLsv16i8
4919  { 1711, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1711 = VRSHLsv1i64
4920  { 1712, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1712 = VRSHLsv2i32
4921  { 1713, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1713 = VRSHLsv2i64
4922  { 1714, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1714 = VRSHLsv4i16
4923  { 1715, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1715 = VRSHLsv4i32
4924  { 1716, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1716 = VRSHLsv8i16
4925  { 1717, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1717 = VRSHLsv8i8
4926  { 1718, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1718 = VRSHLuv16i8
4927  { 1719, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1719 = VRSHLuv1i64
4928  { 1720, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1720 = VRSHLuv2i32
4929  { 1721, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1721 = VRSHLuv2i64
4930  { 1722, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1722 = VRSHLuv4i16
4931  { 1723, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1723 = VRSHLuv4i32
4932  { 1724, 5, 1, 417, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1724 = VRSHLuv8i16
4933  { 1725, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1725 = VRSHLuv8i8
4934  { 1726, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1726 = VRSHRNv2i32
4935  { 1727, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1727 = VRSHRNv4i16
4936  { 1728, 5, 1, 423, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1728 = VRSHRNv8i8
4937  { 1729, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1729 = VRSHRsv16i8
4938  { 1730, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #1730 = VRSHRsv1i64
4939  { 1731, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #1731 = VRSHRsv2i32
4940  { 1732, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1732 = VRSHRsv2i64
4941  { 1733, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #1733 = VRSHRsv4i16
4942  { 1734, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1734 = VRSHRsv4i32
4943  { 1735, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1735 = VRSHRsv8i16
4944  { 1736, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #1736 = VRSHRsv8i8
4945  { 1737, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1737 = VRSHRuv16i8
4946  { 1738, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #1738 = VRSHRuv1i64
4947  { 1739, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #1739 = VRSHRuv2i32
4948  { 1740, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1740 = VRSHRuv2i64
4949  { 1741, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #1741 = VRSHRuv4i16
4950  { 1742, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1742 = VRSHRuv4i32
4951  { 1743, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1743 = VRSHRuv8i16
4952  { 1744, 5, 1, 418, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #1744 = VRSHRuv8i8
4953  { 1745, 4, 1, 419, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1745 = VRSQRTEd
4954  { 1746, 4, 1, 419, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1746 = VRSQRTEfd
4955  { 1747, 4, 1, 420, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1747 = VRSQRTEfq
4956  { 1748, 4, 1, 420, 4, 0|(1<<MCID_Predicable), 0x11000ULL, nullptr, nullptr, OperandInfo135,0,nullptr }, // Inst #1748 = VRSQRTEq
4957  { 1749, 5, 1, 449, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1749 = VRSQRTSfd
4958  { 1750, 5, 1, 450, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1750 = VRSQRTSfq
4959  { 1751, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1751 = VRSRAsv16i8
4960  { 1752, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1752 = VRSRAsv1i64
4961  { 1753, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1753 = VRSRAsv2i32
4962  { 1754, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1754 = VRSRAsv2i64
4963  { 1755, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1755 = VRSRAsv4i16
4964  { 1756, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1756 = VRSRAsv4i32
4965  { 1757, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1757 = VRSRAsv8i16
4966  { 1758, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1758 = VRSRAsv8i8
4967  { 1759, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1759 = VRSRAuv16i8
4968  { 1760, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1760 = VRSRAuv1i64
4969  { 1761, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1761 = VRSRAuv2i32
4970  { 1762, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1762 = VRSRAuv2i64
4971  { 1763, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1763 = VRSRAuv4i16
4972  { 1764, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1764 = VRSRAuv4i32
4973  { 1765, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1765 = VRSRAuv8i16
4974  { 1766, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1766 = VRSRAuv8i8
4975  { 1767, 5, 1, 424, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136,0,nullptr }, // Inst #1767 = VRSUBHNv2i32
4976  { 1768, 5, 1, 424, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136,0,nullptr }, // Inst #1768 = VRSUBHNv4i16
4977  { 1769, 5, 1, 424, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136,0,nullptr }, // Inst #1769 = VRSUBHNv8i8
4978  { 1770, 3, 1, 0, 4, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo194,0,nullptr }, // Inst #1770 = VSELEQD
4979  { 1771, 3, 1, 0, 4, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo196,0,nullptr }, // Inst #1771 = VSELEQS
4980  { 1772, 3, 1, 0, 4, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo194,0,nullptr }, // Inst #1772 = VSELGED
4981  { 1773, 3, 1, 0, 4, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo196,0,nullptr }, // Inst #1773 = VSELGES
4982  { 1774, 3, 1, 0, 4, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo194,0,nullptr }, // Inst #1774 = VSELGTD
4983  { 1775, 3, 1, 0, 4, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo196,0,nullptr }, // Inst #1775 = VSELGTS
4984  { 1776, 3, 1, 0, 4, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo194,0,nullptr }, // Inst #1776 = VSELVSD
4985  { 1777, 3, 1, 0, 4, 0, 0x8800ULL, ImplicitList1, nullptr, OperandInfo196,0,nullptr }, // Inst #1777 = VSELVSS
4986  { 1778, 6, 1, 499, 4, 0|(1<<MCID_Predicable), 0x10e00ULL, nullptr, nullptr, OperandInfo227,0,nullptr }, // Inst #1778 = VSETLNi16
4987  { 1779, 6, 1, 499, 4, 0|(1<<MCID_Predicable)|(1<<MCID_InsertSubreg), 0x10e00ULL, nullptr, nullptr, OperandInfo227,0,nullptr }, // Inst #1779 = VSETLNi32
4988  { 1780, 6, 1, 499, 4, 0|(1<<MCID_Predicable), 0x10e00ULL, nullptr, nullptr, OperandInfo227,0,nullptr }, // Inst #1780 = VSETLNi8
4989  { 1781, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #1781 = VSHLLi16
4990  { 1782, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #1782 = VSHLLi32
4991  { 1783, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #1783 = VSHLLi8
4992  { 1784, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #1784 = VSHLLsv2i64
4993  { 1785, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #1785 = VSHLLsv4i32
4994  { 1786, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #1786 = VSHLLsv8i16
4995  { 1787, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #1787 = VSHLLuv2i64
4996  { 1788, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #1788 = VSHLLuv4i32
4997  { 1789, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo154,0,nullptr }, // Inst #1789 = VSHLLuv8i16
4998  { 1790, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1790 = VSHLiv16i8
4999  { 1791, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1791 = VSHLiv1i64
5000  { 1792, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1792 = VSHLiv2i32
5001  { 1793, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1793 = VSHLiv2i64
5002  { 1794, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1794 = VSHLiv4i16
5003  { 1795, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1795 = VSHLiv4i32
5004  { 1796, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo223,0,nullptr }, // Inst #1796 = VSHLiv8i16
5005  { 1797, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo224,0,nullptr }, // Inst #1797 = VSHLiv8i8
5006  { 1798, 5, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1798 = VSHLsv16i8
5007  { 1799, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1799 = VSHLsv1i64
5008  { 1800, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1800 = VSHLsv2i32
5009  { 1801, 5, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1801 = VSHLsv2i64
5010  { 1802, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1802 = VSHLsv4i16
5011  { 1803, 5, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1803 = VSHLsv4i32
5012  { 1804, 5, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1804 = VSHLsv8i16
5013  { 1805, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1805 = VSHLsv8i8
5014  { 1806, 5, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1806 = VSHLuv16i8
5015  { 1807, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1807 = VSHLuv1i64
5016  { 1808, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1808 = VSHLuv2i32
5017  { 1809, 5, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1809 = VSHLuv2i64
5018  { 1810, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1810 = VSHLuv4i16
5019  { 1811, 5, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1811 = VSHLuv4i32
5020  { 1812, 5, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #1812 = VSHLuv8i16
5021  { 1813, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11300ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #1813 = VSHLuv8i8
5022  { 1814, 5, 1, 422, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1814 = VSHRNv2i32
5023  { 1815, 5, 1, 422, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1815 = VSHRNv4i16
5024  { 1816, 5, 1, 422, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo222,0,nullptr }, // Inst #1816 = VSHRNv8i8
5025  { 1817, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1817 = VSHRsv16i8
5026  { 1818, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #1818 = VSHRsv1i64
5027  { 1819, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #1819 = VSHRsv2i32
5028  { 1820, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1820 = VSHRsv2i64
5029  { 1821, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #1821 = VSHRsv4i16
5030  { 1822, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1822 = VSHRsv4i32
5031  { 1823, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1823 = VSHRsv8i16
5032  { 1824, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #1824 = VSHRsv8i8
5033  { 1825, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1825 = VSHRuv16i8
5034  { 1826, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #1826 = VSHRuv1i64
5035  { 1827, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #1827 = VSHRuv2i32
5036  { 1828, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1828 = VSHRuv2i64
5037  { 1829, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #1829 = VSHRuv4i16
5038  { 1830, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1830 = VSHRuv4i32
5039  { 1831, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo150,0,nullptr }, // Inst #1831 = VSHRuv8i16
5040  { 1832, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo149,0,nullptr }, // Inst #1832 = VSHRuv8i8
5041  { 1833, 5, 1, 189, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo228,0,nullptr }, // Inst #1833 = VSHTOD
5042  { 1834, 5, 1, 190, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo229,0,nullptr }, // Inst #1834 = VSHTOS
5043  { 1835, 4, 1, 481, 4, 0|(1<<MCID_Predicable), 0x8880ULL, nullptr, nullptr, OperandInfo147,0,nullptr }, // Inst #1835 = VSITOD
5044  { 1836, 4, 1, 482, 4, 0|(1<<MCID_Predicable), 0x28880ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #1836 = VSITOS
5045  { 1837, 6, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo230,0,nullptr }, // Inst #1837 = VSLIv16i8
5046  { 1838, 6, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo231,0,nullptr }, // Inst #1838 = VSLIv1i64
5047  { 1839, 6, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo231,0,nullptr }, // Inst #1839 = VSLIv2i32
5048  { 1840, 6, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo230,0,nullptr }, // Inst #1840 = VSLIv2i64
5049  { 1841, 6, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo231,0,nullptr }, // Inst #1841 = VSLIv4i16
5050  { 1842, 6, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo230,0,nullptr }, // Inst #1842 = VSLIv4i32
5051  { 1843, 6, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo230,0,nullptr }, // Inst #1843 = VSLIv8i16
5052  { 1844, 6, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11180ULL, nullptr, nullptr, OperandInfo231,0,nullptr }, // Inst #1844 = VSLIv8i8
5053  { 1845, 5, 1, 189, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo228,0,nullptr }, // Inst #1845 = VSLTOD
5054  { 1846, 5, 1, 190, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo229,0,nullptr }, // Inst #1846 = VSLTOS
5055  { 1847, 4, 1, 589, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo133,0,nullptr }, // Inst #1847 = VSQRTD
5056  { 1848, 4, 1, 587, 4, 0|(1<<MCID_Predicable), 0x8780ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #1848 = VSQRTS
5057  { 1849, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1849 = VSRAsv16i8
5058  { 1850, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1850 = VSRAsv1i64
5059  { 1851, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1851 = VSRAsv2i32
5060  { 1852, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1852 = VSRAsv2i64
5061  { 1853, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1853 = VSRAsv4i16
5062  { 1854, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1854 = VSRAsv4i32
5063  { 1855, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1855 = VSRAsv8i16
5064  { 1856, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1856 = VSRAsv8i8
5065  { 1857, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1857 = VSRAuv16i8
5066  { 1858, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1858 = VSRAuv1i64
5067  { 1859, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1859 = VSRAuv2i32
5068  { 1860, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1860 = VSRAuv2i64
5069  { 1861, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1861 = VSRAuv4i16
5070  { 1862, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1862 = VSRAuv4i32
5071  { 1863, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1863 = VSRAuv8i16
5072  { 1864, 6, 1, 412, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1864 = VSRAuv8i8
5073  { 1865, 6, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1865 = VSRIv16i8
5074  { 1866, 6, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1866 = VSRIv1i64
5075  { 1867, 6, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1867 = VSRIv2i32
5076  { 1868, 6, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1868 = VSRIv2i64
5077  { 1869, 6, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1869 = VSRIv4i16
5078  { 1870, 6, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1870 = VSRIv4i32
5079  { 1871, 6, 1, 392, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo225,0,nullptr }, // Inst #1871 = VSRIv8i16
5080  { 1872, 6, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11200ULL, nullptr, nullptr, OperandInfo226,0,nullptr }, // Inst #1872 = VSRIv8i8
5081  { 1873, 6, 0, 578, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo232,0,nullptr }, // Inst #1873 = VST1LNd16
5082  { 1874, 8, 1, 579, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #1874 = VST1LNd16_UPD
5083  { 1875, 6, 0, 578, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo232,0,nullptr }, // Inst #1875 = VST1LNd32
5084  { 1876, 8, 1, 579, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #1876 = VST1LNd32_UPD
5085  { 1877, 6, 0, 578, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo232,0,nullptr }, // Inst #1877 = VST1LNd8
5086  { 1878, 8, 1, 579, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, nullptr, nullptr, OperandInfo233,0,nullptr }, // Inst #1878 = VST1LNd8_UPD
5087  { 1879, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1879 = VST1LNdAsm_16
5088  { 1880, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1880 = VST1LNdAsm_32
5089  { 1881, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1881 = VST1LNdAsm_8
5090  { 1882, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1882 = VST1LNdWB_fixed_Asm_16
5091  { 1883, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1883 = VST1LNdWB_fixed_Asm_32
5092  { 1884, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1884 = VST1LNdWB_fixed_Asm_8
5093  { 1885, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1885 = VST1LNdWB_register_Asm_16
5094  { 1886, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1886 = VST1LNdWB_register_Asm_32
5095  { 1887, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1887 = VST1LNdWB_register_Asm_8
5096  { 1888, 6, 0, 578, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1888 = VST1LNq16Pseudo
5097  { 1889, 8, 1, 579, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1889 = VST1LNq16Pseudo_UPD
5098  { 1890, 6, 0, 578, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1890 = VST1LNq32Pseudo
5099  { 1891, 8, 1, 579, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1891 = VST1LNq32Pseudo_UPD
5100  { 1892, 6, 0, 578, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1892 = VST1LNq8Pseudo
5101  { 1893, 8, 1, 579, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1893 = VST1LNq8Pseudo_UPD
5102  { 1894, 5, 0, 559, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #1894 = VST1d16
5103  { 1895, 5, 0, 566, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #1895 = VST1d16Q
5104  { 1896, 6, 1, 567, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #1896 = VST1d16Qwb_fixed
5105  { 1897, 7, 1, 567, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #1897 = VST1d16Qwb_register
5106  { 1898, 5, 0, 563, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #1898 = VST1d16T
5107  { 1899, 6, 1, 564, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #1899 = VST1d16Twb_fixed
5108  { 1900, 7, 1, 564, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #1900 = VST1d16Twb_register
5109  { 1901, 6, 1, 561, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #1901 = VST1d16wb_fixed
5110  { 1902, 7, 1, 561, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #1902 = VST1d16wb_register
5111  { 1903, 5, 0, 559, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #1903 = VST1d32
5112  { 1904, 5, 0, 566, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #1904 = VST1d32Q
5113  { 1905, 6, 1, 567, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #1905 = VST1d32Qwb_fixed
5114  { 1906, 7, 1, 567, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #1906 = VST1d32Qwb_register
5115  { 1907, 5, 0, 563, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #1907 = VST1d32T
5116  { 1908, 6, 1, 564, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #1908 = VST1d32Twb_fixed
5117  { 1909, 7, 1, 564, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #1909 = VST1d32Twb_register
5118  { 1910, 6, 1, 561, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #1910 = VST1d32wb_fixed
5119  { 1911, 7, 1, 561, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #1911 = VST1d32wb_register
5120  { 1912, 5, 0, 559, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #1912 = VST1d64
5121  { 1913, 5, 0, 566, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #1913 = VST1d64Q
5122  { 1914, 5, 0, 566, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #1914 = VST1d64QPseudo
5123  { 1915, 6, 1, 568, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo240,0,nullptr }, // Inst #1915 = VST1d64QPseudoWB_fixed
5124  { 1916, 7, 1, 568, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #1916 = VST1d64QPseudoWB_register
5125  { 1917, 6, 1, 567, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #1917 = VST1d64Qwb_fixed
5126  { 1918, 7, 1, 567, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #1918 = VST1d64Qwb_register
5127  { 1919, 5, 0, 563, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #1919 = VST1d64T
5128  { 1920, 5, 0, 563, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #1920 = VST1d64TPseudo
5129  { 1921, 6, 1, 565, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo240,0,nullptr }, // Inst #1921 = VST1d64TPseudoWB_fixed
5130  { 1922, 7, 1, 565, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #1922 = VST1d64TPseudoWB_register
5131  { 1923, 6, 1, 564, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #1923 = VST1d64Twb_fixed
5132  { 1924, 7, 1, 564, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #1924 = VST1d64Twb_register
5133  { 1925, 6, 1, 561, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #1925 = VST1d64wb_fixed
5134  { 1926, 7, 1, 561, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #1926 = VST1d64wb_register
5135  { 1927, 5, 0, 559, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #1927 = VST1d8
5136  { 1928, 5, 0, 566, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #1928 = VST1d8Q
5137  { 1929, 6, 1, 567, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #1929 = VST1d8Qwb_fixed
5138  { 1930, 7, 1, 567, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #1930 = VST1d8Qwb_register
5139  { 1931, 5, 0, 563, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #1931 = VST1d8T
5140  { 1932, 6, 1, 564, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #1932 = VST1d8Twb_fixed
5141  { 1933, 7, 1, 564, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #1933 = VST1d8Twb_register
5142  { 1934, 6, 1, 561, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #1934 = VST1d8wb_fixed
5143  { 1935, 7, 1, 561, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #1935 = VST1d8wb_register
5144  { 1936, 5, 0, 560, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242,0,nullptr }, // Inst #1936 = VST1q16
5145  { 1937, 6, 1, 562, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243,0,nullptr }, // Inst #1937 = VST1q16wb_fixed
5146  { 1938, 7, 1, 562, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #1938 = VST1q16wb_register
5147  { 1939, 5, 0, 560, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242,0,nullptr }, // Inst #1939 = VST1q32
5148  { 1940, 6, 1, 562, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243,0,nullptr }, // Inst #1940 = VST1q32wb_fixed
5149  { 1941, 7, 1, 562, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #1941 = VST1q32wb_register
5150  { 1942, 5, 0, 560, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242,0,nullptr }, // Inst #1942 = VST1q64
5151  { 1943, 6, 1, 562, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243,0,nullptr }, // Inst #1943 = VST1q64wb_fixed
5152  { 1944, 7, 1, 562, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #1944 = VST1q64wb_register
5153  { 1945, 5, 0, 560, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242,0,nullptr }, // Inst #1945 = VST1q8
5154  { 1946, 6, 1, 562, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243,0,nullptr }, // Inst #1946 = VST1q8wb_fixed
5155  { 1947, 7, 1, 562, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #1947 = VST1q8wb_register
5156  { 1948, 7, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo245,0,nullptr }, // Inst #1948 = VST2LNd16
5157  { 1949, 6, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1949 = VST2LNd16Pseudo
5158  { 1950, 8, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1950 = VST2LNd16Pseudo_UPD
5159  { 1951, 9, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo246,0,nullptr }, // Inst #1951 = VST2LNd16_UPD
5160  { 1952, 7, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo245,0,nullptr }, // Inst #1952 = VST2LNd32
5161  { 1953, 6, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1953 = VST2LNd32Pseudo
5162  { 1954, 8, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1954 = VST2LNd32Pseudo_UPD
5163  { 1955, 9, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo246,0,nullptr }, // Inst #1955 = VST2LNd32_UPD
5164  { 1956, 7, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo245,0,nullptr }, // Inst #1956 = VST2LNd8
5165  { 1957, 6, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo234,0,nullptr }, // Inst #1957 = VST2LNd8Pseudo
5166  { 1958, 8, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo235,0,nullptr }, // Inst #1958 = VST2LNd8Pseudo_UPD
5167  { 1959, 9, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo246,0,nullptr }, // Inst #1959 = VST2LNd8_UPD
5168  { 1960, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1960 = VST2LNdAsm_16
5169  { 1961, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1961 = VST2LNdAsm_32
5170  { 1962, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1962 = VST2LNdAsm_8
5171  { 1963, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1963 = VST2LNdWB_fixed_Asm_16
5172  { 1964, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1964 = VST2LNdWB_fixed_Asm_32
5173  { 1965, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1965 = VST2LNdWB_fixed_Asm_8
5174  { 1966, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1966 = VST2LNdWB_register_Asm_16
5175  { 1967, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1967 = VST2LNdWB_register_Asm_32
5176  { 1968, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1968 = VST2LNdWB_register_Asm_8
5177  { 1969, 7, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo245,0,nullptr }, // Inst #1969 = VST2LNq16
5178  { 1970, 6, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo247,0,nullptr }, // Inst #1970 = VST2LNq16Pseudo
5179  { 1971, 8, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo248,0,nullptr }, // Inst #1971 = VST2LNq16Pseudo_UPD
5180  { 1972, 9, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo246,0,nullptr }, // Inst #1972 = VST2LNq16_UPD
5181  { 1973, 7, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo245,0,nullptr }, // Inst #1973 = VST2LNq32
5182  { 1974, 6, 0, 580, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo247,0,nullptr }, // Inst #1974 = VST2LNq32Pseudo
5183  { 1975, 8, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo248,0,nullptr }, // Inst #1975 = VST2LNq32Pseudo_UPD
5184  { 1976, 9, 1, 581, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo246,0,nullptr }, // Inst #1976 = VST2LNq32_UPD
5185  { 1977, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1977 = VST2LNqAsm_16
5186  { 1978, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1978 = VST2LNqAsm_32
5187  { 1979, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1979 = VST2LNqWB_fixed_Asm_16
5188  { 1980, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #1980 = VST2LNqWB_fixed_Asm_32
5189  { 1981, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1981 = VST2LNqWB_register_Asm_16
5190  { 1982, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #1982 = VST2LNqWB_register_Asm_32
5191  { 1983, 5, 0, 569, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242,0,nullptr }, // Inst #1983 = VST2b16
5192  { 1984, 6, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243,0,nullptr }, // Inst #1984 = VST2b16wb_fixed
5193  { 1985, 7, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #1985 = VST2b16wb_register
5194  { 1986, 5, 0, 569, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242,0,nullptr }, // Inst #1986 = VST2b32
5195  { 1987, 6, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243,0,nullptr }, // Inst #1987 = VST2b32wb_fixed
5196  { 1988, 7, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #1988 = VST2b32wb_register
5197  { 1989, 5, 0, 569, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242,0,nullptr }, // Inst #1989 = VST2b8
5198  { 1990, 6, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243,0,nullptr }, // Inst #1990 = VST2b8wb_fixed
5199  { 1991, 7, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #1991 = VST2b8wb_register
5200  { 1992, 5, 0, 569, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242,0,nullptr }, // Inst #1992 = VST2d16
5201  { 1993, 6, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243,0,nullptr }, // Inst #1993 = VST2d16wb_fixed
5202  { 1994, 7, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #1994 = VST2d16wb_register
5203  { 1995, 5, 0, 569, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242,0,nullptr }, // Inst #1995 = VST2d32
5204  { 1996, 6, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243,0,nullptr }, // Inst #1996 = VST2d32wb_fixed
5205  { 1997, 7, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #1997 = VST2d32wb_register
5206  { 1998, 5, 0, 569, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo242,0,nullptr }, // Inst #1998 = VST2d8
5207  { 1999, 6, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo243,0,nullptr }, // Inst #1999 = VST2d8wb_fixed
5208  { 2000, 7, 1, 570, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo244,0,nullptr }, // Inst #2000 = VST2d8wb_register
5209  { 2001, 5, 0, 571, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #2001 = VST2q16
5210  { 2002, 5, 0, 571, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #2002 = VST2q16Pseudo
5211  { 2003, 6, 1, 572, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo240,0,nullptr }, // Inst #2003 = VST2q16PseudoWB_fixed
5212  { 2004, 7, 1, 572, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo249,0,nullptr }, // Inst #2004 = VST2q16PseudoWB_register
5213  { 2005, 6, 1, 573, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #2005 = VST2q16wb_fixed
5214  { 2006, 7, 1, 573, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #2006 = VST2q16wb_register
5215  { 2007, 5, 0, 571, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #2007 = VST2q32
5216  { 2008, 5, 0, 571, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #2008 = VST2q32Pseudo
5217  { 2009, 6, 1, 572, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo240,0,nullptr }, // Inst #2009 = VST2q32PseudoWB_fixed
5218  { 2010, 7, 1, 572, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo249,0,nullptr }, // Inst #2010 = VST2q32PseudoWB_register
5219  { 2011, 6, 1, 573, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #2011 = VST2q32wb_fixed
5220  { 2012, 7, 1, 573, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #2012 = VST2q32wb_register
5221  { 2013, 5, 0, 571, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo236,0,nullptr }, // Inst #2013 = VST2q8
5222  { 2014, 5, 0, 571, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #2014 = VST2q8Pseudo
5223  { 2015, 6, 1, 572, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo240,0,nullptr }, // Inst #2015 = VST2q8PseudoWB_fixed
5224  { 2016, 7, 1, 572, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo249,0,nullptr }, // Inst #2016 = VST2q8PseudoWB_register
5225  { 2017, 6, 1, 573, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo237,0,nullptr }, // Inst #2017 = VST2q8wb_fixed
5226  { 2018, 7, 1, 573, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo238,0,nullptr }, // Inst #2018 = VST2q8wb_register
5227  { 2019, 8, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo250,0,nullptr }, // Inst #2019 = VST3LNd16
5228  { 2020, 6, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo247,0,nullptr }, // Inst #2020 = VST3LNd16Pseudo
5229  { 2021, 8, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo248,0,nullptr }, // Inst #2021 = VST3LNd16Pseudo_UPD
5230  { 2022, 10, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo251,0,nullptr }, // Inst #2022 = VST3LNd16_UPD
5231  { 2023, 8, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo250,0,nullptr }, // Inst #2023 = VST3LNd32
5232  { 2024, 6, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo247,0,nullptr }, // Inst #2024 = VST3LNd32Pseudo
5233  { 2025, 8, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo248,0,nullptr }, // Inst #2025 = VST3LNd32Pseudo_UPD
5234  { 2026, 10, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo251,0,nullptr }, // Inst #2026 = VST3LNd32_UPD
5235  { 2027, 8, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo250,0,nullptr }, // Inst #2027 = VST3LNd8
5236  { 2028, 6, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo247,0,nullptr }, // Inst #2028 = VST3LNd8Pseudo
5237  { 2029, 8, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo248,0,nullptr }, // Inst #2029 = VST3LNd8Pseudo_UPD
5238  { 2030, 10, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo251,0,nullptr }, // Inst #2030 = VST3LNd8_UPD
5239  { 2031, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2031 = VST3LNdAsm_16
5240  { 2032, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2032 = VST3LNdAsm_32
5241  { 2033, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2033 = VST3LNdAsm_8
5242  { 2034, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2034 = VST3LNdWB_fixed_Asm_16
5243  { 2035, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2035 = VST3LNdWB_fixed_Asm_32
5244  { 2036, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2036 = VST3LNdWB_fixed_Asm_8
5245  { 2037, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #2037 = VST3LNdWB_register_Asm_16
5246  { 2038, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #2038 = VST3LNdWB_register_Asm_32
5247  { 2039, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #2039 = VST3LNdWB_register_Asm_8
5248  { 2040, 8, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo250,0,nullptr }, // Inst #2040 = VST3LNq16
5249  { 2041, 6, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo252,0,nullptr }, // Inst #2041 = VST3LNq16Pseudo
5250  { 2042, 8, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253,0,nullptr }, // Inst #2042 = VST3LNq16Pseudo_UPD
5251  { 2043, 10, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo251,0,nullptr }, // Inst #2043 = VST3LNq16_UPD
5252  { 2044, 8, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo250,0,nullptr }, // Inst #2044 = VST3LNq32
5253  { 2045, 6, 0, 582, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo252,0,nullptr }, // Inst #2045 = VST3LNq32Pseudo
5254  { 2046, 8, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253,0,nullptr }, // Inst #2046 = VST3LNq32Pseudo_UPD
5255  { 2047, 10, 1, 583, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo251,0,nullptr }, // Inst #2047 = VST3LNq32_UPD
5256  { 2048, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2048 = VST3LNqAsm_16
5257  { 2049, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2049 = VST3LNqAsm_32
5258  { 2050, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2050 = VST3LNqWB_fixed_Asm_16
5259  { 2051, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2051 = VST3LNqWB_fixed_Asm_32
5260  { 2052, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #2052 = VST3LNqWB_register_Asm_16
5261  { 2053, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #2053 = VST3LNqWB_register_Asm_32
5262  { 2054, 7, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo254,0,nullptr }, // Inst #2054 = VST3d16
5263  { 2055, 5, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #2055 = VST3d16Pseudo
5264  { 2056, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #2056 = VST3d16Pseudo_UPD
5265  { 2057, 9, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo255,0,nullptr }, // Inst #2057 = VST3d16_UPD
5266  { 2058, 7, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo254,0,nullptr }, // Inst #2058 = VST3d32
5267  { 2059, 5, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #2059 = VST3d32Pseudo
5268  { 2060, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #2060 = VST3d32Pseudo_UPD
5269  { 2061, 9, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo255,0,nullptr }, // Inst #2061 = VST3d32_UPD
5270  { 2062, 7, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo254,0,nullptr }, // Inst #2062 = VST3d8
5271  { 2063, 5, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #2063 = VST3d8Pseudo
5272  { 2064, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #2064 = VST3d8Pseudo_UPD
5273  { 2065, 9, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo255,0,nullptr }, // Inst #2065 = VST3d8_UPD
5274  { 2066, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2066 = VST3dAsm_16
5275  { 2067, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2067 = VST3dAsm_32
5276  { 2068, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2068 = VST3dAsm_8
5277  { 2069, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2069 = VST3dWB_fixed_Asm_16
5278  { 2070, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2070 = VST3dWB_fixed_Asm_32
5279  { 2071, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2071 = VST3dWB_fixed_Asm_8
5280  { 2072, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #2072 = VST3dWB_register_Asm_16
5281  { 2073, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #2073 = VST3dWB_register_Asm_32
5282  { 2074, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #2074 = VST3dWB_register_Asm_8
5283  { 2075, 7, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo254,0,nullptr }, // Inst #2075 = VST3q16
5284  { 2076, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2076 = VST3q16Pseudo_UPD
5285  { 2077, 9, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo255,0,nullptr }, // Inst #2077 = VST3q16_UPD
5286  { 2078, 5, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo257,0,nullptr }, // Inst #2078 = VST3q16oddPseudo
5287  { 2079, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2079 = VST3q16oddPseudo_UPD
5288  { 2080, 7, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo254,0,nullptr }, // Inst #2080 = VST3q32
5289  { 2081, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2081 = VST3q32Pseudo_UPD
5290  { 2082, 9, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo255,0,nullptr }, // Inst #2082 = VST3q32_UPD
5291  { 2083, 5, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo257,0,nullptr }, // Inst #2083 = VST3q32oddPseudo
5292  { 2084, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2084 = VST3q32oddPseudo_UPD
5293  { 2085, 7, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo254,0,nullptr }, // Inst #2085 = VST3q8
5294  { 2086, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2086 = VST3q8Pseudo_UPD
5295  { 2087, 9, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo255,0,nullptr }, // Inst #2087 = VST3q8_UPD
5296  { 2088, 5, 0, 574, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo257,0,nullptr }, // Inst #2088 = VST3q8oddPseudo
5297  { 2089, 7, 1, 575, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2089 = VST3q8oddPseudo_UPD
5298  { 2090, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2090 = VST3qAsm_16
5299  { 2091, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2091 = VST3qAsm_32
5300  { 2092, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2092 = VST3qAsm_8
5301  { 2093, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2093 = VST3qWB_fixed_Asm_16
5302  { 2094, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2094 = VST3qWB_fixed_Asm_32
5303  { 2095, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2095 = VST3qWB_fixed_Asm_8
5304  { 2096, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #2096 = VST3qWB_register_Asm_16
5305  { 2097, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #2097 = VST3qWB_register_Asm_32
5306  { 2098, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #2098 = VST3qWB_register_Asm_8
5307  { 2099, 9, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo258,0,nullptr }, // Inst #2099 = VST4LNd16
5308  { 2100, 6, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo247,0,nullptr }, // Inst #2100 = VST4LNd16Pseudo
5309  { 2101, 8, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo248,0,nullptr }, // Inst #2101 = VST4LNd16Pseudo_UPD
5310  { 2102, 11, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo259,0,nullptr }, // Inst #2102 = VST4LNd16_UPD
5311  { 2103, 9, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo258,0,nullptr }, // Inst #2103 = VST4LNd32
5312  { 2104, 6, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo247,0,nullptr }, // Inst #2104 = VST4LNd32Pseudo
5313  { 2105, 8, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo248,0,nullptr }, // Inst #2105 = VST4LNd32Pseudo_UPD
5314  { 2106, 11, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo259,0,nullptr }, // Inst #2106 = VST4LNd32_UPD
5315  { 2107, 9, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo258,0,nullptr }, // Inst #2107 = VST4LNd8
5316  { 2108, 6, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo247,0,nullptr }, // Inst #2108 = VST4LNd8Pseudo
5317  { 2109, 8, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo248,0,nullptr }, // Inst #2109 = VST4LNd8Pseudo_UPD
5318  { 2110, 11, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo259,0,nullptr }, // Inst #2110 = VST4LNd8_UPD
5319  { 2111, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2111 = VST4LNdAsm_16
5320  { 2112, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2112 = VST4LNdAsm_32
5321  { 2113, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2113 = VST4LNdAsm_8
5322  { 2114, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2114 = VST4LNdWB_fixed_Asm_16
5323  { 2115, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2115 = VST4LNdWB_fixed_Asm_32
5324  { 2116, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2116 = VST4LNdWB_fixed_Asm_8
5325  { 2117, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #2117 = VST4LNdWB_register_Asm_16
5326  { 2118, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #2118 = VST4LNdWB_register_Asm_32
5327  { 2119, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #2119 = VST4LNdWB_register_Asm_8
5328  { 2120, 9, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo258,0,nullptr }, // Inst #2120 = VST4LNq16
5329  { 2121, 6, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo252,0,nullptr }, // Inst #2121 = VST4LNq16Pseudo
5330  { 2122, 8, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253,0,nullptr }, // Inst #2122 = VST4LNq16Pseudo_UPD
5331  { 2123, 11, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo259,0,nullptr }, // Inst #2123 = VST4LNq16_UPD
5332  { 2124, 9, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo258,0,nullptr }, // Inst #2124 = VST4LNq32
5333  { 2125, 6, 0, 584, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo252,0,nullptr }, // Inst #2125 = VST4LNq32Pseudo
5334  { 2126, 8, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo253,0,nullptr }, // Inst #2126 = VST4LNq32Pseudo_UPD
5335  { 2127, 11, 1, 585, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo259,0,nullptr }, // Inst #2127 = VST4LNq32_UPD
5336  { 2128, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2128 = VST4LNqAsm_16
5337  { 2129, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2129 = VST4LNqAsm_32
5338  { 2130, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2130 = VST4LNqWB_fixed_Asm_16
5339  { 2131, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo167,0,nullptr }, // Inst #2131 = VST4LNqWB_fixed_Asm_32
5340  { 2132, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #2132 = VST4LNqWB_register_Asm_16
5341  { 2133, 7, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo168,0,nullptr }, // Inst #2133 = VST4LNqWB_register_Asm_32
5342  { 2134, 8, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo260,0,nullptr }, // Inst #2134 = VST4d16
5343  { 2135, 5, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #2135 = VST4d16Pseudo
5344  { 2136, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #2136 = VST4d16Pseudo_UPD
5345  { 2137, 10, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo261,0,nullptr }, // Inst #2137 = VST4d16_UPD
5346  { 2138, 8, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo260,0,nullptr }, // Inst #2138 = VST4d32
5347  { 2139, 5, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #2139 = VST4d32Pseudo
5348  { 2140, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #2140 = VST4d32Pseudo_UPD
5349  { 2141, 10, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo261,0,nullptr }, // Inst #2141 = VST4d32_UPD
5350  { 2142, 8, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo260,0,nullptr }, // Inst #2142 = VST4d8
5351  { 2143, 5, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo239,0,nullptr }, // Inst #2143 = VST4d8Pseudo
5352  { 2144, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo241,0,nullptr }, // Inst #2144 = VST4d8Pseudo_UPD
5353  { 2145, 10, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo261,0,nullptr }, // Inst #2145 = VST4d8_UPD
5354  { 2146, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2146 = VST4dAsm_16
5355  { 2147, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2147 = VST4dAsm_32
5356  { 2148, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2148 = VST4dAsm_8
5357  { 2149, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2149 = VST4dWB_fixed_Asm_16
5358  { 2150, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2150 = VST4dWB_fixed_Asm_32
5359  { 2151, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2151 = VST4dWB_fixed_Asm_8
5360  { 2152, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #2152 = VST4dWB_register_Asm_16
5361  { 2153, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #2153 = VST4dWB_register_Asm_32
5362  { 2154, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #2154 = VST4dWB_register_Asm_8
5363  { 2155, 8, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo260,0,nullptr }, // Inst #2155 = VST4q16
5364  { 2156, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2156 = VST4q16Pseudo_UPD
5365  { 2157, 10, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo261,0,nullptr }, // Inst #2157 = VST4q16_UPD
5366  { 2158, 5, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo257,0,nullptr }, // Inst #2158 = VST4q16oddPseudo
5367  { 2159, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2159 = VST4q16oddPseudo_UPD
5368  { 2160, 8, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo260,0,nullptr }, // Inst #2160 = VST4q32
5369  { 2161, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2161 = VST4q32Pseudo_UPD
5370  { 2162, 10, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo261,0,nullptr }, // Inst #2162 = VST4q32_UPD
5371  { 2163, 5, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo257,0,nullptr }, // Inst #2163 = VST4q32oddPseudo
5372  { 2164, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2164 = VST4q32oddPseudo_UPD
5373  { 2165, 8, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo260,0,nullptr }, // Inst #2165 = VST4q8
5374  { 2166, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2166 = VST4q8Pseudo_UPD
5375  { 2167, 10, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, nullptr, nullptr, OperandInfo261,0,nullptr }, // Inst #2167 = VST4q8_UPD
5376  { 2168, 5, 0, 576, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo257,0,nullptr }, // Inst #2168 = VST4q8oddPseudo
5377  { 2169, 7, 1, 577, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, nullptr, nullptr, OperandInfo256,0,nullptr }, // Inst #2169 = VST4q8oddPseudo_UPD
5378  { 2170, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2170 = VST4qAsm_16
5379  { 2171, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2171 = VST4qAsm_32
5380  { 2172, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2172 = VST4qAsm_8
5381  { 2173, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2173 = VST4qWB_fixed_Asm_16
5382  { 2174, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2174 = VST4qWB_fixed_Asm_32
5383  { 2175, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2175 = VST4qWB_fixed_Asm_8
5384  { 2176, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #2176 = VST4qWB_register_Asm_16
5385  { 2177, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #2177 = VST4qWB_register_Asm_32
5386  { 2178, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo181,0,nullptr }, // Inst #2178 = VST4qWB_register_Asm_8
5387  { 2179, 5, 1, 517, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x8be4ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2179 = VSTMDDB_UPD
5388  { 2180, 4, 0, 516, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x8b84ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #2180 = VSTMDIA
5389  { 2181, 5, 1, 517, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x8be4ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2181 = VSTMDIA_UPD
5390  { 2182, 4, 0, 513, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x18004ULL, nullptr, nullptr, OperandInfo192,0,nullptr }, // Inst #2182 = VSTMQIA
5391  { 2183, 5, 1, 517, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x18be4ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2183 = VSTMSDB_UPD
5392  { 2184, 4, 0, 516, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x18b84ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #2184 = VSTMSIA
5393  { 2185, 5, 1, 517, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x18be4ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2185 = VSTMSIA_UPD
5394  { 2186, 5, 0, 510, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x18b05ULL, nullptr, nullptr, OperandInfo159,0,nullptr }, // Inst #2186 = VSTRD
5395  { 2187, 5, 0, 511, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x18b05ULL, nullptr, nullptr, OperandInfo193,0,nullptr }, // Inst #2187 = VSTRS
5396  { 2188, 5, 1, 448, 4, 0|(1<<MCID_Predicable), 0x8800ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #2188 = VSUBD
5397  { 2189, 5, 1, 421, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136,0,nullptr }, // Inst #2189 = VSUBHNv2i32
5398  { 2190, 5, 1, 421, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136,0,nullptr }, // Inst #2190 = VSUBHNv4i16
5399  { 2191, 5, 1, 421, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo136,0,nullptr }, // Inst #2191 = VSUBHNv8i8
5400  { 2192, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #2192 = VSUBLsv2i64
5401  { 2193, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #2193 = VSUBLsv4i32
5402  { 2194, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #2194 = VSUBLsv8i16
5403  { 2195, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #2195 = VSUBLuv2i64
5404  { 2196, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #2196 = VSUBLuv4i32
5405  { 2197, 5, 1, 379, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo130,0,nullptr }, // Inst #2197 = VSUBLuv8i16
5406  { 2198, 5, 1, 445, 4, 0|(1<<MCID_Predicable), 0x28800ULL, nullptr, nullptr, OperandInfo137,0,nullptr }, // Inst #2198 = VSUBS
5407  { 2199, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo138,0,nullptr }, // Inst #2199 = VSUBWsv2i64
5408  { 2200, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo138,0,nullptr }, // Inst #2200 = VSUBWsv4i32
5409  { 2201, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo138,0,nullptr }, // Inst #2201 = VSUBWsv8i16
5410  { 2202, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo138,0,nullptr }, // Inst #2202 = VSUBWuv2i64
5411  { 2203, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo138,0,nullptr }, // Inst #2203 = VSUBWuv4i32
5412  { 2204, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo138,0,nullptr }, // Inst #2204 = VSUBWuv8i16
5413  { 2205, 5, 1, 442, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #2205 = VSUBfd
5414  { 2206, 5, 1, 443, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #2206 = VSUBfq
5415  { 2207, 5, 1, 395, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #2207 = VSUBv16i8
5416  { 2208, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #2208 = VSUBv1i64
5417  { 2209, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #2209 = VSUBv2i32
5418  { 2210, 5, 1, 395, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #2210 = VSUBv2i64
5419  { 2211, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #2211 = VSUBv4i16
5420  { 2212, 5, 1, 395, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #2212 = VSUBv4i32
5421  { 2213, 5, 1, 395, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #2213 = VSUBv8i16
5422  { 2214, 5, 1, 380, 4, 0|(1<<MCID_Predicable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #2214 = VSUBv8i8
5423  { 2215, 6, 2, 433, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo262,0,nullptr }, // Inst #2215 = VSWPd
5424  { 2216, 6, 2, 433, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo263,0,nullptr }, // Inst #2216 = VSWPq
5425  { 2217, 5, 1, 425, 4, 0|(1<<MCID_Predicable), 0x11480ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #2217 = VTBL1
5426  { 2218, 5, 1, 427, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo264,0,nullptr }, // Inst #2218 = VTBL2
5427  { 2219, 5, 1, 429, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #2219 = VTBL3
5428  { 2220, 5, 1, 429, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x10000ULL, nullptr, nullptr, OperandInfo265,0,nullptr }, // Inst #2220 = VTBL3Pseudo
5429  { 2221, 5, 1, 431, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #2221 = VTBL4
5430  { 2222, 5, 1, 431, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x10000ULL, nullptr, nullptr, OperandInfo265,0,nullptr }, // Inst #2222 = VTBL4Pseudo
5431  { 2223, 6, 1, 426, 4, 0|(1<<MCID_Predicable), 0x11480ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #2223 = VTBX1
5432  { 2224, 6, 1, 428, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo266,0,nullptr }, // Inst #2224 = VTBX2
5433  { 2225, 6, 1, 430, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #2225 = VTBX3
5434  { 2226, 6, 1, 430, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x10000ULL, nullptr, nullptr, OperandInfo267,0,nullptr }, // Inst #2226 = VTBX3Pseudo
5435  { 2227, 6, 1, 432, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, nullptr, nullptr, OperandInfo129,0,nullptr }, // Inst #2227 = VTBX4
5436  { 2228, 6, 1, 432, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x10000ULL, nullptr, nullptr, OperandInfo267,0,nullptr }, // Inst #2228 = VTBX4Pseudo
5437  { 2229, 5, 1, 483, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo228,0,nullptr }, // Inst #2229 = VTOSHD
5438  { 2230, 5, 1, 484, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo229,0,nullptr }, // Inst #2230 = VTOSHS
5439  { 2231, 4, 1, 485, 4, 0|(1<<MCID_Predicable), 0x8880ULL, ImplicitList10, nullptr, OperandInfo146,0,nullptr }, // Inst #2231 = VTOSIRD
5440  { 2232, 4, 1, 486, 4, 0|(1<<MCID_Predicable), 0x8880ULL, ImplicitList10, nullptr, OperandInfo134,0,nullptr }, // Inst #2232 = VTOSIRS
5441  { 2233, 4, 1, 485, 4, 0|(1<<MCID_Predicable), 0x8880ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #2233 = VTOSIZD
5442  { 2234, 4, 1, 486, 4, 0|(1<<MCID_Predicable), 0x28880ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #2234 = VTOSIZS
5443  { 2235, 5, 1, 483, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo228,0,nullptr }, // Inst #2235 = VTOSLD
5444  { 2236, 5, 1, 484, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo229,0,nullptr }, // Inst #2236 = VTOSLS
5445  { 2237, 5, 1, 483, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo228,0,nullptr }, // Inst #2237 = VTOUHD
5446  { 2238, 5, 1, 484, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo229,0,nullptr }, // Inst #2238 = VTOUHS
5447  { 2239, 4, 1, 485, 4, 0|(1<<MCID_Predicable), 0x8880ULL, ImplicitList10, nullptr, OperandInfo146,0,nullptr }, // Inst #2239 = VTOUIRD
5448  { 2240, 4, 1, 486, 4, 0|(1<<MCID_Predicable), 0x8880ULL, ImplicitList10, nullptr, OperandInfo134,0,nullptr }, // Inst #2240 = VTOUIRS
5449  { 2241, 4, 1, 485, 4, 0|(1<<MCID_Predicable), 0x8880ULL, nullptr, nullptr, OperandInfo146,0,nullptr }, // Inst #2241 = VTOUIZD
5450  { 2242, 4, 1, 486, 4, 0|(1<<MCID_Predicable), 0x28880ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #2242 = VTOUIZS
5451  { 2243, 5, 1, 483, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo228,0,nullptr }, // Inst #2243 = VTOULD
5452  { 2244, 5, 1, 484, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo229,0,nullptr }, // Inst #2244 = VTOULS
5453  { 2245, 6, 2, 434, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo262,0,nullptr }, // Inst #2245 = VTRNd16
5454  { 2246, 6, 2, 434, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo262,0,nullptr }, // Inst #2246 = VTRNd32
5455  { 2247, 6, 2, 434, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo262,0,nullptr }, // Inst #2247 = VTRNd8
5456  { 2248, 6, 2, 435, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo263,0,nullptr }, // Inst #2248 = VTRNq16
5457  { 2249, 6, 2, 435, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo263,0,nullptr }, // Inst #2249 = VTRNq32
5458  { 2250, 6, 2, 435, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo263,0,nullptr }, // Inst #2250 = VTRNq8
5459  { 2251, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #2251 = VTSTv16i8
5460  { 2252, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #2252 = VTSTv2i32
5461  { 2253, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #2253 = VTSTv4i16
5462  { 2254, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #2254 = VTSTv4i32
5463  { 2255, 5, 1, 386, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo132,0,nullptr }, // Inst #2255 = VTSTv8i16
5464  { 2256, 5, 1, 387, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, nullptr, nullptr, OperandInfo131,0,nullptr }, // Inst #2256 = VTSTv8i8
5465  { 2257, 5, 1, 189, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo228,0,nullptr }, // Inst #2257 = VUHTOD
5466  { 2258, 5, 1, 190, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo229,0,nullptr }, // Inst #2258 = VUHTOS
5467  { 2259, 4, 1, 481, 4, 0|(1<<MCID_Predicable), 0x8880ULL, nullptr, nullptr, OperandInfo147,0,nullptr }, // Inst #2259 = VUITOD
5468  { 2260, 4, 1, 482, 4, 0|(1<<MCID_Predicable), 0x28880ULL, nullptr, nullptr, OperandInfo134,0,nullptr }, // Inst #2260 = VUITOS
5469  { 2261, 5, 1, 189, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, nullptr, nullptr, OperandInfo228,0,nullptr }, // Inst #2261 = VULTOD
5470  { 2262, 5, 1, 190, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, nullptr, nullptr, OperandInfo229,0,nullptr }, // Inst #2262 = VULTOS
5471  { 2263, 6, 2, 434, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo262,0,nullptr }, // Inst #2263 = VUZPd16
5472  { 2264, 6, 2, 434, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo262,0,nullptr }, // Inst #2264 = VUZPd8
5473  { 2265, 6, 2, 436, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo263,0,nullptr }, // Inst #2265 = VUZPq16
5474  { 2266, 6, 2, 436, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo263,0,nullptr }, // Inst #2266 = VUZPq32
5475  { 2267, 6, 2, 436, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo263,0,nullptr }, // Inst #2267 = VUZPq8
5476  { 2268, 6, 2, 434, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo262,0,nullptr }, // Inst #2268 = VZIPd16
5477  { 2269, 6, 2, 434, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo262,0,nullptr }, // Inst #2269 = VZIPd8
5478  { 2270, 6, 2, 436, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo263,0,nullptr }, // Inst #2270 = VZIPq16
5479  { 2271, 6, 2, 436, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo263,0,nullptr }, // Inst #2271 = VZIPq32
5480  { 2272, 6, 2, 436, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, nullptr, nullptr, OperandInfo263,0,nullptr }, // Inst #2272 = VZIPq8
5481  { 2273, 0, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList11, ImplicitList12, nullptr,0,nullptr }, // Inst #2273 = WIN__CHKSTK
5482  { 2274, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #2274 = sysLDMDA
5483  { 2275, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2275 = sysLDMDA_UPD
5484  { 2276, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #2276 = sysLDMDB
5485  { 2277, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2277 = sysLDMDB_UPD
5486  { 2278, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #2278 = sysLDMIA
5487  { 2279, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2279 = sysLDMIA_UPD
5488  { 2280, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #2280 = sysLDMIB
5489  { 2281, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2281 = sysLDMIB_UPD
5490  { 2282, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #2282 = sysSTMDA
5491  { 2283, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2283 = sysSTMDA_UPD
5492  { 2284, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #2284 = sysSTMDB
5493  { 2285, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2285 = sysSTMDB_UPD
5494  { 2286, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #2286 = sysSTMIA
5495  { 2287, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2287 = sysSTMIA_UPD
5496  { 2288, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #2288 = sysSTMIB
5497  { 2289, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2289 = sysSTMIB_UPD
5498  { 2290, 2, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo268,0,nullptr }, // Inst #2290 = t2ABS
5499  { 2291, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo269,0,nullptr }, // Inst #2291 = t2ADCri
5500  { 2292, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo270,0,nullptr }, // Inst #2292 = t2ADCrr
5501  { 2293, 7, 1, 58, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo271,0,nullptr }, // Inst #2293 = t2ADCrs
5502  { 2294, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo272,0,nullptr }, // Inst #2294 = t2ADDSri
5503  { 2295, 5, 1, 2, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo273,0,nullptr }, // Inst #2295 = t2ADDSrr
5504  { 2296, 6, 1, 238, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo274,0,nullptr }, // Inst #2296 = t2ADDSrs
5505  { 2297, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo275,0,nullptr }, // Inst #2297 = t2ADDri
5506  { 2298, 5, 1, 1, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo276,0,nullptr }, // Inst #2298 = t2ADDri12
5507  { 2299, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo277,0,nullptr }, // Inst #2299 = t2ADDrr
5508  { 2300, 7, 1, 58, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo278,0,nullptr }, // Inst #2300 = t2ADDrs
5509  { 2301, 4, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo279,0,nullptr }, // Inst #2301 = t2ADR
5510  { 2302, 6, 1, 6, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2302 = t2ANDri
5511  { 2303, 6, 1, 7, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2303 = t2ANDrr
5512  { 2304, 7, 1, 59, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo271,0,nullptr }, // Inst #2304 = t2ANDrs
5513  { 2305, 6, 1, 50, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2305 = t2ASRri
5514  { 2306, 6, 1, 49, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2306 = t2ASRrr
5515  { 2307, 3, 0, 10, 4, 0|(1<<MCID_Branch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0xc80ULL, nullptr, nullptr, OperandInfo35,0,nullptr }, // Inst #2307 = t2B
5516  { 2308, 5, 1, 297, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo280,0,nullptr }, // Inst #2308 = t2BFC
5517  { 2309, 6, 1, 298, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo281,0,nullptr }, // Inst #2309 = t2BFI
5518  { 2310, 6, 1, 6, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2310 = t2BICri
5519  { 2311, 6, 1, 7, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2311 = t2BICrr
5520  { 2312, 7, 1, 59, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo271,0,nullptr }, // Inst #2312 = t2BICrs
5521  { 2313, 4, 0, 10, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo37,0,nullptr }, // Inst #2313 = t2BR_JT
5522  { 2314, 3, 0, 15, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo282,0,nullptr }, // Inst #2314 = t2BXJ
5523  { 2315, 3, 0, 10, 4, 0|(1<<MCID_Branch)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo35,0,nullptr }, // Inst #2315 = t2Bcc
5524  { 2316, 8, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo41,0,nullptr }, // Inst #2316 = t2CDP
5525  { 2317, 8, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo41,0,nullptr }, // Inst #2317 = t2CDP2
5526  { 2318, 2, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo40,0,nullptr }, // Inst #2318 = t2CLREX
5527  { 2319, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo283,0,nullptr }, // Inst #2319 = t2CLZ
5528  { 2320, 4, 0, 17, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo92,0,nullptr }, // Inst #2320 = t2CMNri
5529  { 2321, 4, 0, 18, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo284,0,nullptr }, // Inst #2321 = t2CMNzrr
5530  { 2322, 5, 0, 240, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo285,0,nullptr }, // Inst #2322 = t2CMNzrs
5531  { 2323, 4, 0, 241, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo92,0,nullptr }, // Inst #2323 = t2CMPri
5532  { 2324, 4, 0, 242, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo284,0,nullptr }, // Inst #2324 = t2CMPrr
5533  { 2325, 5, 0, 243, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo285,0,nullptr }, // Inst #2325 = t2CMPrs
5534  { 2326, 1, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #2326 = t2CPS1p
5535  { 2327, 2, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo7,0,nullptr }, // Inst #2327 = t2CPS2p
5536  { 2328, 3, 0, 0, 4, 0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo3,0,nullptr }, // Inst #2328 = t2CPS3p
5537  { 2329, 3, 1, 0, 4, 0, 0xc80ULL, nullptr, nullptr, OperandInfo286,0,nullptr }, // Inst #2329 = t2CRC32B
5538  { 2330, 3, 1, 0, 4, 0, 0xc80ULL, nullptr, nullptr, OperandInfo286,0,nullptr }, // Inst #2330 = t2CRC32CB
5539  { 2331, 3, 1, 0, 4, 0, 0xc80ULL, nullptr, nullptr, OperandInfo286,0,nullptr }, // Inst #2331 = t2CRC32CH
5540  { 2332, 3, 1, 0, 4, 0, 0xc80ULL, nullptr, nullptr, OperandInfo286,0,nullptr }, // Inst #2332 = t2CRC32CW
5541  { 2333, 3, 1, 0, 4, 0, 0xc80ULL, nullptr, nullptr, OperandInfo286,0,nullptr }, // Inst #2333 = t2CRC32H
5542  { 2334, 3, 1, 0, 4, 0, 0xc80ULL, nullptr, nullptr, OperandInfo286,0,nullptr }, // Inst #2334 = t2CRC32W
5543  { 2335, 3, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #2335 = t2DBG
5544  { 2336, 2, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo40,0,nullptr }, // Inst #2336 = t2DCPS1
5545  { 2337, 2, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo40,0,nullptr }, // Inst #2337 = t2DCPS2
5546  { 2338, 2, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo40,0,nullptr }, // Inst #2338 = t2DCPS3
5547  { 2339, 3, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #2339 = t2DMB
5548  { 2340, 3, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #2340 = t2DSB
5549  { 2341, 6, 1, 6, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2341 = t2EORri
5550  { 2342, 6, 1, 7, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2342 = t2EORrr
5551  { 2343, 7, 1, 59, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo271,0,nullptr }, // Inst #2343 = t2EORrs
5552  { 2344, 3, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #2344 = t2HINT
5553  { 2345, 1, 0, 10, 4, 0|(1<<MCID_Call)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #2345 = t2HVC
5554  { 2346, 3, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #2346 = t2ISB
5555  { 2347, 2, 0, 378, 2, 0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList13, OperandInfo7,0,0 }, // Inst #2347 = t2IT
5556  { 2348, 2, 0, 0, 0, 0|(1<<MCID_Barrier)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList14, OperandInfo287,0,nullptr }, // Inst #2348 = t2Int_eh_sjlj_setjmp
5557  { 2349, 2, 0, 0, 0, 0|(1<<MCID_Barrier)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList8, OperandInfo287,0,nullptr }, // Inst #2349 = t2Int_eh_sjlj_setjmp_nofp
5558  { 2350, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2350 = t2LDA
5559  { 2351, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2351 = t2LDAB
5560  { 2352, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2352 = t2LDAEX
5561  { 2353, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2353 = t2LDAEXB
5562  { 2354, 5, 2, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo289,0,nullptr }, // Inst #2354 = t2LDAEXD
5563  { 2355, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2355 = t2LDAEXH
5564  { 2356, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2356 = t2LDAH
5565  { 2357, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2357 = t2LDC2L_OFFSET
5566  { 2358, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2358 = t2LDC2L_OPTION
5567  { 2359, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2359 = t2LDC2L_POST
5568  { 2360, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2360 = t2LDC2L_PRE
5569  { 2361, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2361 = t2LDC2_OFFSET
5570  { 2362, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2362 = t2LDC2_OPTION
5571  { 2363, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2363 = t2LDC2_POST
5572  { 2364, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2364 = t2LDC2_PRE
5573  { 2365, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2365 = t2LDCL_OFFSET
5574  { 2366, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2366 = t2LDCL_OPTION
5575  { 2367, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2367 = t2LDCL_POST
5576  { 2368, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2368 = t2LDCL_PRE
5577  { 2369, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2369 = t2LDC_OFFSET
5578  { 2370, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2370 = t2LDC_OPTION
5579  { 2371, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2371 = t2LDC_POST
5580  { 2372, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2372 = t2LDC_PRE
5581  { 2373, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #2373 = t2LDMDB
5582  { 2374, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2374 = t2LDMDB_UPD
5583  { 2375, 4, 0, 353, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #2375 = t2LDMIA
5584  { 2376, 5, 1, 355, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2376 = t2LDMIA_RET
5585  { 2377, 5, 1, 354, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2377 = t2LDMIA_UPD
5586  { 2378, 5, 1, 346, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2378 = t2LDRBT
5587  { 2379, 6, 2, 342, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcccULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #2379 = t2LDRB_POST
5588  { 2380, 6, 2, 342, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcacULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #2380 = t2LDRB_PRE
5589  { 2381, 5, 1, 329, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo59,0,nullptr }, // Inst #2381 = t2LDRBi12
5590  { 2382, 5, 1, 329, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo59,0,nullptr }, // Inst #2382 = t2LDRBi8
5591  { 2383, 4, 1, 329, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo92,0,nullptr }, // Inst #2383 = t2LDRBpci
5592  { 2384, 4, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92,0,nullptr }, // Inst #2384 = t2LDRBpcrel
5593  { 2385, 6, 1, 326, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo291,0,nullptr }, // Inst #2385 = t2LDRBs
5594  { 2386, 7, 3, 352, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8fULL, nullptr, nullptr, OperandInfo292,0,nullptr }, // Inst #2386 = t2LDRD_POST
5595  { 2387, 7, 3, 352, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8fULL, nullptr, nullptr, OperandInfo292,0,nullptr }, // Inst #2387 = t2LDRD_PRE
5596  { 2388, 6, 2, 351, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0xc8fULL, nullptr, nullptr, OperandInfo293,0,nullptr }, // Inst #2388 = t2LDRDi8
5597  { 2389, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo294,0,nullptr }, // Inst #2389 = t2LDREX
5598  { 2390, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2390 = t2LDREXB
5599  { 2391, 5, 2, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo289,0,nullptr }, // Inst #2391 = t2LDREXD
5600  { 2392, 4, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2392 = t2LDREXH
5601  { 2393, 5, 1, 346, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2393 = t2LDRHT
5602  { 2394, 6, 2, 342, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcccULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #2394 = t2LDRH_POST
5603  { 2395, 6, 2, 342, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcacULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #2395 = t2LDRH_PRE
5604  { 2396, 5, 1, 329, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo59,0,nullptr }, // Inst #2396 = t2LDRHi12
5605  { 2397, 5, 1, 329, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo59,0,nullptr }, // Inst #2397 = t2LDRHi8
5606  { 2398, 4, 1, 329, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo92,0,nullptr }, // Inst #2398 = t2LDRHpci
5607  { 2399, 4, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92,0,nullptr }, // Inst #2399 = t2LDRHpcrel
5608  { 2400, 6, 1, 326, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo291,0,nullptr }, // Inst #2400 = t2LDRHs
5609  { 2401, 5, 1, 348, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2401 = t2LDRSBT
5610  { 2402, 6, 2, 349, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcccULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #2402 = t2LDRSB_POST
5611  { 2403, 6, 2, 349, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcacULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #2403 = t2LDRSB_PRE
5612  { 2404, 5, 1, 337, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo59,0,nullptr }, // Inst #2404 = t2LDRSBi12
5613  { 2405, 5, 1, 337, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo59,0,nullptr }, // Inst #2405 = t2LDRSBi8
5614  { 2406, 4, 1, 337, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo92,0,nullptr }, // Inst #2406 = t2LDRSBpci
5615  { 2407, 4, 0, 338, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92,0,nullptr }, // Inst #2407 = t2LDRSBpcrel
5616  { 2408, 6, 1, 339, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo291,0,nullptr }, // Inst #2408 = t2LDRSBs
5617  { 2409, 5, 1, 348, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2409 = t2LDRSHT
5618  { 2410, 6, 2, 349, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcccULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #2410 = t2LDRSH_POST
5619  { 2411, 6, 2, 349, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcacULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #2411 = t2LDRSH_PRE
5620  { 2412, 5, 1, 337, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo59,0,nullptr }, // Inst #2412 = t2LDRSHi12
5621  { 2413, 5, 1, 337, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo59,0,nullptr }, // Inst #2413 = t2LDRSHi8
5622  { 2414, 4, 1, 337, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo92,0,nullptr }, // Inst #2414 = t2LDRSHpci
5623  { 2415, 4, 0, 338, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo92,0,nullptr }, // Inst #2415 = t2LDRSHpcrel
5624  { 2416, 6, 1, 339, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo291,0,nullptr }, // Inst #2416 = t2LDRSHs
5625  { 2417, 5, 1, 347, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2417 = t2LDRT
5626  { 2418, 6, 2, 345, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcccULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #2418 = t2LDR_POST
5627  { 2419, 6, 2, 345, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcacULL, nullptr, nullptr, OperandInfo58,0,nullptr }, // Inst #2419 = t2LDR_PRE
5628  { 2420, 5, 1, 330, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8bULL, nullptr, nullptr, OperandInfo44,0,nullptr }, // Inst #2420 = t2LDRi12
5629  { 2421, 5, 1, 330, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8cULL, nullptr, nullptr, OperandInfo44,0,nullptr }, // Inst #2421 = t2LDRi8
5630  { 2422, 4, 1, 330, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo24,0,nullptr }, // Inst #2422 = t2LDRpci
5631  { 2423, 3, 1, 331, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo295,0,nullptr }, // Inst #2423 = t2LDRpci_pic
5632  { 2424, 4, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo24,0,nullptr }, // Inst #2424 = t2LDRpcrel
5633  { 2425, 6, 1, 332, 4, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8dULL, nullptr, nullptr, OperandInfo296,0,nullptr }, // Inst #2425 = t2LDRs
5634  { 2426, 4, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo297,0,nullptr }, // Inst #2426 = t2LEApcrel
5635  { 2427, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo298,0,nullptr }, // Inst #2427 = t2LEApcrelJT
5636  { 2428, 6, 1, 50, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2428 = t2LSLri
5637  { 2429, 6, 1, 49, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2429 = t2LSLrr
5638  { 2430, 6, 1, 50, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2430 = t2LSRri
5639  { 2431, 6, 1, 49, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2431 = t2LSRrr
5640  { 2432, 8, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo70,0,0 }, // Inst #2432 = t2MCR
5641  { 2433, 8, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo70,0,nullptr }, // Inst #2433 = t2MCR2
5642  { 2434, 7, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2434 = t2MCRR
5643  { 2435, 7, 0, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2435 = t2MCRR2
5644  { 2436, 6, 1, 313, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2436 = t2MLA
5645  { 2437, 6, 1, 313, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2437 = t2MLS
5646  { 2438, 6, 1, 247, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo301,0,nullptr }, // Inst #2438 = t2MOVCCasr
5647  { 2439, 5, 1, 40, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo280,0,nullptr }, // Inst #2439 = t2MOVCCi
5648  { 2440, 5, 1, 40, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo280,0,nullptr }, // Inst #2440 = t2MOVCCi16
5649  { 2441, 5, 1, 292, 8, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo302,0,nullptr }, // Inst #2441 = t2MOVCCi32imm
5650  { 2442, 6, 1, 247, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo301,0,nullptr }, // Inst #2442 = t2MOVCClsl
5651  { 2443, 6, 1, 247, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo301,0,nullptr }, // Inst #2443 = t2MOVCClsr
5652  { 2444, 5, 1, 43, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Select)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x0ULL, nullptr, nullptr, OperandInfo303,0,nullptr }, // Inst #2444 = t2MOVCCr
5653  { 2445, 6, 1, 247, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo301,0,nullptr }, // Inst #2445 = t2MOVCCror
5654  { 2446, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo304,0,nullptr }, // Inst #2446 = t2MOVSsi
5655  { 2447, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo305,0,nullptr }, // Inst #2447 = t2MOVSsr
5656  { 2448, 5, 1, 41, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo280,0,nullptr }, // Inst #2448 = t2MOVTi16
5657  { 2449, 4, 1, 41, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo306,0,nullptr }, // Inst #2449 = t2MOVTi16_ga_pcrel
5658  { 2450, 2, 1, 294, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo307,0,nullptr }, // Inst #2450 = t2MOV_ga_pcrel
5659  { 2451, 5, 1, 41, 4, 0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef)|(1<<MCID_CheapAsAMove), 0xc80ULL, nullptr, nullptr, OperandInfo308,0,nullptr }, // Inst #2451 = t2MOVi
5660  { 2452, 4, 1, 41, 4, 0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_CheapAsAMove), 0xc80ULL, nullptr, nullptr, OperandInfo279,0,nullptr }, // Inst #2452 = t2MOVi16
5661  { 2453, 3, 1, 295, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo295,0,nullptr }, // Inst #2453 = t2MOVi16_ga_pcrel
5662  { 2454, 2, 1, 293, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo307,0,nullptr }, // Inst #2454 = t2MOVi32imm
5663  { 2455, 5, 1, 48, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo309,0,nullptr }, // Inst #2455 = t2MOVr
5664  { 2456, 5, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo304,0,nullptr }, // Inst #2456 = t2MOVsi
5665  { 2457, 6, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo305,0,nullptr }, // Inst #2457 = t2MOVsr
5666  { 2458, 4, 1, 50, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo283,0,nullptr }, // Inst #2458 = t2MOVsra_flag
5667  { 2459, 4, 1, 50, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo283,0,nullptr }, // Inst #2459 = t2MOVsrl_flag
5668  { 2460, 8, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo89,0,nullptr }, // Inst #2460 = t2MRC
5669  { 2461, 8, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo89,0,nullptr }, // Inst #2461 = t2MRC2
5670  { 2462, 7, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2462 = t2MRRC
5671  { 2463, 7, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo299,0,nullptr }, // Inst #2463 = t2MRRC2
5672  { 2464, 3, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo34,0,nullptr }, // Inst #2464 = t2MRS_AR
5673  { 2465, 4, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo279,0,nullptr }, // Inst #2465 = t2MRS_M
5674  { 2466, 4, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo279,0,nullptr }, // Inst #2466 = t2MRSbanked
5675  { 2467, 3, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo34,0,nullptr }, // Inst #2467 = t2MRSsys_AR
5676  { 2468, 4, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2468 = t2MSR_AR
5677  { 2469, 4, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2469 = t2MSR_M
5678  { 2470, 4, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo310,0,nullptr }, // Inst #2470 = t2MSRbanked
5679  { 2471, 5, 1, 310, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2471 = t2MUL
5680  { 2472, 5, 1, 40, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, nullptr, nullptr, OperandInfo280,0,nullptr }, // Inst #2472 = t2MVNCCi
5681  { 2473, 5, 1, 52, 4, 0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef)|(1<<MCID_CheapAsAMove), 0xc80ULL, nullptr, nullptr, OperandInfo308,0,nullptr }, // Inst #2473 = t2MVNi
5682  { 2474, 5, 1, 53, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo312,0,nullptr }, // Inst #2474 = t2MVNr
5683  { 2475, 6, 1, 249, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo313,0,nullptr }, // Inst #2475 = t2MVNs
5684  { 2476, 6, 1, 6, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2476 = t2ORNri
5685  { 2477, 6, 1, 7, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2477 = t2ORNrr
5686  { 2478, 7, 1, 59, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo271,0,nullptr }, // Inst #2478 = t2ORNrs
5687  { 2479, 6, 1, 6, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2479 = t2ORRri
5688  { 2480, 6, 1, 7, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2480 = t2ORRrr
5689  { 2481, 7, 1, 59, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo271,0,nullptr }, // Inst #2481 = t2ORRrs
5690  { 2482, 6, 1, 59, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo314,0,nullptr }, // Inst #2482 = t2PKHBT
5691  { 2483, 6, 1, 59, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo314,0,nullptr }, // Inst #2483 = t2PKHTB
5692  { 2484, 4, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo315,0,nullptr }, // Inst #2484 = t2PLDWi12
5693  { 2485, 4, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo315,0,nullptr }, // Inst #2485 = t2PLDWi8
5694  { 2486, 5, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo316,0,nullptr }, // Inst #2486 = t2PLDWs
5695  { 2487, 4, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo315,0,nullptr }, // Inst #2487 = t2PLDi12
5696  { 2488, 4, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo315,0,nullptr }, // Inst #2488 = t2PLDi8
5697  { 2489, 3, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #2489 = t2PLDpci
5698  { 2490, 5, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo316,0,nullptr }, // Inst #2490 = t2PLDs
5699  { 2491, 4, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo315,0,nullptr }, // Inst #2491 = t2PLIi12
5700  { 2492, 4, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo315,0,nullptr }, // Inst #2492 = t2PLIi8
5701  { 2493, 3, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #2493 = t2PLIpci
5702  { 2494, 5, 0, 60, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo316,0,nullptr }, // Inst #2494 = t2PLIs
5703  { 2495, 5, 1, 300, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2495 = t2QADD
5704  { 2496, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2496 = t2QADD16
5705  { 2497, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2497 = t2QADD8
5706  { 2498, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2498 = t2QASX
5707  { 2499, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2499 = t2QDADD
5708  { 2500, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2500 = t2QDSUB
5709  { 2501, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2501 = t2QSAX
5710  { 2502, 5, 1, 300, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2502 = t2QSUB
5711  { 2503, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2503 = t2QSUB16
5712  { 2504, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2504 = t2QSUB8
5713  { 2505, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo283,0,nullptr }, // Inst #2505 = t2RBIT
5714  { 2506, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo283,0,nullptr }, // Inst #2506 = t2REV
5715  { 2507, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo283,0,nullptr }, // Inst #2507 = t2REV16
5716  { 2508, 4, 1, 16, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo283,0,nullptr }, // Inst #2508 = t2REVSH
5717  { 2509, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo34,0,nullptr }, // Inst #2509 = t2RFEDB
5718  { 2510, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo34,0,nullptr }, // Inst #2510 = t2RFEDBW
5719  { 2511, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo34,0,nullptr }, // Inst #2511 = t2RFEIA
5720  { 2512, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo34,0,nullptr }, // Inst #2512 = t2RFEIAW
5721  { 2513, 6, 1, 50, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2513 = t2RORri
5722  { 2514, 6, 1, 49, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2514 = t2RORrr
5723  { 2515, 5, 1, 50, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, ImplicitList1, nullptr, OperandInfo312,0,nullptr }, // Inst #2515 = t2RRX
5724  { 2516, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo317,0,nullptr }, // Inst #2516 = t2RSBSri
5725  { 2517, 6, 1, 58, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo318,0,nullptr }, // Inst #2517 = t2RSBSrs
5726  { 2518, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo269,0,nullptr }, // Inst #2518 = t2RSBri
5727  { 2519, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo270,0,nullptr }, // Inst #2519 = t2RSBrr
5728  { 2520, 7, 1, 250, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo271,0,nullptr }, // Inst #2520 = t2RSBrs
5729  { 2521, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2521 = t2SADD16
5730  { 2522, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2522 = t2SADD8
5731  { 2523, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2523 = t2SASX
5732  { 2524, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo269,0,nullptr }, // Inst #2524 = t2SBCri
5733  { 2525, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo270,0,nullptr }, // Inst #2525 = t2SBCrr
5734  { 2526, 7, 1, 58, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo271,0,nullptr }, // Inst #2526 = t2SBCrs
5735  { 2527, 6, 1, 297, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo319,0,nullptr }, // Inst #2527 = t2SBFX
5736  { 2528, 5, 1, 324, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2528 = t2SDIV
5737  { 2529, 5, 1, 296, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo18,0,nullptr }, // Inst #2529 = t2SEL
5738  { 2530, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2530 = t2SHADD16
5739  { 2531, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2531 = t2SHADD8
5740  { 2532, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2532 = t2SHASX
5741  { 2533, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2533 = t2SHSAX
5742  { 2534, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2534 = t2SHSUB16
5743  { 2535, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2535 = t2SHSUB8
5744  { 2536, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #2536 = t2SMC
5745  { 2537, 6, 1, 317, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2537 = t2SMLABB
5746  { 2538, 6, 1, 317, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2538 = t2SMLABT
5747  { 2539, 6, 1, 320, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2539 = t2SMLAD
5748  { 2540, 6, 1, 320, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2540 = t2SMLADX
5749  { 2541, 8, 2, 323, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo320,0,nullptr }, // Inst #2541 = t2SMLAL
5750  { 2542, 6, 2, 323, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2542 = t2SMLALBB
5751  { 2543, 6, 2, 323, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2543 = t2SMLALBT
5752  { 2544, 6, 2, 323, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2544 = t2SMLALD
5753  { 2545, 6, 2, 323, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2545 = t2SMLALDX
5754  { 2546, 6, 2, 323, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2546 = t2SMLALTB
5755  { 2547, 6, 2, 323, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2547 = t2SMLALTT
5756  { 2548, 6, 1, 317, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2548 = t2SMLATB
5757  { 2549, 6, 1, 317, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2549 = t2SMLATT
5758  { 2550, 6, 1, 317, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2550 = t2SMLAWB
5759  { 2551, 6, 1, 317, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2551 = t2SMLAWT
5760  { 2552, 6, 1, 318, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2552 = t2SMLSD
5761  { 2553, 6, 1, 318, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2553 = t2SMLSDX
5762  { 2554, 6, 2, 323, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2554 = t2SMLSLD
5763  { 2555, 6, 2, 323, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2555 = t2SMLSLDX
5764  { 2556, 6, 1, 313, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2556 = t2SMMLA
5765  { 2557, 6, 1, 313, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2557 = t2SMMLAR
5766  { 2558, 6, 1, 313, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2558 = t2SMMLS
5767  { 2559, 6, 1, 313, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2559 = t2SMMLSR
5768  { 2560, 5, 1, 310, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2560 = t2SMMUL
5769  { 2561, 5, 1, 310, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2561 = t2SMMULR
5770  { 2562, 5, 1, 315, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2562 = t2SMUAD
5771  { 2563, 5, 1, 315, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2563 = t2SMUADX
5772  { 2564, 5, 1, 311, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2564 = t2SMULBB
5773  { 2565, 5, 1, 311, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2565 = t2SMULBT
5774  { 2566, 6, 2, 322, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2566 = t2SMULL
5775  { 2567, 5, 1, 311, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2567 = t2SMULTB
5776  { 2568, 5, 1, 311, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2568 = t2SMULTT
5777  { 2569, 5, 1, 311, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2569 = t2SMULWB
5778  { 2570, 5, 1, 311, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2570 = t2SMULWT
5779  { 2571, 5, 1, 312, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2571 = t2SMUSD
5780  { 2572, 5, 1, 312, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2572 = t2SMUSDX
5781  { 2573, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #2573 = t2SRSDB
5782  { 2574, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #2574 = t2SRSDB_UPD
5783  { 2575, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #2575 = t2SRSIA
5784  { 2576, 3, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #2576 = t2SRSIA_UPD
5785  { 2577, 6, 1, 300, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo321,0,nullptr }, // Inst #2577 = t2SSAT
5786  { 2578, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo322,0,nullptr }, // Inst #2578 = t2SSAT16
5787  { 2579, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2579 = t2SSAX
5788  { 2580, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2580 = t2SSUB16
5789  { 2581, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2581 = t2SSUB8
5790  { 2582, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2582 = t2STC2L_OFFSET
5791  { 2583, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2583 = t2STC2L_OPTION
5792  { 2584, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2584 = t2STC2L_POST
5793  { 2585, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2585 = t2STC2L_PRE
5794  { 2586, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2586 = t2STC2_OFFSET
5795  { 2587, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2587 = t2STC2_OPTION
5796  { 2588, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2588 = t2STC2_POST
5797  { 2589, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2589 = t2STC2_PRE
5798  { 2590, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2590 = t2STCL_OFFSET
5799  { 2591, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2591 = t2STCL_OPTION
5800  { 2592, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2592 = t2STCL_POST
5801  { 2593, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2593 = t2STCL_PRE
5802  { 2594, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2594 = t2STC_OFFSET
5803  { 2595, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2595 = t2STC_OPTION
5804  { 2596, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2596 = t2STC_POST
5805  { 2597, 6, 0, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo56,0,nullptr }, // Inst #2597 = t2STC_PRE
5806  { 2598, 4, 0, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2598 = t2STL
5807  { 2599, 4, 0, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2599 = t2STLB
5808  { 2600, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo323,0,nullptr }, // Inst #2600 = t2STLEX
5809  { 2601, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo323,0,nullptr }, // Inst #2601 = t2STLEXB
5810  { 2602, 6, 1, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo324,0,nullptr }, // Inst #2602 = t2STLEXD
5811  { 2603, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo323,0,nullptr }, // Inst #2603 = t2STLEXH
5812  { 2604, 4, 0, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo288,0,nullptr }, // Inst #2604 = t2STLH
5813  { 2605, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #2605 = t2STMDB
5814  { 2606, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2606 = t2STMDB_UPD
5815  { 2607, 4, 0, 374, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo52,0,nullptr }, // Inst #2607 = t2STMIA
5816  { 2608, 5, 1, 375, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2608 = t2STMIA_UPD
5817  { 2609, 5, 1, 370, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2609 = t2STRBT
5818  { 2610, 6, 1, 367, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcccULL, nullptr, nullptr, OperandInfo325,0,nullptr }, // Inst #2610 = t2STRB_POST
5819  { 2611, 6, 1, 367, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcacULL, nullptr, nullptr, OperandInfo325,0,nullptr }, // Inst #2611 = t2STRB_PRE
5820  { 2612, 6, 1, 368, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo326,0,nullptr }, // Inst #2612 = t2STRB_preidx
5821  { 2613, 5, 0, 363, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2613 = t2STRBi12
5822  { 2614, 5, 0, 363, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2614 = t2STRBi8
5823  { 2615, 6, 0, 360, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo327,0,nullptr }, // Inst #2615 = t2STRBs
5824  { 2616, 7, 1, 373, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8fULL, nullptr, nullptr, OperandInfo328,0,nullptr }, // Inst #2616 = t2STRD_POST
5825  { 2617, 7, 1, 373, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8fULL, nullptr, nullptr, OperandInfo328,0,nullptr }, // Inst #2617 = t2STRD_PRE
5826  { 2618, 6, 0, 372, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0xc8fULL, nullptr, nullptr, OperandInfo293,0,nullptr }, // Inst #2618 = t2STRDi8
5827  { 2619, 6, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo329,0,nullptr }, // Inst #2619 = t2STREX
5828  { 2620, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo323,0,nullptr }, // Inst #2620 = t2STREXB
5829  { 2621, 6, 1, 0, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo324,0,nullptr }, // Inst #2621 = t2STREXD
5830  { 2622, 5, 1, 0, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo323,0,nullptr }, // Inst #2622 = t2STREXH
5831  { 2623, 5, 1, 370, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2623 = t2STRHT
5832  { 2624, 6, 1, 367, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcccULL, nullptr, nullptr, OperandInfo325,0,nullptr }, // Inst #2624 = t2STRH_POST
5833  { 2625, 6, 1, 369, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcacULL, nullptr, nullptr, OperandInfo325,0,nullptr }, // Inst #2625 = t2STRH_PRE
5834  { 2626, 6, 1, 368, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo326,0,nullptr }, // Inst #2626 = t2STRH_preidx
5835  { 2627, 5, 0, 363, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2627 = t2STRHi12
5836  { 2628, 5, 0, 363, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2628 = t2STRHi8
5837  { 2629, 6, 0, 360, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo327,0,nullptr }, // Inst #2629 = t2STRHs
5838  { 2630, 5, 1, 371, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, nullptr, nullptr, OperandInfo290,0,nullptr }, // Inst #2630 = t2STRT
5839  { 2631, 6, 1, 369, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcccULL, nullptr, nullptr, OperandInfo330,0,nullptr }, // Inst #2631 = t2STR_POST
5840  { 2632, 6, 1, 369, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcacULL, nullptr, nullptr, OperandInfo330,0,nullptr }, // Inst #2632 = t2STR_PRE
5841  { 2633, 6, 1, 368, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo326,0,nullptr }, // Inst #2633 = t2STR_preidx
5842  { 2634, 5, 0, 364, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, nullptr, nullptr, OperandInfo44,0,nullptr }, // Inst #2634 = t2STRi12
5843  { 2635, 5, 0, 364, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, nullptr, nullptr, OperandInfo44,0,nullptr }, // Inst #2635 = t2STRi8
5844  { 2636, 6, 0, 362, 4, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, nullptr, nullptr, OperandInfo296,0,nullptr }, // Inst #2636 = t2STRs
5845  { 2637, 3, 0, 0, 4, 0|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0xc80ULL, nullptr, ImplicitList4, OperandInfo48,0,nullptr }, // Inst #2637 = t2SUBS_PC_LR
5846  { 2638, 5, 1, 1, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo272,0,nullptr }, // Inst #2638 = t2SUBSri
5847  { 2639, 5, 1, 2, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo273,0,nullptr }, // Inst #2639 = t2SUBSrr
5848  { 2640, 6, 1, 238, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, nullptr, ImplicitList1, OperandInfo274,0,nullptr }, // Inst #2640 = t2SUBSrs
5849  { 2641, 6, 1, 1, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo275,0,nullptr }, // Inst #2641 = t2SUBri
5850  { 2642, 5, 1, 1, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo276,0,nullptr }, // Inst #2642 = t2SUBri12
5851  { 2643, 6, 1, 2, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo277,0,nullptr }, // Inst #2643 = t2SUBrr
5852  { 2644, 7, 1, 58, 4, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo278,0,nullptr }, // Inst #2644 = t2SUBrs
5853  { 2645, 6, 1, 306, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo314,0,nullptr }, // Inst #2645 = t2SXTAB
5854  { 2646, 6, 1, 306, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo314,0,nullptr }, // Inst #2646 = t2SXTAB16
5855  { 2647, 6, 1, 306, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo314,0,nullptr }, // Inst #2647 = t2SXTAH
5856  { 2648, 5, 1, 291, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo317,0,nullptr }, // Inst #2648 = t2SXTB
5857  { 2649, 5, 1, 291, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo317,0,nullptr }, // Inst #2649 = t2SXTB16
5858  { 2650, 5, 1, 291, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo317,0,nullptr }, // Inst #2650 = t2SXTH
5859  { 2651, 4, 0, 14, 4, 0|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo331,0,nullptr }, // Inst #2651 = t2TBB
5860  { 2652, 3, 0, 10, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39,0,nullptr }, // Inst #2652 = t2TBB_JT
5861  { 2653, 4, 0, 14, 4, 0|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo331,0,nullptr }, // Inst #2653 = t2TBH
5862  { 2654, 3, 0, 10, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo39,0,nullptr }, // Inst #2654 = t2TBH_JT
5863  { 2655, 4, 0, 255, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo92,0,nullptr }, // Inst #2655 = t2TEQri
5864  { 2656, 4, 0, 256, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo284,0,nullptr }, // Inst #2656 = t2TEQrr
5865  { 2657, 5, 0, 257, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo285,0,nullptr }, // Inst #2657 = t2TEQrs
5866  { 2658, 4, 0, 255, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo92,0,nullptr }, // Inst #2658 = t2TSTri
5867  { 2659, 4, 0, 256, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo284,0,nullptr }, // Inst #2659 = t2TSTrr
5868  { 2660, 5, 0, 257, 4, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo285,0,nullptr }, // Inst #2660 = t2TSTrs
5869  { 2661, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2661 = t2UADD16
5870  { 2662, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2662 = t2UADD8
5871  { 2663, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2663 = t2UASX
5872  { 2664, 6, 1, 297, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo319,0,nullptr }, // Inst #2664 = t2UBFX
5873  { 2665, 1, 0, 76, 4, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #2665 = t2UDF
5874  { 2666, 5, 1, 324, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2666 = t2UDIV
5875  { 2667, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2667 = t2UHADD16
5876  { 2668, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2668 = t2UHADD8
5877  { 2669, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2669 = t2UHASX
5878  { 2670, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2670 = t2UHSAX
5879  { 2671, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2671 = t2UHSUB16
5880  { 2672, 5, 1, 305, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2672 = t2UHSUB8
5881  { 2673, 6, 2, 323, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2673 = t2UMAAL
5882  { 2674, 8, 2, 323, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo320,0,nullptr }, // Inst #2674 = t2UMLAL
5883  { 2675, 6, 2, 322, 4, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2675 = t2UMULL
5884  { 2676, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2676 = t2UQADD16
5885  { 2677, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2677 = t2UQADD8
5886  { 2678, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2678 = t2UQASX
5887  { 2679, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2679 = t2UQSAX
5888  { 2680, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2680 = t2UQSUB16
5889  { 2681, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2681 = t2UQSUB8
5890  { 2682, 5, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2682 = t2USAD8
5891  { 2683, 6, 1, 0, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo300,0,nullptr }, // Inst #2683 = t2USADA8
5892  { 2684, 6, 1, 300, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo321,0,nullptr }, // Inst #2684 = t2USAT
5893  { 2685, 5, 1, 300, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo322,0,nullptr }, // Inst #2685 = t2USAT16
5894  { 2686, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2686 = t2USAX
5895  { 2687, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2687 = t2USUB16
5896  { 2688, 5, 1, 302, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo311,0,nullptr }, // Inst #2688 = t2USUB8
5897  { 2689, 6, 1, 306, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo314,0,nullptr }, // Inst #2689 = t2UXTAB
5898  { 2690, 6, 1, 306, 4, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo314,0,nullptr }, // Inst #2690 = t2UXTAB16
5899  { 2691, 6, 1, 306, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo314,0,nullptr }, // Inst #2691 = t2UXTAH
5900  { 2692, 5, 1, 291, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo317,0,nullptr }, // Inst #2692 = t2UXTB
5901  { 2693, 5, 1, 291, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo317,0,nullptr }, // Inst #2693 = t2UXTB16
5902  { 2694, 5, 1, 291, 4, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo317,0,nullptr }, // Inst #2694 = t2UXTH
5903  { 2695, 6, 2, 258, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, ImplicitList1, nullptr, OperandInfo332,0,nullptr }, // Inst #2695 = tADC
5904  { 2696, 3, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList1, OperandInfo333,0,nullptr }, // Inst #2696 = tADDframe
5905  { 2697, 5, 1, 258, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo78,0,nullptr }, // Inst #2697 = tADDhirr
5906  { 2698, 6, 2, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo334,0,nullptr }, // Inst #2698 = tADDi3
5907  { 2699, 6, 2, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo335,0,nullptr }, // Inst #2699 = tADDi8
5908  { 2700, 5, 1, 258, 2, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo336,0,nullptr }, // Inst #2700 = tADDrSP
5909  { 2701, 5, 1, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo337,0,nullptr }, // Inst #2701 = tADDrSPi
5910  { 2702, 6, 2, 258, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo338,0,nullptr }, // Inst #2702 = tADDrr
5911  { 2703, 5, 1, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo339,0,nullptr }, // Inst #2703 = tADDspi
5912  { 2704, 5, 1, 258, 2, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo340,0,nullptr }, // Inst #2704 = tADDspr
5913  { 2705, 1, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo2,0,nullptr }, // Inst #2705 = tADJCALLSTACKDOWN
5914  { 2706, 2, 0, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo8,0,nullptr }, // Inst #2706 = tADJCALLSTACKUP
5915  { 2707, 4, 1, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo341,0,nullptr }, // Inst #2707 = tADR
5916  { 2708, 6, 2, 260, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo332,0,nullptr }, // Inst #2708 = tAND
5917  { 2709, 6, 2, 50, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo334,0,nullptr }, // Inst #2709 = tASRri
5918  { 2710, 6, 2, 49, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo332,0,nullptr }, // Inst #2710 = tASRrr
5919  { 2711, 3, 0, 10, 2, 0|(1<<MCID_Branch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0xc80ULL, nullptr, nullptr, OperandInfo35,0,nullptr }, // Inst #2711 = tB
5920  { 2712, 6, 2, 260, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo332,0,nullptr }, // Inst #2712 = tBIC
5921  { 2713, 1, 0, 0, 2, 0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #2713 = tBKPT
5922  { 2714, 3, 0, 12, 4, 0|(1<<MCID_Call)|(1<<MCID_Predicable), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo342,0,nullptr }, // Inst #2714 = tBL
5923  { 2715, 3, 0, 12, 4, 0|(1<<MCID_Call)|(1<<MCID_Predicable), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo342,0,nullptr }, // Inst #2715 = tBLXi
5924  { 2716, 3, 0, 12, 2, 0|(1<<MCID_Call)|(1<<MCID_Predicable), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo343,0,nullptr }, // Inst #2716 = tBLXr
5925  { 2717, 3, 0, 10, 2, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x0ULL, nullptr, nullptr, OperandInfo34,0,nullptr }, // Inst #2717 = tBRIND
5926  { 2718, 3, 0, 14, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_Barrier)|(1<<MCID_Terminator), 0x0ULL, nullptr, nullptr, OperandInfo333,0,nullptr }, // Inst #2718 = tBR_JTr
5927  { 2719, 3, 0, 10, 2, 0|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo34,0,nullptr }, // Inst #2719 = tBX
5928  { 2720, 1, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo36,0,nullptr }, // Inst #2720 = tBX_CALL
5929  { 2721, 2, 0, 10, 2, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x0ULL, nullptr, nullptr, OperandInfo40,0,nullptr }, // Inst #2721 = tBX_RET
5930  { 2722, 3, 0, 10, 2, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo344,0,nullptr }, // Inst #2722 = tBX_RET_vararg
5931  { 2723, 3, 0, 10, 2, 0|(1<<MCID_Branch)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo35,0,nullptr }, // Inst #2723 = tBcc
5932  { 2724, 3, 0, 14, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList3, OperandInfo35,0,nullptr }, // Inst #2724 = tBfar
5933  { 2725, 2, 0, 10, 2, 0|(1<<MCID_Branch)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo345,0,nullptr }, // Inst #2725 = tCBNZ
5934  { 2726, 2, 0, 10, 2, 0|(1<<MCID_Branch)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo345,0,nullptr }, // Inst #2726 = tCBZ
5935  { 2727, 4, 0, 242, 2, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo346,0,nullptr }, // Inst #2727 = tCMNz
5936  { 2728, 4, 0, 242, 2, 0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList1, OperandInfo43,0,nullptr }, // Inst #2728 = tCMPhir
5937  { 2729, 4, 0, 241, 2, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo347,0,nullptr }, // Inst #2729 = tCMPi8
5938  { 2730, 4, 0, 242, 2, 0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo346,0,nullptr }, // Inst #2730 = tCMPr
5939  { 2731, 2, 0, 0, 2, 0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo7,0,nullptr }, // Inst #2731 = tCPS
5940  { 2732, 6, 2, 260, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo332,0,nullptr }, // Inst #2732 = tEOR
5941  { 2733, 3, 0, 0, 2, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo48,0,nullptr }, // Inst #2733 = tHINT
5942  { 2734, 1, 0, 0, 2, 0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #2734 = tHLT
5943  { 2735, 2, 0, 0, 0, 0|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, ImplicitList6, OperandInfo12,0,nullptr }, // Inst #2735 = tInt_eh_sjlj_longjmp
5944  { 2736, 2, 0, 0, 0, 0|(1<<MCID_Barrier)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, ImplicitList15, OperandInfo287,0,nullptr }, // Inst #2736 = tInt_eh_sjlj_setjmp
5945  { 2737, 4, 0, 353, 2, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo348,0,nullptr }, // Inst #2737 = tLDMIA
5946  { 2738, 5, 1, 354, 2, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Variadic), 0x0ULL, nullptr, nullptr, OperandInfo51,0,nullptr }, // Inst #2738 = tLDMIA_UPD
5947  { 2739, 5, 1, 329, 2, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc87ULL, nullptr, nullptr, OperandInfo349,0,nullptr }, // Inst #2739 = tLDRBi
5948  { 2740, 5, 1, 333, 2, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc87ULL, nullptr, nullptr, OperandInfo350,0,nullptr }, // Inst #2740 = tLDRBr
5949  { 2741, 5, 1, 329, 2, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc88ULL, nullptr, nullptr, OperandInfo349,0,nullptr }, // Inst #2741 = tLDRHi
5950  { 2742, 5, 1, 333, 2, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc88ULL, nullptr, nullptr, OperandInfo350,0,nullptr }, // Inst #2742 = tLDRHr
5951  { 2743, 2, 1, 33, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo351,0,nullptr }, // Inst #2743 = tLDRLIT_ga_abs
5952  { 2744, 2, 1, 34, 0, 0|(1<<MCID_Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo351,0,nullptr }, // Inst #2744 = tLDRLIT_ga_pcrel
5953  { 2745, 5, 1, 340, 2, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc87ULL, nullptr, nullptr, OperandInfo350,0,nullptr }, // Inst #2745 = tLDRSB
5954  { 2746, 5, 1, 340, 2, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc88ULL, nullptr, nullptr, OperandInfo350,0,nullptr }, // Inst #2746 = tLDRSH
5955  { 2747, 5, 1, 330, 2, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc89ULL, nullptr, nullptr, OperandInfo349,0,nullptr }, // Inst #2747 = tLDRi
5956  { 2748, 4, 1, 330, 2, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8aULL, nullptr, nullptr, OperandInfo341,0,nullptr }, // Inst #2748 = tLDRpci
5957  { 2749, 3, 1, 327, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo84,0,nullptr }, // Inst #2749 = tLDRpci_pic
5958  { 2750, 5, 1, 334, 2, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc89ULL, nullptr, nullptr, OperandInfo350,0,nullptr }, // Inst #2750 = tLDRr
5959  { 2751, 5, 1, 330, 2, 0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8aULL, nullptr, nullptr, OperandInfo352,0,nullptr }, // Inst #2751 = tLDRspi
5960  { 2752, 4, 1, 259, 2, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo353,0,nullptr }, // Inst #2752 = tLEApcrel
5961  { 2753, 5, 1, 259, 2, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo354,0,nullptr }, // Inst #2753 = tLEApcrelJT
5962  { 2754, 6, 2, 50, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo334,0,nullptr }, // Inst #2754 = tLSLri
5963  { 2755, 6, 2, 49, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo332,0,nullptr }, // Inst #2755 = tLSLrr
5964  { 2756, 6, 2, 50, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo334,0,nullptr }, // Inst #2756 = tLSRri
5965  { 2757, 6, 2, 49, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo332,0,nullptr }, // Inst #2757 = tLSRrr
5966  { 2758, 5, 1, 0, 0, 0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, nullptr, nullptr, OperandInfo355,0,nullptr }, // Inst #2758 = tMOVCCr_pseudo
5967  { 2759, 2, 1, 48, 2, 0, 0xc80ULL, nullptr, ImplicitList1, OperandInfo287,0,nullptr }, // Inst #2759 = tMOVSr
5968  { 2760, 5, 2, 41, 2, 0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo356,0,nullptr }, // Inst #2760 = tMOVi8
5969  { 2761, 4, 1, 48, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo43,0,nullptr }, // Inst #2761 = tMOVr
5970  { 2762, 6, 2, 51, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo357,0,nullptr }, // Inst #2762 = tMUL
5971  { 2763, 5, 2, 53, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo358,0,nullptr }, // Inst #2763 = tMVN
5972  { 2764, 6, 2, 260, 2, 0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo332,0,nullptr }, // Inst #2764 = tORR
5973  { 2765, 3, 1, 258, 2, 0|(1<<MCID_NotDuplicable), 0xc80ULL, nullptr, nullptr, OperandInfo359,0,nullptr }, // Inst #2765 = tPICADD
5974  { 2766, 3, 0, 356, 2, 0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, ImplicitList2, ImplicitList2, OperandInfo360,0,nullptr }, // Inst #2766 = tPOP
5975  { 2767, 3, 0, 357, 2, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo360,0,nullptr }, // Inst #2767 = tPOP_RET
5976  { 2768, 3, 0, 376, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, ImplicitList2, ImplicitList2, OperandInfo360,0,nullptr }, // Inst #2768 = tPUSH
5977  { 2769, 4, 1, 16, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo346,0,nullptr }, // Inst #2769 = tREV
5978  { 2770, 4, 1, 16, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo346,0,nullptr }, // Inst #2770 = tREV16
5979  { 2771, 4, 1, 16, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo346,0,nullptr }, // Inst #2771 = tREVSH
5980  { 2772, 6, 2, 49, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo332,0,nullptr }, // Inst #2772 = tROR
5981  { 2773, 5, 2, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo358,0,nullptr }, // Inst #2773 = tRSB
5982  { 2774, 6, 2, 258, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, ImplicitList1, nullptr, OperandInfo332,0,nullptr }, // Inst #2774 = tSBC
5983  { 2775, 1, 0, 0, 2, 0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5,ARM_HasV8Ops,nullptr }, // Inst #2775 = tSETEND
5984  { 2776, 5, 1, 375, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, nullptr, nullptr, OperandInfo361,0,nullptr }, // Inst #2776 = tSTMIA_UPD
5985  { 2777, 5, 0, 363, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc87ULL, nullptr, nullptr, OperandInfo349,0,nullptr }, // Inst #2777 = tSTRBi
5986  { 2778, 5, 0, 359, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc87ULL, nullptr, nullptr, OperandInfo350,0,nullptr }, // Inst #2778 = tSTRBr
5987  { 2779, 5, 0, 363, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc88ULL, nullptr, nullptr, OperandInfo349,0,nullptr }, // Inst #2779 = tSTRHi
5988  { 2780, 5, 0, 359, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc88ULL, nullptr, nullptr, OperandInfo350,0,nullptr }, // Inst #2780 = tSTRHr
5989  { 2781, 5, 0, 364, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc89ULL, nullptr, nullptr, OperandInfo349,0,nullptr }, // Inst #2781 = tSTRi
5990  { 2782, 5, 0, 358, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc89ULL, nullptr, nullptr, OperandInfo350,0,nullptr }, // Inst #2782 = tSTRr
5991  { 2783, 5, 0, 364, 2, 0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8aULL, nullptr, nullptr, OperandInfo352,0,nullptr }, // Inst #2783 = tSTRspi
5992  { 2784, 6, 2, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo334,0,nullptr }, // Inst #2784 = tSUBi3
5993  { 2785, 6, 2, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo335,0,nullptr }, // Inst #2785 = tSUBi8
5994  { 2786, 6, 2, 258, 2, 0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, nullptr, nullptr, OperandInfo338,0,nullptr }, // Inst #2786 = tSUBrr
5995  { 2787, 5, 1, 259, 2, 0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo339,0,nullptr }, // Inst #2787 = tSUBspi
5996  { 2788, 3, 0, 10, 2, 0|(1<<MCID_Call)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, ImplicitList2, nullptr, OperandInfo48,0,nullptr }, // Inst #2788 = tSVC
5997  { 2789, 4, 1, 16, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo346,0,nullptr }, // Inst #2789 = tSXTB
5998  { 2790, 4, 1, 16, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo346,0,nullptr }, // Inst #2790 = tSXTH
5999  { 2791, 3, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo35,0,nullptr }, // Inst #2791 = tTAILJMPd
6000  { 2792, 3, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo35,0,nullptr }, // Inst #2792 = tTAILJMPdND
6001  { 2793, 1, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, nullptr, OperandInfo126,0,nullptr }, // Inst #2793 = tTAILJMPr
6002  { 2794, 0, 0, 10, 4, 0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList9, nullptr,0,nullptr }, // Inst #2794 = tTPsoft
6003  { 2795, 0, 0, 10, 2, 0|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, nullptr,0,nullptr }, // Inst #2795 = tTRAP
6004  { 2796, 4, 0, 263, 2, 0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0xc80ULL, nullptr, ImplicitList1, OperandInfo346,0,nullptr }, // Inst #2796 = tTST
6005  { 2797, 1, 0, 76, 2, 0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo5,0,nullptr }, // Inst #2797 = tUDF
6006  { 2798, 4, 1, 16, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo346,0,nullptr }, // Inst #2798 = tUXTB
6007  { 2799, 4, 1, 16, 2, 0|(1<<MCID_Predicable), 0xc80ULL, nullptr, nullptr, OperandInfo346,0,nullptr }, // Inst #2799 = tUXTH
6008 };
6009 
6010 #endif // GET_INSTRINFO_MC_DESC
6011 
MCOI_OPERAND_PCREL
@ MCOI_OPERAND_PCREL
Definition: MCInstrDesc.h:48
MCOI_OPERAND_UNKNOWN
@ MCOI_OPERAND_UNKNOWN
Definition: MCInstrDesc.h:44
MCOI_OPERAND_IMMEDIATE
@ MCOI_OPERAND_IMMEDIATE
Definition: MCInstrDesc.h:45
MCOI_OPERAND_REGISTER
@ MCOI_OPERAND_REGISTER
Definition: MCInstrDesc.h:46
MCOI_Predicate
@ MCOI_Predicate
Definition: MCInstrDesc.h:38
MCOI_OptionalDef
@ MCOI_OptionalDef
Definition: MCInstrDesc.h:39
MCOI_LookupPtrRegClass
@ MCOI_LookupPtrRegClass
Definition: MCInstrDesc.h:37
MCID_FoldableAsLoad
@ MCID_FoldableAsLoad
Definition: MCInstrDesc.h:98
MCID_Compare
@ MCID_Compare
Definition: MCInstrDesc.h:93
MCID_Return
@ MCID_Return
Definition: MCInstrDesc.h:87
MCID_Branch
@ MCID_Branch
Definition: MCInstrDesc.h:91
MCID_Terminator
@ MCID_Terminator
Definition: MCInstrDesc.h:90
MCID_HasOptionalDef
@ MCID_HasOptionalDef
Definition: MCInstrDesc.h:85
MCID_UsesCustomInserter
@ MCID_UsesCustomInserter
Definition: MCInstrDesc.h:106
MCID_ExtraSrcRegAllocReq
@ MCID_ExtraSrcRegAllocReq
Definition: MCInstrDesc.h:110
MCID_ExtractSubreg
@ MCID_ExtractSubreg
Definition: MCInstrDesc.h:113
MCID_MayLoad
@ MCID_MayLoad
Definition: MCInstrDesc.h:99
MCID_Pseudo
@ MCID_Pseudo
Definition: MCInstrDesc.h:86
MCID_HasPostISelHook
@ MCID_HasPostISelHook
Definition: MCInstrDesc.h:107
MCID_Bitcast
@ MCID_Bitcast
Definition: MCInstrDesc.h:95
MCID_Predicable
@ MCID_Predicable
Definition: MCInstrDesc.h:101
MCID_Commutable
@ MCID_Commutable
Definition: MCInstrDesc.h:104
MCID_Variadic
@ MCID_Variadic
Definition: MCInstrDesc.h:84
MCID_MoveImm
@ MCID_MoveImm
Definition: MCInstrDesc.h:94
MCID_Select
@ MCID_Select
Definition: MCInstrDesc.h:96
MCID_InsertSubreg
@ MCID_InsertSubreg
Definition: MCInstrDesc.h:114
MCID_MayStore
@ MCID_MayStore
Definition: MCInstrDesc.h:100
MCID_RegSequence
@ MCID_RegSequence
Definition: MCInstrDesc.h:112
MCID_NotDuplicable
@ MCID_NotDuplicable
Definition: MCInstrDesc.h:102
MCID_UnmodeledSideEffects
@ MCID_UnmodeledSideEffects
Definition: MCInstrDesc.h:103
MCID_ExtraDefRegAllocReq
@ MCID_ExtraDefRegAllocReq
Definition: MCInstrDesc.h:111
MCID_CheapAsAMove
@ MCID_CheapAsAMove
Definition: MCInstrDesc.h:109
MCID_Rematerializable
@ MCID_Rematerializable
Definition: MCInstrDesc.h:108
MCID_IndirectBranch
@ MCID_IndirectBranch
Definition: MCInstrDesc.h:92
MCID_Call
@ MCID_Call
Definition: MCInstrDesc.h:88
MCID_Barrier
@ MCID_Barrier
Definition: MCInstrDesc.h:89
MCOI_TIED_TO
@ MCOI_TIED_TO
Definition: MCInstrDesc.h:29
MCOI_EARLY_CLOBBER
@ MCOI_EARLY_CLOBBER
Definition: MCInstrDesc.h:30
ARM_UXTH
@ ARM_UXTH
Definition: armass64.c:35
ARM_SXTB
@ ARM_SXTB
Definition: armass64.c:38
ARM_UXTB
@ ARM_UXTB
Definition: armass64.c:34
ARM_SXTH
@ ARM_SXTH
Definition: armass64.c:39