12 #include "../../MCInst.h"
13 #include "../../LEB128.h"
16 #define FieldFromInstruction(fname, InsnType) \
17 static InsnType fname(InsnType insn, unsigned startBit, unsigned numBits) \
20 if (numBits == sizeof(InsnType)*8) \
21 fieldMask = (InsnType)(-1LL); \
23 fieldMask = (((InsnType)1 << numBits) - 1) << startBit; \
24 return (insn & fieldMask) >> startBit; \
27 static const uint8_t DecoderTableARM32[] = {
274 MCD_OPC_SoftFail, 128, 128, 128, 128, 1 , 128, 128, 128, 128, 14 ,
1896 static const uint8_t DecoderTableNEONData32[] = {
5439 static const uint8_t DecoderTableNEONDup32[] = {
5532 static const uint8_t DecoderTableNEONLoadStore32[] = {
6919 static const uint8_t DecoderTableThumb16[] = {
7156 static const uint8_t DecoderTableThumb32[] = {
7173 static uint8_t DecoderTableThumb216[] = {
7181 static const uint8_t DecoderTableThumb232[] = {
8768 static const uint8_t DecoderTableThumbSBit16[] = {
8847 static const uint8_t DecoderTableVFP32[] = {
9476 static const uint8_t DecoderTableVFPV832[] = {
9698 static const uint8_t DecoderTablev8Crypto32[] = {
9799 static const uint8_t DecoderTablev8NEON32[] = {
10020 static bool checkDecoderPredicate(
unsigned Idx,
uint64_t Bits)
10025 return getbool(!(Bits & ARM_ModeThumb));
10027 return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_HasV6Ops));
10029 return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_HasV8Ops) && (Bits & ARM_FeatureCRC));
10031 return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_HasV5TEOps));
10033 return getbool(!(Bits & ARM_HasV8Ops));
10035 return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_HasV8Ops));
10037 return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_FeatureVirtualization));
10039 return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_HasV4TOps));
10041 return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_HasV5TOps));
10043 return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_FeatureTrustZone));
10045 return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_HasV6T2Ops));
10047 return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_HasV7Ops));
10049 return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_HasV7Ops) && (Bits & ARM_FeatureMP));
10051 return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_FeatureDB));
10053 return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_FeatureHWDivARM));
10055 return getbool(!(Bits & ARM_ModeThumb) && (Bits & ARM_FeatureNaClTrap));
10057 return getbool((Bits & ARM_FeatureNEON));
10059 return getbool((Bits & ARM_HasV8Ops) && (Bits & ARM_FeatureCrypto));
10061 return getbool((Bits & ARM_FeatureNEON) && (Bits & ARM_FeatureFP16));
10063 return getbool((Bits & ARM_FeatureNEON) && (Bits & ARM_FeatureVFP4));
10065 return getbool((Bits & ARM_FeatureVFP2));
10067 return getbool((Bits & ARM_ModeThumb));
10069 return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_HasV5TOps));
10071 return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_HasV6Ops));
10073 return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2));
10075 return getbool(!(Bits & ARM_FeatureMClass));
10077 return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_HasV8Ops));
10079 return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_HasV6MOps));
10081 return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_HasV5TOps) && !(Bits & ARM_FeatureMClass));
10083 return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2) && !(Bits & ARM_FeatureMClass));
10085 return getbool((Bits & ARM_FeatureT2XtPk) && (Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2));
10087 return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2) && !(Bits & ARM_HasV8Ops));
10089 return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2) && (Bits & ARM_FeatureDSPThumb2));
10091 return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2) && (Bits & ARM_HasV7Ops));
10093 return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureDB));
10095 return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2) && (Bits & ARM_HasV8Ops));
10097 return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2) && !(Bits & ARM_FeatureMClass) && !(Bits & ARM_HasV8Ops));
10099 return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2) && (Bits & ARM_FeatureVirtualization));
10101 return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2) && (Bits & ARM_FeatureTrustZone));
10103 return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureVirtualization));
10105 return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureMClass));
10107 return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2) && (Bits & ARM_HasV7Ops) && (Bits & ARM_FeatureMP));
10109 return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2) && (Bits & ARM_FeatureT2XtPk));
10111 return getbool((Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2) && (Bits & ARM_HasV8Ops) && (Bits & ARM_FeatureCRC));
10113 return getbool((Bits & ARM_FeatureHWDiv) && (Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2));
10115 return getbool(!(Bits & ARM_HasV8Ops) && (Bits & ARM_ModeThumb) && (Bits & ARM_FeatureThumb2));
10117 return getbool((Bits & ARM_FeatureVFP2) && !(Bits & ARM_FeatureVFPOnlySP));
10119 return getbool((Bits & ARM_FeatureVFP4));
10121 return getbool((Bits & ARM_FeatureVFP4) && !(Bits & ARM_FeatureVFPOnlySP));
10123 return getbool((Bits & ARM_FeatureVFP3));
10125 return getbool((Bits & ARM_FeatureFPARMv8));
10127 return getbool((Bits & ARM_FeatureVFP3) && !(Bits & ARM_FeatureVFPOnlySP));
10129 return getbool((Bits & ARM_FeatureFPARMv8) && !(Bits & ARM_FeatureVFPOnlySP));
10131 return getbool((Bits & ARM_HasV8Ops) && (Bits & ARM_FeatureNEON));
10135 #define DecodeToMCInst(fname,fieldname, InsnType) \
10136 static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *MI, \
10137 uint64_t Address, const void *Decoder) \
10143 tmp = fieldname(insn, 12, 4); \
10144 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10145 tmp = fieldname(insn, 16, 4); \
10146 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10147 tmp = fieldname(insn, 0, 4); \
10148 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10149 tmp = fieldname(insn, 28, 4); \
10150 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10151 tmp = fieldname(insn, 20, 1); \
10152 if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10155 tmp = fieldname(insn, 12, 4); \
10156 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10157 tmp = fieldname(insn, 16, 4); \
10158 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10160 tmp |= fieldname(insn, 0, 4) << 0; \
10161 tmp |= fieldname(insn, 5, 7) << 5; \
10162 if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10163 tmp = fieldname(insn, 28, 4); \
10164 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10165 tmp = fieldname(insn, 20, 1); \
10166 if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10169 tmp = fieldname(insn, 12, 4); \
10170 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10171 tmp = fieldname(insn, 16, 4); \
10172 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10174 tmp |= fieldname(insn, 0, 4) << 0; \
10175 tmp |= fieldname(insn, 5, 2) << 5; \
10176 tmp |= fieldname(insn, 8, 4) << 8; \
10177 if (!Check(&S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10178 tmp = fieldname(insn, 28, 4); \
10179 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10180 tmp = fieldname(insn, 20, 1); \
10181 if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10184 tmp = fieldname(insn, 12, 4); \
10185 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10186 tmp = fieldname(insn, 16, 4); \
10187 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10189 tmp |= fieldname(insn, 0, 4) << 0; \
10190 tmp |= fieldname(insn, 5, 2) << 5; \
10191 tmp |= fieldname(insn, 8, 4) << 8; \
10192 if (!Check(&S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10193 tmp = fieldname(insn, 28, 4); \
10194 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10195 tmp = fieldname(insn, 20, 1); \
10196 if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10199 tmp = fieldname(insn, 16, 4); \
10200 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10201 tmp = fieldname(insn, 0, 4); \
10202 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10203 tmp = fieldname(insn, 8, 4); \
10204 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10205 tmp = fieldname(insn, 28, 4); \
10206 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10207 tmp = fieldname(insn, 20, 1); \
10208 if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10211 tmp = fieldname(insn, 12, 4); \
10212 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10213 tmp = fieldname(insn, 16, 4); \
10214 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10215 tmp = fieldname(insn, 0, 4); \
10216 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10217 tmp = fieldname(insn, 8, 4); \
10218 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10219 tmp = fieldname(insn, 28, 4); \
10220 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10223 tmp = fieldname(insn, 12, 4); \
10224 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10225 tmp = fieldname(insn, 16, 4); \
10226 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10227 tmp = fieldname(insn, 0, 4); \
10228 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10229 tmp = fieldname(insn, 8, 4); \
10230 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10231 tmp = fieldname(insn, 28, 4); \
10232 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10233 tmp = fieldname(insn, 20, 1); \
10234 if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10237 if (!Check(&S, DecodeAddrMode3Instruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
10240 tmp = fieldname(insn, 12, 4); \
10241 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10242 tmp = fieldname(insn, 16, 4); \
10243 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10244 tmp = fieldname(insn, 0, 4); \
10245 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10248 if (!Check(&S, DecodeCPSInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
10251 tmp = fieldname(insn, 9, 1); \
10252 MCOperand_CreateImm0(MI, tmp); \
10255 tmp = fieldname(insn, 12, 4); \
10256 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10257 tmp = fieldname(insn, 28, 4); \
10258 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10261 if (!Check(&S, DecodeQADDInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
10264 if (!Check(&S, DecodeSMLAInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
10267 if (!Check(&S, DecodeSwap(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
10271 tmp |= fieldname(insn, 0, 4) << 0; \
10272 tmp |= fieldname(insn, 8, 12) << 4; \
10273 MCOperand_CreateImm0(MI, tmp); \
10276 tmp = fieldname(insn, 16, 4); \
10277 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10278 tmp = fieldname(insn, 0, 4); \
10279 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10280 tmp = fieldname(insn, 28, 4); \
10281 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10284 tmp = fieldname(insn, 16, 4); \
10285 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10287 tmp |= fieldname(insn, 0, 4) << 0; \
10288 tmp |= fieldname(insn, 5, 7) << 5; \
10289 if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10290 tmp = fieldname(insn, 28, 4); \
10291 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10294 tmp = fieldname(insn, 16, 4); \
10295 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10297 tmp |= fieldname(insn, 0, 4) << 0; \
10298 tmp |= fieldname(insn, 5, 2) << 5; \
10299 tmp |= fieldname(insn, 8, 4) << 8; \
10300 if (!Check(&S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10301 tmp = fieldname(insn, 28, 4); \
10302 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10305 tmp = fieldname(insn, 12, 4); \
10306 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10307 tmp = fieldname(insn, 16, 4); \
10308 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10309 tmp = fieldname(insn, 0, 4); \
10310 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10311 tmp = fieldname(insn, 8, 4); \
10312 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10313 tmp = fieldname(insn, 28, 4); \
10314 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10317 tmp = fieldname(insn, 12, 4); \
10318 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10319 tmp = fieldname(insn, 0, 4); \
10320 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10321 tmp = fieldname(insn, 16, 4); \
10322 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10323 tmp = fieldname(insn, 28, 4); \
10324 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10327 tmp = fieldname(insn, 0, 4); \
10328 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10329 tmp = fieldname(insn, 16, 4); \
10330 if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10331 tmp = fieldname(insn, 28, 4); \
10332 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10335 tmp = fieldname(insn, 12, 4); \
10336 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10337 tmp = fieldname(insn, 16, 4); \
10338 if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10339 tmp = fieldname(insn, 28, 4); \
10340 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10343 tmp = fieldname(insn, 12, 4); \
10344 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10345 tmp = fieldname(insn, 0, 4); \
10346 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10347 tmp = fieldname(insn, 16, 4); \
10348 if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10349 tmp = fieldname(insn, 28, 4); \
10350 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10353 tmp = fieldname(insn, 12, 4); \
10354 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10356 tmp |= fieldname(insn, 8, 1) << 4; \
10357 tmp |= fieldname(insn, 16, 4) << 0; \
10358 tmp |= fieldname(insn, 22, 1) << 5; \
10359 if (!Check(&S, DecodeBankedReg(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10360 tmp = fieldname(insn, 28, 4); \
10361 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10365 tmp |= fieldname(insn, 16, 4) << 0; \
10366 tmp |= fieldname(insn, 22, 1) << 4; \
10367 if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10368 tmp = fieldname(insn, 0, 4); \
10369 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10370 tmp = fieldname(insn, 28, 4); \
10371 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10375 tmp |= fieldname(insn, 8, 1) << 4; \
10376 tmp |= fieldname(insn, 16, 4) << 0; \
10377 tmp |= fieldname(insn, 22, 1) << 5; \
10378 if (!Check(&S, DecodeBankedReg(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10379 tmp = fieldname(insn, 0, 4); \
10380 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10381 tmp = fieldname(insn, 28, 4); \
10382 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10385 tmp = fieldname(insn, 0, 4); \
10386 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10387 tmp = fieldname(insn, 28, 4); \
10388 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10391 tmp = fieldname(insn, 28, 4); \
10392 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10395 tmp = fieldname(insn, 16, 4); \
10396 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10397 tmp = fieldname(insn, 0, 4); \
10398 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10399 tmp = fieldname(insn, 8, 4); \
10400 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10401 tmp = fieldname(insn, 28, 4); \
10402 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10405 tmp = fieldname(insn, 12, 4); \
10406 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10407 tmp = fieldname(insn, 0, 4); \
10408 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10409 tmp = fieldname(insn, 28, 4); \
10410 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10411 tmp = fieldname(insn, 20, 1); \
10412 if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10415 tmp = fieldname(insn, 12, 4); \
10416 if (!Check(&S, DecodetcGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10417 tmp = fieldname(insn, 0, 4); \
10418 if (!Check(&S, DecodetcGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10419 tmp = fieldname(insn, 28, 4); \
10420 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10421 tmp = fieldname(insn, 20, 1); \
10422 if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10425 tmp = fieldname(insn, 12, 4); \
10426 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10428 tmp |= fieldname(insn, 0, 4) << 0; \
10429 tmp |= fieldname(insn, 5, 7) << 5; \
10430 if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10431 tmp = fieldname(insn, 28, 4); \
10432 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10433 tmp = fieldname(insn, 20, 1); \
10434 if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10437 tmp = fieldname(insn, 0, 4); \
10438 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10441 tmp = fieldname(insn, 12, 4); \
10442 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10443 tmp = fieldname(insn, 0, 4); \
10444 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10445 tmp = fieldname(insn, 28, 4); \
10446 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10449 tmp = fieldname(insn, 0, 4); \
10450 MCOperand_CreateImm0(MI, tmp); \
10451 tmp = fieldname(insn, 28, 4); \
10452 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10455 tmp = fieldname(insn, 12, 4); \
10456 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10458 tmp |= fieldname(insn, 0, 4) << 0; \
10459 tmp |= fieldname(insn, 5, 2) << 5; \
10460 tmp |= fieldname(insn, 8, 4) << 8; \
10461 if (!Check(&S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10462 tmp = fieldname(insn, 28, 4); \
10463 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10464 tmp = fieldname(insn, 20, 1); \
10465 if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10468 tmp = fieldname(insn, 12, 4); \
10469 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10471 tmp |= fieldname(insn, 0, 4) << 0; \
10472 tmp |= fieldname(insn, 5, 2) << 5; \
10473 tmp |= fieldname(insn, 8, 4) << 8; \
10474 if (!Check(&S, DecodeSORegRegOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10475 tmp = fieldname(insn, 28, 4); \
10476 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10477 tmp = fieldname(insn, 20, 1); \
10478 if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10481 tmp = fieldname(insn, 16, 4); \
10482 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10483 tmp = fieldname(insn, 0, 4); \
10484 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10485 tmp = fieldname(insn, 8, 4); \
10486 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10487 tmp = fieldname(insn, 12, 4); \
10488 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10489 tmp = fieldname(insn, 28, 4); \
10490 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10491 tmp = fieldname(insn, 20, 1); \
10492 if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10495 tmp = fieldname(insn, 16, 4); \
10496 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10497 tmp = fieldname(insn, 0, 4); \
10498 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10499 tmp = fieldname(insn, 8, 4); \
10500 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10501 tmp = fieldname(insn, 12, 4); \
10502 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10503 tmp = fieldname(insn, 28, 4); \
10504 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10507 tmp = fieldname(insn, 12, 4); \
10508 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10509 tmp = fieldname(insn, 16, 4); \
10510 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10511 tmp = fieldname(insn, 0, 4); \
10512 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10513 tmp = fieldname(insn, 8, 4); \
10514 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10515 tmp = fieldname(insn, 12, 4); \
10516 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10517 tmp = fieldname(insn, 16, 4); \
10518 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10519 tmp = fieldname(insn, 28, 4); \
10520 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10521 tmp = fieldname(insn, 20, 1); \
10522 if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10525 if (!Check(&S, DecodeDoubleRegStore(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
10528 if (!Check(&S, DecodeDoubleRegLoad(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
10531 tmp = fieldname(insn, 16, 4); \
10532 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10533 tmp = fieldname(insn, 12, 4); \
10534 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10535 tmp = fieldname(insn, 16, 4); \
10536 if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10538 tmp |= fieldname(insn, 0, 4) << 0; \
10539 tmp |= fieldname(insn, 23, 1) << 4; \
10540 if (!Check(&S, DecodePostIdxReg(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10541 tmp = fieldname(insn, 28, 4); \
10542 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10545 tmp = fieldname(insn, 16, 4); \
10546 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10547 tmp = fieldname(insn, 12, 4); \
10548 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10549 tmp = fieldname(insn, 16, 4); \
10550 if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10552 tmp |= fieldname(insn, 0, 4) << 0; \
10553 tmp |= fieldname(insn, 8, 4) << 4; \
10554 tmp |= fieldname(insn, 23, 1) << 8; \
10555 MCOperand_CreateImm0(MI, tmp); \
10556 tmp = fieldname(insn, 28, 4); \
10557 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10560 if (!Check(&S, DecodeLDR(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
10563 tmp = fieldname(insn, 12, 4); \
10564 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10565 tmp = fieldname(insn, 16, 4); \
10566 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10567 tmp = fieldname(insn, 16, 4); \
10568 if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10570 tmp |= fieldname(insn, 0, 4) << 0; \
10571 tmp |= fieldname(insn, 8, 4) << 4; \
10572 tmp |= fieldname(insn, 23, 1) << 8; \
10573 MCOperand_CreateImm0(MI, tmp); \
10574 tmp = fieldname(insn, 28, 4); \
10575 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10578 tmp = fieldname(insn, 12, 4); \
10579 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10580 tmp = fieldname(insn, 16, 4); \
10581 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10582 tmp = fieldname(insn, 0, 12); \
10583 MCOperand_CreateImm0(MI, tmp); \
10584 tmp = fieldname(insn, 28, 4); \
10585 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10586 tmp = fieldname(insn, 20, 1); \
10587 if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10590 tmp = fieldname(insn, 12, 4); \
10591 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10593 tmp |= fieldname(insn, 0, 12) << 0; \
10594 tmp |= fieldname(insn, 22, 2) << 12; \
10595 MCOperand_CreateImm0(MI, tmp); \
10596 tmp = fieldname(insn, 28, 4); \
10597 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10600 if (!Check(&S, DecodeArmMOVTWInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
10603 tmp = fieldname(insn, 16, 4); \
10604 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10605 tmp = fieldname(insn, 0, 12); \
10606 MCOperand_CreateImm0(MI, tmp); \
10607 tmp = fieldname(insn, 28, 4); \
10608 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10611 tmp = fieldname(insn, 0, 8); \
10612 MCOperand_CreateImm0(MI, tmp); \
10613 tmp = fieldname(insn, 28, 4); \
10614 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10618 tmp |= fieldname(insn, 16, 4) << 0; \
10619 tmp |= fieldname(insn, 22, 1) << 4; \
10620 if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10621 tmp = fieldname(insn, 0, 12); \
10622 MCOperand_CreateImm0(MI, tmp); \
10623 tmp = fieldname(insn, 28, 4); \
10624 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10627 tmp = fieldname(insn, 12, 4); \
10628 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10629 tmp = fieldname(insn, 0, 12); \
10630 MCOperand_CreateImm0(MI, tmp); \
10631 tmp = fieldname(insn, 28, 4); \
10632 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10633 tmp = fieldname(insn, 20, 1); \
10634 if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10637 if (!Check(&S, DecodeAddrMode2IdxInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
10640 tmp = fieldname(insn, 12, 4); \
10641 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10643 tmp |= fieldname(insn, 0, 12) << 0; \
10644 tmp |= fieldname(insn, 16, 4) << 13; \
10645 tmp |= fieldname(insn, 23, 1) << 12; \
10646 if (!Check(&S, DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10647 tmp = fieldname(insn, 28, 4); \
10648 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10652 tmp |= fieldname(insn, 0, 12) << 0; \
10653 tmp |= fieldname(insn, 16, 4) << 13; \
10654 tmp |= fieldname(insn, 23, 1) << 12; \
10655 if (!Check(&S, DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10658 if (!Check(&S, DecodeSTRPreImm(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
10661 if (!Check(&S, DecodeLDRPreImm(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
10664 tmp = fieldname(insn, 12, 4); \
10665 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10667 tmp |= fieldname(insn, 0, 12) << 0; \
10668 tmp |= fieldname(insn, 16, 4) << 13; \
10669 tmp |= fieldname(insn, 23, 1) << 12; \
10670 if (!Check(&S, DecodeAddrModeImm12Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10671 tmp = fieldname(insn, 28, 4); \
10672 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10677 tmp = fieldname(insn, 0, 4); \
10678 if (!Check(&S, DecodeMemBarrierOption(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10681 tmp = fieldname(insn, 0, 4); \
10682 if (!Check(&S, DecodeInstSyncBarrierOption(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10685 tmp = fieldname(insn, 12, 4); \
10686 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10688 tmp |= fieldname(insn, 0, 4) << 0; \
10689 tmp |= fieldname(insn, 5, 7) << 5; \
10690 tmp |= fieldname(insn, 16, 4) << 13; \
10691 tmp |= fieldname(insn, 23, 1) << 12; \
10692 if (!Check(&S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10693 tmp = fieldname(insn, 28, 4); \
10694 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10698 tmp |= fieldname(insn, 0, 4) << 0; \
10699 tmp |= fieldname(insn, 5, 7) << 5; \
10700 tmp |= fieldname(insn, 16, 4) << 13; \
10701 tmp |= fieldname(insn, 23, 1) << 12; \
10702 if (!Check(&S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10705 tmp = fieldname(insn, 12, 4); \
10706 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10707 tmp = fieldname(insn, 16, 4); \
10708 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10709 tmp = fieldname(insn, 0, 4); \
10710 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10711 tmp = fieldname(insn, 28, 4); \
10712 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10715 tmp = fieldname(insn, 12, 4); \
10716 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10717 tmp = fieldname(insn, 16, 4); \
10718 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10719 tmp = fieldname(insn, 0, 4); \
10720 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10721 tmp = fieldname(insn, 7, 5); \
10722 MCOperand_CreateImm0(MI, tmp); \
10723 tmp = fieldname(insn, 28, 4); \
10724 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10727 tmp = fieldname(insn, 16, 4); \
10728 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10729 tmp = fieldname(insn, 0, 4); \
10730 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10731 tmp = fieldname(insn, 8, 4); \
10732 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10733 tmp = fieldname(insn, 28, 4); \
10734 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10737 tmp = fieldname(insn, 16, 4); \
10738 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10739 tmp = fieldname(insn, 0, 4); \
10740 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10741 tmp = fieldname(insn, 8, 4); \
10742 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10743 tmp = fieldname(insn, 12, 4); \
10744 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10745 tmp = fieldname(insn, 28, 4); \
10746 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10749 tmp = fieldname(insn, 12, 4); \
10750 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10751 tmp = fieldname(insn, 16, 4); \
10752 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10753 tmp = fieldname(insn, 0, 4); \
10754 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10755 tmp = fieldname(insn, 28, 4); \
10756 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10759 tmp = fieldname(insn, 12, 4); \
10760 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10761 tmp = fieldname(insn, 0, 4); \
10762 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10763 tmp = fieldname(insn, 10, 2); \
10764 MCOperand_CreateImm0(MI, tmp); \
10765 tmp = fieldname(insn, 28, 4); \
10766 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10769 tmp = fieldname(insn, 12, 4); \
10770 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10771 tmp = fieldname(insn, 16, 4); \
10772 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10773 tmp = fieldname(insn, 0, 4); \
10774 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10775 tmp = fieldname(insn, 10, 2); \
10776 MCOperand_CreateImm0(MI, tmp); \
10777 tmp = fieldname(insn, 28, 4); \
10778 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10781 if (!Check(&S, DecodeSTRPreReg(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
10784 if (!Check(&S, DecodeLDRPreReg(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
10787 tmp = fieldname(insn, 12, 4); \
10788 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10789 tmp = fieldname(insn, 16, 5); \
10790 MCOperand_CreateImm0(MI, tmp); \
10791 tmp = fieldname(insn, 0, 4); \
10792 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10794 tmp |= fieldname(insn, 6, 1) << 5; \
10795 tmp |= fieldname(insn, 7, 5) << 0; \
10796 MCOperand_CreateImm0(MI, tmp); \
10797 tmp = fieldname(insn, 28, 4); \
10798 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10801 tmp = fieldname(insn, 12, 4); \
10802 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10803 tmp = fieldname(insn, 16, 4); \
10804 MCOperand_CreateImm0(MI, tmp); \
10805 tmp = fieldname(insn, 0, 4); \
10806 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10807 tmp = fieldname(insn, 28, 4); \
10808 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10811 tmp = fieldname(insn, 12, 4); \
10812 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10813 tmp = fieldname(insn, 0, 4); \
10814 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10815 tmp = fieldname(insn, 7, 5); \
10816 MCOperand_CreateImm0(MI, tmp); \
10817 tmp = fieldname(insn, 16, 5); \
10818 MCOperand_CreateImm0(MI, tmp); \
10819 tmp = fieldname(insn, 28, 4); \
10820 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10823 tmp = fieldname(insn, 12, 4); \
10824 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10826 tmp |= fieldname(insn, 0, 4) << 0; \
10827 tmp |= fieldname(insn, 5, 7) << 5; \
10828 tmp |= fieldname(insn, 16, 4) << 13; \
10829 tmp |= fieldname(insn, 23, 1) << 12; \
10830 if (!Check(&S, DecodeSORegMemOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10831 tmp = fieldname(insn, 28, 4); \
10832 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10835 tmp = fieldname(insn, 12, 4); \
10836 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10837 tmp = fieldname(insn, 12, 4); \
10838 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10840 tmp |= fieldname(insn, 7, 5) << 0; \
10841 tmp |= fieldname(insn, 16, 5) << 5; \
10842 if (!Check(&S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10843 tmp = fieldname(insn, 28, 4); \
10844 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10847 tmp = fieldname(insn, 12, 4); \
10848 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10849 tmp = fieldname(insn, 12, 4); \
10850 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10851 tmp = fieldname(insn, 0, 4); \
10852 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10854 tmp |= fieldname(insn, 7, 5) << 0; \
10855 tmp |= fieldname(insn, 16, 5) << 5; \
10856 if (!Check(&S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10857 tmp = fieldname(insn, 28, 4); \
10858 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10861 tmp = fieldname(insn, 16, 4); \
10862 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10863 tmp = fieldname(insn, 28, 4); \
10864 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10865 tmp = fieldname(insn, 0, 16); \
10866 if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10869 tmp = fieldname(insn, 16, 4); \
10870 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10873 if (!Check(&S, DecodeMemMultipleWritebackInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
10876 tmp = fieldname(insn, 0, 5); \
10877 MCOperand_CreateImm0(MI, tmp); \
10880 if (!Check(&S, DecodeBranchImmInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
10884 tmp |= fieldname(insn, 0, 24) << 1; \
10885 tmp |= fieldname(insn, 24, 1) << 0; \
10886 MCOperand_CreateImm0(MI, tmp); \
10889 if (!Check(&S, DecodeCopMemInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
10892 if (!Check(&S, DecodeMRRC2(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
10895 tmp = fieldname(insn, 8, 4); \
10896 if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10897 tmp = fieldname(insn, 4, 4); \
10898 MCOperand_CreateImm0(MI, tmp); \
10899 tmp = fieldname(insn, 12, 4); \
10900 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10901 tmp = fieldname(insn, 16, 4); \
10902 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10903 tmp = fieldname(insn, 0, 4); \
10904 MCOperand_CreateImm0(MI, tmp); \
10905 tmp = fieldname(insn, 28, 4); \
10906 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10909 tmp = fieldname(insn, 8, 4); \
10910 if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10911 tmp = fieldname(insn, 20, 4); \
10912 MCOperand_CreateImm0(MI, tmp); \
10913 tmp = fieldname(insn, 12, 4); \
10914 MCOperand_CreateImm0(MI, tmp); \
10915 tmp = fieldname(insn, 16, 4); \
10916 MCOperand_CreateImm0(MI, tmp); \
10917 tmp = fieldname(insn, 0, 4); \
10918 MCOperand_CreateImm0(MI, tmp); \
10919 tmp = fieldname(insn, 5, 3); \
10920 MCOperand_CreateImm0(MI, tmp); \
10923 tmp = fieldname(insn, 8, 4); \
10924 if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10925 tmp = fieldname(insn, 20, 4); \
10926 MCOperand_CreateImm0(MI, tmp); \
10927 tmp = fieldname(insn, 12, 4); \
10928 MCOperand_CreateImm0(MI, tmp); \
10929 tmp = fieldname(insn, 16, 4); \
10930 MCOperand_CreateImm0(MI, tmp); \
10931 tmp = fieldname(insn, 0, 4); \
10932 MCOperand_CreateImm0(MI, tmp); \
10933 tmp = fieldname(insn, 5, 3); \
10934 MCOperand_CreateImm0(MI, tmp); \
10935 tmp = fieldname(insn, 28, 4); \
10936 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10939 tmp = fieldname(insn, 8, 4); \
10940 if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10941 tmp = fieldname(insn, 21, 3); \
10942 MCOperand_CreateImm0(MI, tmp); \
10943 tmp = fieldname(insn, 12, 4); \
10944 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10945 tmp = fieldname(insn, 16, 4); \
10946 MCOperand_CreateImm0(MI, tmp); \
10947 tmp = fieldname(insn, 0, 4); \
10948 MCOperand_CreateImm0(MI, tmp); \
10949 tmp = fieldname(insn, 5, 3); \
10950 MCOperand_CreateImm0(MI, tmp); \
10953 tmp = fieldname(insn, 8, 4); \
10954 if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10955 tmp = fieldname(insn, 21, 3); \
10956 MCOperand_CreateImm0(MI, tmp); \
10957 tmp = fieldname(insn, 12, 4); \
10958 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10959 tmp = fieldname(insn, 16, 4); \
10960 MCOperand_CreateImm0(MI, tmp); \
10961 tmp = fieldname(insn, 0, 4); \
10962 MCOperand_CreateImm0(MI, tmp); \
10963 tmp = fieldname(insn, 5, 3); \
10964 MCOperand_CreateImm0(MI, tmp); \
10965 tmp = fieldname(insn, 28, 4); \
10966 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10969 tmp = fieldname(insn, 12, 4); \
10970 if (!Check(&S, DecodeGPRwithAPSRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10971 tmp = fieldname(insn, 8, 4); \
10972 if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10973 tmp = fieldname(insn, 21, 3); \
10974 MCOperand_CreateImm0(MI, tmp); \
10975 tmp = fieldname(insn, 16, 4); \
10976 MCOperand_CreateImm0(MI, tmp); \
10977 tmp = fieldname(insn, 0, 4); \
10978 MCOperand_CreateImm0(MI, tmp); \
10979 tmp = fieldname(insn, 5, 3); \
10980 MCOperand_CreateImm0(MI, tmp); \
10983 tmp = fieldname(insn, 12, 4); \
10984 if (!Check(&S, DecodeGPRwithAPSRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10985 tmp = fieldname(insn, 8, 4); \
10986 if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10987 tmp = fieldname(insn, 21, 3); \
10988 MCOperand_CreateImm0(MI, tmp); \
10989 tmp = fieldname(insn, 16, 4); \
10990 MCOperand_CreateImm0(MI, tmp); \
10991 tmp = fieldname(insn, 0, 4); \
10992 MCOperand_CreateImm0(MI, tmp); \
10993 tmp = fieldname(insn, 5, 3); \
10994 MCOperand_CreateImm0(MI, tmp); \
10995 tmp = fieldname(insn, 28, 4); \
10996 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
10999 tmp = fieldname(insn, 0, 24); \
11000 MCOperand_CreateImm0(MI, tmp); \
11001 tmp = fieldname(insn, 28, 4); \
11002 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11006 tmp |= fieldname(insn, 12, 4) << 0; \
11007 tmp |= fieldname(insn, 22, 1) << 4; \
11008 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11010 tmp |= fieldname(insn, 7, 1) << 4; \
11011 tmp |= fieldname(insn, 16, 4) << 0; \
11012 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11014 tmp |= fieldname(insn, 0, 4) << 0; \
11015 tmp |= fieldname(insn, 5, 1) << 4; \
11016 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11020 tmp |= fieldname(insn, 12, 4) << 0; \
11021 tmp |= fieldname(insn, 22, 1) << 4; \
11022 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11024 tmp |= fieldname(insn, 7, 1) << 4; \
11025 tmp |= fieldname(insn, 16, 4) << 0; \
11026 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11028 tmp |= fieldname(insn, 0, 4) << 0; \
11029 tmp |= fieldname(insn, 5, 1) << 4; \
11030 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11034 tmp |= fieldname(insn, 12, 4) << 0; \
11035 tmp |= fieldname(insn, 22, 1) << 4; \
11036 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11038 tmp |= fieldname(insn, 7, 1) << 4; \
11039 tmp |= fieldname(insn, 16, 4) << 0; \
11040 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11042 tmp |= fieldname(insn, 0, 4) << 0; \
11043 tmp |= fieldname(insn, 5, 1) << 4; \
11044 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11048 tmp |= fieldname(insn, 12, 4) << 0; \
11049 tmp |= fieldname(insn, 22, 1) << 4; \
11050 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11052 tmp |= fieldname(insn, 7, 1) << 4; \
11053 tmp |= fieldname(insn, 16, 4) << 0; \
11054 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11056 tmp |= fieldname(insn, 0, 4) << 0; \
11057 tmp |= fieldname(insn, 5, 1) << 4; \
11058 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11062 tmp |= fieldname(insn, 12, 4) << 0; \
11063 tmp |= fieldname(insn, 22, 1) << 4; \
11064 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11066 tmp |= fieldname(insn, 0, 4) << 0; \
11067 tmp |= fieldname(insn, 5, 1) << 4; \
11068 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11070 tmp |= fieldname(insn, 7, 1) << 4; \
11071 tmp |= fieldname(insn, 16, 4) << 0; \
11072 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11076 tmp |= fieldname(insn, 12, 4) << 0; \
11077 tmp |= fieldname(insn, 22, 1) << 4; \
11078 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11080 tmp |= fieldname(insn, 0, 4) << 0; \
11081 tmp |= fieldname(insn, 5, 1) << 4; \
11082 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11084 tmp |= fieldname(insn, 7, 1) << 4; \
11085 tmp |= fieldname(insn, 16, 4) << 0; \
11086 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11090 tmp |= fieldname(insn, 12, 4) << 0; \
11091 tmp |= fieldname(insn, 22, 1) << 4; \
11092 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11094 tmp |= fieldname(insn, 7, 1) << 4; \
11095 tmp |= fieldname(insn, 16, 4) << 0; \
11096 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11098 tmp |= fieldname(insn, 0, 4) << 0; \
11099 tmp |= fieldname(insn, 5, 1) << 4; \
11100 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11104 tmp |= fieldname(insn, 12, 4) << 0; \
11105 tmp |= fieldname(insn, 22, 1) << 4; \
11106 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11108 tmp |= fieldname(insn, 12, 4) << 0; \
11109 tmp |= fieldname(insn, 22, 1) << 4; \
11110 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11112 tmp |= fieldname(insn, 7, 1) << 4; \
11113 tmp |= fieldname(insn, 16, 4) << 0; \
11114 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11116 tmp |= fieldname(insn, 0, 4) << 0; \
11117 tmp |= fieldname(insn, 5, 1) << 4; \
11118 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11122 tmp |= fieldname(insn, 12, 4) << 0; \
11123 tmp |= fieldname(insn, 22, 1) << 4; \
11124 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11126 tmp |= fieldname(insn, 12, 4) << 0; \
11127 tmp |= fieldname(insn, 22, 1) << 4; \
11128 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11130 tmp |= fieldname(insn, 7, 1) << 4; \
11131 tmp |= fieldname(insn, 16, 4) << 0; \
11132 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11134 tmp |= fieldname(insn, 0, 4) << 0; \
11135 tmp |= fieldname(insn, 5, 1) << 4; \
11136 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11140 tmp |= fieldname(insn, 12, 4) << 0; \
11141 tmp |= fieldname(insn, 22, 1) << 4; \
11142 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11144 tmp |= fieldname(insn, 12, 4) << 0; \
11145 tmp |= fieldname(insn, 22, 1) << 4; \
11146 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11148 tmp |= fieldname(insn, 7, 1) << 4; \
11149 tmp |= fieldname(insn, 16, 4) << 0; \
11150 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11152 tmp |= fieldname(insn, 0, 4) << 0; \
11153 tmp |= fieldname(insn, 5, 1) << 4; \
11154 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11158 tmp |= fieldname(insn, 12, 4) << 0; \
11159 tmp |= fieldname(insn, 22, 1) << 4; \
11160 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11162 tmp |= fieldname(insn, 12, 4) << 0; \
11163 tmp |= fieldname(insn, 22, 1) << 4; \
11164 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11166 tmp |= fieldname(insn, 7, 1) << 4; \
11167 tmp |= fieldname(insn, 16, 4) << 0; \
11168 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11169 tmp = fieldname(insn, 0, 3); \
11170 if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11172 tmp |= fieldname(insn, 3, 1) << 0; \
11173 tmp |= fieldname(insn, 5, 1) << 1; \
11174 MCOperand_CreateImm0(MI, tmp); \
11178 tmp |= fieldname(insn, 12, 4) << 0; \
11179 tmp |= fieldname(insn, 22, 1) << 4; \
11180 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11182 tmp |= fieldname(insn, 12, 4) << 0; \
11183 tmp |= fieldname(insn, 22, 1) << 4; \
11184 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11186 tmp |= fieldname(insn, 7, 1) << 4; \
11187 tmp |= fieldname(insn, 16, 4) << 0; \
11188 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11189 tmp = fieldname(insn, 0, 3); \
11190 if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11192 tmp |= fieldname(insn, 3, 1) << 0; \
11193 tmp |= fieldname(insn, 5, 1) << 1; \
11194 MCOperand_CreateImm0(MI, tmp); \
11198 tmp |= fieldname(insn, 12, 4) << 0; \
11199 tmp |= fieldname(insn, 22, 1) << 4; \
11200 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11202 tmp |= fieldname(insn, 12, 4) << 0; \
11203 tmp |= fieldname(insn, 22, 1) << 4; \
11204 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11206 tmp |= fieldname(insn, 7, 1) << 4; \
11207 tmp |= fieldname(insn, 16, 4) << 0; \
11208 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11209 tmp = fieldname(insn, 0, 3); \
11210 if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11212 tmp |= fieldname(insn, 3, 1) << 0; \
11213 tmp |= fieldname(insn, 5, 1) << 1; \
11214 MCOperand_CreateImm0(MI, tmp); \
11218 tmp |= fieldname(insn, 12, 4) << 0; \
11219 tmp |= fieldname(insn, 22, 1) << 4; \
11220 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11222 tmp |= fieldname(insn, 7, 1) << 4; \
11223 tmp |= fieldname(insn, 16, 4) << 0; \
11224 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11225 tmp = fieldname(insn, 0, 3); \
11226 if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11228 tmp |= fieldname(insn, 3, 1) << 0; \
11229 tmp |= fieldname(insn, 5, 1) << 1; \
11230 MCOperand_CreateImm0(MI, tmp); \
11234 tmp |= fieldname(insn, 12, 4) << 0; \
11235 tmp |= fieldname(insn, 22, 1) << 4; \
11236 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11238 tmp |= fieldname(insn, 7, 1) << 4; \
11239 tmp |= fieldname(insn, 16, 4) << 0; \
11240 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11241 tmp = fieldname(insn, 0, 3); \
11242 if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11244 tmp |= fieldname(insn, 3, 1) << 0; \
11245 tmp |= fieldname(insn, 5, 1) << 1; \
11246 MCOperand_CreateImm0(MI, tmp); \
11250 tmp |= fieldname(insn, 12, 4) << 0; \
11251 tmp |= fieldname(insn, 22, 1) << 4; \
11252 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11254 tmp |= fieldname(insn, 7, 1) << 4; \
11255 tmp |= fieldname(insn, 16, 4) << 0; \
11256 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11257 tmp = fieldname(insn, 0, 3); \
11258 if (!Check(&S, DecodeDPR_8RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11260 tmp |= fieldname(insn, 3, 1) << 0; \
11261 tmp |= fieldname(insn, 5, 1) << 1; \
11262 MCOperand_CreateImm0(MI, tmp); \
11266 tmp |= fieldname(insn, 12, 4) << 0; \
11267 tmp |= fieldname(insn, 22, 1) << 4; \
11268 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11270 tmp |= fieldname(insn, 12, 4) << 0; \
11271 tmp |= fieldname(insn, 22, 1) << 4; \
11272 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11274 tmp |= fieldname(insn, 7, 1) << 4; \
11275 tmp |= fieldname(insn, 16, 4) << 0; \
11276 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11277 tmp = fieldname(insn, 0, 4); \
11278 if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11279 tmp = fieldname(insn, 5, 1); \
11280 MCOperand_CreateImm0(MI, tmp); \
11284 tmp |= fieldname(insn, 12, 4) << 0; \
11285 tmp |= fieldname(insn, 22, 1) << 4; \
11286 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11288 tmp |= fieldname(insn, 12, 4) << 0; \
11289 tmp |= fieldname(insn, 22, 1) << 4; \
11290 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11292 tmp |= fieldname(insn, 7, 1) << 4; \
11293 tmp |= fieldname(insn, 16, 4) << 0; \
11294 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11295 tmp = fieldname(insn, 0, 4); \
11296 if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11297 tmp = fieldname(insn, 5, 1); \
11298 MCOperand_CreateImm0(MI, tmp); \
11302 tmp |= fieldname(insn, 12, 4) << 0; \
11303 tmp |= fieldname(insn, 22, 1) << 4; \
11304 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11306 tmp |= fieldname(insn, 12, 4) << 0; \
11307 tmp |= fieldname(insn, 22, 1) << 4; \
11308 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11310 tmp |= fieldname(insn, 7, 1) << 4; \
11311 tmp |= fieldname(insn, 16, 4) << 0; \
11312 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11313 tmp = fieldname(insn, 0, 4); \
11314 if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11315 tmp = fieldname(insn, 5, 1); \
11316 MCOperand_CreateImm0(MI, tmp); \
11320 tmp |= fieldname(insn, 12, 4) << 0; \
11321 tmp |= fieldname(insn, 22, 1) << 4; \
11322 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11324 tmp |= fieldname(insn, 7, 1) << 4; \
11325 tmp |= fieldname(insn, 16, 4) << 0; \
11326 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11327 tmp = fieldname(insn, 0, 4); \
11328 if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11329 tmp = fieldname(insn, 5, 1); \
11330 MCOperand_CreateImm0(MI, tmp); \
11334 tmp |= fieldname(insn, 12, 4) << 0; \
11335 tmp |= fieldname(insn, 22, 1) << 4; \
11336 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11338 tmp |= fieldname(insn, 7, 1) << 4; \
11339 tmp |= fieldname(insn, 16, 4) << 0; \
11340 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11341 tmp = fieldname(insn, 0, 4); \
11342 if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11343 tmp = fieldname(insn, 5, 1); \
11344 MCOperand_CreateImm0(MI, tmp); \
11348 tmp |= fieldname(insn, 12, 4) << 0; \
11349 tmp |= fieldname(insn, 22, 1) << 4; \
11350 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11352 tmp |= fieldname(insn, 7, 1) << 4; \
11353 tmp |= fieldname(insn, 16, 4) << 0; \
11354 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11355 tmp = fieldname(insn, 0, 4); \
11356 if (!Check(&S, DecodeDPR_VFP2RegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11357 tmp = fieldname(insn, 5, 1); \
11358 MCOperand_CreateImm0(MI, tmp); \
11362 tmp |= fieldname(insn, 12, 4) << 0; \
11363 tmp |= fieldname(insn, 22, 1) << 4; \
11364 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11366 tmp |= fieldname(insn, 7, 1) << 4; \
11367 tmp |= fieldname(insn, 16, 4) << 0; \
11368 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11370 tmp |= fieldname(insn, 0, 4) << 0; \
11371 tmp |= fieldname(insn, 5, 1) << 4; \
11372 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11373 tmp = fieldname(insn, 10, 1); \
11374 MCOperand_CreateImm0(MI, tmp); \
11378 tmp |= fieldname(insn, 12, 4) << 0; \
11379 tmp |= fieldname(insn, 22, 1) << 4; \
11380 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11382 tmp |= fieldname(insn, 7, 1) << 4; \
11383 tmp |= fieldname(insn, 16, 4) << 0; \
11384 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11386 tmp |= fieldname(insn, 0, 4) << 0; \
11387 tmp |= fieldname(insn, 5, 1) << 4; \
11388 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11389 tmp = fieldname(insn, 9, 2); \
11390 MCOperand_CreateImm0(MI, tmp); \
11394 tmp |= fieldname(insn, 12, 4) << 0; \
11395 tmp |= fieldname(insn, 22, 1) << 4; \
11396 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11398 tmp |= fieldname(insn, 7, 1) << 4; \
11399 tmp |= fieldname(insn, 16, 4) << 0; \
11400 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11402 tmp |= fieldname(insn, 0, 4) << 0; \
11403 tmp |= fieldname(insn, 5, 1) << 4; \
11404 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11405 tmp = fieldname(insn, 8, 3); \
11406 MCOperand_CreateImm0(MI, tmp); \
11410 tmp |= fieldname(insn, 12, 4) << 0; \
11411 tmp |= fieldname(insn, 22, 1) << 4; \
11412 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11414 tmp |= fieldname(insn, 7, 1) << 4; \
11415 tmp |= fieldname(insn, 16, 4) << 0; \
11416 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11418 tmp |= fieldname(insn, 0, 4) << 0; \
11419 tmp |= fieldname(insn, 5, 1) << 4; \
11420 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11421 tmp = fieldname(insn, 11, 1); \
11422 MCOperand_CreateImm0(MI, tmp); \
11426 tmp |= fieldname(insn, 12, 4) << 0; \
11427 tmp |= fieldname(insn, 22, 1) << 4; \
11428 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11430 tmp |= fieldname(insn, 7, 1) << 4; \
11431 tmp |= fieldname(insn, 16, 4) << 0; \
11432 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11434 tmp |= fieldname(insn, 0, 4) << 0; \
11435 tmp |= fieldname(insn, 5, 1) << 4; \
11436 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11437 tmp = fieldname(insn, 10, 2); \
11438 MCOperand_CreateImm0(MI, tmp); \
11442 tmp |= fieldname(insn, 12, 4) << 0; \
11443 tmp |= fieldname(insn, 22, 1) << 4; \
11444 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11446 tmp |= fieldname(insn, 7, 1) << 4; \
11447 tmp |= fieldname(insn, 16, 4) << 0; \
11448 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11450 tmp |= fieldname(insn, 0, 4) << 0; \
11451 tmp |= fieldname(insn, 5, 1) << 4; \
11452 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11453 tmp = fieldname(insn, 9, 3); \
11454 MCOperand_CreateImm0(MI, tmp); \
11458 tmp |= fieldname(insn, 12, 4) << 0; \
11459 tmp |= fieldname(insn, 22, 1) << 4; \
11460 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11462 tmp |= fieldname(insn, 7, 1) << 4; \
11463 tmp |= fieldname(insn, 16, 4) << 0; \
11464 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11466 tmp |= fieldname(insn, 0, 4) << 0; \
11467 tmp |= fieldname(insn, 5, 1) << 4; \
11468 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11469 tmp = fieldname(insn, 8, 4); \
11470 MCOperand_CreateImm0(MI, tmp); \
11474 tmp |= fieldname(insn, 12, 4) << 0; \
11475 tmp |= fieldname(insn, 22, 1) << 4; \
11476 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11478 tmp |= fieldname(insn, 0, 4) << 0; \
11479 tmp |= fieldname(insn, 5, 1) << 4; \
11480 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11484 tmp |= fieldname(insn, 12, 4) << 0; \
11485 tmp |= fieldname(insn, 22, 1) << 4; \
11486 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11488 tmp |= fieldname(insn, 0, 4) << 0; \
11489 tmp |= fieldname(insn, 5, 1) << 4; \
11490 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11494 tmp |= fieldname(insn, 12, 4) << 0; \
11495 tmp |= fieldname(insn, 22, 1) << 4; \
11496 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11498 tmp |= fieldname(insn, 0, 4) << 0; \
11499 tmp |= fieldname(insn, 5, 1) << 4; \
11500 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11502 tmp |= fieldname(insn, 12, 4) << 0; \
11503 tmp |= fieldname(insn, 22, 1) << 4; \
11504 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11506 tmp |= fieldname(insn, 0, 4) << 0; \
11507 tmp |= fieldname(insn, 5, 1) << 4; \
11508 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11512 tmp |= fieldname(insn, 12, 4) << 0; \
11513 tmp |= fieldname(insn, 22, 1) << 4; \
11514 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11516 tmp |= fieldname(insn, 0, 4) << 0; \
11517 tmp |= fieldname(insn, 5, 1) << 4; \
11518 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11520 tmp |= fieldname(insn, 12, 4) << 0; \
11521 tmp |= fieldname(insn, 22, 1) << 4; \
11522 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11524 tmp |= fieldname(insn, 0, 4) << 0; \
11525 tmp |= fieldname(insn, 5, 1) << 4; \
11526 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11530 tmp |= fieldname(insn, 12, 4) << 0; \
11531 tmp |= fieldname(insn, 22, 1) << 4; \
11532 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11534 tmp |= fieldname(insn, 0, 4) << 0; \
11535 tmp |= fieldname(insn, 5, 1) << 4; \
11536 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11539 if (!Check(&S, DecodeVSHLMaxInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
11543 tmp |= fieldname(insn, 12, 4) << 0; \
11544 tmp |= fieldname(insn, 22, 1) << 4; \
11545 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11547 tmp |= fieldname(insn, 12, 4) << 0; \
11548 tmp |= fieldname(insn, 22, 1) << 4; \
11549 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11551 tmp |= fieldname(insn, 0, 4) << 0; \
11552 tmp |= fieldname(insn, 5, 1) << 4; \
11553 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11557 tmp |= fieldname(insn, 12, 4) << 0; \
11558 tmp |= fieldname(insn, 22, 1) << 4; \
11559 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11561 tmp |= fieldname(insn, 12, 4) << 0; \
11562 tmp |= fieldname(insn, 22, 1) << 4; \
11563 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11565 tmp |= fieldname(insn, 0, 4) << 0; \
11566 tmp |= fieldname(insn, 5, 1) << 4; \
11567 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11571 tmp |= fieldname(insn, 12, 4) << 0; \
11572 tmp |= fieldname(insn, 22, 1) << 4; \
11573 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11575 tmp |= fieldname(insn, 0, 4) << 0; \
11576 tmp |= fieldname(insn, 5, 1) << 4; \
11577 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11580 if (!Check(&S, DecodeTBLInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
11584 tmp |= fieldname(insn, 12, 4) << 0; \
11585 tmp |= fieldname(insn, 22, 1) << 4; \
11586 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11588 tmp |= fieldname(insn, 0, 4) << 0; \
11589 tmp |= fieldname(insn, 5, 1) << 4; \
11590 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11591 tmp = fieldname(insn, 19, 1); \
11592 MCOperand_CreateImm0(MI, tmp); \
11596 tmp |= fieldname(insn, 12, 4) << 0; \
11597 tmp |= fieldname(insn, 22, 1) << 4; \
11598 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11600 tmp |= fieldname(insn, 0, 4) << 0; \
11601 tmp |= fieldname(insn, 5, 1) << 4; \
11602 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11603 tmp = fieldname(insn, 18, 2); \
11604 MCOperand_CreateImm0(MI, tmp); \
11608 tmp |= fieldname(insn, 12, 4) << 0; \
11609 tmp |= fieldname(insn, 22, 1) << 4; \
11610 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11612 tmp |= fieldname(insn, 0, 4) << 0; \
11613 tmp |= fieldname(insn, 5, 1) << 4; \
11614 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11615 tmp = fieldname(insn, 17, 3); \
11616 MCOperand_CreateImm0(MI, tmp); \
11620 tmp |= fieldname(insn, 12, 4) << 0; \
11621 tmp |= fieldname(insn, 22, 1) << 4; \
11622 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11624 tmp |= fieldname(insn, 0, 4) << 0; \
11625 tmp |= fieldname(insn, 5, 1) << 4; \
11626 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11627 tmp = fieldname(insn, 19, 1); \
11628 MCOperand_CreateImm0(MI, tmp); \
11632 tmp |= fieldname(insn, 12, 4) << 0; \
11633 tmp |= fieldname(insn, 22, 1) << 4; \
11634 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11636 tmp |= fieldname(insn, 0, 4) << 0; \
11637 tmp |= fieldname(insn, 5, 1) << 4; \
11638 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11639 tmp = fieldname(insn, 18, 2); \
11640 MCOperand_CreateImm0(MI, tmp); \
11644 tmp |= fieldname(insn, 12, 4) << 0; \
11645 tmp |= fieldname(insn, 22, 1) << 4; \
11646 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11648 tmp |= fieldname(insn, 0, 4) << 0; \
11649 tmp |= fieldname(insn, 5, 1) << 4; \
11650 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11651 tmp = fieldname(insn, 17, 3); \
11652 MCOperand_CreateImm0(MI, tmp); \
11656 tmp |= fieldname(insn, 12, 4) << 0; \
11657 tmp |= fieldname(insn, 22, 1) << 4; \
11658 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11660 tmp |= fieldname(insn, 0, 4) << 0; \
11661 tmp |= fieldname(insn, 5, 1) << 4; \
11662 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11663 tmp = fieldname(insn, 16, 3); \
11664 if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11668 tmp |= fieldname(insn, 12, 4) << 0; \
11669 tmp |= fieldname(insn, 22, 1) << 4; \
11670 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11672 tmp |= fieldname(insn, 0, 4) << 0; \
11673 tmp |= fieldname(insn, 5, 1) << 4; \
11674 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11675 tmp = fieldname(insn, 16, 4); \
11676 if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11680 tmp |= fieldname(insn, 12, 4) << 0; \
11681 tmp |= fieldname(insn, 22, 1) << 4; \
11682 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11684 tmp |= fieldname(insn, 0, 4) << 0; \
11685 tmp |= fieldname(insn, 5, 1) << 4; \
11686 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11687 tmp = fieldname(insn, 16, 5); \
11688 if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11692 tmp |= fieldname(insn, 12, 4) << 0; \
11693 tmp |= fieldname(insn, 22, 1) << 4; \
11694 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11696 tmp |= fieldname(insn, 12, 4) << 0; \
11697 tmp |= fieldname(insn, 22, 1) << 4; \
11698 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11700 tmp |= fieldname(insn, 0, 4) << 0; \
11701 tmp |= fieldname(insn, 5, 1) << 4; \
11702 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11703 tmp = fieldname(insn, 16, 3); \
11704 if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11708 tmp |= fieldname(insn, 12, 4) << 0; \
11709 tmp |= fieldname(insn, 22, 1) << 4; \
11710 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11712 tmp |= fieldname(insn, 12, 4) << 0; \
11713 tmp |= fieldname(insn, 22, 1) << 4; \
11714 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11716 tmp |= fieldname(insn, 0, 4) << 0; \
11717 tmp |= fieldname(insn, 5, 1) << 4; \
11718 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11719 tmp = fieldname(insn, 16, 4); \
11720 if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11724 tmp |= fieldname(insn, 12, 4) << 0; \
11725 tmp |= fieldname(insn, 22, 1) << 4; \
11726 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11728 tmp |= fieldname(insn, 12, 4) << 0; \
11729 tmp |= fieldname(insn, 22, 1) << 4; \
11730 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11732 tmp |= fieldname(insn, 0, 4) << 0; \
11733 tmp |= fieldname(insn, 5, 1) << 4; \
11734 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11735 tmp = fieldname(insn, 16, 5); \
11736 if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11740 tmp |= fieldname(insn, 12, 4) << 0; \
11741 tmp |= fieldname(insn, 22, 1) << 4; \
11742 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11744 tmp |= fieldname(insn, 0, 4) << 0; \
11745 tmp |= fieldname(insn, 5, 1) << 4; \
11746 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11747 tmp = fieldname(insn, 16, 3); \
11748 MCOperand_CreateImm0(MI, tmp); \
11752 tmp |= fieldname(insn, 12, 4) << 0; \
11753 tmp |= fieldname(insn, 22, 1) << 4; \
11754 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11756 tmp |= fieldname(insn, 12, 4) << 0; \
11757 tmp |= fieldname(insn, 22, 1) << 4; \
11758 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11760 tmp |= fieldname(insn, 0, 4) << 0; \
11761 tmp |= fieldname(insn, 5, 1) << 4; \
11762 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11763 tmp = fieldname(insn, 16, 3); \
11764 MCOperand_CreateImm0(MI, tmp); \
11768 tmp |= fieldname(insn, 12, 4) << 0; \
11769 tmp |= fieldname(insn, 22, 1) << 4; \
11770 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11772 tmp |= fieldname(insn, 0, 4) << 0; \
11773 tmp |= fieldname(insn, 5, 1) << 4; \
11774 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11775 tmp = fieldname(insn, 16, 4); \
11776 MCOperand_CreateImm0(MI, tmp); \
11780 tmp |= fieldname(insn, 12, 4) << 0; \
11781 tmp |= fieldname(insn, 22, 1) << 4; \
11782 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11784 tmp |= fieldname(insn, 12, 4) << 0; \
11785 tmp |= fieldname(insn, 22, 1) << 4; \
11786 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11788 tmp |= fieldname(insn, 0, 4) << 0; \
11789 tmp |= fieldname(insn, 5, 1) << 4; \
11790 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11791 tmp = fieldname(insn, 16, 4); \
11792 MCOperand_CreateImm0(MI, tmp); \
11796 tmp |= fieldname(insn, 12, 4) << 0; \
11797 tmp |= fieldname(insn, 22, 1) << 4; \
11798 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11800 tmp |= fieldname(insn, 0, 4) << 0; \
11801 tmp |= fieldname(insn, 5, 1) << 4; \
11802 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11803 tmp = fieldname(insn, 16, 5); \
11804 MCOperand_CreateImm0(MI, tmp); \
11808 tmp |= fieldname(insn, 12, 4) << 0; \
11809 tmp |= fieldname(insn, 22, 1) << 4; \
11810 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11812 tmp |= fieldname(insn, 12, 4) << 0; \
11813 tmp |= fieldname(insn, 22, 1) << 4; \
11814 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11816 tmp |= fieldname(insn, 0, 4) << 0; \
11817 tmp |= fieldname(insn, 5, 1) << 4; \
11818 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11819 tmp = fieldname(insn, 16, 5); \
11820 MCOperand_CreateImm0(MI, tmp); \
11824 tmp |= fieldname(insn, 12, 4) << 0; \
11825 tmp |= fieldname(insn, 22, 1) << 4; \
11826 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11828 tmp |= fieldname(insn, 0, 4) << 0; \
11829 tmp |= fieldname(insn, 5, 1) << 4; \
11830 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11831 tmp = fieldname(insn, 16, 3); \
11832 if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11836 tmp |= fieldname(insn, 12, 4) << 0; \
11837 tmp |= fieldname(insn, 22, 1) << 4; \
11838 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11840 tmp |= fieldname(insn, 0, 4) << 0; \
11841 tmp |= fieldname(insn, 5, 1) << 4; \
11842 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11843 tmp = fieldname(insn, 16, 4); \
11844 if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11848 tmp |= fieldname(insn, 12, 4) << 0; \
11849 tmp |= fieldname(insn, 22, 1) << 4; \
11850 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11852 tmp |= fieldname(insn, 0, 4) << 0; \
11853 tmp |= fieldname(insn, 5, 1) << 4; \
11854 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11855 tmp = fieldname(insn, 16, 5); \
11856 if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11860 tmp |= fieldname(insn, 12, 4) << 0; \
11861 tmp |= fieldname(insn, 22, 1) << 4; \
11862 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11864 tmp |= fieldname(insn, 0, 4) << 0; \
11865 tmp |= fieldname(insn, 5, 1) << 4; \
11866 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11867 tmp = fieldname(insn, 16, 3); \
11868 MCOperand_CreateImm0(MI, tmp); \
11872 tmp |= fieldname(insn, 12, 4) << 0; \
11873 tmp |= fieldname(insn, 22, 1) << 4; \
11874 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11876 tmp |= fieldname(insn, 0, 4) << 0; \
11877 tmp |= fieldname(insn, 5, 1) << 4; \
11878 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11879 tmp = fieldname(insn, 16, 4); \
11880 MCOperand_CreateImm0(MI, tmp); \
11884 tmp |= fieldname(insn, 12, 4) << 0; \
11885 tmp |= fieldname(insn, 22, 1) << 4; \
11886 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11888 tmp |= fieldname(insn, 0, 4) << 0; \
11889 tmp |= fieldname(insn, 5, 1) << 4; \
11890 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11891 tmp = fieldname(insn, 16, 5); \
11892 MCOperand_CreateImm0(MI, tmp); \
11895 if (!Check(&S, DecodeNEONModImmInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
11898 if (!Check(&S, DecodeVCVTD(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
11902 tmp |= fieldname(insn, 12, 4) << 0; \
11903 tmp |= fieldname(insn, 22, 1) << 4; \
11904 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11906 tmp |= fieldname(insn, 0, 4) << 0; \
11907 tmp |= fieldname(insn, 5, 1) << 4; \
11908 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11909 tmp = fieldname(insn, 16, 6); \
11910 if (!Check(&S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11914 tmp |= fieldname(insn, 12, 4) << 0; \
11915 tmp |= fieldname(insn, 22, 1) << 4; \
11916 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11918 tmp |= fieldname(insn, 12, 4) << 0; \
11919 tmp |= fieldname(insn, 22, 1) << 4; \
11920 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11922 tmp |= fieldname(insn, 0, 4) << 0; \
11923 tmp |= fieldname(insn, 5, 1) << 4; \
11924 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11925 tmp = fieldname(insn, 16, 6); \
11926 if (!Check(&S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11930 tmp |= fieldname(insn, 12, 4) << 0; \
11931 tmp |= fieldname(insn, 22, 1) << 4; \
11932 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11934 tmp |= fieldname(insn, 0, 4) << 0; \
11935 tmp |= fieldname(insn, 5, 1) << 4; \
11936 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11937 tmp = fieldname(insn, 16, 6); \
11938 MCOperand_CreateImm0(MI, tmp); \
11942 tmp |= fieldname(insn, 12, 4) << 0; \
11943 tmp |= fieldname(insn, 22, 1) << 4; \
11944 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11946 tmp |= fieldname(insn, 12, 4) << 0; \
11947 tmp |= fieldname(insn, 22, 1) << 4; \
11948 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11950 tmp |= fieldname(insn, 0, 4) << 0; \
11951 tmp |= fieldname(insn, 5, 1) << 4; \
11952 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11953 tmp = fieldname(insn, 16, 6); \
11954 MCOperand_CreateImm0(MI, tmp); \
11958 tmp |= fieldname(insn, 12, 4) << 0; \
11959 tmp |= fieldname(insn, 22, 1) << 4; \
11960 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11962 tmp |= fieldname(insn, 0, 4) << 0; \
11963 tmp |= fieldname(insn, 5, 1) << 4; \
11964 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11965 tmp = fieldname(insn, 16, 3); \
11966 if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11970 tmp |= fieldname(insn, 12, 4) << 0; \
11971 tmp |= fieldname(insn, 22, 1) << 4; \
11972 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11974 tmp |= fieldname(insn, 0, 4) << 0; \
11975 tmp |= fieldname(insn, 5, 1) << 4; \
11976 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11977 tmp = fieldname(insn, 16, 4); \
11978 if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11982 tmp |= fieldname(insn, 12, 4) << 0; \
11983 tmp |= fieldname(insn, 22, 1) << 4; \
11984 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11986 tmp |= fieldname(insn, 0, 4) << 0; \
11987 tmp |= fieldname(insn, 5, 1) << 4; \
11988 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11989 tmp = fieldname(insn, 16, 5); \
11990 if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11994 tmp |= fieldname(insn, 12, 4) << 0; \
11995 tmp |= fieldname(insn, 22, 1) << 4; \
11996 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
11998 tmp |= fieldname(insn, 12, 4) << 0; \
11999 tmp |= fieldname(insn, 22, 1) << 4; \
12000 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12002 tmp |= fieldname(insn, 0, 4) << 0; \
12003 tmp |= fieldname(insn, 5, 1) << 4; \
12004 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12005 tmp = fieldname(insn, 16, 3); \
12006 if (!Check(&S, DecodeShiftRight8Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12010 tmp |= fieldname(insn, 12, 4) << 0; \
12011 tmp |= fieldname(insn, 22, 1) << 4; \
12012 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12014 tmp |= fieldname(insn, 12, 4) << 0; \
12015 tmp |= fieldname(insn, 22, 1) << 4; \
12016 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12018 tmp |= fieldname(insn, 0, 4) << 0; \
12019 tmp |= fieldname(insn, 5, 1) << 4; \
12020 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12021 tmp = fieldname(insn, 16, 4); \
12022 if (!Check(&S, DecodeShiftRight16Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12026 tmp |= fieldname(insn, 12, 4) << 0; \
12027 tmp |= fieldname(insn, 22, 1) << 4; \
12028 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12030 tmp |= fieldname(insn, 12, 4) << 0; \
12031 tmp |= fieldname(insn, 22, 1) << 4; \
12032 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12034 tmp |= fieldname(insn, 0, 4) << 0; \
12035 tmp |= fieldname(insn, 5, 1) << 4; \
12036 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12037 tmp = fieldname(insn, 16, 5); \
12038 if (!Check(&S, DecodeShiftRight32Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12042 tmp |= fieldname(insn, 12, 4) << 0; \
12043 tmp |= fieldname(insn, 22, 1) << 4; \
12044 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12046 tmp |= fieldname(insn, 0, 4) << 0; \
12047 tmp |= fieldname(insn, 5, 1) << 4; \
12048 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12049 tmp = fieldname(insn, 16, 3); \
12050 MCOperand_CreateImm0(MI, tmp); \
12054 tmp |= fieldname(insn, 12, 4) << 0; \
12055 tmp |= fieldname(insn, 22, 1) << 4; \
12056 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12058 tmp |= fieldname(insn, 12, 4) << 0; \
12059 tmp |= fieldname(insn, 22, 1) << 4; \
12060 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12062 tmp |= fieldname(insn, 0, 4) << 0; \
12063 tmp |= fieldname(insn, 5, 1) << 4; \
12064 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12065 tmp = fieldname(insn, 16, 3); \
12066 MCOperand_CreateImm0(MI, tmp); \
12070 tmp |= fieldname(insn, 12, 4) << 0; \
12071 tmp |= fieldname(insn, 22, 1) << 4; \
12072 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12074 tmp |= fieldname(insn, 0, 4) << 0; \
12075 tmp |= fieldname(insn, 5, 1) << 4; \
12076 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12077 tmp = fieldname(insn, 16, 4); \
12078 MCOperand_CreateImm0(MI, tmp); \
12082 tmp |= fieldname(insn, 12, 4) << 0; \
12083 tmp |= fieldname(insn, 22, 1) << 4; \
12084 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12086 tmp |= fieldname(insn, 12, 4) << 0; \
12087 tmp |= fieldname(insn, 22, 1) << 4; \
12088 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12090 tmp |= fieldname(insn, 0, 4) << 0; \
12091 tmp |= fieldname(insn, 5, 1) << 4; \
12092 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12093 tmp = fieldname(insn, 16, 4); \
12094 MCOperand_CreateImm0(MI, tmp); \
12098 tmp |= fieldname(insn, 12, 4) << 0; \
12099 tmp |= fieldname(insn, 22, 1) << 4; \
12100 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12102 tmp |= fieldname(insn, 0, 4) << 0; \
12103 tmp |= fieldname(insn, 5, 1) << 4; \
12104 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12105 tmp = fieldname(insn, 16, 5); \
12106 MCOperand_CreateImm0(MI, tmp); \
12110 tmp |= fieldname(insn, 12, 4) << 0; \
12111 tmp |= fieldname(insn, 22, 1) << 4; \
12112 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12114 tmp |= fieldname(insn, 12, 4) << 0; \
12115 tmp |= fieldname(insn, 22, 1) << 4; \
12116 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12118 tmp |= fieldname(insn, 0, 4) << 0; \
12119 tmp |= fieldname(insn, 5, 1) << 4; \
12120 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12121 tmp = fieldname(insn, 16, 5); \
12122 MCOperand_CreateImm0(MI, tmp); \
12125 if (!Check(&S, DecodeVCVTQ(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
12129 tmp |= fieldname(insn, 12, 4) << 0; \
12130 tmp |= fieldname(insn, 22, 1) << 4; \
12131 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12133 tmp |= fieldname(insn, 0, 4) << 0; \
12134 tmp |= fieldname(insn, 5, 1) << 4; \
12135 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12136 tmp = fieldname(insn, 16, 6); \
12137 if (!Check(&S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12141 tmp |= fieldname(insn, 12, 4) << 0; \
12142 tmp |= fieldname(insn, 22, 1) << 4; \
12143 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12145 tmp |= fieldname(insn, 12, 4) << 0; \
12146 tmp |= fieldname(insn, 22, 1) << 4; \
12147 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12149 tmp |= fieldname(insn, 0, 4) << 0; \
12150 tmp |= fieldname(insn, 5, 1) << 4; \
12151 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12152 tmp = fieldname(insn, 16, 6); \
12153 if (!Check(&S, DecodeShiftRight64Imm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12157 tmp |= fieldname(insn, 12, 4) << 0; \
12158 tmp |= fieldname(insn, 22, 1) << 4; \
12159 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12161 tmp |= fieldname(insn, 0, 4) << 0; \
12162 tmp |= fieldname(insn, 5, 1) << 4; \
12163 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12164 tmp = fieldname(insn, 16, 6); \
12165 MCOperand_CreateImm0(MI, tmp); \
12169 tmp |= fieldname(insn, 12, 4) << 0; \
12170 tmp |= fieldname(insn, 22, 1) << 4; \
12171 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12173 tmp |= fieldname(insn, 12, 4) << 0; \
12174 tmp |= fieldname(insn, 22, 1) << 4; \
12175 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12177 tmp |= fieldname(insn, 0, 4) << 0; \
12178 tmp |= fieldname(insn, 5, 1) << 4; \
12179 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12180 tmp = fieldname(insn, 16, 6); \
12181 MCOperand_CreateImm0(MI, tmp); \
12185 tmp |= fieldname(insn, 7, 1) << 4; \
12186 tmp |= fieldname(insn, 16, 4) << 0; \
12187 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12189 tmp |= fieldname(insn, 7, 1) << 4; \
12190 tmp |= fieldname(insn, 16, 4) << 0; \
12191 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12192 tmp = fieldname(insn, 12, 4); \
12193 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12194 tmp = fieldname(insn, 21, 1); \
12195 MCOperand_CreateImm0(MI, tmp); \
12196 tmp = fieldname(insn, 28, 4); \
12197 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12200 tmp = fieldname(insn, 12, 4); \
12201 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12203 tmp |= fieldname(insn, 7, 1) << 4; \
12204 tmp |= fieldname(insn, 16, 4) << 0; \
12205 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12206 tmp = fieldname(insn, 21, 1); \
12207 MCOperand_CreateImm0(MI, tmp); \
12208 tmp = fieldname(insn, 28, 4); \
12209 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12213 tmp |= fieldname(insn, 7, 1) << 4; \
12214 tmp |= fieldname(insn, 16, 4) << 0; \
12215 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12217 tmp |= fieldname(insn, 7, 1) << 4; \
12218 tmp |= fieldname(insn, 16, 4) << 0; \
12219 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12220 tmp = fieldname(insn, 12, 4); \
12221 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12223 tmp |= fieldname(insn, 6, 1) << 0; \
12224 tmp |= fieldname(insn, 21, 1) << 1; \
12225 MCOperand_CreateImm0(MI, tmp); \
12226 tmp = fieldname(insn, 28, 4); \
12227 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12230 tmp = fieldname(insn, 12, 4); \
12231 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12233 tmp |= fieldname(insn, 7, 1) << 4; \
12234 tmp |= fieldname(insn, 16, 4) << 0; \
12235 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12237 tmp |= fieldname(insn, 6, 1) << 0; \
12238 tmp |= fieldname(insn, 21, 1) << 1; \
12239 MCOperand_CreateImm0(MI, tmp); \
12240 tmp = fieldname(insn, 28, 4); \
12241 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12245 tmp |= fieldname(insn, 7, 1) << 4; \
12246 tmp |= fieldname(insn, 16, 4) << 0; \
12247 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12249 tmp |= fieldname(insn, 7, 1) << 4; \
12250 tmp |= fieldname(insn, 16, 4) << 0; \
12251 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12252 tmp = fieldname(insn, 12, 4); \
12253 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12255 tmp |= fieldname(insn, 5, 2) << 0; \
12256 tmp |= fieldname(insn, 21, 1) << 2; \
12257 MCOperand_CreateImm0(MI, tmp); \
12258 tmp = fieldname(insn, 28, 4); \
12259 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12262 tmp = fieldname(insn, 12, 4); \
12263 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12265 tmp |= fieldname(insn, 7, 1) << 4; \
12266 tmp |= fieldname(insn, 16, 4) << 0; \
12267 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12269 tmp |= fieldname(insn, 5, 2) << 0; \
12270 tmp |= fieldname(insn, 21, 1) << 2; \
12271 MCOperand_CreateImm0(MI, tmp); \
12272 tmp = fieldname(insn, 28, 4); \
12273 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12277 tmp |= fieldname(insn, 7, 1) << 4; \
12278 tmp |= fieldname(insn, 16, 4) << 0; \
12279 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12280 tmp = fieldname(insn, 12, 4); \
12281 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12282 tmp = fieldname(insn, 28, 4); \
12283 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12287 tmp |= fieldname(insn, 7, 1) << 4; \
12288 tmp |= fieldname(insn, 16, 4) << 0; \
12289 if (!Check(&S, DecodeQPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12290 tmp = fieldname(insn, 12, 4); \
12291 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12292 tmp = fieldname(insn, 28, 4); \
12293 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12296 if (!Check(&S, DecodeVLDST4Instruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
12299 if (!Check(&S, DecodeVST1LN(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
12302 if (!Check(&S, DecodeVLD1LN(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
12305 if (!Check(&S, DecodeVST2LN(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
12308 if (!Check(&S, DecodeVLD2LN(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
12311 if (!Check(&S, DecodeVLDST1Instruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
12314 if (!Check(&S, DecodeVST3LN(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
12317 if (!Check(&S, DecodeVLD3LN(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
12320 if (!Check(&S, DecodeVLDST2Instruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
12323 if (!Check(&S, DecodeVST4LN(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
12326 if (!Check(&S, DecodeVLD4LN(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
12329 if (!Check(&S, DecodeVLDST3Instruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
12332 if (!Check(&S, DecodeVLD1DupInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
12335 if (!Check(&S, DecodeVLD2DupInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
12338 if (!Check(&S, DecodeVLD3DupInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
12341 if (!Check(&S, DecodeVLD4DupInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
12344 tmp = fieldname(insn, 0, 3); \
12345 if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12346 tmp = fieldname(insn, 3, 3); \
12347 if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12350 tmp = fieldname(insn, 8, 3); \
12351 if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12352 tmp = fieldname(insn, 0, 8); \
12353 MCOperand_CreateImm0(MI, tmp); \
12356 if (!Check(&S, DecodeThumbAddSPReg(MI, (uint16_t)insn, Address, Decoder))) return MCDisassembler_Fail; \
12360 tmp |= fieldname(insn, 0, 3) << 0; \
12361 tmp |= fieldname(insn, 7, 1) << 3; \
12362 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12364 tmp |= fieldname(insn, 0, 3) << 0; \
12365 tmp |= fieldname(insn, 7, 1) << 3; \
12366 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12367 tmp = fieldname(insn, 3, 4); \
12368 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12372 tmp |= fieldname(insn, 0, 3) << 0; \
12373 tmp |= fieldname(insn, 7, 1) << 3; \
12374 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12375 tmp = fieldname(insn, 3, 4); \
12376 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12379 tmp = fieldname(insn, 3, 4); \
12380 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12383 tmp = fieldname(insn, 8, 3); \
12384 if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12385 tmp = fieldname(insn, 0, 8); \
12386 if (!Check(&S, DecodeThumbAddrModePC(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12389 tmp = fieldname(insn, 0, 3); \
12390 if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12391 tmp = fieldname(insn, 3, 6); \
12392 if (!Check(&S, DecodeThumbAddrModeRR(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12395 tmp = fieldname(insn, 0, 3); \
12396 if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12397 tmp = fieldname(insn, 3, 8); \
12398 if (!Check(&S, DecodeThumbAddrModeIS(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12401 tmp = fieldname(insn, 8, 3); \
12402 if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12403 tmp = fieldname(insn, 0, 8); \
12404 if (!Check(&S, DecodeThumbAddrModeSP(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12407 if (!Check(&S, DecodeThumbAddSpecialReg(MI, (uint16_t)insn, Address, Decoder))) return MCDisassembler_Fail; \
12410 if (!Check(&S, DecodeThumbAddSPImm(MI, (uint16_t)insn, Address, Decoder))) return MCDisassembler_Fail; \
12413 tmp = fieldname(insn, 0, 3); \
12414 if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12416 tmp |= fieldname(insn, 3, 5) << 0; \
12417 tmp |= fieldname(insn, 9, 1) << 5; \
12418 if (!Check(&S, DecodeThumbCmpBROperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12422 tmp |= fieldname(insn, 0, 8) << 0; \
12423 tmp |= fieldname(insn, 8, 1) << 14; \
12424 if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12427 tmp = fieldname(insn, 3, 1); \
12428 MCOperand_CreateImm0(MI, tmp); \
12431 if (!Check(&S, DecodeThumbCPS(MI, (uint16_t)insn, Address, Decoder))) return MCDisassembler_Fail; \
12434 tmp = fieldname(insn, 0, 6); \
12435 MCOperand_CreateImm0(MI, tmp); \
12439 tmp |= fieldname(insn, 0, 8) << 0; \
12440 tmp |= fieldname(insn, 8, 1) << 15; \
12441 if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12444 tmp = fieldname(insn, 0, 8); \
12445 MCOperand_CreateImm0(MI, tmp); \
12448 tmp = fieldname(insn, 4, 4); \
12449 MCOperand_CreateImm0(MI, tmp); \
12452 tmp = fieldname(insn, 8, 3); \
12453 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12454 tmp = fieldname(insn, 8, 3); \
12455 if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12456 tmp = fieldname(insn, 0, 8); \
12457 if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12460 tmp = fieldname(insn, 8, 3); \
12461 if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12462 tmp = fieldname(insn, 0, 8); \
12463 if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12466 tmp = fieldname(insn, 0, 8); \
12467 if (!Check(&S, DecodeThumbBCCTargetOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12468 tmp = fieldname(insn, 8, 4); \
12469 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12472 tmp = fieldname(insn, 0, 11); \
12473 if (!Check(&S, DecodeThumbBROperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12477 tmp |= fieldname(insn, 1, 10) << 1; \
12478 tmp |= fieldname(insn, 11, 1) << 21; \
12479 tmp |= fieldname(insn, 13, 1) << 22; \
12480 tmp |= fieldname(insn, 16, 10) << 11; \
12481 tmp |= fieldname(insn, 26, 1) << 23; \
12482 if (!Check(&S, DecodeThumbBLXOffset(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12486 tmp |= fieldname(insn, 0, 11) << 0; \
12487 tmp |= fieldname(insn, 11, 1) << 21; \
12488 tmp |= fieldname(insn, 13, 1) << 22; \
12489 tmp |= fieldname(insn, 16, 10) << 11; \
12490 tmp |= fieldname(insn, 26, 1) << 23; \
12491 if (!Check(&S, DecodeThumbBLTargetOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12494 if (!Check(&S, DecodeIT(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
12497 tmp = fieldname(insn, 16, 4); \
12498 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12500 tmp |= fieldname(insn, 0, 13) << 0; \
12501 tmp |= fieldname(insn, 14, 1) << 14; \
12502 if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12505 tmp = fieldname(insn, 16, 4); \
12506 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12507 tmp = fieldname(insn, 0, 16); \
12508 if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12511 tmp = fieldname(insn, 16, 4); \
12512 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12513 tmp = fieldname(insn, 16, 4); \
12514 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12516 tmp |= fieldname(insn, 0, 13) << 0; \
12517 tmp |= fieldname(insn, 14, 1) << 14; \
12518 if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12521 tmp = fieldname(insn, 16, 4); \
12522 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12523 tmp = fieldname(insn, 16, 4); \
12524 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12525 tmp = fieldname(insn, 0, 16); \
12526 if (!Check(&S, DecodeRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12529 tmp = fieldname(insn, 8, 4); \
12530 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12531 tmp = fieldname(insn, 12, 4); \
12532 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12534 tmp |= fieldname(insn, 0, 8) << 0; \
12535 tmp |= fieldname(insn, 16, 4) << 8; \
12536 if (!Check(&S, DecodeT2AddrModeImm0_1020s4(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12539 tmp = fieldname(insn, 0, 4); \
12540 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12541 tmp = fieldname(insn, 12, 4); \
12542 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12543 tmp = fieldname(insn, 16, 4); \
12544 if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12547 tmp = fieldname(insn, 0, 4); \
12548 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12549 tmp = fieldname(insn, 12, 4); \
12550 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12551 tmp = fieldname(insn, 8, 4); \
12552 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12553 tmp = fieldname(insn, 16, 4); \
12554 if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12557 tmp = fieldname(insn, 12, 4); \
12558 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12559 tmp = fieldname(insn, 16, 4); \
12560 if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12563 tmp = fieldname(insn, 12, 4); \
12564 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12566 tmp |= fieldname(insn, 0, 8) << 0; \
12567 tmp |= fieldname(insn, 16, 4) << 8; \
12568 if (!Check(&S, DecodeT2AddrModeImm0_1020s4(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12571 if (!Check(&S, DecodeThumbTableBranch(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
12574 tmp = fieldname(insn, 12, 4); \
12575 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12576 tmp = fieldname(insn, 8, 4); \
12577 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12578 tmp = fieldname(insn, 16, 4); \
12579 if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12582 tmp = fieldname(insn, 16, 4); \
12583 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12584 tmp = fieldname(insn, 12, 4); \
12585 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12586 tmp = fieldname(insn, 8, 4); \
12587 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12588 tmp = fieldname(insn, 16, 4); \
12589 if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12591 tmp |= fieldname(insn, 0, 8) << 0; \
12592 tmp |= fieldname(insn, 23, 1) << 8; \
12593 if (!Check(&S, DecodeT2Imm8S4(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12596 tmp = fieldname(insn, 12, 4); \
12597 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12598 tmp = fieldname(insn, 8, 4); \
12599 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12600 tmp = fieldname(insn, 16, 4); \
12601 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12602 tmp = fieldname(insn, 16, 4); \
12603 if (!Check(&S, DecodeAddrMode7Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12605 tmp |= fieldname(insn, 0, 8) << 0; \
12606 tmp |= fieldname(insn, 23, 1) << 8; \
12607 if (!Check(&S, DecodeT2Imm8S4(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12610 tmp = fieldname(insn, 12, 4); \
12611 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12612 tmp = fieldname(insn, 8, 4); \
12613 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12615 tmp |= fieldname(insn, 0, 8) << 0; \
12616 tmp |= fieldname(insn, 16, 4) << 9; \
12617 tmp |= fieldname(insn, 23, 1) << 8; \
12618 if (!Check(&S, DecodeT2AddrModeImm8s4(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12621 if (!Check(&S, DecodeT2STRDPreInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
12624 if (!Check(&S, DecodeT2LDRDPreInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
12627 tmp = fieldname(insn, 16, 4); \
12628 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12629 tmp = fieldname(insn, 0, 4); \
12630 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12633 tmp = fieldname(insn, 16, 4); \
12634 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12636 tmp |= fieldname(insn, 0, 4) << 0; \
12637 tmp |= fieldname(insn, 4, 4) << 5; \
12638 tmp |= fieldname(insn, 12, 3) << 9; \
12639 if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12642 tmp = fieldname(insn, 8, 4); \
12643 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12644 tmp = fieldname(insn, 16, 4); \
12645 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12646 tmp = fieldname(insn, 0, 4); \
12647 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12648 tmp = fieldname(insn, 20, 1); \
12649 if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12652 tmp = fieldname(insn, 8, 4); \
12653 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12654 tmp = fieldname(insn, 16, 4); \
12655 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12657 tmp |= fieldname(insn, 0, 4) << 0; \
12658 tmp |= fieldname(insn, 4, 4) << 5; \
12659 tmp |= fieldname(insn, 12, 3) << 9; \
12660 if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12661 tmp = fieldname(insn, 20, 1); \
12662 if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12665 tmp = fieldname(insn, 8, 4); \
12666 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12667 tmp = fieldname(insn, 0, 4); \
12668 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12669 tmp = fieldname(insn, 20, 1); \
12670 if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12673 tmp = fieldname(insn, 8, 4); \
12674 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12675 tmp = fieldname(insn, 0, 4); \
12676 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12677 tmp = fieldname(insn, 20, 1); \
12678 if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12681 tmp = fieldname(insn, 8, 4); \
12682 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12683 tmp = fieldname(insn, 0, 4); \
12684 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12686 tmp |= fieldname(insn, 6, 2) << 0; \
12687 tmp |= fieldname(insn, 12, 3) << 2; \
12688 MCOperand_CreateImm0(MI, tmp); \
12689 tmp = fieldname(insn, 20, 1); \
12690 if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12693 tmp = fieldname(insn, 8, 4); \
12694 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12696 tmp |= fieldname(insn, 0, 4) << 0; \
12697 tmp |= fieldname(insn, 4, 4) << 5; \
12698 tmp |= fieldname(insn, 12, 3) << 9; \
12699 if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12700 tmp = fieldname(insn, 20, 1); \
12701 if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12704 tmp = fieldname(insn, 8, 4); \
12705 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12706 tmp = fieldname(insn, 16, 4); \
12707 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12708 tmp = fieldname(insn, 0, 4); \
12709 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12711 tmp |= fieldname(insn, 6, 2) << 0; \
12712 tmp |= fieldname(insn, 12, 3) << 2; \
12713 MCOperand_CreateImm0(MI, tmp); \
12716 tmp = fieldname(insn, 8, 4); \
12717 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12718 tmp = fieldname(insn, 16, 4); \
12719 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12720 tmp = fieldname(insn, 0, 4); \
12721 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12722 tmp = fieldname(insn, 20, 1); \
12723 if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12726 tmp = fieldname(insn, 8, 4); \
12727 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12728 tmp = fieldname(insn, 16, 4); \
12729 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12731 tmp |= fieldname(insn, 0, 4) << 0; \
12732 tmp |= fieldname(insn, 4, 4) << 5; \
12733 tmp |= fieldname(insn, 12, 3) << 9; \
12734 if (!Check(&S, DecodeSORegImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12735 tmp = fieldname(insn, 20, 1); \
12736 if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12739 tmp = fieldname(insn, 8, 4); \
12740 if (!Check(&S, DecodeCoprocessor(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12741 tmp = fieldname(insn, 4, 4); \
12742 MCOperand_CreateImm0(MI, tmp); \
12743 tmp = fieldname(insn, 12, 4); \
12744 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12745 tmp = fieldname(insn, 16, 4); \
12746 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12747 tmp = fieldname(insn, 0, 4); \
12748 MCOperand_CreateImm0(MI, tmp); \
12751 tmp = fieldname(insn, 16, 4); \
12752 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12754 tmp |= fieldname(insn, 0, 8) << 0; \
12755 tmp |= fieldname(insn, 12, 3) << 8; \
12756 tmp |= fieldname(insn, 26, 1) << 11; \
12757 if (!Check(&S, DecodeT2SOImm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12760 tmp = fieldname(insn, 8, 4); \
12761 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12762 tmp = fieldname(insn, 16, 4); \
12763 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12765 tmp |= fieldname(insn, 0, 8) << 0; \
12766 tmp |= fieldname(insn, 12, 3) << 8; \
12767 tmp |= fieldname(insn, 26, 1) << 11; \
12768 if (!Check(&S, DecodeT2SOImm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12769 tmp = fieldname(insn, 20, 1); \
12770 if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12773 tmp = fieldname(insn, 8, 4); \
12774 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12776 tmp |= fieldname(insn, 0, 8) << 0; \
12777 tmp |= fieldname(insn, 12, 3) << 8; \
12778 tmp |= fieldname(insn, 26, 1) << 11; \
12779 if (!Check(&S, DecodeT2SOImm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12780 tmp = fieldname(insn, 20, 1); \
12781 if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12784 tmp = fieldname(insn, 8, 4); \
12785 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12786 tmp = fieldname(insn, 16, 4); \
12787 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12789 tmp |= fieldname(insn, 0, 8) << 0; \
12790 tmp |= fieldname(insn, 12, 3) << 8; \
12791 tmp |= fieldname(insn, 26, 1) << 11; \
12792 if (!Check(&S, DecodeT2SOImm(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12793 tmp = fieldname(insn, 20, 1); \
12794 if (!Check(&S, DecodeCCOutOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12797 tmp = fieldname(insn, 8, 4); \
12798 if (!Check(&S, DecodeGPRnopcRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12799 tmp = fieldname(insn, 16, 4); \
12800 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12802 tmp |= fieldname(insn, 0, 8) << 0; \
12803 tmp |= fieldname(insn, 12, 3) << 8; \
12804 tmp |= fieldname(insn, 26, 1) << 11; \
12805 MCOperand_CreateImm0(MI, tmp); \
12808 if (!Check(&S, DecodeT2Adr(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
12811 if (!Check(&S, DecodeT2MOVTWInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
12814 tmp = fieldname(insn, 8, 4); \
12815 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12816 tmp = fieldname(insn, 0, 4); \
12817 MCOperand_CreateImm0(MI, tmp); \
12818 tmp = fieldname(insn, 16, 4); \
12819 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12822 tmp = fieldname(insn, 8, 4); \
12823 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12824 tmp = fieldname(insn, 0, 5); \
12825 MCOperand_CreateImm0(MI, tmp); \
12826 tmp = fieldname(insn, 16, 4); \
12827 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12829 tmp |= fieldname(insn, 6, 2) << 0; \
12830 tmp |= fieldname(insn, 12, 3) << 2; \
12831 tmp |= fieldname(insn, 21, 1) << 5; \
12832 if (!Check(&S, DecodeT2ShifterImmOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12835 tmp = fieldname(insn, 8, 4); \
12836 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12837 tmp = fieldname(insn, 16, 4); \
12838 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12840 tmp |= fieldname(insn, 6, 2) << 0; \
12841 tmp |= fieldname(insn, 12, 3) << 2; \
12842 MCOperand_CreateImm0(MI, tmp); \
12843 tmp = fieldname(insn, 0, 5); \
12844 MCOperand_CreateImm0(MI, tmp); \
12847 tmp = fieldname(insn, 8, 4); \
12848 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12849 tmp = fieldname(insn, 8, 4); \
12850 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12852 tmp |= fieldname(insn, 0, 5) << 5; \
12853 tmp |= fieldname(insn, 6, 2) << 0; \
12854 tmp |= fieldname(insn, 12, 3) << 2; \
12855 if (!Check(&S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12858 tmp = fieldname(insn, 8, 4); \
12859 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12860 tmp = fieldname(insn, 8, 4); \
12861 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12862 tmp = fieldname(insn, 16, 4); \
12863 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12865 tmp |= fieldname(insn, 0, 5) << 5; \
12866 tmp |= fieldname(insn, 6, 2) << 0; \
12867 tmp |= fieldname(insn, 12, 3) << 2; \
12868 if (!Check(&S, DecodeBitfieldMaskOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12871 tmp = fieldname(insn, 0, 4); \
12872 MCOperand_CreateImm0(MI, tmp); \
12875 if (!Check(&S, DecodeT2CPSInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
12878 tmp = fieldname(insn, 8, 4); \
12879 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12882 tmp = fieldname(insn, 16, 4); \
12883 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12887 tmp |= fieldname(insn, 0, 12) << 0; \
12888 tmp |= fieldname(insn, 16, 4) << 12; \
12889 MCOperand_CreateImm0(MI, tmp); \
12892 tmp = fieldname(insn, 16, 4); \
12893 MCOperand_CreateImm0(MI, tmp); \
12897 tmp |= fieldname(insn, 8, 4) << 0; \
12898 tmp |= fieldname(insn, 20, 1) << 4; \
12899 if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12900 tmp = fieldname(insn, 16, 4); \
12901 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12905 tmp |= fieldname(insn, 4, 1) << 4; \
12906 tmp |= fieldname(insn, 8, 4) << 0; \
12907 tmp |= fieldname(insn, 20, 1) << 5; \
12908 if (!Check(&S, DecodeBankedReg(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12909 tmp = fieldname(insn, 16, 4); \
12910 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12914 tmp |= fieldname(insn, 0, 8) << 0; \
12915 tmp |= fieldname(insn, 10, 2) << 10; \
12916 if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12917 tmp = fieldname(insn, 16, 4); \
12918 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12921 tmp = fieldname(insn, 8, 4); \
12922 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12924 tmp |= fieldname(insn, 4, 1) << 4; \
12925 tmp |= fieldname(insn, 16, 4) << 0; \
12926 tmp |= fieldname(insn, 20, 1) << 5; \
12927 if (!Check(&S, DecodeBankedReg(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12930 tmp = fieldname(insn, 8, 4); \
12931 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12932 tmp = fieldname(insn, 0, 8); \
12933 if (!Check(&S, DecodeMSRMask(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12936 if (!Check(&S, DecodeThumb2BCCInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
12939 if (!Check(&S, DecodeT2BInstruction(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
12942 tmp = fieldname(insn, 12, 4); \
12943 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12945 tmp |= fieldname(insn, 0, 4) << 2; \
12946 tmp |= fieldname(insn, 4, 2) << 0; \
12947 tmp |= fieldname(insn, 16, 4) << 6; \
12948 if (!Check(&S, DecodeT2AddrModeSOReg(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12951 if (!Check(&S, DecodeT2LdStPre(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
12954 tmp = fieldname(insn, 12, 4); \
12955 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12957 tmp |= fieldname(insn, 0, 8) << 0; \
12958 tmp |= fieldname(insn, 16, 4) << 9; \
12959 if (!Check(&S, DecodeT2AddrModeImm8(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12962 tmp = fieldname(insn, 12, 4); \
12963 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12965 tmp |= fieldname(insn, 0, 8) << 0; \
12966 tmp |= fieldname(insn, 9, 1) << 8; \
12967 tmp |= fieldname(insn, 16, 4) << 9; \
12968 if (!Check(&S, DecodeT2AddrModeImm8(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12971 tmp = fieldname(insn, 12, 4); \
12972 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12974 tmp |= fieldname(insn, 0, 12) << 0; \
12975 tmp |= fieldname(insn, 16, 4) << 13; \
12976 if (!Check(&S, DecodeT2AddrModeImm12(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12979 if (!Check(&S, DecodeT2LoadShift(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
12982 if (!Check(&S, DecodeT2LoadImm8(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
12985 if (!Check(&S, DecodeT2LoadT(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
12988 if (!Check(&S, DecodeT2LoadImm12(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
12991 if (!Check(&S, DecodeT2LoadLabel(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
12994 tmp = fieldname(insn, 12, 4); \
12995 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
12997 tmp |= fieldname(insn, 0, 4) << 2; \
12998 tmp |= fieldname(insn, 4, 2) << 0; \
12999 tmp |= fieldname(insn, 16, 4) << 6; \
13000 if (!Check(&S, DecodeT2AddrModeSOReg(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13003 tmp = fieldname(insn, 12, 4); \
13004 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13006 tmp |= fieldname(insn, 0, 8) << 0; \
13007 tmp |= fieldname(insn, 9, 1) << 8; \
13008 tmp |= fieldname(insn, 16, 4) << 9; \
13009 if (!Check(&S, DecodeT2AddrModeImm8(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13012 tmp = fieldname(insn, 12, 4); \
13013 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13015 tmp |= fieldname(insn, 0, 12) << 0; \
13016 tmp |= fieldname(insn, 16, 4) << 13; \
13017 if (!Check(&S, DecodeT2AddrModeImm12(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13020 tmp = fieldname(insn, 8, 4); \
13021 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13022 tmp = fieldname(insn, 0, 4); \
13023 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13024 tmp = fieldname(insn, 4, 2); \
13025 MCOperand_CreateImm0(MI, tmp); \
13028 tmp = fieldname(insn, 8, 4); \
13029 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13030 tmp = fieldname(insn, 16, 4); \
13031 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13032 tmp = fieldname(insn, 0, 4); \
13033 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13034 tmp = fieldname(insn, 4, 2); \
13035 MCOperand_CreateImm0(MI, tmp); \
13038 tmp = fieldname(insn, 8, 4); \
13039 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13040 tmp = fieldname(insn, 16, 4); \
13041 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13042 tmp = fieldname(insn, 0, 4); \
13043 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13046 tmp = fieldname(insn, 8, 4); \
13047 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13048 tmp = fieldname(insn, 0, 4); \
13049 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13050 tmp = fieldname(insn, 16, 4); \
13051 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13054 tmp = fieldname(insn, 8, 4); \
13055 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13057 tmp |= fieldname(insn, 0, 4) << 0; \
13058 tmp |= fieldname(insn, 16, 4) << 0; \
13059 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13062 tmp = fieldname(insn, 8, 4); \
13063 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13064 tmp = fieldname(insn, 16, 4); \
13065 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13066 tmp = fieldname(insn, 0, 4); \
13067 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13070 tmp = fieldname(insn, 8, 4); \
13071 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13072 tmp = fieldname(insn, 16, 4); \
13073 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13074 tmp = fieldname(insn, 0, 4); \
13075 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13076 tmp = fieldname(insn, 12, 4); \
13077 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13080 tmp = fieldname(insn, 12, 4); \
13081 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13082 tmp = fieldname(insn, 8, 4); \
13083 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13084 tmp = fieldname(insn, 16, 4); \
13085 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13086 tmp = fieldname(insn, 0, 4); \
13087 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13090 tmp = fieldname(insn, 12, 4); \
13091 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13092 tmp = fieldname(insn, 8, 4); \
13093 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13094 tmp = fieldname(insn, 16, 4); \
13095 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13096 tmp = fieldname(insn, 0, 4); \
13097 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13098 tmp = fieldname(insn, 12, 4); \
13099 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13100 tmp = fieldname(insn, 8, 4); \
13101 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13104 tmp = fieldname(insn, 12, 4); \
13105 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13106 tmp = fieldname(insn, 8, 4); \
13107 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13108 tmp = fieldname(insn, 0, 4); \
13109 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13110 tmp = fieldname(insn, 16, 4); \
13111 if (!Check(&S, DecoderGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13114 tmp = fieldname(insn, 0, 3); \
13115 if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13116 tmp = fieldname(insn, 3, 3); \
13117 if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13118 tmp = fieldname(insn, 6, 5); \
13119 MCOperand_CreateImm0(MI, tmp); \
13122 tmp = fieldname(insn, 0, 3); \
13123 if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13124 tmp = fieldname(insn, 3, 3); \
13125 if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13126 tmp = fieldname(insn, 6, 3); \
13127 if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13130 tmp = fieldname(insn, 0, 3); \
13131 if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13132 tmp = fieldname(insn, 3, 3); \
13133 if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13134 tmp = fieldname(insn, 6, 3); \
13135 MCOperand_CreateImm0(MI, tmp); \
13138 tmp = fieldname(insn, 8, 3); \
13139 if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13140 tmp = fieldname(insn, 8, 3); \
13141 if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13142 tmp = fieldname(insn, 0, 8); \
13143 MCOperand_CreateImm0(MI, tmp); \
13146 tmp = fieldname(insn, 0, 3); \
13147 if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13148 tmp = fieldname(insn, 0, 3); \
13149 if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13150 tmp = fieldname(insn, 3, 3); \
13151 if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13154 tmp = fieldname(insn, 0, 3); \
13155 if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13156 tmp = fieldname(insn, 3, 3); \
13157 if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13158 tmp = fieldname(insn, 0, 3); \
13159 if (!Check(&S, DecodetGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13162 if (!Check(&S, DecodeVMOVSRR(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
13165 tmp = fieldname(insn, 16, 4); \
13166 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13167 tmp = fieldname(insn, 28, 4); \
13168 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13170 tmp |= fieldname(insn, 0, 8) << 0; \
13171 tmp |= fieldname(insn, 12, 4) << 9; \
13172 tmp |= fieldname(insn, 22, 1) << 8; \
13173 if (!Check(&S, DecodeSPRRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13177 tmp |= fieldname(insn, 0, 4) << 0; \
13178 tmp |= fieldname(insn, 5, 1) << 4; \
13179 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13180 tmp = fieldname(insn, 12, 4); \
13181 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13182 tmp = fieldname(insn, 16, 4); \
13183 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13184 tmp = fieldname(insn, 28, 4); \
13185 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13188 tmp = fieldname(insn, 16, 4); \
13189 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13190 tmp = fieldname(insn, 28, 4); \
13191 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13193 tmp |= fieldname(insn, 1, 7) << 1; \
13194 tmp |= fieldname(insn, 12, 4) << 8; \
13195 tmp |= fieldname(insn, 22, 1) << 12; \
13196 if (!Check(&S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13199 tmp = fieldname(insn, 16, 4); \
13200 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13201 tmp = fieldname(insn, 28, 4); \
13202 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13204 tmp |= fieldname(insn, 1, 7) << 1; \
13205 tmp |= fieldname(insn, 12, 4) << 8; \
13206 if (!Check(&S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13210 tmp |= fieldname(insn, 12, 4) << 1; \
13211 tmp |= fieldname(insn, 22, 1) << 0; \
13212 if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13214 tmp |= fieldname(insn, 0, 8) << 0; \
13215 tmp |= fieldname(insn, 16, 4) << 9; \
13216 tmp |= fieldname(insn, 23, 1) << 8; \
13217 if (!Check(&S, DecodeAddrMode5Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13218 tmp = fieldname(insn, 28, 4); \
13219 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13223 tmp |= fieldname(insn, 12, 4) << 0; \
13224 tmp |= fieldname(insn, 22, 1) << 4; \
13225 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13227 tmp |= fieldname(insn, 0, 8) << 0; \
13228 tmp |= fieldname(insn, 16, 4) << 9; \
13229 tmp |= fieldname(insn, 23, 1) << 8; \
13230 if (!Check(&S, DecodeAddrMode5Operand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13231 tmp = fieldname(insn, 28, 4); \
13232 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13236 tmp |= fieldname(insn, 12, 4) << 1; \
13237 tmp |= fieldname(insn, 22, 1) << 0; \
13238 if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13240 tmp |= fieldname(insn, 12, 4) << 1; \
13241 tmp |= fieldname(insn, 22, 1) << 0; \
13242 if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13244 tmp |= fieldname(insn, 7, 1) << 0; \
13245 tmp |= fieldname(insn, 16, 4) << 1; \
13246 if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13248 tmp |= fieldname(insn, 0, 4) << 1; \
13249 tmp |= fieldname(insn, 5, 1) << 0; \
13250 if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13251 tmp = fieldname(insn, 28, 4); \
13252 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13256 tmp |= fieldname(insn, 12, 4) << 1; \
13257 tmp |= fieldname(insn, 22, 1) << 0; \
13258 if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13260 tmp |= fieldname(insn, 7, 1) << 0; \
13261 tmp |= fieldname(insn, 16, 4) << 1; \
13262 if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13264 tmp |= fieldname(insn, 0, 4) << 1; \
13265 tmp |= fieldname(insn, 5, 1) << 0; \
13266 if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13267 tmp = fieldname(insn, 28, 4); \
13268 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13272 tmp |= fieldname(insn, 12, 4) << 0; \
13273 tmp |= fieldname(insn, 22, 1) << 4; \
13274 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13276 tmp |= fieldname(insn, 12, 4) << 0; \
13277 tmp |= fieldname(insn, 22, 1) << 4; \
13278 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13280 tmp |= fieldname(insn, 7, 1) << 4; \
13281 tmp |= fieldname(insn, 16, 4) << 0; \
13282 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13284 tmp |= fieldname(insn, 0, 4) << 0; \
13285 tmp |= fieldname(insn, 5, 1) << 4; \
13286 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13287 tmp = fieldname(insn, 28, 4); \
13288 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13292 tmp |= fieldname(insn, 12, 4) << 0; \
13293 tmp |= fieldname(insn, 22, 1) << 4; \
13294 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13296 tmp |= fieldname(insn, 7, 1) << 4; \
13297 tmp |= fieldname(insn, 16, 4) << 0; \
13298 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13300 tmp |= fieldname(insn, 0, 4) << 0; \
13301 tmp |= fieldname(insn, 5, 1) << 4; \
13302 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13303 tmp = fieldname(insn, 28, 4); \
13304 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13308 tmp |= fieldname(insn, 7, 1) << 0; \
13309 tmp |= fieldname(insn, 16, 4) << 1; \
13310 if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13311 tmp = fieldname(insn, 12, 4); \
13312 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13313 tmp = fieldname(insn, 28, 4); \
13314 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13317 if (!Check(&S, DecodeVMOVRRS(MI, insn, Address, Decoder))) return MCDisassembler_Fail; \
13320 tmp = fieldname(insn, 12, 4); \
13321 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13322 tmp = fieldname(insn, 16, 4); \
13323 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13325 tmp |= fieldname(insn, 0, 4) << 0; \
13326 tmp |= fieldname(insn, 5, 1) << 4; \
13327 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13328 tmp = fieldname(insn, 28, 4); \
13329 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13332 tmp = fieldname(insn, 12, 4); \
13333 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13335 tmp |= fieldname(insn, 7, 1) << 0; \
13336 tmp |= fieldname(insn, 16, 4) << 1; \
13337 if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13338 tmp = fieldname(insn, 28, 4); \
13339 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13342 tmp = fieldname(insn, 16, 4); \
13343 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13344 tmp = fieldname(insn, 16, 4); \
13345 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13346 tmp = fieldname(insn, 28, 4); \
13347 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13349 tmp |= fieldname(insn, 0, 8) << 0; \
13350 tmp |= fieldname(insn, 12, 4) << 9; \
13351 tmp |= fieldname(insn, 22, 1) << 8; \
13352 if (!Check(&S, DecodeSPRRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13355 tmp = fieldname(insn, 16, 4); \
13356 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13357 tmp = fieldname(insn, 16, 4); \
13358 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13359 tmp = fieldname(insn, 28, 4); \
13360 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13362 tmp |= fieldname(insn, 1, 7) << 1; \
13363 tmp |= fieldname(insn, 12, 4) << 8; \
13364 tmp |= fieldname(insn, 22, 1) << 12; \
13365 if (!Check(&S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13368 tmp = fieldname(insn, 16, 4); \
13369 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13370 tmp = fieldname(insn, 16, 4); \
13371 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13372 tmp = fieldname(insn, 28, 4); \
13373 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13375 tmp |= fieldname(insn, 1, 7) << 1; \
13376 tmp |= fieldname(insn, 12, 4) << 8; \
13377 if (!Check(&S, DecodeDPRRegListOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13380 tmp = fieldname(insn, 12, 4); \
13381 if (!Check(&S, DecodeGPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13382 tmp = fieldname(insn, 28, 4); \
13383 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13387 tmp |= fieldname(insn, 12, 4) << 1; \
13388 tmp |= fieldname(insn, 22, 1) << 0; \
13389 if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13391 tmp |= fieldname(insn, 0, 4) << 0; \
13392 tmp |= fieldname(insn, 16, 4) << 4; \
13393 MCOperand_CreateImm0(MI, tmp); \
13394 tmp = fieldname(insn, 28, 4); \
13395 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13399 tmp |= fieldname(insn, 12, 4) << 1; \
13400 tmp |= fieldname(insn, 22, 1) << 0; \
13401 if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13403 tmp |= fieldname(insn, 0, 4) << 1; \
13404 tmp |= fieldname(insn, 5, 1) << 0; \
13405 if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13406 tmp = fieldname(insn, 28, 4); \
13407 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13411 tmp |= fieldname(insn, 12, 4) << 1; \
13412 tmp |= fieldname(insn, 22, 1) << 0; \
13413 if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13414 tmp = fieldname(insn, 28, 4); \
13415 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13419 tmp |= fieldname(insn, 12, 4) << 1; \
13420 tmp |= fieldname(insn, 22, 1) << 0; \
13421 if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13423 tmp |= fieldname(insn, 12, 4) << 1; \
13424 tmp |= fieldname(insn, 22, 1) << 0; \
13425 if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13427 tmp |= fieldname(insn, 0, 4) << 1; \
13428 tmp |= fieldname(insn, 5, 1) << 0; \
13429 MCOperand_CreateImm0(MI, tmp); \
13430 tmp = fieldname(insn, 28, 4); \
13431 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13435 tmp |= fieldname(insn, 12, 4) << 0; \
13436 tmp |= fieldname(insn, 22, 1) << 4; \
13437 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13439 tmp |= fieldname(insn, 0, 4) << 1; \
13440 tmp |= fieldname(insn, 5, 1) << 0; \
13441 if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13442 tmp = fieldname(insn, 28, 4); \
13443 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13447 tmp |= fieldname(insn, 12, 4) << 0; \
13448 tmp |= fieldname(insn, 22, 1) << 4; \
13449 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13451 tmp |= fieldname(insn, 0, 4) << 0; \
13452 tmp |= fieldname(insn, 16, 4) << 4; \
13453 MCOperand_CreateImm0(MI, tmp); \
13454 tmp = fieldname(insn, 28, 4); \
13455 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13459 tmp |= fieldname(insn, 12, 4) << 0; \
13460 tmp |= fieldname(insn, 22, 1) << 4; \
13461 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13463 tmp |= fieldname(insn, 0, 4) << 0; \
13464 tmp |= fieldname(insn, 5, 1) << 4; \
13465 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13466 tmp = fieldname(insn, 28, 4); \
13467 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13471 tmp |= fieldname(insn, 12, 4) << 1; \
13472 tmp |= fieldname(insn, 22, 1) << 0; \
13473 if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13475 tmp |= fieldname(insn, 0, 4) << 0; \
13476 tmp |= fieldname(insn, 5, 1) << 4; \
13477 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13478 tmp = fieldname(insn, 28, 4); \
13479 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13483 tmp |= fieldname(insn, 12, 4) << 0; \
13484 tmp |= fieldname(insn, 22, 1) << 4; \
13485 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13486 tmp = fieldname(insn, 28, 4); \
13487 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13491 tmp |= fieldname(insn, 12, 4) << 0; \
13492 tmp |= fieldname(insn, 22, 1) << 4; \
13493 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13495 tmp |= fieldname(insn, 12, 4) << 0; \
13496 tmp |= fieldname(insn, 22, 1) << 4; \
13497 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13499 tmp |= fieldname(insn, 0, 4) << 1; \
13500 tmp |= fieldname(insn, 5, 1) << 0; \
13501 MCOperand_CreateImm0(MI, tmp); \
13502 tmp = fieldname(insn, 28, 4); \
13503 if (!Check(&S, DecodePredicateOperand(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13507 tmp |= fieldname(insn, 12, 4) << 1; \
13508 tmp |= fieldname(insn, 22, 1) << 0; \
13509 if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13511 tmp |= fieldname(insn, 7, 1) << 0; \
13512 tmp |= fieldname(insn, 16, 4) << 1; \
13513 if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13515 tmp |= fieldname(insn, 0, 4) << 1; \
13516 tmp |= fieldname(insn, 5, 1) << 0; \
13517 if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13521 tmp |= fieldname(insn, 12, 4) << 1; \
13522 tmp |= fieldname(insn, 22, 1) << 0; \
13523 if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13525 tmp |= fieldname(insn, 0, 4) << 1; \
13526 tmp |= fieldname(insn, 5, 1) << 0; \
13527 if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13531 tmp |= fieldname(insn, 12, 4) << 1; \
13532 tmp |= fieldname(insn, 22, 1) << 0; \
13533 if (!Check(&S, DecodeSPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13535 tmp |= fieldname(insn, 0, 4) << 0; \
13536 tmp |= fieldname(insn, 5, 1) << 4; \
13537 if (!Check(&S, DecodeDPRRegisterClass(MI, tmp, Address, Decoder))) return MCDisassembler_Fail; \
13542 #define DecodeInstruction(fname, fieldname, decoder, InsnType) \
13543 static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
13544 InsnType insn, uint64_t Address, const MCRegisterInfo *MRI, int feature) \
13546 uint64_t Bits = ARM_getFeatureBits(feature); \
13547 const uint8_t *Ptr = DecodeTable; \
13548 uint32_t CurFieldValue = 0, ExpectedValue; \
13549 DecodeStatus S = MCDisassembler_Success; \
13550 unsigned Start, Len, NumToSkip, PIdx, Opc, DecodeIdx; \
13551 InsnType Val, FieldValue, PositiveMask, NegativeMask; \
13556 return MCDisassembler_Fail; \
13557 case MCD_OPC_ExtractField: { \
13561 CurFieldValue = (uint32_t)fieldname(insn, Start, Len); \
13564 case MCD_OPC_FilterValue: { \
13565 Val = (InsnType)decodeULEB128(++Ptr, &Len); \
13567 NumToSkip = *Ptr++; \
13568 NumToSkip |= (*Ptr++) << 8; \
13569 if (Val != CurFieldValue) \
13570 Ptr += NumToSkip; \
13573 case MCD_OPC_CheckField: { \
13576 FieldValue = fieldname(insn, Start, Len); \
13577 ExpectedValue = (uint32_t)decodeULEB128(++Ptr, &Len); \
13579 NumToSkip = *Ptr++; \
13580 NumToSkip |= (*Ptr++) << 8; \
13581 if (ExpectedValue != FieldValue) \
13582 Ptr += NumToSkip; \
13585 case MCD_OPC_CheckPredicate: { \
13586 PIdx = (uint32_t)decodeULEB128(++Ptr, &Len); \
13588 NumToSkip = *Ptr++; \
13589 NumToSkip |= (*Ptr++) << 8; \
13590 Pred = checkDecoderPredicate(PIdx, Bits); \
13592 Ptr += NumToSkip; \
13596 case MCD_OPC_Decode: { \
13597 Opc = (unsigned)decodeULEB128(++Ptr, &Len); \
13599 DecodeIdx = (unsigned)decodeULEB128(Ptr, &Len); \
13601 MCInst_setOpcode(MI, Opc); \
13602 return decoder(S, DecodeIdx, insn, MI, Address, MRI); \
13604 case MCD_OPC_SoftFail: { \
13605 PositiveMask = (InsnType)decodeULEB128(++Ptr, &Len); \
13607 NegativeMask = (InsnType)decodeULEB128(Ptr, &Len); \
13609 Fail = (insn & PositiveMask) || (~insn & NegativeMask); \
13611 S = MCDisassembler_SoftFail; \
13614 case MCD_OPC_Fail: { \
13615 return MCDisassembler_Fail; \
13621 FieldFromInstruction(fieldFromInstruction_2,
uint16_t)
13622 DecodeToMCInst(decodeToMCInst_2, fieldFromInstruction_2,
uint16_t)
13623 DecodeInstruction(decodeInstruction_2, fieldFromInstruction_2, decodeToMCInst_2,
uint16_t)
13624 FieldFromInstruction(fieldFromInstruction_4,
uint32_t)
13625 DecodeToMCInst(decodeToMCInst_4, fieldFromInstruction_4,
uint32_t)
13626 DecodeInstruction(decodeInstruction_4, fieldFromInstruction_4, decodeToMCInst_4,
uint32_t)